Renesas / Mbed OS SDG_Mouse_Sample

SDG+USBHost(Mouse) Sample

Dependencies:   Sound_Generator USBHost_custom

Fork of SDG_Mouse_Sample by GR-PEACH_producer_meeting

Information

Japanese version is available in lower part of this page.
このページの後半に日本語版が用意されています．

What is this?

This program is a demonstration that sounds the sound by mouse operation by using USBHost(Mouse) and Sound Generator.

Settings

Close JP3 of GR-PEACH.
/media/uploads/RyoheiHagimoto/sdg-mouse.jpg

Operation

operationeffect
Right clickSounds
Left clickReset to base tone (C)
Moves the mouse to the rightLower the sound
Moves the mouse to the leftHigher the sound
Center cursorAdjust the sensitivity.
Reset the reference value in the click.

Others

The default setting of serial communication (baud rate etc.) in mbed is shown the following link.
Please refer to the link and change the settings of your PC terminal software.
The default value of baud rate in mbed is 9600, and this application uses baud rate 9600.
https://developer.mbed.org/teams/Renesas/wiki/GR-PEACH-Getting-Started#install-the-usb-serial-communication


概要

このプログラムは、USBHost(Mouse) + Sound Generatorで、マウス操作による擬似笛デモです。

設定

GR-PEACHのJP3をショートする必要があります。
/media/uploads/RyoheiHagimoto/sdg-mouse.jpg

操作方法

操作内容
右クリック音出力開始
左クリック基準音(ド)にリセット
マウス右移動高音になります
マウス左移動低音になります
センターカーソル音高低の変化量調整(クリックで基準値にリセット)

Others

mbedのシリアル通信(ボーレート等)のデフォルト設定は以下のリンクに示しています。
リンクを参考に、お使いのPCターミナルソフトの設定を変更して下さい。
mbedでのボーレートのデフォルト値は9600で、このサンプルではボーレート9600を使います。
https://developer.mbed.org/teams/Renesas/wiki/GR-PEACH-Getting-Started#install-the-usb-serial-communication

USBHost/USBHALHost_LPC17.cpp@27:4206883f4cb7, 2015-01-19 (annotated)

Committer:
mbed_official
Date:
Mon Jan 19 14:30:37 2015 +0000
Revision:
27:4206883f4cb7
Synchronized with git revision 0ab8d2e6b3d884137dcb5c62d29a07abe132bac7



Full URL: https://github.com/mbedmicro/mbed/commit/0ab8d2e6b3d884137dcb5c62d29a07abe132bac7/



RZ_A1H - Implement some USB functions and fix some bugs about USBHost common codes.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 27:4206883f4cb7 1 /* mbed USBHost Library
mbed_official 27:4206883f4cb7 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 27:4206883f4cb7 3 *
mbed_official 27:4206883f4cb7 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 27:4206883f4cb7 5 * you may not use this file except in compliance with the License.
mbed_official 27:4206883f4cb7 6 * You may obtain a copy of the License at
mbed_official 27:4206883f4cb7 7 *
mbed_official 27:4206883f4cb7 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 27:4206883f4cb7 9 *
mbed_official 27:4206883f4cb7 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 27:4206883f4cb7 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 27:4206883f4cb7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 27:4206883f4cb7 13 * See the License for the specific language governing permissions and
mbed_official 27:4206883f4cb7 14 * limitations under the License.
mbed_official 27:4206883f4cb7 15 */
mbed_official 27:4206883f4cb7 16
mbed_official 27:4206883f4cb7 17 #if defined(TARGET_LPC1768)
mbed_official 27:4206883f4cb7 18
mbed_official 27:4206883f4cb7 19 #include "mbed.h"
mbed_official 27:4206883f4cb7 20 #include "USBHALHost.h"
mbed_official 27:4206883f4cb7 21 #include "dbg.h"
mbed_official 27:4206883f4cb7 22
mbed_official 27:4206883f4cb7 23 // bits of the USB/OTG clock control register
mbed_official 27:4206883f4cb7 24 #define HOST_CLK_EN (1<<0)
mbed_official 27:4206883f4cb7 25 #define DEV_CLK_EN (1<<1)
mbed_official 27:4206883f4cb7 26 #define PORTSEL_CLK_EN (1<<3)
mbed_official 27:4206883f4cb7 27 #define AHB_CLK_EN (1<<4)
mbed_official 27:4206883f4cb7 28
mbed_official 27:4206883f4cb7 29 // bits of the USB/OTG clock status register
mbed_official 27:4206883f4cb7 30 #define HOST_CLK_ON (1<<0)
mbed_official 27:4206883f4cb7 31 #define DEV_CLK_ON (1<<1)
mbed_official 27:4206883f4cb7 32 #define PORTSEL_CLK_ON (1<<3)
mbed_official 27:4206883f4cb7 33 #define AHB_CLK_ON (1<<4)
mbed_official 27:4206883f4cb7 34
mbed_official 27:4206883f4cb7 35 // we need host clock, OTG/portsel clock and AHB clock
mbed_official 27:4206883f4cb7 36 #define CLOCK_MASK (HOST_CLK_EN | PORTSEL_CLK_EN | AHB_CLK_EN)
mbed_official 27:4206883f4cb7 37
mbed_official 27:4206883f4cb7 38 #define HCCA_SIZE sizeof(HCCA)
mbed_official 27:4206883f4cb7 39 #define ED_SIZE sizeof(HCED)
mbed_official 27:4206883f4cb7 40 #define TD_SIZE sizeof(HCTD)
mbed_official 27:4206883f4cb7 41
mbed_official 27:4206883f4cb7 42 #define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
mbed_official 27:4206883f4cb7 43
mbed_official 27:4206883f4cb7 44 static volatile uint8_t usb_buf[TOTAL_SIZE] __attribute((section("AHBSRAM1"),aligned(256))); //256 bytes aligned!
mbed_official 27:4206883f4cb7 45
mbed_official 27:4206883f4cb7 46 USBHALHost * USBHALHost::instHost;
mbed_official 27:4206883f4cb7 47
mbed_official 27:4206883f4cb7 48 USBHALHost::USBHALHost() {
mbed_official 27:4206883f4cb7 49 instHost = this;
mbed_official 27:4206883f4cb7 50 memInit();
mbed_official 27:4206883f4cb7 51 memset((void*)usb_hcca, 0, HCCA_SIZE);
mbed_official 27:4206883f4cb7 52 for (int i = 0; i < MAX_ENDPOINT; i++) {
mbed_official 27:4206883f4cb7 53 edBufAlloc[i] = false;
mbed_official 27:4206883f4cb7 54 }
mbed_official 27:4206883f4cb7 55 for (int i = 0; i < MAX_TD; i++) {
mbed_official 27:4206883f4cb7 56 tdBufAlloc[i] = false;
mbed_official 27:4206883f4cb7 57 }
mbed_official 27:4206883f4cb7 58 }
mbed_official 27:4206883f4cb7 59
mbed_official 27:4206883f4cb7 60 void USBHALHost::init() {
mbed_official 27:4206883f4cb7 61 NVIC_DisableIRQ(USB_IRQn);
mbed_official 27:4206883f4cb7 62
mbed_official 27:4206883f4cb7 63 //Cut power
mbed_official 27:4206883f4cb7 64 LPC_SC->PCONP &= ~(1UL<<31);
mbed_official 27:4206883f4cb7 65 wait_ms(100);
mbed_official 27:4206883f4cb7 66
mbed_official 27:4206883f4cb7 67 // turn on power for USB
mbed_official 27:4206883f4cb7 68 LPC_SC->PCONP |= (1UL<<31);
mbed_official 27:4206883f4cb7 69
mbed_official 27:4206883f4cb7 70 // Enable USB host clock, port selection and AHB clock
mbed_official 27:4206883f4cb7 71 LPC_USB->USBClkCtrl |= CLOCK_MASK;
mbed_official 27:4206883f4cb7 72
mbed_official 27:4206883f4cb7 73 // Wait for clocks to become available
mbed_official 27:4206883f4cb7 74 while ((LPC_USB->USBClkSt & CLOCK_MASK) != CLOCK_MASK);
mbed_official 27:4206883f4cb7 75
mbed_official 27:4206883f4cb7 76 // it seems the bits[0:1] mean the following
mbed_official 27:4206883f4cb7 77 // 0: U1=device, U2=host
mbed_official 27:4206883f4cb7 78 // 1: U1=host, U2=host
mbed_official 27:4206883f4cb7 79 // 2: reserved
mbed_official 27:4206883f4cb7 80 // 3: U1=host, U2=device
mbed_official 27:4206883f4cb7 81 // NB: this register is only available if OTG clock (aka "port select") is enabled!!
mbed_official 27:4206883f4cb7 82 // since we don't care about port 2, set just bit 0 to 1 (U1=host)
mbed_official 27:4206883f4cb7 83 LPC_USB->OTGStCtrl |= 1;
mbed_official 27:4206883f4cb7 84
mbed_official 27:4206883f4cb7 85 // now that we've configured the ports, we can turn off the portsel clock
mbed_official 27:4206883f4cb7 86 LPC_USB->USBClkCtrl &= ~PORTSEL_CLK_EN;
mbed_official 27:4206883f4cb7 87
mbed_official 27:4206883f4cb7 88 // configure USB D+/D- pins
mbed_official 27:4206883f4cb7 89 // P0[29] = USB_D+, 01
mbed_official 27:4206883f4cb7 90 // P0[30] = USB_D-, 01
mbed_official 27:4206883f4cb7 91 LPC_PINCON->PINSEL1 &= ~((3<<26) | (3<<28));
mbed_official 27:4206883f4cb7 92 LPC_PINCON->PINSEL1 |= ((1<<26) | (1<<28));
mbed_official 27:4206883f4cb7 93
mbed_official 27:4206883f4cb7 94 LPC_USB->HcControl = 0; // HARDWARE RESET
mbed_official 27:4206883f4cb7 95 LPC_USB->HcControlHeadED = 0; // Initialize Control list head to Zero
mbed_official 27:4206883f4cb7 96 LPC_USB->HcBulkHeadED = 0; // Initialize Bulk list head to Zero
mbed_official 27:4206883f4cb7 97
mbed_official 27:4206883f4cb7 98 // Wait 100 ms before apply reset
mbed_official 27:4206883f4cb7 99 wait_ms(100);
mbed_official 27:4206883f4cb7 100
mbed_official 27:4206883f4cb7 101 // software reset
mbed_official 27:4206883f4cb7 102 LPC_USB->HcCommandStatus = OR_CMD_STATUS_HCR;
mbed_official 27:4206883f4cb7 103
mbed_official 27:4206883f4cb7 104 // Write Fm Interval and Largest Data Packet Counter
mbed_official 27:4206883f4cb7 105 LPC_USB->HcFmInterval = DEFAULT_FMINTERVAL;
mbed_official 27:4206883f4cb7 106 LPC_USB->HcPeriodicStart = FI * 90 / 100;
mbed_official 27:4206883f4cb7 107
mbed_official 27:4206883f4cb7 108 // Put HC in operational state
mbed_official 27:4206883f4cb7 109 LPC_USB->HcControl = (LPC_USB->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
mbed_official 27:4206883f4cb7 110 // Set Global Power
mbed_official 27:4206883f4cb7 111 LPC_USB->HcRhStatus = OR_RH_STATUS_LPSC;
mbed_official 27:4206883f4cb7 112
mbed_official 27:4206883f4cb7 113 LPC_USB->HcHCCA = (uint32_t)(usb_hcca);
mbed_official 27:4206883f4cb7 114
mbed_official 27:4206883f4cb7 115 // Clear Interrrupt Status
mbed_official 27:4206883f4cb7 116 LPC_USB->HcInterruptStatus |= LPC_USB->HcInterruptStatus;
mbed_official 27:4206883f4cb7 117
mbed_official 27:4206883f4cb7 118 LPC_USB->HcInterruptEnable = OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC;
mbed_official 27:4206883f4cb7 119
mbed_official 27:4206883f4cb7 120 // Enable the USB Interrupt
mbed_official 27:4206883f4cb7 121 NVIC_SetVector(USB_IRQn, (uint32_t)(_usbisr));
mbed_official 27:4206883f4cb7 122 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
mbed_official 27:4206883f4cb7 123 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
mbed_official 27:4206883f4cb7 124
mbed_official 27:4206883f4cb7 125 NVIC_EnableIRQ(USB_IRQn);
mbed_official 27:4206883f4cb7 126
mbed_official 27:4206883f4cb7 127 // Check for any connected devices
mbed_official 27:4206883f4cb7 128 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
mbed_official 27:4206883f4cb7 129 //Device connected
mbed_official 27:4206883f4cb7 130 wait_ms(150);
mbed_official 27:4206883f4cb7 131 USB_DBG("Device connected (%08x)\n\r", LPC_USB->HcRhPortStatus1);
mbed_official 27:4206883f4cb7 132 deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
mbed_official 27:4206883f4cb7 133 }
mbed_official 27:4206883f4cb7 134 }
mbed_official 27:4206883f4cb7 135
mbed_official 27:4206883f4cb7 136 uint32_t USBHALHost::controlHeadED() {
mbed_official 27:4206883f4cb7 137 return LPC_USB->HcControlHeadED;
mbed_official 27:4206883f4cb7 138 }
mbed_official 27:4206883f4cb7 139
mbed_official 27:4206883f4cb7 140 uint32_t USBHALHost::bulkHeadED() {
mbed_official 27:4206883f4cb7 141 return LPC_USB->HcBulkHeadED;
mbed_official 27:4206883f4cb7 142 }
mbed_official 27:4206883f4cb7 143
mbed_official 27:4206883f4cb7 144 uint32_t USBHALHost::interruptHeadED() {
mbed_official 27:4206883f4cb7 145 return usb_hcca->IntTable[0];
mbed_official 27:4206883f4cb7 146 }
mbed_official 27:4206883f4cb7 147
mbed_official 27:4206883f4cb7 148 void USBHALHost::updateBulkHeadED(uint32_t addr) {
mbed_official 27:4206883f4cb7 149 LPC_USB->HcBulkHeadED = addr;
mbed_official 27:4206883f4cb7 150 }
mbed_official 27:4206883f4cb7 151
mbed_official 27:4206883f4cb7 152
mbed_official 27:4206883f4cb7 153 void USBHALHost::updateControlHeadED(uint32_t addr) {
mbed_official 27:4206883f4cb7 154 LPC_USB->HcControlHeadED = addr;
mbed_official 27:4206883f4cb7 155 }
mbed_official 27:4206883f4cb7 156
mbed_official 27:4206883f4cb7 157 void USBHALHost::updateInterruptHeadED(uint32_t addr) {
mbed_official 27:4206883f4cb7 158 usb_hcca->IntTable[0] = addr;
mbed_official 27:4206883f4cb7 159 }
mbed_official 27:4206883f4cb7 160
mbed_official 27:4206883f4cb7 161
mbed_official 27:4206883f4cb7 162 void USBHALHost::enableList(ENDPOINT_TYPE type) {
mbed_official 27:4206883f4cb7 163 switch(type) {
mbed_official 27:4206883f4cb7 164 case CONTROL_ENDPOINT:
mbed_official 27:4206883f4cb7 165 LPC_USB->HcCommandStatus = OR_CMD_STATUS_CLF;
mbed_official 27:4206883f4cb7 166 LPC_USB->HcControl |= OR_CONTROL_CLE;
mbed_official 27:4206883f4cb7 167 break;
mbed_official 27:4206883f4cb7 168 case ISOCHRONOUS_ENDPOINT:
mbed_official 27:4206883f4cb7 169 break;
mbed_official 27:4206883f4cb7 170 case BULK_ENDPOINT:
mbed_official 27:4206883f4cb7 171 LPC_USB->HcCommandStatus = OR_CMD_STATUS_BLF;
mbed_official 27:4206883f4cb7 172 LPC_USB->HcControl |= OR_CONTROL_BLE;
mbed_official 27:4206883f4cb7 173 break;
mbed_official 27:4206883f4cb7 174 case INTERRUPT_ENDPOINT:
mbed_official 27:4206883f4cb7 175 LPC_USB->HcControl |= OR_CONTROL_PLE;
mbed_official 27:4206883f4cb7 176 break;
mbed_official 27:4206883f4cb7 177 }
mbed_official 27:4206883f4cb7 178 }
mbed_official 27:4206883f4cb7 179
mbed_official 27:4206883f4cb7 180
mbed_official 27:4206883f4cb7 181 bool USBHALHost::disableList(ENDPOINT_TYPE type) {
mbed_official 27:4206883f4cb7 182 switch(type) {
mbed_official 27:4206883f4cb7 183 case CONTROL_ENDPOINT:
mbed_official 27:4206883f4cb7 184 if(LPC_USB->HcControl & OR_CONTROL_CLE) {
mbed_official 27:4206883f4cb7 185 LPC_USB->HcControl &= ~OR_CONTROL_CLE;
mbed_official 27:4206883f4cb7 186 return true;
mbed_official 27:4206883f4cb7 187 }
mbed_official 27:4206883f4cb7 188 return false;
mbed_official 27:4206883f4cb7 189 case ISOCHRONOUS_ENDPOINT:
mbed_official 27:4206883f4cb7 190 return false;
mbed_official 27:4206883f4cb7 191 case BULK_ENDPOINT:
mbed_official 27:4206883f4cb7 192 if(LPC_USB->HcControl & OR_CONTROL_BLE){
mbed_official 27:4206883f4cb7 193 LPC_USB->HcControl &= ~OR_CONTROL_BLE;
mbed_official 27:4206883f4cb7 194 return true;
mbed_official 27:4206883f4cb7 195 }
mbed_official 27:4206883f4cb7 196 return false;
mbed_official 27:4206883f4cb7 197 case INTERRUPT_ENDPOINT:
mbed_official 27:4206883f4cb7 198 if(LPC_USB->HcControl & OR_CONTROL_PLE) {
mbed_official 27:4206883f4cb7 199 LPC_USB->HcControl &= ~OR_CONTROL_PLE;
mbed_official 27:4206883f4cb7 200 return true;
mbed_official 27:4206883f4cb7 201 }
mbed_official 27:4206883f4cb7 202 return false;
mbed_official 27:4206883f4cb7 203 }
mbed_official 27:4206883f4cb7 204 return false;
mbed_official 27:4206883f4cb7 205 }
mbed_official 27:4206883f4cb7 206
mbed_official 27:4206883f4cb7 207
mbed_official 27:4206883f4cb7 208 void USBHALHost::memInit() {
mbed_official 27:4206883f4cb7 209 usb_hcca = (volatile HCCA *)usb_buf;
mbed_official 27:4206883f4cb7 210 usb_edBuf = usb_buf + HCCA_SIZE;
mbed_official 27:4206883f4cb7 211 usb_tdBuf = usb_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE);
mbed_official 27:4206883f4cb7 212 }
mbed_official 27:4206883f4cb7 213
mbed_official 27:4206883f4cb7 214 volatile uint8_t * USBHALHost::getED() {
mbed_official 27:4206883f4cb7 215 for (int i = 0; i < MAX_ENDPOINT; i++) {
mbed_official 27:4206883f4cb7 216 if ( !edBufAlloc[i] ) {
mbed_official 27:4206883f4cb7 217 edBufAlloc[i] = true;
mbed_official 27:4206883f4cb7 218 return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
mbed_official 27:4206883f4cb7 219 }
mbed_official 27:4206883f4cb7 220 }
mbed_official 27:4206883f4cb7 221 perror("Could not allocate ED\r\n");
mbed_official 27:4206883f4cb7 222 return NULL; //Could not alloc ED
mbed_official 27:4206883f4cb7 223 }
mbed_official 27:4206883f4cb7 224
mbed_official 27:4206883f4cb7 225 volatile uint8_t * USBHALHost::getTD() {
mbed_official 27:4206883f4cb7 226 int i;
mbed_official 27:4206883f4cb7 227 for (i = 0; i < MAX_TD; i++) {
mbed_official 27:4206883f4cb7 228 if ( !tdBufAlloc[i] ) {
mbed_official 27:4206883f4cb7 229 tdBufAlloc[i] = true;
mbed_official 27:4206883f4cb7 230 return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
mbed_official 27:4206883f4cb7 231 }
mbed_official 27:4206883f4cb7 232 }
mbed_official 27:4206883f4cb7 233 perror("Could not allocate TD\r\n");
mbed_official 27:4206883f4cb7 234 return NULL; //Could not alloc TD
mbed_official 27:4206883f4cb7 235 }
mbed_official 27:4206883f4cb7 236
mbed_official 27:4206883f4cb7 237
mbed_official 27:4206883f4cb7 238 void USBHALHost::freeED(volatile uint8_t * ed) {
mbed_official 27:4206883f4cb7 239 int i;
mbed_official 27:4206883f4cb7 240 i = (ed - usb_edBuf) / ED_SIZE;
mbed_official 27:4206883f4cb7 241 edBufAlloc[i] = false;
mbed_official 27:4206883f4cb7 242 }
mbed_official 27:4206883f4cb7 243
mbed_official 27:4206883f4cb7 244 void USBHALHost::freeTD(volatile uint8_t * td) {
mbed_official 27:4206883f4cb7 245 int i;
mbed_official 27:4206883f4cb7 246 i = (td - usb_tdBuf) / TD_SIZE;
mbed_official 27:4206883f4cb7 247 tdBufAlloc[i] = false;
mbed_official 27:4206883f4cb7 248 }
mbed_official 27:4206883f4cb7 249
mbed_official 27:4206883f4cb7 250
mbed_official 27:4206883f4cb7 251 void USBHALHost::resetRootHub() {
mbed_official 27:4206883f4cb7 252 // Initiate port reset
mbed_official 27:4206883f4cb7 253 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRS;
mbed_official 27:4206883f4cb7 254
mbed_official 27:4206883f4cb7 255 while (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRS);
mbed_official 27:4206883f4cb7 256
mbed_official 27:4206883f4cb7 257 // ...and clear port reset signal
mbed_official 27:4206883f4cb7 258 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
mbed_official 27:4206883f4cb7 259 }
mbed_official 27:4206883f4cb7 260
mbed_official 27:4206883f4cb7 261
mbed_official 27:4206883f4cb7 262 void USBHALHost::_usbisr(void) {
mbed_official 27:4206883f4cb7 263 if (instHost) {
mbed_official 27:4206883f4cb7 264 instHost->UsbIrqhandler();
mbed_official 27:4206883f4cb7 265 }
mbed_official 27:4206883f4cb7 266 }
mbed_official 27:4206883f4cb7 267
mbed_official 27:4206883f4cb7 268 void USBHALHost::UsbIrqhandler() {
mbed_official 27:4206883f4cb7 269 if( LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable ) //Is there something to actually process?
mbed_official 27:4206883f4cb7 270 {
mbed_official 27:4206883f4cb7 271
mbed_official 27:4206883f4cb7 272 uint32_t int_status = LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable;
mbed_official 27:4206883f4cb7 273
mbed_official 27:4206883f4cb7 274 // Root hub status change interrupt
mbed_official 27:4206883f4cb7 275 if (int_status & OR_INTR_STATUS_RHSC) {
mbed_official 27:4206883f4cb7 276 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CSC) {
mbed_official 27:4206883f4cb7 277 if (LPC_USB->HcRhStatus & OR_RH_STATUS_DRWE) {
mbed_official 27:4206883f4cb7 278 // When DRWE is on, Connect Status Change
mbed_official 27:4206883f4cb7 279 // means a remote wakeup event.
mbed_official 27:4206883f4cb7 280 } else {
mbed_official 27:4206883f4cb7 281
mbed_official 27:4206883f4cb7 282 //Root device connected
mbed_official 27:4206883f4cb7 283 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
mbed_official 27:4206883f4cb7 284
mbed_official 27:4206883f4cb7 285 // wait 150ms to avoid bounce
mbed_official 27:4206883f4cb7 286 wait_ms(150);
mbed_official 27:4206883f4cb7 287
mbed_official 27:4206883f4cb7 288 //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
mbed_official 27:4206883f4cb7 289 deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
mbed_official 27:4206883f4cb7 290 }
mbed_official 27:4206883f4cb7 291
mbed_official 27:4206883f4cb7 292 //Root device disconnected
mbed_official 27:4206883f4cb7 293 else {
mbed_official 27:4206883f4cb7 294
mbed_official 27:4206883f4cb7 295 if (!(int_status & OR_INTR_STATUS_WDH)) {
mbed_official 27:4206883f4cb7 296 usb_hcca->DoneHead = 0;
mbed_official 27:4206883f4cb7 297 }
mbed_official 27:4206883f4cb7 298
mbed_official 27:4206883f4cb7 299 // wait 200ms to avoid bounce
mbed_official 27:4206883f4cb7 300 wait_ms(200);
mbed_official 27:4206883f4cb7 301
mbed_official 27:4206883f4cb7 302 deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
mbed_official 27:4206883f4cb7 303
mbed_official 27:4206883f4cb7 304 if (int_status & OR_INTR_STATUS_WDH) {
mbed_official 27:4206883f4cb7 305 usb_hcca->DoneHead = 0;
mbed_official 27:4206883f4cb7 306 LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;
mbed_official 27:4206883f4cb7 307 }
mbed_official 27:4206883f4cb7 308 }
mbed_official 27:4206883f4cb7 309 }
mbed_official 27:4206883f4cb7 310 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
mbed_official 27:4206883f4cb7 311 }
mbed_official 27:4206883f4cb7 312 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRSC) {
mbed_official 27:4206883f4cb7 313 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
mbed_official 27:4206883f4cb7 314 }
mbed_official 27:4206883f4cb7 315 LPC_USB->HcInterruptStatus = OR_INTR_STATUS_RHSC;
mbed_official 27:4206883f4cb7 316 }
mbed_official 27:4206883f4cb7 317
mbed_official 27:4206883f4cb7 318 // Writeback Done Head interrupt
mbed_official 27:4206883f4cb7 319 if (int_status & OR_INTR_STATUS_WDH) {
mbed_official 27:4206883f4cb7 320 transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
mbed_official 27:4206883f4cb7 321 LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;
mbed_official 27:4206883f4cb7 322 }
mbed_official 27:4206883f4cb7 323 }
mbed_official 27:4206883f4cb7 324 }
mbed_official 27:4206883f4cb7 325 #endif