Renesas / Mbed OS SDG_Mouse_Sample

SDG+USBHost(Mouse) Sample

Dependencies:   Sound_Generator USBHost_custom

Fork of SDG_Mouse_Sample by GR-PEACH_producer_meeting

Information

Japanese version is available in lower part of this page.
このページの後半に日本語版が用意されています．

What is this?

This program is a demonstration that sounds the sound by mouse operation by using USBHost(Mouse) and Sound Generator.

Settings

Close JP3 of GR-PEACH.
/media/uploads/RyoheiHagimoto/sdg-mouse.jpg

Operation

operationeffect
Right clickSounds
Left clickReset to base tone (C)
Moves the mouse to the rightLower the sound
Moves the mouse to the leftHigher the sound
Center cursorAdjust the sensitivity.
Reset the reference value in the click.

Others

The default setting of serial communication (baud rate etc.) in mbed is shown the following link.
Please refer to the link and change the settings of your PC terminal software.
The default value of baud rate in mbed is 9600, and this application uses baud rate 9600.
https://developer.mbed.org/teams/Renesas/wiki/GR-PEACH-Getting-Started#install-the-usb-serial-communication


概要

このプログラムは、USBHost(Mouse) + Sound Generatorで、マウス操作による擬似笛デモです。

設定

GR-PEACHのJP3をショートする必要があります。
/media/uploads/RyoheiHagimoto/sdg-mouse.jpg

操作方法

操作内容
右クリック音出力開始
左クリック基準音(ド)にリセット
マウス右移動高音になります
マウス左移動低音になります
センターカーソル音高低の変化量調整(クリックで基準値にリセット)

Others

mbedのシリアル通信(ボーレート等)のデフォルト設定は以下のリンクに示しています。
リンクを参考に、お使いのPCターミナルソフトの設定を変更して下さい。
mbedでのボーレートのデフォルト値は9600で、このサンプルではボーレート9600を使います。
https://developer.mbed.org/teams/Renesas/wiki/GR-PEACH-Getting-Started#install-the-usb-serial-communication

USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_dmacdrv.c@27:4206883f4cb7, 2015-01-19 (annotated)

Committer:
mbed_official
Date:
Mon Jan 19 14:30:37 2015 +0000
Revision:
27:4206883f4cb7
Synchronized with git revision 0ab8d2e6b3d884137dcb5c62d29a07abe132bac7



Full URL: https://github.com/mbedmicro/mbed/commit/0ab8d2e6b3d884137dcb5c62d29a07abe132bac7/



RZ_A1H - Implement some USB functions and fix some bugs about USBHost common codes.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 27:4206883f4cb7 1 /*******************************************************************************
mbed_official 27:4206883f4cb7 2 * DISCLAIMER
mbed_official 27:4206883f4cb7 3 * This software is supplied by Renesas Electronics Corporation and is only
mbed_official 27:4206883f4cb7 4 * intended for use with Renesas products. No other uses are authorized. This
mbed_official 27:4206883f4cb7 5 * software is owned by Renesas Electronics Corporation and is protected under
mbed_official 27:4206883f4cb7 6 * all applicable laws, including copyright laws.
mbed_official 27:4206883f4cb7 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
mbed_official 27:4206883f4cb7 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
mbed_official 27:4206883f4cb7 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
mbed_official 27:4206883f4cb7 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
mbed_official 27:4206883f4cb7 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
mbed_official 27:4206883f4cb7 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
mbed_official 27:4206883f4cb7 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
mbed_official 27:4206883f4cb7 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
mbed_official 27:4206883f4cb7 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
mbed_official 27:4206883f4cb7 16 * Renesas reserves the right, without notice, to make changes to this software
mbed_official 27:4206883f4cb7 17 * and to discontinue the availability of this software. By using this software,
mbed_official 27:4206883f4cb7 18 * you agree to the additional terms and conditions found by accessing the
mbed_official 27:4206883f4cb7 19 * following link:
mbed_official 27:4206883f4cb7 20 * http://www.renesas.com/disclaimer
mbed_official 27:4206883f4cb7 21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
mbed_official 27:4206883f4cb7 22 *******************************************************************************/
mbed_official 27:4206883f4cb7 23 /*******************************************************************************
mbed_official 27:4206883f4cb7 24 * File Name : usb0_host_dmacdrv.c
mbed_official 27:4206883f4cb7 25 * $Rev: 1116 $
mbed_official 27:4206883f4cb7 26 * $Date:: 2014-07-09 16:29:19 +0900#$
mbed_official 27:4206883f4cb7 27 * Device(s) : RZ/A1H
mbed_official 27:4206883f4cb7 28 * Tool-Chain :
mbed_official 27:4206883f4cb7 29 * OS : None
mbed_official 27:4206883f4cb7 30 * H/W Platform :
mbed_official 27:4206883f4cb7 31 * Description : RZ/A1H R7S72100 USB Sample Program
mbed_official 27:4206883f4cb7 32 * Operation :
mbed_official 27:4206883f4cb7 33 * Limitations :
mbed_official 27:4206883f4cb7 34 *******************************************************************************/
mbed_official 27:4206883f4cb7 35
mbed_official 27:4206883f4cb7 36
mbed_official 27:4206883f4cb7 37 /*******************************************************************************
mbed_official 27:4206883f4cb7 38 Includes <System Includes> , "Project Includes"
mbed_official 27:4206883f4cb7 39 *******************************************************************************/
mbed_official 27:4206883f4cb7 40 #include "r_typedefs.h"
mbed_official 27:4206883f4cb7 41 #include "iodefine.h"
mbed_official 27:4206883f4cb7 42 #include "rza_io_regrw.h"
mbed_official 27:4206883f4cb7 43 #include "usb0_host_dmacdrv.h"
mbed_official 27:4206883f4cb7 44
mbed_official 27:4206883f4cb7 45
mbed_official 27:4206883f4cb7 46 /*******************************************************************************
mbed_official 27:4206883f4cb7 47 Typedef definitions
mbed_official 27:4206883f4cb7 48 *******************************************************************************/
mbed_official 27:4206883f4cb7 49
mbed_official 27:4206883f4cb7 50
mbed_official 27:4206883f4cb7 51 /*******************************************************************************
mbed_official 27:4206883f4cb7 52 Macro definitions
mbed_official 27:4206883f4cb7 53 *******************************************************************************/
mbed_official 27:4206883f4cb7 54 #define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */
mbed_official 27:4206883f4cb7 55
mbed_official 27:4206883f4cb7 56 /* ==== Request setting information for on-chip peripheral module ==== */
mbed_official 27:4206883f4cb7 57 typedef enum dmac_peri_req_reg_type
mbed_official 27:4206883f4cb7 58 {
mbed_official 27:4206883f4cb7 59 DMAC_REQ_MID,
mbed_official 27:4206883f4cb7 60 DMAC_REQ_RID,
mbed_official 27:4206883f4cb7 61 DMAC_REQ_AM,
mbed_official 27:4206883f4cb7 62 DMAC_REQ_LVL,
mbed_official 27:4206883f4cb7 63 DMAC_REQ_REQD
mbed_official 27:4206883f4cb7 64 } dmac_peri_req_reg_type_t;
mbed_official 27:4206883f4cb7 65
mbed_official 27:4206883f4cb7 66
mbed_official 27:4206883f4cb7 67 /*******************************************************************************
mbed_official 27:4206883f4cb7 68 Imported global variables and functions (from other files)
mbed_official 27:4206883f4cb7 69 *******************************************************************************/
mbed_official 27:4206883f4cb7 70
mbed_official 27:4206883f4cb7 71
mbed_official 27:4206883f4cb7 72 /*******************************************************************************
mbed_official 27:4206883f4cb7 73 Exported global variables and functions (to be accessed by other files)
mbed_official 27:4206883f4cb7 74 *******************************************************************************/
mbed_official 27:4206883f4cb7 75
mbed_official 27:4206883f4cb7 76
mbed_official 27:4206883f4cb7 77 /*******************************************************************************
mbed_official 27:4206883f4cb7 78 Private global variables and functions
mbed_official 27:4206883f4cb7 79 *******************************************************************************/
mbed_official 27:4206883f4cb7 80 /* ==== Prototype declaration ==== */
mbed_official 27:4206883f4cb7 81
mbed_official 27:4206883f4cb7 82 /* ==== Global variable ==== */
mbed_official 27:4206883f4cb7 83 /* On-chip peripheral module request setting table */
mbed_official 27:4206883f4cb7 84 static const uint8_t usb0_host_dmac_peri_req_init_table[8][5] =
mbed_official 27:4206883f4cb7 85 {
mbed_official 27:4206883f4cb7 86 /* MID,RID, AM,LVL,REQD */
mbed_official 27:4206883f4cb7 87 { 32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */
mbed_official 27:4206883f4cb7 88 { 32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */
mbed_official 27:4206883f4cb7 89 { 33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */
mbed_official 27:4206883f4cb7 90 { 33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */
mbed_official 27:4206883f4cb7 91 { 34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */
mbed_official 27:4206883f4cb7 92 { 34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */
mbed_official 27:4206883f4cb7 93 { 35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */
mbed_official 27:4206883f4cb7 94 { 35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */
mbed_official 27:4206883f4cb7 95 };
mbed_official 27:4206883f4cb7 96
mbed_official 27:4206883f4cb7 97
mbed_official 27:4206883f4cb7 98 /*******************************************************************************
mbed_official 27:4206883f4cb7 99 * Function Name: usb0_host_DMAC1_PeriReqInit
mbed_official 27:4206883f4cb7 100 * Description : Sets the register mode for DMA mode and the on-chip peripheral
mbed_official 27:4206883f4cb7 101 * : module request for transfer request for DMAC channel 1.
mbed_official 27:4206883f4cb7 102 * : Executes DMAC initial setting using the DMA information
mbed_official 27:4206883f4cb7 103 * : specified by the argument *trans_info and the enabled/disabled
mbed_official 27:4206883f4cb7 104 * : continuous transfer specified by the argument continuation.
mbed_official 27:4206883f4cb7 105 * : Registers DMAC channel 1 interrupt handler function and sets
mbed_official 27:4206883f4cb7 106 * : the interrupt priority level. Then enables transfer completion
mbed_official 27:4206883f4cb7 107 * : interrupt.
mbed_official 27:4206883f4cb7 108 * Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
mbed_official 27:4206883f4cb7 109 * : : register
mbed_official 27:4206883f4cb7 110 * : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
mbed_official 27:4206883f4cb7 111 * : uint32_t continuation : Set continuous transfer to be valid
mbed_official 27:4206883f4cb7 112 * : : after DMA transfer has been completed
mbed_official 27:4206883f4cb7 113 * : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
mbed_official 27:4206883f4cb7 114 * : DMAC_SAMPLE_SINGLE : Do not execute continuous
mbed_official 27:4206883f4cb7 115 * : : transfer
mbed_official 27:4206883f4cb7 116 * : uint32_t request_factor : Factor for on-chip peripheral module
mbed_official 27:4206883f4cb7 117 * : : request
mbed_official 27:4206883f4cb7 118 * : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
mbed_official 27:4206883f4cb7 119 * : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
mbed_official 27:4206883f4cb7 120 * : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
mbed_official 27:4206883f4cb7 121 * : :
mbed_official 27:4206883f4cb7 122 * : uint32_t req_direction : Setting value of CHCFG_n register
mbed_official 27:4206883f4cb7 123 * : : REQD bit
mbed_official 27:4206883f4cb7 124 * Return Value : none
mbed_official 27:4206883f4cb7 125 *******************************************************************************/
mbed_official 27:4206883f4cb7 126 void usb0_host_DMAC1_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
mbed_official 27:4206883f4cb7 127 uint32_t request_factor, uint32_t req_direction)
mbed_official 27:4206883f4cb7 128 {
mbed_official 27:4206883f4cb7 129 /* ==== Register mode ==== */
mbed_official 27:4206883f4cb7 130 if (DMAC_MODE_REGISTER == dmamode)
mbed_official 27:4206883f4cb7 131 {
mbed_official 27:4206883f4cb7 132 /* ==== Next0 register set ==== */
mbed_official 27:4206883f4cb7 133 DMAC1.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
mbed_official 27:4206883f4cb7 134 DMAC1.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
mbed_official 27:4206883f4cb7 135 DMAC1.N0TB_n = trans_info->count; /* Total transfer byte count */
mbed_official 27:4206883f4cb7 136
mbed_official 27:4206883f4cb7 137 /* DAD : Transfer destination address counting direction */
mbed_official 27:4206883f4cb7 138 /* SAD : Transfer source address counting direction */
mbed_official 27:4206883f4cb7 139 /* DDS : Transfer destination transfer size */
mbed_official 27:4206883f4cb7 140 /* SDS : Transfer source transfer size */
mbed_official 27:4206883f4cb7 141 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 27:4206883f4cb7 142 trans_info->daddr_dir,
mbed_official 27:4206883f4cb7 143 DMAC1_CHCFG_n_DAD_SHIFT,
mbed_official 27:4206883f4cb7 144 DMAC1_CHCFG_n_DAD);
mbed_official 27:4206883f4cb7 145 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 27:4206883f4cb7 146 trans_info->saddr_dir,
mbed_official 27:4206883f4cb7 147 DMAC1_CHCFG_n_SAD_SHIFT,
mbed_official 27:4206883f4cb7 148 DMAC1_CHCFG_n_SAD);
mbed_official 27:4206883f4cb7 149 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 27:4206883f4cb7 150 trans_info->dst_size,
mbed_official 27:4206883f4cb7 151 DMAC1_CHCFG_n_DDS_SHIFT,
mbed_official 27:4206883f4cb7 152 DMAC1_CHCFG_n_DDS);
mbed_official 27:4206883f4cb7 153 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 27:4206883f4cb7 154 trans_info->src_size,
mbed_official 27:4206883f4cb7 155 DMAC1_CHCFG_n_SDS_SHIFT,
mbed_official 27:4206883f4cb7 156 DMAC1_CHCFG_n_SDS);
mbed_official 27:4206883f4cb7 157
mbed_official 27:4206883f4cb7 158 /* DMS : Register mode */
mbed_official 27:4206883f4cb7 159 /* RSEL : Select Next0 register set */
mbed_official 27:4206883f4cb7 160 /* SBE : No discharge of buffer data when aborted */
mbed_official 27:4206883f4cb7 161 /* DEM : No DMA interrupt mask */
mbed_official 27:4206883f4cb7 162 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 27:4206883f4cb7 163 0,
mbed_official 27:4206883f4cb7 164 DMAC1_CHCFG_n_DMS_SHIFT,
mbed_official 27:4206883f4cb7 165 DMAC1_CHCFG_n_DMS);
mbed_official 27:4206883f4cb7 166 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 27:4206883f4cb7 167 0,
mbed_official 27:4206883f4cb7 168 DMAC1_CHCFG_n_RSEL_SHIFT,
mbed_official 27:4206883f4cb7 169 DMAC1_CHCFG_n_RSEL);
mbed_official 27:4206883f4cb7 170 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 27:4206883f4cb7 171 0,
mbed_official 27:4206883f4cb7 172 DMAC1_CHCFG_n_SBE_SHIFT,
mbed_official 27:4206883f4cb7 173 DMAC1_CHCFG_n_SBE);
mbed_official 27:4206883f4cb7 174 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 27:4206883f4cb7 175 0,
mbed_official 27:4206883f4cb7 176 DMAC1_CHCFG_n_DEM_SHIFT,
mbed_official 27:4206883f4cb7 177 DMAC1_CHCFG_n_DEM);
mbed_official 27:4206883f4cb7 178
mbed_official 27:4206883f4cb7 179 /* ---- Continuous transfer ---- */
mbed_official 27:4206883f4cb7 180 if (DMAC_SAMPLE_CONTINUATION == continuation)
mbed_official 27:4206883f4cb7 181 {
mbed_official 27:4206883f4cb7 182 /* REN : Execute continuous transfer */
mbed_official 27:4206883f4cb7 183 /* RSW : Change register set when DMA transfer is completed. */
mbed_official 27:4206883f4cb7 184 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 27:4206883f4cb7 185 1,
mbed_official 27:4206883f4cb7 186 DMAC1_CHCFG_n_REN_SHIFT,
mbed_official 27:4206883f4cb7 187 DMAC1_CHCFG_n_REN);
mbed_official 27:4206883f4cb7 188 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 27:4206883f4cb7 189 1,
mbed_official 27:4206883f4cb7 190 DMAC1_CHCFG_n_RSW_SHIFT,
mbed_official 27:4206883f4cb7 191 DMAC1_CHCFG_n_RSW);
mbed_official 27:4206883f4cb7 192 }
mbed_official 27:4206883f4cb7 193 /* ---- Single transfer ---- */
mbed_official 27:4206883f4cb7 194 else
mbed_official 27:4206883f4cb7 195 {
mbed_official 27:4206883f4cb7 196 /* REN : Do not execute continuous transfer */
mbed_official 27:4206883f4cb7 197 /* RSW : Do not change register set when DMA transfer is completed. */
mbed_official 27:4206883f4cb7 198 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 27:4206883f4cb7 199 0,
mbed_official 27:4206883f4cb7 200 DMAC1_CHCFG_n_REN_SHIFT,
mbed_official 27:4206883f4cb7 201 DMAC1_CHCFG_n_REN);
mbed_official 27:4206883f4cb7 202 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 27:4206883f4cb7 203 0,
mbed_official 27:4206883f4cb7 204 DMAC1_CHCFG_n_RSW_SHIFT,
mbed_official 27:4206883f4cb7 205 DMAC1_CHCFG_n_RSW);
mbed_official 27:4206883f4cb7 206 }
mbed_official 27:4206883f4cb7 207
mbed_official 27:4206883f4cb7 208 /* TM : Single transfer */
mbed_official 27:4206883f4cb7 209 /* SEL : Channel setting */
mbed_official 27:4206883f4cb7 210 /* HIEN, LOEN : On-chip peripheral module request */
mbed_official 27:4206883f4cb7 211 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 27:4206883f4cb7 212 0,
mbed_official 27:4206883f4cb7 213 DMAC1_CHCFG_n_TM_SHIFT,
mbed_official 27:4206883f4cb7 214 DMAC1_CHCFG_n_TM);
mbed_official 27:4206883f4cb7 215 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 27:4206883f4cb7 216 1,
mbed_official 27:4206883f4cb7 217 DMAC1_CHCFG_n_SEL_SHIFT,
mbed_official 27:4206883f4cb7 218 DMAC1_CHCFG_n_SEL);
mbed_official 27:4206883f4cb7 219 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 27:4206883f4cb7 220 1,
mbed_official 27:4206883f4cb7 221 DMAC1_CHCFG_n_HIEN_SHIFT,
mbed_official 27:4206883f4cb7 222 DMAC1_CHCFG_n_HIEN);
mbed_official 27:4206883f4cb7 223 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 27:4206883f4cb7 224 0,
mbed_official 27:4206883f4cb7 225 DMAC1_CHCFG_n_LOEN_SHIFT,
mbed_official 27:4206883f4cb7 226 DMAC1_CHCFG_n_LOEN);
mbed_official 27:4206883f4cb7 227
mbed_official 27:4206883f4cb7 228 /* ---- Set factor by specified on-chip peripheral module request ---- */
mbed_official 27:4206883f4cb7 229 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 27:4206883f4cb7 230 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
mbed_official 27:4206883f4cb7 231 DMAC1_CHCFG_n_AM_SHIFT,
mbed_official 27:4206883f4cb7 232 DMAC1_CHCFG_n_AM);
mbed_official 27:4206883f4cb7 233 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 27:4206883f4cb7 234 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
mbed_official 27:4206883f4cb7 235 DMAC1_CHCFG_n_LVL_SHIFT,
mbed_official 27:4206883f4cb7 236 DMAC1_CHCFG_n_LVL);
mbed_official 27:4206883f4cb7 237 if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
mbed_official 27:4206883f4cb7 238 {
mbed_official 27:4206883f4cb7 239 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 27:4206883f4cb7 240 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
mbed_official 27:4206883f4cb7 241 DMAC1_CHCFG_n_REQD_SHIFT,
mbed_official 27:4206883f4cb7 242 DMAC1_CHCFG_n_REQD);
mbed_official 27:4206883f4cb7 243 }
mbed_official 27:4206883f4cb7 244 else
mbed_official 27:4206883f4cb7 245 {
mbed_official 27:4206883f4cb7 246 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 27:4206883f4cb7 247 req_direction,
mbed_official 27:4206883f4cb7 248 DMAC1_CHCFG_n_REQD_SHIFT,
mbed_official 27:4206883f4cb7 249 DMAC1_CHCFG_n_REQD);
mbed_official 27:4206883f4cb7 250 }
mbed_official 27:4206883f4cb7 251 RZA_IO_RegWrite_32(&DMAC01.DMARS,
mbed_official 27:4206883f4cb7 252 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
mbed_official 27:4206883f4cb7 253 DMAC01_DMARS_CH1_RID_SHIFT,
mbed_official 27:4206883f4cb7 254 DMAC01_DMARS_CH1_RID);
mbed_official 27:4206883f4cb7 255 RZA_IO_RegWrite_32(&DMAC01.DMARS,
mbed_official 27:4206883f4cb7 256 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
mbed_official 27:4206883f4cb7 257 DMAC01_DMARS_CH1_MID_SHIFT,
mbed_official 27:4206883f4cb7 258 DMAC01_DMARS_CH1_MID);
mbed_official 27:4206883f4cb7 259
mbed_official 27:4206883f4cb7 260 /* PR : Round robin mode */
mbed_official 27:4206883f4cb7 261 RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
mbed_official 27:4206883f4cb7 262 1,
mbed_official 27:4206883f4cb7 263 DMAC07_DCTRL_0_7_PR_SHIFT,
mbed_official 27:4206883f4cb7 264 DMAC07_DCTRL_0_7_PR);
mbed_official 27:4206883f4cb7 265 }
mbed_official 27:4206883f4cb7 266 }
mbed_official 27:4206883f4cb7 267
mbed_official 27:4206883f4cb7 268 /*******************************************************************************
mbed_official 27:4206883f4cb7 269 * Function Name: usb0_host_DMAC1_Open
mbed_official 27:4206883f4cb7 270 * Description : Enables DMAC channel 1 transfer.
mbed_official 27:4206883f4cb7 271 * Arguments : uint32_t req : DMAC request mode
mbed_official 27:4206883f4cb7 272 * Return Value : 0 : Succeeded in enabling DMA transfer
mbed_official 27:4206883f4cb7 273 * : -1 : Failed to enable DMA transfer (due to DMA operation)
mbed_official 27:4206883f4cb7 274 *******************************************************************************/
mbed_official 27:4206883f4cb7 275 int32_t usb0_host_DMAC1_Open (uint32_t req)
mbed_official 27:4206883f4cb7 276 {
mbed_official 27:4206883f4cb7 277 int32_t ret;
mbed_official 27:4206883f4cb7 278 volatile uint8_t dummy;
mbed_official 27:4206883f4cb7 279
mbed_official 27:4206883f4cb7 280 /* Transferable? */
mbed_official 27:4206883f4cb7 281 if ((0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
mbed_official 27:4206883f4cb7 282 DMAC1_CHSTAT_n_EN_SHIFT,
mbed_official 27:4206883f4cb7 283 DMAC1_CHSTAT_n_EN)) &&
mbed_official 27:4206883f4cb7 284 (0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
mbed_official 27:4206883f4cb7 285 DMAC1_CHSTAT_n_TACT_SHIFT,
mbed_official 27:4206883f4cb7 286 DMAC1_CHSTAT_n_TACT)))
mbed_official 27:4206883f4cb7 287 {
mbed_official 27:4206883f4cb7 288 /* Clear Channel Status Register */
mbed_official 27:4206883f4cb7 289 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
mbed_official 27:4206883f4cb7 290 1,
mbed_official 27:4206883f4cb7 291 DMAC1_CHCTRL_n_SWRST_SHIFT,
mbed_official 27:4206883f4cb7 292 DMAC1_CHCTRL_n_SWRST);
mbed_official 27:4206883f4cb7 293 dummy = RZA_IO_RegRead_32(&DMAC1.CHCTRL_n,
mbed_official 27:4206883f4cb7 294 DMAC1_CHCTRL_n_SWRST_SHIFT,
mbed_official 27:4206883f4cb7 295 DMAC1_CHCTRL_n_SWRST);
mbed_official 27:4206883f4cb7 296 /* Enable DMA transfer */
mbed_official 27:4206883f4cb7 297 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
mbed_official 27:4206883f4cb7 298 1,
mbed_official 27:4206883f4cb7 299 DMAC1_CHCTRL_n_SETEN_SHIFT,
mbed_official 27:4206883f4cb7 300 DMAC1_CHCTRL_n_SETEN);
mbed_official 27:4206883f4cb7 301
mbed_official 27:4206883f4cb7 302 /* ---- Request by software ---- */
mbed_official 27:4206883f4cb7 303 if (DMAC_REQ_MODE_SOFT == req)
mbed_official 27:4206883f4cb7 304 {
mbed_official 27:4206883f4cb7 305 /* DMA transfer Request by software */
mbed_official 27:4206883f4cb7 306 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
mbed_official 27:4206883f4cb7 307 1,
mbed_official 27:4206883f4cb7 308 DMAC1_CHCTRL_n_STG_SHIFT,
mbed_official 27:4206883f4cb7 309 DMAC1_CHCTRL_n_STG);
mbed_official 27:4206883f4cb7 310 }
mbed_official 27:4206883f4cb7 311
mbed_official 27:4206883f4cb7 312 ret = 0;
mbed_official 27:4206883f4cb7 313 }
mbed_official 27:4206883f4cb7 314 else
mbed_official 27:4206883f4cb7 315 {
mbed_official 27:4206883f4cb7 316 ret = -1;
mbed_official 27:4206883f4cb7 317 }
mbed_official 27:4206883f4cb7 318
mbed_official 27:4206883f4cb7 319 return ret;
mbed_official 27:4206883f4cb7 320 }
mbed_official 27:4206883f4cb7 321
mbed_official 27:4206883f4cb7 322 /*******************************************************************************
mbed_official 27:4206883f4cb7 323 * Function Name: usb0_host_DMAC1_Close
mbed_official 27:4206883f4cb7 324 * Description : Aborts DMAC channel 1 transfer. Returns the remaining transfer
mbed_official 27:4206883f4cb7 325 * : byte count at the time of DMA transfer abort to the argument
mbed_official 27:4206883f4cb7 326 * : *remain.
mbed_official 27:4206883f4cb7 327 * Arguments : uint32_t * remain : Remaining transfer byte count when
mbed_official 27:4206883f4cb7 328 * : : DMA transfer is aborted
mbed_official 27:4206883f4cb7 329 * Return Value : none
mbed_official 27:4206883f4cb7 330 *******************************************************************************/
mbed_official 27:4206883f4cb7 331 void usb0_host_DMAC1_Close (uint32_t * remain)
mbed_official 27:4206883f4cb7 332 {
mbed_official 27:4206883f4cb7 333
mbed_official 27:4206883f4cb7 334 /* ==== Abort transfer ==== */
mbed_official 27:4206883f4cb7 335 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
mbed_official 27:4206883f4cb7 336 1,
mbed_official 27:4206883f4cb7 337 DMAC1_CHCTRL_n_CLREN_SHIFT,
mbed_official 27:4206883f4cb7 338 DMAC1_CHCTRL_n_CLREN);
mbed_official 27:4206883f4cb7 339
mbed_official 27:4206883f4cb7 340 while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
mbed_official 27:4206883f4cb7 341 DMAC1_CHSTAT_n_TACT_SHIFT,
mbed_official 27:4206883f4cb7 342 DMAC1_CHSTAT_n_TACT))
mbed_official 27:4206883f4cb7 343 {
mbed_official 27:4206883f4cb7 344 /* Loop until transfer is aborted */
mbed_official 27:4206883f4cb7 345 }
mbed_official 27:4206883f4cb7 346
mbed_official 27:4206883f4cb7 347 while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
mbed_official 27:4206883f4cb7 348 DMAC1_CHSTAT_n_EN_SHIFT,
mbed_official 27:4206883f4cb7 349 DMAC1_CHSTAT_n_EN))
mbed_official 27:4206883f4cb7 350 {
mbed_official 27:4206883f4cb7 351 /* Loop until 0 is set in EN before checking the remaining transfer byte count */
mbed_official 27:4206883f4cb7 352 }
mbed_official 27:4206883f4cb7 353 /* ==== Obtain remaining transfer byte count ==== */
mbed_official 27:4206883f4cb7 354 *remain = DMAC1.CRTB_n;
mbed_official 27:4206883f4cb7 355 }
mbed_official 27:4206883f4cb7 356
mbed_official 27:4206883f4cb7 357 /*******************************************************************************
mbed_official 27:4206883f4cb7 358 * Function Name: usb0_host_DMAC1_Load_Set
mbed_official 27:4206883f4cb7 359 * Description : Sets the transfer source address, transfer destination
mbed_official 27:4206883f4cb7 360 * : address, and total transfer byte count respectively
mbed_official 27:4206883f4cb7 361 * : specified by the argument src_addr, dst_addr, and count to
mbed_official 27:4206883f4cb7 362 * : DMAC channel 1 as DMA transfer information.
mbed_official 27:4206883f4cb7 363 * : Sets the register set selected by the CHCFG_n register
mbed_official 27:4206883f4cb7 364 * : RSEL bit from the Next0 or Next1 register set.
mbed_official 27:4206883f4cb7 365 * : This function should be called when DMA transfer of DMAC
mbed_official 27:4206883f4cb7 366 * : channel 1 is aboted.
mbed_official 27:4206883f4cb7 367 * Arguments : uint32_t src_addr : Transfer source address
mbed_official 27:4206883f4cb7 368 * : uint32_t dst_addr : Transfer destination address
mbed_official 27:4206883f4cb7 369 * : uint32_t count : Total transfer byte count
mbed_official 27:4206883f4cb7 370 * Return Value : none
mbed_official 27:4206883f4cb7 371 *******************************************************************************/
mbed_official 27:4206883f4cb7 372 void usb0_host_DMAC1_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
mbed_official 27:4206883f4cb7 373 {
mbed_official 27:4206883f4cb7 374 uint8_t reg_set;
mbed_official 27:4206883f4cb7 375
mbed_official 27:4206883f4cb7 376 /* Obtain register set in use */
mbed_official 27:4206883f4cb7 377 reg_set = RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
mbed_official 27:4206883f4cb7 378 DMAC1_CHSTAT_n_SR_SHIFT,
mbed_official 27:4206883f4cb7 379 DMAC1_CHSTAT_n_SR);
mbed_official 27:4206883f4cb7 380
mbed_official 27:4206883f4cb7 381 /* ==== Load ==== */
mbed_official 27:4206883f4cb7 382 if (0 == reg_set)
mbed_official 27:4206883f4cb7 383 {
mbed_official 27:4206883f4cb7 384 /* ---- Next0 Register Set ---- */
mbed_official 27:4206883f4cb7 385 DMAC1.N0SA_n = src_addr; /* Start address of transfer source */
mbed_official 27:4206883f4cb7 386 DMAC1.N0DA_n = dst_addr; /* Start address of transfer destination */
mbed_official 27:4206883f4cb7 387 DMAC1.N0TB_n = count; /* Total transfer byte count */
mbed_official 27:4206883f4cb7 388 }
mbed_official 27:4206883f4cb7 389 else
mbed_official 27:4206883f4cb7 390 {
mbed_official 27:4206883f4cb7 391 /* ---- Next1 Register Set ---- */
mbed_official 27:4206883f4cb7 392 DMAC1.N1SA_n = src_addr; /* Start address of transfer source */
mbed_official 27:4206883f4cb7 393 DMAC1.N1DA_n = dst_addr; /* Start address of transfer destination */
mbed_official 27:4206883f4cb7 394 DMAC1.N1TB_n = count; /* Total transfer byte count */
mbed_official 27:4206883f4cb7 395 }
mbed_official 27:4206883f4cb7 396 }
mbed_official 27:4206883f4cb7 397
mbed_official 27:4206883f4cb7 398 /*******************************************************************************
mbed_official 27:4206883f4cb7 399 * Function Name: usb0_host_DMAC2_PeriReqInit
mbed_official 27:4206883f4cb7 400 * Description : Sets the register mode for DMA mode and the on-chip peripheral
mbed_official 27:4206883f4cb7 401 * : module request for transfer request for DMAC channel 2.
mbed_official 27:4206883f4cb7 402 * : Executes DMAC initial setting using the DMA information
mbed_official 27:4206883f4cb7 403 * : specified by the argument *trans_info and the enabled/disabled
mbed_official 27:4206883f4cb7 404 * : continuous transfer specified by the argument continuation.
mbed_official 27:4206883f4cb7 405 * : Registers DMAC channel 2 interrupt handler function and sets
mbed_official 27:4206883f4cb7 406 * : the interrupt priority level. Then enables transfer completion
mbed_official 27:4206883f4cb7 407 * : interrupt.
mbed_official 27:4206883f4cb7 408 * Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
mbed_official 27:4206883f4cb7 409 * : : register
mbed_official 27:4206883f4cb7 410 * : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
mbed_official 27:4206883f4cb7 411 * : uint32_t continuation : Set continuous transfer to be valid
mbed_official 27:4206883f4cb7 412 * : : after DMA transfer has been completed
mbed_official 27:4206883f4cb7 413 * : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
mbed_official 27:4206883f4cb7 414 * : DMAC_SAMPLE_SINGLE : Do not execute continuous
mbed_official 27:4206883f4cb7 415 * : : transfer
mbed_official 27:4206883f4cb7 416 * : uint32_t request_factor : Factor for on-chip peripheral module
mbed_official 27:4206883f4cb7 417 * : : request
mbed_official 27:4206883f4cb7 418 * : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
mbed_official 27:4206883f4cb7 419 * : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
mbed_official 27:4206883f4cb7 420 * : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
mbed_official 27:4206883f4cb7 421 * : :
mbed_official 27:4206883f4cb7 422 * : uint32_t req_direction : Setting value of CHCFG_n register
mbed_official 27:4206883f4cb7 423 * : : REQD bit
mbed_official 27:4206883f4cb7 424 * Return Value : none
mbed_official 27:4206883f4cb7 425 *******************************************************************************/
mbed_official 27:4206883f4cb7 426 void usb0_host_DMAC2_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
mbed_official 27:4206883f4cb7 427 uint32_t request_factor, uint32_t req_direction)
mbed_official 27:4206883f4cb7 428 {
mbed_official 27:4206883f4cb7 429 /* ==== Register mode ==== */
mbed_official 27:4206883f4cb7 430 if (DMAC_MODE_REGISTER == dmamode)
mbed_official 27:4206883f4cb7 431 {
mbed_official 27:4206883f4cb7 432 /* ==== Next0 register set ==== */
mbed_official 27:4206883f4cb7 433 DMAC2.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
mbed_official 27:4206883f4cb7 434 DMAC2.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
mbed_official 27:4206883f4cb7 435 DMAC2.N0TB_n = trans_info->count; /* Total transfer byte count */
mbed_official 27:4206883f4cb7 436
mbed_official 27:4206883f4cb7 437 /* DAD : Transfer destination address counting direction */
mbed_official 27:4206883f4cb7 438 /* SAD : Transfer source address counting direction */
mbed_official 27:4206883f4cb7 439 /* DDS : Transfer destination transfer size */
mbed_official 27:4206883f4cb7 440 /* SDS : Transfer source transfer size */
mbed_official 27:4206883f4cb7 441 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 27:4206883f4cb7 442 trans_info->daddr_dir,
mbed_official 27:4206883f4cb7 443 DMAC2_CHCFG_n_DAD_SHIFT,
mbed_official 27:4206883f4cb7 444 DMAC2_CHCFG_n_DAD);
mbed_official 27:4206883f4cb7 445 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 27:4206883f4cb7 446 trans_info->saddr_dir,
mbed_official 27:4206883f4cb7 447 DMAC2_CHCFG_n_SAD_SHIFT,
mbed_official 27:4206883f4cb7 448 DMAC2_CHCFG_n_SAD);
mbed_official 27:4206883f4cb7 449 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 27:4206883f4cb7 450 trans_info->dst_size,
mbed_official 27:4206883f4cb7 451 DMAC2_CHCFG_n_DDS_SHIFT,
mbed_official 27:4206883f4cb7 452 DMAC2_CHCFG_n_DDS);
mbed_official 27:4206883f4cb7 453 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 27:4206883f4cb7 454 trans_info->src_size,
mbed_official 27:4206883f4cb7 455 DMAC2_CHCFG_n_SDS_SHIFT,
mbed_official 27:4206883f4cb7 456 DMAC2_CHCFG_n_SDS);
mbed_official 27:4206883f4cb7 457
mbed_official 27:4206883f4cb7 458 /* DMS : Register mode */
mbed_official 27:4206883f4cb7 459 /* RSEL : Select Next0 register set */
mbed_official 27:4206883f4cb7 460 /* SBE : No discharge of buffer data when aborted */
mbed_official 27:4206883f4cb7 461 /* DEM : No DMA interrupt mask */
mbed_official 27:4206883f4cb7 462 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 27:4206883f4cb7 463 0,
mbed_official 27:4206883f4cb7 464 DMAC2_CHCFG_n_DMS_SHIFT,
mbed_official 27:4206883f4cb7 465 DMAC2_CHCFG_n_DMS);
mbed_official 27:4206883f4cb7 466 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 27:4206883f4cb7 467 0,
mbed_official 27:4206883f4cb7 468 DMAC2_CHCFG_n_RSEL_SHIFT,
mbed_official 27:4206883f4cb7 469 DMAC2_CHCFG_n_RSEL);
mbed_official 27:4206883f4cb7 470 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 27:4206883f4cb7 471 0,
mbed_official 27:4206883f4cb7 472 DMAC2_CHCFG_n_SBE_SHIFT,
mbed_official 27:4206883f4cb7 473 DMAC2_CHCFG_n_SBE);
mbed_official 27:4206883f4cb7 474 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 27:4206883f4cb7 475 0,
mbed_official 27:4206883f4cb7 476 DMAC2_CHCFG_n_DEM_SHIFT,
mbed_official 27:4206883f4cb7 477 DMAC2_CHCFG_n_DEM);
mbed_official 27:4206883f4cb7 478
mbed_official 27:4206883f4cb7 479 /* ---- Continuous transfer ---- */
mbed_official 27:4206883f4cb7 480 if (DMAC_SAMPLE_CONTINUATION == continuation)
mbed_official 27:4206883f4cb7 481 {
mbed_official 27:4206883f4cb7 482 /* REN : Execute continuous transfer */
mbed_official 27:4206883f4cb7 483 /* RSW : Change register set when DMA transfer is completed. */
mbed_official 27:4206883f4cb7 484 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 27:4206883f4cb7 485 1,
mbed_official 27:4206883f4cb7 486 DMAC2_CHCFG_n_REN_SHIFT,
mbed_official 27:4206883f4cb7 487 DMAC2_CHCFG_n_REN);
mbed_official 27:4206883f4cb7 488 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 27:4206883f4cb7 489 1,
mbed_official 27:4206883f4cb7 490 DMAC2_CHCFG_n_RSW_SHIFT,
mbed_official 27:4206883f4cb7 491 DMAC2_CHCFG_n_RSW);
mbed_official 27:4206883f4cb7 492 }
mbed_official 27:4206883f4cb7 493 /* ---- Single transfer ---- */
mbed_official 27:4206883f4cb7 494 else
mbed_official 27:4206883f4cb7 495 {
mbed_official 27:4206883f4cb7 496 /* REN : Do not execute continuous transfer */
mbed_official 27:4206883f4cb7 497 /* RSW : Do not change register set when DMA transfer is completed. */
mbed_official 27:4206883f4cb7 498 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 27:4206883f4cb7 499 0,
mbed_official 27:4206883f4cb7 500 DMAC2_CHCFG_n_REN_SHIFT,
mbed_official 27:4206883f4cb7 501 DMAC2_CHCFG_n_REN);
mbed_official 27:4206883f4cb7 502 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 27:4206883f4cb7 503 0,
mbed_official 27:4206883f4cb7 504 DMAC2_CHCFG_n_RSW_SHIFT,
mbed_official 27:4206883f4cb7 505 DMAC2_CHCFG_n_RSW);
mbed_official 27:4206883f4cb7 506 }
mbed_official 27:4206883f4cb7 507
mbed_official 27:4206883f4cb7 508 /* TM : Single transfer */
mbed_official 27:4206883f4cb7 509 /* SEL : Channel setting */
mbed_official 27:4206883f4cb7 510 /* HIEN, LOEN : On-chip peripheral module request */
mbed_official 27:4206883f4cb7 511 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 27:4206883f4cb7 512 0,
mbed_official 27:4206883f4cb7 513 DMAC2_CHCFG_n_TM_SHIFT,
mbed_official 27:4206883f4cb7 514 DMAC2_CHCFG_n_TM);
mbed_official 27:4206883f4cb7 515 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 27:4206883f4cb7 516 2,
mbed_official 27:4206883f4cb7 517 DMAC2_CHCFG_n_SEL_SHIFT,
mbed_official 27:4206883f4cb7 518 DMAC2_CHCFG_n_SEL);
mbed_official 27:4206883f4cb7 519 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 27:4206883f4cb7 520 1,
mbed_official 27:4206883f4cb7 521 DMAC2_CHCFG_n_HIEN_SHIFT,
mbed_official 27:4206883f4cb7 522 DMAC2_CHCFG_n_HIEN);
mbed_official 27:4206883f4cb7 523 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 27:4206883f4cb7 524 0,
mbed_official 27:4206883f4cb7 525 DMAC2_CHCFG_n_LOEN_SHIFT,
mbed_official 27:4206883f4cb7 526 DMAC2_CHCFG_n_LOEN);
mbed_official 27:4206883f4cb7 527
mbed_official 27:4206883f4cb7 528 /* ---- Set factor by specified on-chip peripheral module request ---- */
mbed_official 27:4206883f4cb7 529 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 27:4206883f4cb7 530 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
mbed_official 27:4206883f4cb7 531 DMAC2_CHCFG_n_AM_SHIFT,
mbed_official 27:4206883f4cb7 532 DMAC2_CHCFG_n_AM);
mbed_official 27:4206883f4cb7 533 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 27:4206883f4cb7 534 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
mbed_official 27:4206883f4cb7 535 DMAC2_CHCFG_n_LVL_SHIFT,
mbed_official 27:4206883f4cb7 536 DMAC2_CHCFG_n_LVL);
mbed_official 27:4206883f4cb7 537 if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
mbed_official 27:4206883f4cb7 538 {
mbed_official 27:4206883f4cb7 539 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 27:4206883f4cb7 540 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
mbed_official 27:4206883f4cb7 541 DMAC2_CHCFG_n_REQD_SHIFT,
mbed_official 27:4206883f4cb7 542 DMAC2_CHCFG_n_REQD);
mbed_official 27:4206883f4cb7 543 }
mbed_official 27:4206883f4cb7 544 else
mbed_official 27:4206883f4cb7 545 {
mbed_official 27:4206883f4cb7 546 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 27:4206883f4cb7 547 req_direction,
mbed_official 27:4206883f4cb7 548 DMAC2_CHCFG_n_REQD_SHIFT,
mbed_official 27:4206883f4cb7 549 DMAC2_CHCFG_n_REQD);
mbed_official 27:4206883f4cb7 550 }
mbed_official 27:4206883f4cb7 551 RZA_IO_RegWrite_32(&DMAC23.DMARS,
mbed_official 27:4206883f4cb7 552 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
mbed_official 27:4206883f4cb7 553 DMAC23_DMARS_CH2_RID_SHIFT,
mbed_official 27:4206883f4cb7 554 DMAC23_DMARS_CH2_RID);
mbed_official 27:4206883f4cb7 555 RZA_IO_RegWrite_32(&DMAC23.DMARS,
mbed_official 27:4206883f4cb7 556 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
mbed_official 27:4206883f4cb7 557 DMAC23_DMARS_CH2_MID_SHIFT,
mbed_official 27:4206883f4cb7 558 DMAC23_DMARS_CH2_MID);
mbed_official 27:4206883f4cb7 559
mbed_official 27:4206883f4cb7 560 /* PR : Round robin mode */
mbed_official 27:4206883f4cb7 561 RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
mbed_official 27:4206883f4cb7 562 1,
mbed_official 27:4206883f4cb7 563 DMAC07_DCTRL_0_7_PR_SHIFT,
mbed_official 27:4206883f4cb7 564 DMAC07_DCTRL_0_7_PR);
mbed_official 27:4206883f4cb7 565 }
mbed_official 27:4206883f4cb7 566 }
mbed_official 27:4206883f4cb7 567
mbed_official 27:4206883f4cb7 568 /*******************************************************************************
mbed_official 27:4206883f4cb7 569 * Function Name: usb0_host_DMAC2_Open
mbed_official 27:4206883f4cb7 570 * Description : Enables DMAC channel 2 transfer.
mbed_official 27:4206883f4cb7 571 * Arguments : uint32_t req : DMAC request mode
mbed_official 27:4206883f4cb7 572 * Return Value : 0 : Succeeded in enabling DMA transfer
mbed_official 27:4206883f4cb7 573 * : -1 : Failed to enable DMA transfer (due to DMA operation)
mbed_official 27:4206883f4cb7 574 *******************************************************************************/
mbed_official 27:4206883f4cb7 575 int32_t usb0_host_DMAC2_Open (uint32_t req)
mbed_official 27:4206883f4cb7 576 {
mbed_official 27:4206883f4cb7 577 int32_t ret;
mbed_official 27:4206883f4cb7 578 volatile uint8_t dummy;
mbed_official 27:4206883f4cb7 579
mbed_official 27:4206883f4cb7 580 /* Transferable? */
mbed_official 27:4206883f4cb7 581 if ((0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
mbed_official 27:4206883f4cb7 582 DMAC2_CHSTAT_n_EN_SHIFT,
mbed_official 27:4206883f4cb7 583 DMAC2_CHSTAT_n_EN)) &&
mbed_official 27:4206883f4cb7 584 (0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
mbed_official 27:4206883f4cb7 585 DMAC2_CHSTAT_n_TACT_SHIFT,
mbed_official 27:4206883f4cb7 586 DMAC2_CHSTAT_n_TACT)))
mbed_official 27:4206883f4cb7 587 {
mbed_official 27:4206883f4cb7 588 /* Clear Channel Status Register */
mbed_official 27:4206883f4cb7 589 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
mbed_official 27:4206883f4cb7 590 1,
mbed_official 27:4206883f4cb7 591 DMAC2_CHCTRL_n_SWRST_SHIFT,
mbed_official 27:4206883f4cb7 592 DMAC2_CHCTRL_n_SWRST);
mbed_official 27:4206883f4cb7 593 dummy = RZA_IO_RegRead_32(&DMAC2.CHCTRL_n,
mbed_official 27:4206883f4cb7 594 DMAC2_CHCTRL_n_SWRST_SHIFT,
mbed_official 27:4206883f4cb7 595 DMAC2_CHCTRL_n_SWRST);
mbed_official 27:4206883f4cb7 596 /* Enable DMA transfer */
mbed_official 27:4206883f4cb7 597 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
mbed_official 27:4206883f4cb7 598 1,
mbed_official 27:4206883f4cb7 599 DMAC2_CHCTRL_n_SETEN_SHIFT,
mbed_official 27:4206883f4cb7 600 DMAC2_CHCTRL_n_SETEN);
mbed_official 27:4206883f4cb7 601
mbed_official 27:4206883f4cb7 602 /* ---- Request by software ---- */
mbed_official 27:4206883f4cb7 603 if (DMAC_REQ_MODE_SOFT == req)
mbed_official 27:4206883f4cb7 604 {
mbed_official 27:4206883f4cb7 605 /* DMA transfer Request by software */
mbed_official 27:4206883f4cb7 606 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
mbed_official 27:4206883f4cb7 607 1,
mbed_official 27:4206883f4cb7 608 DMAC2_CHCTRL_n_STG_SHIFT,
mbed_official 27:4206883f4cb7 609 DMAC2_CHCTRL_n_STG);
mbed_official 27:4206883f4cb7 610 }
mbed_official 27:4206883f4cb7 611
mbed_official 27:4206883f4cb7 612 ret = 0;
mbed_official 27:4206883f4cb7 613 }
mbed_official 27:4206883f4cb7 614 else
mbed_official 27:4206883f4cb7 615 {
mbed_official 27:4206883f4cb7 616 ret = -1;
mbed_official 27:4206883f4cb7 617 }
mbed_official 27:4206883f4cb7 618
mbed_official 27:4206883f4cb7 619 return ret;
mbed_official 27:4206883f4cb7 620 }
mbed_official 27:4206883f4cb7 621
mbed_official 27:4206883f4cb7 622 /*******************************************************************************
mbed_official 27:4206883f4cb7 623 * Function Name: usb0_host_DMAC2_Close
mbed_official 27:4206883f4cb7 624 * Description : Aborts DMAC channel 2 transfer. Returns the remaining transfer
mbed_official 27:4206883f4cb7 625 * : byte count at the time of DMA transfer abort to the argument
mbed_official 27:4206883f4cb7 626 * : *remain.
mbed_official 27:4206883f4cb7 627 * Arguments : uint32_t * remain : Remaining transfer byte count when
mbed_official 27:4206883f4cb7 628 * : : DMA transfer is aborted
mbed_official 27:4206883f4cb7 629 * Return Value : none
mbed_official 27:4206883f4cb7 630 *******************************************************************************/
mbed_official 27:4206883f4cb7 631 void usb0_host_DMAC2_Close (uint32_t * remain)
mbed_official 27:4206883f4cb7 632 {
mbed_official 27:4206883f4cb7 633
mbed_official 27:4206883f4cb7 634 /* ==== Abort transfer ==== */
mbed_official 27:4206883f4cb7 635 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
mbed_official 27:4206883f4cb7 636 1,
mbed_official 27:4206883f4cb7 637 DMAC2_CHCTRL_n_CLREN_SHIFT,
mbed_official 27:4206883f4cb7 638 DMAC2_CHCTRL_n_CLREN);
mbed_official 27:4206883f4cb7 639
mbed_official 27:4206883f4cb7 640 while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
mbed_official 27:4206883f4cb7 641 DMAC2_CHSTAT_n_TACT_SHIFT,
mbed_official 27:4206883f4cb7 642 DMAC2_CHSTAT_n_TACT))
mbed_official 27:4206883f4cb7 643 {
mbed_official 27:4206883f4cb7 644 /* Loop until transfer is aborted */
mbed_official 27:4206883f4cb7 645 }
mbed_official 27:4206883f4cb7 646
mbed_official 27:4206883f4cb7 647 while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
mbed_official 27:4206883f4cb7 648 DMAC2_CHSTAT_n_EN_SHIFT,
mbed_official 27:4206883f4cb7 649 DMAC2_CHSTAT_n_EN))
mbed_official 27:4206883f4cb7 650 {
mbed_official 27:4206883f4cb7 651 /* Loop until 0 is set in EN before checking the remaining transfer byte count */
mbed_official 27:4206883f4cb7 652 }
mbed_official 27:4206883f4cb7 653 /* ==== Obtain remaining transfer byte count ==== */
mbed_official 27:4206883f4cb7 654 *remain = DMAC2.CRTB_n;
mbed_official 27:4206883f4cb7 655 }
mbed_official 27:4206883f4cb7 656
mbed_official 27:4206883f4cb7 657 /*******************************************************************************
mbed_official 27:4206883f4cb7 658 * Function Name: usb0_host_DMAC2_Load_Set
mbed_official 27:4206883f4cb7 659 * Description : Sets the transfer source address, transfer destination
mbed_official 27:4206883f4cb7 660 * : address, and total transfer byte count respectively
mbed_official 27:4206883f4cb7 661 * : specified by the argument src_addr, dst_addr, and count to
mbed_official 27:4206883f4cb7 662 * : DMAC channel 2 as DMA transfer information.
mbed_official 27:4206883f4cb7 663 * : Sets the register set selected by the CHCFG_n register
mbed_official 27:4206883f4cb7 664 * : RSEL bit from the Next0 or Next1 register set.
mbed_official 27:4206883f4cb7 665 * : This function should be called when DMA transfer of DMAC
mbed_official 27:4206883f4cb7 666 * : channel 2 is aboted.
mbed_official 27:4206883f4cb7 667 * Arguments : uint32_t src_addr : Transfer source address
mbed_official 27:4206883f4cb7 668 * : uint32_t dst_addr : Transfer destination address
mbed_official 27:4206883f4cb7 669 * : uint32_t count : Total transfer byte count
mbed_official 27:4206883f4cb7 670 * Return Value : none
mbed_official 27:4206883f4cb7 671 *******************************************************************************/
mbed_official 27:4206883f4cb7 672 void usb0_host_DMAC2_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
mbed_official 27:4206883f4cb7 673 {
mbed_official 27:4206883f4cb7 674 uint8_t reg_set;
mbed_official 27:4206883f4cb7 675
mbed_official 27:4206883f4cb7 676 /* Obtain register set in use */
mbed_official 27:4206883f4cb7 677 reg_set = RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
mbed_official 27:4206883f4cb7 678 DMAC2_CHSTAT_n_SR_SHIFT,
mbed_official 27:4206883f4cb7 679 DMAC2_CHSTAT_n_SR);
mbed_official 27:4206883f4cb7 680
mbed_official 27:4206883f4cb7 681 /* ==== Load ==== */
mbed_official 27:4206883f4cb7 682 if (0 == reg_set)
mbed_official 27:4206883f4cb7 683 {
mbed_official 27:4206883f4cb7 684 /* ---- Next0 Register Set ---- */
mbed_official 27:4206883f4cb7 685 DMAC2.N0SA_n = src_addr; /* Start address of transfer source */
mbed_official 27:4206883f4cb7 686 DMAC2.N0DA_n = dst_addr; /* Start address of transfer destination */
mbed_official 27:4206883f4cb7 687 DMAC2.N0TB_n = count; /* Total transfer byte count */
mbed_official 27:4206883f4cb7 688 }
mbed_official 27:4206883f4cb7 689 else
mbed_official 27:4206883f4cb7 690 {
mbed_official 27:4206883f4cb7 691 /* ---- Next1 Register Set ---- */
mbed_official 27:4206883f4cb7 692 DMAC2.N1SA_n = src_addr; /* Start address of transfer source */
mbed_official 27:4206883f4cb7 693 DMAC2.N1DA_n = dst_addr; /* Start address of transfer destination */
mbed_official 27:4206883f4cb7 694 DMAC2.N1TB_n = count; /* Total transfer byte count */
mbed_official 27:4206883f4cb7 695 }
mbed_official 27:4206883f4cb7 696 }
mbed_official 27:4206883f4cb7 697
mbed_official 27:4206883f4cb7 698 /* End of File */