Revision 6:aa1fc6a5cc2a, committed 2015-10-02

Comitter:

dkato

Date:

Fri Oct 02 03:03:25 2015 +0000

Parent:

5:1390bfcb667c

Child:

7:30ebba78fff0

Commit message:

Add SCUX driver

Changed in this revision

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_inc/scux_if.h	Fri Oct 02 03:03:25 2015 +0000
@@ -0,0 +1,469 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          scux_if.h
+* $Rev: 1032 $
+* $Date:: 2014-08-06 09:04:50 +0900#$
+* @brief         SCUX Driver IOIF API header
+******************************************************************************/
+
+#ifndef SCUX_IF_H
+#define SCUX_IF_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+
+#include "cmsis_os.h"
+#include "r_errno.h"
+#include "r_typedefs.h"
+#if(1) /* mbed */
+#include "ioif_aio.h"
+#include "misratypes.h"
+#include "R_BSP_ScuxDef.h"
+#else  /* not mbed */
+#include "ioif_public.h"
+#endif /* end mbed */
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+#if(1) /* mbed */
+#else  /* not mbed */
+/* Number of SCUX channel */
+typedef enum
+{
+    SCUX_CH_0 = 0,
+    SCUX_CH_1 = 1,
+    SCUX_CH_2 = 2,
+    SCUX_CH_3 = 3,
+    SCUX_CH_NUM = 4  /* Number of SCUX channel */
+} scux_ch_num_t;
+#endif /* end mbed */
+
+/* SCUX route setting */
+typedef enum
+{
+    /* mem to mem */
+    SCUX_ROUTE_SRC_MEM_MIN = 0x1000,
+    SCUX_ROUTE_SRC0_MEM    = 0x1001,
+    SCUX_ROUTE_SRC1_MEM    = 0x1002,
+    SCUX_ROUTE_SRC2_MEM    = 0x1003,
+    SCUX_ROUTE_SRC3_MEM    = 0x1004,
+    SCUX_ROUTE_SRC_MEM_MAX = 0x1005,
+    /* mem to SSIF */
+    SCUX_ROUTE_SRC_SSIF_MIN = 0x2000,
+    SCUX_ROUTE_SRC0_SSIF0   = 0x2001,
+    SCUX_ROUTE_SRC0_SSIF012 = 0x2002,
+    SCUX_ROUTE_SRC0_SSIF3   = 0x2003,
+    SCUX_ROUTE_SRC0_SSIF345 = 0x2004,
+    SCUX_ROUTE_SRC1_SSIF0   = 0x2005,
+    SCUX_ROUTE_SRC1_SSIF012 = 0x2006,
+    SCUX_ROUTE_SRC1_SSIF3   = 0x2007,
+    SCUX_ROUTE_SRC1_SSIF345 = 0x2008,    
+    SCUX_ROUTE_SRC2_SSIF1   = 0x2009,
+    SCUX_ROUTE_SRC2_SSIF4   = 0x200A,
+    SCUX_ROUTE_SRC3_SSIF2   = 0x200B,
+    SCUX_ROUTE_SRC3_SSIF5   = 0x200C,
+    SCUX_ROUTE_SRC_SSIF_MAX = 0x200D,
+    /* mem to NIX to SSIF */
+    SCUX_ROUTE_SRC_MIX_SSIF_MIN  = 0x3000,
+    SCUX_ROUTE_SRC0_MIX_SSIF0   = 0x3001,
+    SCUX_ROUTE_SRC0_MIX_SSIF012 = 0x3002,
+    SCUX_ROUTE_SRC0_MIX_SSIF3   = 0x3003,
+    SCUX_ROUTE_SRC0_MIX_SSIF345 = 0x3004,
+    SCUX_ROUTE_SRC1_MIX_SSIF0   = 0x3005,
+    SCUX_ROUTE_SRC1_MIX_SSIF012 = 0x3006,
+    SCUX_ROUTE_SRC1_MIX_SSIF3   = 0x3007,
+    SCUX_ROUTE_SRC1_MIX_SSIF345 = 0x3008,   
+    SCUX_ROUTE_SRC2_MIX_SSIF0   = 0x3009,
+    SCUX_ROUTE_SRC2_MIX_SSIF012 = 0x300A,
+    SCUX_ROUTE_SRC2_MIX_SSIF3   = 0x300B,
+    SCUX_ROUTE_SRC2_MIX_SSIF345 = 0x300C,
+    SCUX_ROUTE_SRC3_MIX_SSIF0   = 0x300D,
+    SCUX_ROUTE_SRC3_MIX_SSIF012 = 0x300E,
+    SCUX_ROUTE_SRC3_MIX_SSIF3   = 0x300F,
+    SCUX_ROUTE_SRC3_MIX_SSIF345 = 0x3010,   
+    SCUX_ROUTE_SRC_MIX_SSIF_MAX = 0x3011
+} scux_route_t;
+
+#if(1) /* mbed */
+#else  /* not mbed */
+/* used audio channel number setting */
+typedef enum
+{
+    SCUX_USE_CH_1 = 1,   /* used audio channel number is 1 */
+    SCUX_USE_CH_2 = 2,   /* used audio channel number is 2 */
+    SCUX_USE_CH_4 = 4,   /* used audio channel number is 4 */
+    SCUX_USE_CH_6 = 6,   /* used audio channel number is 6 */
+    SCUX_USE_CH_8 = 8    /* used audio channel number is 8 */
+} scux_use_channel_t;
+#endif /* end mbed */
+
+/* select audio channel number setting */
+typedef enum
+{
+    SCUX_AUDIO_CH_MIN = -1,
+    SCUX_AUDIO_CH_0 = 0,   /* select audio channel number is 0 */
+    SCUX_AUDIO_CH_1 = 1,   /* select audio channel number is 1 */
+    SCUX_AUDIO_CH_2 = 2,   /* select audio channel number is 2 */
+    SCUX_AUDIO_CH_3 = 3,   /* select audio channel number is 3 */
+    SCUX_AUDIO_CH_4 = 4,   /* select audio channel number is 4 */
+    SCUX_AUDIO_CH_5 = 5,   /* select audio channel number is 5 */
+    SCUX_AUDIO_CH_6 = 6,   /* select audio channel number is 6 */
+    SCUX_AUDIO_CH_7 = 7,   /* select audio channel number is 7 */
+    SCUX_AUDIO_CH_MAX = 8
+} scux_audio_channel_t;
+
+#if(1) /* mbed */
+#else  /* not mbed */
+/* SCUX data word length */
+typedef enum
+{
+    SCUX_DATA_LEN_MIN      =(-1),
+    SCUX_DATA_LEN_24       = 0,   /* data word length is 24bit */
+    SCUX_DATA_LEN_16       = 1,   /* data word length is 16bit */
+    SCUX_DATA_LEN_16_TO_24 = 2,   /* data word length is 24bit */
+    SCUX_DATA_LEN_MAX      = 3
+} scux_data_word_len_t;
+#endif /* end mbed */
+
+/* SSIF PIN mode setting */
+typedef enum
+{
+    SCUX_PIN_MODE_MIN          =(-1),
+    SCUX_PIN_MODE_INDEPEND     = 0,   /* PIN mode is independent */
+    SCUX_PIN_MODE_SLAVE_SLAVE  = 1,   /* PIN mode is slave-slave */
+    SCUX_PIN_MODE_MASTER_SLAVE = 2,   /* PIN mode is master-slave */
+    SCUX_PIN_MODE_MAX = 3
+} scux_pin_mode_t;
+
+/* SCUX sampling rate */
+typedef enum
+{
+    SCUX_SYNC_RATE_8      = 8000,    /* 8KHz */
+    SCUX_SYNC_RATE_11_025 = 11025,   /* 11.025KHz */
+    SCUX_SYNC_RATE_12     = 12000,   /* 12KHz */
+    SCUX_SYNC_RATE_16     = 16000,   /* 16KHz */
+    SCUX_SYNC_RATE_22_05  = 22050,   /* 22.05KHz */
+    SCUX_SYNC_RATE_24     = 24000,   /* 24KHz */
+    SCUX_SYNC_RATE_32     = 32000,   /* 32KHz */
+    SCUX_SYNC_RATE_44_1   = 44100,   /* 44.1KHz */
+    SCUX_SYNC_RATE_48     = 48000,   /* 48KHz */
+    SCUX_SYNC_RATE_64     = 64000,   /* 64KHz */
+    SCUX_SYNC_RATE_88_2   = 88200,   /* 88.2KHz */
+    SCUX_SYNC_RATE_96     = 96000    /* 96KHz */
+} scux_src_sync_rate_t;
+
+/* SCUX clock source setting */
+typedef enum
+{
+    SCUX_CLK_MIN  =(-1),
+    SCUX_CLK_AUDIO_CLK  = 0,   /* clock source is AUDIO_CLK */
+    SCUX_CLK_AUDIO_X1   = 1,   /* clock source is AUDIO_X1 */
+    SCUX_CLK_MLB_CLK    = 2,   /* clock source is MLB_CLK */
+    SCUX_CLK_USB_X1     = 3,   /* clock source is USB_X1 */
+    SCUX_CLK_CLKP1_2    = 4,   /* clock source is surrounding clock */
+    SCUX_CLK_MTU_TIOC3A = 5,   /* clock source is TIOC3A */
+    SCUX_CLK_MTU_TIOC4A = 6,   /* clock source is TIOC4A */
+    SCUX_CLK_SSIF0_WS   = 8,   /* clock source is SSIF0 WS */
+    SCUX_CLK_SSIF1_WS   = 9,   /* clock source is SSIF1 WS */
+    SCUX_CLK_SSIF2_WS   = 10,   /* clock source is SSIF2 WS */
+    SCUX_CLK_SSIF3_WS   = 11,  /* clock source is SSIF3 WS */
+    SCUX_CLK_SSIF4_WS   = 12,  /* clock source is SSIF4 WS */
+    SCUX_CLK_SSIF5_WS   = 13,  /* clock source is SSIF5 WS */
+    SCUX_CLK_MAX        = 14
+} scux_src_clk_source_t;
+
+/* SCUX delay mode setting */
+typedef enum
+{
+    SCUX_DELAY_MIN         =(-1),  
+    SCUX_DELAY_NORMAL      = 0,    /* Delay mode is normal */
+    SCUX_DELAY_LOW_DELAY1  = 1,    /* Delay mode is Low Delay1 */
+    SCUX_DELAY_LOW_DELAY2  = 2,    /* Delay mode is Low Delay2 */
+    SCUX_DELAY_MAX         = 3     
+} scux_src_delay_mode_t;
+
+/* DVU ramp time setting */
+typedef enum
+{
+    SCUX_DVU_TIME_MIN  =(-1),
+    SCUX_DVU_TIME_128DB_1STEP      = 0,   /* volume change 128DB among 1 step */
+    SCUX_DVU_TIME_64DB_1STEP       = 1,   /* volume change 64DB among 1 step */
+    SCUX_DVU_TIME_32DB_1STEP       = 2,   /* volume change 32DB among 1 step */
+    SCUX_DVU_TIME_16DB_1STEP       = 3,   /* volume change 16DB among 1 step */
+    SCUX_DVU_TIME_8DB_1STEP        = 4,   /* volume change 8DB among 1 step */
+    SCUX_DVU_TIME_4DB_1STEP        = 5,   /* volume change 4DB among 1 step */
+    SCUX_DVU_TIME_2DB_1STEP        = 6,   /* volume change 2DB among 1 step */
+    SCUX_DVU_TIME_1DB_1STEP        = 7,   /* volume change 1DB among 1 step */
+    SCUX_DVU_TIME_0_5DB_1STEP      = 8,   /* volume change 0.5DB among 1 step */
+    SCUX_DVU_TIME_0_25DB_1STEP     = 9,   /* volume change 0.25DB among 1 step */
+    SCUX_DVU_TIME_0_125DB_1STEP    = 10,  /* volume change 0.125DB among 1 step */
+    SCUX_DVU_TIME_0_125DB_2STEP    = 11,  /* volume change 0.125DB among 2 step */
+    SCUX_DVU_TIME_0_125DB_4STEP    = 12,  /* volume change 0.125DB among 4 step */
+    SCUX_DVU_TIME_0_125DB_8STEP    = 13,  /* volume change 0.125DB among 8 step */
+    SCUX_DVU_TIME_0_125DB_16STEP   = 14,  /* volume change 0.125DB among 16 step */
+    SCUX_DVU_TIME_0_125DB_32STEP   = 15,  /* volume change 0.125DB among 32 step */
+    SCUX_DVU_TIME_0_125DB_64STEP   = 16,  /* volume change 0.125DB among 64 step */
+    SCUX_DVU_TIME_0_125DB_128STEP  = 17,  /* volume change 0.125DB among 128 step */
+    SCUX_DVU_TIME_0_125DB_256STEP  = 18,  /* volume change 0.125DB among 256 step */
+    SCUX_DVU_TIME_0_125DB_512STEP  = 19,  /* volume change 0.125DB among 512 step */
+    SCUX_DVU_TIME_0_125DB_1024STEP = 20,  /* volume change 0.125DB among 1024 step */
+    SCUX_DVU_TIME_0_125DB_2048STEP = 21,  /* volume change 0.125DB among 2048 step */
+    SCUX_DVU_TIME_0_125DB_4096STEP = 22,  /* volume change 0.125DB among 4096 step */
+    SCUX_DVU_TIME_0_125DB_8192STEP = 23,  /* volume change 0.125DB among 8192 step */
+    SCUX_DVU_TIME_MAX              = 24   
+} scux_dvu_ramp_time_t;
+
+/* MIX ramp time setting */
+typedef enum
+{
+    SCUX_MIX_TIME_MIN            =(-1),  
+    SCUX_MIX_TIME_128DB_1STEP    = 0,    /* volume change 128DB among 1 step */
+    SCUX_MIX_TIME_64DB_1STEP     = 1,    /* volume change 64DB among 1 step */
+    SCUX_MIX_TIME_32DB_1STEP     = 2,    /* volume change 32DB among 1 step */
+    SCUX_MIX_TIME_16DB_1STEP     = 3,    /* volume change 16DB among 1 step */
+    SCUX_MIX_TIME_8DB_1STEP      = 4,    /* volume change 8DB among 1 step */
+    SCUX_MIX_TIME_4DB_1STEP      = 5,    /* volume change 4DB among 1 step */
+    SCUX_MIX_TIME_2DB_1STEP      = 6,    /* volume change 2DB among 1 step */
+    SCUX_MIX_TIME_1DB_1STEP      = 7,    /* volume change 1DB among 1 step */
+    SCUX_MIX_TIME_0_5DB_1STEP    = 8,    /* volume change 0.5DB among 1 step */
+    SCUX_MIX_TIME_0_25DB_1STEP   = 9,    /* volume change 0.25DB among 1 step */
+    SCUX_MIX_TIME_0_125DB_1STEP  = 10,   /* volume change 0.125DB among 1 step */
+    SCUX_MIX_TIME_MAX            = 11     
+} scux_mix_ramp_time_t;
+
+/* SSIF channels */
+typedef enum
+{
+    SCUX_SSIF_CH_0    = 0,    /* volume change 128DB among 1 step */
+    SCUX_SSIF_CH_1    = 1,    /* volume change 64DB among 1 step */
+    SCUX_SSIF_CH_2    = 2,    /* volume change 32DB among 1 step */
+    SCUX_SSIF_CH_3    = 3,    /* volume change 16DB among 1 step */
+    SCUX_SSIF_CH_4    = 4,    /* volume change 8DB among 1 step */
+    SCUX_SSIF_CH_5    = 5,    /* volume change 4DB among 1 step */
+    SCUX_SSIF_CH_NUM  = 6
+} scux_ssif_ch_num_t;
+
+/* SSIF channels */
+typedef enum
+{
+    SCUX_SSIF_SYSTEM_LEN_MIN   = 0,    
+    SCUX_SSIF_SYSTEM_LEN_16    = 1,    /* SSIF system word length is 16bit */
+    SCUX_SSIF_SYSTEM_LEN_24    = 2,    /* SSIF system word length is 24bit */
+    SCUX_SSIF_SYSTEM_LEN_32    = 3,    /* SSIF system word length is 32bit */
+    SCUX_SSIF_SYSTEM_LEN_48    = 4,    /* SSIF system word length is 48bit */
+    SCUX_SSIF_SYSTEM_LEN_64    = 5,    /* SSIF system word length is 64bit */
+    SCUX_SSIF_SYSTEM_LEN_128   = 6,    /* SSIF system word length is 128bit */
+    SCUX_SSIF_SYSTEM_LEN_256   = 7,    /* SSIF system word length is 256bit */
+    SCUX_SSIF_SYSTEM_LEN_MAX   = 8
+} scux_ssif_system_len_t;
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* SCUX IOCTL function code */
+#define SCUX_IOCTL_MIN                 (-1)
+#define SCUX_IOCTL_SET_START           0   /* start transfer */
+#define SCUX_IOCTL_SET_FLUSH_STOP      1   /* set flush stop function */
+#define SCUX_IOCTL_SET_CLEAR_STOP      2   /* set clear stop function */
+#define SCUX_IOCTL_SET_ROUTE           3   /* set route parameter */
+#define SCUX_IOCTL_SET_PIN_CLK         4   /* set pin clock parameter */
+#define SCUX_IOCTL_SET_PIN_MODE        5   /* set pin mode parameter */
+#define SCUX_IOCTL_SET_SRC_CFG         6   /* set SRC parameter */
+#define SCUX_IOCTL_SET_DVU_CFG         7   /* set DVU parameter */
+#define SCUX_IOCTL_SET_DVU_DIGI_VOL    8   /* set dgital volume parameter */
+#define SCUX_IOCTL_SET_DVU_RAMP_VOL    9   /* set ramp volume parameter */
+#define SCUX_IOCTL_SET_ZEROCROSS_MUTE  10  /* set zerocross mute paramter */
+#define SCUX_IOCTL_SET_STOP_MUTE       11  /* set mute stop */
+#define SCUX_IOCTL_SET_MIX_CFG         12  /* set MIX parameter */
+#define SCUX_IOCTL_SET_MIX_VOL         13  /* set MIX volume parameter */
+#define SCUX_IOCTL_SET_SSIF_CFG        14  /* set SSIF parameter */
+#define SCUX_IOCTL_GET_WRITE_STAT      15  /* get write status */
+#define SCUX_IOCTL_GET_READ_STAT       16  /* get read status */
+#define SCUX_IOCTL_GET_DVU_STAT        17  /* get DVU status */
+#define SCUX_IOCTL_GET_MUTE_STAT       18  /* get MUTE status */
+#define SCUX_IOCTL_GET_MIX_STAT        19  /* get MIX status */
+#define SCUX_IOCTL_MAX                 20
+
+#if(1) /* mbed */
+#else  /* not mbed */
+/* SCUX status */
+#define SCUX_STAT_STOP    0  /* request regstration isn't start */
+#define SCUX_STAT_IDLE    1  /* request isn't receied */
+#define SCUX_STAT_TRANS   2  /* under data transfer execution */
+#endif /* end mbed */
+
+/* DVU status */
+#define SCUX_DVU_STAT_MUTE          0  /* DVU volume is mute */
+#define SCUX_DVU_STAT_RAMP_DOWN     1  /* DVU volume is ramp down */
+#define SCUX_DVU_STAT_RAMP_UP       2  /* DVU volume is ramp up */
+#define SCUX_DVU_STAT_RAMP_FIXED    3  /* DVU volume change is stop */
+#define SCUX_DVU_STAT_ORIGINAL_SIZE 4  /* DVU volume is original size */
+
+/* MIX status */
+#define SCUX_MIX_STAT_RAMP_FIXED  0  /* MIX volume change is stop */
+#define SCUX_MIX_STAT_RAMP_DOWN   1  /* MIX volume is ramp down */
+#define SCUX_MIX_STAT_RAMP_UP     2  /* MIX volume is ramp up */
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+
+/* SSIF channel synchronous setting */
+typedef struct
+{
+    scux_ssif_ch_num_t     ssif_ch_num;       /* ssif channel number */
+    scux_pin_mode_t        pin_mode;          /* SSIF sync setting */
+} scux_ssif_pin_mode_t;
+
+/* SSIF AUDIO_CLK source parameters */
+typedef struct
+{
+    scux_ssif_ch_num_t     ssif_ch_num;       /* ssif channel number */
+    scux_src_clk_source_t  pin_clk;           /* AUDIO_CLK source */
+} scux_ssif_pin_clk_t;
+
+/* SSIF parameters */
+typedef struct
+{
+    scux_ssif_ch_num_t     ssif_ch_num;       /* ssif channel number */
+    bool_t                 mode_master;       /* master mode / slave mode select */
+    bool_t                 select_audio_clk;  /* AUDIO_X1 / AUDIO_CLK select */
+    scux_ssif_system_len_t system_word;       /* system word length */
+    bool_t                 sck_polarity_rise; /* SCK polarity type select */
+    bool_t                 ws_polarity_high;  /* WS polarity type select */
+    bool_t                 padding_high;      /* padding type select */
+    bool_t                 serial_data_align; /* serial data alingment type select */
+    bool_t                 ws_delay;          /* WS delay type select */
+    bool_t                 use_noise_cancel;  /* noise cancel ON / OFF select */
+    bool_t                 use_tdm;           /* TDM mode ON / OFF select */
+} scux_ssif_cfg_t;
+
+/* MIX parameters */
+typedef struct
+{
+    bool_t               mixmode_ramp;                          /* ramp mode / step mpde select */
+    scux_mix_ramp_time_t up_period;                             /* ramp up period */
+    scux_mix_ramp_time_t down_period;                           /* ramp down period */
+    uint32_t             mix_vol[SCUX_CH_NUM];                  /* MIX volume value */
+    scux_audio_channel_t select_out_data_ch[SCUX_AUDIO_CH_MAX]; /* audio data position setting */
+} scux_mix_cfg_t;
+
+/* zerocross mute parameters */
+typedef struct
+{
+    bool_t               zc_mute_enable[SCUX_AUDIO_CH_MAX];     /* zerocross mute enable setting */
+    void                 (*pcallback[SCUX_AUDIO_CH_MAX])(void); /* callback pointer for zerocross */
+} scux_zc_mute_t;
+
+/* ramp volume parameters */
+typedef struct
+{
+    bool_t               ramp_vol_enable[SCUX_AUDIO_CH_MAX];  /* ramp volume enable setting */
+    scux_dvu_ramp_time_t up_period;                           /* ramp up period */
+    scux_dvu_ramp_time_t down_period;                         /* ramp down period */
+    uint32_t             ramp_vol;                            /* ramp volume value */
+    uint32_t             ramp_wait_time;                      /* wait time for volume change */
+} scux_dvu_ramp_vol_t;
+
+/* digital volume parameters */
+typedef struct
+{
+    bool_t               digi_vol_enable;             /* digital volume enable setting */
+    uint32_t             digi_vol[SCUX_AUDIO_CH_MAX]; /* digital volume value */
+} scux_dvu_digi_vol_t;
+
+/* DVU parameters */
+typedef struct
+{
+    bool_t               dvu_enable;          /* DVU enable setting */
+    scux_dvu_digi_vol_t  dvu_digi_vol;        /* digital volume setting */
+    scux_dvu_ramp_vol_t  dvu_ramp_vol;        /* ramp volume setting */
+    scux_zc_mute_t       dvu_zc_mute;         /* zerocross mute setting */
+} scux_dvu_cfg_t;
+
+/* SRC parameters */
+typedef struct
+{
+    bool_t                src_enable;          /* SRC enable setting */
+    scux_use_channel_t    use_ch;              /* used data channel setting */
+    scux_data_word_len_t  word_len;            /* used word length setting */
+    bool_t                mode_sync;           /* sync mode/async mode select */
+    scux_src_sync_rate_t  input_rate_sync;     /* input rate on sync mode */
+    scux_src_clk_source_t input_clk_async;      /* input clock source on async mode */
+    uint32_t              input_div_async;     /* input divide rate on async mode */
+    scux_src_sync_rate_t  output_rate_sync;    /* output rate on sync mode */
+    scux_src_clk_source_t output_clk_async;    /* output clock source on async mode */
+    uint32_t              output_div_async;    /* output divide rate on async mode */
+    uint32_t              input_ws;            /* input WS frequency */
+    uint32_t              output_ws;           /* output WS frequency */
+    uint32_t              freq_tioc3a;         /* frequency of TIOC3A */
+    uint32_t              freq_tioc4a;         /* frequency of TIOC4A */
+    scux_src_delay_mode_t delay_mode;          /* delay mode setting */
+    uint32_t              wait_sample;         /* wait time setting */
+    uint8_t               min_rate_percentage; /* minimum rate setting */
+    scux_audio_channel_t  select_in_data_ch[SCUX_AUDIO_CH_MAX]; /* audio data position setting */
+} scux_src_cfg_t;
+
+/* SCUX setup parameter */
+typedef struct
+{
+    bool_t           enabled;               /* channel used flag */
+    uint8_t          int_level;             /* interrupt priority */
+    scux_route_t     route;                 /* reoute setting */
+    scux_src_cfg_t   src_cfg;               /* SRC parameters */
+} scux_channel_cfg_t;
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+#if(1) /* mbed */
+extern void *R_SCUX_InitOne(const int_t channel, const void * const p_config_data, int32_t * const p_errno);
+extern int_t R_SCUX_UnInitOne(const int_t channel, const void * const p_driver_instance, int32_t * const p_errno);
+extern int_t R_SCUX_Open(void * const p_driver_instance, const char_t * const p_path_name, const int_t flags, const int_t mode, int32_t * const p_errno);
+extern int_t R_SCUX_Close(void * const p_fd, int32_t * const p_errno);
+extern int_t R_SCUX_Ioctl(void * const p_fd, const int_t request, void * const p_buf, int32_t * const p_errno);
+extern int_t R_SCUX_WriteAsync(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno);
+extern int_t R_SCUX_ReadAsync(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno);
+extern int_t R_SCUX_Cancel(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno);
+#else  /* not mbed */
+IOIF_DRV_API* R_SCUX_MakeCbTbl(void);
+#endif /* end mbed */
+
+extern uint16_t R_SCUX_GetVersion(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* SCUX_IF_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_src/scux/scux.c	Fri Oct 02 03:03:25 2015 +0000
@@ -0,0 +1,2592 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         scux.c
+* $Rev: 1674 $
+* $Date:: 2015-05-29 16:35:57 +0900#$
+* @brief        SCUX Driver functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+
+#include "scux.h"
+
+#if(1) /* mbed */
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define INIT_WAIT_TIME_MSEC (1)
+#define INIT_WAIT_NUM       (1000U)
+
+#endif /* end mbed */
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/* ->MISRA 8.8 This description is based on the way to fill out OS defined. */
+/* ->IPA M2.2.2, MISRA 8.10 This description is based on the way to fill out OS defined. */
+osSemaphoreDef(scux_ch0_access);
+osSemaphoreDef(scux_ch1_access);
+osSemaphoreDef(scux_ch2_access);
+osSemaphoreDef(scux_ch3_access);
+
+osSemaphoreDef(scux_ssif_ch0_access);
+osSemaphoreDef(scux_ssif_ch1_access);
+osSemaphoreDef(scux_ssif_ch2_access);
+osSemaphoreDef(scux_ssif_ch3_access);
+osSemaphoreDef(scux_ssif_ch4_access);
+osSemaphoreDef(scux_ssif_ch5_access);
+
+osSemaphoreDef(scux_shared_access);
+/* <-MISRA 8.10, IPA M2.2.2 */
+/* <-MISRA 8.8 */
+
+/******************************************************************************
+Private global driver management information
+******************************************************************************/
+
+/* driver management infrmation */
+static scux_info_drv_t gb_scux_info_drv = {
+    SCUX_DRV_UNINIT,
+    {
+        {SCUX_CH_0, false, 0, SCUX_CH_UNINIT}, /* ch0 */
+        {SCUX_CH_1, false, 0, SCUX_CH_UNINIT}, /* ch1 */
+        {SCUX_CH_2, false, 0, SCUX_CH_UNINIT}, /* ch2 */
+        {SCUX_CH_3, false, 0, SCUX_CH_UNINIT}  /* ch3 */
+    }
+};
+
+/* SSIF management information */
+static scux_ssif_info_t gb_scux_ssif_info[SCUX_SSIF_CH_NUM];
+
+/* ->MISRA 11.3, 11.4 11.5 This cast is needed for register access. */
+/* address table of register set for each SCUX channel */
+static scux_reg_info_t p_scux_ch_reg_addr_table[SCUX_CH_NUM] = {
+    {
+        &SCUX_FROM_DVUIR_DVU0_0,
+        &SCUX_FROM_SRCIR0_2SRC0_0, 
+        &SCUX_FROM_FFUIR_FFU0_0, 
+        &SCUX_FROM_FFDIR_FFD0_0, 
+        &SCUX_FROM_OPCIR_OPC0_0, 
+        &SCUX_FROM_IPCIR_IPC0_0,
+        &SCUXMIXIR_MIX0_0,
+        &SCUXMADIR_MIX0_0,
+        &SCUXMIXBR_MIX0_0,
+        &SCUXMIXMR_MIX0_0,
+        &SCUXMVPDR_MIX0_0,
+        &SCUXMDBAR_MIX0_0,
+        &SCUXMDBER_MIX0_0,
+        &SCUXMIXSR_MIX0_0,
+        &SCUXSWRSR_CIM,
+        &SCUXDMACR_CIM,
+        &SCUXDMATD0_CIM,
+        &SCUXDMATU0_CIM,
+        &SCUXSSIRSEL_CIM,
+        &SCUXFDTSEL0_CIM,
+        &SCUXFUTSEL0_CIM,
+        &SCUXSSIPMD_CIM,
+        &SCUXSSICTRL_CIM,
+        &SCUXSRCRSEL0_CIM,
+        &SCUXMIXRSEL_CIM
+    },
+    {
+        &SCUX_FROM_DVUIR_DVU0_1, 
+        &SCUX_FROM_SRCIR0_2SRC0_0, 
+        &SCUX_FROM_FFUIR_FFU0_1, 
+        &SCUX_FROM_FFDIR_FFD0_1, 
+        &SCUX_FROM_OPCIR_OPC0_1, 
+        &SCUX_FROM_IPCIR_IPC0_1,
+        &SCUXMIXIR_MIX0_0,
+        &SCUXMADIR_MIX0_0,
+        &SCUXMIXBR_MIX0_0,
+        &SCUXMIXMR_MIX0_0,
+        &SCUXMVPDR_MIX0_0,
+        &SCUXMDBBR_MIX0_0,
+        &SCUXMDBER_MIX0_0,
+        &SCUXMIXSR_MIX0_0,
+        &SCUXSWRSR_CIM,
+        &SCUXDMACR_CIM,
+        &SCUXDMATD1_CIM,
+        &SCUXDMATU1_CIM,
+        &SCUXSSIRSEL_CIM,
+        &SCUXFDTSEL1_CIM,
+        &SCUXFUTSEL1_CIM,
+        &SCUXSSIPMD_CIM,
+        &SCUXSSICTRL_CIM,
+        &SCUXSRCRSEL1_CIM,
+        &SCUXMIXRSEL_CIM
+    },
+    {
+        &SCUX_FROM_DVUIR_DVU0_2, 
+        &SCUX_FROM_SRCIR0_2SRC0_1, 
+        &SCUX_FROM_FFUIR_FFU0_2, 
+        &SCUX_FROM_FFDIR_FFD0_2, 
+        &SCUX_FROM_OPCIR_OPC0_2, 
+        &SCUX_FROM_IPCIR_IPC0_2,
+        &SCUXMIXIR_MIX0_0,
+        &SCUXMADIR_MIX0_0,
+        &SCUXMIXBR_MIX0_0,
+        &SCUXMIXMR_MIX0_0,
+        &SCUXMVPDR_MIX0_0,
+        &SCUXMDBCR_MIX0_0,
+        &SCUXMDBER_MIX0_0,
+        &SCUXMIXSR_MIX0_0,
+        &SCUXSWRSR_CIM,
+        &SCUXDMACR_CIM,
+        &SCUXDMATD2_CIM,
+        &SCUXDMATU2_CIM,
+        &SCUXSSIRSEL_CIM,
+        &SCUXFDTSEL2_CIM,
+        &SCUXFUTSEL2_CIM,
+        &SCUXSSIPMD_CIM,
+        &SCUXSSICTRL_CIM,
+        &SCUXSRCRSEL2_CIM,
+        &SCUXMIXRSEL_CIM
+    },
+    {
+        &SCUX_FROM_DVUIR_DVU0_3, 
+        &SCUX_FROM_SRCIR0_2SRC0_1, 
+        &SCUX_FROM_FFUIR_FFU0_3, 
+        &SCUX_FROM_FFDIR_FFD0_3, 
+        &SCUX_FROM_OPCIR_OPC0_3, 
+        &SCUX_FROM_IPCIR_IPC0_3,
+        &SCUXMIXIR_MIX0_0,
+        &SCUXMADIR_MIX0_0,
+        &SCUXMIXBR_MIX0_0,
+        &SCUXMIXMR_MIX0_0,
+        &SCUXMVPDR_MIX0_0,
+        &SCUXMDBDR_MIX0_0,
+        &SCUXMDBER_MIX0_0,
+        &SCUXMIXSR_MIX0_0,
+        &SCUXSWRSR_CIM,
+        &SCUXDMACR_CIM,
+        &SCUXDMATD3_CIM,
+        &SCUXDMATU3_CIM,
+        &SCUXSSIRSEL_CIM,
+        &SCUXFDTSEL3_CIM,
+        &SCUXFUTSEL3_CIM,
+        &SCUXSSIPMD_CIM,
+        &SCUXSSICTRL_CIM,
+        &SCUXSRCRSEL3_CIM,
+        &SCUXMIXRSEL_CIM
+    }
+};
+/* <-MISRA 11.3, 11.4 11.5 */
+    
+/* ->MISRA 11.3 This cast is needed for register access. */
+/* address table of register set for each SSIF channel */
+static volatile struct st_ssif * const p_scux_ssif_ch_reg_addr[SCUX_SSIF_CH_NUM] = 
+{ 
+    &SSIF0,
+    &SSIF1,
+    &SSIF2,
+    &SSIF3,
+    &SSIF4,
+    &SSIF5
+};
+/* <-MISRA 11.3 */
+    
+/* SCUX semaphore table define */
+static const osSemaphoreDef_t * const p_semdef_ch_scux_access[SCUX_CH_NUM] = 
+{ 
+    osSemaphore(scux_ch0_access),
+    osSemaphore(scux_ch1_access),
+    osSemaphore(scux_ch2_access),
+    osSemaphore(scux_ch3_access)
+};
+    
+/* SSIF semaphore table define */
+static const osSemaphoreDef_t * const p_semdef_ch_scux_ssif_access[SCUX_SSIF_CH_NUM] = 
+{ 
+    osSemaphore(scux_ssif_ch0_access),
+    osSemaphore(scux_ssif_ch1_access),
+    osSemaphore(scux_ssif_ch2_access),
+    osSemaphore(scux_ssif_ch3_access),
+    osSemaphore(scux_ssif_ch4_access),
+    osSemaphore(scux_ssif_ch5_access)
+};
+
+/* write DMA resource define */
+static const dma_res_select_t gb_dma_res_select_tx[SCUX_CH_NUM] =
+{
+    DMA_RS_SCUTXI0,
+    DMA_RS_SCUTXI1,
+    DMA_RS_SCUTXI2,
+    DMA_RS_SCUTXI3
+};
+   
+/* read DMA resource define */
+static const dma_res_select_t gb_dma_res_select_rx[SCUX_CH_NUM] =
+{
+    DMA_RS_SCURXI0,
+    DMA_RS_SCURXI1,
+    DMA_RS_SCURXI2,
+    DMA_RS_SCURXI3
+}; 
+
+/* write dummy data buffer */
+static uint8_t gb_scux_write_dummy_buf[SCUX_DUMMY_BUF_SIZE];
+   
+/* read dummy data buffer */
+static uint8_t gb_scux_read_dummy_buf[SCUX_DUMMY_BUF_SIZE];
+
+/******************************************************************************
+ Function prototypes
+******************************************************************************/
+ 
+static int_t SCUX_CheckSrcParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT]);
+static int_t SCUX_CheckDvuParam(const scux_info_ch_t * const p_scux_info_ch);
+static int_t SCUX_CheckSsifParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT], const bool_t use_mix_flag);
+static int_t SCUX_CheckMixParam(const scux_info_ch_t * const p_scux_info_ch);
+#if(1) /* mbed */
+static int_t SCUX_CmnUnInitialize(void);
+#endif /* end mbed */
+
+/**************************************************************************//**
+* Function Name: SCUX_GetDrvInstance
+* @brief         Get pointer of gb_scux_info_drv.
+*
+*                Description:<br>
+*                
+* @param         None. 
+* @retval        pointer of gb_scux_info_drv -
+*                  driver instance.
+******************************************************************************/
+
+scux_info_drv_t *SCUX_GetDrvInstance(void)
+{
+    
+    return &gb_scux_info_drv;
+}
+
+/******************************************************************************
+End of function SCUX_GetDrv_Instance
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_GetDrvChInfo
+* @brief         gb_scux_info_drv.info_ch[channel].
+*
+*                Description:<br>
+*                
+* @param[in]     channel information number. 
+* @retval        pointer of gb_scux_info_drv -
+*                  pointer of channel information.
+******************************************************************************/
+
+scux_info_ch_t *SCUX_GetDrvChInfo(const int_t channel)
+{
+    
+    return &gb_scux_info_drv.info_ch[channel];
+}
+
+/******************************************************************************
+End of function SCUX_GetDrvChInfo
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_GetSsifChInfo
+* @brief         gb_scux_ssif_info.channel.
+*
+*                Description:<br>
+*                
+* @param[in]     SSIF channel number. 
+* @retval        pointer of gb_scux_ssif_info -
+*                  pointer of SSIF information.
+******************************************************************************/
+
+scux_ssif_info_t *SCUX_GetSsifChInfo(const int_t channel)
+{
+    
+    return &gb_scux_ssif_info[channel];
+}
+
+/******************************************************************************
+End of function SCUX_GetSsifChInfo
+******************************************************************************/
+
+#if(1) /* mbed */
+/**************************************************************************//**
+* Function Name: SCUX_InitializeOne
+* @brief         Init SCUX driver.
+*
+*                Description:<br>
+*                
+* @param[in]     channel    :initialize channel number.
+* @param[in]     p_scux_init_param :Initialize parameter for SCUX. 
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+*                    error code -
+*                       ENOMEM : Making semaphore is failed.
+*                       EFAULT : Internal error is occured.
+******************************************************************************/
+#else  /* not mbed */
+/**************************************************************************//**
+* Function Name: SCUX_Initialize
+* @brief         Init SCUX driver.
+*
+*                Description:<br>
+*                
+* @param[in]     p_scux_init_param :Initialize parameter for SCUX. 
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+*                    error code -
+*                       ENOMEM : Making semaphore is failed.
+*                       EFAULT : Internal error is occured.
+******************************************************************************/
+#endif /* end mbed */
+#if(1) /* mbed */
+int_t SCUX_InitializeOne(const int_t channel, const scux_channel_cfg_t * const p_scux_init_param)
+#else  /* not mbed */
+int_t SCUX_Initialize(const scux_channel_cfg_t * const p_scux_init_param)
+#endif /* end mbed */
+{
+    int_t    retval = ESUCCESS;
+    osStatus sem_ercd;
+    int_t    scux_ch_count;
+    int_t    audio_ch_count;
+    scux_ssif_ch_num_t    ssif_ch_count;
+    uint32_t cpg_value;
+    bool_t   init_shared_flag = false;
+    int_t    was_masked;
+    volatile uint8_t dummy_buf;
+#if(1) /* mbed */
+    uint32_t scux_init_count;
+    int_t    uninit_ercd;
+    bool_t   init_start_flag = false;
+    bool_t   uninit_all_flag = false;
+    uint32_t i;
+#endif /* end mbed */
+
+    if (NULL == p_scux_init_param)
+    {
+        retval = EFAULT;
+    }
+#if(1) /* mbed */
+    else if (false == p_scux_init_param->enabled)
+    {
+        retval = EFAULT;
+    }
+#endif /* end mbed */
+    else
+    {
+        /* init channel management information */
+#if(1) /* mbed */
+        scux_ch_count = channel;
+
+        for (i = 0; ((i < INIT_WAIT_NUM) && (false == init_start_flag)); i++)
+        {
+            was_masked = __disable_irq();
+
+            if (SCUX_DRV_INIT == gb_scux_info_drv.drv_stat)
+            {
+                /* already scux driver shared information is initialized */
+                init_shared_flag = true;
+
+                /* enable the channel */
+                gb_scux_info_drv.info_ch[scux_ch_count].enabled = true;
+
+                init_start_flag = true;
+            }
+            else if (SCUX_DRV_UNINIT == gb_scux_info_drv.drv_stat)
+            {
+                /* change the status to scux initialization running */
+                gb_scux_info_drv.drv_stat = SCUX_DRV_INIT_RUNNING;
+
+                for (scux_init_count = SCUX_CH_0; scux_init_count < SCUX_CH_NUM; scux_init_count++)
+                {
+                    gb_scux_info_drv.info_ch[scux_init_count].enabled = false;
+                    gb_scux_info_drv.info_ch[scux_init_count].ch_stat = SCUX_CH_UNINIT;
+
+                    gb_scux_info_drv.info_ch[scux_init_count].sem_ch_scux_access = NULL;
+                }
+
+                for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
+                {
+                    gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = NULL;
+                }
+
+                gb_scux_info_drv.shared_info.sem_shared_access = NULL;
+
+                /* enable the channel */
+                gb_scux_info_drv.info_ch[scux_ch_count].enabled = true;
+
+                init_start_flag = true;
+            }
+            else
+            {
+                /* do nothing : SCUX_DRV_INIT_RUNNING */
+            }
+
+            if (0 == was_masked)
+            {
+                __enable_irq();
+            }
+
+            if (false == init_start_flag)
+            {
+                /* wait for the change of drv_stat to SCUX_DRV_INIT */
+                (void)osDelay(INIT_WAIT_TIME_MSEC);
+            }
+        }
+
+        if (false == init_start_flag)
+        {
+            retval = EFAULT;
+        }
+        else
+        {
+#else  /* not mbed */
+        for (scux_ch_count = 0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
+        {
+            if (false == p_scux_init_param[scux_ch_count].enabled)
+            {
+                /* set disable parameter */
+                gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
+                gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
+            }
+            else
+#endif /* end mbed */
+            {
+#if(1) /* mbed */
+#else  /* not mbed */
+                gb_scux_info_drv.info_ch[scux_ch_count].enabled = true;
+#endif /* end mbed */
+    
+                /* copy parameter */
+                /* set interrupt parameter */
+#if(1) /* mbed */
+                gb_scux_info_drv.info_ch[scux_ch_count].int_level = p_scux_init_param->int_level;
+#else  /* not mbed */
+                gb_scux_info_drv.info_ch[scux_ch_count].int_level = p_scux_init_param[scux_ch_count].int_level;
+#endif /* end mbed */
+                        
+                /* set route parameter */
+#if(1) /* mbed */
+                gb_scux_info_drv.info_ch[scux_ch_count].route_set = p_scux_init_param->route;
+#else  /* not mbed */
+                gb_scux_info_drv.info_ch[scux_ch_count].route_set = p_scux_init_param[scux_ch_count].route;
+#endif /* end mbed */
+                
+                /* set SRC paramter */
+#if(1) /* mbed */
+                SCUX_IoctlSetSrcCfg(scux_ch_count, &p_scux_init_param->src_cfg);
+#else  /* not mbed */
+                SCUX_IoctlSetSrcCfg(scux_ch_count, &p_scux_init_param[scux_ch_count].src_cfg);
+#endif /* end mbed */
+                
+                /* init SCUX parameter */
+                if ((SCUX_CH_0 == scux_ch_count) || (SCUX_CH_1 == scux_ch_count))
+                {
+                    gb_scux_info_drv.info_ch[scux_ch_count].fifo_size = SCUX_FIFO_SIZE_CH0_1;
+                }
+                else
+                {
+                    gb_scux_info_drv.info_ch[scux_ch_count].fifo_size = SCUX_FIFO_SIZE_CH2_3;
+                }
+                gb_scux_info_drv.info_ch[scux_ch_count].dma_resource_tx = gb_dma_res_select_tx[scux_ch_count];
+                gb_scux_info_drv.info_ch[scux_ch_count].dma_resource_rx = gb_dma_res_select_rx[scux_ch_count];
+                gb_scux_info_drv.info_ch[scux_ch_count].futsel_cim_value = FUTSEL_CIM_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].err_stat_backup = ESUCCESS;
+                
+                /* init DVU parameter */
+                for (audio_ch_count = SCUX_AUDIO_CH_0; audio_ch_count < SCUX_AUDIO_CH_MAX; audio_ch_count++)
+                {
+                    gb_scux_info_drv.info_ch[scux_ch_count].dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch_count] = false; 
+                }
+                gb_scux_info_drv.info_ch[scux_ch_count].dvu_setup = false;
+             
+                if (false == init_shared_flag)
+                {
+                    /* init MIX parameter */
+                    gb_scux_info_drv.shared_info.mix_setup = false;
+                    gb_scux_info_drv.shared_info.mix_run_ch = 0U;
+                    gb_scux_info_drv.shared_info.mix_ssif_ch = 0U;
+                    
+                    /* init SSIF parameter */
+                    for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
+                    {
+                        gb_scux_ssif_info[ssif_ch_count].ssif_setup = false;
+                        gb_scux_ssif_info[ssif_ch_count].ssif_cfg.ssif_ch_num = ssif_ch_count;
+                        gb_scux_ssif_info[ssif_ch_count].scux_channel = 0;
+                        gb_scux_ssif_info[ssif_ch_count].pin_mode = SCUX_PIN_MODE_INDEPEND;
+                    }
+                    
+                    /* init regsiter store value */
+                    gb_scux_info_drv.shared_info.ssictrl_cim_value = SSICTRL_CIM_INIT_VALUE;
+                }
+            
+                /* set register address */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg = &p_scux_ch_reg_addr_table[scux_ch_count];
+                                       
+                if (false == init_shared_flag) {
+#if defined (__ICCARM__)
+                    was_masked = __disable_irq_iar();
+#else
+                    was_masked = __disable_irq();
+#endif
+
+                    /* supply clock for SCUX */
+                    cpg_value = (uint32_t)CPG.STBCR8 & ~(CPG_STBCR8_BIT_MSTP81);
+                    CPG.STBCR8 = (uint8_t)cpg_value;
+                    dummy_buf = CPG.STBCR8;
+                    
+                    if (0 == was_masked)
+                    {
+                        __enable_irq();
+                    }
+
+                    /* software reset */
+                    SCUX.SWRSR_CIM &= ~SWRSR_CIM_SWRST_SET;
+                    SCUX.SWRSR_CIM |= SWRSR_CIM_SWRST_SET;
+                }
+                
+                /* init DVU register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 = DVUIR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = VADIR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 = DVUBR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 = DVUCR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 = ZCMCR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = VRCTR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = VRPDR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = VRDBR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = VRWTR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL0R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL1R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL2R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL3R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL4R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL5R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL6R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL7R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUER_DVU0_0 = DVUER_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = VEVMR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VEVCR_DVU0_0 = VEVCR_DVU0_INIT_VALUE;
+                
+                /* init SRC register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SADIR0_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSCR0_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSVR0_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCCR0_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->MNFSR0_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->BFSSR0_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR0_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SADIR1_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSCR1_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSVR1_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCCR1_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->MNFSR1_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->BFSSR1_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 = SRCIRR_2SRC0_INIT_VALUE;
+                
+                /* init FFU register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 = FFUIR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FUAIR_FFU0_0 = FUAIR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->URQSR_FFU0_0 = URQSR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 = UEVMR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = UEVCR_FFU0_INIT_VALUE;
+                
+                /* init FFD register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 = FFDIR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FDAIR_FFD0_0 = FDAIR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DRQSR_FFD0_0 = DRQSR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 = FFDBR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = DEVMR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE;
+                
+                /* init OPC register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_opc_reg->OPCIR_OPC0_0 = OPCIR_OPC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC0_INIT_VALUE;
+    
+                /* init IPC register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 = IPCIR_IPC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC0_INIT_VALUE;
+    
+                /* init MIX register for each channel */
+                *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mdb_n_r_mix0_0) = MDB_N_R_MIX0_0_INIT_VALUE;
+                
+                /* init CIM register for each channel */
+                *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->fdtsel_n_cim) = FDTSEL_CIM_INIT_VALUE;
+                *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->futsel_n_cim) = FUTSEL_CIM_INIT_VALUE;
+                *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->srcrsel_n_cim) = SRCRSEL_CIM_INIT_VALUE;
+                
+                /* init shared register */
+                if (false == init_shared_flag)
+                {
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixir_mix0_0) = MIXIR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->madir_mix0_0) = MADIR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixbr_mix0_0) = MIXBR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixmr_mix0_0) = MIXMR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mvpdr_mix0_0) = MVPDR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mdber_mix0_0) = MDBER_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->dmacr_cim) = DMACR_CIM_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssirsel_cim) = SSIRSEL_CIM_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssipmd_cim) = SSIPMD_CIM_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssictrl_cim) = SSICTRL_CIM_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixrsel_cim) = MIXRSEL_CIM_INIT_VALUE;
+                }
+                
+                if (false == init_shared_flag)
+                {
+                    /* set SSIF register */
+                    for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
+                    {
+                        gb_scux_ssif_info[ssif_ch_count].p_scux_ssif_reg = p_scux_ssif_ch_reg_addr[ssif_ch_count];
+                    }
+                }
+            
+                /* set  semaphore parameter */
+                gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = osSemaphoreCreate(p_semdef_ch_scux_access[scux_ch_count], 1);
+                if (NULL == gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access)
+                {
+                     retval = ENOMEM;
+                }
+                if ((ESUCCESS == retval) && (false == init_shared_flag))
+                {
+                    for (ssif_ch_count = SCUX_SSIF_CH_0; ((ssif_ch_count < SCUX_SSIF_CH_NUM) && (ESUCCESS == retval)); ssif_ch_count++) 
+                    {
+                        gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = osSemaphoreCreate(p_semdef_ch_scux_ssif_access[ssif_ch_count], 1);
+                        if (NULL == gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access)
+                        {
+                            retval = ENOMEM;
+                        }
+                    }
+                }
+                if ((ESUCCESS == retval) && (false == init_shared_flag))
+                {
+                    gb_scux_info_drv.shared_info.sem_shared_access = osSemaphoreCreate(osSemaphore(scux_shared_access), 1);
+                    if (NULL == gb_scux_info_drv.shared_info.sem_shared_access)
+                    {
+                        retval = ENOMEM;
+                    }
+                }
+                
+#if(1) /* mbed */
+#else  /* not mbed */
+                if (false == init_shared_flag)
+                {
+                    init_shared_flag = true;
+                }
+#endif /* end mbed */
+                
+                gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_INIT;
+            }
+
+#if(1) /* mbed */
+            if (ESUCCESS != retval)
+            {
+                /* uninit each resouces */
+                gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
+
+                if (NULL != gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access)
+                {
+                    /* semaphore delete */
+                    sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
+                    /* semaphore error check */
+                    if (osOK != sem_ercd)
+                    {
+                        /* set error return value */
+                        retval = EFAULT;
+                    }
+
+                    gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = NULL;
+                }
+
+                was_masked = __disable_irq();
+
+                gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
+
+                for (i = SCUX_CH_0; i < SCUX_CH_NUM; i++)
+                {
+                    if (false != gb_scux_info_drv.info_ch[i].enabled)
+                    {
+                        break;
+                    }
+                }
+
+                if (SCUX_CH_NUM == i)
+                {
+                    gb_scux_info_drv.drv_stat = SCUX_DRV_INIT_RUNNING;
+                    uninit_all_flag = true;
+                }
+
+                if (0 == was_masked)
+                {
+                    __enable_irq();
+                }
+
+                if (false != uninit_all_flag)
+                {
+                    /* uninitialize driver infomation */
+                    uninit_ercd = SCUX_CmnUnInitialize();
+                    if (ESUCCESS != uninit_ercd)
+                    {
+                        retval = uninit_ercd;
+                    }
+
+                    gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
+                }
+            }
+            else
+            {
+                gb_scux_info_drv.drv_stat = SCUX_DRV_INIT;
+            }
+#endif /* end mbed */
+        }
+    }
+    
+#if(1) /* mbed */
+#else  /* not mbed */
+    if (ESUCCESS != retval)
+    {
+        for (scux_ch_count = SCUX_SSIF_CH_0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
+        {
+            if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
+            {
+                /* semaphore delete */
+                sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
+                /* semaphore error check */
+                if (osOK != sem_ercd)
+                {
+                    /* set error return value */
+                    retval = EFAULT;
+                }
+                
+                gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
+                gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
+            }
+        }
+        
+        for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++) 
+        {
+            sem_ercd = osSemaphoreDelete(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set error return value */
+                retval = EFAULT;
+            }
+        }
+                
+        sem_ercd = osSemaphoreDelete(gb_scux_info_drv.shared_info.sem_shared_access);
+        /* semaphore error check */
+        if (osOK != sem_ercd)
+        {
+            /* set error return value */
+            retval = EFAULT;
+        }
+        
+        gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
+    }
+    else
+    {
+        gb_scux_info_drv.drv_stat = SCUX_DRV_INIT;
+    }
+#endif /* end mbed */
+    
+    return retval;
+}
+
+#if(1) /* mbed */
+/******************************************************************************
+End of function SCUX_InitializeOne
+******************************************************************************/
+#else  /* not mbed */
+/******************************************************************************
+End of function SCUX_Initialize
+******************************************************************************/
+#endif /* end mbed */
+
+#if(1) /* mbed */
+/**************************************************************************//**
+* Function Name: SCUX_UnInitializeOne
+* @brief         Uninit SCUX driver.
+*
+*                Description:<br>
+*                
+* @param[in]     channel    :unInitialize channel number.
+* @retval        None.
+******************************************************************************/
+#else  /* not mbed */
+/**************************************************************************//**
+* Function Name: SCUX_UnInitialize
+* @brief         Uninit SCUX driver.
+*
+*                Description:<br>
+*                
+* @param[in]     None. 
+* @retval        None.
+******************************************************************************/
+#endif /* end mbed */
+#if(1) /* mbed */
+void SCUX_UnInitializeOne(const int_t channel)
+#else  /* not mbed */
+void SCUX_UnInitialize(void)
+#endif /* end mbed */
+{
+    osStatus sem_ercd;
+    int_t    ercd;
+    int_t    scux_ch_count;
+    int_t    ssif_ch_count;
+#if(1) /* mbed */
+    bool_t   uninit_all_flag = false;
+    uint32_t i;
+#else  /* not mbed */
+    uint32_t cpg_value;
+#endif /* end mbed */
+    int_t    was_masked;
+
+#if(1) /* mbed */
+    scux_ch_count = channel;
+#else  /* not mbed */
+    for (scux_ch_count = 0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
+#endif /* end mbed */
+    {
+        if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
+        {
+            /* check ch_stat whether going transfer */
+            if ((SCUX_CH_UNINIT != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat) && 
+                (SCUX_CH_INIT != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat) &&
+                (SCUX_CH_STOP != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat))
+            {
+                /* The exclusive access control (interrupt disabled) starts */
+#if defined (__ICCARM__)
+                was_masked = __disable_irq_iar();
+#else
+                was_masked = __disable_irq();
+#endif
+
+                /* This exclusive access control ends in the SCUX_IoctlClearStop */
+                /* call the __enable_irq in the SCUX_IoctlClearStop */
+                ercd = SCUX_IoctlClearStop(scux_ch_count, was_masked);
+                if (ESUCCESS != ercd)
+                {
+                    /* NON_NOTICE_ASSERT: SCUX stop failed */
+                }
+                
+                ercd = R_DMA_Free(gb_scux_info_drv.info_ch[scux_ch_count].dma_tx_ch, NULL);
+                if (ESUCCESS != ercd)
+                {
+                     /* NON_NOTICE_ASSERT: DMA release failed */
+                }
+            }
+        }
+    }
+    
+#if(1) /* mbed */
+#else  /* not mbed */
+    /* software reset */
+    SCUX.SWRSR_CIM &= ~SWRSR_CIM_SWRST_SET;
+
+    for (scux_ch_count = 0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
+#endif /* end mbed */
+    {
+        if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
+        {
+            if (gb_scux_info_drv.info_ch[scux_ch_count].ch_stat == SCUX_CH_UNINIT)
+            {
+                /* NON_NOTICE_ASSERT: abnormal status */
+            }
+            
+            /* uninit each resouces */
+            gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
+            
+#if(1) /* mbed */
+            if (NULL != gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access)
+            {
+                /* delete each semaphore  */
+                sem_ercd = osSemaphoreRelease(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
+                /* semaphore error check */
+                if (osOK != sem_ercd)
+                {
+                    /* NON_NOTICE_ASSERT: semaphore error */
+                }
+
+                sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
+                /* semaphore error check */
+                if (osOK != sem_ercd)
+                {
+                    /* NON_NOTICE_ASSERT: semaphore error */
+                }
+
+                gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = NULL;
+            }
+#else  /* not mbed */
+            /* delete each semaphore  */
+            sem_ercd = osSemaphoreRelease(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* NON_NOTICE_ASSERT: semaphore error */
+            }
+            
+            sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* NON_NOTICE_ASSERT: semaphore error */
+            }
+            
+            gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = NULL;
+#endif /* end mbed */
+            
+            /* delete queue */
+            ahf_cancelall(&gb_scux_info_drv.info_ch[scux_ch_count].tx_que);
+            ahf_destroy(&gb_scux_info_drv.info_ch[scux_ch_count].tx_que);
+            ahf_cancelall(&gb_scux_info_drv.info_ch[scux_ch_count].rx_que);
+            ahf_destroy(&gb_scux_info_drv.info_ch[scux_ch_count].rx_que);
+        }
+    }
+
+#if(1) /* mbed */
+    was_masked = __disable_irq();
+
+    gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
+
+    for (i = SCUX_CH_0; i < SCUX_CH_NUM; i++)
+    {
+        if (false != gb_scux_info_drv.info_ch[i].enabled)
+        {
+            break;
+        }
+    }
+
+    if (SCUX_CH_NUM == i)
+    {
+        if (SCUX_DRV_INIT == gb_scux_info_drv.drv_stat)
+        {
+            gb_scux_info_drv.drv_stat = SCUX_DRV_INIT_RUNNING;
+            uninit_all_flag = true;
+        }
+    }
+
+    if (0 == was_masked)
+    {
+        __enable_irq();
+    }
+
+    if (false != uninit_all_flag)
+    {
+        for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++) 
+        {
+            if (NULL != gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access)
+            {
+                sem_ercd = osSemaphoreRelease(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
+                /* semaphore error check */
+                if (osOK != sem_ercd)
+                {
+                    /* NON_NOTICE_ASSERT: semaphore error */
+                }
+            }
+        }
+
+        if (NULL != gb_scux_info_drv.shared_info.sem_shared_access)
+        {
+            sem_ercd = osSemaphoreRelease(gb_scux_info_drv.shared_info.sem_shared_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* NON_NOTICE_ASSERT: semaphore error */
+            }
+        }
+
+        /* uninitialize driver infomation */
+        (void)SCUX_CmnUnInitialize();
+
+        gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
+    }
+#else  /* not mbed */
+    for (ssif_ch_count = 0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++) 
+    {
+        sem_ercd = osSemaphoreRelease(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
+        /* semaphore error check */
+        if (osOK != sem_ercd)
+        {
+            /* NON_NOTICE_ASSERT: semaphore error */
+        }
+            
+        sem_ercd = osSemaphoreDelete(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
+        /* semaphore error check */
+        if (osOK != sem_ercd)
+        {
+            /* NON_NOTICE_ASSERT: semaphore error */
+        }
+            
+        gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = NULL;
+    }
+            
+    sem_ercd = osSemaphoreRelease(gb_scux_info_drv.shared_info.sem_shared_access);
+    /* semaphore error check */
+    if (osOK != sem_ercd)
+    {
+        /* NON_NOTICE_ASSERT: semaphore error */
+    }
+            
+    sem_ercd = osSemaphoreDelete(gb_scux_info_drv.shared_info.sem_shared_access);
+    /* semaphore error check */
+    if (osOK != sem_ercd)
+    {
+        /* NON_NOTICE_ASSERT: semaphore error */
+    }
+            
+    gb_scux_info_drv.shared_info.sem_shared_access = NULL;
+         
+#if defined (__ICCARM__)
+    was_masked = __disable_irq_iar();
+#else
+    was_masked = __disable_irq();
+#endif
+
+    /* stop clock for SCUX */
+    cpg_value = ((uint32_t)CPG.STBCR8 | CPG_STBCR8_BIT_MSTP81);
+    CPG.STBCR8 = (uint8_t)cpg_value;
+          
+    if (0 == was_masked)
+    {
+        /* enable all irq */
+        __enable_irq();
+    }
+
+    gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
+#endif /* end mbed */
+}
+
+#if(1) /* mbed */
+/******************************************************************************
+End of function SCUX_UnInitializeOne
+******************************************************************************/
+#else  /* not mbed */
+/******************************************************************************
+End of function SCUX_UnInitialize
+******************************************************************************/
+#endif /* end mbed */
+
+/**************************************************************************//**
+* Function Name: SCUX_OpenChannel
+* @brief         Open SCUX driver channel.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:open channel number.
+* @param[in]     flags:specifies the access mode whether the channel is 
+*                      opened for a read or a write
+* @retval        ESUCCESS: Operation successful.
+*                ENOMEM: Create queue is failed.
+*                EMFILE: Allocate DMA ch for write is failed.
+******************************************************************************/
+
+int_t SCUX_OpenChannel(const int_t channel, const int_t flags)
+{
+    int_t    retval;
+    
+    /* create write request queue */
+    retval = ahf_create(&gb_scux_info_drv.info_ch[channel].tx_que, AHF_LOCKINT);
+    if (ESUCCESS != retval)
+    {
+        retval = ENOMEM;
+    }
+    else
+    {
+        /* create read request queue */
+        retval = ahf_create(&gb_scux_info_drv.info_ch[channel].rx_que, AHF_LOCKINT);
+        if (ESUCCESS != retval)
+        {
+            retval = ENOMEM;
+        }
+    }
+    
+    if (ESUCCESS == retval)
+    {
+        SCUX_InterruptInit(channel);
+        
+        /* init channel information parameter */
+        gb_scux_info_drv.info_ch[channel].open_flags = flags;
+        gb_scux_info_drv.info_ch[channel].p_tx_aio = NULL;
+        gb_scux_info_drv.info_ch[channel].p_tx_next_aio = NULL;
+        gb_scux_info_drv.info_ch[channel].p_rx_aio = NULL;
+        gb_scux_info_drv.info_ch[channel].p_rx_next_aio = NULL;
+        gb_scux_info_drv.info_ch[channel].p_ssif_info1 = NULL;
+        gb_scux_info_drv.info_ch[channel].p_ssif_info2 = NULL;
+        gb_scux_info_drv.info_ch[channel].p_ssif_info3 = NULL;
+        gb_scux_info_drv.info_ch[channel].p_flush_callback = NULL;
+        gb_scux_info_drv.info_ch[channel].p_tx_dummy_data = &gb_scux_write_dummy_buf[0];
+        gb_scux_info_drv.info_ch[channel].p_rx_dummy_data = &gb_scux_read_dummy_buf[0];
+        
+        /* get DMA channel for write */
+        gb_scux_info_drv.info_ch[channel].dma_tx_ch = R_DMA_Alloc(DMA_ALLOC_CH, NULL);
+        if (EERROR == gb_scux_info_drv.info_ch[channel].dma_tx_ch)
+        {
+            retval = EMFILE;
+        }
+        else
+        {
+            gb_scux_info_drv.info_ch[channel].ch_stat = SCUX_CH_STOP;
+        }
+
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_OpenChannel
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CloseChannel
+* @brief         Close SCUX driver channel.
+*
+*                Description:<br>
+*                
+* @param[in]     channel: SCUX channel number.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t  SCUX_CloseChannel(const int_t channel)
+{
+    int_t    retval = ESUCCESS;
+    int_t    ercd;
+    int_t    was_masked;
+
+    /* check ch_stat whether going transfer */
+    if ((SCUX_CH_UNINIT != gb_scux_info_drv.info_ch[channel].ch_stat) && 
+        (SCUX_CH_INIT != gb_scux_info_drv.info_ch[channel].ch_stat) &&
+        (SCUX_CH_STOP != gb_scux_info_drv.info_ch[channel].ch_stat))
+    {
+#if defined (__ICCARM__)
+        was_masked = __disable_irq_iar();
+#else
+        was_masked = __disable_irq();
+#endif
+
+        /* This exclusive access control ends in the SCUX_IoctlClearStop */
+        ercd = SCUX_IoctlClearStop(channel, was_masked);
+        if (ESUCCESS != ercd)
+        {
+            retval = EFAULT;
+        }
+    }
+    
+    if (ESUCCESS == retval)
+    {
+        /* delete queue */
+        ahf_cancelall(&gb_scux_info_drv.info_ch[channel].tx_que);
+        ahf_destroy(&gb_scux_info_drv.info_ch[channel].tx_que);
+        ahf_cancelall(&gb_scux_info_drv.info_ch[channel].rx_que);
+        ahf_destroy(&gb_scux_info_drv.info_ch[channel].rx_que);
+
+        SCUX_InterruptUninit(channel);
+        
+        ercd = R_DMA_Free(gb_scux_info_drv.info_ch[channel].dma_tx_ch, NULL);
+        if (ESUCCESS != ercd)
+        {
+            retval = EFAULT;
+        }
+        else
+        {
+            /* reset error status */
+            gb_scux_info_drv.info_ch[channel].err_stat_backup = ESUCCESS;
+            /* set channel status to open */
+            gb_scux_info_drv.info_ch[channel].ch_stat = SCUX_CH_INIT;
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CloseChannel
+******************************************************************************/
+
+
+/**************************************************************************//**
+* Function Name: SCUX_CheckParam
+* @brief         Check SCUX parameter.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch:SCUX channel information.
+* @retval        ESUCCESS : Parameter is no problems.
+*                EACCES : DVU setting isn't performed when DVU is used.
+*                EACCES : MIX setting isn't performed when MIX is used.
+*                EACCES : SSIF setting isn't performed when SSIF is used.
+*                EPERM : Parameter is unexpected value.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_CheckParam(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t retval = ESUCCESS;
+    uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT] = {SCUX_SSIF_NO_USE_CH, SCUX_SSIF_NO_USE_CH, SCUX_SSIF_NO_USE_CH};
+    bool_t use_mix_flag = false;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        /* check route parameter */
+        if (((SCUX_ROUTE_SRC_MEM_MIN >= p_scux_info_ch->route_set) || (SCUX_ROUTE_SRC_MEM_MAX <= p_scux_info_ch->route_set)) &&
+            ((SCUX_ROUTE_SRC_SSIF_MIN >= p_scux_info_ch->route_set) || (SCUX_ROUTE_SRC_SSIF_MAX <= p_scux_info_ch->route_set)) &&
+            ((SCUX_ROUTE_SRC_MIX_SSIF_MIN >= p_scux_info_ch->route_set) || (SCUX_ROUTE_SRC_MIX_SSIF_MAX <= p_scux_info_ch->route_set)))
+        {
+            retval = EPERM;
+        }
+        else
+        {
+            /* check route whether include SCUX channel */
+            switch (p_scux_info_ch->channel)
+            {
+                case SCUX_CH_0:
+                    if ((SCUX_ROUTE_SRC0_MEM != p_scux_info_ch->route_set)         &&
+                        (SCUX_ROUTE_SRC0_SSIF0 != p_scux_info_ch->route_set)       && 
+                        (SCUX_ROUTE_SRC0_MIX_SSIF0 != p_scux_info_ch->route_set)   &&
+                        (SCUX_ROUTE_SRC0_SSIF3 != p_scux_info_ch->route_set)       &&
+                        (SCUX_ROUTE_SRC0_MIX_SSIF3 != p_scux_info_ch->route_set)   &&
+                        (SCUX_ROUTE_SRC0_SSIF012 != p_scux_info_ch->route_set)     &&
+                        (SCUX_ROUTE_SRC0_MIX_SSIF012 != p_scux_info_ch->route_set) &&
+                        (SCUX_ROUTE_SRC0_SSIF345 != p_scux_info_ch->route_set)     &&
+                        (SCUX_ROUTE_SRC0_MIX_SSIF345 != p_scux_info_ch->route_set))
+                    {       
+                        retval = EPERM;
+                    }
+                break;
+                
+                case SCUX_CH_1:
+                    if ((SCUX_ROUTE_SRC1_MEM != p_scux_info_ch->route_set)         &&
+                        (SCUX_ROUTE_SRC1_SSIF0 != p_scux_info_ch->route_set)       && 
+                        (SCUX_ROUTE_SRC1_MIX_SSIF0 != p_scux_info_ch->route_set)   &&
+                        (SCUX_ROUTE_SRC1_SSIF3 != p_scux_info_ch->route_set)       &&
+                        (SCUX_ROUTE_SRC1_MIX_SSIF3 != p_scux_info_ch->route_set)   &&
+                        (SCUX_ROUTE_SRC1_SSIF012 != p_scux_info_ch->route_set)     &&
+                        (SCUX_ROUTE_SRC1_MIX_SSIF012 != p_scux_info_ch->route_set) &&
+                        (SCUX_ROUTE_SRC1_SSIF345 != p_scux_info_ch->route_set)     &&
+                        (SCUX_ROUTE_SRC1_MIX_SSIF345 != p_scux_info_ch->route_set))
+                    {  
+                        retval = EPERM;
+                    }
+                break;
+                
+                case SCUX_CH_2:
+                    if ((SCUX_ROUTE_SRC2_MEM != p_scux_info_ch->route_set)         &&
+                        (SCUX_ROUTE_SRC2_MIX_SSIF0 != p_scux_info_ch->route_set)   && 
+                        (SCUX_ROUTE_SRC2_SSIF1 != p_scux_info_ch->route_set)       &&
+                        (SCUX_ROUTE_SRC2_MIX_SSIF3 != p_scux_info_ch->route_set)   &&
+                        (SCUX_ROUTE_SRC2_SSIF4 != p_scux_info_ch->route_set)       &&
+                        (SCUX_ROUTE_SRC2_MIX_SSIF012 != p_scux_info_ch->route_set) &&
+                        (SCUX_ROUTE_SRC2_MIX_SSIF345 != p_scux_info_ch->route_set))
+                    {  
+                        retval = EPERM;
+                    }
+                break;
+                
+                case SCUX_CH_3:
+                    if ((SCUX_ROUTE_SRC3_MEM != p_scux_info_ch->route_set)          && 
+                        (SCUX_ROUTE_SRC3_MIX_SSIF0 != p_scux_info_ch->route_set)    && 
+                        (SCUX_ROUTE_SRC3_SSIF2 != p_scux_info_ch->route_set)        &&
+                        (SCUX_ROUTE_SRC3_MIX_SSIF3 != p_scux_info_ch->route_set)    &&
+                        (SCUX_ROUTE_SRC3_SSIF5 != p_scux_info_ch->route_set)        &&
+                        (SCUX_ROUTE_SRC3_MIX_SSIF012 != p_scux_info_ch->route_set)  &&
+                        (SCUX_ROUTE_SRC3_MIX_SSIF345 != p_scux_info_ch->route_set))
+                    {  
+                        retval = EPERM;
+                    }
+                break;
+                
+                default :
+                    /* NOTREACHED on At the time of a normal performance */
+                    retval = EFAULT;
+                break;
+                
+            }
+        }
+    
+        if (ESUCCESS == retval)
+        {
+            /* set using SSIF channel and MIX information */
+            switch (p_scux_info_ch->route_set)
+            {
+                case SCUX_ROUTE_SRC0_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC1_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC2_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC3_MEM :
+                    /* do nothing, when mem to mem route is setting */
+                break;
+                
+                case SCUX_ROUTE_SRC0_SSIF0 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
+                break;
+                
+                case SCUX_ROUTE_SRC0_SSIF012 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_1;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_2;
+                break;
+                
+                case SCUX_ROUTE_SRC0_SSIF3 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
+                break;                
+                
+                case SCUX_ROUTE_SRC0_SSIF345 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_4;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_5;
+                break;
+                
+                case SCUX_ROUTE_SRC1_SSIF0 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
+                break;
+                
+                case SCUX_ROUTE_SRC1_SSIF012 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_1;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_2;
+                break;
+                
+                case SCUX_ROUTE_SRC1_SSIF3 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
+                break;                
+                
+                case SCUX_ROUTE_SRC1_SSIF345 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_4;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_5;
+                break;      
+                
+                case SCUX_ROUTE_SRC2_SSIF1 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_1;
+                break;                
+                          
+                case SCUX_ROUTE_SRC2_SSIF4 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_4;
+                break;                
+                
+                case SCUX_ROUTE_SRC3_SSIF2 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_2;
+                break;
+                
+                case SCUX_ROUTE_SRC3_SSIF5 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_5;
+                break;                                
+                
+                case SCUX_ROUTE_SRC0_MIX_SSIF0 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC0_MIX_SSIF012 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC0_MIX_SSIF3 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC0_MIX_SSIF345 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC1_MIX_SSIF0 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC1_MIX_SSIF012 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC1_MIX_SSIF3 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC1_MIX_SSIF345 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC2_MIX_SSIF0 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC2_MIX_SSIF012 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC2_MIX_SSIF3 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC2_MIX_SSIF345 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC3_MIX_SSIF0 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC3_MIX_SSIF012 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC3_MIX_SSIF3 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC3_MIX_SSIF345 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
+                    use_mix_flag = true;
+                break;
+                        
+                default :
+                    /* NOTREACHED on At the time of a normal performance */
+                    retval = EPERM;
+                break;
+            }
+        }
+        
+        if (ESUCCESS == retval) 
+        {
+            if (false != p_scux_info_ch->src_cfg.src_enable)
+            {
+                retval = SCUX_CheckSrcParam(p_scux_info_ch, ssif_ch);
+            }
+            else
+            {
+                if (false != p_scux_info_ch->src_cfg.mode_sync)
+                {
+                    /* src disable is async mode only */
+                    retval = EPERM;
+                }
+            }
+        }
+        
+        if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1])
+        {
+            /* check parameter for SSIF direct route */
+            if ((ESUCCESS == retval) && (false != p_scux_info_ch->dvu_cfg.dvu_enable))
+            {
+                retval = SCUX_CheckDvuParam(p_scux_info_ch);
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                retval = SCUX_CheckSsifParam(p_scux_info_ch, ssif_ch, use_mix_flag);
+            }
+            
+            if ((ESUCCESS == retval) && (false != use_mix_flag))
+            {
+                retval = SCUX_CheckMixParam(p_scux_info_ch);
+            }
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CheckParam
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CheckSrcParam
+* @brief         Check SRC parameter and set rate parameter to SCUX information.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @param[in]     ssif_ch : Used ssif channel number.
+* @param[in]     use_mix_flag : Flag of Using MIX .
+* @retval        ESUCCESS : Parameter is no problems.
+*                EPERM : Parameter is unexpected value.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+static int_t SCUX_CheckSrcParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT])
+{
+    int_t retval = ESUCCESS;
+    uint32_t ssif_arrange_num;
+    uint32_t rate_sample_ratio;
+    uint32_t max_conv_rate;
+    uint32_t min_conv_rate = 0;
+    uint32_t freq_value = 0;
+    int_t audio_ch;
+    uint32_t max_rate;
+    
+    if ((NULL == p_scux_info_ch) || (NULL == ssif_ch))
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        /* check use ch */
+        if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_1 == p_scux_info_ch->channel))
+        {
+            if ((SCUX_USE_CH_1 != p_scux_info_ch->src_cfg.use_ch) && 
+                (SCUX_USE_CH_2 != p_scux_info_ch->src_cfg.use_ch) && 
+                (SCUX_USE_CH_4 != p_scux_info_ch->src_cfg.use_ch) && 
+                (SCUX_USE_CH_6 != p_scux_info_ch->src_cfg.use_ch) && 
+                (SCUX_USE_CH_8 != p_scux_info_ch->src_cfg.use_ch))
+            {
+                retval = EPERM;
+            }
+        }
+        else
+        {
+            /* on SCUX2, SCUX3, enable audio channel is only 1ch and 2ch */
+            if ((SCUX_USE_CH_1 != p_scux_info_ch->src_cfg.use_ch) && (SCUX_USE_CH_2 != p_scux_info_ch->src_cfg.use_ch))
+            {
+                retval = EPERM;
+            }           
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            /* if using SSIF, 1ch audio channel is disabled */
+            if ((SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]) && (SCUX_USE_CH_1 == p_scux_info_ch->src_cfg.use_ch))
+            {
+                retval = EPERM;
+            }
+        }
+            
+        if (ESUCCESS == retval)
+        {
+            /* if  mutiple SSIF channel and enable TDM mode, only 2ch audio channel is enabled */
+            for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
+            {
+                if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
+                {
+                    if (false != gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.use_tdm)
+                    {
+                        if (SCUX_USE_CH_2 == p_scux_info_ch->src_cfg.use_ch)
+                        {
+                            retval = EPERM;
+                        }
+                    }
+                }
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            /* multiple SSIF ch check (multiple SSIF is used SSIF2) */
+            if ((SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]) && (SCUX_USE_CH_6 != p_scux_info_ch->src_cfg.use_ch))
+            {
+                retval = EPERM;
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            /* check word length */
+            if ((SCUX_DATA_LEN_MIN >= p_scux_info_ch->src_cfg.word_len) || (SCUX_DATA_LEN_MAX <= p_scux_info_ch->src_cfg.word_len))
+            {
+                retval = EPERM;
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            /* check delay mode */
+            if ((SCUX_DELAY_MIN >= p_scux_info_ch->src_cfg.delay_mode) || (SCUX_DELAY_MAX <= p_scux_info_ch->src_cfg.delay_mode))
+            {
+                retval = EPERM;
+            }
+            else
+            {
+                /* enable audio channel is less than 2ch when delay mode is enabled */
+                if ((SCUX_DELAY_NORMAL != p_scux_info_ch->src_cfg.delay_mode) && (SCUX_USE_CH_2 < p_scux_info_ch->src_cfg.use_ch))
+                {
+                    retval = EPERM;
+                }
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            /* check rate setting */
+            if (false != p_scux_info_ch->src_cfg.mode_sync)
+            {
+                /* check input rate */
+                if ((SCUX_SYNC_RATE_8      == p_scux_info_ch->src_cfg.input_rate_sync)  ||
+                    (SCUX_SYNC_RATE_11_025  == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_12      == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_16      == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_22_05   == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_24      == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_32      == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_44_1    == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_48      == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_64      == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_88_2    == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_96      == p_scux_info_ch->src_cfg.input_rate_sync))
+                {
+                    /* enable rate is less than 66KHz on 6ch */
+                    if ((SCUX_USE_CH_6 == p_scux_info_ch->src_cfg.use_ch) && 
+                        ((SCUX_SYNC_RATE_88_2 == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                         (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.input_rate_sync)))
+                    {
+                        retval = EPERM;
+                    }
+                    
+                    /* enable rate is less than 49KHz on 8ch */
+                    if ((SCUX_USE_CH_8 == p_scux_info_ch->src_cfg.use_ch) && 
+                        ((SCUX_SYNC_RATE_64 == p_scux_info_ch->src_cfg.input_rate_sync)   ||
+                         (SCUX_SYNC_RATE_88_2 == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                         (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.input_rate_sync)))
+                    {
+                        retval = EPERM;
+                    }
+                }
+                else
+                {
+                    retval = EPERM;
+                }
+                
+                if (ESUCCESS == retval) {
+                    /* check output rate */
+                    if ((SCUX_SYNC_RATE_8   == p_scux_info_ch->src_cfg.output_rate_sync)  ||
+                        (SCUX_SYNC_RATE_16   == p_scux_info_ch->src_cfg.output_rate_sync) ||
+                        (SCUX_SYNC_RATE_24   == p_scux_info_ch->src_cfg.output_rate_sync) ||
+                        (SCUX_SYNC_RATE_32   == p_scux_info_ch->src_cfg.output_rate_sync) ||
+                        (SCUX_SYNC_RATE_44_1 == p_scux_info_ch->src_cfg.output_rate_sync) ||
+                        (SCUX_SYNC_RATE_48   == p_scux_info_ch->src_cfg.output_rate_sync) ||
+                        (SCUX_SYNC_RATE_96   == p_scux_info_ch->src_cfg.output_rate_sync))
+                    {
+                        /* enable rate is less than 66KHz on 6ch, enable rate is less than 49KHz on 8ch  */
+                        if ((SCUX_USE_CH_6 <= p_scux_info_ch->src_cfg.use_ch) && 
+                            (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.output_rate_sync))
+                        {
+                            retval = EPERM;
+                        }
+                    }
+                    else
+                    {
+                        retval = EPERM;
+                    }
+                }
+                
+                if (ESUCCESS == retval)
+                {
+                    p_scux_info_ch->input_rate = p_scux_info_ch->src_cfg.input_rate_sync;
+                    p_scux_info_ch->output_rate = p_scux_info_ch->src_cfg.output_rate_sync;
+                }
+            }
+            else
+            {
+                /* async mode */
+                /* check input rate */
+                /* get input source clock */
+                switch (p_scux_info_ch->src_cfg.input_clk_async)
+                {
+                    case SCUX_CLK_AUDIO_CLK :
+                        freq_value = SCUX_AUDIO_CLK;
+                    break;                  
+                    
+                    case SCUX_CLK_AUDIO_X1 :
+                        freq_value = SCUX_AUDIO_X1;
+                    break;
+                    
+                    case SCUX_CLK_MLB_CLK :
+                        freq_value = SCUX_MLB_CLK;
+                    break;
+    
+                    case SCUX_CLK_USB_X1 :
+                        freq_value = SCUX_USB_X1;
+                    break;
+    
+                    case SCUX_CLK_CLKP1_2 :
+                        freq_value = SCUX_CLKLP1_DIV2;
+                    break;
+    
+                    case SCUX_CLK_MTU_TIOC3A :
+                        freq_value = p_scux_info_ch->src_cfg.freq_tioc3a;
+                        if (0U == freq_value)
+                        {
+                            retval = EPERM;
+                        }
+                    break;
+    
+                    case SCUX_CLK_MTU_TIOC4A :
+                        freq_value = p_scux_info_ch->src_cfg.freq_tioc4a;
+                        if (0U == freq_value)
+                        {
+                            retval = EPERM;
+                        }
+                    break;
+    
+                    case SCUX_CLK_SSIF0_WS :
+                        /* fall through */
+                    case SCUX_CLK_SSIF1_WS :
+                        /* fall through */
+                    case SCUX_CLK_SSIF2_WS :
+                        /* fall through */
+                    case SCUX_CLK_SSIF3_WS :
+                        /* fall through */
+                    case SCUX_CLK_SSIF4_WS :
+                        /* fall through */
+                    case SCUX_CLK_SSIF5_WS :
+                        freq_value = p_scux_info_ch->src_cfg.input_ws;
+                        if (0U == freq_value)
+                        {
+                            retval = EPERM;
+                        }
+                    break;
+                    
+                    default :
+                        /* NOTREACHED on At the time of a normal performance */
+                        retval = EPERM;
+                    break;
+                }
+                    
+                if (ESUCCESS == retval)
+                { 
+                    /* check devide rate and devide source clock */
+                    /* check source clock isn't SSIF WS signal */
+                    if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async) && 
+                        (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.input_clk_async))
+                    {
+                        if ((0U != (p_scux_info_ch->src_cfg.input_div_async % SCUX_EVEN_VALUE_DIV)) ||
+                            (SCUX_MAX_DIV_CLK < p_scux_info_ch->src_cfg.input_div_async))
+                        {
+                            retval = EPERM;
+                        }
+                        else
+                        {
+                            if (0U == p_scux_info_ch->src_cfg.input_div_async)
+                            {
+                                /* 0 is a same size */
+                                p_scux_info_ch->input_rate = freq_value;
+                            }
+                            else{
+                                p_scux_info_ch->input_rate = freq_value / p_scux_info_ch->src_cfg.input_div_async;
+                            }
+                        }
+                    }
+                    else
+                    {
+                        p_scux_info_ch->input_rate = freq_value;
+                    }
+                    
+                    if (ESUCCESS == retval)
+                    {
+                        /* check input frequency is enable range */
+                        if (SCUX_USE_CH_6 == p_scux_info_ch->src_cfg.use_ch)
+                        {
+                            max_rate = SCUX_MAX_FREQ_CH6;
+                        }
+                        else if (SCUX_USE_CH_8 == p_scux_info_ch->src_cfg.use_ch)
+                        {
+                            max_rate = SCUX_MAX_FREQ_CH8;
+                        }
+                        else
+                        {
+                            max_rate = SCUX_MAX_FREQ_CH1_4;
+                        }
+                        
+                        if ((SCUX_MIN_FREQ > p_scux_info_ch->input_rate) || 
+                           (max_rate < p_scux_info_ch->input_rate))
+                        {
+                            retval = EPERM;
+                        }
+                    }
+                }
+                    
+                if (ESUCCESS == retval)
+                {
+                    /* if output route is SSIF direct route ,WS signal frequency is used */
+                    if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1])
+                    {
+                        if ((SCUX_SYNC_RATE_8      == p_scux_info_ch->src_cfg.output_ws)  ||
+                            (SCUX_SYNC_RATE_11_025  == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_12      == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_16      == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_22_05   == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_24      == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_32      == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_44_1    == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_48      == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_64      == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_88_2    == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_96      == p_scux_info_ch->src_cfg.output_ws))
+                        {
+                            p_scux_info_ch->output_rate = p_scux_info_ch->src_cfg.output_ws;
+                        }   
+                        else
+                        {
+                            retval = EPERM;
+                        }
+                    }
+                    else
+                    {              
+                        /* check output rate (mem to mem)*/
+                        /* get output source clock */
+                        switch (p_scux_info_ch->src_cfg.output_clk_async)
+                        {
+                            case SCUX_CLK_AUDIO_CLK :
+                                freq_value = SCUX_AUDIO_CLK;
+                            break;
+                                                        
+                            case SCUX_CLK_AUDIO_X1 :
+                                freq_value = SCUX_AUDIO_X1;
+                            break;
+                          
+                            case SCUX_CLK_MLB_CLK :
+                                freq_value = SCUX_MLB_CLK;
+                            break;
+            
+                            case SCUX_CLK_USB_X1 :
+                                freq_value = SCUX_USB_X1;
+                            break;
+            
+                            case SCUX_CLK_CLKP1_2 :
+                                freq_value = SCUX_CLKLP1_DIV2;
+                            break;
+        
+                            case SCUX_CLK_MTU_TIOC3A :
+                                freq_value = p_scux_info_ch->src_cfg.freq_tioc3a;
+                                if (0U == freq_value)
+                                {
+                                    retval = EPERM;
+                                }
+                            break;
+            
+                            case SCUX_CLK_MTU_TIOC4A :
+                                freq_value = p_scux_info_ch->src_cfg.freq_tioc4a;
+                                if (0U == freq_value)
+                                {
+                                    retval = EPERM;
+                                }
+                            break;
+            
+                            case SCUX_CLK_SSIF0_WS :
+                                /* fall through */
+                            case SCUX_CLK_SSIF1_WS :
+                                /* fall through */
+                            case SCUX_CLK_SSIF2_WS :
+                                /* fall through */
+                            case SCUX_CLK_SSIF3_WS :
+                                /* fall through */
+                            case SCUX_CLK_SSIF4_WS :
+                                /* fall through */
+                            case SCUX_CLK_SSIF5_WS :
+                                freq_value = p_scux_info_ch->src_cfg.output_ws;
+                                if (0U == freq_value)
+                                {
+                                    retval = EPERM;
+                                }
+                            break;
+                            
+                            default :
+                                /* error check is gone when route is other than SSIF */
+                                if (SCUX_ROUTE_SSIF != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                                {
+                                    retval = EPERM;
+                                }
+                            break;
+                        }
+                    }
+                    
+                    if (ESUCCESS == retval)
+                    {         
+                        /* check devide rate on only except for SSIF route, MISRA R1.1 mesure */          
+                        if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+                            (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+                            (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+                            (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.output_clk_async) && 
+                            (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+                            (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.output_clk_async))
+                        {                  
+                            if ((0U != (p_scux_info_ch->src_cfg.output_div_async % SCUX_EVEN_VALUE_DIV)) ||
+                                (SCUX_MAX_DIV_CLK < p_scux_info_ch->src_cfg.output_div_async))
+                            {
+                                retval = EPERM;
+                            }
+                        }
+                    }
+
+                    if (ESUCCESS == retval)
+                    {
+                        /* check source clock isn't SSIF WS signal */
+                        if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+                            (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+                            (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+                            (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.output_clk_async) && 
+                            (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+                            (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.output_clk_async))
+                        {
+                            if (0U == p_scux_info_ch->src_cfg.output_div_async)
+                            {
+                                /* 0 is a same size */
+                                p_scux_info_ch->output_rate = freq_value;
+                            }
+                            else
+                            {
+                                p_scux_info_ch->output_rate = freq_value / p_scux_info_ch->src_cfg.output_div_async;
+                            }
+                        }
+                        else
+                        {
+                            p_scux_info_ch->output_rate = freq_value;
+                        }
+                        /* check input frequency is enable range */
+                        if (SCUX_USE_CH_6 == p_scux_info_ch->src_cfg.use_ch)
+                        {
+                            max_rate = SCUX_MAX_FREQ_CH6;
+                        }
+                        else if (SCUX_USE_CH_8 == p_scux_info_ch->src_cfg.use_ch)
+                        {
+                            max_rate = SCUX_MAX_FREQ_CH8;
+                        }
+                        else
+                        {
+                            max_rate = SCUX_MAX_FREQ_CH1_4;
+                        }
+                        
+                        if ((SCUX_MIN_FREQ > p_scux_info_ch->output_rate) || 
+                            (max_rate < p_scux_info_ch->output_rate))
+                        {
+                            retval = EPERM;
+                        }
+                        
+                    }
+                }
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                /* check convert rate range */
+                max_conv_rate = SCUX_MAX_CONV_RATE;
+                switch (p_scux_info_ch->src_cfg.delay_mode)
+                {
+                    case SCUX_DELAY_NORMAL :
+                        switch (p_scux_info_ch->src_cfg.use_ch)
+                        {
+                            case SCUX_USE_CH_1 :
+                                /* fall through */
+                            case SCUX_USE_CH_2 :
+                                min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH1_2;
+                            break;
+                            
+                            case SCUX_USE_CH_4 :
+                                min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH4;
+                            break;
+                            
+                            case SCUX_USE_CH_6 :
+                                min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH6;
+                            break;
+                            
+                            case SCUX_USE_CH_8 :
+                                min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH8;
+                            break;                          
+                    
+                            default :
+                                /* NOTREACHED on At the time of a normal performance */
+                                retval = EPERM;
+                            break;
+                        }                   
+                    break;
+                        
+                    case SCUX_DELAY_LOW_DELAY1 :
+                        min_conv_rate = SCUX_MIN_CONV_RATE_DELAY1;
+                    break;
+    
+                    case SCUX_DELAY_LOW_DELAY2 :
+                        min_conv_rate = SCUX_MIN_CONV_RATE_DELAY2;
+                    break;                
+                        
+                    default :
+                        /* NOTREACHED on At the time of a normal performance */
+                        retval = EPERM;
+                    break;
+                }
+                        
+                rate_sample_ratio = ((p_scux_info_ch->output_rate * SCUX_RATE_INT_CONV_VALUE) / p_scux_info_ch->input_rate);
+                if ((min_conv_rate > rate_sample_ratio) || (max_conv_rate < rate_sample_ratio))
+                {
+                    retval = EPERM;
+                }
+            }
+        }
+    
+        if (ESUCCESS == retval)
+        {
+            /* check wait time */
+            if (SCUX_MAX_WAIT_TIME < p_scux_info_ch->src_cfg.wait_sample)
+            {
+                retval = EPERM;
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            /* check min rate ratio */
+            if ((SCUX_MIN_RATE_MIN_PAERCENTAGE > (uint32_t)p_scux_info_ch->src_cfg.min_rate_percentage) || 
+                (SCUX_MIN_RATE_MAX_PAERCENTAGE < (uint32_t)p_scux_info_ch->src_cfg.min_rate_percentage))
+            {
+                retval = EPERM;
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            /* check input data position */
+            for (audio_ch = 0; ((ESUCCESS == retval) && (audio_ch < p_scux_info_ch->src_cfg.use_ch)); audio_ch++)
+            {
+                if ((SCUX_AUDIO_CH_MIN >= p_scux_info_ch->src_cfg.select_in_data_ch[audio_ch]) || 
+                    (SCUX_AUDIO_CH_MAX <= p_scux_info_ch->src_cfg.select_in_data_ch[audio_ch]))
+                {
+                    retval = EPERM;
+                }
+            }
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CheckSrcParam
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CheckDvuParam
+* @brief         Check DVU parameter.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch:SCUX channel information.
+* @retval        ESUCCESS : Parameter is no problems.
+*                EACCES : DVU setting isn't performed when DVU is used.
+*                EPERM : Parameter is unexpected value.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+static int_t SCUX_CheckDvuParam(const scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t retval = ESUCCESS;
+    int_t audio_ch;
+    uint32_t enable_ch_flag = false;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        if (false == p_scux_info_ch->dvu_setup)
+        {
+            retval = EACCES;
+        }
+        else
+        {
+            if (false != p_scux_info_ch->dvu_cfg.dvu_enable)
+            {
+                /* check digital volume value */
+                if (false !=  p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol_enable)
+                {
+                    /* check digital volume value */
+                    for (audio_ch = 0; ((ESUCCESS == retval) && (audio_ch < p_scux_info_ch->src_cfg.use_ch)); audio_ch++)
+                    {
+                        if (SCUX_MAX_DIGITAL_VOLUME < p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch])
+                        {
+                            retval = EPERM;
+                        }
+                    }
+                }
+                
+                /* check ramp volume value */
+                for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
+                {
+                    enable_ch_flag |= (uint32_t)p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol_enable[audio_ch];
+                }
+                
+                if ((ESUCCESS == retval) && (false != (bool_t)enable_ch_flag))
+                {
+                    /* check ramp up period */
+                    if ((p_scux_info_ch->dvu_cfg.dvu_ramp_vol.up_period <= SCUX_DVU_TIME_MIN) ||
+                        (p_scux_info_ch->dvu_cfg.dvu_ramp_vol.up_period >= SCUX_DVU_TIME_MAX))
+                    {
+                        retval = EPERM;
+                    }
+                    
+                    if (ESUCCESS == retval) 
+                    {
+                        /* check ramp down period */
+                        if ((p_scux_info_ch->dvu_cfg.dvu_ramp_vol.down_period <= SCUX_DVU_TIME_MIN) ||
+                            (p_scux_info_ch->dvu_cfg.dvu_ramp_vol.down_period >= SCUX_DVU_TIME_MAX))
+                        {
+                            retval = EPERM;
+                        }
+                    }
+                
+                    if (ESUCCESS == retval)
+                    {
+                        /* check ramp volume */
+                        if (SCUX_MAX_RAMP_VOLUME < p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol)
+                        {
+                            retval = EPERM;
+                        }
+                    }
+                
+                    if (ESUCCESS != retval)
+                    {
+                        /* check wait time */
+                        if (SCUX_MAX_WAIT_TIME < p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_wait_time)
+                        {
+                            retval = EPERM;
+                        }
+                    }
+                }
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CheckDvuParam
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CheckSsifParam
+* @brief         Check SSIF parameter.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @param[in]     ssif_ch : Used ssif channel number.
+* @param[in]     use_mix_flag : Flag of Using MIX .
+* @retval        ESUCCESS : Parameter is no problems.
+*                EACCES : SSIF setting isn't performed when SSIF is used.
+*                EACCES : SSIF channel is already used.
+*                EACCES : When use MIX, it is a setup which does not agree in a route setup. 
+*                EPERM : Parameter is unexpected value.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+static int_t SCUX_CheckSsifParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT], const bool_t use_mix_flag)
+{
+    int_t retval = ESUCCESS;
+    uint32_t ssif_arrange_num;
+    uint32_t mix_ssif_ch_bit = 0;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch) || (NULL == ssif_ch)) 
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        if (false == use_mix_flag)
+        {
+            /* used SSIF channel check no used MIX route */
+            for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
+            {
+                if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
+                {
+                    /* check SSIF is already setup */
+                    if (false == gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_setup)
+                    {
+                        retval = EACCES;
+                    }
+                    else
+                    {
+                        /* used SSIF channel is checked by other SCUX channel */
+                        if (0 != gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].scux_channel)
+                        {
+                            retval = EACCES;
+                        }
+                    }
+                }
+            }
+        }
+        else
+        {
+            /* used SSIF channel check on MIX route */
+            for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
+            {
+                if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
+                {
+                    /* clear SCUX_SSIF_use_mix_flag and get SSIF channel number */
+                    mix_ssif_ch_bit |= (1U << ssif_ch[ssif_arrange_num]);
+                    /* check SSIF is already setup */
+                    if (false == gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_setup)
+                    {
+                        retval = EACCES;
+                    }
+                }
+            }
+            if (ESUCCESS == retval)
+            {
+                /* used SSIF channel check, on MIX route check */
+                if (0U != p_info_drv->shared_info.mix_ssif_ch)
+                {
+                    /* In the MIX setup for the and after 2times, it is checked that same SSIF ch on 1st setting is set up */
+                    if (p_info_drv->shared_info.mix_ssif_ch != mix_ssif_ch_bit)
+                    {
+                        retval = EACCES;
+                    }   
+                }
+                else
+                {
+                    /*It checks that SSIF channel is not used once on first MIX setup */
+                    if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2])
+                    {
+                        if ((0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]].scux_channel) ||
+                            (0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]].scux_channel) ||
+                            (0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3]].scux_channel))
+                        {
+                            retval = EACCES;
+                        }
+                    }
+                    else
+                    {
+                        if (0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]].scux_channel)
+                        {
+                            retval = EACCES;
+                        }
+                    }
+                }
+            }
+        }
+                
+        /* each SSIF parameter check */
+        for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
+        {
+            /* used SSIF channel check, on SSIF direct route check */
+            if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
+            {
+                
+                /* check system word */
+                if ((gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.system_word <= SCUX_SSIF_SYSTEM_LEN_MIN) ||
+                    (gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.system_word >= SCUX_SSIF_SYSTEM_LEN_MAX))
+                {
+                    retval = EPERM;
+                }
+                else
+                {
+                    /* check system word >= data word */
+                    /* The combination applicable to error only of data word of 24bit and system word of 16bit */
+                    if ((SCUX_DATA_LEN_16 != p_scux_info_ch->src_cfg.word_len) && 
+                        (SCUX_SSIF_SYSTEM_LEN_16 == gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.system_word))
+                    {
+                        retval = EPERM;
+                    }
+                }
+    
+                if (ESUCCESS == retval)
+                {
+                    /* if multiple channel is used, TDM is disable */
+                    if ((SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]) &&
+                        (false != gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.use_tdm))
+                    {
+                        retval = EPERM;
+                    }
+                }
+                if (ESUCCESS == retval)
+                {
+                    retval = SCUX_CheckSsifClockDiv(p_scux_info_ch, ssif_ch[ssif_arrange_num]);
+                }
+                
+                if (ESUCCESS == retval)
+                {
+                    gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].scux_channel 
+                    = (int_t)((uint32_t)gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].scux_channel | (1U << p_scux_info_ch->channel));
+                }
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            /* set SSIF information structure pointer */
+            if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2])
+            {
+                p_scux_info_ch->p_ssif_info1 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]];
+                p_scux_info_ch->p_ssif_info2 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]];
+                p_scux_info_ch->p_ssif_info3 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3]];
+            }
+            else
+            {
+                p_scux_info_ch->p_ssif_info1 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]];
+                p_scux_info_ch->p_ssif_info2 = NULL;
+                p_scux_info_ch->p_ssif_info3 = NULL;
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CheckSsifParam
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CheckMixParam
+* @brief         Check MIX parameter.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch:SCUX channel information.
+* @retval        ESUCCESS : Parameter is no problems.
+*                EACCES : MIX setting isn't performed when MIX is used.
+*                EPERM : Parameter is unexpected value.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+static int_t SCUX_CheckMixParam(const scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t retval = ESUCCESS;
+    int_t scux_ch;
+    int_t audio_ch;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    { 
+        retval = EFAULT;
+    }
+    else
+    {
+        if (false == p_info_drv->shared_info.mix_setup)
+        {
+            retval = EACCES;
+        }
+        else
+        {
+            if (false != p_info_drv->shared_info.mixmode_ramp)
+            {
+                /* check ramp up time */
+                if ((SCUX_MIX_TIME_MIN >= p_info_drv->shared_info.up_period) ||
+                    (SCUX_MIX_TIME_MAX <= p_info_drv->shared_info.up_period))
+                {
+                    retval = EPERM;
+                }
+                
+                /* check ramp down time */
+                if ((SCUX_MIX_TIME_MIN >= p_info_drv->shared_info.down_period) ||
+                    (SCUX_MIX_TIME_MAX <= p_info_drv->shared_info.down_period))
+                {
+                    retval = EPERM;
+                }
+            }
+            
+            /* check MIX volume */
+            for (scux_ch = SCUX_CH_0; ((ESUCCESS == retval) && (SCUX_CH_NUM > scux_ch)); scux_ch++)
+            {
+                /* register set on the channel itself which sets up or channel which has already MIX operated */
+                if ((scux_ch == p_scux_info_ch->channel) ||
+                    (0U != (p_info_drv->shared_info.mix_run_ch & (1U << scux_ch))))
+                {
+                    if (SCUX_MAX_RAMP_VOLUME < p_info_drv->shared_info.mix_vol[scux_ch])
+                    {
+                        retval = EPERM;
+                    }
+                }
+            }
+                    
+            /* check output data position */
+            for (audio_ch = 0; ((ESUCCESS == retval) && (audio_ch < p_scux_info_ch->src_cfg.use_ch)); audio_ch++)
+            {
+                /* check min rate ratio */
+                if ((SCUX_AUDIO_CH_MIN >= p_info_drv->shared_info.select_out_data_ch[audio_ch]) || 
+                    (SCUX_AUDIO_CH_MAX <= p_info_drv->shared_info.select_out_data_ch[audio_ch]))
+                {
+                    retval = EPERM;
+                }
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CheckMixParam
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_StrNLen
+* @brief         computes the length of the string
+*
+*                Description:<br>
+*                if string is longer than maxlen, this function return maxlen
+* @param[in]     p_str      :pointer of string 
+* @param[in]     maxlen     :maximum length of inspection
+* @retval        'number of characters in the string' or 'maxlen'
+******************************************************************************/
+size_t SCUX_StrNLen(const char_t* p_str, size_t maxlen)
+{
+    size_t ret_len;
+
+    if (NULL == p_str)
+    {
+        /* character string does not exist */
+        ret_len = 0;
+    }
+    else
+    {
+        /* ->IPA P1.3.1 Even if a sign is positive, even a negative is no problem. */
+        for (ret_len = 0; (maxlen != 0U) && (*p_str != '\0'); ret_len++)
+        /* <-IPA P1.3.1 */
+        {
+            maxlen--;
+            p_str++;
+        }
+    }
+
+    return ret_len;
+}
+
+/******************************************************************************
+End of function SCUX_StrNLen
+******************************************************************************/
+
+#if(1) /* mbed */
+/**************************************************************************//**
+* Function Name: SCUX_CmnUnInitialize
+* @brief         uninitialize driver infomation.
+*
+*                Description:<br>
+*                
+* @param[in]     None.
+* @retval        ESUCCESS : Parameter is no problems.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+static int_t SCUX_CmnUnInitialize(void)
+{
+    int_t    retval = ESUCCESS;
+    osStatus sem_ercd;
+    int_t    ssif_ch_count;
+    uint32_t cpg_value;
+    uint32_t was_masked;
+    volatile uint8_t dummy_buf;
+
+    /* software reset */
+    SCUX.SWRSR_CIM &= ~SWRSR_CIM_SWRST_SET;
+
+    for (ssif_ch_count = 0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++) 
+    {
+        if (NULL != gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access)
+        {
+            sem_ercd = osSemaphoreDelete(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set error return value */
+                 retval = EFAULT;
+            }
+
+            gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = NULL;
+        }
+    }
+
+    if (NULL != gb_scux_info_drv.shared_info.sem_shared_access)
+    {
+        sem_ercd = osSemaphoreDelete(gb_scux_info_drv.shared_info.sem_shared_access);
+        /* semaphore error check */
+        if (osOK != sem_ercd)
+        {
+            /* set error return value */
+            retval = EFAULT;
+        }
+
+        gb_scux_info_drv.shared_info.sem_shared_access = NULL;
+    }
+
+    was_masked = __disable_irq();
+
+    /* stop clock for SCUX */
+    cpg_value = ((uint32_t)CPG.STBCR8 | CPG_STBCR8_BIT_MSTP81);
+    CPG.STBCR8 = (uint8_t)cpg_value;
+    dummy_buf = CPG.STBCR8;
+
+    if (0U == was_masked)
+    {
+        /* enable all irq */
+        __enable_irq();
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CmnUnInitialize
+******************************************************************************/
+#endif /* end mbed */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_src/scux/scux.h	Fri Oct 02 03:03:25 2015 +0000
@@ -0,0 +1,780 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          scux.h
+* $Rev: 993 $
+* $Date:: 2014-07-22 09:54:45 +0900#$
+* @brief         Sample driver internal header
+******************************************************************************/
+
+#ifndef SCUX_H
+#define SCUX_H
+
+/******************************************************************************
+Includes <System Includes>, "Project Includes"
+******************************************************************************/
+
+#include "scux_if.h" 
+#include "scux_int.h"
+#include "aioif.h"
+#include "iodefine.h"
+#include "Renesas_RZ_A1.h"
+#include "dma_if.h"
+#include "bsp_drv_cmn.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* SCUX Register Set Value */
+/* Init Value */
+/* IPC */
+#define IPCIR_IPC0_INIT_VALUE      (0x00000001U)
+#define IPSLR_IPC0_INIT_VALUE      (0x00000000U)
+/* OPC */
+#define OPCIR_OPC0_INIT_VALUE      (0x00000001U)
+#define OPSLR_OPC0_INIT_VALUE      (0x00000000U)
+/* FFD */
+#define FFDIR_FFD0_INIT_VALUE      (0x00000001U)
+#define FDAIR_FFD0_INIT_VALUE      (0x00000000U)
+#define DRQSR_FFD0_INIT_VALUE      (0x00000000U)
+#define FFDPR_FFD0_INIT_VALUE      (0x00000000U)
+#define FFDBR_FFD0_INIT_VALUE      (0x00000000U)
+#define DEVMR_FFD0_INIT_VALUE      (0x00000000U)
+#define DEVCR_FFD0_INIT_VALUE      (0x00000000U)
+/* FFU */
+#define FFUIR_FFU0_INIT_VALUE      (0x00000001U)
+#define FUAIR_FFU0_INIT_VALUE      (0x00000000U)
+#define URQSR_FFU0_INIT_VALUE      (0x00000000U)
+#define FFUPR_FFU0_INIT_VALUE      (0x00000000U)
+#define UEVMR_FFU0_INIT_VALUE      (0x00000000U)
+#define UEVCR_FFU0_INIT_VALUE      (0x00000000U)
+/* SRC */
+#define SRCIR_2SRC0_INIT_VALUE     (0x00000001U)
+#define SADIR_2SRC0_INIT_VALUE     (0x00000000U)
+#define SRCBR_2SRC0_INIT_VALUE     (0x00000000U)
+#define IFSCR_2SRC0_INIT_VALUE     (0x00000000U)
+#define IFSVR_2SRC0_INIT_VALUE     (0x00000000U)
+#define SRCCR_2SRC0_INIT_VALUE     (0x00000000U)
+#define MNFSR_2SRC0_INIT_VALUE     (0x00000000U)
+#define BFSSR_2SRC0_INIT_VALUE     (0x00000000U)
+#define WATSR_2SRC0_INIT_VALUE     (0x00000000U)
+#define SEVMR_2SRC0_INIT_VALUE     (0x00000000U)
+#define SEVCR_2SRC0_INIT_VALUE     (0x00000000U)
+#define SRCIRR_2SRC0_INIT_VALUE    (0x00000001U)
+/* DVU */
+#define DVUIR_DVU0_INIT_VALUE      (0x00000001U)
+#define VADIR_DVU0_INIT_VALUE      (0x00000000U)
+#define DVUBR_DVU0_INIT_VALUE      (0x00000000U)
+#define DVUCR_DVU0_INIT_VALUE      (0x00000000U)
+#define ZCMCR_DVU0_INIT_VALUE      (0x00000000U)
+#define VRCTR_DVU0_INIT_VALUE      (0x00000000U)
+#define VRPDR_DVU0_INIT_VALUE      (0x00000000U)
+#define VRDBR_DVU0_INIT_VALUE      (0x00000000U)
+#define VRWTR_DVU0_INIT_VALUE      (0x00000000U)
+#define VOL_N_R_DVU0_INIT_VALUE    (0x00000000U)
+#define DVUER_DVU0_INIT_VALUE      (0x00000000U)
+#define VEVMR_DVU0_INIT_VALUE      (0x00000000U)
+#define VEVCR_DVU0_INIT_VALUE      (0x00000000U)
+/* MIX */
+#define MIXIR_MIX0_0_INIT_VALUE    (0x00000001U)
+#define MADIR_MIX0_0_INIT_VALUE    (0x00000000U)
+#define MIXBR_MIX0_0_INIT_VALUE    (0x00000000U)
+#define MIXMR_MIX0_0_INIT_VALUE    (0x00000000U)
+#define MVPDR_MIX0_0_INIT_VALUE    (0x00000000U)
+#define MDB_N_R_MIX0_0_INIT_VALUE  (0x00000000U)
+#define MDBER_MIX0_0_INIT_VALUE    (0x00000000U)
+/* CIM */
+#define SWRSR_CIM_INIT_VALUE       (0x00000001U)
+#define DMACR_CIM_INIT_VALUE       (0x00000000U)
+#define SSIRSEL_CIM_INIT_VALUE     (0x00000000U)
+#define FDTSEL_CIM_INIT_VALUE      (0x00000000U)
+#define FUTSEL_CIM_INIT_VALUE      (0x00000000U)
+#define SSIPMD_CIM_INIT_VALUE      (0x00000000U)
+#define SSICTRL_CIM_INIT_VALUE     (0x00000000U)
+#define SRCRSEL_CIM_INIT_VALUE     (0x76543210U)
+#define MIXRSEL_CIM_INIT_VALUE     (0x76543210U)
+
+/* SCUX bit value & mask & fixed setting */
+
+/* IPC */
+#define IPCIR_IPC0_INIT_SET           (1U << 0)
+
+#define IPSLR_IPC_PASS_SEL_MASK       (7U << 0)
+#define IPSLR_IPC_PASS_SEL_SET_ASYNC  (3U << 0)
+#define IPSLR_IPC_PASS_SEL_SET_SYNC   (4U << 0)
+
+/* OPC */
+#define OPCIR_OPC0_INIT_SET           (1U << 0)
+
+#define OPSLR_OPC_PASS_SEL_MASK       (7U << 0)
+#define OPSLR_OPC_PASS_SEL_SET_DIRECT (1U << 0)
+#define OPSLR_OPC_PASS_SEL_SET_ASYNC  (3U << 0)
+#define OPSLR_OPC_PASS_SEL_SET_SYNC   (4U << 0)
+
+/* FFD */
+#define FFDIR_FFD0_INIT_SET           (1U << 0)
+
+#define FDAIR_FFD0_CHNUM_MASK         (0x0FU << 0)
+
+#define DRQSR_FFD0_SIZE_MASK          (0x0FU << 0)
+
+#define FFDPR_FFD0_PASS_SET_ASYNC     (1U << 0)
+#define FFDPR_FFD0_PASS_SET_SYNC      (2U << 0)
+
+#define FFDBR_FFD0_BOOT_SET           (1U << 0)
+
+#define DEVMR_FFD0_DEVMUF_SET         (1U << 31)
+#define DEVMR_FFD0_DEVMOF_SET         (1U << 30)
+#define DEVMR_FFD0_DEVMOL_SET         (1U << 29)
+#define DEVMR_FFD0_DEVMIUF_SET        (1U << 28)
+#define DEVMR_FFD0_DEVMRQ_SET         (1U << 15)
+
+#define DEVCR_FFD0_DEVCUF_MASK        (1U << 31)
+#define DEVCR_FFD0_DEVCUF_SET         (1U << 31)
+#define DEVCR_FFD0_DEVCOF_MASK        (1U << 30)
+#define DEVCR_FFD0_DEVCOF_SET         (1U << 30)
+#define DEVCR_FFD0_DEVCOL_MASK        (1U << 29)
+#define DEVCR_FFD0_DEVCOL_SET         (1U << 29)
+#define DEVCR_FFD0_DEVCIUF_MASK       (1U << 28)
+#define DEVCR_FFD0_DEVCIUF_SET        (1U << 28)
+#define DEVCR_FFD0_DEVCRQ_MASK        (1U << 15)
+#define DEVCR_FFD0_DEVCRQ_SET         (1U << 15)
+
+/* FFU */
+#define FFUIR_FFU0_INIT_SET           (1U << 0)
+
+#define FUAIR_FFU0_CHNUM_MASK         (0x0FU << 0)
+
+#define URQSR_FFU0_SIZE_MASK          (0x0FU << 0)
+
+#define FFUPR_FFU0_PASS_SET_ASYNC     (1U << 0)
+#define FFUPR_FFU0_PASS_SET_SYNC      (2U << 0)
+
+#define UEVMR_FFU0_UEVMUF_SET         (1U << 31)
+#define UEVMR_FFU0_UEVMOF_SET         (1U << 30)
+#define UEVMR_FFU0_UEVMOL_SET         (1U << 29)
+#define UEVMR_FFU0_UEVMRQ_SET         (1U << 15)
+
+#define UEVCR_FFU0_UEVCUF_MASK        (1U << 31)
+#define UEVCR_FFU0_UEVCUF_SET         (1U << 31)
+#define UEVCR_FFU0_UEVCOF_MASK        (1U << 30)
+#define UEVCR_FFU0_UEVCOF_SET         (1U << 30)
+#define UEVCR_FFU0_UEVCOL_MASK        (1U << 29)
+#define UEVCR_FFU0_UEVCOL_SET         (1U << 29)
+#define UEVCR_FFU0_UEVCRQ_MASK        (1U << 15)
+#define UEVCR_FFU0_UEVCRQ_SET         (1U << 15)
+
+/* SRC */
+#define SRCIR_2SRC0_INIT_SET          (1U << 0)
+
+#define SADIR_2SRC0_CHNUM_MASK        (0x0FU << 0)
+#define SADIR_2SRC0_OTBL_MASK         (0x1FU << 16)
+#define SADIR_2SRC0_OTBL_SET_24BIT    (0x0U << 16)
+#define SADIR_2SRC0_OTBL_SET_16BIT    (0x8U << 16)
+
+#define SRCBR_2SRC0_BYPASS_SET        (0x1U << 0)
+
+#define IFSCR_2SRC0_INTIFSEN_SET      (0x1U << 0)
+
+#define IFSVR_2SRC0_INTIFS_MASK       (0x0FFFFFFFU << 0)
+
+#define SRCCR_2SRC0_BASE_VALUE        (0x00010110U)
+#define SRCCR_2SRC0_WATMD_SET         (1U << 20)
+#define SRCCR_2SRC0_BUFMD_SET         (1U << 12)
+#define SRCCR_2SRC0_SRCMD_SET         (1U << 0)
+
+#define MNFSR_2SRC0_MINFS_MASK        (0x0FFFFFFFU << 0)
+
+#define BFSSR_2SRC0_BUFDATA_MASK      (0x3FFU << 16)
+#define BFSSR_2SRC0_BUFDATA_SET_DELAY_MODE1 (0x80U << 16)
+#define BFSSR_2SRC0_BUFDATA_SET_DELAY_MODE2 (0x40U << 16)
+#define BFSSR_2SRC0_BUFIN_MASK        (0x0FU << 0)
+#define BFSSR_2SRC0_BUFIN_SET_DELAY_MODE (0x05U << 0)
+
+#define WATSR_2SRC0_WTIME_MASK        (0xFFFFFFU << 0)
+
+#define SEVMR_2SRC0_EVMUF_SET         (1U << 31)
+#define SEVMR_2SRC0_EVMOF_SET         (1U << 30)
+
+#define SEVCR_2SRC0_EVCUF_MASK        (1U << 31)
+#define SEVCR_2SRC0_EVCUF_SET         (1U << 31)
+#define SEVCR_2SRC0_EVCOF_MASK        (1U << 30)
+#define SEVCR_2SRC0_EVCOF_SET         (1U << 30)
+
+#define SRCIRR_2SRC0_INIT_SET         (1U << 0)
+
+#define DVUIR_DVU0_INIT_SET           (1U << 0)
+
+#define VADIR_DVU0_OTBL_MASK          (0x1FU << 16)
+#define VADIR_DVU0_OTBL_SET_24BIT     (0x0U << 16)
+#define VADIR_DVU0_OTBL_SET_16BIT     (0x8U << 16)
+#define VADIR_DVU0_CHNUM_MASK         (0x0FU << 0)
+
+#define DVUBR_DVU0_BYPASS_SET         (0x1U << 0)
+
+#define DVUCR_DVU0_VVMD_SET           (1U << 8)
+#define DVUCR_DVU0_VRMD_SET           (1U << 4)
+#define DVUCR_DVU0_ZCMD_SET           (1U << 0)
+
+#define ZCMCR_DVU0_ZCEN_SET           (1U << 0)
+
+#define VRCTR_DVU0_VREN_SET           (1U << 0)
+
+#define VRPDR_DVU0_VRPDUP_SHIFT       (8U)
+#define VRPDR_DVU0_VRPDUP_MASK        (0x1F << VRPDR_DVU0_VRPDUP_SHIFT)
+#define VRPDR_DVU0_VRPDDW_SHIFT       (0U)
+#define VRPDR_DVU0_VRPDDW_MASK        (0x1F << VRPDR_DVU0_VRPDDW_SHIFT)
+
+#define VRDBR_DVU0_VRDB_MASK          (0x3FFU << 0)
+
+#define VRWTR_DVU0_VRWT_MASK          (0xFFFFFFU << 0)
+
+#define VOL_N_R_DVU_VOLVAL_MASK       (0xFFFFFFU << 0)
+
+#define DVUER_DVU0_DVUEN_SET          (1U << 0)
+
+#define DVUSR_DVU0_ZSTS_N_SHIFT       (16U)
+#define DVUSR_DVU0_ZSTS_N_MASK        (1U << DVUSR_DVU0_ZSTS_N_SHIFT)
+#define DVUSR_DVU0_ZSTS_MASK          (0xFFU << DVUSR_DVU0_ZSTS_N_SHIFT)
+#define DVUSR_DVU0_VRSTS_MASK         (7U << 0)
+#define DVUSR_DVU0_VRSTS_VOL_FIX      (4U << 0)
+
+#define VEVMR_DVU0_VEVMZCM_SET        (1U << 24)
+
+#define VEVCR_DVU0_VEVCZCM_SET        (1U << 24)
+
+/* MIX */
+#define MIXIR_MIX0_INIT_SET           (1U << 0)
+
+#define MADIR_MIX0_CHNUM_MASK         (0x0FU << 0)
+
+#define MIXMR_MIX0_MIXMODE_SET        (1U << 0)
+
+#define MVPDR_MIX0_MXPDUP_SHIFT       (8U)
+#define MVPDR_MIX0_MXPDUP_MASK        (0x0FU << MVPDR_MIX0_MXPDUP_SHIFT)
+#define MVPDR_MIX0_MXPDDW_SHIFT       (0U)
+#define MVPDR_MIX0_MXPDDW_MASK        (0x0FU << MVPDR_MIX0_MXPDDW_SHIFT)
+
+#define MDB_N_R_MIX0_MIXDB_N_MASK     (0x3FFU <<0)
+
+#define MDBER_MIX0_MIXDBEN_SET        (1U << 0)
+
+#define MIXSR_MIX0_MIXSTS_MASK        (3U << 0)
+
+/* CIM */
+#define SWRSR_CIM_SWRST_SET           (1U << 0)
+
+#define DMACR_CIM_DMAMDFFU_N_SET      (1U << 4)
+#define DMACR_CIM_DMAMDFFD_N_SET      (1U << 0)
+
+#define SSIRSEL_CIM_SOSEL5_MASK       (3U << 20)
+#define SSIRSEL_CIM_SOSEL5_SRC3_SET   (0U << 20)
+#define SSIRSEL_CIM_SOSEL5_SRC1_SET   (1U << 20)
+#define SSIRSEL_CIM_SOSEL5_SRC0_SET   (2U << 20)
+#define SSIRSEL_CIM_SOSEL5_MIX_SET    (3U << 20)
+#define SSIRSEL_CIM_SOSEL4_MASK       (3U << 16)
+#define SSIRSEL_CIM_SOSEL4_SRC2_SET   (0U << 16)
+#define SSIRSEL_CIM_SOSEL4_SRC1_SET   (1U << 16)
+#define SSIRSEL_CIM_SOSEL4_SRC0_SET   (2U << 16)
+#define SSIRSEL_CIM_SOSEL4_MIX_SET    (3U << 16)
+#define SSIRSEL_CIM_SOSEL3_MASK       (3U << 12)
+#define SSIRSEL_CIM_SOSEL3_SRC1_SET   (0U << 12)
+#define SSIRSEL_CIM_SOSEL3_SRC0_SET   (1U << 12)
+#define SSIRSEL_CIM_SOSEL3_MIX_SET    (2U << 12)
+#define SSIRSEL_CIM_SOSEL2_MASK       (3U << 8)
+#define SSIRSEL_CIM_SOSEL2_SRC3_SET   (0U << 8)
+#define SSIRSEL_CIM_SOSEL2_SRC0_SET   (1U << 8)
+#define SSIRSEL_CIM_SOSEL2_SRC1_SET   (2U << 8)
+#define SSIRSEL_CIM_SOSEL2_MIX_SET    (3U << 8)
+#define SSIRSEL_CIM_SOSEL1_MASK       (3U << 4)
+#define SSIRSEL_CIM_SOSEL1_SRC2_SET   (0U << 4)
+#define SSIRSEL_CIM_SOSEL1_SRC0_SET   (1U << 4)
+#define SSIRSEL_CIM_SOSEL1_SRC1_SET   (2U << 4)
+#define SSIRSEL_CIM_SOSEL1_MIX_SET    (3U << 4)
+#define SSIRSEL_CIM_SOSEL0_MASK       (3U << 0)
+#define SSIRSEL_CIM_SOSEL0_SRC0_SET   (0U << 0)
+#define SSIRSEL_CIM_SOSEL0_SRC1_SET   (1U << 0)
+#define SSIRSEL_CIM_SOSEL0_MIX_SET    (2U << 0)
+
+#define FDTSEL_CIM_SCKDIV_SHIFT       (16U)
+#define FDTSEL_CIM_SCKDIV_MASK        (0x7FFU << FDTSEL_CIM_SCKDIV_SHIFT)
+#define FDTSEL_CIM_DIVEN_MASK         (1U << 8)
+#define FDTSEL_CIM_DIVEN_SET          (1U << 8)
+#define FDTSEL_CIM_MTUSEL_MASK        (1U << 4)
+#define FDTSEL_CIM_MTUSEL_SET_TIOC3A  (0U << 4)
+#define FDTSEL_CIM_MTUSEL_SET_TIOC4A  (1U << 4)
+#define FDTSEL_CIM_SCKSEL_MASK        (0x0FU << 0)
+#define FDTSEL_CIM_SCKSEL_AUDIO_CLK_SET (0U)
+#define FDTSEL_CIM_SCKSEL_AUDIO_X1_SET  (1U)
+#define FDTSEL_CIM_SCKSEL_MLB_CLK_SET   (2U)
+#define FDTSEL_CIM_SCKSEL_USB_X1_SET    (3U)
+#define FDTSEL_CIM_SCKSEL_CLKP1_2_SET   (4U)
+#define FDTSEL_CIM_SCKSEL_MTUSEL2_SET   (5U)
+#define FDTSEL_CIM_SCKSEL_SSIF0_WS_SET  (8U)
+#define FDTSEL_CIM_SCKSEL_SSIF1_WS_SET  (9U)
+#define FDTSEL_CIM_SCKSEL_SSIF2_WS_SET  (10U)
+#define FDTSEL_CIM_SCKSEL_SSIF3_WS_SET  (11U)
+#define FDTSEL_CIM_SCKSEL_SSIF4_WS_SET  (12U)
+#define FDTSEL_CIM_SCKSEL_SSIF5_WS_SET  (13U)
+
+#define FUTSEL_CIM_SCKDIV_SHIFT         (16U)
+#define FUTSEL_CIM_SCKDIV_MASK          (0x7FFU << FDTSEL_CIM_SCKDIV_SHIFT)
+#define FUTSEL_CIM_DIVEN_MASK           (1U << 8)
+#define FUTSEL_CIM_DIVEN_SET            (1U << 8)
+#define FUTSEL_CIM_MTUSEL_MASK          (1U << 4)
+#define FUTSEL_CIM_MTUSEL_SET_TIOC3A    (0U << 4)
+#define FUTSEL_CIM_MTUSEL_SET_TIOC4A    (1U << 4)
+#define FUTSEL_CIM_SCKSEL_MASK          (0x0FU << 0)
+#define FUTSEL_CIM_SCKSEL_AUDIO_CLK_SET (0U)
+#define FUTSEL_CIM_SCKSEL_AUDIO_X1_SET  (1U)
+#define FUTSEL_CIM_SCKSEL_MLB_CLK_SET   (2U)
+#define FUTSEL_CIM_SCKSEL_USB_X1_SET    (3U)
+#define FUTSEL_CIM_SCKSEL_CLKP1_2_SET   (4U)
+#define FUTSEL_CIM_SCKSEL_MTUSEL2_SET   (5U)
+#define FUTSEL_CIM_SCKSEL_SSIF0_WS_SET  (8U)
+#define FUTSEL_CIM_SCKSEL_SSIF1_WS_SET  (9U)
+#define FUTSEL_CIM_SCKSEL_SSIF2_WS_SET  (10U)
+#define FUTSEL_CIM_SCKSEL_SSIF3_WS_SET  (11U)
+#define FUTSEL_CIM_SCKSEL_SSIF4_WS_SET  (12U)
+#define FUTSEL_CIM_SCKSEL_SSIF5_WS_SET  (13U)
+
+#define SSIPMD_CIM_SSI5CKS_MASK     (1U << 21)
+#define SSIPMD_CIM_SSI5CKS_SET      (1U << 21)
+#define SSIPMD_CIM_SSI4CKS_MASK     (1U << 20)
+#define SSIPMD_CIM_SSI4CKS_SET      (1U << 20)
+#define SSIPMD_CIM_SSI3CKS_MASK     (1U << 19)
+#define SSIPMD_CIM_SSI3CKS_SET      (1U << 19)
+#define SSIPMD_CIM_SSI2CKS_MASK     (1U << 18)
+#define SSIPMD_CIM_SSI2CKS_SET      (1U << 18)
+#define SSIPMD_CIM_SSI1CKS_MASK     (1U << 17)
+#define SSIPMD_CIM_SSI1CKS_SET      (1U << 17)
+#define SSIPMD_CIM_SSI0CKS_MASK     (1U << 16)
+#define SSIPMD_CIM_SSI0CKS_SET      (1U << 16)
+#define SSIPMD_CIM_SSI3PMD_SHIFT    (14U)
+#define SSIPMD_CIM_SSI3PMD_MASK     (3U << SSIPMD_CIM_SSI3PMD_SHIFT)
+#define SSIPMD_CIM_SSI345EN_MASK    (1U << 12)
+#define SSIPMD_CIM_SSI345EN_SET     (1U << 12)
+#define SSIPMD_CIM_SSI4PMD_SHIFT    (10U)
+#define SSIPMD_CIM_SSI4PMD_MASK     (3U << SSIPMD_CIM_SSI4PMD_SHIFT)
+#define SSIPMD_CIM_SSI5PMD_SHIFT    (8U)
+#define SSIPMD_CIM_SSI5PMD_MASK     (3U << SSIPMD_CIM_SSI5PMD_SHIFT)
+#define SSIPMD_CIM_SSI012EN_MASK    (1U << 4)
+#define SSIPMD_CIM_SSI012EN_SET     (1U << 4)
+#define SSIPMD_CIM_SSI2PMD_SHIFT    (2U)
+#define SSIPMD_CIM_SSI2PMD_MASK     (3U << SSIPMD_CIM_SSI2PMD_SHIFT)
+#define SSIPMD_CIM_SSI1PMD_SHIFT    (0U)
+#define SSIPMD_CIM_SSI1PMD_MASK     (3U << SSIPMD_CIM_SSI1PMD_SHIFT)
+
+#define SSICTRL_CIM_SSI3TX_SET      (1U << 30)
+#define SSICTRL_CIM_SSI4TX_SET      (1U << 29)
+#define SSICTRL_CIM_SSI5TX_SET      (1U << 28)
+#define SSICTRL_CIM_SSI345TEN_SET   (1U << 17)
+#define SSICTRL_CIM_SSI0TX_SET      (1U << 14)
+#define SSICTRL_CIM_SSI1TX_SET      (1U << 13)
+#define SSICTRL_CIM_SSI2TX_SET      (1U << 12)
+#define SSICTRL_CIM_SSI012TEN_SET   (1U << 1)
+
+#define SRCRSEL_CIM_PLACE_N_MASK    (7U)
+#define SRCRSEL_CIM_PLACE_N_SHIFT   (4U)
+
+#define MIXRSEL_CIM_PLACE_N_MASK    (7U)
+#define MIXRSEL_CIM_PLACE_N_SHIFT   (4U)
+
+
+/* SSIF Register Set Value */
+/* Init Value */
+#define SCUX_SSICR_INIT_VALUE       (0x00000000U)
+#define SCUX_SSIFCR_INIT_VALUE      (0x00000000U)
+#define SCUX_SSIFTDR_INIT_VALUE     (0x00000000U)
+#define SCUX_SSITDMR_INIT_VALUE     (0x00000000U)
+#define SCUX_SSIFCCR_INIT_VALUE     (0x00000000U)
+#define SCUX_SSIFCMR_INIT_VALUE     (0x00000000U)
+
+/* SSIF bit value & mask & fixed setting */
+#define SCUX_SSICR_CKS_SET              (1U << 30)
+#define SCUX_SSICR_TUIEN_SET            (1U << 29)
+#define SCUX_SSICR_TOIEN_SET            (1U << 28)
+#define SCUX_SSICR_RUIEN_SET            (1U << 27)
+#define SCUX_SSICR_ROIEN_SET            (1U << 26)
+#define SCUX_SSICR_CHNL_SET_1CH         (0U << 22)
+#define SCUX_SSICR_CHNL_SET_2CH         (1U << 22)
+#define SCUX_SSICR_CHNL_SET_3CH         (2U << 22)
+#define SCUX_SSICR_CHNL_SET_4CH         (3U << 22)
+#define SCUX_SSICR_DWL_16BIT_SET        (1U << 19)
+#define SCUX_SSICR_DWL_24BIT_SET        (5U << 19)
+#define SCUX_SSICR_SWL_SHIFT            (16U)
+#define SCUX_SSICR_SCKD_SET             (1U << 15)
+#define SCUX_SSICR_SWSD_SET             (1U << 14)
+#define SCUX_SSICR_SCKP_SET             (1U << 13)
+#define SCUX_SSICR_SWSP_SET             (1U << 12)
+#define SCUX_SSICR_SPDP_SET             (1U << 11)
+#define SCUX_SSICR_SDTA_SET             (1U << 10)
+#define SCUX_SSICR_DEL_SET              (1U << 8)
+#define SCUX_SSICR_CKDV_SHIFT           (4U)
+#define SCUX_SSICR_TEN_SET              (1U << 1)
+
+#define SCUX_SSITDMR_CONT_SET           (1U << 8)
+#define SCUX_SSITDMR_TDM_SET            (1U << 0)
+
+/* SCUX fixed value */
+#define SCUX_RATE_CONVERT_CALC_VALUE     (0x400000U)
+#define SCUX_CALC_MINFS_VALUE            (100U)
+#define SCUX_MAX_DIV_CLK                 (2046U)
+#define SCUX_MIN_RATE_MIN_PAERCENTAGE    (90U)
+#define SCUX_MIN_RATE_MAX_PAERCENTAGE    (98U)
+#define SCUX_MIN_RATE_DENOMINATOR        (100U)
+#define SCUX_MAX_WAIT_TIME               (0xFFFFFFU)
+#define SCUX_MAX_DIGITAL_VOLUME          (0x7FFFFFU)
+#define SCUX_MAX_RAMP_VOLUME             (0x3FFU)
+#define SCUX_RATE_INT_CONV_VALUE         (1000U)
+#define SCUX_ADJUST_REST_VALUE           (1U)
+#define SCUX_MAX_CONV_RATE               (16000U)
+#define SCUX_MIN_CONV_RATE_NORMAL_CH1_2  (125U)
+#define SCUX_MIN_CONV_RATE_NORMAL_CH4    (250U)
+#define SCUX_MIN_CONV_RATE_NORMAL_CH6    (375U)
+#define SCUX_MIN_CONV_RATE_NORMAL_CH8    (500U)
+#define SCUX_MIN_CONV_RATE_DELAY1        (500U)
+#define SCUX_MIN_CONV_RATE_DELAY2        (1000U)
+#define SCUX_MIN_FREQ                    (1000U)
+#define SCUX_MAX_FREQ_CH1_4              (96000U)
+#define SCUX_MAX_FREQ_CH6                (66000U)
+#define SCUX_MAX_FREQ_CH8                (49000U)
+#define SCUX_PROC_DELAY_NONE             (0U)
+#define SCUX_PROCESS_DELAY_NORMAL_CH1    (641U)
+#define SCUX_PROCESS_DELAY_NORMAL_CH2    (321U)
+#define SCUX_PROCESS_DELAY_NORMAL_CH4    (161U)
+#define SCUX_PROCESS_DELAY_NORMAL_CH6    (102U)
+#define SCUX_PROCESS_DELAY_NORMAL_CH8    (81U)
+#define SCUX_PROCESS_DELAY_1_CH1_2       (81U)
+#define SCUX_PROCESS_DELAY_2_CH1_2       (49U)
+#define SCUX_LOGIC_DELAY_BYPASS_ON       (1U)
+#define SCUX_LOGIC_DELAY_BYPASS_OFF      (3U)
+#define SCUX_AUDIO_X1                    (22579200U)
+#define SCUX_AUDIO_CLK                   (0U)
+#define SCUX_MLB_CLK                     (66670000U)
+#define SCUX_USB_X1                      (48000000U)
+#define SCUX_CLKLP1_DIV2                 (33335000U)
+#define SCUX_SYSTEMWORD_16               (16U)
+#define SCUX_SYSTEMWORD_24               (24U)
+#define SCUX_SYSTEMWORD_32               (32U)
+#define SCUX_SYSTEMWORD_48               (48U)
+#define SCUX_SYSTEMWORD_64               (64U)
+#define SCUX_SYSTEMWORD_128              (128U)
+#define SCUX_SYSTEMWORD_256              (256U)
+#define SCUX_SSIF_CLK_DIV1               (1U)
+#define SCUX_SSIF_CLK_DIV2               (2U)
+#define SCUX_SSIF_CLK_DIV4               (4U)
+#define SCUX_SSIF_CLK_DIV8               (8U)
+#define SCUX_SSIF_CLK_DIV16              (16U)
+#define SCUX_SSIF_CLK_DIV32              (32U)
+#define SCUX_SSIF_CLK_DIV64              (64U)
+#define SCUX_SSIF_CLK_DIV128             (128U)
+#define SCUX_SSIF_CLK_DIV6               (6U)
+#define SCUX_SSIF_CLK_DIV12              (12U)
+#define SCUX_SSIF_CLK_DIV24              (24U)
+#define SCUX_SSIF_CLK_DIV48              (48U)
+#define SCUX_SSIF_CLK_DIV96              (96U)
+#define SCUX_SSIF_GPIO_SNCR_SHIFT_CH0    (0U)
+#define SCUX_SSIF_GPIO_SNCR_SHIFT_CH1    (1U)
+#define SCUX_SSIF_GPIO_SNCR_SHIFT_CH2    (2U)
+#define SCUX_SSIF_GPIO_SNCR_SHIFT_CH3    (3U)
+#define SCUX_SSIF_GPIO_SNCR_SHIFT_CH4    (4U)
+#define SCUX_SSIF_GPIO_SNCR_SHIFT_CH5    (5U)
+#define SCUX_DUMMY_BUF_SIZE              (4096U)
+#define SCUX_GET_ROUTE_MASK              (0xF000)
+#define SCUX_ROUTE_MEM_TO_MEM            (0x1000)
+#define SCUX_ROUTE_SSIF                  (0x2000)
+#define SCUX_ROUTE_MIX                   (0x3000)
+#define SCUX_FIFO_SIZE_CH0_1             (1024U)
+#define SCUX_FIFO_SIZE_CH2_3             (256U)
+#define SCUX_SSIF_NO_USE_CH              (0xFFFFU)
+#define SCUX_SSIF_USE_MIX_BIT            (0x1000U)
+#define SRC_MOD_SRC0                     (0U)
+#define SRC_MOD_SRC1                     (1U)
+#define SCUX_EVEN_VALUE_DIV              (2U)
+#define SCUX_SSIF_NUM_CH_ARRANGEMENT     (3U)
+#define SCUX_SSIF_CH_ARRANGEMENT1        (0U)
+#define SCUX_SSIF_CH_ARRANGEMENT2        (1U)
+#define SCUX_SSIF_CH_ARRANGEMENT3        (2U)
+#define SCUX_DMA_UNIT_SIZE16             (2U)
+#define SCUX_DMA_UNIT_SIZE24             (4U)
+#define SCUX_HALF_SIZE_VALUE             (2U)
+#define SCUX_RAMP_WAIT_MAX               (10U)
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+/* DRV Status */
+typedef enum
+{
+    SCUX_DRV_UNINIT = 0,   /* Uninit */
+#if(1) /* mbed */
+    SCUX_DRV_INIT_RUNNING = 1, /* Init running */
+    SCUX_DRV_INIT         = 2  /* Init */
+#else  /* not mbed */
+    SCUX_DRV_INIT   = 1    /* Init */
+#endif /* end mbed */
+} scux_stat_drv_t;
+
+/* Channel Status */
+typedef enum
+{
+    SCUX_CH_UNINIT         = 0,   /* Uninit */
+    SCUX_CH_INIT           = 1,   /* Init */
+    SCUX_CH_STOP           = 2,   /* Open (request can't be received) */
+    SCUX_CH_TRANS_IDLE     = 4,   /* Open (request is not received) */
+    SCUX_CH_TRANS_RD       = 8,   /* Transfer (read only) */
+    SCUX_CH_TRANS_WR       = 16,  /* Transfer (read only) */
+    SCUX_CH_TRANS_RDWR     = 32,  /* Transfer (read & write) */
+    SCUX_CH_STOP_WAIT      = 64,  /* Transfer (wait flush stop) */
+    SCUX_CH_STOP_WAIT_IDLE = 128  /* Transfer (wait flush stop and request is not received */
+} scux_stat_ch_t;
+
+/* fifo size */
+typedef enum
+{
+    SCUX_FIFO_REQ_SIZE_256_64 = 0, /* fifo size is 256 data (SRC0, 1) and 64 data (SRC2, 3) */
+    SCUX_FIFO_REQ_SIZE_128_32 = 1, /* fifo size is 128 data (SRC0, 1) and 32 data (SRC2, 3) */
+    SCUX_FIFO_REQ_SIZE_64_16  = 2, /* fifo size is 64 data (SRC0, 1) and 16 data (SRC2, 3) */
+    SCUX_FIFO_REQ_SIZE_32_8   = 3, /* fifo size is 32 data (SRC0, 1) and 8 data (SRC2, 3) */
+    SCUX_FIFO_REQ_SIZE_16_4   = 4, /* fifo size is 16 data (SRC0, 1) and 4 data (SRC2, 3) */
+    SCUX_FIFO_REQ_SIZE_8_2    = 5, /* fifo size is 8 data (SRC0, 1) and 2 data (SRC2, 3) */
+    SCUX_FIFO_REQ_SIZE_4_1    = 6, /* fifo size is 4 data (SRC0, 1) and 1 data (SRC2, 3) */
+    SCUX_FIFO_REQ_SIZE_2      = 7, /* fifo size is 2 data (SRC0, 1) */
+    SCUX_FIFO_REQ_SIZE_1      = 8  /* fifo size is 1 data (SRC0, 1) */
+} scux_fifo_req_size_t;
+
+/* SSIF over sampling clock divide rate */
+typedef enum
+{
+    SCUX_SSIF_CKDIV_1      = 0,   /* divide rate 1/1 */
+    SCUX_SSIF_CKDIV_2      = 1,   /* divide rate 1/2 */
+    SCUX_SSIF_CKDIV_4      = 2,   /* divide rate 1/4 */
+    SCUX_SSIF_CKDIV_8      = 3,   /* divide rate 1/8 */
+    SCUX_SSIF_CKDIV_16     = 4,   /* divide rate 1/16 */
+    SCUX_SSIF_CKDIV_32     = 5,   /* divide rate 1/32 */
+    SCUX_SSIF_CKDIV_64     = 6,   /* divide rate 1/64 */
+    SCUX_SSIF_CKDIV_128    = 7,   /* divide rate 1/128 */
+    SCUX_SSIF_CKDIV_6      = 8,   /* divide rate 1/6 */
+    SCUX_SSIF_CKDIV_12     = 9,   /* divide rate 1/12 */
+    SCUX_SSIF_CKDIV_24     = 10,  /* divide rate 1/24 */
+    SCUX_SSIF_CKDIV_48     = 11,  /* divide rate 1/48 */
+    SCUX_SSIF_CKDIV_96     = 12   /* divide rate 1/96 */
+} scux_ssif_ckdiv_t;
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+
+/* Information of SCUX register */
+typedef struct
+{
+    struct st_scux_from_dvuir_dvu0_n            *p_dvu_reg;      /* DVU register */
+    struct st_scux_from_srcir0_2src0_n          *p_src_reg;      /* SRC register */
+    struct st_scux_from_ffuir_ffu0_n            *p_ffu_reg;      /* FFU register */
+    struct st_scux_from_ffdir_ffd0_n            *p_ffd_reg;      /* FFD register */
+    struct st_scux_from_opcir_opc0_n            *p_opc_reg;      /* OPC register */
+    struct st_scux_from_ipcir_ipc0_n            *p_ipc_reg;      /* IPC register */
+    volatile uint32_t                           *mixir_mix0_0;   /* MIXIR_MIX0_0 register */
+    volatile uint32_t                           *madir_mix0_0;   /* MADIR_MIX0_0 register */
+    volatile uint32_t                           *mixbr_mix0_0;   /* MIXBR_MIX0_0 register */
+    volatile uint32_t                           *mixmr_mix0_0;   /* MIXMR_MIX0_0 register */
+    volatile uint32_t                           *mvpdr_mix0_0;   /* MVPDR_MIX0_0 register */
+    volatile uint32_t                           *mdb_n_r_mix0_0; /* MDBAR_MIX0_0 - MDBDR_MIX0_0 register */
+    volatile uint32_t                           *mdber_mix0_0;   /* MDBER_MIX0_0 register */
+    volatile uint32_t                           *mixsr_mix0_0;   /* MIXSR_MIX0_0 register */
+    volatile uint32_t                           *swrsr_cim;      /* SWRSR_CIM register */
+    volatile uint32_t                           *dmacr_cim;      /* DMACR_CIM register */
+    volatile uint32_t                           *dmatd_n_cim;    /* DMATD0_CIM - DMATD3_CIM register */
+    volatile uint32_t                           *dmatu_n_cim;    /* DMATU0_CIM - DMATU3_CIM register */
+    volatile uint32_t                           *ssirsel_cim;    /* SSIRSEL_CIM register */
+    volatile uint32_t                           *fdtsel_n_cim;   /* FDTSEL0_CIM - FDTSEL3_CIM register */
+    volatile uint32_t                           *futsel_n_cim;   /* FUTSEL0_CIM - FUTSEL3_CIM register */
+    volatile uint32_t                           *ssipmd_cim;     /* SSIPMD_CIM register */
+    volatile uint32_t                           *ssictrl_cim;    /* SSICTRL_CIM register */
+    volatile uint32_t                           *srcrsel_n_cim;  /* SRCRSEL0_CIM - SRCRSEL3_CIM register */
+    volatile uint32_t                           *mixrsel_cim;    /* MIXRSEL_CIM register */
+} scux_reg_info_t;
+
+/* Information of SSIF */
+typedef struct
+{
+    bool_t                  ssif_enable;              /* USE SSIF flag */
+    bool_t                  ssif_setup;               /* SSIF setup complete flag */
+    osSemaphoreId           sem_ch_scux_ssif_access;  /* SSIF info semaphore */
+    int_t                   scux_channel;             /* SCUX ch which is using SSIF */
+    scux_src_clk_source_t   pin_clk;                  /* AUDIO_CLK source */
+    scux_pin_mode_t         pin_mode;                 /* SSIF sync setting */
+    scux_pin_mode_t         pin_mode_backup;          /* back up of SSIF sync setting */
+    scux_ssif_cfg_t         ssif_cfg;                 /* SSIF parameters */
+    scux_ssif_ckdiv_t       clk_div;                  /* Over sampling clock divide rate */
+    volatile struct st_ssif *p_scux_ssif_reg;         /* SSIF register */
+} scux_ssif_info_t;
+
+/* Information of Driver */
+typedef struct
+{
+    osSemaphoreId        sem_shared_access;        /* Shared info semaphore */
+    bool_t               mix_setup;                /* MIX setup complete flag */
+    uint32_t             mix_run_ch;               /* MIX used channel */
+    uint32_t             mix_ssif_ch;              /* SSIF channel on used MIX */
+    bool_t               mixmode_ramp;             /* Ramp mode / Step mode select */
+    scux_mix_ramp_time_t up_period;                /* Ramp up period */
+    scux_mix_ramp_time_t down_period;              /* Ramp down period */
+    uint32_t             mix_vol[SCUX_CH_NUM];     /* MIX volume value */
+    scux_audio_channel_t select_out_data_ch[SCUX_AUDIO_CH_MAX]; /* Audio data position setting */
+    uint32_t             ssictrl_cim_value;        /* SSICTRL_CIM register (write only) value */
+} scux_shared_info_t;
+
+/* Information of Channel */
+typedef struct
+{
+    int_t              channel;                    /* Channel Number */
+    bool_t             enabled;                    /* Used channel flag */
+    int_t              open_flags;                 /* Read/write flag */
+    scux_stat_ch_t     ch_stat;                    /* Channel Status */
+    osSemaphoreId      sem_ch_scux_access;         /* Channel Semaphore */
+    AHF_S              tx_que;                     /* Write request queue */
+    AHF_S              rx_que;                     /* Read request queue */
+    AIOCB              *p_tx_aio;                  /* Write request information pointer */
+    AIOCB              *p_tx_next_aio;             /* Next write request information pointer */ 
+    AIOCB              *p_rx_aio;                  /* Read request information pointer */
+    AIOCB              *p_rx_next_aio;             /* Next read request information pointer */ 
+    uint8_t            int_level;                  /* Interrupt priority */
+    IRQn_Type          int_num[SCUX_INT_MAX];      /* Each interrupt number */
+    int_t              dma_tx_ch;                  /* Write DMA channel */
+    int_t              dma_rx_ch;                  /* Read DMA channel */
+    dma_res_select_t   dma_resource_tx;            /* Write DMA resource */
+    dma_res_select_t   dma_resource_rx;            /* Read DMA resource */
+    uint32_t           dma_tx_current_size;        /* Current write DMA size */
+    uint32_t           dma_tx_next_size;           /* Next write DMA size */
+    uint32_t           dma_rx_current_size;        /* Current read DMA size */
+    uint32_t           dma_rx_next_size;           /* Next read DMA size */
+    dma_ch_setup_t     dma_tx_setup;               /* Write DMA paramtter */
+    dma_ch_setup_t     dma_rx_setup;               /* Read DMA paramtter */
+    scux_reg_info_t    *p_scux_reg;                /* SCUX register information */
+    scux_route_t       route_set;                  /* SCUX route paramter */
+    scux_src_cfg_t     src_cfg;                    /* SRC parameter */
+    scux_dvu_cfg_t     dvu_cfg;                    /* DVU parameter */
+    bool_t             dvu_setup;                  /* DVU setup complete flag */
+    uint32_t           dvu_mute_stat;              /* DVU mute status */
+    scux_ssif_info_t   *p_ssif_info1;              /* SSIF channel information1  */
+    scux_ssif_info_t   *p_ssif_info2;              /* SSIF channel information2  */
+    scux_ssif_info_t   *p_ssif_info3;              /* SSIF channel information3  */
+    void               (*p_flush_callback)(int_t ercd);   /* Call back pointer for flush stop */
+    bool_t             first_tx_flag;              /* First write data transfer flag */
+    bool_t             first_rx_flag;              /* First read data transfer flag */    
+    bool_t             first_ramp_flag;            /* First ramp setting flag */
+    volatile uint8_t   *p_tx_dummy_data;           /* Write dummy data buffer pointer */
+    volatile uint8_t   *p_rx_dummy_data;           /* Read dummy data buffer pointer */
+    uint32_t           flush_stop_size;            /* Needed transfer size for flush stop */ 
+    uint32_t           fifo_size;                  /* Fifo size */
+    uint32_t           fifo_req_size;              /* Fifo request size */
+    uint32_t           last_dummy_size;            /* Last dummy data size for flush stop */
+    uint32_t           tx_fifo_total_size;         /* Total data size of write request size / FIFO size */
+    uint32_t           rx_fifo_total_size;         /* Total data size of read request size / FIFO size */
+    bool_t             tx_dummy_run_flag;          /* Dummy data transfer flag */
+    bool_t             cancel_operate_flag;        /* indicate cancel operation */
+    bool_t             restart_ramp_flag;          /* ramp restart flag after cancel operation */
+    uint32_t           input_rate;                 /* Input rate */
+    uint32_t           output_rate;                /* Output rate */
+    uint32_t           futsel_cim_value;           /* FUTSEL_CIM register value (write only) */
+    int_t              err_stat_backup;            /* SCUX HW error status backup */
+} scux_info_ch_t;
+
+/* Information of Driver */
+typedef struct
+{
+    scux_stat_drv_t    drv_stat;              /* DRV status */
+    scux_info_ch_t     info_ch[SCUX_CH_NUM];  /* CH status */
+    scux_shared_info_t shared_info;           /* shared resource information */
+} scux_info_drv_t;
+
+/***********************************************************************************
+ Function Prototypes
+***********************************************************************************/
+
+scux_info_drv_t *SCUX_GetDrvInstance(void);
+scux_info_ch_t  *SCUX_GetDrvChInfo(const int_t channel);
+scux_ssif_info_t *SCUX_GetSsifChInfo(const int_t channel);
+#if(1) /* mbed */
+int_t SCUX_InitializeOne(const int_t channel, const scux_channel_cfg_t * const p_scux_init_param);
+void SCUX_UnInitializeOne(const int_t channel);
+#else  /* not mbed */
+int_t SCUX_Initialize(const scux_channel_cfg_t * const p_scux_init_param);
+void SCUX_UnInitialize(void);
+#endif /* end mbed */
+int_t SCUX_OpenChannel(const int_t channel, const int_t flags);
+int_t SCUX_CloseChannel(const int_t channel);
+int_t SCUX_IoctlTransStart(const int_t channel);
+int_t SCUX_IoctlFlushStop(const int_t channel, void (* const callback)(int_t ercd), const int_t was_masked);
+int_t SCUX_IoctlClearStop(const int_t channel, const int_t was_masked);
+void SCUX_IoctlSetRoute(const int_t channel, const scux_route_t route);
+int_t SCUX_IoctlSetPinClk(const int_t channel, const scux_ssif_pin_clk_t * const p_pin_clk_param);
+int_t SCUX_IoctlSetPinMode(const int_t channel, const scux_ssif_pin_mode_t * const p_pin_mode_param);
+void SCUX_IoctlSetSrcCfg(const int_t channel, const scux_src_cfg_t * const p_src_param);
+void SCUX_IoctlSetDvuCfg(const int_t channel, const scux_dvu_cfg_t * const p_dvu_param);
+int_t SCUX_IoctlSetDvuDigiVol(const int_t channel, const scux_dvu_digi_vol_t * const p_digi_vol_param);
+int_t SCUX_IoctlSetDvuRampVol(const int_t channel, const scux_dvu_ramp_vol_t * const p_ramp_vol_param);
+int_t SCUX_IoctlSetDvuZerocrossMute(const int_t channel, const scux_zc_mute_t * const p_zc_mute_param);
+int_t SCUX_IoctlSetStopMute(const int_t channel, const uint32_t audio_channel);
+int_t SCUX_IoctlSetMixCfg(const scux_mix_cfg_t * const p_mix_param);
+int_t SCUX_IoctlSetMixVol(const int_t channel, const uint32_t mix_vol);
+int_t SCUX_IoctlSetSsifCfg(const scux_ssif_cfg_t *const p_ssif_param);
+void SCUX_IoctlGetWriteStat(const int_t channel, uint32_t * const p_write_stat);
+void SCUX_IoctlGetReadStat(const int_t channel, uint32_t * const p_read_stat);
+void SCUX_IoctlGetDvuStat(const int_t channel, uint32_t * const p_dvu_stat);
+void SCUX_IoctlGetMuteStat(const int_t channel, uint32_t * const p_mute_stat);
+void SCUX_IoctlGetMixStat(const int_t channel, uint32_t * const p_mix_stat);
+int_t SCUX_CheckParam(scux_info_ch_t * const p_scux_info_ch);
+int_t SCUX_FlushWriteStart(scux_info_ch_t * const p_scux_info_ch);
+void SCUX_InitHw(scux_info_ch_t * const p_scux_info_ch);
+void SCUX_SetupSsif(const scux_info_ch_t * const p_scux_info_ch);
+void SCUX_SetupSrc(scux_info_ch_t * const p_scux_info_ch);
+void SCUX_SetupDvu(scux_info_ch_t * const p_scux_info_ch);
+int_t SCUX_SetupDma(scux_info_ch_t * const p_scux_info_ch);
+void  SCUX_SyncStartHw(const scux_info_ch_t * const p_scux_info_ch);
+void SCUX_AsyncStartHw(scux_info_ch_t * const p_scux_info_ch);
+int_t SCUX_CopyWriteStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_write_aio);
+int_t SCUX_DirectWriteStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_write_aio);
+int_t SCUX_CopyReadStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_read_aio);
+int_t SCUX_CopyCancelSpecific(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_cancel_aio);
+int_t SCUX_DirectCancelSpecific(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_cancel_aio);
+int_t SCUX_CopyCancelAll(scux_info_ch_t * const p_scux_info_ch);
+int_t SCUX_DirectCancelAll(scux_info_ch_t * const p_scux_info_ch);
+void SCUX_AdjustAccessFifo(scux_info_ch_t * const p_scux_info_ch, const uint32_t tx_remain_size, const uint32_t rx_remain_size);
+void  SCUX_SyncStartHw(const scux_info_ch_t * const p_scux_info_ch);
+void SCUX_AsyncStartHw(scux_info_ch_t * const p_scux_info_ch);
+void  SCUX_SyncStopHw(const scux_info_ch_t * const p_scux_info_ch);
+void  SCUX_AsyncStopHw(scux_info_ch_t * const p_scux_info_ch);
+void SCUX_SetDigiVolRegister(const scux_info_ch_t * const p_scux_info_ch);
+void SCUX_SetRampVolRegister(scux_info_ch_t * const p_scux_info_ch);
+void SCUX_SetZerocrossMuteRegister(const scux_info_ch_t * const p_scux_info_ch);
+void SCUX_SetMixVolRegister(const int_t channel);
+int_t SCUX_CheckSsifClockDiv(const scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch_num);
+void SCUX_SetupSsifGpio(const scux_ssif_ch_num_t ssif_ch);
+size_t SCUX_StrNLen(const char_t* p_str, size_t maxlen);
+
+#endif /* SCUX_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_src/scux/scux_board.c	Fri Oct 02 03:03:25 2015 +0000
@@ -0,0 +1,564 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         scux_board.c
+* $Rev: 891 $
+* $Date:: 2014-06-27 10:40:52 +0900#$
+* @brief        SCUX functions depending on borad 
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+
+#include "scux.h"
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CheckSsifClockDiv
+* @brief         Check SSIF clock divide rate.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @param[in]     ssif_ch : Used ssif channel number.
+* @retval        ESUCCESS : Parameter is no problems.
+*                EPERM : Parameter is unexpected value.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_CheckSsifClockDiv(const scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch_num)
+{
+    int_t retval = ESUCCESS;
+    uint32_t input_clk;
+    uint32_t dot_clk;
+    uint32_t n_syswd_per_smp;
+    uint32_t syswd_len =0;
+    uint32_t smp_freq;
+    uint32_t result;
+    uint32_t division;
+    scux_ssif_info_t * p_ssif_ch;
+    
+    p_ssif_ch = SCUX_GetSsifChInfo((int_t)ssif_ch_num);
+
+    if ((NULL == p_scux_info_ch) || (NULL == p_ssif_ch))
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        if (false == p_ssif_ch->ssif_cfg.mode_master)
+        {
+            /* In slave mode, a temporary value is to SCUX_SSIF_CKDIV_1 (0) */
+            p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_1;         
+        }
+        else
+        {
+            /* check only SSIF master mode */
+            /* get source clock */
+            if (false == p_ssif_ch->ssif_cfg.select_audio_clk)
+            {
+                input_clk = SCUX_AUDIO_X1;
+            }
+            else
+            {
+                input_clk = SCUX_AUDIO_CLK;
+            }
+            
+            if (0u == input_clk)
+            {
+                retval = EPERM;
+            }
+        
+            if (ESUCCESS == retval)
+            {
+                switch (p_ssif_ch->ssif_cfg.system_word)
+                {
+                    case SCUX_SSIF_SYSTEM_LEN_16 :
+                        syswd_len = SCUX_SYSTEMWORD_16;
+                    break;
+                    
+                    case SCUX_SSIF_SYSTEM_LEN_24 :
+                        syswd_len = SCUX_SYSTEMWORD_24;
+                    break;
+        
+                    case SCUX_SSIF_SYSTEM_LEN_32 :
+                        syswd_len = SCUX_SYSTEMWORD_32;
+                    break;
+        
+                    case SCUX_SSIF_SYSTEM_LEN_48 :
+                        syswd_len = SCUX_SYSTEMWORD_48;
+                    break;
+                            
+                    case SCUX_SSIF_SYSTEM_LEN_64 :
+                        syswd_len = SCUX_SYSTEMWORD_64;
+                    break;
+        
+                    case SCUX_SSIF_SYSTEM_LEN_128 :
+                        syswd_len = SCUX_SYSTEMWORD_128;
+                    break;
+        
+                    case SCUX_SSIF_SYSTEM_LEN_256 :
+                        syswd_len = SCUX_SYSTEMWORD_256;
+                    break;
+                            
+                    default :
+                        retval = EPERM;
+                    break;
+                }
+        
+                smp_freq = p_scux_info_ch->src_cfg.output_ws;
+            
+                if (false == p_ssif_ch->ssif_cfg.use_tdm)
+                {
+                    n_syswd_per_smp = SCUX_USE_CH_2;
+                }
+                else
+                {
+                    n_syswd_per_smp = p_scux_info_ch->src_cfg.use_ch;
+                }
+        
+                dot_clk = syswd_len * n_syswd_per_smp * smp_freq;
+                if (0u == dot_clk)
+                {
+                    retval = EPERM;
+                }
+                else
+                {
+                    /* check if input audio clock can be divided by dotclock */
+                    result = input_clk % dot_clk;
+        
+                    if (0U != result)
+                    {
+                        /* cannot create dotclock from input audio clock */
+                        retval = EPERM;
+                    }
+                    else
+                    {
+                        division = input_clk / dot_clk;
+        
+                        switch (division)
+                        {
+                            case SCUX_SSIF_CLK_DIV1:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_1;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV2:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_2;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV4:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_4;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV8:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_8;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV16:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_16;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV32:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_32;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV64:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_64;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV128:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_128;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV6:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_6;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV12:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_12;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV24:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_24;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV48:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_48;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV96:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_96;
+                            break;
+                            
+                            default:
+                                retval = EPERM;
+                            break;
+                        }
+                    }
+                }
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CheckSsifClockDiv
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetupSsifGpio
+* @brief         GPIO of SSIF module setup.
+
+*                Description:<br>
+*                R7S72100 Boards depended pin connections bellow<br>
+*                Clock settings<br>
+*                  AUDIO_X1 : Private use pin(nothing to do)<br>
+*                  AUDIO_X2 : No connection<br>
+*                  AUDIO_CLK: Working with SSIF5<br>
+*                Channel settings<br>
+*                  SSIF0    : Fully connected to WM8978<br>
+*                  SSIF1    : Read only (NC:SSITxD1) connected to CD Deck<br>
+*                  SSIF2    : No connection<br>
+*                  SSIF3    : Write only (NC:SSIRxD3) connected to AK4353<br>
+*                  SSIF4    : Fully connected to AK4353<br>
+*                  SSIF5    : Fully connected to HCI
+*                
+* @param[in]     ssif_ch :SSIF channel number.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_SetupSsifGpio(const scux_ssif_ch_num_t ssif_ch)
+{
+    switch (ssif_ch)
+    {
+        case SCUX_SSIF_CH_0:
+            /* SSISCK0(P4_4, Alternative Mode 5,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N4);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS0(P4_5, Alternative Mode 5,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N5);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIRxD0(P4_6, Alternative Mode 5,Input) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N6);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N6);
+
+            /* SSITxD0(P4_7, Alternative Mode 5,Output) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N7);
+
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N7);
+
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PM4    &= (uint16_t)~(GPIO_BIT_N7);
+        break;
+
+        case SCUX_SSIF_CH_1:
+            /* SSISCK1(P3_4, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC3  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC3   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCE3  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCAE3 &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PIPC3  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS1(P3_5, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC3  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC3   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCE3  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCAE3 &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PIPC3 |=  (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIRxD1(P3_6, Alternative Mode 3,Input) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFC3   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCE3  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCAE3 &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PIPC3  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N6);
+
+            /* SSITxD1:  no connection */
+        break;
+
+        case SCUX_SSIF_CH_2:
+            /* SSISCK2:  no connection */
+            /* SSIWS2:   no connection */
+            /* SSIDATA2: no connection */
+            break;
+
+        case SCUX_SSIF_CH_3:
+            /* SSISCK3(P4_12, Alternative Mode 6,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N12);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PFC4   |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N12);
+
+            GPIO.PIPC4  |= (uint16_t) GPIO_BIT_N12;
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N12);
+
+            /* SSIWS3(P4_13, Alternative Mode 6,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N13);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PFC4   |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N13);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N13);
+
+            /* SSIRxD3:  no connection */
+
+            /* SSITxD3(P4_15, Alternative Mode 6,Output) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N15);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N15);
+
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PFC4   |= (uint16_t) (GPIO_BIT_N15);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N15);
+
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N15);
+            GPIO.PM4    &= (uint16_t)~(GPIO_BIT_N15);
+        break;
+
+        case SCUX_SSIF_CH_4:
+            /* SSISCK4(P11_4, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC11  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC11  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM11    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC11   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC11  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC11  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC11   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCE11  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCAE11 &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PIPC11  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC11   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS4(P11_5, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC11  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC11  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM11    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC11   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC11  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC11  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC11   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCE11  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCAE11 &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PIPC11  |= (uint16_t) GPIO_BIT_N5;
+            GPIO.PMC11   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIDATA4(P11_6, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC11  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC11  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM11    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC11   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC11  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC11  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFC11   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCE11  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCAE11 &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PIPC11  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC11   |= (uint16_t) (GPIO_BIT_N6);
+        break;
+
+        case SCUX_SSIF_CH_5:
+            /* SSISCK5(P2_4, Alternative Mode 4,InputOutput) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC2  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PIPC2  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS5(P2_5, Alternative Mode 4,InputOutput) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC2  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PIPC2  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIRxD5(P2_6, Alternative Mode 4,Input) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PIPC2  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N6);
+
+            /* SSITxD5(P2_7, Alternative Mode 4,Output) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N7);
+
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N7);
+
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PM2    &= (uint16_t)~(GPIO_BIT_N7);
+
+            /* AUDIO_CLK(P3_1, Alternative Mode 6,Input) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N1);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N1);
+
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PFC3   |= (uint16_t) (GPIO_BIT_N1);
+            GPIO.PFCE3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PFCAE3 |= (uint16_t) (GPIO_BIT_N1);
+
+            GPIO.PIPC3  |= (uint16_t) (GPIO_BIT_N1);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N1);
+        break;
+
+        default:
+            /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+            /* <-IPA R3.5.2 */
+            /* NOTREACHED on At the time of a normal performance */
+        break;
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupSsifGpio
+******************************************************************************/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_src/scux/scux_dev.c	Fri Oct 02 03:03:25 2015 +0000
@@ -0,0 +1,4832 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         scux_dev.c
+* $Rev: 1674 $
+* $Date:: 2015-05-29 16:35:57 +0900#$
+* @brief        SCUX device control functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+
+#include "scux.h"
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global driver management information
+******************************************************************************/
+
+/* SSIF clock mask register table define */
+static const uint32_t gb_cpg_scux_ssif_stbcr_bit[SCUX_SSIF_CH_NUM] = 
+{ 
+    CPG_STBCR11_BIT_MSTP115,    /* SSIF0 */
+    CPG_STBCR11_BIT_MSTP114,    /* SSIF1 */
+    CPG_STBCR11_BIT_MSTP113,    /* SSIF2 */
+    CPG_STBCR11_BIT_MSTP112,    /* SSIF3 */
+    CPG_STBCR11_BIT_MSTP111,    /* SSIF4 */
+    CPG_STBCR11_BIT_MSTP110     /* SSIF5 */
+};
+
+/* SSIF software reset register table define */
+static const uint32_t gb_cpg_scux_ssif_swrst_bit[SCUX_SSIF_CH_NUM] = 
+{ 
+    CPG_SWRSTCR1_BIT_SRST16,    /* SSIF0 */
+    CPG_SWRSTCR1_BIT_SRST15,    /* SSIF1 */
+    CPG_SWRSTCR1_BIT_SRST14,    /* SSIF2 */
+    CPG_SWRSTCR1_BIT_SRST13,    /* SSIF3 */
+    CPG_SWRSTCR1_BIT_SRST12,    /* SSIF4 */
+    CPG_SWRSTCR1_BIT_SRST11     /* SSIF5 */
+};
+
+/* SSIF noise cancel register table define */
+static const uint32_t gb_cpg_scux_ssif_sncr_bit[SCUX_SSIF_CH_NUM] = 
+{ 
+    SCUX_SSIF_GPIO_SNCR_SHIFT_CH0,  /* SSIF0 */
+    SCUX_SSIF_GPIO_SNCR_SHIFT_CH1,  /* SSIF1 */
+    SCUX_SSIF_GPIO_SNCR_SHIFT_CH2,  /* SSIF2 */
+    SCUX_SSIF_GPIO_SNCR_SHIFT_CH3,  /* SSIF3 */
+    SCUX_SSIF_GPIO_SNCR_SHIFT_CH4,  /* SSIF4 */
+    SCUX_SSIF_GPIO_SNCR_SHIFT_CH5   /* SSIF5 */
+};
+
+/* AIOCB information for DMA */
+static AIOCB gb_scux_write_dma_aio[SCUX_CH_NUM];
+static AIOCB gb_scux_read_dma_aio[SCUX_CH_NUM];
+
+/******************************************************************************
+ Function prototypes
+******************************************************************************/
+ 
+static void  SCUX_SetupDataPosition(scux_info_ch_t * const p_scux_info_ch);
+static void  SCUX_SetupSrcClk(scux_info_ch_t * const p_scux_info_ch);
+static void  SCUX_SetupFifo(scux_info_ch_t * const p_scux_info_ch);
+static void  SCUX_SetupSrcFunction(scux_info_ch_t * const p_scux_info_ch);
+static void  SCUX_SetupDvuVolume(scux_info_ch_t * const p_scux_info_ch);
+static void  SCUX_SetupMix(scux_info_ch_t * const p_scux_info_ch);
+static void  SCUX_DMA_CopyRxCallBack(union sigval const param);
+static void  SCUX_DMA_CommonTxNextDummyData(scux_info_ch_t * const p_info_ch);
+static void  SCUX_DMA_CopyTxEndFlush(scux_info_ch_t * const p_info_ch);
+static void  SCUX_DMA_CopyTxNextRemainData(scux_info_ch_t * const p_info_ch);
+static void  SCUX_DMA_CopyTxNextData(scux_info_ch_t * const p_info_ch);
+static void  SCUX_DMA_CopyTxCallBack(union sigval const param);
+static void  SCUX_DMA_DirectTxEndFlush(scux_info_ch_t * const p_info_ch);
+static void  SCUX_DMA_DirectTxNextRemainData(scux_info_ch_t * const p_info_ch);
+static void  SCUX_DMA_DirectTxNextData(scux_info_ch_t * const p_info_ch);
+static void  SCUX_DMA_DirectTxCallBack(union sigval const param);
+
+/**************************************************************************//**
+* Function Name: SCUX_CopyWriteStart
+* @brief         Start write request (mem->mem).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch:SCUX channel information.
+* @param[in]     *p_write_aio:Write request information.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_CopyWriteStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_write_aio)
+{
+    int_t    retval;
+    int_t    dma_retval;
+    dma_trans_data_t dma_address_param;
+    uint32_t         dma_src_addr;
+    int_t            ret;
+    
+    if ((NULL == p_scux_info_ch) || (NULL == p_write_aio))
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        retval = R_DMA_Setup(p_scux_info_ch->dma_tx_ch, &p_scux_info_ch->dma_tx_setup, NULL);
+        
+        if (ESUCCESS != retval)
+        {
+            retval = EFAULT;
+        }
+        else
+        {
+            /* set first trans information */
+            p_scux_info_ch->p_tx_aio = p_write_aio;
+            p_scux_info_ch->p_tx_next_aio = NULL;
+            p_scux_info_ch->first_tx_flag = false;
+                
+            /* cast uint8_t pointer from void pointer */
+            dma_src_addr = (uint32_t)p_write_aio->aio_buf;
+                
+            /* set 1st DMA parameter */
+            dma_address_param.src_addr = (void *)dma_src_addr;
+            dma_address_param.dst_addr = (void *)p_scux_info_ch->p_scux_reg->dmatd_n_cim;
+            dma_address_param.count = p_write_aio->aio_nbytes;
+                
+            dma_retval = R_DMA_Start(p_scux_info_ch->dma_tx_ch, &dma_address_param, &ret);
+            if (ESUCCESS != dma_retval)
+            {
+                retval = EFAULT;
+            }
+            else
+            {
+                p_scux_info_ch->dma_tx_current_size = dma_address_param.count;
+                /* enable interrupt */
+                p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = (DEVMR_FFD0_DEVMUF_SET | 
+                                                                       DEVMR_FFD0_DEVMOF_SET | 
+                                                                       DEVMR_FFD0_DEVMOL_SET | 
+                                                                       DEVMR_FFD0_DEVMIUF_SET);
+                p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE;
+                /* start clock devide on async mode */
+                if (false == p_scux_info_ch->src_cfg.mode_sync) 
+                {
+                    if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async) && 
+                        (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.input_clk_async))
+                    {
+                        *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) |= FDTSEL_CIM_DIVEN_SET;
+                    }
+                }
+                /* update channel status */
+                switch (p_scux_info_ch->ch_stat)
+                {
+                    case SCUX_CH_UNINIT :
+                        /* fall through */
+                    case SCUX_CH_INIT :
+                        /* fall through */
+                    case SCUX_CH_STOP :
+                        retval = EBADF;
+                    break;                  
+                    
+                    case SCUX_CH_TRANS_IDLE :
+                        p_scux_info_ch->ch_stat = SCUX_CH_TRANS_WR;
+                    break;
+                    
+                    case SCUX_CH_TRANS_RD :
+                        p_scux_info_ch->ch_stat = SCUX_CH_TRANS_RDWR;
+                    break;
+                    
+                    case SCUX_CH_TRANS_WR :
+                        /* fall through */
+                    case SCUX_CH_TRANS_RDWR :
+                        /* fall through */
+                    case SCUX_CH_STOP_WAIT :
+                        /* fall through */
+                    case SCUX_CH_STOP_WAIT_IDLE :
+                        /* do nothing, stats isn't updated */
+                    break;
+                    
+                    default :
+                        retval = EFAULT;
+                        /* NOTREACHED on At the time of a normal performance */
+                    break;
+                }
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CopyWriteStart
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DirectWriteStart
+* @brief         Start write request(SSIF direct route).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch:SCUX channel information.
+* @param[in]     *p_write_aio:Write request information.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_DirectWriteStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_write_aio)
+{
+    int_t    retval;
+    int_t    dma_retval;
+    dma_trans_data_t dma_address_param;
+    dma_trans_data_t next_dma_address_param;
+    uint32_t         dma_src_addr;
+    int_t            ret;
+    uint32_t         ramp_wait_cnt = 0;
+    
+    if ((NULL == p_scux_info_ch) || (NULL == p_write_aio))
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        retval = R_DMA_Setup(p_scux_info_ch->dma_tx_ch, &p_scux_info_ch->dma_tx_setup, NULL);
+        
+        if (ESUCCESS != retval)
+        {
+            retval = EFAULT;
+        }
+        else
+        {
+            /* set first trans information */
+            p_scux_info_ch->p_tx_aio = NULL;
+            p_scux_info_ch->p_tx_next_aio = p_write_aio;
+            p_scux_info_ch->first_tx_flag = true;
+            
+            /* cast uint8_t pointer from void pointer */
+            dma_src_addr = (uint32_t)p_write_aio->aio_buf;
+            
+            /* set 2nd DMA parameter */
+            next_dma_address_param.src_addr = (void *)(dma_src_addr + (p_write_aio->aio_nbytes / SCUX_HALF_SIZE_VALUE));
+            next_dma_address_param.dst_addr = (void *)p_scux_info_ch->p_scux_reg->dmatd_n_cim;
+            next_dma_address_param.count = (p_write_aio->aio_nbytes / SCUX_HALF_SIZE_VALUE);
+            if (0U != (p_write_aio->aio_nbytes % SCUX_HALF_SIZE_VALUE))
+            {
+                /* last data ,when even value size */
+                next_dma_address_param.count++;
+            }
+            dma_retval = R_DMA_NextData(p_scux_info_ch->dma_tx_ch, &next_dma_address_param, &ret);
+            
+            if (ESUCCESS != dma_retval)
+            {
+                retval = EFAULT;
+            }
+            else
+            {
+                p_scux_info_ch->dma_tx_next_size = next_dma_address_param.count;
+                /* set 1st DMA parameter */
+                dma_address_param.src_addr = (void *)dma_src_addr;
+                dma_address_param.dst_addr = (void *)p_scux_info_ch->p_scux_reg->dmatd_n_cim;
+                dma_address_param.count = (p_write_aio->aio_nbytes / SCUX_HALF_SIZE_VALUE);
+            
+                dma_retval = R_DMA_Start(p_scux_info_ch->dma_tx_ch, &dma_address_param, &ret);
+                if (ESUCCESS != dma_retval)
+                {
+                    retval = EFAULT;
+                }
+                else
+                {
+                    p_scux_info_ch->dma_tx_current_size = dma_address_param.count;
+                    /* enable interrupt */
+                    p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = (DEVMR_FFD0_DEVMUF_SET | 
+                                                                           DEVMR_FFD0_DEVMOF_SET | 
+                                                                           DEVMR_FFD0_DEVMOL_SET | 
+                                                                           DEVMR_FFD0_DEVMIUF_SET);
+                    p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE;
+                    *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) |= FDTSEL_CIM_DIVEN_SET;
+                    
+                    switch (p_scux_info_ch->ch_stat)
+                    {
+                        case SCUX_CH_UNINIT :
+                            /* fall through */
+                        case SCUX_CH_INIT :
+                            /* fall through */
+                        case SCUX_CH_STOP :
+                            /* fall through */
+                            retval = EBADF;
+                        break;
+                    
+                        case SCUX_CH_TRANS_IDLE :
+                            p_scux_info_ch->ch_stat = SCUX_CH_TRANS_WR;
+                        break;   
+                        
+                        case SCUX_CH_TRANS_RD :
+                            /* read function disabled */
+                            retval = EFAULT;
+                        break;                 
+                    
+                        case SCUX_CH_TRANS_WR :
+                            /* do nothing, stats isn't updated */
+                        break;                        
+                        
+                        case SCUX_CH_TRANS_RDWR :
+                            /* read function disabled */
+                            retval = EFAULT;
+                        break;                          
+                        
+                        case SCUX_CH_STOP_WAIT :
+                            /* do nothing, stats isn't updated */
+                        break;
+                    
+                        case SCUX_CH_STOP_WAIT_IDLE :
+                            /* read function disabled */
+                            retval = EFAULT;
+                        break; 
+                    
+                        default :
+                            /* NOTREACHED on At the time of a normal performance */
+                            retval = EFAULT;
+                        break;
+                    }
+                    
+                    /* set ramp setting */
+                    if (false == p_scux_info_ch->first_ramp_flag)
+                    {
+                        while((DVUSR_DVU0_VRSTS_VOL_FIX != (p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUSR_DVU0_0 & DVUSR_DVU0_VRSTS_MASK)) &&
+                              (SCUX_RAMP_WAIT_MAX > ramp_wait_cnt))
+                        {
+                            ramp_wait_cnt++;
+                        }
+                        if (SCUX_RAMP_WAIT_MAX <= ramp_wait_cnt)
+                        {
+                            retval = EFAULT;
+                        }
+                        else
+                        {
+                            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 &= ~DVUER_DVU0_DVUEN_SET;
+                            SCUX_SetRampVolRegister(p_scux_info_ch);
+                            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET;
+                            p_scux_info_ch->first_ramp_flag = true;
+                        }
+                    }
+                }
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_DirectWriteStart
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CopyReadStart
+* @brief         Start read request(mem -> mem).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch:SCUX channel information.
+* @param[in]     *p_read_aio:Read request information.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_CopyReadStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_read_aio)
+{
+    int_t    retval;
+    int_t    dma_retval;
+    dma_trans_data_t dma_address_param;
+    uint32_t         dma_dst_addr;
+    
+    if ((NULL == p_scux_info_ch) || (NULL == p_read_aio))
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        retval = R_DMA_Setup(p_scux_info_ch->dma_rx_ch, &p_scux_info_ch->dma_rx_setup, NULL);
+                    
+        if (ESUCCESS != retval)
+        {
+            retval = EFAULT;
+        }
+        else
+        {
+            /* set first trans information */
+            p_scux_info_ch->p_rx_aio = p_read_aio;
+            p_scux_info_ch->p_rx_next_aio = NULL;
+            p_scux_info_ch->first_rx_flag = false;
+            
+            /* cast uint8_t pointer from void pointer */
+            dma_dst_addr = (uint32_t)p_read_aio->aio_buf;
+            
+            /* set 1st DMA parameter */
+            dma_address_param.src_addr = (void *)p_scux_info_ch->p_scux_reg->dmatu_n_cim;
+            dma_address_param.dst_addr = (void *)dma_dst_addr;
+            dma_address_param.count = p_read_aio->aio_nbytes;
+            
+            dma_retval = R_DMA_Start(p_scux_info_ch->dma_rx_ch, &dma_address_param, NULL);
+                
+            if (ESUCCESS != dma_retval)
+            {
+                retval = EFAULT;
+            }
+            else
+            {
+                /* enable interrupt */
+                p_scux_info_ch->dma_rx_current_size = dma_address_param.count;
+                p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 = (UEVMR_FFU0_UEVMUF_SET | 
+                                                                       UEVMR_FFU0_UEVMOF_SET | 
+                                                                       UEVMR_FFU0_UEVMOL_SET);
+                p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = DEVCR_FFD0_INIT_VALUE;
+                /* start clock devide on async mode */
+                if (false == p_scux_info_ch->src_cfg.mode_sync)
+                {
+                    if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async) && 
+                        (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.input_clk_async))
+                    {
+                        p_scux_info_ch->futsel_cim_value |= FUTSEL_CIM_DIVEN_SET;
+                        *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = p_scux_info_ch->futsel_cim_value;
+                    }
+                }
+                /* update channel status */
+                
+                switch (p_scux_info_ch->ch_stat)
+                {
+                    case SCUX_CH_UNINIT :
+                        /* fall through */
+                    case SCUX_CH_INIT :
+                        /* fall through */
+                    case SCUX_CH_STOP :
+                        /* fall through */
+                        retval = EBADF;
+                    break;                  
+                    
+                    case SCUX_CH_TRANS_IDLE :
+                        p_scux_info_ch->ch_stat = SCUX_CH_TRANS_RD;
+                    break;
+
+                    case SCUX_CH_TRANS_RD :
+                        /* do nothing, stats isn't updated */
+                    break;
+
+                    case SCUX_CH_TRANS_WR :
+                        p_scux_info_ch->ch_stat = SCUX_CH_TRANS_RDWR;
+                    break;
+                    
+                    case SCUX_CH_TRANS_RDWR :
+                        /* fall through */
+                    case SCUX_CH_STOP_WAIT :
+                        /* do nothing, stats isn't updated */
+                    break;
+                    
+                    case SCUX_CH_STOP_WAIT_IDLE :
+                        p_scux_info_ch->ch_stat = SCUX_CH_STOP_WAIT;
+                    break;
+                    
+                    default :
+                        /* NOTREACHED on At the time of a normal performance */
+                        retval = EFAULT;
+                    break;
+                }
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CopyReadStart
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_FlushWriteStart
+* @brief         Start dummy write for FIFO flush.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch:SCUX channel information.
+* @param[in]     *p_write_aio:Write request information.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_FlushWriteStart(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t retval = ESUCCESS;
+    dma_trans_data_t dma_address_param;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        if (0U != p_scux_info_ch->flush_stop_size)
+        {
+            retval = R_DMA_Setup(p_scux_info_ch->dma_tx_ch, &p_scux_info_ch->dma_tx_setup, NULL);
+                    
+            if (ESUCCESS != retval)
+            {
+                retval = EFAULT;
+            }
+            else
+            {
+                /* trans dummy data size is FIFO size unit */
+                if (p_scux_info_ch->flush_stop_size >= p_scux_info_ch->fifo_size)
+                {
+                    dma_address_param.count = p_scux_info_ch->fifo_size;
+                    p_scux_info_ch->flush_stop_size -= p_scux_info_ch->fifo_size;
+                }
+                else
+                {
+                    /* last data is fraction of FIFO size */
+                    dma_address_param.count = p_scux_info_ch->flush_stop_size;
+                    p_scux_info_ch->flush_stop_size = 0;
+                }
+                      
+                dma_address_param.src_addr = (void *)(p_scux_info_ch->p_tx_dummy_data);
+                dma_address_param.dst_addr = (void *)p_scux_info_ch->p_scux_reg->dmatd_n_cim;
+                                            
+                retval = R_DMA_Start(p_scux_info_ch->dma_tx_ch, &dma_address_param, NULL);
+                if (ESUCCESS != retval)
+                {
+                    retval = EFAULT;
+                }
+                else
+                {
+                    p_scux_info_ch->dma_tx_current_size = dma_address_param.count;
+                        
+                    p_scux_info_ch->tx_dummy_run_flag = true;
+                     
+                    if ((SCUX_CH_TRANS_RD == p_scux_info_ch->ch_stat) || (SCUX_CH_TRANS_IDLE == p_scux_info_ch->ch_stat))
+                    {
+                        /* restart write operation when write is stopped */
+                        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = (DEVMR_FFD0_DEVMUF_SET | 
+                                                                               DEVMR_FFD0_DEVMOF_SET | 
+                                                                               DEVMR_FFD0_DEVMOL_SET | 
+                                                                               DEVMR_FFD0_DEVMIUF_SET);
+                        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 
+                        = DEVCR_FFD0_INIT_VALUE;
+                        /* start clock devide on async mode or SSIF direct route setting */
+                        if (false == p_scux_info_ch->src_cfg.mode_sync)  
+                        {
+                            if((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                               (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                               (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                               (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async) && 
+                               (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                               (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.input_clk_async)) 
+                            {
+                                *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) |= FDTSEL_CIM_DIVEN_SET;
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_FlushWriteStart
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CopyCancelSpecific
+* @brief         Cancel specific request(mem->mem).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @param[in]     *p_cancel_aio : Cancel request information.
+* @retval        ESUCCESS : Operation successful.
+*                EBUSY  : Cancel requst is on going.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+#if(1) /* mbed */
+#if defined (__CC_ARM)
+#pragma O0
+#endif
+#endif /* end mbed */
+int_t SCUX_CopyCancelSpecific(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_cancel_aio)
+{
+    int_t    retval = ESUCCESS;
+    int_t    dummy_retval;
+    int_t    was_masked;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+#if defined (__ICCARM__)
+        was_masked = __disable_irq_iar();
+#else
+        was_masked = __disable_irq();
+#endif    
+    
+        /* check cancel request */
+        if ((p_scux_info_ch->p_tx_aio == p_cancel_aio) || (p_scux_info_ch->p_rx_aio == p_cancel_aio))
+        {
+            retval = EBUSY;
+        }
+        else
+        {
+            /* request don't going */
+            dummy_retval = ahf_cancel(&p_scux_info_ch->tx_que, p_cancel_aio);
+            if (ESUCCESS != dummy_retval)
+            {
+                /* NON_NOTICE_ASSERT: queue cancel error */
+            }
+            dummy_retval = ahf_cancel(&p_scux_info_ch->rx_que, p_cancel_aio);
+            if (ESUCCESS != dummy_retval)
+            {
+                /* NON_NOTICE_ASSERT: queue cancel error */
+            }
+        }
+        
+        if (0 == was_masked)
+        {
+            __enable_irq();
+        }
+    }
+    
+    return retval;
+}
+#if(1) /* mbed */
+#if defined (__CC_ARM)
+#pragma O3
+#endif
+#endif /* end mbed */
+
+/******************************************************************************
+End of function SCUX_CopyCancelSpecific
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DirectCancelSpecific
+* @brief         Cancel specific request(SSIF direct route).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @param[in]     *p_cancel_aio : Cancel request information.
+* @retval        ESUCCESS : Operation successful.
+*                EBUSY  : Cancel requst is on going.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_DirectCancelSpecific(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_cancel_aio)
+{
+    int_t    retval = ESUCCESS;
+    int_t    dummy_retval;
+    int_t    was_masked;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+#if defined (__ICCARM__)
+        was_masked = __disable_irq_iar();
+#else
+        was_masked = __disable_irq();
+#endif    
+    
+        /* check cancel request */
+        if ((p_scux_info_ch->p_tx_aio == p_cancel_aio) || (p_scux_info_ch->p_tx_next_aio == p_cancel_aio))
+        {
+            retval = EBUSY;
+        }
+        else
+        {
+            /* request don't going */
+            dummy_retval = ahf_cancel(&p_scux_info_ch->tx_que, p_cancel_aio);
+            if (ESUCCESS != dummy_retval)
+            {
+                /* NON_NOTICE_ASSERT: queue cancel error */
+            }
+        }
+        
+        if (0 == was_masked)
+        {
+            __enable_irq();
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_DirectCancelSpecific
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CopyCancelAll
+* @brief         Cancel all request(mem->mem).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+#if(1) /* mbed */
+#if defined (__CC_ARM)
+#pragma O0
+#endif
+#endif /* end mbed */
+int_t SCUX_CopyCancelAll(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t    retval = ESUCCESS;
+    int_t    dma_ercd;
+    int_t    dma_retval;
+    int_t    was_masked;
+    uint32_t tx_remain_size = 0;
+    uint32_t rx_remain_size = 0;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+#if defined (__ICCARM__)
+        was_masked = __disable_irq_iar();
+#else
+        was_masked = __disable_irq();
+#endif
+
+        dma_retval = R_DMA_Cancel(p_scux_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd);
+        /* DMA stop check, (when dma_ercd is EBADF, DMA stopped already) */
+        if ((ESUCCESS != dma_retval) && (EBADF != dma_ercd))
+        {
+            retval = EFAULT;
+        }
+        else
+        {
+            p_scux_info_ch->tx_fifo_total_size += p_scux_info_ch->dma_tx_current_size;
+            p_scux_info_ch->dma_tx_current_size = 0;
+        }
+             
+        dma_retval = R_DMA_Cancel(p_scux_info_ch->dma_rx_ch, &rx_remain_size, &dma_ercd);
+        /* DMA stop check, (when dma_ercd is EBADF, DMA stopped already) */
+        if ((ESUCCESS != dma_retval) && (EBADF != dma_ercd))
+        {
+            retval = EFAULT;
+        }
+        else
+        {
+            p_scux_info_ch->rx_fifo_total_size += p_scux_info_ch->dma_rx_current_size;
+            p_scux_info_ch->dma_rx_current_size = 0;
+        }
+                        
+        if (ESUCCESS == retval)
+        {
+            /* return write request */
+            if (NULL !=  p_scux_info_ch->p_tx_aio)
+            {
+                p_scux_info_ch->p_tx_aio->aio_return = ECANCELED;
+                ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_aio);
+            }
+            
+            /* return read request */
+            if (NULL != p_scux_info_ch->p_rx_aio)
+            {
+                p_scux_info_ch->p_rx_aio->aio_return = ECANCELED;
+                ahf_complete(&p_scux_info_ch->rx_que, p_scux_info_ch->p_rx_aio);
+            }   
+                               
+            ahf_cancelall(&p_scux_info_ch->tx_que);
+            ahf_cancelall(&p_scux_info_ch->rx_que);
+            
+            p_scux_info_ch->p_tx_aio = NULL;
+            p_scux_info_ch->p_rx_aio = NULL;
+        
+            SCUX_AdjustAccessFifo(p_scux_info_ch, tx_remain_size, rx_remain_size);
+            p_scux_info_ch->cancel_operate_flag = true;
+            
+            if (false != p_scux_info_ch->src_cfg.mode_sync)
+            {
+                SCUX_SyncStopHw(p_scux_info_ch);
+                SCUX_InitHw(p_scux_info_ch);
+                SCUX_SetupSrc(p_scux_info_ch);
+                SCUX_SyncStartHw(p_scux_info_ch);
+            }
+            else
+            {
+                SCUX_AsyncStopHw(p_scux_info_ch);
+                SCUX_InitHw(p_scux_info_ch);
+                SCUX_SetupSrc(p_scux_info_ch);
+                SCUX_AsyncStartHw(p_scux_info_ch);
+            }
+            
+            p_scux_info_ch->ch_stat = SCUX_CH_TRANS_IDLE;
+            p_scux_info_ch->p_flush_callback = NULL;
+            
+            p_scux_info_ch->tx_fifo_total_size = 0;
+            p_scux_info_ch->rx_fifo_total_size = 0;            
+            
+            p_scux_info_ch->cancel_operate_flag = false;
+        }
+
+        if (0 == was_masked)
+        {
+            __enable_irq();
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CopyCancelAll
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DirectCancelAll
+* @brief         Cancel all request(SSIF direct route).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_DirectCancelAll(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t    retval = ESUCCESS;
+    int_t    dma_ercd;
+    int_t    dma_retval;
+    int_t    was_masked;
+    uint32_t tx_remain_size = 0;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+#if defined (__ICCARM__)
+        was_masked = __disable_irq_iar();
+#else
+        was_masked = __disable_irq();
+#endif
+
+        dma_retval = R_DMA_Cancel(p_scux_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd);
+        /* DMA stop check, (when dma_ercd is EBADF, DMA stopped already) */
+        if ((ESUCCESS != dma_retval) && (EBADF != dma_ercd))
+        {
+            retval = EFAULT;
+        }
+        else
+        {
+            p_scux_info_ch->tx_fifo_total_size += p_scux_info_ch->dma_tx_current_size;
+            p_scux_info_ch->dma_tx_current_size = 0;
+            
+            if (NULL != p_scux_info_ch->p_tx_aio)
+            {
+                p_scux_info_ch->p_tx_aio->aio_return = ECANCELED;
+                ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_aio);
+            }
+            if (NULL != p_scux_info_ch->p_tx_next_aio)
+            {
+                p_scux_info_ch->p_tx_next_aio->aio_return = ECANCELED;
+                ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_next_aio);
+            }
+            ahf_cancelall(&p_scux_info_ch->tx_que);
+                
+            p_scux_info_ch->p_tx_aio = NULL;
+            p_scux_info_ch->p_tx_next_aio = NULL;
+            
+            SCUX_AdjustAccessFifo(p_scux_info_ch, tx_remain_size, 0);
+            
+            p_scux_info_ch->cancel_operate_flag = true;
+            p_scux_info_ch->restart_ramp_flag = true;
+            
+            SCUX_AsyncStopHw(p_scux_info_ch);
+            
+            SCUX_InitHw(p_scux_info_ch);
+            SCUX_SetupSsif(p_scux_info_ch);
+            SCUX_SetupSrc(p_scux_info_ch);
+            SCUX_SetupDvu(p_scux_info_ch);
+            SCUX_AsyncStartHw(p_scux_info_ch);
+            
+            p_scux_info_ch->ch_stat = SCUX_CH_TRANS_IDLE;
+            p_scux_info_ch->p_flush_callback = NULL;
+            
+            p_scux_info_ch->tx_fifo_total_size = 0;
+            p_scux_info_ch->rx_fifo_total_size = 0;
+            p_scux_info_ch->dvu_mute_stat = 0;
+            p_scux_info_ch->first_ramp_flag = false;
+            p_scux_info_ch->cancel_operate_flag = false;            
+        }   
+
+        if (0 == was_masked)
+        {
+            __enable_irq();
+        }
+    }
+    
+    return retval;
+}
+#if(1) /* mbed */
+#if defined (__CC_ARM)
+#pragma O3
+#endif
+#endif /* end mbed */
+
+/******************************************************************************
+End of function SCUX_DirectCancelAll
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_AdjustAccessFifo
+* @brief         Fifo is Cleared.
+*
+*                Description:<br>
+*                
+* @param[in]     p_scux_info_ch:channel information.
+* @retval        None.
+******************************************************************************/
+    
+void SCUX_AdjustAccessFifo(scux_info_ch_t * const p_scux_info_ch, const uint32_t tx_remain_size, const uint32_t rx_remain_size)
+{
+    uint32_t dummy_data_size;
+    uint32_t request_data_size;
+    uint32_t access_size = SCUX_DMA_UNIT_SIZE16;
+    uint32_t dummy_read_data;
+
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        *(p_scux_info_ch->p_scux_reg->dmacr_cim) &= ~(DMACR_CIM_DMAMDFFD_N_SET << p_scux_info_ch->channel);
+        switch (p_scux_info_ch->src_cfg.word_len)
+        {
+            case SCUX_DATA_LEN_24 :
+                access_size = SCUX_DMA_UNIT_SIZE24;
+            break;
+            
+            case SCUX_DATA_LEN_16 :
+                /* fall through */
+            case SCUX_DATA_LEN_16_TO_24 :
+                access_size = SCUX_DMA_UNIT_SIZE16;
+            break;
+            
+            default :
+                /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                /* <-IPA R3.5.2 */
+                /* NOTREACHED on At the time of a normal performance */
+            break;
+        }
+
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 &= ~(DEVMR_FFD0_DEVMUF_SET | 
+                                                                 DEVMR_FFD0_DEVMOF_SET | 
+                                                                 DEVMR_FFD0_DEVMOL_SET | 
+                                                                 DEVMR_FFD0_DEVMIUF_SET);
+        /* access count is adjusted for tx DMA remain size */
+        if (0U != tx_remain_size)
+        {
+            for (dummy_data_size = 0; dummy_data_size < tx_remain_size; dummy_data_size += access_size )
+            {
+                *(p_scux_info_ch->p_scux_reg->dmatd_n_cim) = 0;
+            }
+        }    
+        
+        /* access count is adjusted for tx total remain size */
+        if (0U != (p_scux_info_ch->tx_fifo_total_size & (p_scux_info_ch->fifo_size - 1U)))
+        {
+            request_data_size = (p_scux_info_ch->fifo_size - (p_scux_info_ch->tx_fifo_total_size & (p_scux_info_ch->fifo_size - 1U)));
+            for (dummy_data_size = 0; dummy_data_size < request_data_size; dummy_data_size += access_size )
+            {
+                *(p_scux_info_ch->p_scux_reg->dmatd_n_cim) = 0;
+            }
+        }
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = 0;
+        *(p_scux_info_ch->p_scux_reg->dmacr_cim) |= (DMACR_CIM_DMAMDFFD_N_SET << p_scux_info_ch->channel);
+    
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            *(p_scux_info_ch->p_scux_reg->dmacr_cim) &= ~(DMACR_CIM_DMAMDFFU_N_SET << p_scux_info_ch->channel);
+            switch (p_scux_info_ch->src_cfg.word_len)
+            {
+                case SCUX_DATA_LEN_16 :
+                    access_size = SCUX_DMA_UNIT_SIZE16;
+                break;
+                
+                case SCUX_DATA_LEN_24 :
+                    /* fall through */
+                case SCUX_DATA_LEN_16_TO_24 :
+                    access_size = SCUX_DMA_UNIT_SIZE24;
+                break;
+                
+                default :
+                    /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                    /* <-IPA R3.5.2 */
+                    /* NOTREACHED on At the time of a normal performance */
+                break;
+            }            
+        
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 &= ~(UEVMR_FFU0_UEVMUF_SET | 
+                                                                     UEVMR_FFU0_UEVMOF_SET | 
+                                                                     UEVMR_FFU0_UEVMOL_SET);
+            /* access count is adjusted for rx DMA remain size */
+            if (0U != rx_remain_size)
+            {
+                for (dummy_data_size = 0; dummy_data_size < rx_remain_size; dummy_data_size += access_size )
+                {
+                    dummy_read_data = *(p_scux_info_ch->p_scux_reg->dmatu_n_cim);
+                    UNUSED_ARG(dummy_read_data);
+                }
+            }
+            
+            /* access count is adjusted for rx total remain size */
+            if (0U != (p_scux_info_ch->rx_fifo_total_size & (p_scux_info_ch->fifo_size - 1U)))
+            {
+                request_data_size = (p_scux_info_ch->fifo_size - (p_scux_info_ch->rx_fifo_total_size & (p_scux_info_ch->fifo_size - 1U)));
+                
+                for (dummy_data_size = 0; dummy_data_size < request_data_size; dummy_data_size += access_size )
+                {
+                    dummy_read_data = *(p_scux_info_ch->p_scux_reg->dmatu_n_cim);
+                    UNUSED_ARG(dummy_read_data);
+                }
+            }
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = 0;
+            *(p_scux_info_ch->p_scux_reg->dmacr_cim) |= (DMACR_CIM_DMAMDFFU_N_SET << p_scux_info_ch->channel);
+        }
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_AdjustAccessFifo
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetupSrc
+* @brief         SRC HW setup.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_SetupSrc(scux_info_ch_t * const p_scux_info_ch)
+{
+    uint32_t process_delay = 0;
+    uint32_t data_size;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (false != p_scux_info_ch->src_cfg.src_enable)
+        {
+            /* check delay mode and enabled audio channel */
+            switch (p_scux_info_ch->src_cfg.delay_mode)
+            {
+                case SCUX_DELAY_NORMAL :
+                    switch (p_scux_info_ch->src_cfg.use_ch)
+                    {
+                        case SCUX_USE_CH_1 :
+                            process_delay = SCUX_PROCESS_DELAY_NORMAL_CH1;
+                        break;
+        
+                        case SCUX_USE_CH_2 :
+                            process_delay = SCUX_PROCESS_DELAY_NORMAL_CH2;
+                        break;
+        
+                        case SCUX_USE_CH_4 :
+                            process_delay = SCUX_PROCESS_DELAY_NORMAL_CH4;
+                        break;
+                        
+                        case SCUX_USE_CH_6 :
+                            process_delay = SCUX_PROCESS_DELAY_NORMAL_CH6;
+                        break;
+        
+                        case SCUX_USE_CH_8 :
+                            process_delay = SCUX_PROCESS_DELAY_NORMAL_CH8;
+                        break;
+                        
+                        default :
+                            /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                            /* <-IPA R3.5.2 */
+                            /* NOTREACHED on At the time of a normal performance */
+                        break;  
+                    }                                          
+                break;
+                            
+                case SCUX_DELAY_LOW_DELAY1 :
+                    process_delay = SCUX_PROCESS_DELAY_1_CH1_2;
+                break;
+        
+                case SCUX_DELAY_LOW_DELAY2 :
+                    process_delay = SCUX_PROCESS_DELAY_2_CH1_2;
+                break;                
+                            
+                default :
+                    /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                    /* <-IPA R3.5.2 */
+                    /* NOTREACHED on At the time of a normal performance */
+                break;
+            }        
+        
+            /* set dummy data size for flush */
+            if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len)
+            {
+                data_size = sizeof(uint16_t);
+            }
+            else
+            {
+                data_size = sizeof(uint32_t);
+            }
+        
+            process_delay = (process_delay * ((p_scux_info_ch->output_rate * SCUX_RATE_INT_CONV_VALUE) / p_scux_info_ch->input_rate));
+            if (0U != (process_delay % SCUX_RATE_INT_CONV_VALUE))
+            {
+                /* A redundant value is added that delay size below a decimal point may come out */
+                process_delay = ((process_delay / SCUX_RATE_INT_CONV_VALUE) + SCUX_ADJUST_REST_VALUE);
+            }
+            else
+            {
+                process_delay = (process_delay / SCUX_RATE_INT_CONV_VALUE);
+            }
+            
+            p_scux_info_ch->flush_stop_size = (p_scux_info_ch->src_cfg.use_ch * (data_size * (process_delay + SCUX_LOGIC_DELAY_BYPASS_OFF)));    
+            if (0U != (p_scux_info_ch->flush_stop_size % SCUX_EVEN_VALUE_DIV))
+            {
+                /* set even value */
+                p_scux_info_ch->flush_stop_size++;
+            }
+        }
+        else
+        {
+            /* set dummy data size for flush */
+            if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len)
+            {
+                data_size = sizeof(uint16_t);
+            }
+            else
+            {
+                data_size = sizeof(uint32_t);
+            }
+            
+            p_scux_info_ch->flush_stop_size = (p_scux_info_ch->src_cfg.use_ch * (data_size * SCUX_LOGIC_DELAY_BYPASS_ON));
+            if (0U != (p_scux_info_ch->flush_stop_size % SCUX_EVEN_VALUE_DIV))
+            {
+                /* set even value */
+                p_scux_info_ch->flush_stop_size++;
+            }
+        }
+            
+        p_scux_info_ch->tx_dummy_run_flag = false;
+        
+        /* set FFD & FFU parameter depend on the combination of route and sync mode */
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            if (false != p_scux_info_ch->src_cfg.mode_sync)
+            {
+                p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_PASS_SET_SYNC;
+                p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_PASS_SET_SYNC;
+                p_scux_info_ch->p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC_PASS_SEL_SET_SYNC;
+                p_scux_info_ch->p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC_PASS_SEL_SET_SYNC;
+            }
+            else
+            {
+                p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_PASS_SET_ASYNC;
+                p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_PASS_SET_ASYNC;
+                p_scux_info_ch->p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC_PASS_SEL_SET_ASYNC;
+                p_scux_info_ch->p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC_PASS_SEL_SET_ASYNC;
+            }
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_PASS_SET_ASYNC;
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = 0;
+            p_scux_info_ch->p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC_PASS_SEL_SET_ASYNC;
+            p_scux_info_ch->p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC_PASS_SEL_SET_DIRECT;
+        }
+            
+        /* set route CIM register for SSIF channel and MIX */
+        switch (p_scux_info_ch->route_set)
+        {
+            case SCUX_ROUTE_SRC0_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC1_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC2_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC3_MEM :
+                /* do nothing, when mem to mem route is setting */
+            break;
+                        
+            case SCUX_ROUTE_SRC0_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_SRC0_SET;
+            break;
+            
+            case SCUX_ROUTE_SRC0_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_SRC0_SET | SSIRSEL_CIM_SOSEL1_SRC0_SET | SSIRSEL_CIM_SOSEL2_SRC0_SET);
+            break;
+            
+            case SCUX_ROUTE_SRC0_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_SRC0_SET;
+            break;
+            
+            case SCUX_ROUTE_SRC0_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_SRC0_SET | SSIRSEL_CIM_SOSEL4_SRC0_SET | SSIRSEL_CIM_SOSEL5_SRC0_SET);
+            break;
+            
+            case SCUX_ROUTE_SRC1_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_SRC1_SET;
+            break;
+            
+            case SCUX_ROUTE_SRC1_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_SRC1_SET | SSIRSEL_CIM_SOSEL1_SRC1_SET | SSIRSEL_CIM_SOSEL2_SRC1_SET);
+            break;
+            
+            case SCUX_ROUTE_SRC1_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_SRC1_SET;
+            break;
+            
+            case SCUX_ROUTE_SRC1_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_SRC1_SET | SSIRSEL_CIM_SOSEL4_SRC1_SET | SSIRSEL_CIM_SOSEL5_SRC1_SET);
+            break;
+            
+            case SCUX_ROUTE_SRC2_SSIF1 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL1_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL1_SRC2_SET;
+            break;
+        
+            case SCUX_ROUTE_SRC2_SSIF4 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL4_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL4_SRC2_SET;
+            break;
+            
+            case SCUX_ROUTE_SRC3_SSIF2 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL2_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL2_SRC3_SET;
+            break;
+            
+            case SCUX_ROUTE_SRC3_SSIF5 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL5_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL5_SRC3_SET;
+            break;
+            
+            case SCUX_ROUTE_SRC0_MIX_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_MIX_SET;
+            break;            
+            
+            case SCUX_ROUTE_SRC0_MIX_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_MIX_SET | SSIRSEL_CIM_SOSEL1_MIX_SET | SSIRSEL_CIM_SOSEL2_MIX_SET);
+            break;            
+            
+            case SCUX_ROUTE_SRC0_MIX_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_MIX_SET;
+            break;
+
+            case SCUX_ROUTE_SRC0_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_MIX_SET | SSIRSEL_CIM_SOSEL4_MIX_SET | SSIRSEL_CIM_SOSEL5_MIX_SET);
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_MIX_SET;
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_MIX_SET | SSIRSEL_CIM_SOSEL1_MIX_SET | SSIRSEL_CIM_SOSEL2_MIX_SET);
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_MIX_SET;
+            break;
+            
+            case SCUX_ROUTE_SRC1_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_MIX_SET | SSIRSEL_CIM_SOSEL4_MIX_SET | SSIRSEL_CIM_SOSEL5_MIX_SET);
+            break;            
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_MIX_SET;
+            break;            
+            
+            case SCUX_ROUTE_SRC2_MIX_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_MIX_SET | SSIRSEL_CIM_SOSEL1_MIX_SET | SSIRSEL_CIM_SOSEL2_MIX_SET);
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_MIX_SET;
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_MIX_SET | SSIRSEL_CIM_SOSEL4_MIX_SET | SSIRSEL_CIM_SOSEL5_MIX_SET);
+            break;
+
+            case SCUX_ROUTE_SRC3_MIX_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_MIX_SET;
+            break;
+            
+            case SCUX_ROUTE_SRC3_MIX_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_MIX_SET | SSIRSEL_CIM_SOSEL1_MIX_SET | SSIRSEL_CIM_SOSEL2_MIX_SET);
+            break;            
+            
+            case SCUX_ROUTE_SRC3_MIX_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_MIX_SET;
+            break;
+            
+            case SCUX_ROUTE_SRC3_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_MIX_SET | SSIRSEL_CIM_SOSEL4_MIX_SET | SSIRSEL_CIM_SOSEL5_MIX_SET);
+            break;
+            
+            default :
+                /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                /* <-IPA R3.5.2 */
+                 /* NOTREACHED on At the time of a normal performance */
+            break;
+        }
+            
+        SCUX_SetupDataPosition(p_scux_info_ch);
+        
+        /* set route SSICTRL register for each route */
+        if (false == p_scux_info_ch->src_cfg.mode_sync)
+        {
+            switch (p_scux_info_ch->route_set)
+            {
+                case SCUX_ROUTE_SRC0_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC1_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC2_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC3_MEM :
+                    /* do nothing, when mem to mem route is setting */
+                break;
+
+                case SCUX_ROUTE_SRC0_SSIF0 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC0_SSIF012 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                case SCUX_ROUTE_SRC0_SSIF3 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC0_SSIF345 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                case SCUX_ROUTE_SRC1_SSIF0 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC1_SSIF012 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                case SCUX_ROUTE_SRC1_SSIF3 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC1_SSIF345 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                case SCUX_ROUTE_SRC2_SSIF1 :
+                    /* fall through */
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI1TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                case SCUX_ROUTE_SRC2_SSIF4 :
+                    /* fall through */
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI4TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+                
+                case SCUX_ROUTE_SRC3_SSIF2 :
+                    /* fall through */
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI2TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                case SCUX_ROUTE_SRC3_SSIF5 :
+                    /* fall through */
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI5TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;                
+                
+                case SCUX_ROUTE_SRC0_MIX_SSIF0 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC0_MIX_SSIF012 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+                
+                case SCUX_ROUTE_SRC0_MIX_SSIF3 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC0_MIX_SSIF345 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;                
+
+                case SCUX_ROUTE_SRC1_MIX_SSIF0 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC1_MIX_SSIF012 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+                
+                case SCUX_ROUTE_SRC1_MIX_SSIF3 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC1_MIX_SSIF345 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+    
+                case SCUX_ROUTE_SRC2_MIX_SSIF0 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC2_MIX_SSIF012 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+                
+                case SCUX_ROUTE_SRC2_MIX_SSIF3 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC2_MIX_SSIF345 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+                
+                case SCUX_ROUTE_SRC3_MIX_SSIF0 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC3_MIX_SSIF012 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;          
+                
+                case SCUX_ROUTE_SRC3_MIX_SSIF3 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC3_MIX_SSIF345 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+                        
+                default :
+                    /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                    /* <-IPA R3.5.2 */
+                    /* NOTREACHED on At the time of a normal performance */
+                break;
+            }
+        }
+        
+        SCUX_SetupSrcClk(p_scux_info_ch);
+        
+        /* set pin mode for each route */
+        switch (p_scux_info_ch->route_set)
+        {
+            case SCUX_ROUTE_SRC0_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC1_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC2_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC3_MEM :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;            
+            
+            case SCUX_ROUTE_SRC0_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;            
+            
+            case SCUX_ROUTE_SRC0_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                    
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;    
+                }
+            break;            
+            
+            case SCUX_ROUTE_SRC0_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;            
+            
+            case SCUX_ROUTE_SRC0_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                                                                  
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;                                                                  
+                }
+            break;
+
+            case SCUX_ROUTE_SRC1_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;
+
+            case SCUX_ROUTE_SRC1_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                    
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;    
+                }
+            break;
+
+            case SCUX_ROUTE_SRC1_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;
+
+            case SCUX_ROUTE_SRC1_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                                                                  
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;                                                                  
+                }
+            break;
+
+            case SCUX_ROUTE_SRC2_SSIF1 :
+                /* fall through */
+            case SCUX_ROUTE_SRC2_SSIF4 :
+                /* fall through */
+            case SCUX_ROUTE_SRC3_SSIF2 :
+                /* fall through */
+            case SCUX_ROUTE_SRC3_SSIF5 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;
+
+            case SCUX_ROUTE_SRC0_MIX_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;
+
+            case SCUX_ROUTE_SRC0_MIX_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                    
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;    
+                }
+            break;
+
+            case SCUX_ROUTE_SRC0_MIX_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;
+            
+            case SCUX_ROUTE_SRC0_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                                                                  
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;                                                                  
+                }
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                    
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;    
+                }
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                                                                  
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;                                                                  
+                }
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                    
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;    
+                }
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                                                                  
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;                                                                  
+                }
+            break;
+
+            case SCUX_ROUTE_SRC3_MIX_SSIF0 :
+                /* fall through */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;
+
+            case SCUX_ROUTE_SRC3_MIX_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                    
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;    
+                }
+            break;
+
+            case SCUX_ROUTE_SRC3_MIX_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;
+            
+            case SCUX_ROUTE_SRC3_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                                                                  
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;                                                                  
+                }
+            break;
+            
+            default :
+                /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                /* <-IPA R3.5.2 */
+                /* NOTREACHED on At the time of a normal performance */
+            break;
+        }
+            
+        SCUX_SetupFifo(p_scux_info_ch);
+        SCUX_SetupSrcFunction(p_scux_info_ch);
+    }
+        
+    return;
+}
+    
+/******************************************************************************
+End of function SCUX_SetupSrc
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_SetupDataPosition
+* @brief         Audio data position setup.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_SetupDataPosition(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t audio_ch;
+    uint32_t audio_place = 0;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {    
+        /* set data posion for SRC */
+        for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
+        {
+            audio_place |= (((uint32_t)p_scux_info_ch->src_cfg.select_in_data_ch[audio_ch] & SRCRSEL_CIM_PLACE_N_MASK) << ((uint32_t)audio_ch * SRCRSEL_CIM_PLACE_N_SHIFT));
+        }
+        *(p_scux_info_ch->p_scux_reg->srcrsel_n_cim) = audio_place;
+        
+        /* set data position for MIX */
+        if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            if (0U == p_info_drv->shared_info.mix_run_ch)
+            {
+                audio_place = 0;
+                for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
+                {
+                    audio_place |= (((uint32_t)p_info_drv->shared_info.select_out_data_ch[audio_ch] & MIXRSEL_CIM_PLACE_N_MASK) << ((uint32_t)audio_ch * MIXRSEL_CIM_PLACE_N_SHIFT));
+                }
+                *(p_scux_info_ch->p_scux_reg->mixrsel_cim) = audio_place;
+            }
+        }
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupDataPosition
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_SetupSrcClk
+* @brief         SRC clock setup.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_SetupSrcClk(scux_info_ch_t * const p_scux_info_ch)
+{
+    uint32_t fdtsel_value = 0;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* set input timing clock */
+        if (false == p_scux_info_ch->src_cfg.mode_sync)
+        {
+            /* get value of register setting */
+            switch (p_scux_info_ch->src_cfg.input_clk_async)
+            {
+    
+                case SCUX_CLK_AUDIO_CLK :
+                    fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) | 
+                                   FDTSEL_CIM_SCKSEL_AUDIO_CLK_SET);
+                break;              
+                
+                case SCUX_CLK_AUDIO_X1 :
+                    fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) | 
+                                   FDTSEL_CIM_SCKSEL_AUDIO_X1_SET);
+                break;
+                    
+                case SCUX_CLK_MLB_CLK :
+                    fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) | 
+                                   FDTSEL_CIM_SCKSEL_MLB_CLK_SET);
+                break;
+    
+                case SCUX_CLK_USB_X1 :
+                    fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) | 
+                                   FDTSEL_CIM_SCKSEL_USB_X1_SET);
+                break;
+    
+                case SCUX_CLK_CLKP1_2 :
+                    fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) | 
+                                   FDTSEL_CIM_SCKSEL_CLKP1_2_SET);
+                break;
+    
+                case SCUX_CLK_MTU_TIOC3A :
+                    fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) | 
+                                    FDTSEL_CIM_SCKSEL_MTUSEL2_SET | 
+                                    FDTSEL_CIM_MTUSEL_SET_TIOC3A);
+                break;
+                
+                case SCUX_CLK_MTU_TIOC4A :
+                    fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) | 
+                                    FDTSEL_CIM_SCKSEL_MTUSEL2_SET | 
+                                    FDTSEL_CIM_MTUSEL_SET_TIOC4A);
+                break;
+    
+                case SCUX_CLK_SSIF0_WS :
+                    fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF0_WS_SET;
+                break;
+                    
+                case SCUX_CLK_SSIF1_WS :
+                    fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF1_WS_SET;
+                break;
+                    
+                case SCUX_CLK_SSIF2_WS :
+                    fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF2_WS_SET;
+                break;
+                    
+                case SCUX_CLK_SSIF3_WS :
+                    fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF3_WS_SET;
+                break;
+                    
+                case SCUX_CLK_SSIF4_WS :
+                    fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF4_WS_SET;
+                break;
+                    
+                case SCUX_CLK_SSIF5_WS :
+                    fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF5_WS_SET;
+                break;
+                
+                default :
+                    /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                    /* <-IPA R3.5.2 */
+                    /* NOTREACHED on At the time of a normal performance */
+                break;
+            }
+            *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) = fdtsel_value;
+        }
+        
+        /* set output timing clock on MIX */
+        if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_scux_info_ch->futsel_cim_value = (((0 << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 
+                                                (((uint32_t)p_scux_info_ch->p_ssif_info1->ssif_cfg.ssif_ch_num | FUTSEL_CIM_SCKSEL_SSIF0_WS_SET) & FUTSEL_CIM_SCKSEL_MASK));
+            *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = p_scux_info_ch->futsel_cim_value;
+        }
+        else if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {   
+            /* set output timing clock on other MIX */
+            if (false == p_scux_info_ch->src_cfg.mode_sync)
+            {
+                switch (p_scux_info_ch->src_cfg.output_clk_async)
+                {
+                    case SCUX_CLK_AUDIO_CLK :
+                        p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 
+                                                            FUTSEL_CIM_SCKSEL_AUDIO_CLK_SET);
+                    break;
+                    
+                    case SCUX_CLK_AUDIO_X1 :
+                        p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 
+                                                            FUTSEL_CIM_SCKSEL_AUDIO_X1_SET);
+                    break;
+                        
+                    case SCUX_CLK_MLB_CLK :
+                        p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 
+                                                            FUTSEL_CIM_SCKSEL_MLB_CLK_SET);
+                    break;
+        
+                    case SCUX_CLK_USB_X1 :
+                        p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 
+                                                            FUTSEL_CIM_SCKSEL_USB_X1_SET);
+                    break;
+        
+                    case SCUX_CLK_CLKP1_2 :
+                        p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 
+                                                            FUTSEL_CIM_SCKSEL_CLKP1_2_SET);
+                    break;
+        
+                    case SCUX_CLK_MTU_TIOC3A :
+                        p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 
+                                                            FUTSEL_CIM_SCKSEL_MTUSEL2_SET | 
+                                                            FUTSEL_CIM_MTUSEL_SET_TIOC3A);
+                    break;
+                    
+                    case SCUX_CLK_MTU_TIOC4A :
+                        p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 
+                                                            FUTSEL_CIM_SCKSEL_MTUSEL2_SET | 
+                                                            FUTSEL_CIM_MTUSEL_SET_TIOC4A);
+                    break;
+        
+                    case SCUX_CLK_SSIF0_WS :
+                        p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF0_WS_SET;
+                    break;
+                        
+                    case SCUX_CLK_SSIF1_WS :
+                        p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF1_WS_SET;
+                    break;
+                        
+                    case SCUX_CLK_SSIF2_WS :
+                        p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF2_WS_SET;
+                    break;
+                        
+                    case SCUX_CLK_SSIF3_WS :
+                        p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF3_WS_SET;
+                    break;
+                        
+                    case SCUX_CLK_SSIF4_WS :
+                        p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF4_WS_SET;
+                    break;
+                        
+                    case SCUX_CLK_SSIF5_WS :
+                        p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF5_WS_SET;
+                    break;
+                    
+                    default :
+                        /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                        /* <-IPA R3.5.2 */
+                        /* NOTREACHED on At the time of a normal performance */
+                    break;
+                }
+                *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = p_scux_info_ch->futsel_cim_value;
+            }
+        }
+        else
+        {
+            /* do nothing for SSIF route */
+        }
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupSrcClk
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_SetupFifo
+* @brief         SRC FIFO setup.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_SetupFifo(scux_info_ch_t * const p_scux_info_ch)
+{
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* set FFD register */
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FDAIR_FFD0_0 = p_scux_info_ch->src_cfg.use_ch;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DRQSR_FFD0_0 = SCUX_FIFO_REQ_SIZE_128_32;
+    
+        GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_FDI]);
+        
+        /* set FFU register */
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->FUAIR_FFU0_0 = p_scux_info_ch->src_cfg.use_ch;
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->URQSR_FFU0_0 = SCUX_FIFO_REQ_SIZE_128_32;
+        
+            GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_FUI]);
+        }   
+        
+        p_scux_info_ch->tx_fifo_total_size = 0;
+        p_scux_info_ch->rx_fifo_total_size = 0;
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupFifo
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_SetupSrcFunction
+* @brief         SRC function setup.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_SetupSrcFunction(scux_info_ch_t * const p_scux_info_ch)
+{
+    float32_t ifs_calc_value;
+    uint32_t ifs_value;
+    uint32_t sadir_value;
+    uint32_t srccr_value = 0;
+    uint32_t bfssr_value;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (false == p_scux_info_ch->src_cfg.src_enable)
+        {
+            /* set bypass mode */
+            if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
+            {
+                p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 |= SRCBR_2SRC0_BYPASS_SET;
+            }
+            else
+            {
+                p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 |= SRCBR_2SRC0_BYPASS_SET;
+            }
+        }   
+        else
+        {
+            /* calculate sampling rate convert rate parameter */
+            ifs_calc_value = ((float32_t)p_scux_info_ch->input_rate / (float32_t)p_scux_info_ch->output_rate);
+            /* ->IPA R2.4.1 float value is intentionall casted to uint32_t value, because it is resigter value. */
+            ifs_value = (uint32_t)(ifs_calc_value * (float32_t)SCUX_RATE_CONVERT_CALC_VALUE);
+            /* <-IPA R2.4.1 */
+            if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len)
+            {
+                sadir_value = (((uint32_t)p_scux_info_ch->src_cfg.use_ch & SADIR_2SRC0_CHNUM_MASK) | SADIR_2SRC0_OTBL_SET_16BIT);
+            }
+            else
+            {
+                sadir_value = (((uint32_t)p_scux_info_ch->src_cfg.use_ch & SADIR_2SRC0_CHNUM_MASK) | SADIR_2SRC0_OTBL_SET_24BIT);
+            }
+            
+            /* setting of sync mode bit */
+            if (false != p_scux_info_ch->src_cfg.mode_sync)
+            {
+                /* set sync mode */
+                srccr_value |= SRCCR_2SRC0_SRCMD_SET;
+            }
+            else
+            {
+                /* set async mode (bit clear) */
+                srccr_value &= ~SRCCR_2SRC0_SRCMD_SET;
+            }
+            
+            /* setting of buffer for delay mode */
+            if (SCUX_DELAY_NORMAL == p_scux_info_ch->src_cfg.delay_mode)
+            {
+                /* delay normal setting (bit clear) */
+                srccr_value &= ~SRCCR_2SRC0_BUFMD_SET;
+            }
+            else
+            {
+                /* delay setting (bit set) */
+                srccr_value |= SRCCR_2SRC0_BUFMD_SET;
+            }
+            
+            /* setting enable bit for wait mode */
+            if ((0U == p_scux_info_ch->src_cfg.wait_sample) || (false != p_scux_info_ch->cancel_operate_flag))
+            {
+                /* clear wait mode enable bit when wait value is 0 or cancel operatin on going */
+                srccr_value &= ~SRCCR_2SRC0_WATMD_SET;
+            }
+            else
+            {
+                /* set wait mode enable bit when wait value is other than 0 */
+                srccr_value |= SRCCR_2SRC0_WATMD_SET;
+            }
+            
+            /* setting buffer value for delay mode */
+            if (SCUX_DELAY_NORMAL == p_scux_info_ch->src_cfg.delay_mode)
+            {
+                /* set 0 to BFSSR register on delay normal */
+                bfssr_value = 0;
+            }
+            else if (SCUX_DELAY_LOW_DELAY1 == p_scux_info_ch->src_cfg.delay_mode)
+            {
+                /* set delay mode 1 setting to BFSSR register on delay mode1 */
+                bfssr_value = ((BFSSR_2SRC0_BUFDATA_SET_DELAY_MODE1 & BFSSR_2SRC0_BUFDATA_MASK) | 
+                               (BFSSR_2SRC0_BUFIN_SET_DELAY_MODE & BFSSR_2SRC0_BUFIN_MASK));
+            }
+            else
+            {
+                /* set delay mode 2 setting to BFSSR register on delay mode2 */
+                bfssr_value = ((BFSSR_2SRC0_BUFDATA_SET_DELAY_MODE2 & BFSSR_2SRC0_BUFDATA_MASK) | 
+                               (BFSSR_2SRC0_BUFIN_SET_DELAY_MODE & BFSSR_2SRC0_BUFIN_MASK));
+            }
+            
+            /* set register */
+            if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
+            {
+                p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 &= ~SRCBR_2SRC0_BYPASS_SET;
+                p_scux_info_ch->p_scux_reg->p_src_reg->SADIR0_2SRC0_0 = sadir_value;
+                p_scux_info_ch->p_scux_reg->p_src_reg->IFSCR0_2SRC0_0 |= IFSCR_2SRC0_INTIFSEN_SET;
+                p_scux_info_ch->p_scux_reg->p_src_reg->IFSVR0_2SRC0_0 = ifs_value;
+                p_scux_info_ch->p_scux_reg->p_src_reg->MNFSR0_2SRC0_0 = ((ifs_value * (uint32_t)p_scux_info_ch->src_cfg.min_rate_percentage) 
+                                                                         / SCUX_CALC_MINFS_VALUE);
+                p_scux_info_ch->p_scux_reg->p_src_reg->SRCCR0_2SRC0_0 = (SRCCR_2SRC0_BASE_VALUE | srccr_value);
+                p_scux_info_ch->p_scux_reg->p_src_reg->BFSSR0_2SRC0_0 = bfssr_value;
+                if (false != p_scux_info_ch->cancel_operate_flag)
+                {
+                    /* set 0 to register compulsorily when cancel operation on going */
+                    p_scux_info_ch->p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = 0U;
+                }
+                else
+                {
+                    /* set wait value to register when cancel operation on going */
+                    p_scux_info_ch->p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = (p_scux_info_ch->src_cfg.wait_sample & WATSR_2SRC0_WTIME_MASK);
+                }
+            }
+            else
+            {
+                p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 &= ~SRCBR_2SRC0_BYPASS_SET;
+                p_scux_info_ch->p_scux_reg->p_src_reg->SADIR1_2SRC0_0 = sadir_value;
+                p_scux_info_ch->p_scux_reg->p_src_reg->IFSCR1_2SRC0_0 |= IFSCR_2SRC0_INTIFSEN_SET;
+                p_scux_info_ch->p_scux_reg->p_src_reg->IFSVR1_2SRC0_0 = ifs_value;
+                p_scux_info_ch->p_scux_reg->p_src_reg->MNFSR1_2SRC0_0 = ((ifs_value * (uint32_t)p_scux_info_ch->src_cfg.min_rate_percentage) 
+                                                                         / SCUX_CALC_MINFS_VALUE);
+                p_scux_info_ch->p_scux_reg->p_src_reg->SRCCR1_2SRC0_0 = (SRCCR_2SRC0_BASE_VALUE | srccr_value);
+                p_scux_info_ch->p_scux_reg->p_src_reg->BFSSR1_2SRC0_0 = bfssr_value;
+                if (false != p_scux_info_ch->cancel_operate_flag)
+                {
+                    /* set 0 to register compulsorily when cancel operation on going */
+                    p_scux_info_ch->p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = 0U;
+                }
+                else
+                {
+                    /* set wait value to register when cancel operation on going */
+                    p_scux_info_ch->p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = (p_scux_info_ch->src_cfg.wait_sample & WATSR_2SRC0_WTIME_MASK);
+                }
+            }
+        }
+    }
+        
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupSrcFunction
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_SetupDvu
+* @brief         DVU module setup.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+void SCUX_SetupDvu(scux_info_ch_t * const p_scux_info_ch)
+{
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len)
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = (((uint32_t)p_scux_info_ch->src_cfg.use_ch & VADIR_DVU0_CHNUM_MASK) | 
+                                                                   VADIR_DVU0_OTBL_SET_16BIT);
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = (((uint32_t)p_scux_info_ch->src_cfg.use_ch & VADIR_DVU0_CHNUM_MASK) | 
+                                                                   VADIR_DVU0_OTBL_SET_24BIT);
+        }
+        
+        if (false == p_scux_info_ch->dvu_cfg.dvu_enable)
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 |= DVUBR_DVU0_BYPASS_SET;
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 &= ~DVUBR_DVU0_BYPASS_SET;
+        }
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupDvu
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_SetupDvuVolume
+* @brief         DVU volume setup.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_SetupDvuVolume(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t audio_ch;
+    uint32_t vrctr_value = 0;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* init DVU module */
+        p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 &= ~DVUIR_DVU0_INIT_SET;
+        if (false != p_scux_info_ch->dvu_cfg.dvu_enable)
+        {
+            /* set digital volume */
+            SCUX_SetDigiVolRegister(p_scux_info_ch);
+            
+            /* dummy setting to volume ramp */
+            for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
+            {
+                vrctr_value |= (VRCTR_DVU0_VREN_SET << audio_ch);
+            }
+
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 |= DVUCR_DVU0_VRMD_SET;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = vrctr_value;
+        
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = 0;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = 0;  
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = 0;
+        
+            /* set zerocross mute */
+            SCUX_SetZerocrossMuteRegister(p_scux_info_ch);
+            
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET;
+            GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_DVI]);
+        }
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupDvu
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_SetupMix
+* @brief         MIX module setup.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_SetupMix(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t scux_ch;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* initialized MIX resgister when the channel using MIX to the begining and not on going cancel */ 
+        if ((0U == p_info_drv->shared_info.mix_run_ch) && (false == p_scux_info_ch->cancel_operate_flag))
+        {
+            *(p_scux_info_ch->p_scux_reg->madir_mix0_0) = ((uint32_t)p_scux_info_ch->src_cfg.use_ch & MADIR_MIX0_CHNUM_MASK);
+            *(p_scux_info_ch->p_scux_reg->mixir_mix0_0) &= ~MIXIR_MIX0_INIT_SET;
+        }    
+        
+        for (scux_ch = SCUX_CH_0; scux_ch < SCUX_CH_NUM; scux_ch++)
+        {
+            /* register set on the channel itself which sets up or channel which has already MIX operated */
+            if ((scux_ch == p_scux_info_ch->channel) ||
+                (0U != (p_info_drv->shared_info.mix_run_ch & (1U << scux_ch))))
+            {
+                SCUX_SetMixVolRegister(scux_ch);
+            }
+        }
+        
+        /* initialized MIX resgister when the channel using MIX to the begining and not on going cancel */ 
+        if ((0U == p_info_drv->shared_info.mix_run_ch) && (false == p_scux_info_ch->cancel_operate_flag))
+        {
+            *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) &= ~MDBER_MIX0_MIXDBEN_SET;
+            
+            if (false != p_info_drv->shared_info.mixmode_ramp)
+            {
+                /* set ramp mode */
+                *(p_scux_info_ch->p_scux_reg->mixmr_mix0_0) |= MIXMR_MIX0_MIXMODE_SET;
+                *(p_scux_info_ch->p_scux_reg->mvpdr_mix0_0) = (uint32_t)((((uint32_t)p_info_drv->shared_info.up_period << MVPDR_MIX0_MXPDUP_SHIFT) & MVPDR_MIX0_MXPDUP_MASK) | 
+                                                              (((uint32_t)p_info_drv->shared_info.down_period << MVPDR_MIX0_MXPDDW_SHIFT) & MVPDR_MIX0_MXPDDW_MASK));
+            }
+            else
+            {
+                /* set step mode */
+                *(p_scux_info_ch->p_scux_reg->mixmr_mix0_0) &= ~MIXMR_MIX0_MIXMODE_SET;
+            }
+            
+            *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) |= MDBER_MIX0_MIXDBEN_SET;
+        }
+        /* set bit SCUX channel which useing MIX */
+        p_info_drv->shared_info.mix_run_ch |= (1U << p_scux_info_ch->channel);
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupMix
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_SetupSsif
+* @brief         SSIF module setup.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+void SCUX_SetupSsif(const scux_info_ch_t * const p_scux_info_ch)
+{
+    scux_ssif_info_t *p_set_ssif;
+    volatile uint8_t dummy_buf;
+    uint32_t ssif_arrange_num;
+    uint32_t ssicr_value = 0;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    int_t    was_masked;
+    
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {    
+        for (ssif_arrange_num = 0; ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT; ssif_arrange_num++)
+        {
+            switch (ssif_arrange_num)
+            {
+                case SCUX_SSIF_CH_ARRANGEMENT1:
+                    p_set_ssif = p_scux_info_ch->p_ssif_info1;
+                break;
+                
+                case SCUX_SSIF_CH_ARRANGEMENT2:
+                    p_set_ssif = p_scux_info_ch->p_ssif_info2;
+                break;
+                
+                case SCUX_SSIF_CH_ARRANGEMENT3:
+                    p_set_ssif = p_scux_info_ch->p_ssif_info3;
+                break;
+                
+                default :
+                    /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                    /* <-IPA R3.5.2 */
+                    /* NOTREACHED on At the time of a normal performance */
+                break;
+            }
+            
+            /* check wherher SSIF pointer 1, 2, 3 is NULL */
+            if (NULL != p_set_ssif)
+            {
+                /* check SSIF is used on other MIX SCUX channel */
+                if (0U == ((uint32_t)p_set_ssif->scux_channel & ~(1U << p_scux_info_ch->channel)))
+                {
+                    if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch |= (1U << p_set_ssif->ssif_cfg.ssif_ch_num);
+                    }
+                    
+#if defined (__ICCARM__)
+                    was_masked = __disable_irq_iar();
+#else
+                    was_masked = __disable_irq();
+#endif
+
+                    /* input clock */
+                    CPGSTBCR11 &= (uint8_t)~((uint8_t)gb_cpg_scux_ssif_stbcr_bit[p_set_ssif->ssif_cfg.ssif_ch_num]);
+                    dummy_buf = CPGSTBCR11;
+
+                    /* SSIF rest */
+                    CPGSWRSTCR1 |= (uint8_t)gb_cpg_scux_ssif_swrst_bit[p_set_ssif->ssif_cfg.ssif_ch_num];
+                    dummy_buf = CPGSWRSTCR1;
+                    
+                    CPGSWRSTCR1 &= (uint8_t)~((uint8_t)gb_cpg_scux_ssif_swrst_bit[p_set_ssif->ssif_cfg.ssif_ch_num]);
+                    dummy_buf = CPGSWRSTCR1;
+                    
+                    if (0 == was_masked)
+                    {
+                        __enable_irq();
+                    }
+
+                    SCUX_SetupSsifGpio(p_set_ssif->ssif_cfg.ssif_ch_num);
+                    
+                    /* if mode is master mode, WS continue mode is enabled */
+                    if (false != p_set_ssif->ssif_cfg.mode_master)
+                    {
+                        p_set_ssif->p_scux_ssif_reg->SSITDMR |= SCUX_SSITDMR_CONT_SET;
+                    }
+                    else
+                    {
+                        p_set_ssif->p_scux_ssif_reg->SSITDMR &= ~SCUX_SSITDMR_CONT_SET;
+                    }
+                    
+                    /* TDM mode is set according to use_tdm */
+                    if (false != p_set_ssif->ssif_cfg.use_tdm)
+                    {
+                        p_set_ssif->p_scux_ssif_reg->SSITDMR |= SCUX_SSITDMR_TDM_SET;
+                    }
+                    else
+                    {
+                        p_set_ssif->p_scux_ssif_reg->SSITDMR &= ~SCUX_SSITDMR_TDM_SET;
+                    }
+                    
+                    /* over sample clock is set according to select_audio_clk */
+                    /* if select_audio_clk is 0, set AUDIO_X1 */
+                    /* if select_audio_clk is 0, set AUDIO_CLK */
+                    if (false != p_set_ssif->ssif_cfg.select_audio_clk)
+                    {
+                        ssicr_value |= SCUX_SSICR_CKS_SET;
+                    }
+                    else
+                    {
+                        ssicr_value &= ~SCUX_SSICR_CKS_SET;
+                    }
+                    
+                    if (NULL == p_scux_info_ch->p_ssif_info2)
+                    {
+                        /* in case single channel, SSIF channel is set as use_ch kinds */
+                        switch (p_scux_info_ch->src_cfg.use_ch)
+                        {
+                            case SCUX_USE_CH_1:
+                                /* NOTREACHED on At the time of a normal performance */
+                            break;                          
+                            
+                            case SCUX_USE_CH_2:
+                                /* if TDM mode is used on audio 2ch , error occured in SCUX_CheckSrcParam */
+                                ssicr_value |= SCUX_SSICR_CHNL_SET_1CH;
+                            break;
+                            
+                            case SCUX_USE_CH_4:
+                                ssicr_value |= SCUX_SSICR_CHNL_SET_2CH;
+                            break;
+                                            
+                            case SCUX_USE_CH_6:
+                                ssicr_value |= SCUX_SSICR_CHNL_SET_3CH;
+                            break;
+                            
+                            case SCUX_USE_CH_8:
+                                ssicr_value |= SCUX_SSICR_CHNL_SET_4CH;
+                            break;
+                            
+                            default :
+                                /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                                /* <-IPA R3.5.2 */
+                                /* NOTREACHED on At the time of a normal performance */
+                            break;
+                        }
+                    }
+                    else
+                    {
+                        /* in case multi channel, SSIF channel is set 1ch compulsorily */
+                        ssicr_value |= SCUX_SSICR_CHNL_SET_1CH;
+                    }
+                    
+                    /* set data word */
+                    if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len)
+                    {
+                        ssicr_value |= SCUX_SSICR_DWL_16BIT_SET;
+                    }
+                    else
+                    {
+                        ssicr_value |= SCUX_SSICR_DWL_24BIT_SET;
+                    }
+                    
+                    ssicr_value |= ((uint32_t)p_set_ssif->ssif_cfg.system_word << SCUX_SSICR_SWL_SHIFT);
+                            
+                    
+                    if (SCUX_PIN_MODE_INDEPEND == p_set_ssif->pin_mode)
+                    {
+                        /* in case pin synchronization is slave, SSIF mode is set mode following mode_master */
+                        if (false != p_set_ssif->ssif_cfg.mode_master)
+                        {
+                            ssicr_value |= (SCUX_SSICR_SCKD_SET | SCUX_SSICR_SWSD_SET);
+                        }
+                        else
+                        {
+                            ssicr_value &= ~(SCUX_SSICR_SCKD_SET | SCUX_SSICR_SWSD_SET);
+                        }
+                    }
+                    else
+                    {
+                        /* in case pin synchronization is slave, SSIF mode is set slave mode compulsorily */
+                        ssicr_value &= ~(SCUX_SSICR_SCKD_SET | SCUX_SSICR_SWSD_SET);
+                    }
+                    
+                    /* set serial bit clock polarity */
+                    if (false != p_set_ssif->ssif_cfg.sck_polarity_rise)
+                    {
+                        ssicr_value |= SCUX_SSICR_SCKP_SET;
+                    }
+                    else
+                    {
+                        ssicr_value &= ~SCUX_SSICR_SCKP_SET;
+                    }
+                    
+                    /* set WS signal polarity */
+                    if (false != p_set_ssif->ssif_cfg.ws_polarity_high)
+                    {
+                        ssicr_value |= SCUX_SSICR_SWSP_SET;
+                    }
+                    else
+                    {
+                        ssicr_value &= ~SCUX_SSICR_SWSP_SET;
+                    }
+                    
+                    /* set serial padding polarity */
+                    if (false != p_set_ssif->ssif_cfg.padding_high)
+                    {
+                        ssicr_value |= SCUX_SSICR_SPDP_SET;
+                    }
+                    else
+                    {
+                        ssicr_value &= ~SCUX_SSICR_SPDP_SET;
+                    }
+                
+                    /* set serial data align polarity */
+                    if (false != p_set_ssif->ssif_cfg.serial_data_align)
+                    {
+                        ssicr_value &= ~SCUX_SSICR_SDTA_SET;
+                    }
+                    else
+                    {
+                        ssicr_value |= SCUX_SSICR_SDTA_SET;
+                    }
+                    
+                    /* set WS delay setting */
+                    if (false == p_set_ssif->ssif_cfg.ws_delay)
+                    {
+                        ssicr_value |= SCUX_SSICR_DEL_SET;
+                    }
+                    else
+                    {
+                        ssicr_value &= ~SCUX_SSICR_DEL_SET;
+                    }
+                
+                    /* set SSIF devide rate */
+                    ssicr_value |= ((uint32_t)p_set_ssif->clk_div << SCUX_SSICR_CKDV_SHIFT);
+                    
+                    p_set_ssif->p_scux_ssif_reg->SSICR = ssicr_value;
+                
+                    /* set noise cancel setting */
+                    if ((false == p_set_ssif->ssif_cfg.mode_master) && (false != p_set_ssif->ssif_cfg.use_noise_cancel))
+                    {
+                        GPIO.SNCR |= (1U << gb_cpg_scux_ssif_sncr_bit[p_set_ssif->ssif_cfg.ssif_ch_num]);
+                    }
+                    else
+                    {
+                        GPIO.SNCR &= ~(1U << gb_cpg_scux_ssif_sncr_bit[p_set_ssif->ssif_cfg.ssif_ch_num]);
+                    }
+                }
+            }
+        }
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupSsif
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetupDma
+* @brief         DMA setup.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+int_t SCUX_SetupDma(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t    retval = ESUCCESS;
+    AIOCB    *dma_aio;
+    uint32_t dmacr_cim_value = 0;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        dma_aio = &gb_scux_write_dma_aio[p_scux_info_ch->channel];
+        /* dummy data write start */
+        dma_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+        dma_aio->aio_sigevent.sigev_value.sival_int = p_scux_info_ch->channel;
+        if (SCUX_ROUTE_MEM_TO_MEM != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            dma_aio->aio_sigevent.sigev_notify_function = &SCUX_DMA_DirectTxCallBack;
+        }
+        else
+        {
+            dma_aio->aio_sigevent.sigev_notify_function = &SCUX_DMA_CopyTxCallBack;
+        }
+        p_scux_info_ch->dma_tx_setup.resource = p_scux_info_ch->dma_resource_tx;
+        p_scux_info_ch->dma_tx_setup.direction = DMA_REQ_DES;
+        
+        switch (p_scux_info_ch->src_cfg.word_len)
+        {
+            case SCUX_DATA_LEN_16 :
+                /* fall through */
+            case SCUX_DATA_LEN_16_TO_24 :
+                p_scux_info_ch->dma_tx_setup.dst_width = DMA_UNIT_2;
+                p_scux_info_ch->dma_tx_setup.src_width = DMA_UNIT_2;
+            break;
+            
+            case SCUX_DATA_LEN_24 :
+                p_scux_info_ch->dma_tx_setup.dst_width = DMA_UNIT_4;
+                p_scux_info_ch->dma_tx_setup.src_width = DMA_UNIT_4;
+            break;
+            
+            default :
+                /* NOTREACHED on At the time of a normal performance */
+            break;
+        }  
+        
+        p_scux_info_ch->dma_tx_setup.dst_cnt = DMA_ADDR_FIX;
+        p_scux_info_ch->dma_tx_setup.src_cnt = DMA_ADDR_INCREMENT;
+        p_scux_info_ch->dma_tx_setup.p_aio = dma_aio;
+        
+        /* get read DMA channel */
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_scux_info_ch->dma_rx_ch = R_DMA_Alloc(DMA_ALLOC_CH, NULL);
+            if (EERROR == p_scux_info_ch->dma_rx_ch)
+            {
+                retval = EMFILE;
+            }
+            else
+            {
+                dma_aio = &gb_scux_read_dma_aio[p_scux_info_ch->channel];
+                dma_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+                dma_aio->aio_sigevent.sigev_value.sival_int = p_scux_info_ch->channel;
+                dma_aio->aio_sigevent.sigev_notify_function = &SCUX_DMA_CopyRxCallBack;
+                p_scux_info_ch->dma_rx_setup.resource = p_scux_info_ch->dma_resource_rx;
+                p_scux_info_ch->dma_rx_setup.direction = DMA_REQ_SRC;
+                
+                switch (p_scux_info_ch->src_cfg.word_len)
+                {
+                    case SCUX_DATA_LEN_16 :
+                        p_scux_info_ch->dma_rx_setup.dst_width = DMA_UNIT_2;
+                        p_scux_info_ch->dma_rx_setup.src_width = DMA_UNIT_2;
+                    break;
+                    
+                    case SCUX_DATA_LEN_24 :
+                        /* fall through */
+                    case SCUX_DATA_LEN_16_TO_24 :
+                        p_scux_info_ch->dma_rx_setup.dst_width = DMA_UNIT_4;
+                        p_scux_info_ch->dma_rx_setup.src_width = DMA_UNIT_4;
+                    break;
+                    
+                    default :
+                        /* NOTREACHED on At the time of a normal performance */
+                    break;
+                }    
+                
+                p_scux_info_ch->dma_rx_setup.dst_cnt = DMA_ADDR_INCREMENT;
+                p_scux_info_ch->dma_rx_setup.src_cnt = DMA_ADDR_FIX;
+                p_scux_info_ch->dma_rx_setup.p_aio = dma_aio;
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            dmacr_cim_value = *(p_scux_info_ch->p_scux_reg->dmacr_cim);
+            /* set write DMA param */
+            dmacr_cim_value |= (DMACR_CIM_DMAMDFFD_N_SET << p_scux_info_ch->channel);
+          
+            /* set read DMA param */
+            if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+            {
+                dmacr_cim_value |= (DMACR_CIM_DMAMDFFU_N_SET << p_scux_info_ch->channel);
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            *(p_scux_info_ch->p_scux_reg->dmacr_cim) = dmacr_cim_value;
+        }
+    }
+        
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_SetupDma
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_InitHw
+* @brief         Initialize HW .
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+void SCUX_InitHw(scux_info_ch_t * const p_scux_info_ch)
+{
+    scux_ssif_info_t *p_set_ssif;
+    uint32_t ssif_arrange_num;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* init FFD register */
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 = FFDIR_FFD0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FDAIR_FFD0_0 = FDAIR_FFD0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DRQSR_FFD0_0 = DRQSR_FFD0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 = FFDBR_FFD0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = DEVMR_FFD0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 = IPCIR_IPC0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC0_INIT_VALUE;
+        *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) = FDTSEL_CIM_INIT_VALUE;
+        *(p_scux_info_ch->p_scux_reg->srcrsel_n_cim) = SRCRSEL_CIM_INIT_VALUE;
+                
+        /* check usc_ch ,and init SRC register */
+        if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SADIR0_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->IFSCR0_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->IFSVR0_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCCR0_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
+            p_scux_info_ch->p_scux_reg->p_src_reg->MNFSR0_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->BFSSR0_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVCR0_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SADIR1_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->IFSCR1_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->IFSVR1_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCCR1_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
+            p_scux_info_ch->p_scux_reg->p_src_reg->MNFSR1_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->BFSSR1_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
+        }
+        
+        /* init FFU register */
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 = FFUIR_FFU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->FUAIR_FFU0_0 = FUAIR_FFU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->URQSR_FFU0_0 = URQSR_FFU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 = UEVMR_FFU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = UEVCR_FFU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 = OPCIR_OPC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC0_INIT_VALUE;
+            *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = FUTSEL_CIM_INIT_VALUE;
+            p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_INIT_VALUE;
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 = DVUIR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = VADIR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 = DVUBR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 = DVUCR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 = ZCMCR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = VRCTR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = VRPDR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = VRDBR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = VRWTR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL0R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL1R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL2R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL3R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL4R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL5R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL6R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL7R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 = DVUER_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = VEVMR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VEVCR_DVU0_0 = VEVCR_DVU0_INIT_VALUE;
+            
+            for (ssif_arrange_num = 0; ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT; ssif_arrange_num++)
+            {
+                switch (ssif_arrange_num)
+                {
+                    case SCUX_SSIF_CH_ARRANGEMENT1:
+                        p_set_ssif = p_scux_info_ch->p_ssif_info1;
+                    break;
+                    
+                    case SCUX_SSIF_CH_ARRANGEMENT2:
+                        p_set_ssif = p_scux_info_ch->p_ssif_info2;
+                    break;
+                    
+                    case SCUX_SSIF_CH_ARRANGEMENT3:
+                        p_set_ssif = p_scux_info_ch->p_ssif_info3;
+                    break;
+                    
+                    default :
+                        /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                        /* <-IPA R3.5.2 */
+                        /* NOTREACHED on At the time of a normal performance */
+                    break;
+                }
+                
+                if (NULL != p_set_ssif)
+                {
+                    /* check SSIF is used on other MIX SCUX channel */
+                    if (0U == ((uint32_t)p_set_ssif->scux_channel & ~(1U << p_scux_info_ch->channel)))
+                    {
+                        /* init SSIF register */
+                        p_set_ssif->p_scux_ssif_reg->SSICR = SCUX_SSICR_INIT_VALUE;
+                        p_set_ssif->p_scux_ssif_reg->SSIFCR = SCUX_SSIFCR_INIT_VALUE;
+                        p_set_ssif->p_scux_ssif_reg->SSIFTDR = SCUX_SSIFTDR_INIT_VALUE;
+                        p_set_ssif->p_scux_ssif_reg->SSITDMR = SCUX_SSITDMR_INIT_VALUE;
+                        p_set_ssif->p_scux_ssif_reg->SSIFCCR = SCUX_SSIFCCR_INIT_VALUE;
+                        p_set_ssif->p_scux_ssif_reg->SSIFCMR = SCUX_SSIFCMR_INIT_VALUE;
+                    }
+                }
+            }
+        }
+    
+        if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            /* initialized MIX resgister when the channel using MIX to the begining and not on going cancel */ 
+            if ((0U == p_info_drv->shared_info.mix_run_ch) && (false == p_scux_info_ch->cancel_operate_flag))
+            {
+                *(p_scux_info_ch->p_scux_reg->mdb_n_r_mix0_0) = MDB_N_R_MIX0_0_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = FUTSEL_CIM_INIT_VALUE;
+                p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->srcrsel_n_cim) = SRCRSEL_CIM_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->mixir_mix0_0) = MIXIR_MIX0_0_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->madir_mix0_0) = MADIR_MIX0_0_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->mixbr_mix0_0) = MIXBR_MIX0_0_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->mixmr_mix0_0) = MIXMR_MIX0_0_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->mvpdr_mix0_0) = MVPDR_MIX0_0_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) = MDBER_MIX0_0_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->mixrsel_cim) = MIXRSEL_CIM_INIT_VALUE;
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_InitHw
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_SyncStartHw
+* @brief         Start Hw on sync mode.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+void SCUX_SyncStartHw(const scux_info_ch_t * const p_scux_info_ch)
+{
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 &= ~FFDIR_FFD0_INIT_SET;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 |= FFDBR_FFD0_BOOT_SET;
+        p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 &= ~FFUIR_FFU0_INIT_SET;
+        
+        /* check usc_ch ,and init SRC register */
+        if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 &= ~SRCIR_2SRC0_INIT_SET;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 |= (SEVMR_2SRC0_EVMUF_SET | SEVMR_2SRC0_EVMOF_SET);
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 &= ~SRCIR_2SRC0_INIT_SET;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 |= (SEVMR_2SRC0_EVMUF_SET | SEVMR_2SRC0_EVMOF_SET);
+        }
+        p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 &= ~IPCIR_IPC0_INIT_SET;
+        p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 &= ~OPCIR_OPC0_INIT_SET;
+        
+        p_scux_info_ch->p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 &= ~SRCIRR_2SRC0_INIT_SET;
+        
+        GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_AI]);
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SyncStartHw
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_AsyncStartHw
+* @brief         Start Hw on async mode.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+void SCUX_AsyncStartHw(scux_info_ch_t * const p_scux_info_ch)
+{
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 &= ~FFDIR_FFD0_INIT_SET;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 |= FFDBR_FFD0_BOOT_SET;
+            
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 &= ~FFUIR_FFU0_INIT_SET;
+        }
+        
+        /* check usc_ch ,and init SRC register */
+        if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 &= ~SRCIR_2SRC0_INIT_SET;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 |= (SEVMR_2SRC0_EVMUF_SET | SEVMR_2SRC0_EVMOF_SET);
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 &= ~SRCIR_2SRC0_INIT_SET;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 |= (SEVMR_2SRC0_EVMUF_SET | SEVMR_2SRC0_EVMOF_SET);
+        }
+        
+        p_scux_info_ch->p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 &= ~SRCIRR_2SRC0_INIT_SET;
+        
+        GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_AI]);
+        
+        if (SCUX_ROUTE_MEM_TO_MEM != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            SCUX_SetupDvuVolume(p_scux_info_ch);
+            
+            if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+            {
+                SCUX_SetupMix(p_scux_info_ch);
+            }
+        }
+        
+        p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 &= ~IPCIR_IPC0_INIT_SET;
+        p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 &= ~OPCIR_OPC0_INIT_SET;
+            
+        if (SCUX_ROUTE_MEM_TO_MEM != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            /* check used SSIF is only 1 ch */
+            if (NULL == p_scux_info_ch->p_ssif_info2)
+            {
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR |= SCUX_SSICR_TEN_SET;
+            }
+            else
+            {
+                if (SCUX_SSIF_CH_0 == p_scux_info_ch->p_ssif_info1->ssif_cfg.ssif_ch_num)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  |= SSICTRL_CIM_SSI012TEN_SET; 
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                }
+                else
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI345TEN_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                }
+            }
+        }
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_AsyncStartHw
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_SyncStopHw
+* @brief         Stop Hw on sync mode.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+void SCUX_SyncStopHw(const scux_info_ch_t * const p_scux_info_ch)
+{
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 &= ~(UEVMR_FFU0_UEVMUF_SET | 
+                                                                 UEVMR_FFU0_UEVMOF_SET | 
+                                                                 UEVMR_FFU0_UEVMOL_SET);
+        GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_FUI]);
+        
+        p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 |= FFUIR_FFU0_INIT_SET;
+        p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 |= OPCIR_OPC0_INIT_SET;
+        
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 &= ~(DEVMR_FFD0_DEVMUF_SET | 
+                                                                 DEVMR_FFD0_DEVMOF_SET | 
+                                                                 DEVMR_FFD0_DEVMOL_SET | 
+                                                                 DEVMR_FFD0_DEVMIUF_SET);
+        GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_FDI]);
+        
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 |= FFDIR_FFD0_INIT_SET;
+        p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 |= IPCIR_IPC0_INIT_SET;
+        
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 &= ~FFDBR_FFD0_BOOT_SET;
+        
+        /* check usc_ch ,and init SRC register */
+        if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 |= SRCIR_2SRC0_INIT_SET;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 &= ~(SEVMR_2SRC0_EVMUF_SET | 
+                                                                       SEVMR_2SRC0_EVMOF_SET);
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 |= SRCIR_2SRC0_INIT_SET;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 &= ~(SEVMR_2SRC0_EVMUF_SET | 
+                                                                       SEVMR_2SRC0_EVMOF_SET);
+        }
+    
+        p_scux_info_ch->p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 |= SRCIRR_2SRC0_INIT_SET;
+        
+        GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_AI]);
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SyncStopHw
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_AsyncStopHw
+* @brief         Stop Hw on async mode.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+void SCUX_AsyncStopHw(scux_info_ch_t * const p_scux_info_ch)
+{
+    uint32_t  scux_check_ch;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    uint32_t  ssipmd_mask_ssif2 = 0;
+    uint32_t  ssipmd_mask_ssif3 = 0;
+    uint32_t  ssipmd_shift_ssif2 = 0;
+    uint32_t  ssipmd_shift_ssif3 = 0;
+    uint32_t  ssipmd_reg;
+    scux_info_ch_t *p_pair_scux_ch;
+    int_t    was_masked;
+    
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 &= ~(UEVMR_FFU0_UEVMUF_SET | 
+                                                                     UEVMR_FFU0_UEVMOF_SET | 
+                                                                     UEVMR_FFU0_UEVMOL_SET);
+            GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_FUI]);
+            p_scux_info_ch->futsel_cim_value &= ~FUTSEL_CIM_DIVEN_SET;
+            *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = p_scux_info_ch->futsel_cim_value;
+            
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 |= FFUIR_FFU0_INIT_SET;
+        }
+    
+        p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 |= OPCIR_OPC0_INIT_SET;
+        
+        if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_info_drv->shared_info.mix_run_ch &= ~(1U << p_scux_info_ch->channel);
+        }
+        
+        switch (p_scux_info_ch->route_set)
+        {
+            case SCUX_ROUTE_SRC0_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC1_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC2_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC3_MEM :
+                /* do nothing, when mem to mem route is setting */
+            break;          
+            
+            case SCUX_ROUTE_SRC0_SSIF0 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;
+            
+            case SCUX_ROUTE_SRC0_SSIF012 :
+                p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+            break;            
+            
+            case SCUX_ROUTE_SRC0_SSIF3 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;            
+            
+            case SCUX_ROUTE_SRC0_SSIF345 :
+                p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+            break;            
+            
+            case SCUX_ROUTE_SRC1_SSIF0 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;            
+            
+            case SCUX_ROUTE_SRC1_SSIF012 :
+                p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+            break;            
+            
+            case SCUX_ROUTE_SRC1_SSIF3 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;                      
+                            
+            case SCUX_ROUTE_SRC1_SSIF345 : 
+                p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+            break;              
+            
+            case SCUX_ROUTE_SRC2_SSIF1 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI1TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;
+                
+            case SCUX_ROUTE_SRC2_SSIF4 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI4TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;
+                
+            case SCUX_ROUTE_SRC3_SSIF2 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI2TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;
+                
+            case SCUX_ROUTE_SRC3_SSIF5 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI5TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;
+                
+            case SCUX_ROUTE_SRC0_MIX_SSIF0 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag) 
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC0_MIX_SSIF012 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;                
+                
+            case SCUX_ROUTE_SRC0_MIX_SSIF3 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;                
+            
+            case SCUX_ROUTE_SRC0_MIX_SSIF345 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;                
+                
+            case SCUX_ROUTE_SRC1_MIX_SSIF0 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF012 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag) 
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF3 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF345 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF0 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF012 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF3 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF345 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;                
+                
+            case SCUX_ROUTE_SRC3_MIX_SSIF0 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+            
+            case SCUX_ROUTE_SRC3_MIX_SSIF012 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+            
+            case SCUX_ROUTE_SRC3_MIX_SSIF3 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;                 
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+                
+            case SCUX_ROUTE_SRC3_MIX_SSIF345 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+                        
+            default :
+                /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                /* <-IPA R3.5.2 */
+                /* do nothing, when mem to mem route is setting */
+            break;
+        }
+        
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 &= ~(DEVMR_FFD0_DEVMUF_SET | 
+                                                                 DEVMR_FFD0_DEVMOF_SET | 
+                                                                 DEVMR_FFD0_DEVMOL_SET | 
+                                                                 DEVMR_FFD0_DEVMIUF_SET);
+        GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_FDI]);
+        
+        *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) &= ~FDTSEL_CIM_DIVEN_SET;
+        
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 |= FFDIR_FFD0_INIT_SET;
+        p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 |= IPCIR_IPC0_INIT_SET;
+        
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 &= ~FFDBR_FFD0_BOOT_SET;
+        
+        /* check usc_ch ,and init SRC register */
+        if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 &= ~(SEVMR_2SRC0_EVMUF_SET | 
+                                                                       SEVMR_2SRC0_EVMOF_SET);        
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 |= SRCIR_2SRC0_INIT_SET;
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 &= ~(SEVMR_2SRC0_EVMUF_SET | 
+                                                                       SEVMR_2SRC0_EVMOF_SET);
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 |= SRCIR_2SRC0_INIT_SET;
+        }
+        
+        /* if pair channel is stopped, common SRC unit is initialized */
+        if (SCUX_CH_0 == p_scux_info_ch->channel)
+        {
+            p_pair_scux_ch = SCUX_GetDrvChInfo(SCUX_CH_1);
+        }
+        else if (SCUX_CH_1 == p_scux_info_ch->channel)
+        {
+            p_pair_scux_ch = SCUX_GetDrvChInfo(SCUX_CH_0);
+        }
+        else if (SCUX_CH_2 == p_scux_info_ch->channel)
+        {
+            p_pair_scux_ch = SCUX_GetDrvChInfo(SCUX_CH_3);
+        }
+        else
+        {
+            p_pair_scux_ch = SCUX_GetDrvChInfo(SCUX_CH_2);
+        }
+        
+        if (NULL != p_pair_scux_ch)
+        {
+            if ((SCUX_CH_UNINIT == p_pair_scux_ch->ch_stat) ||
+                (SCUX_CH_INIT == p_pair_scux_ch->ch_stat)   || 
+                (SCUX_CH_STOP == p_pair_scux_ch->ch_stat))
+            {
+                p_scux_info_ch->p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 |= SRCIRR_2SRC0_INIT_SET;
+                GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_AI]);
+            }
+        }
+        else
+        {
+            /* NON_NOTICE_ASSERT: NULL pointer */
+        }
+            
+        if (SCUX_ROUTE_MEM_TO_MEM != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 |= DVUIR_DVU0_INIT_SET;
+        
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = 0;
+            GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_DVI]);
+            
+            scux_check_ch = (uint32_t)p_scux_info_ch->p_ssif_info1->scux_channel;
+            scux_check_ch &= ~(1U << p_scux_info_ch->channel);
+            p_scux_info_ch->p_ssif_info1->scux_channel = (int_t)scux_check_ch;
+            if (0 == p_scux_info_ch->p_ssif_info1->scux_channel)
+            {
+#if defined (__ICCARM__)
+                was_masked = __disable_irq_iar();
+#else
+                was_masked = __disable_irq();
+#endif
+
+                /* clock mask on all used SSIF channel shutdown */
+                CPGSTBCR11 |= ((uint8_t)gb_cpg_scux_ssif_stbcr_bit[p_scux_info_ch->p_ssif_info1->ssif_cfg.ssif_ch_num]);
+
+                if (0 == was_masked)
+                {
+                    __enable_irq();
+                }
+            }
+            
+            if (NULL != p_scux_info_ch->p_ssif_info2)
+            {
+                /* clear multiple SSIF setting */
+                scux_check_ch = (uint32_t)p_scux_info_ch->p_ssif_info2->scux_channel;
+                scux_check_ch &= ~(1U << p_scux_info_ch->channel);
+                p_scux_info_ch->p_ssif_info2->scux_channel = (int_t)scux_check_ch;
+                p_scux_info_ch->p_ssif_info2->pin_mode = p_scux_info_ch->p_ssif_info2->pin_mode_backup;
+                
+                switch (p_scux_info_ch->p_ssif_info2->ssif_cfg.ssif_ch_num)
+                {
+                    case SCUX_SSIF_CH_1 :
+                        ssipmd_mask_ssif2 = SSIPMD_CIM_SSI1PMD_MASK;
+                        ssipmd_shift_ssif2 = SSIPMD_CIM_SSI1PMD_SHIFT;
+                    break;
+                                
+                    case SCUX_SSIF_CH_2 :
+                        ssipmd_mask_ssif2 = SSIPMD_CIM_SSI2PMD_MASK;
+                        ssipmd_shift_ssif2 = SSIPMD_CIM_SSI2PMD_SHIFT;
+                    break;
+            
+                    case SCUX_SSIF_CH_3 :
+                        ssipmd_mask_ssif2 = SSIPMD_CIM_SSI3PMD_MASK;
+                        ssipmd_shift_ssif2 = SSIPMD_CIM_SSI3PMD_SHIFT;
+                    break;
+            
+                    case SCUX_SSIF_CH_4 :
+                        ssipmd_mask_ssif2 = SSIPMD_CIM_SSI4PMD_MASK;
+                        ssipmd_shift_ssif2 = SSIPMD_CIM_SSI4PMD_SHIFT;
+                    break;
+                                
+                    case SCUX_SSIF_CH_5 :
+                        ssipmd_mask_ssif2 = SSIPMD_CIM_SSI5PMD_MASK;
+                        ssipmd_shift_ssif2 = SSIPMD_CIM_SSI5PMD_SHIFT;
+                    break;                  
+                            
+                    default :
+                        /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                        /* <-IPA R3.5.2 */
+                        /* NOTREACHED on At the time of a normal performance */
+                    break;
+                }
+                
+                scux_check_ch = (uint32_t)p_scux_info_ch->p_ssif_info3->scux_channel;
+                scux_check_ch &= ~(1U << p_scux_info_ch->channel);
+                p_scux_info_ch->p_ssif_info3->scux_channel = (int_t)scux_check_ch;  
+                p_scux_info_ch->p_ssif_info3->pin_mode = p_scux_info_ch->p_ssif_info3->pin_mode_backup;
+                
+                switch (p_scux_info_ch->p_ssif_info3->ssif_cfg.ssif_ch_num)
+                {
+                    case SCUX_SSIF_CH_1 :
+                        ssipmd_mask_ssif3 = SSIPMD_CIM_SSI1PMD_MASK;
+                        ssipmd_shift_ssif3 = SSIPMD_CIM_SSI1PMD_SHIFT;
+                    break;
+                                
+                    case SCUX_SSIF_CH_2 :
+                        ssipmd_mask_ssif3 = SSIPMD_CIM_SSI2PMD_MASK;
+                        ssipmd_shift_ssif3 = SSIPMD_CIM_SSI2PMD_SHIFT;
+                    break;
+            
+                    case SCUX_SSIF_CH_3 :
+                        ssipmd_mask_ssif3 = SSIPMD_CIM_SSI3PMD_MASK;
+                        ssipmd_shift_ssif3 = SSIPMD_CIM_SSI3PMD_SHIFT;
+                    break;
+            
+                    case SCUX_SSIF_CH_4 :
+                        ssipmd_mask_ssif3 = SSIPMD_CIM_SSI4PMD_MASK;
+                        ssipmd_shift_ssif3 = SSIPMD_CIM_SSI4PMD_SHIFT;
+                    break;
+                                
+                    case SCUX_SSIF_CH_5 :
+                        ssipmd_mask_ssif3 = SSIPMD_CIM_SSI5PMD_MASK;
+                        ssipmd_shift_ssif3 = SSIPMD_CIM_SSI5PMD_SHIFT;
+                    break;                  
+                            
+                    default :
+                        /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                        /* <-IPA R3.5.2 */
+                        /* NOTREACHED on At the time of a normal performance */
+                    break;
+                }
+                ssipmd_reg = *(p_scux_info_ch->p_scux_reg->ssipmd_cim);
+                ssipmd_reg &= ~(ssipmd_mask_ssif2 | ssipmd_mask_ssif3);
+                
+                /* ->IPA R2.4.1 Even if pinmode and ssipmd_shift are max value, omission dose not occur. */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) = (ssipmd_reg | 
+                                                        ((uint32_t)p_scux_info_ch->p_ssif_info2->pin_mode << ssipmd_shift_ssif2) |
+                                                        ((uint32_t)p_scux_info_ch->p_ssif_info3->pin_mode << ssipmd_shift_ssif3));
+                /* <-IPA R2.4.1 */
+                
+                if (0 == p_scux_info_ch->p_ssif_info2->scux_channel)
+                {
+#if defined (__ICCARM__)
+                    was_masked = __disable_irq_iar();
+#else
+                    was_masked = __disable_irq();
+#endif
+
+                    /* clock mask */
+                    CPGSTBCR11 |= ((uint8_t)gb_cpg_scux_ssif_stbcr_bit[p_scux_info_ch->p_ssif_info2->ssif_cfg.ssif_ch_num]);
+
+                    if (0 == was_masked)
+                    {
+                        __enable_irq();
+                    }
+                }
+                
+                if (0 == p_scux_info_ch->p_ssif_info3->scux_channel)
+                {                
+#if defined (__ICCARM__)
+                    was_masked = __disable_irq_iar();
+#else
+                    was_masked = __disable_irq();
+#endif
+
+                    CPGSTBCR11 |= ((uint8_t)gb_cpg_scux_ssif_stbcr_bit[p_scux_info_ch->p_ssif_info3->ssif_cfg.ssif_ch_num]);
+
+                    if (0 == was_masked)
+                    {
+                        __enable_irq();
+                    }
+                }
+                
+                if (false == p_scux_info_ch->cancel_operate_flag)
+                {
+                    /* set NULL to SSIF information when cancel not on going */
+                    p_scux_info_ch->p_ssif_info2 = NULL;
+                    p_scux_info_ch->p_ssif_info3 = NULL;
+                }
+            }
+            if (false == p_scux_info_ch->cancel_operate_flag)
+            {
+                /* set NULL to SSIF information when cancel not on going */
+                p_scux_info_ch->p_ssif_info1 = NULL;
+            }
+            
+            if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+            {
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    *(p_scux_info_ch->p_scux_reg->mixmr_mix0_0) |= MIXIR_MIX0_INIT_SET;
+                    *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) &= ~MDBER_MIX0_MIXDBEN_SET;
+                }
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_AsyncStopHw
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetDigiVolRegister
+* @brief         Set digital volume register.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        none.
+******************************************************************************/
+    
+void SCUX_SetDigiVolRegister(const scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t audio_ch;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* check and set digital volume */
+        if (false != p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol_enable)
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 |= DVUCR_DVU0_VVMD_SET;
+        
+            for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
+            {
+                switch (audio_ch)
+                {
+                    case SCUX_AUDIO_CH_0 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL0R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;
+                       
+                    case SCUX_AUDIO_CH_1 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL1R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;
+                    
+                    case SCUX_AUDIO_CH_2 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL2R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;      
+            
+                    case SCUX_AUDIO_CH_3 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL3R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;  
+    
+                    case SCUX_AUDIO_CH_4 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL4R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;
+        
+                    case SCUX_AUDIO_CH_5 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL5R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;
+        
+                    case SCUX_AUDIO_CH_6 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL6R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;
+        
+                    case SCUX_AUDIO_CH_7 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL7R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;
+        
+                    default :
+                        /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                        /* <-IPA R3.5.2 */
+                        /* NOTREACHED on At the time of a normal performance */
+                    break;
+                }
+            }
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 &= ~DVUCR_DVU0_VVMD_SET;
+        }
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetDigiVolRegister
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetRampVolRegister
+* @brief         Set ramp volume register.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        none.
+******************************************************************************/
+    
+void SCUX_SetRampVolRegister(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t audio_ch;
+    uint32_t vrctr_value = 0;
+
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
+        {
+            if (false != p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol_enable[audio_ch])
+            {
+                vrctr_value |= (VRCTR_DVU0_VREN_SET << audio_ch);
+            }
+            else
+            {
+                vrctr_value &= ~(VRCTR_DVU0_VREN_SET << audio_ch);
+            }
+        }
+            
+        p_scux_info_ch->p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = vrctr_value;
+        
+        if (false == p_scux_info_ch->restart_ramp_flag)
+        {
+            /* set ramp paramteter to register when timming isn't restart after cancel */ 
+            /* ->IPA R2.4.1 Even if each parameters are max value, omission dose not occur. */
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = (uint32_t)((((uint32_t)p_scux_info_ch->dvu_cfg.dvu_ramp_vol.up_period << VRPDR_DVU0_VRPDUP_SHIFT) & VRPDR_DVU0_VRPDUP_MASK) | 
+                                                                  (((uint32_t)p_scux_info_ch->dvu_cfg.dvu_ramp_vol.down_period << VRPDR_DVU0_VRPDDW_SHIFT) & VRPDR_DVU0_VRPDDW_MASK));
+            /* <-IPA R2.4.1 */    
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = (p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_wait_time & VRWTR_DVU0_VRWT_MASK);
+        }
+        else
+        {
+            /* set fatest ramp parameter to register when timming is restart after cancel */ 
+            /* ->IPA R2.4.1 Even if each parameters are max value, omission dose not occur. */
+            /* when restart ,volume is changed immedeatly */
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = (uint32_t)((((uint32_t)SCUX_DVU_TIME_128DB_1STEP << VRPDR_DVU0_VRPDUP_SHIFT) & VRPDR_DVU0_VRPDUP_MASK) | 
+                                                                  (((uint32_t)SCUX_DVU_TIME_128DB_1STEP << VRPDR_DVU0_VRPDDW_SHIFT) & VRPDR_DVU0_VRPDDW_MASK));
+            /* <-IPA R2.4.1 */    
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = 0U;
+            p_scux_info_ch->restart_ramp_flag = false;
+        }   
+        p_scux_info_ch->p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol;
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetRampVolRegister
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetZerocrossMuteRegister
+* @brief         Set zerocross mute register.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+void SCUX_SetZerocrossMuteRegister(const scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t    audio_ch;
+    uint32_t zcmcr_value = 0;
+    uint32_t vevmr_value = 0;
+
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
+        {
+            if (false != p_scux_info_ch->dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch])
+            {
+                zcmcr_value |= (ZCMCR_DVU0_ZCEN_SET << audio_ch);
+                vevmr_value |= (VEVMR_DVU0_VEVMZCM_SET << audio_ch);
+            }
+            else
+            {
+                zcmcr_value &= ~(ZCMCR_DVU0_ZCEN_SET << audio_ch);
+                vevmr_value &= ~(VEVMR_DVU0_VEVMZCM_SET << audio_ch);
+            }
+        }
+        p_scux_info_ch->p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 = zcmcr_value;
+        p_scux_info_ch->p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = vevmr_value;
+
+        if (0U != zcmcr_value)
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 |= DVUCR_DVU0_ZCMD_SET;
+        }
+        else
+        {   
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 &= ~DVUCR_DVU0_ZCMD_SET;
+        }
+        
+    }
+        
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetZerocrossMuteRegister
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetMixVolRegister
+* @brief         Set MIX volume register.
+*
+*                Description:<br>
+*                
+* @param[in]     channel : SCUX channel number.
+* @retval        None.
+******************************************************************************/
+    
+void SCUX_SetMixVolRegister(const int_t channel)
+{
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    scux_info_ch_t * const p_scux_info_ch = SCUX_GetDrvChInfo(channel);
+
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) &= ~MDBER_MIX0_MIXDBEN_SET;
+        *(p_scux_info_ch->p_scux_reg->mdb_n_r_mix0_0) = p_info_drv->shared_info.mix_vol[channel];
+        *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) |= MDBER_MIX0_MIXDBEN_SET;
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetMixVolRegister
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_RxCallBack
+* @brief         Read request callback (mem to mem).
+*
+*                Description:<br>
+*                
+* @param[in]     param : SCUX channel number.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_DMA_CopyRxCallBack(union sigval const param)
+{
+    dma_trans_data_t dma_address_param;
+    int_t retval;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(param.sival_int);
+    
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (NULL != p_info_ch->p_rx_aio)
+        {
+            p_info_ch->p_rx_aio->aio_return = (ssize_t)p_info_ch->p_rx_aio->aio_nbytes;
+            ahf_complete(&p_info_ch->rx_que, p_info_ch->p_rx_aio);
+            p_info_ch->first_rx_flag = false;
+        }
+          
+        p_info_ch->rx_fifo_total_size += p_info_ch->dma_rx_current_size;
+        p_info_ch->dma_rx_current_size = 0;
+        p_info_ch->p_rx_aio = ahf_removehead(&p_info_ch->rx_que);
+                     
+        if (NULL != p_info_ch->p_rx_aio)
+        {
+            /* set nect data read */
+            dma_address_param.src_addr = (void *)p_info_ch->p_scux_reg->dmatu_n_cim;
+            dma_address_param.dst_addr = (void *)(p_info_ch->p_rx_aio->aio_buf);
+            dma_address_param.count = p_info_ch->p_rx_aio->aio_nbytes;
+                        
+            retval = R_DMA_Start(p_info_ch->dma_rx_ch, &dma_address_param, NULL);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+            else
+            {
+                p_info_ch->dma_rx_current_size = dma_address_param.count;
+            }
+        }
+        else
+        {
+            switch (p_info_ch->ch_stat)
+            {
+                case SCUX_CH_UNINIT :
+                    /* fall through */
+                case SCUX_CH_INIT :
+                    /* fall through */
+                case SCUX_CH_STOP :
+                    /* fall through */
+                case SCUX_CH_TRANS_IDLE :
+                    /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
+                break;                  
+                
+                case SCUX_CH_TRANS_RD :
+                    p_info_ch->ch_stat = SCUX_CH_TRANS_IDLE;
+                break;
+                                
+                case SCUX_CH_TRANS_WR :
+                    /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
+                break;              
+                                
+                case SCUX_CH_TRANS_RDWR :
+                    p_info_ch->ch_stat = SCUX_CH_TRANS_WR;
+                break;
+                
+                case SCUX_CH_STOP_WAIT :
+                    p_info_ch->ch_stat = SCUX_CH_STOP_WAIT_IDLE;
+                break;
+
+                case SCUX_CH_STOP_WAIT_IDLE :
+                    /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
+                break;
+
+                default :
+                    /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
+                break;
+            }
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_CopyRxCallBack
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_CommonTxNextDummyData
+* @brief         Set next dummy data for flush (mem to mem , SSIF direct route).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_DMA_CommonTxNextDummyData(scux_info_ch_t * const p_info_ch)
+{
+    int_t retval;
+    
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+        p_info_ch->dma_tx_current_size = 0;
+                    
+        retval = SCUX_FlushWriteStart(p_info_ch);
+        if (ESUCCESS != retval)
+        {
+            /* NON_NOTICE_ASSERT: DMA operation failed */
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_CommonTxNextDummyData
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_CopyTxEndFlush
+* @brief         End of flush operation (mem to mem route).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_DMA_CopyTxEndFlush(scux_info_ch_t * const p_info_ch)
+{
+    int_t retval;
+    int_t dma_ercd;
+    uint32_t tx_remain_size = 0;
+    uint32_t rx_remain_size = 0;
+    
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* finish send dummy data process, and SCUX stop process */
+        retval = R_DMA_Cancel(p_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd);
+        /* It isn't an error even if error code is EBADF, because it is already stopped. */
+        if ((ESUCCESS != retval) && (EBADF != dma_ercd))
+        {
+            /* NON_NOTICE_ASSERT: DMA operation failed */
+        }
+                    
+        p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+        p_info_ch->dma_tx_current_size = 0;
+               
+        retval = R_DMA_Cancel(p_info_ch->dma_rx_ch, &rx_remain_size, &dma_ercd);
+        /* It isn't an error even if error code is EBADF, because it is already stopped. */
+        if ((ESUCCESS != retval) && (EBADF != dma_ercd))
+        {
+            /* NON_NOTICE_ASSERT: DMA operation failed */
+        }
+        else
+        {
+            retval = R_DMA_Free(p_info_ch->dma_rx_ch, NULL);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: DMA operation failed */
+            }
+        }
+        p_info_ch->rx_fifo_total_size += p_info_ch->dma_rx_current_size;
+        p_info_ch->dma_rx_current_size = 0;
+                    
+        if (NULL != p_info_ch->p_rx_aio)
+        {
+            /* in case NULL, dummy data read */
+            p_info_ch->p_rx_aio->aio_return = (ssize_t)(p_info_ch->p_rx_aio->aio_nbytes - rx_remain_size);
+            ahf_complete(&p_info_ch->rx_que, p_info_ch->p_rx_aio);
+        }
+        ahf_cancelall(&p_info_ch->rx_que);
+        p_info_ch->p_rx_aio = NULL;
+                    
+        SCUX_AdjustAccessFifo(p_info_ch, tx_remain_size, rx_remain_size);
+                      
+        if (false != p_info_ch->src_cfg.mode_sync)
+        {
+            SCUX_SyncStopHw(p_info_ch);
+        }   
+        else    
+        {
+            SCUX_AsyncStopHw(p_info_ch);
+        }
+                    
+        p_info_ch->ch_stat = SCUX_CH_STOP;
+        if (NULL != p_info_ch->p_flush_callback)
+        {
+            p_info_ch->p_flush_callback(ESUCCESS);
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_CopyTxEndFlush
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_CopyTxNextRemainData
+* @brief         Set next remain data for flush (mem to mem route).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_DMA_CopyTxNextRemainData(scux_info_ch_t * const p_info_ch)
+{
+    dma_trans_data_t dma_address_param;
+    int_t retval;
+    
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* send remain tx data prcess for flush */
+        if (NULL != p_info_ch->p_tx_aio)
+        {
+            p_info_ch->p_tx_aio->aio_return = (ssize_t)p_info_ch->p_tx_aio->aio_nbytes;
+            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
+        }
+                
+        p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+        p_info_ch->dma_tx_current_size = 0;
+        p_info_ch->p_tx_aio = ahf_removehead(&p_info_ch->tx_que);
+                
+        if (NULL == p_info_ch->p_tx_aio)
+        {
+            retval = SCUX_FlushWriteStart(p_info_ch);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: DMA operation failed */
+            }
+        }
+        else
+        {
+            dma_address_param.src_addr = (void *)(p_info_ch->p_tx_aio->aio_buf);
+            dma_address_param.dst_addr = (void *)p_info_ch->p_scux_reg->dmatd_n_cim;
+            dma_address_param.count = p_info_ch->p_tx_aio->aio_nbytes;
+                        
+            retval = R_DMA_Start(p_info_ch->dma_tx_ch, &dma_address_param, NULL);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: DMA operation failed */
+            }
+            else
+            {
+                p_info_ch->dma_tx_current_size = dma_address_param.count;
+            }
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_CopyTxNextRemainData
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_CopyTxNextData
+* @brief         Set next data for normal operation (mem to mem route).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_DMA_CopyTxNextData(scux_info_ch_t * const p_info_ch)
+{
+    dma_trans_data_t dma_address_param;
+    int_t retval;
+    
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* normal send process */
+        if (NULL != p_info_ch->p_tx_aio)
+        {
+            p_info_ch->p_tx_aio->aio_return = (ssize_t)p_info_ch->p_tx_aio->aio_nbytes;
+            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
+        }
+            
+        p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+        p_info_ch->dma_tx_current_size = 0;
+        p_info_ch->p_tx_aio = ahf_removehead(&p_info_ch->tx_que);
+                
+        if (NULL != p_info_ch->p_tx_aio)
+        {
+            dma_address_param.src_addr = (void *)(p_info_ch->p_tx_aio->aio_buf);
+            dma_address_param.dst_addr = (void *)p_info_ch->p_scux_reg->dmatd_n_cim;
+            dma_address_param.count = p_info_ch->p_tx_aio->aio_nbytes;
+                    
+            retval = R_DMA_Start(p_info_ch->dma_tx_ch, &dma_address_param, NULL);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+            else
+            {
+                p_info_ch->dma_tx_current_size = dma_address_param.count;
+            }
+        }
+        else
+        {
+            switch (p_info_ch->ch_stat)
+            {
+                case SCUX_CH_UNINIT :
+                    /* fall through */
+                case SCUX_CH_INIT :
+                    /* fall through */
+                case SCUX_CH_STOP :
+                    /* fall through */
+                case SCUX_CH_TRANS_IDLE :
+                    /* fall through */
+                case SCUX_CH_TRANS_RD :
+                    /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
+                break;
+              
+                case SCUX_CH_TRANS_WR :
+                    p_info_ch->ch_stat = SCUX_CH_TRANS_IDLE;
+                break;                  
+                    
+                case SCUX_CH_TRANS_RDWR :
+                    p_info_ch->ch_stat = SCUX_CH_TRANS_RD;
+                break;
+                    
+                case SCUX_CH_STOP_WAIT :
+                    /* fall through */
+                case SCUX_CH_STOP_WAIT_IDLE :
+                    /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
+                break;
+                    
+                default :
+                    /* NOTREACHED on At the time of a normal performance */
+                break;                    
+            }           
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_CopyTxNextData
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_CopyTxCallBack
+* @brief         Write request callback (mem to mem route).
+*
+*                Description:<br>
+*                
+* @param[in]     param : SCUX channel number.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_DMA_CopyTxCallBack(union sigval const param)
+{
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(param.sival_int);
+    
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if ((SCUX_CH_STOP_WAIT == p_info_ch->ch_stat) || (SCUX_CH_STOP_WAIT_IDLE == p_info_ch->ch_stat))
+        {
+            /* data flush process */
+            if (false != p_info_ch->tx_dummy_run_flag)
+            {
+                if (0U == p_info_ch->flush_stop_size)
+                {
+                    SCUX_DMA_CopyTxEndFlush(p_info_ch);
+                }
+                else
+                {
+                    SCUX_DMA_CommonTxNextDummyData(p_info_ch);
+                }
+            }
+            else
+            {
+                SCUX_DMA_CopyTxNextRemainData(p_info_ch);   
+            }
+        }
+        else
+        {
+            SCUX_DMA_CopyTxNextData(p_info_ch);
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_CopyTxCallBack
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_DirectTxEndFlush
+* @brief         End of flush operation (SSIF Direct route).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_DMA_DirectTxEndFlush(scux_info_ch_t * const p_info_ch)
+{
+    int_t retval;
+    int_t dma_ercd;
+    uint32_t tx_remain_size = 0;
+    
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* finish send dummy data process, and SCUX stop process */
+        retval = R_DMA_Cancel(p_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd);
+        /* It isn't an error even if error code is EBADF, because it is already stopped. */
+        if ((ESUCCESS != retval) && (EBADF != dma_ercd))
+        {
+            /* NON_NOTICE_ASSERT: NULL pointer */
+        }
+        p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+        p_info_ch->dma_tx_current_size = 0;
+                                      
+        SCUX_AdjustAccessFifo(p_info_ch, tx_remain_size, 0);
+                      
+        SCUX_AsyncStopHw(p_info_ch);
+                  
+        p_info_ch->ch_stat = SCUX_CH_STOP;
+        if (NULL != p_info_ch->p_flush_callback)
+        {
+            p_info_ch->p_flush_callback(ESUCCESS);
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_DirectTxEndFlush
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_DirectTxNextRemainData
+* @brief         Set next remain data for flush (SSIF Direct route).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_DMA_DirectTxNextRemainData(scux_info_ch_t * const p_info_ch)
+{
+    dma_trans_data_t dma_next_address_param;
+    int_t retval;
+    
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (NULL != p_info_ch->p_tx_aio)
+        {
+            p_info_ch->p_tx_aio->aio_return = (ssize_t)p_info_ch->p_tx_aio->aio_nbytes;
+            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
+            p_info_ch->first_tx_flag = false;
+        }
+                
+
+        /* send remain tx data prcess for flush */
+        p_info_ch->p_tx_aio = p_info_ch->p_tx_next_aio;
+        p_info_ch->p_tx_next_aio = ahf_removehead(&p_info_ch->tx_que);
+        p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+        p_info_ch->dma_tx_current_size = 0;
+                    
+        if ((NULL != p_info_ch->p_tx_next_aio) && (NULL != p_info_ch->p_tx_aio))
+        {
+           /* 1.
+            * p_info_ch->p_tx_next_aio isn't NULL, and p_info_ch->p_tx_aio isn't NULL.
+            * Since, Next DMA is effective and p_info_ch->p_tx_aio is set to Next DMA
+            * The vaule of p_info_ch->dma_tx_current_size is updated to the value of 
+            * p_info_ch->dma_tx_next_size.
+            * The vaule of p_info_ch->dma_tx_next_size is updated to the value of DMA size
+            * on Next DMA.
+            */
+            dma_next_address_param.src_addr = (void *)(p_info_ch->p_tx_next_aio->aio_buf);
+            dma_next_address_param.dst_addr = (void *)p_info_ch->p_scux_reg->dmatd_n_cim;
+            dma_next_address_param.count = p_info_ch->p_tx_next_aio->aio_nbytes;
+                        
+            retval = R_DMA_NextData(p_info_ch->dma_tx_ch, &dma_next_address_param, NULL);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+            else
+            {
+                p_info_ch->dma_tx_current_size = p_info_ch->dma_tx_next_size;
+                p_info_ch->dma_tx_next_size = dma_next_address_param.count;
+            }
+        }
+        else if ((NULL != p_info_ch->p_tx_next_aio) && (NULL == p_info_ch->p_tx_aio))
+        {
+           /* 2.
+            * p_info_ch->p_tx_next_aio isn't NULL, and p_info_ch->p_tx_aio is NULL.
+            * Since, Next DMA is Stopped and DMA is restarted to p_info_ch->p_tx_aio
+            * The vaule of p_info_ch->dma_tx_current_size and p_info_ch->dma_tx_next_size 
+            * are updated to restart DMA value. 
+            */
+            retval = SCUX_DirectWriteStart(p_info_ch, p_info_ch->p_tx_next_aio);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+        }
+        else if ((NULL == p_info_ch->p_tx_next_aio) && (NULL == p_info_ch->p_tx_aio))
+        {
+            /* 3.
+             * p_info_ch->p_tx_next_aio is NULL, and p_info_ch->p_tx_aio is NULL.
+             * Since, all request finished, and flush data write start.
+             * The vaule of p_info_ch->dma_tx_current_size is updated to flush DMA value. 
+             */
+                        
+            retval = SCUX_FlushWriteStart(p_info_ch);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: DMA operation failed */
+            }
+        }
+        else
+        {
+           /* 4.
+            * p_info_ch->p_tx_next_aio is NULL, and p_info_ch->p_tx_aio isn't NULL.
+            * Since, Nothing new aio request, and processing of 2. or 3. is performed
+            * in the next loop.
+            * The vaule of p_info_ch->dma_tx_current_size is updated to the value of 
+            * p_info_ch->dma_tx_next_size.
+            */  
+                        
+            p_info_ch->dma_tx_current_size = p_info_ch->dma_tx_next_size;
+            p_info_ch->dma_tx_next_size = 0;
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_DirectTxNextRemainData
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_DirectTxNextData
+* @brief         Set next data normal operation (SSIF Direct route).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_DMA_DirectTxNextData(scux_info_ch_t * const p_info_ch)
+{
+    dma_trans_data_t dma_next_address_param;
+    int_t retval;
+    
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (NULL != p_info_ch->p_tx_aio)
+        {
+            p_info_ch->p_tx_aio->aio_return = (ssize_t)p_info_ch->p_tx_aio->aio_nbytes;
+            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
+            p_info_ch->first_tx_flag = false;
+        }
+           
+        /* normal send process */
+        p_info_ch->p_tx_aio = p_info_ch->p_tx_next_aio;
+        p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+        p_info_ch->p_tx_next_aio = ahf_removehead(&p_info_ch->tx_que);
+            
+        if ((NULL != p_info_ch->p_tx_next_aio) && (NULL != p_info_ch->p_tx_aio))
+        {
+            /* 1.
+             * p_info_ch->p_tx_next_aio isn't NULL, and p_info_ch->p_tx_aio isn't NULL.
+.            * Since, Next DMA is effective and p_info_ch->p_tx_aio is set to Next DMA
+             * The vaule of p_info_ch->dma_tx_current_size is updated to the value of 
+             * p_info_ch->dma_tx_next_size.
+             * The vaule of p_info_ch->dma_tx_next_size is updated to the value of DMA size
+             * on Next DMA.
+             */
+            dma_next_address_param.src_addr = (void *)(p_info_ch->p_tx_next_aio->aio_buf);
+            dma_next_address_param.dst_addr = (void *)p_info_ch->p_scux_reg->dmatd_n_cim;
+            dma_next_address_param.count = p_info_ch->p_tx_next_aio->aio_nbytes;
+                    
+            retval = R_DMA_NextData(p_info_ch->dma_tx_ch, &dma_next_address_param, NULL);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+            else
+            {
+                p_info_ch->dma_tx_current_size = p_info_ch->dma_tx_next_size;
+                p_info_ch->dma_tx_next_size = dma_next_address_param.count;
+            }
+        }
+        else if ((NULL != p_info_ch->p_tx_next_aio) && (NULL == p_info_ch->p_tx_aio))
+        {
+            /* 2.
+             * p_info_ch->p_tx_next_aio isn't NULL, and p_info_ch->p_tx_aio is NULL.
+             * Since, Next DMA is Stopped and DMA is restarted to p_info_ch->p_tx_aio
+             * The vaule of p_info_ch->dma_tx_current_size and p_info_ch->dma_tx_next_size 
+             * are updated to restart DMA value. 
+             */
+                   
+            retval = SCUX_DirectWriteStart(p_info_ch, p_info_ch->p_tx_next_aio);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+        }
+        else if((NULL == p_info_ch->p_tx_next_aio) && (NULL == p_info_ch->p_tx_aio))
+        {
+            /* 3.
+             * p_info_ch->p_tx_next_aio is NULL, and p_info_ch->p_tx_aio is NULL.
+             * Since, all request finished, and status is made to change IDLE.
+             * The vaule of p_info_ch->dma_tx_current_size is updated to 0. 
+             */
+            p_info_ch->ch_stat = SCUX_CH_TRANS_IDLE;
+            p_info_ch->dma_tx_current_size = 0;
+                    
+        }
+        else
+        {
+            /* 4.
+             * p_info_ch->p_tx_next_aio is NULL, and p_info_ch->p_tx_aio isn't NULL.
+             * Since, Nothing new aio request, and processing of 2. or 3. is performed
+             * in the next loop.
+             * The vaule of p_info_ch->dma_tx_current_size is updated to the value of 
+             * p_info_ch->dma_tx_next_size.
+             */                 
+                
+            p_info_ch->dma_tx_current_size = p_info_ch->dma_tx_next_size;
+            p_info_ch->dma_tx_next_size = 0;
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_DirectTxNextData
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_DirectTxCallBack
+* @brief         Write request callback (SSIF Direct route).
+*
+*                Description:<br>
+*                
+* @param[in]     param : SCUX channel number.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_DMA_DirectTxCallBack(union sigval const param)
+{
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(param.sival_int);
+    
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (SCUX_CH_STOP_WAIT == p_info_ch->ch_stat)
+        {
+            /* data flush process */
+            if (false != p_info_ch->tx_dummy_run_flag)
+            {                
+                if (0U == p_info_ch->flush_stop_size)
+                {
+                    SCUX_DMA_DirectTxEndFlush(p_info_ch);
+                }
+                else
+                {
+                    SCUX_DMA_CommonTxNextDummyData(p_info_ch);
+                }
+            }
+            else
+            {
+                SCUX_DMA_DirectTxNextRemainData(p_info_ch);
+            }
+        }
+        else
+        {
+            SCUX_DMA_DirectTxNextData(p_info_ch);
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_DirextTxCallBack
+******************************************************************************/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_src/scux/scux_if.c	Fri Oct 02 03:03:25 2015 +0000
@@ -0,0 +1,1796 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         scux_if.c
+* $Rev: 1674 $
+* $Date:: 2015-05-29 16:35:57 +0900#$
+* @brief        SCUX Driver interface functions
+
+*******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+
+#include "scux.h"
+#include "bsp_util.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+#define SCUX_PATH_CH0 "\\0"    /**< channel 0 pathname */
+#define SCUX_PATH_CH1 "\\1"    /**< channel 1 pathname */
+#define SCUX_PATH_CH2 "\\2"    /**< channel 2 pathname */
+#define SCUX_PATH_CH3 "\\3"    /**< channel 3 pathname */
+#define MAX_PATH_SEARCH_LEN (32U)
+
+/******************************************************************************
+Private global tables
+******************************************************************************/
+
+#if(1) /* mbed */
+#else  /* not mbed */
+static IOIF_DRV_API gb_ioif_scux_cb_table;
+#endif /* end mbed */
+
+static const char_t* const p_gb_device_name[SCUX_CH_NUM] =
+{
+    SCUX_PATH_CH0,
+    SCUX_PATH_CH1,
+    SCUX_PATH_CH2,
+    SCUX_PATH_CH3
+};
+
+/******************************************************************************
+Private global driver semaphore informationn
+******************************************************************************/
+
+/******************************************************************************
+ Function prototypes
+ *****************************************************************************/
+#if(1) /* mbed */
+#else  /* not mbed */
+static void* R_SCUX_Init(void * p_config_data, int32_t * const p_errno);
+static int_t R_SCUX_UnInit(void *p_driver_instance, int32_t * const p_errno);
+static int_t R_SCUX_Open(void * const p_driver_instance, const char_t * p_path_name, const int_t flags, int_t mode, int32_t * const p_errno);
+static int_t R_SCUX_Close(void * const p_fd, int32_t * const p_errno);
+static int_t R_SCUX_Ioctl(void * const p_fd, const int_t request, void * const p_buf, int32_t * const p_errno);
+static int_t R_SCUX_WriteAsync(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno);
+static int_t R_SCUX_ReadAsync(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno);
+static int_t R_SCUX_Cancel(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno);
+#endif /* end mbed */
+static void  SCUX_SetErrCode(const int_t error_code, int32_t * const p_errno);
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+#if(1) /* mbed */
+#else  /* not mbed */
+/**************************************************************************//**
+* Function Name: R_SCUX_MakeCbTbl
+* @brief         Returns the SCUX driver callback function table.
+*
+*                Description:<br>
+*                
+* @param         none
+* @retval        pointer of sample driver callback table
+******************************************************************************/
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+IOIF_DRV_API* R_SCUX_MakeCbTbl(void)
+/* <-IPA M1.1.1 */
+{
+    IOIF_DRV_API* const p_api = &gb_ioif_scux_cb_table;
+
+    /* ->MISRA 16.4, IPA M4.5.1 This description is based on the way to fill out OS defined. */
+    p_api->family = IOIF_SERIAL_FAMILY;
+    p_api->fns.serial.initialise   = &R_SCUX_Init;
+    p_api->fns.serial.uninitialise = &R_SCUX_UnInit;
+    p_api->fns.serial.open         = &R_SCUX_Open;
+    p_api->fns.serial.close        = &R_SCUX_Close;
+    p_api->fns.serial.ioctl        = &R_SCUX_Ioctl;
+    p_api->fns.serial.write_a      = &R_SCUX_WriteAsync;
+    p_api->fns.serial.read_a       = &R_SCUX_ReadAsync;
+    p_api->fns.serial.cancel       = &R_SCUX_Cancel;
+    /* <-MISRA 16.4, IPA M4.5.1 */
+     
+    return p_api;
+}
+
+/******************************************************************************
+End of function R_SCUX_MakeCbTbl
+******************************************************************************/
+#endif /* end mbed */
+
+/**************************************************************************//**
+* Function Name: SCUX_SetErrCode
+* @brief         Set error code to error code pointer.
+*
+*                Description:<br>
+*                If error code pointer is NULL, nothing is done.
+* @param[in]     error_code :Error code.
+* @param[in,out] p_errno    :Pointer of set error code.
+* @retval        none
+******************************************************************************/
+static void SCUX_SetErrCode(int_t error_code, int32_t * const p_errno)
+{
+    if (NULL != p_errno)
+    {
+        *p_errno = error_code;
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function R_SCUX_SetErrCode
+******************************************************************************/
+
+/******************************************************************************
+Private functions
+******************************************************************************/
+
+#if(1) /* mbed */
+/**************************************************************************//**
+* Function Name: R_SCUX_InitOne
+* @brief         Init SCUX driver.
+*
+*                Description:<br>
+*                
+* @param[in]     channel    :Initialize channel number.
+* @param[in]     p_config_data :pointer of several parameters array per channels
+* @param[in,out] p_errno    :pointer of error code
+*                            error code -
+*                            ENOMEM : Making semaphore failed.
+*                            EBUSY  : SCUX driver has been initialized already.
+*                            EFAULT : p_config_data is NULL.
+*                            EFAULT : Internal error is occured.
+* @retval        other than (-1)
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+#else  /* not mbed */
+/**************************************************************************//**
+* Function Name: R_SCUX_Init
+* @brief         Init SCUX driver.
+*
+*                Description:<br>
+*                
+* @param[in]     p_config_data :pointer of several parameters array per channels
+* @param[in,out] p_errno    :pointer of error code
+*                            error code -
+*                            ENOMEM : Making semaphore failed.
+*                            EBUSY  : SCUX driver has been initialized already.
+*                            EFAULT : p_config_data is NULL.
+*                            EFAULT : Internal error is occured.
+* @retval        other than (-1)
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+#endif /* end mbed */
+/* ->MISRA 16.7 'p_config_data' is based on the way to fill out OS defined. */
+/* ->IPA M1.11.1 */
+#if(1) /* mbed */
+void *R_SCUX_InitOne(const int_t channel, const void * const p_config_data, int32_t * const p_errno) 
+#else  /* not mbed */
+static void *R_SCUX_Init(void * p_config_data, int32_t * const p_errno) 
+#endif /* end mbed */
+/* <-IPA M1.11.1 */
+/* <-MISRA 16.7 */
+{
+    int_t         ercd;
+    void          *ret;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+#if(1) /* mbed */
+    scux_info_ch_t  * p_info_ch;
+#endif /* end mbed */
+
+    if (NULL == p_info_drv)
+    {
+        ercd = EFAULT;
+    }
+#if(1) /* mbed */
+    else if ((SCUX_CH_0 > channel) || ( SCUX_CH_NUM <= channel))
+    {
+        ercd = EFAULT;
+    }
+#endif /* end mbed */
+    else
+    {
+#if(1) /* mbed */
+        p_info_ch = SCUX_GetDrvChInfo(channel);
+
+        if (NULL == p_info_ch)
+        {
+            ercd = EFAULT;
+        }
+        else if (false != p_info_ch->enabled)
+        {
+            ercd = EBUSY;
+        }
+#else  /* not mbed */
+        if (SCUX_DRV_UNINIT != p_info_drv->drv_stat)
+        {
+            ercd = EBUSY;
+        }
+#endif /* end mbed */
+        else
+        {
+            if (NULL == p_config_data)
+            {
+                /* set error return value */
+                ercd = EFAULT;
+            }
+            else
+            {
+                /* init SCUX driver */
+#if(1) /* mbed */
+                ercd = SCUX_InitializeOne(channel, (const scux_channel_cfg_t *)p_config_data);
+#else  /* not mbed */
+                ercd = SCUX_Initialize((scux_channel_cfg_t *)p_config_data);
+#endif /* end mbed */
+            }
+        }
+    }
+    
+    if (ESUCCESS == ercd)
+    {
+        ret = (void *)p_info_drv;
+    }
+    else
+    {
+        ret = (void *)(EERROR);
+    }
+
+    SCUX_SetErrCode(ercd, p_errno);
+    
+    return ret;
+}
+
+#if(1) /* mbed */
+/******************************************************************************
+End of function R_SCUX_InitOne
+******************************************************************************/
+#else  /* not mbed */
+/******************************************************************************
+End of function R_SCUX_Init
+******************************************************************************/
+#endif /* end mbed */
+
+#if(1) /* mbed */
+/**************************************************************************//**
+* Function Name: R_SCUX_UnInitOne
+* @brief         Uninit SCUX driver.
+*
+*                Description:<br>
+*                
+* @param[in]     channel    :Uninitialize channel number.
+* @param[in]     p_driver_instance :which was returned by R_SCUX_Init
+* @param[in,out] p_errno    :pointer of error code
+*                            error code -
+*                            EBADF : Driver status isn't SCUX_DRV_INIT.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+#else  /* not mbed */
+/**************************************************************************//**
+* Function Name: R_SCUX_UnInit
+* @brief         Uninit SCUX driver.
+*
+*                Description:<br>
+*                
+* @param[in]     p_driver_instance :which was returned by R_SCUX_Init
+* @param[in,out] p_errno    :pointer of error code
+*                            error code -
+*                            EBADF : Driver status isn't SCUX_DRV_INIT.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+#endif /* end mbed */
+/* ->MISRA 16.7 'p_driver_instance' is based on the way to fill out OS defined. */
+/* ->IPA M1.11.1 */
+#if(1) /* mbed */
+int_t R_SCUX_UnInitOne(const int_t channel, const void* const p_driver_instance, int32_t * const p_errno)
+#else  /* not mbed */
+static int_t R_SCUX_UnInit(void* p_driver_instance, int32_t * const p_errno)
+#endif /* end mbed */
+/* <-IPA M1.11.1 */
+/* <-MISRA 16.7 */
+{
+    int_t            retval = ESUCCESS;
+    int_t            ercd = ESUCCESS;
+    scux_info_drv_t  * const p_info_drv = SCUX_GetDrvInstance();
+#if(1) /* mbed */
+    scux_info_ch_t   * p_info_ch;
+#endif /* end mbed */
+
+    UNUSED_ARG(p_driver_instance);
+    
+    if (NULL == p_info_drv)
+    {
+        ercd = EFAULT;
+    }
+#if(1) /* mbed */
+    else if ((SCUX_CH_0 > channel) || ( SCUX_CH_NUM <= channel))
+    {
+        ercd = EFAULT;
+    }
+#endif /* end mbed */
+    else
+    {
+        if (SCUX_DRV_INIT != p_info_drv->drv_stat)
+        {
+            ercd = EBADF;
+        }
+        else
+        {
+#if(1) /* mbed */
+            p_info_ch = SCUX_GetDrvChInfo(channel);
+
+            if (NULL == p_info_ch)
+            {
+                ercd = EFAULT;
+            }
+            else if (false == p_info_ch->enabled)
+            {
+                ercd = EBADF;
+            }
+            else
+            {
+                SCUX_UnInitializeOne(channel);
+            }
+#else  /* not mbed */
+            SCUX_UnInitialize();
+#endif /* end mbed */
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+    }
+    SCUX_SetErrCode(ercd, p_errno);
+    
+    return retval;
+}
+
+#if(1) /* mbed */
+/******************************************************************************
+End of function R_SCUX_UnInitOne
+******************************************************************************/
+#else  /* not mbed */
+/******************************************************************************
+End of function R_SCUX_UnInit
+******************************************************************************/
+#endif /* end mbed */
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Open
+* @brief         Open SCUX Channel.
+*
+*                Description:<br>
+*                
+* @param[in]     p_driver_instance:which was returned by R_SCUX_Init()
+* @param[in]     p_path_name   :device Name
+* @param[in]     flags         :specifies the access mode whether the channel is 
+*                               opened for a read or a write
+* @param[in]     mode          :specifies the permissions to use in case a new file
+*                               is created (not used for serial family driver)
+* @param[in,out] p_errno       :pointer of error code
+*                               error code -
+*                               ENOMEM : Craeaton of IOIF queue is failed.
+*                               ENOENT : Pathname is incorrect length.
+*                               ENOENT : Channel information is NULL.
+*                               EACCES : Setting to flag is other than O_WONLY or O_RDWR
+*                               EMFILE : Allocation of write DMA channel is failed.
+*                               ENOTSUP : Channel is not support.
+*                               EFAULT : Internal error is occured.
+*                               
+* @retval        Except ERROR -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+/* ->IPA M1.11.1 This description is based on the way to fill out OS defined. */
+#if(1) /* mbed */
+int_t R_SCUX_Open(void * const p_driver_instance, const char_t * const p_path_name, const int_t flags, const int_t mode, int32_t * const p_errno)
+#else  /* not mbed */
+static int_t R_SCUX_Open(void * const p_driver_instance, const char_t * p_path_name, const int_t flags, int_t mode , int32_t * const p_errno)
+#endif /* end mbed */
+/* <-IPA M1.11.1 */
+{
+    int_t ercd = ESUCCESS;
+    osStatus sem_ercd;
+    int32_t  sem_wait_ercd;
+    void* p_channel_handle;
+    scux_info_drv_t * const p_info_drv = (scux_info_drv_t *)p_driver_instance;
+    scux_info_ch_t *p_info_ch = NULL;
+    uint32_t open_channel;
+    size_t pathname_len;
+    size_t compare_len;
+
+    UNUSED_ARG(mode);
+
+    /* check driver instance */
+    if (NULL == p_driver_instance)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (NULL == p_info_drv)
+        {
+            ercd = EFAULT;
+        }
+        else
+        {
+            if (SCUX_DRV_INIT != p_info_drv->drv_stat)
+            {
+                ercd = EFAULT;
+            }
+        }
+    }
+    
+    /* check path name */
+    if (ESUCCESS == ercd)
+    {
+        if (NULL == p_info_drv)
+        {
+            ercd = EFAULT;
+        }
+        else
+        {
+            if (NULL == p_path_name)
+            {
+                ercd = EFAULT;
+            }
+            else
+            {
+                /* check length of path name */
+                pathname_len = SCUX_StrNLen(p_path_name, MAX_PATH_SEARCH_LEN);
+                if ( (0U == pathname_len) || (MAX_PATH_SEARCH_LEN == pathname_len) )
+                {
+                    ercd = ENOENT;
+                }
+                else
+                {
+                    for (open_channel = 0; ((open_channel < SCUX_CH_NUM) && (NULL == p_info_ch)); open_channel++)
+                    {
+                        /* Avoid reading beyond the end of the shortest of the two strings */
+                        compare_len = SCUX_StrNLen(p_gb_device_name[open_channel], MAX_PATH_SEARCH_LEN);
+                        if (pathname_len < compare_len)
+                        {
+                            compare_len = pathname_len;
+                        }
+        
+                        if (0 == strncmp(p_path_name, p_gb_device_name[open_channel], compare_len))
+                        {
+                            if (NULL != p_info_drv->info_ch)
+                            {
+                                p_info_ch = &p_info_drv->info_ch[open_channel]; /* found a match */
+                            }
+                        }           
+                    }
+                    
+                    if (NULL == p_info_ch)
+                    {
+                        ercd = ENOENT; /* Pathname not recognised */
+                    }
+                }
+            }
+        }
+    }
+    
+    if (NULL != p_info_ch)
+    {
+        if (ESUCCESS == ercd)
+        {
+            if ((O_WRONLY != flags) && (O_RDWR != flags))
+            {
+                ercd = EACCES;
+            }
+            
+            /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+            sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* <-MISRA 1.2 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT;
+            }
+            else
+            {
+                if (false == p_info_ch->enabled)
+                {
+                    ercd = ENOTSUP;
+                }
+                
+                if (ESUCCESS == ercd)
+                {
+                    if (SCUX_CH_INIT != p_info_ch->ch_stat)
+                    {
+                        ercd = EBUSY;
+                    }
+                }
+    
+                if (ESUCCESS == ercd)
+                {
+                    ercd = SCUX_OpenChannel(p_info_ch->channel, flags);
+                }
+            }
+            sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT;
+            }
+        }
+    }
+
+    if (ESUCCESS == ercd)
+    {
+        p_channel_handle = (void*)p_info_ch;
+    }
+    else
+    {
+        p_channel_handle = (void*)EERROR;
+    }
+    SCUX_SetErrCode(ercd, p_errno);
+    
+    return (int_t)p_channel_handle;
+}
+
+/******************************************************************************
+End of function R_SCUX_Open
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Close
+* @brief         Close SCUX Channel.
+*
+*                Description:<br>
+*                
+* @param[in]     p_fd:which was returned by R_SCUX_Init()
+* @param[in,out] p_errno:pointer of error code
+*                        error code -
+*                           EFAULT : Internal error is occured.
+*                               
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+#if(1) /* mbed */
+int_t R_SCUX_Close(void * const p_fd, int32_t * const p_errno)
+#else  /* not mbed */
+static int_t R_SCUX_Close(void * const p_fd, int32_t * const p_errno)
+#endif /* end mbed */
+{
+    int_t retval = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    int32_t sem_wait_ercd;
+    osStatus sem_ercd;
+    scux_info_ch_t * const p_info_ch = p_fd;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_ch) || (NULL == p_info_drv))
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (SCUX_DRV_INIT != p_info_drv->drv_stat)
+        {
+            ercd = EFAULT;
+        }
+        
+        if (ESUCCESS == ercd)
+        {
+            /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+            sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* <-MISRA 1.2 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT;
+            }
+            
+            if (ESUCCESS == ercd)
+            {
+                if (false == p_info_ch->enabled)
+                {
+                    ercd = EFAULT;
+                }
+                
+                if (ESUCCESS == ercd)
+                {
+                    if ((SCUX_CH_UNINIT == p_info_ch->ch_stat) ||
+                        (SCUX_CH_INIT == p_info_ch->ch_stat))
+                    {
+                        ercd = EFAULT;
+                    }
+                }
+                
+                if (ESUCCESS == ercd)
+                {
+                    /* close channel */
+                    ercd = SCUX_CloseChannel(p_info_ch->channel);               
+                }
+            }
+            sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set error return value */
+                    ercd = EFAULT;
+            }
+            
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+    }
+    SCUX_SetErrCode(ercd, p_errno);
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function R_SCUX_Close
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Ioctl
+* @brief         SCUX driver IOCTL function.
+*
+*                Description:<br>
+*                
+* @param[in]     p_fd: pointer of SCUX handler
+* @param[in]     request:IOCTL request code
+* @param[in]     p_buf  :Data buffer for IOCTL request code.
+* @param[in,out] p_errno:pointer of error code
+*                        error code -
+*                           EINVAL : IOCTL request code is unexpected value.
+*                           EFAULT : Internal error is occured.
+*                           other value : The value depending on IOCTL request code.
+*                                         Refer to the function of scux_ioctl.c for those meanings. 
+*                               
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+#if(1) /* mbed */
+int_t R_SCUX_Ioctl(void * const p_fd, const int_t request, void * const p_buf, int32_t * const p_errno)
+#else  /* not mbed */
+static int_t R_SCUX_Ioctl(void * const p_fd, const int_t request, void * const p_buf, int32_t * const p_errno)
+#endif /* end mbed */
+{
+    int_t retval = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    int32_t sem_wait_ercd;
+    int_t  was_masked;
+    osStatus sem_ercd;
+    scux_info_ch_t * const p_info_ch = p_fd;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_ch) || (NULL == p_info_drv))
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (SCUX_DRV_INIT != p_info_drv->drv_stat)
+        {
+            ercd = EFAULT;
+        }
+    
+        if (ESUCCESS == ercd)
+        {
+            /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+            if (0 == R_ExceptionalMode())
+            {
+                sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+                /* <-MISRA 10.6 */
+                /* <-MISRA 1.2 */
+                /* semaphore error check */
+                if ((-1) == sem_wait_ercd)
+                {
+                    /* set error return value */
+                    ercd = EFAULT;
+                }
+            }
+            
+            if (ESUCCESS == ercd)
+            {
+                if (false == p_info_ch->enabled)
+                {
+                    ercd = EFAULT;
+                }
+                
+                if (ESUCCESS == ercd)
+                {
+                    if ((SCUX_CH_UNINIT == p_info_ch->ch_stat) ||
+                        (SCUX_CH_INIT == p_info_ch->ch_stat))
+                    {
+                        ercd = EFAULT;
+                    }
+                }
+                
+            }
+            
+            if (0 == R_ExceptionalMode())
+            {
+                sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                /* semaphore error check */
+                if (osOK != sem_ercd)
+                {
+                    /* set error return value */
+                    ercd = EFAULT;
+                }
+            }
+            
+            if (ESUCCESS == ercd)
+            {
+                switch (request)
+                {
+                    case SCUX_IOCTL_SET_START:
+                    
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                        sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            if (SCUX_CH_STOP != p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY;
+                            }
+                            else
+                            {
+                                ercd = SCUX_IoctlTransStart(p_info_ch->channel);
+                            }
+                        }
+                        
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                        
+                    break;
+            
+                    case SCUX_IOCTL_SET_FLUSH_STOP:
+                    
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                        sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            /* check p_Buf */
+                            if (NULL == p_buf)
+                            {
+                                ercd = EFAULT;
+                            }
+                            else
+                            {                    
+#if defined (__ICCARM__)
+                                was_masked = __disable_irq_iar();
+#else
+                                was_masked = __disable_irq();
+#endif    
+                                if (SCUX_CH_STOP == p_info_ch->ch_stat)
+                                {
+                                    ercd = EBUSY;
+                                }
+                                
+                                /* The mesure to MISRA 1.1 , SEC P1.1.1 */
+                                if ((ESUCCESS != ercd) && (0 == was_masked))
+                                {
+                                    /* enable all irq when ch_stat is SCUX_CH_STOP */
+                                    __enable_irq();                                 
+                                }
+                                
+                                if (ESUCCESS == ercd)
+                                {
+                                    /* ->MISRA 11.1 Since it is necessary to register a callback function, 
+                                    the cast from a void pointer is performed intentionally. */
+                                    ercd = SCUX_IoctlFlushStop(p_info_ch->channel, (void ( *)(int_t))p_buf, was_masked);
+                                    /* <-MISRA 11.1 */
+                                }
+                                
+                            }
+                        }
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                                                
+                    break;
+            
+                    case SCUX_IOCTL_SET_CLEAR_STOP:
+    
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/                   
+                        sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+#if defined (__ICCARM__)
+                            was_masked = __disable_irq_iar();
+#else
+                            was_masked = __disable_irq();
+#endif    
+                            if (SCUX_CH_STOP == p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY;
+                                        
+                                if (0 == was_masked)
+                                {
+                                    /* enable all irq */
+                                    __enable_irq();
+                                }                                
+                            }
+                            else
+                            {
+                                /* This exclusive access control ends in the SCUX_IoctlClearStop */
+                                ercd = SCUX_IoctlClearStop(p_info_ch->channel, was_masked);
+                            }
+                        }
+                        
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                            
+                    break;
+                        
+                    case SCUX_IOCTL_SET_ROUTE:
+    
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/                     
+                        sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            if (SCUX_CH_STOP != p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY;
+                            }
+                            else
+                            {
+                                if (NULL == p_buf)
+                                {
+                                    ercd = EFAULT;
+                                }
+                                else
+                                {
+                                    SCUX_IoctlSetRoute(p_info_ch->channel, *(scux_route_t *)p_buf);
+                                }
+                            }
+                        }
+                        
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                            
+                    break;
+                        
+                    case SCUX_IOCTL_SET_PIN_CLK:
+    
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/                     
+                        sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            if (SCUX_CH_STOP != p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY;
+                            }
+                            else
+                            {
+                                if (NULL == p_buf)
+                                {
+                                    ercd = EFAULT;
+                                }
+                                else
+                                {
+                                    ercd = SCUX_IoctlSetPinClk(p_info_ch->channel, (scux_ssif_pin_clk_t *)p_buf);
+                                }
+                            }
+                        }
+                        
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                        
+                    break;
+    
+                    case SCUX_IOCTL_SET_PIN_MODE:
+    
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/                     
+                        sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            if (SCUX_CH_STOP != p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY;
+                            }
+                            else
+                            {
+                                if (NULL == p_buf)
+                                {
+                                    ercd = EFAULT;
+                                }
+                                else
+                                {
+                                    ercd = SCUX_IoctlSetPinMode(p_info_ch->channel, (scux_ssif_pin_mode_t *)p_buf);
+                                }
+                            }
+                        }
+                        
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }                    
+                            
+                    break;
+                    
+                    case SCUX_IOCTL_SET_SRC_CFG:
+    
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/                     
+                        sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            if (SCUX_CH_STOP != p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY;
+                            }
+                            else
+                            {
+                                if (NULL == p_buf)
+                                {
+                                    ercd = EFAULT;
+                                }
+                                else
+                                {
+                                    SCUX_IoctlSetSrcCfg(p_info_ch->channel, (scux_src_cfg_t *)p_buf);
+                                }
+                            }
+                        }
+                        
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                            
+                    break;
+                            
+                    case SCUX_IOCTL_SET_DVU_CFG:
+    
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/                     
+                        sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            if (SCUX_CH_STOP != p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY;
+                            }
+                            else
+                            {
+                                if (NULL == p_buf)
+                                {
+                                    ercd = EFAULT;
+                                }
+                                else
+                                {
+                                    SCUX_IoctlSetDvuCfg(p_info_ch->channel, (scux_dvu_cfg_t *)p_buf);
+                                }
+                            }   
+                        }
+                        
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }                    
+                        
+                    break;
+                       
+                    case SCUX_IOCTL_SET_DVU_DIGI_VOL:
+                        
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            ercd = SCUX_IoctlSetDvuDigiVol(p_info_ch->channel, (scux_dvu_digi_vol_t *)p_buf);
+                        }
+                            
+                    break;
+                        
+                    case SCUX_IOCTL_SET_DVU_RAMP_VOL:
+                        
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            ercd = SCUX_IoctlSetDvuRampVol(p_info_ch->channel, (scux_dvu_ramp_vol_t *)p_buf);
+                        }
+                            
+                    break;
+                        
+                    case SCUX_IOCTL_SET_ZEROCROSS_MUTE:
+                        
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            ercd = SCUX_IoctlSetDvuZerocrossMute(p_info_ch->channel, (scux_zc_mute_t *)p_buf);
+                        }
+                            
+                    break;
+                        
+                    case SCUX_IOCTL_SET_STOP_MUTE:
+                        
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            ercd = SCUX_IoctlSetStopMute(p_info_ch->channel, *(uint32_t *)p_buf);
+                        }
+                            
+                    break;
+                        
+                    case SCUX_IOCTL_SET_MIX_CFG:
+                        
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            ercd = SCUX_IoctlSetMixCfg((scux_mix_cfg_t *)p_buf);
+                        }
+                            
+                    break;
+                        
+                    case SCUX_IOCTL_SET_MIX_VOL:
+                        
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            ercd = SCUX_IoctlSetMixVol(p_info_ch->channel, *(uint32_t *)p_buf);
+                        }
+                    
+                    break;
+                        
+                    case SCUX_IOCTL_SET_SSIF_CFG:
+    
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/                     
+                        sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            if (SCUX_CH_STOP != p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY;
+                            }
+                            else
+                            {
+                                if (NULL == p_buf)
+                                {
+                                    ercd = EFAULT;
+                                }
+                                else
+                                {
+                                    ercd = SCUX_IoctlSetSsifCfg((scux_ssif_cfg_t *)p_buf);
+                                }
+                            }
+                        }
+                        
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }                    
+                            
+                    break;
+                        
+                    case SCUX_IOCTL_GET_WRITE_STAT:
+                    
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            SCUX_IoctlGetWriteStat(p_info_ch->channel, (uint32_t *)p_buf);
+                        }
+                            
+                    break;
+                    
+                    case SCUX_IOCTL_GET_READ_STAT:
+                    
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            SCUX_IoctlGetReadStat(p_info_ch->channel, (uint32_t *)p_buf);
+                        }
+                            
+                    break;
+                        
+                    case SCUX_IOCTL_GET_DVU_STAT:
+                    
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            SCUX_IoctlGetDvuStat(p_info_ch->channel, (uint32_t *)p_buf);
+                        }
+                            
+                    break;
+                    
+                    case SCUX_IOCTL_GET_MUTE_STAT:
+                    
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            SCUX_IoctlGetMuteStat(p_info_ch->channel, (uint32_t *)p_buf);
+                        }
+                            
+                    break;
+                        
+                    case SCUX_IOCTL_GET_MIX_STAT:
+                        
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            SCUX_IoctlGetMixStat(p_info_ch->channel, (uint32_t *)p_buf);
+                        }
+                            
+                    break;
+                                            
+                    default:
+                        ercd = EINVAL;
+                    break;
+                }
+            }
+        }
+    }
+    
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+    }
+    SCUX_SetErrCode(ercd, p_errno);
+    
+    return retval;
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Ioctl
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_WriteAsync
+* @brief         SCUX driver asynchronous write.
+*
+*                Description:<br>
+*                
+* @param[in]     p_fd   :channel handle which was returned by R_SCUX_Open
+* @param[in]     p_aio  :aio control block.
+* @param[in,out] p_errno:pointer of error code
+*                               error code -
+*                               EBADF : Channel status isn't SCUX_CH_STOP or SCUX_CH_STOP_WAIT. 
+*                               EINVAL : p_fd is NULL.
+*                               EINVAL : write size is 0.
+*                               EFAULT : Internal error is occured.
+*                               
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+#if(1) /* mbed */
+int_t R_SCUX_WriteAsync(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno)
+#else  /* not mbed */
+static int_t R_SCUX_WriteAsync(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno)
+#endif /* end mbed */
+{
+    int_t retval = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    int_t sem_ercd;
+    int32_t  sem_wait_ercd;
+    int_t was_masked;
+    scux_info_ch_t * const p_info_ch = p_fd;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_ch) || (NULL == p_aio) || (NULL == p_info_drv))
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (0U == p_aio->aio_nbytes)
+        {
+            ercd = EINVAL;
+        }
+        
+        if (ESUCCESS == ercd)
+        {
+            if (SCUX_DRV_INIT != p_info_drv->drv_stat)
+            {
+                ercd = EFAULT;
+            }
+        }
+        
+        if (ESUCCESS == ercd)
+        {
+            /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+            sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* <-MISRA 1.2 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT;
+            }
+            else
+            {
+                if (false == p_info_ch->enabled)
+                {
+                    ercd = EFAULT;
+                }
+            }
+            
+            if (ESUCCESS == ercd)
+            {
+#if defined (__ICCARM__)
+                was_masked = __disable_irq_iar();
+#else
+                was_masked = __disable_irq();
+#endif
+
+                if (ESUCCESS != p_info_ch->err_stat_backup)
+                {
+                    /* set error code */
+                    ercd = p_info_ch->err_stat_backup;
+                }
+                else
+                {
+                    switch (p_info_ch->ch_stat)
+                    {
+                        case SCUX_CH_UNINIT :
+                            /* fall through */
+                        case SCUX_CH_INIT :
+                            ercd = EFAULT;
+                        break;              
+                        
+                        case SCUX_CH_STOP :
+                            ercd = EBADF;
+                        break;                  
+                        
+                        case SCUX_CH_TRANS_IDLE :
+                            /* fall through */
+                        case SCUX_CH_TRANS_RD :
+                            if (SCUX_ROUTE_MEM_TO_MEM != (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                            {
+                                ercd = SCUX_DirectWriteStart(p_info_ch, p_aio);
+                            }
+                            else
+                            {
+                                ercd = SCUX_CopyWriteStart(p_info_ch, p_aio);
+                            }
+                        break;
+                        
+                        case SCUX_CH_TRANS_WR :
+                            /* fall through */
+                        case SCUX_CH_TRANS_RDWR :
+                            ahf_addtail(&p_info_ch->tx_que, p_aio);
+                        break;
+                        
+                        case SCUX_CH_STOP_WAIT :
+                            /* fall through */
+                        case SCUX_CH_STOP_WAIT_IDLE :
+                            ercd = EBADF;
+                        break;
+                        
+                        default :
+                            ercd = EFAULT;
+                        break;
+                    }
+                }
+                
+                if (0 == was_masked)
+                {
+                    __enable_irq();
+                } 
+            }
+            sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT;
+            }
+        }
+    }
+    
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+    }
+    SCUX_SetErrCode(ercd, p_errno);
+    
+    return retval;
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_WriteAsync
+******************************************************************************/
+/**************************************************************************//**
+* Function Name: R_SCUX_ReadAsync
+* @brief         SCUX driver asynchronous read.
+*
+*                Description:<br>
+*                
+* @param[in]     p_fd   :channel handle which was returned by R_SCUX_open
+* @param[in]     p_aio  :aio control block.
+* @param[in,out] p_errno:pointer of error code
+*                               error code -
+*                               EBADF : Channel status isn't SCUX_CH_STOP or SCUX_CH_STOP_WAIT. 
+*                               EINVAL : read size is 0.
+*                               EACCES : Request for write only mode channel.
+*                               EACCES : Route setting is unexpected.
+*                               EFAULT : Internal error is occured.
+*                               
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+#if(1) /* mbed */
+int_t R_SCUX_ReadAsync(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno)
+#else  /* not mbed */
+static int_t R_SCUX_ReadAsync(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno)
+#endif /* end mbed */
+{
+    int_t retval = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    osStatus sem_ercd;
+    int32_t sem_wait_ercd;
+    int_t was_masked;
+    scux_info_ch_t * const p_info_ch = p_fd;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_ch) || (NULL == p_info_drv) || (NULL == p_aio))
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (0U == p_aio->aio_nbytes)
+        {
+            ercd = EINVAL;
+        }
+        
+        if (ESUCCESS == ercd)
+        {
+            if (SCUX_DRV_INIT != p_info_drv->drv_stat)
+            {
+                ercd = EFAULT;
+            }
+        }
+        
+        if (ESUCCESS == ercd)
+        {
+            /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+            sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* <-MISRA 1.2 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT;
+            }
+            else
+            {
+                if (false == p_info_ch->enabled)
+                {
+                    ercd = EFAULT;
+                }
+            }
+            
+            if (ESUCCESS == ercd)
+            {
+                if (O_WRONLY == (p_info_ch->open_flags & O_ACCMODE))
+                {
+                    ercd = EACCES;
+                }
+            }
+            
+            if (ESUCCESS == ercd)
+            {
+                
+                if (SCUX_ROUTE_MEM_TO_MEM != (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                {
+                    ercd = EACCES;
+                }
+                
+                if (ESUCCESS == ercd)
+                {
+#if defined (__ICCARM__)
+                    was_masked = __disable_irq_iar();
+#else
+                    was_masked = __disable_irq();
+#endif
+
+                    if (ESUCCESS != p_info_ch->err_stat_backup)
+                    {
+                        /* set error code */
+                        ercd = p_info_ch->err_stat_backup;
+                    }
+                    else
+                    {
+                        switch (p_info_ch->ch_stat)
+                        {
+                            case SCUX_CH_UNINIT :
+                                /* fall through */
+                            case SCUX_CH_INIT :
+                                ercd = EFAULT;
+                            break;              
+                            
+                            case SCUX_CH_STOP :
+                                ercd = EBADF;
+                            break;                          
+                            
+                            case SCUX_CH_TRANS_IDLE :
+                                ercd = SCUX_CopyReadStart(p_info_ch, p_aio);
+                            break;
+                            
+                            case SCUX_CH_TRANS_RD :
+                                ahf_addtail(&p_info_ch->rx_que, p_aio);
+                            break;
+                            
+                            case SCUX_CH_TRANS_WR :
+                                ercd = SCUX_CopyReadStart(p_info_ch, p_aio);
+                            break;
+                            
+                            case SCUX_CH_TRANS_RDWR :
+                                /* fall through */
+                            case SCUX_CH_STOP_WAIT :
+                                ahf_addtail(&p_info_ch->rx_que, p_aio);
+                            break;
+                            
+                            case SCUX_CH_STOP_WAIT_IDLE :
+                                ercd = SCUX_CopyReadStart(p_info_ch, p_aio);
+                            break;                        
+                            
+                            default :
+                                ercd = EFAULT;
+                            break;
+                        }
+                    }                 
+                    
+                    if (0 == was_masked)
+                    {
+                        __enable_irq();
+                    }
+                }
+            }
+            sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT;
+            }
+        }
+    }
+    
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+    }
+    SCUX_SetErrCode(ercd, p_errno);
+    
+    return retval;
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_ReadAsync
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Cancel
+* @brief         Request cancel.
+*
+*                Description:<br>
+*                
+* @param[in]     p_fd   :channel handle which was returned by R_SCUX_open
+* @param[in]     p_aio  :aio control block.
+* @param[in,out] p_errno:pointer of error code
+*                               error code -
+*                               EFAULT : Internal error is occured.
+*                               
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+#if(1) /* mbed */
+int_t R_SCUX_Cancel(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno)
+#else  /* not mbed */
+static int_t R_SCUX_Cancel(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno)
+#endif /* end mbed */
+{
+    int_t retval = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    osStatus sem_ercd;
+    int32_t sem_wait_ercd;
+    scux_info_ch_t * const p_info_ch = p_fd;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_ch) || (NULL == p_info_drv))
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (SCUX_DRV_INIT != p_info_drv->drv_stat)
+        {
+            ercd = EFAULT;
+        }
+    
+        if (ESUCCESS == ercd)
+        {
+            /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+            sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* <-MISRA 1.2 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT;
+            }
+            
+            if (ESUCCESS == ercd)
+            {
+                if (false == p_info_ch->enabled)
+                {
+                    ercd = EFAULT;
+                }
+                
+                if (ESUCCESS == ercd)
+                {
+                    if ((SCUX_CH_INIT == p_info_ch->ch_stat) ||
+                        (SCUX_CH_UNINIT == p_info_ch->ch_stat))
+                    {
+                        /* It should not becomde status */
+                        ercd = EFAULT;
+                    }
+                    else if ((SCUX_CH_STOP_WAIT == p_info_ch->ch_stat) ||
+                              (SCUX_CH_STOP_WAIT_IDLE == p_info_ch->ch_stat) ||
+                              (SCUX_CH_STOP == p_info_ch->ch_stat))
+                    {
+                        /* busy error on flush waiting */
+                        ercd = EBADF;
+                    }
+                    else
+                    {
+                        if (NULL == p_aio)
+                        {
+                            if (SCUX_ROUTE_MEM_TO_MEM != (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                            {
+                                ercd = SCUX_DirectCancelAll(p_info_ch);
+                            }
+                            else
+                            {
+                                ercd = SCUX_CopyCancelAll(p_info_ch);   
+                            }
+                        }
+                        else
+                        {
+                            if (SCUX_ROUTE_MEM_TO_MEM != (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                            {
+                                ercd = SCUX_DirectCancelSpecific(p_info_ch, p_aio);
+                            }
+                            else
+                            {
+                                ercd = SCUX_CopyCancelSpecific(p_info_ch, p_aio);
+                            }
+                        }
+                    }
+                }
+            }
+            sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT;
+            }
+        }
+    }
+    
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+    }
+    SCUX_SetErrCode(ercd, p_errno);
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function R_SCUX_Cancel
+******************************************************************************/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_src/scux/scux_int.c	Fri Oct 02 03:03:25 2015 +0000
@@ -0,0 +1,887 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         scux_int.c
+* $Rev: 993 $
+* $Date:: 2014-07-22 09:54:45 +0900#$
+* @brief        SCUX Driver interrupt functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "scux.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+static void R_SCUX_Fdi0InterruptHandler(void);
+static void R_SCUX_Fdi1InterruptHandler(void);
+static void R_SCUX_Fdi2InterruptHandler(void);
+static void R_SCUX_Fdi3InterruptHandler(void);
+static void R_SCUX_FdiHandlerProcess(const scux_ch_num_t channel);
+
+static void R_SCUX_Fui0InterruptHandler(void);
+static void R_SCUX_Fui1InterruptHandler(void);
+static void R_SCUX_Fui2InterruptHandler(void);
+static void R_SCUX_Fui3InterruptHandler(void);
+static void R_SCUX_FuiHandlerProcess(const scux_ch_num_t channel);
+
+static void R_SCUX_Dvi0InterruptHandler(void);
+static void R_SCUX_Dvi1InterruptHandler(void);
+static void R_SCUX_Dvi2InterruptHandler(void);
+static void R_SCUX_Dvi3InterruptHandler(void);
+static void R_SCUX_DviHandlerProcess(const scux_ch_num_t channel);
+
+static void R_SCUX_Ai0InterruptHandler(void);
+static void R_SCUX_Ai1InterruptHandler(void);
+static void R_SCUX_AiHandlerProcess(const uint32_t src_channel);
+
+static void R_SCUX_ErrHandlerProcess(scux_info_ch_t * const p_scux_info_ch, const int_t ercd);
+
+/**************************************************************************//**
+* Function Name: SCUX_InterruptInit
+* @brief         Initialize SCUX interrupts.
+*
+*                Description:<br>
+*                
+* @param[in] channel : SCUX channel number.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_InterruptInit(const int_t channel)
+{
+    uint32_t int_type;
+    uint32_t ercd;
+    scux_info_ch_t * const p_scux_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    /* interrupt information table define */
+    static const scux_info_int_t scux_int_info[SCUX_CH_NUM][SCUX_INT_MAX] = 
+    {
+        {                                                                 /* ch0 */
+            {&R_SCUX_Fdi0InterruptHandler, SCUFDI0_IRQn, SCUX_INT_LEVEL}, /* FDI */
+            {&R_SCUX_Fui0InterruptHandler, SCUFUI0_IRQn, SCUX_INT_LEVEL}, /* FUI */
+            {&R_SCUX_Dvi0InterruptHandler, SCUDVI0_IRQn, SCUX_INT_LEVEL}, /* DVI */
+            {&R_SCUX_Ai0InterruptHandler,  SCUAI0_IRQn,  SCUX_INT_LEVEL}  /* AI */
+        },
+        {                                                                 /* ch1 */
+            {&R_SCUX_Fdi1InterruptHandler, SCUFDI1_IRQn, SCUX_INT_LEVEL}, /* FDI */
+            {&R_SCUX_Fui1InterruptHandler, SCUFUI1_IRQn, SCUX_INT_LEVEL}, /* FUI */
+            {&R_SCUX_Dvi1InterruptHandler, SCUDVI1_IRQn, SCUX_INT_LEVEL}, /* DVI */
+            {&R_SCUX_Ai0InterruptHandler,  SCUAI0_IRQn,  SCUX_INT_LEVEL}  /* AI */
+        },
+        {                                                                 /* ch2 */
+            {&R_SCUX_Fdi2InterruptHandler, SCUFDI2_IRQn, SCUX_INT_LEVEL}, /* FDI */
+            {&R_SCUX_Fui2InterruptHandler, SCUFUI2_IRQn, SCUX_INT_LEVEL}, /* FUI */
+            {&R_SCUX_Dvi2InterruptHandler, SCUDVI2_IRQn, SCUX_INT_LEVEL}, /* DVI */
+            {&R_SCUX_Ai1InterruptHandler,  SCUAI1_IRQn,  SCUX_INT_LEVEL}  /* AI */
+        },
+        {                                                                 /* ch3 */
+            {&R_SCUX_Fdi3InterruptHandler, SCUFDI3_IRQn, SCUX_INT_LEVEL}, /* FDI */
+            {&R_SCUX_Fui3InterruptHandler, SCUFUI3_IRQn, SCUX_INT_LEVEL}, /* FUI */
+            {&R_SCUX_Dvi3InterruptHandler, SCUDVI3_IRQn, SCUX_INT_LEVEL}, /* DVI */
+            {&R_SCUX_Ai1InterruptHandler,  SCUAI1_IRQn,  SCUX_INT_LEVEL}  /* AI */
+        }
+    };
+    
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        for (int_type = SCUX_INT_FDI; int_type < SCUX_INT_MAX; int_type++)
+        {
+            ercd = InterruptHandlerRegister(scux_int_info[channel][int_type].int_num,
+                                     scux_int_info[channel][int_type].int_handler
+                                     );
+                                     
+            if (0U != ercd)
+            {
+                /* NON_NOTICE_ASSERT: interrupt handler regist error */
+            }
+                                     
+            /* set interrupt level (1-N model) */
+            GIC_SetLevelModel(scux_int_info[channel][int_type].int_num, 
+                              (int8_t)scux_int_info[channel][int_type].info_level, 
+                              1
+                              );
+            
+            /* set interrupt priority */
+            GIC_SetPriority(scux_int_info[channel][int_type].int_num, p_scux_info_ch->int_level);
+            
+            /* get interrupt number */
+            p_scux_info_ch->int_num[int_type] = scux_int_info[channel][int_type].int_num;
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_InterrptInit
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_InterruptUntinit
+* @brief         Uninitialize SCUX interrupts.
+*
+*                Description:<br>
+*                
+* @param[in/out] channel : SCUX channel number.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_InterruptUninit(const int_t channel)
+{
+    uint32_t int_type;
+    uint32_t ercd;
+    scux_info_ch_t * const p_scux_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        for (int_type = SCUX_INT_FDI; int_type < SCUX_INT_MAX; int_type++)
+        {
+            GIC_DisableIRQ(p_scux_info_ch->int_num[int_type]);
+            ercd = InterruptHandlerUnregister(p_scux_info_ch->int_num[int_type]);
+            
+            if (0U != ercd)
+            {
+                /* NON_NOTICE_ASSERT: interrupt handler unregist error */
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_InterruptUnInit
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fdi0InterruptHandler
+* @brief         FDI interrupt handler on channel 0.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fdi0InterruptHandler(void)
+{
+    
+    R_SCUX_FdiHandlerProcess(SCUX_CH_0);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Fdi0InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fdi1InterruptHandler
+* @brief         FDI interrupt handler on channel 1.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fdi1InterruptHandler(void)
+{
+    
+    R_SCUX_FdiHandlerProcess(SCUX_CH_1);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Fdi1InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fdi2InterruptHandler
+* @brief         FDI interrupt handler on channel 2.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fdi2InterruptHandler(void)
+{
+    
+    R_SCUX_FdiHandlerProcess(SCUX_CH_2);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Fdi2InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fdi3InterruptHandler
+* @brief         FDI interrupt handler on channel 3.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fdi3InterruptHandler(void)
+{
+    
+    R_SCUX_FdiHandlerProcess(SCUX_CH_3);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Fdi3InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_FdiHandlerProcess
+* @brief         Processing FDI interrupt handler.
+*
+*                Description:<br>
+*                
+* @param[in] channel:SCUX channel number.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_FdiHandlerProcess(const scux_ch_num_t channel)
+{   
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo((int_t)channel);
+    int_t ercd;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* check error type */
+        if ((p_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 & DEVCR_FFD0_DEVCOL_MASK) != 0)
+        {
+            /* critical error (over lap) */
+            ercd = EIO;
+        }
+        else
+        {
+            /* be returned error (FFD under flow, over flow) */
+            ercd = EOVERFLOW;
+        }
+        
+        p_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 &= ~(DEVCR_FFD0_DEVCUF_SET | 
+                                                            DEVCR_FFD0_DEVCOF_SET | 
+                                                            DEVCR_FFD0_DEVCOL_SET | 
+                                                            DEVCR_FFD0_DEVCIUF_SET);
+                                                            
+        R_SCUX_ErrHandlerProcess(p_info_ch, ercd);
+    }
+
+}
+
+/******************************************************************************
+End of function R_SCUX_FdiHandlerProcess
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fui0InterruptHandler
+* @brief         FUI interrupt handler on channel 0.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fui0InterruptHandler(void)
+{
+    
+    R_SCUX_FuiHandlerProcess(SCUX_CH_0);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Fui0InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fui1InterruptHandler
+* @brief         FUI interrupt handler on channel 1.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fui1InterruptHandler(void)
+{
+    
+    R_SCUX_FuiHandlerProcess(SCUX_CH_1);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Fui1InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fui2InterruptHandler
+* @brief         FUI interrupt handler on channel 2.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fui2InterruptHandler(void)
+{
+    
+    R_SCUX_FuiHandlerProcess(SCUX_CH_2);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Fui2InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fui3InterruptHandler
+* @brief         FUI interrupt handler on channel 3.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fui3InterruptHandler(void)
+{
+    
+    R_SCUX_FuiHandlerProcess(SCUX_CH_3);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Fui3InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_FuiHandlerProcess
+* @brief         Processing FUI interrupt handler.
+*
+*                Description:<br>
+*                
+* @param[in] channel:SCUX channel number.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_FuiHandlerProcess(const scux_ch_num_t channel)
+{
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo((int_t)channel);
+    int_t ercd;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* check error type */
+        if ((p_info_ch->p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 & UEVCR_FFU0_UEVCOL_MASK) != 0)
+        {
+            /* critical error (over lap) */
+            ercd = EIO;
+        }
+        else
+        {
+            /* be returned error (FFU under flow, over flow) */
+            ercd = EOVERFLOW;
+        }
+        
+        p_info_ch->p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 &= ~(UEVCR_FFU0_UEVCUF_SET | 
+                                                            UEVCR_FFU0_UEVCOF_SET | 
+                                                            UEVCR_FFU0_UEVCOL_SET);
+                                                                
+        R_SCUX_ErrHandlerProcess(p_info_ch, ercd);
+
+    }
+
+}
+
+/******************************************************************************
+End of function R_SCUX_FuiHandlerProcess
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Dvi0InterruptHandler
+* @brief         DVI interrupt handler on channel 0.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Dvi0InterruptHandler(void)
+{
+    
+    R_SCUX_DviHandlerProcess(SCUX_CH_0);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Dvi0InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Dvi1InterruptHandler
+* @brief         DVI interrupt handler on channel 1.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Dvi1InterruptHandler(void)
+{
+    
+    R_SCUX_DviHandlerProcess(SCUX_CH_1);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Dvi1InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Dvi2InterruptHandler
+* @brief         DVI interrupt handler on channel 2.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Dvi2InterruptHandler(void)
+{
+    
+    R_SCUX_DviHandlerProcess(SCUX_CH_2);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Dvi2InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Dvi3InterruptHandler
+* @brief         DVI interrupt handler on channel 3.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Dvi3InterruptHandler(void)
+{
+    
+    R_SCUX_DviHandlerProcess(SCUX_CH_3);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Dvi3InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_DviHandlerProcess
+* @brief         Processing DVI interrupt handler.
+*
+*                Description:<br>
+*                
+* @param[in] channel:SCUX channel number.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_DviHandlerProcess(const scux_ch_num_t channel)
+{
+    uint32_t stat_zerocross;
+    int_t    ch_zerocross;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo((int_t)channel);
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        stat_zerocross = p_info_ch->p_scux_reg->p_dvu_reg->VEVCR_DVU0_0;
+        
+        for (ch_zerocross = 0; ch_zerocross <= p_info_ch->src_cfg.use_ch; ch_zerocross++)
+        {
+            /* check zerocross bit */
+            if (0U != (stat_zerocross & (VEVCR_DVU0_VEVCZCM_SET << ch_zerocross)))
+            {
+                p_info_ch->dvu_mute_stat |= (1U << ch_zerocross);
+                if (NULL != p_info_ch->dvu_cfg.dvu_zc_mute.pcallback[ch_zerocross])
+                {
+                    /* callback function */
+                    p_info_ch->dvu_cfg.dvu_zc_mute.pcallback[ch_zerocross]();
+                }
+            }
+            p_info_ch->p_scux_reg->p_dvu_reg->VEVCR_DVU0_0 &= ~stat_zerocross;
+        }
+    }
+
+}
+
+/******************************************************************************
+End of function R_SCUX_DviHandlerProcess
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Ai0InterruptHandler
+* @brief         AI interrupt handler on channel 0.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Ai0InterruptHandler(void)
+{
+    
+    R_SCUX_AiHandlerProcess(SRC_MOD_SRC0);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Ai0InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Ai1InterruptHandler
+* @brief         AI interrupt handler on channel 1.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Ai1InterruptHandler(void)
+{
+    
+    R_SCUX_AiHandlerProcess(SRC_MOD_SRC1);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Ai1InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_AiHandlerProcess
+* @brief         Processing AI interrupt handler.
+*
+*                Description:<br>
+*                
+* @param[in] channel:SCUX channel number.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_AiHandlerProcess(const uint32_t src_channel)
+{
+    scux_info_ch_t *p_info_ch_check;
+    scux_info_ch_t *p_info_ch;
+
+    if (SRC_MOD_SRC0 == src_channel)
+    {
+        p_info_ch_check = SCUX_GetDrvChInfo(SCUX_CH_0);
+        if (NULL == p_info_ch_check)
+        {
+            /* NON_NOTICE_ASSERT: NULL pointer */
+        }
+        else
+        {
+            if (0U != p_info_ch_check->p_scux_reg->p_src_reg->SEVCR0_2SRC0_0)
+            {
+                p_info_ch = SCUX_GetDrvChInfo(SCUX_CH_0);
+                if (NULL == p_info_ch)
+                {
+                    /* NON_NOTICE_ASSERT: NULL pointer */
+                }
+                else
+                {
+                    p_info_ch->p_scux_reg->p_src_reg->SEVCR0_2SRC0_0 &= ~(SEVCR_2SRC0_EVCUF_SET | 
+                                                                          SEVCR_2SRC0_EVCOF_SET);
+                    /* be returned error (FFU under flow, over flow) */
+                    R_SCUX_ErrHandlerProcess(p_info_ch, EOVERFLOW);
+                }
+            }
+            
+            if (0U != p_info_ch_check->p_scux_reg->p_src_reg->SEVCR1_2SRC0_0)
+            {
+                
+                p_info_ch = SCUX_GetDrvChInfo(SCUX_CH_1);
+                if (NULL == p_info_ch)
+                {
+                    /* NON_NOTICE_ASSERT: NULL pointer */
+                }
+                else
+                {
+                    p_info_ch->p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 &= ~(SEVCR_2SRC0_EVCUF_SET | 
+                                                                          SEVCR_2SRC0_EVCOF_SET);
+                    /* be returned error (FFU under flow, over flow) */                                                      
+                    R_SCUX_ErrHandlerProcess(p_info_ch, EOVERFLOW);
+                }
+            }
+        }
+    }
+    else
+    {
+        p_info_ch_check = SCUX_GetDrvChInfo(SCUX_CH_2);
+        if (NULL == p_info_ch_check)
+        {
+            /* NON_NOTICE_ASSERT: NULL pointer */
+        }
+        else
+        {
+            if (0U != p_info_ch_check->p_scux_reg->p_src_reg->SEVCR0_2SRC0_0)
+            {
+                p_info_ch = SCUX_GetDrvChInfo(SCUX_CH_2);
+                if (NULL == p_info_ch)
+                {
+                    /* NON_NOTICE_ASSERT: NULL pointer */
+                }
+                else
+                {
+                    p_info_ch->p_scux_reg->p_src_reg->SEVCR0_2SRC0_0 &= ~(SEVCR_2SRC0_EVCUF_SET | 
+                                                                          SEVCR_2SRC0_EVCOF_SET);
+                    /* be returned error (FFU under flow, over flow) */                                                       
+                    R_SCUX_ErrHandlerProcess(p_info_ch, EOVERFLOW);
+                }
+            }
+            
+            if (0U != p_info_ch_check->p_scux_reg->p_src_reg->SEVCR1_2SRC0_0)
+            {
+                
+                p_info_ch = SCUX_GetDrvChInfo(SCUX_CH_3);
+                if (NULL == p_info_ch)
+                {
+                    /* NON_NOTICE_ASSERT: NULL pointer */
+                }
+                else
+                {
+                    p_info_ch->p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 &= ~(SEVCR_2SRC0_EVCUF_SET | 
+                                                                          SEVCR_2SRC0_EVCOF_SET);
+                    /* be returned error (FFU under flow, over flow) */                                                       
+                    R_SCUX_ErrHandlerProcess(p_info_ch, EOVERFLOW);
+                }
+            }
+        }
+    }
+}
+
+/******************************************************************************
+End of function R_SCUX_AiHandlerProcess
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_ErrHandlerProcess
+* @brief         Error processing on interrupt handler.
+*
+*                Description:<br>
+*                
+* @param[in] p_scux_info_ch:SCUX channel information.
+* @param[in] ercd:return error code.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_ErrHandlerProcess(scux_info_ch_t * const p_scux_info_ch, const int_t ercd)
+{
+    int_t retval;
+    int_t dma_retval;
+    scux_stat_ch_t old_stat;
+    uint32_t tx_remain_size = 0;
+    uint32_t rx_remain_size = 0;
+
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        retval = R_DMA_Cancel(p_scux_info_ch->dma_tx_ch, &tx_remain_size, &dma_retval);
+        /* DMA stop check, (when dma_retval is EBADF, DMA stopped already) */
+        if ((ESUCCESS != retval) && (EBADF != dma_retval))
+        {
+            /* NON_NOTICE_ASSERT: NULL pointer */
+        }
+        else
+        {
+            p_scux_info_ch->tx_fifo_total_size += p_scux_info_ch->dma_tx_current_size;
+            p_scux_info_ch->dma_tx_current_size = 0;
+        }
+        
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            retval = R_DMA_Cancel(p_scux_info_ch->dma_rx_ch, &rx_remain_size, &dma_retval);
+
+            /* DMA stop check, (when dma_retval is EBADF, DMA stopped already) */
+            if ((ESUCCESS != retval) && (EBADF != dma_retval))
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+            else
+            {
+                p_scux_info_ch->rx_fifo_total_size += p_scux_info_ch->dma_rx_current_size;
+                p_scux_info_ch->dma_rx_current_size = 0;
+            }
+            
+            retval = R_DMA_Free(p_scux_info_ch->dma_rx_ch, NULL);
+            
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+        }
+        
+        SCUX_AdjustAccessFifo(p_scux_info_ch, tx_remain_size, rx_remain_size);
+        /* stop HW */
+        if (false != p_scux_info_ch->src_cfg.mode_sync)
+        {
+            SCUX_SyncStopHw(p_scux_info_ch);
+        }
+        else
+        {
+            SCUX_AsyncStopHw(p_scux_info_ch);
+        }
+
+        if (false == p_scux_info_ch->first_tx_flag)
+        {
+            /* return callback on normal operation */
+            if (NULL != p_scux_info_ch->p_tx_aio)
+            {
+                p_scux_info_ch->p_tx_aio->aio_return = ercd;
+                ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_aio);
+            }
+            if (NULL != p_scux_info_ch->p_tx_next_aio)
+            {
+                if (NULL == p_scux_info_ch->p_tx_aio)
+                {
+                    p_scux_info_ch->p_tx_next_aio->aio_return = ercd;
+                }
+                else
+                {
+                    p_scux_info_ch->p_tx_next_aio->aio_return = ECANCELED;
+                }
+                ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_next_aio);
+            }
+            ahf_cancelall(&p_scux_info_ch->tx_que);
+            p_scux_info_ch->p_tx_aio = NULL;
+            p_scux_info_ch->p_tx_next_aio = NULL;
+        }
+        else
+        {
+            /* return callback on first operation */
+            if (NULL != p_scux_info_ch->p_tx_next_aio)
+            {
+                p_scux_info_ch->p_tx_next_aio->aio_return = ercd;
+                ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_next_aio);
+            }
+            else
+            {
+                p_scux_info_ch->p_tx_aio->aio_return = ercd;
+                ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_aio);                
+            }
+            ahf_cancelall(&p_scux_info_ch->tx_que);
+            p_scux_info_ch->p_tx_aio = NULL;
+            p_scux_info_ch->p_tx_next_aio = NULL;
+        }
+        
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            /* if request is nothing, aio is NULL */
+            if (NULL != p_scux_info_ch->p_rx_aio)
+            {
+                p_scux_info_ch->p_rx_aio->aio_return = ercd;
+                ahf_complete(&p_scux_info_ch->rx_que, p_scux_info_ch->p_rx_aio);
+            }
+            ahf_cancelall(&p_scux_info_ch->rx_que);
+            p_scux_info_ch->p_rx_aio = NULL;
+        }
+        old_stat = p_scux_info_ch->ch_stat;
+        p_scux_info_ch->ch_stat = SCUX_CH_STOP;
+        if ((SCUX_CH_STOP_WAIT == old_stat) || (SCUX_CH_STOP_WAIT_IDLE == old_stat))
+        {
+            if (NULL != p_scux_info_ch->p_flush_callback)
+            {
+                p_scux_info_ch->p_flush_callback(ercd);
+            }
+        }
+        
+        /* set error status */
+        p_scux_info_ch->err_stat_backup = ercd;
+    }
+}
+
+/******************************************************************************
+End of function R_SCUX_ErrHandlerProcess
+******************************************************************************/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_src/scux/scux_int.h	Fri Oct 02 03:03:25 2015 +0000
@@ -0,0 +1,83 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          scux_int.h
+* $Rev: 891 $
+* $Date:: 2014-06-27 10:40:52 +0900#$
+* @brief         SCUX driver interrupt header
+******************************************************************************/
+
+#ifndef SCUX_INT_H
+#define SCUX_INT_H
+
+/******************************************************************************
+Includes <System Includes>, "Project Includes"
+******************************************************************************/
+
+#include "scux.h" 
+#include "Renesas_RZ_A1.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+/* Interrupt types */
+typedef enum
+{
+    SCUX_INT_FDI  = 0,   /* FDI interrupt */
+    SCUX_INT_FUI  = 1,   /* FUI interrupt */
+    SCUX_INT_DVI  = 2,   /* DVI interrupt */
+    SCUX_INT_AI   = 3,   /* AI interrupt */
+    SCUX_INT_MAX  = 4
+} scux_int_type_t;
+
+/* Interrupt level */
+typedef enum
+{
+    SCUX_INT_LEVEL = 0,   /* Level interrupt */
+    SCUX_INT_EDGE  = 1    /* Edge interrupt */
+} scux_int_leve_t;
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+/* Table Information of Interrupt */
+typedef struct
+{
+    IRQHandler       int_handler;          /* Interrupt handler */
+    IRQn_Type        int_num;              /* Interrupt number */
+    scux_int_leve_t  info_level;           /* Edge or level  */
+} scux_info_int_t;
+
+/***********************************************************************************
+ Function Prototypes
+***********************************************************************************/
+
+void SCUX_InterruptInit(const int_t channel);
+void SCUX_InterruptUninit(const int_t channel);
+
+#endif /* SCUX_INT_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_src/scux/scux_ioctl.c	Fri Oct 02 03:03:25 2015 +0000
@@ -0,0 +1,2583 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         scux_ioctl.c
+* $Rev: 1674 $
+* $Date:: 2015-05-29 16:35:57 +0900#$
+* @brief        SCUX Driver ioctl functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+
+#include "scux.h"
+#include "bsp_util.h"
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global driver management information
+******************************************************************************/
+
+/******************************************************************************
+ Function prototypes
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlTransStart
+* @brief         SCUX transfer start.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     p_scux_addr_param:address parameter.
+* @retval        ESUCCESS : Operation successful.
+*                EACCES : DVU setup isn't carried out when using DVU.
+*                EACCES : MIX setup isn't carried out when using MIX.
+*                EACCES : SSIF setup isn't carried out when using SSIF.
+*                EACCES : SSIF channel is already used.
+*                EACCES : When use MIX, it is a setup which does not agree in a route setup. 
+*                EBUSY : It has already transmitted.
+*                EMFILE : Allocate DMA ch for read is failed.
+*                EPERM : Transfer parameter is unexpected.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+#if(1) /* mbed */
+#if defined (__CC_ARM)
+#pragma O0
+#endif
+#endif /* end mbed */
+int_t SCUX_IoctlTransStart(const int_t channel)
+{
+    int32_t          sem_wait_ercd;
+    int_t            retval = ESUCCESS;
+    uint32_t         ssif_sem_ch = 0;
+    int_t            was_masked;
+    int_t            ssif_ch;
+    osStatus         sem_ercd;
+    scux_ssif_info_t * p_ssif_ch;
+    scux_ssif_info_t  * p_ssif_ch_num[SCUX_SSIF_CH_NUM];
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+
+    /* for processing for the measure against MISRA R1.1 and IPA R3.2.2 */
+    for (ssif_ch = 0; ssif_ch < SCUX_SSIF_CH_NUM; ssif_ch++)
+    {
+        p_ssif_ch_num[ssif_ch] = SCUX_GetSsifChInfo(ssif_ch);
+    }
+    if ((NULL == p_info_drv) || (NULL == p_info_ch)) 
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        /* check using MIX route */
+        if (SCUX_ROUTE_MIX == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+            sem_wait_ercd = osSemaphoreWait(p_info_drv->shared_info.sem_shared_access, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_ercd)
+            {
+                /* set semaphore error */
+                retval = EFAULT;
+            }
+        }
+
+        if ((SCUX_ROUTE_SSIF == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK)) || 
+            (SCUX_ROUTE_MIX == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK)))
+        {
+            /* check using SSIF route */
+            /* mode is async mode only when SSIF direvct route */
+            p_info_ch->src_cfg.mode_sync = false;
+            switch (p_info_ch->route_set)
+            {
+                case SCUX_ROUTE_SRC0_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC1_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC2_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC3_MEM :
+                    /* NOTREACHED on At the time of a normal performance */
+                break;              
+                
+                case SCUX_ROUTE_SRC0_SSIF0 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                break;
+                
+                case SCUX_ROUTE_SRC0_SSIF012 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                     
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_1);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_2);
+                    }
+                break;
+                
+                case SCUX_ROUTE_SRC0_SSIF3 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                break;
+                
+                case SCUX_ROUTE_SRC0_SSIF345 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                    
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_4);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_5);
+                    }
+                break;
+                
+                case SCUX_ROUTE_SRC1_SSIF0 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                break;              
+                
+                case SCUX_ROUTE_SRC1_SSIF012 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                     
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_1);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_2);
+                    }
+                break;              
+                
+                case SCUX_ROUTE_SRC1_SSIF3 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                break;              
+                
+                case SCUX_ROUTE_SRC1_SSIF345 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                    
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_4);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_5);
+                    }
+                break;
+                
+                case SCUX_ROUTE_SRC2_SSIF1 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_1);
+                    }
+                break;              
+                
+                case SCUX_ROUTE_SRC2_SSIF4 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_4);
+                    }
+                break;              
+                
+                case SCUX_ROUTE_SRC3_SSIF2 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_2);
+                    }
+                break;                
+                
+                case SCUX_ROUTE_SRC3_SSIF5 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_5);
+                    }
+                break;                
+
+                case SCUX_ROUTE_SRC0_MIX_SSIF0 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                break;
+
+                case SCUX_ROUTE_SRC0_MIX_SSIF012 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                     
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_1);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_2);
+                    }
+                break;
+
+                case SCUX_ROUTE_SRC0_MIX_SSIF3 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                break;
+
+                case SCUX_ROUTE_SRC0_MIX_SSIF345 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                    
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_4);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_5);
+                    }
+                break;
+
+                case SCUX_ROUTE_SRC1_MIX_SSIF0 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                break;
+                
+                case SCUX_ROUTE_SRC1_MIX_SSIF012 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                     
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_1);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_2);
+                    }
+                break;
+                
+                case SCUX_ROUTE_SRC1_MIX_SSIF3 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                break;
+                
+                case SCUX_ROUTE_SRC1_MIX_SSIF345 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                    
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_4);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_5);
+                    }
+                break;
+                
+                case SCUX_ROUTE_SRC2_MIX_SSIF0 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                break;              
+                
+                case SCUX_ROUTE_SRC2_MIX_SSIF012 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                     
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_1);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_2);
+                    }
+                break;              
+                
+                case SCUX_ROUTE_SRC2_MIX_SSIF3 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                break;
+                
+                case SCUX_ROUTE_SRC2_MIX_SSIF345 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                    
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_4);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_5);
+                    }
+                break;              
+                
+                case SCUX_ROUTE_SRC3_MIX_SSIF0 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                break;
+                
+                case SCUX_ROUTE_SRC3_MIX_SSIF012 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                     
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_1);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_2);
+                    }
+                break;                
+                
+                case SCUX_ROUTE_SRC3_MIX_SSIF3 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                break;
+    
+                case SCUX_ROUTE_SRC3_MIX_SSIF345 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                    
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_4);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_5);
+                    }
+                break;
+                        
+                default :
+                    /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                    /* <-IPA R3.5.2 */
+                    /* NOTREACHED on At the time of a normal performance */
+                break;
+            }
+        }
+
+        if (ESUCCESS == retval)
+        {
+            retval = SCUX_CheckParam(p_info_ch);
+                
+            if (ESUCCESS == retval)
+            {
+#if defined (__ICCARM__)
+                was_masked = __disable_irq_iar();
+#else
+                was_masked = __disable_irq();
+#endif    
+                SCUX_InitHw(p_info_ch);
+                if (SCUX_ROUTE_MEM_TO_MEM != (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                {
+                    SCUX_SetupSsif(p_info_ch);
+                }
+                
+                SCUX_SetupSrc(p_info_ch);
+                if (SCUX_ROUTE_MEM_TO_MEM != (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                {
+                    SCUX_SetupDvu(p_info_ch);
+                }
+                
+                retval = SCUX_SetupDma(p_info_ch);
+                
+                if (ESUCCESS == retval)
+                {
+                    if (false != p_info_ch->src_cfg.mode_sync)
+                    {
+                        SCUX_SyncStartHw(p_info_ch);
+                    }
+                    else
+                    {
+                        SCUX_AsyncStartHw(p_info_ch);
+                    }
+                    p_info_ch->ch_stat = SCUX_CH_TRANS_IDLE;
+                    p_info_ch->p_flush_callback = NULL;
+                    
+                    p_info_ch->dma_tx_current_size = 0;
+                    p_info_ch->dma_rx_current_size = 0;
+                    p_info_ch->tx_fifo_total_size = 0;
+                    p_info_ch->rx_fifo_total_size = 0;
+                    
+                    p_info_ch->p_tx_aio = NULL;
+                    p_info_ch->p_rx_aio = NULL;
+                    p_info_ch->p_tx_next_aio = NULL;
+                    p_info_ch->p_rx_next_aio = NULL;
+                    p_info_ch->dvu_mute_stat = 0;
+                    p_info_ch->first_ramp_flag = false;
+                    p_info_ch->cancel_operate_flag = false;
+                    p_info_ch->restart_ramp_flag = false;
+                    p_info_ch->err_stat_backup = ESUCCESS;
+                }
+                
+                if (0 == was_masked)
+                {
+                    __enable_irq();
+                }
+            }
+        }
+        
+        for (ssif_ch = 0; ssif_ch < SCUX_SSIF_CH_NUM; ssif_ch++)
+        {
+            if (0U != (ssif_sem_ch & (1U << ssif_ch)))
+            {
+                p_ssif_ch = p_ssif_ch_num[ssif_ch];
+                sem_ercd = osSemaphoreRelease(p_ssif_ch->sem_ch_scux_ssif_access);
+                /* semaphore error check */
+                if (osOK != sem_ercd)
+                {
+                    /* set semaphore error */
+                    retval = EFAULT;
+                    p_info_ch->ch_stat = SCUX_CH_STOP;
+                }
+            }
+        }
+        
+        /* check using MIX route */
+        if (SCUX_ROUTE_MIX == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            sem_ercd = osSemaphoreRelease(p_info_drv->shared_info.sem_shared_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set semaphore error */
+                retval = EFAULT;
+                p_info_ch->ch_stat = SCUX_CH_STOP;
+            }
+        }
+    }
+    
+    return retval;
+}
+#if(1) /* mbed */
+#if defined (__CC_ARM)
+#pragma O3
+#endif
+#endif /* end mbed */
+
+/******************************************************************************
+End of function SCUX_IoctlTransStart
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlFlushStop
+* @brief         Set flush stop paramter.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     (*callback)(void):callback function pointer.
+* @param[in]     was_masked:interrupt enable information.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlFlushStop(const int_t channel, void (* const callback)(int_t), const int_t was_masked) 
+{
+    int_t retval = ESUCCESS;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if (NULL == p_info_ch)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {  
+            /* mem to mem route */
+            if ((SCUX_CH_TRANS_IDLE == p_info_ch->ch_stat) || (SCUX_CH_TRANS_RD == p_info_ch->ch_stat))
+            {
+                /* Flush process is performed only when dummy buffer transmission has not been started yet */
+                if (false == p_info_ch->tx_dummy_run_flag)
+                {
+                    /* start flush write */
+                    retval = SCUX_FlushWriteStart(p_info_ch);
+                }
+                
+                if (ESUCCESS == retval)
+                {
+                    /* memory to memory route */
+                    if (SCUX_CH_TRANS_RD == p_info_ch->ch_stat)
+                    {
+                        p_info_ch->ch_stat = SCUX_CH_STOP_WAIT;
+                    }
+                    else
+                    {
+                        p_info_ch->ch_stat = SCUX_CH_STOP_WAIT_IDLE;
+                    }
+                    p_info_ch->p_flush_callback = callback;
+                }
+            }
+            else
+            {
+                /* on going write process */
+                /* status is SCUX_CH_TRANS_WR, SCUX_CH_TRANS_RDWR, SCUX_CH_STOP_WAIT, SCUX_CH_STOP_WAIT_IDLE */
+                if (SCUX_CH_TRANS_RDWR == p_info_ch->ch_stat)
+                {
+                    p_info_ch->ch_stat = SCUX_CH_STOP_WAIT;
+                }
+                if (SCUX_CH_TRANS_WR == p_info_ch->ch_stat)
+                {
+                    p_info_ch->ch_stat = SCUX_CH_STOP_WAIT_IDLE;
+                }
+                
+                p_info_ch->p_flush_callback = callback;
+            }
+        }
+        else
+        {
+            /* SSIF direct route */
+            if (SCUX_CH_TRANS_IDLE == p_info_ch->ch_stat)
+            {
+                /* Flush process is performed only when dummy buffer transmission has not been started yet */
+                if (false == p_info_ch->tx_dummy_run_flag)
+                {
+                    /* start flush write */
+                    retval = SCUX_FlushWriteStart(p_info_ch);
+                }
+                
+                if (ESUCCESS == retval)
+                {
+                    /* memory to memory route */
+                    p_info_ch->ch_stat = SCUX_CH_STOP_WAIT;
+                    p_info_ch->p_flush_callback = callback;
+                }
+            }
+            else
+            {
+                /* on going write process */
+                p_info_ch->ch_stat = SCUX_CH_STOP_WAIT;
+                p_info_ch->p_flush_callback = callback;
+                
+            }
+        }
+    }
+    
+    if (0 == was_masked)
+    {
+        /* enable all irq */
+        __enable_irq();
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlFlushStop
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlClearStop
+* @brief         Set flush stop paramter.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlClearStop(const int_t channel, const int_t was_masked) 
+{
+    int_t retval = ESUCCESS;
+    int_t dma_ercd;
+    int_t dma_retval;
+    scux_stat_ch_t old_stat;
+    uint32_t rx_remain_size = 0;
+    uint32_t tx_remain_size = 0;
+    
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    if (NULL == p_info_ch)
+    {
+        retval = EFAULT;
+        if (0 == was_masked)
+        {
+            /* enable all irq */
+            __enable_irq();
+        } 
+    }
+    else
+    {  
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        { 
+            /* memory to memory route */
+            dma_retval = R_DMA_Cancel(p_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd);
+            /* DMA stop check, (when dma_ercd is EBADF, DMA stopped already) */
+            if ((ESUCCESS != dma_retval) && (EBADF != dma_ercd))
+            {
+                retval = EFAULT;
+            }
+            else
+            {
+                p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+                p_info_ch->dma_tx_current_size = 0;
+            }
+             
+            dma_retval = R_DMA_Cancel(p_info_ch->dma_rx_ch, &rx_remain_size, &dma_ercd);
+            /* DMA stop check, (when dma_ercd is EBADF, DMA stopped already) */
+            if ((ESUCCESS != dma_retval) && (EBADF != dma_ercd))
+            {
+                retval = EFAULT;
+            }
+            else
+            {
+                p_info_ch->rx_fifo_total_size += p_info_ch->dma_rx_current_size;
+                p_info_ch->dma_rx_current_size = 0;
+                
+                dma_retval = R_DMA_Free(p_info_ch->dma_rx_ch, NULL);
+                if (ESUCCESS != dma_retval)
+                {
+                    retval = EFAULT;
+                }
+            }
+                        
+            if (ESUCCESS == retval)
+            {
+                /* return write request */
+                if (NULL !=  p_info_ch->p_tx_aio)
+                {
+                    p_info_ch->p_tx_aio->aio_return = (ssize_t)(p_info_ch->p_tx_aio->aio_nbytes - tx_remain_size);
+                    ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
+                }
+                
+                /* return read request */
+                if (NULL != p_info_ch->p_rx_aio)
+                {
+                    p_info_ch->p_rx_aio->aio_return = (ssize_t)(p_info_ch->p_rx_aio->aio_nbytes - rx_remain_size);
+                    ahf_complete(&p_info_ch->rx_que, p_info_ch->p_rx_aio);
+                }   
+                               
+                ahf_cancelall(&p_info_ch->tx_que);
+                ahf_cancelall(&p_info_ch->rx_que);
+                
+                p_info_ch->p_tx_aio = NULL;
+                p_info_ch->p_rx_aio = NULL;
+            }
+        }
+        else
+        {
+            /* SSIF direct route */
+            dma_retval = R_DMA_Cancel(p_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd);
+            /* DMA stop check, (when dma_ercd is EBADF, DMA stopped already) */
+            if ((ESUCCESS != dma_retval) && (EBADF != dma_ercd))
+            {
+                retval = EFAULT;
+            }
+            else
+            {
+                p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+                p_info_ch->dma_tx_current_size = 0;
+            }
+            
+            if (ESUCCESS == retval) 
+            {
+                /* return the request after 2nd */
+                if (false == p_info_ch->first_tx_flag)
+                {
+                    /* return current aio request */
+                    if (NULL !=  p_info_ch->p_tx_aio)
+                    {
+                        p_info_ch->p_tx_aio->aio_return = (ssize_t)(p_info_ch->p_tx_aio->aio_nbytes - tx_remain_size);
+                        ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
+                    }
+                    /* return next aio request */
+                    if (NULL != p_info_ch->p_tx_next_aio)
+                    {
+                        p_info_ch->p_tx_next_aio->aio_return = ECANCELED;
+                        ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_next_aio);
+                    }
+                }
+                else
+                {
+                    /* return the 1st request  */
+                    if (NULL == p_info_ch->p_tx_aio)
+                    {
+                        /* return the first half part of a 1st request */
+                        if (NULL != p_info_ch->p_tx_next_aio)
+                        {
+                            p_info_ch->p_tx_next_aio->aio_return 
+                            = (ssize_t)((p_info_ch->p_tx_next_aio->aio_nbytes / SCUX_HALF_SIZE_VALUE) - tx_remain_size);
+                            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_next_aio);
+                        }
+                    }
+                    else
+                    {
+                        /* return the second half part of a 1st request */
+                        p_info_ch->p_tx_aio->aio_return 
+                        = (ssize_t)(p_info_ch->p_tx_aio->aio_nbytes - tx_remain_size);
+                        ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
+                         
+                        /* in case of the next request is acquired */
+                        if (NULL != p_info_ch->p_tx_next_aio)
+                        {
+                            p_info_ch->p_tx_next_aio->aio_return = ECANCELED;
+                            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_next_aio);
+                        }
+                    }
+                }
+                ahf_cancelall(&p_info_ch->tx_que);
+                
+                p_info_ch->p_tx_aio = NULL;
+                p_info_ch->p_tx_next_aio = NULL;
+            }   
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            SCUX_AdjustAccessFifo(p_info_ch, tx_remain_size, rx_remain_size);
+            if (false != p_info_ch->src_cfg.mode_sync)
+            {
+                SCUX_SyncStopHw(p_info_ch);
+            }
+            else
+            {
+                SCUX_AsyncStopHw(p_info_ch);
+            }
+            
+            old_stat = p_info_ch->ch_stat;
+            p_info_ch->ch_stat = SCUX_CH_STOP;
+            
+            if (0 == was_masked)
+            {
+                /* enable all irq */
+                __enable_irq();
+            } 
+            
+            if ((SCUX_CH_STOP_WAIT == old_stat) || (SCUX_CH_STOP_WAIT_IDLE == old_stat))
+            {         
+                p_info_ch->p_flush_callback(ECANCELED);
+                p_info_ch->p_flush_callback = NULL;
+            }
+        }
+        else
+        {
+            if (0 == was_masked)
+            {
+                /* enable all irq */
+                __enable_irq();
+            } 
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlClearStop
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetRoute
+* @brief         Set SCUX data transfer route.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     route:route parameter.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlSetRoute(const int_t channel, const scux_route_t route) 
+{
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        p_info_ch->route_set = route;
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetRoute
+******************************************************************************/
+
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetPinClk
+* @brief         Set clock source for AUDIO_CLK pin.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_pin_clk_param:clock source parameter.
+* @retval        ESUCCESS:Operation successful.
+*                EPERM:Parameter is unexpected value.
+*                EFAULT:Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetPinClk(const int_t channel, const scux_ssif_pin_clk_t * const p_pin_clk_param) 
+{
+    int_t retval = ESUCCESS;
+    int32_t  sem_wait_ercd;
+    osStatus sem_ercd;
+    scux_ssif_info_t * p_ssif_ch;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if ((NULL == p_info_drv) || (NULL == p_info_ch) || (NULL == p_pin_clk_param))
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        /* check SSIF channel number */
+        if (SCUX_SSIF_CH_NUM > p_pin_clk_param->ssif_ch_num)
+        {
+            p_ssif_ch = SCUX_GetSsifChInfo((int_t)p_pin_clk_param->ssif_ch_num);
+            if (NULL == p_ssif_ch)
+            {
+                retval = EFAULT;
+            }
+            else
+            {
+                /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                /* <-MISRA 10.6 */
+                /* semaphore error check */
+                if ((-1) == sem_wait_ercd)
+                {
+                    /* set semaphore error */
+                    retval = EFAULT;
+                }
+                else
+                {
+                    /* check clock source parameter */
+                    if ((SCUX_CLK_AUDIO_CLK == p_pin_clk_param->pin_clk) || (SCUX_CLK_MLB_CLK == p_pin_clk_param->pin_clk))
+                    {
+                        p_ssif_ch->pin_clk = p_pin_clk_param->pin_clk;
+                    }
+                    else
+                    {
+                        retval = EPERM;
+                    }
+                }
+                sem_ercd = osSemaphoreRelease(p_ssif_ch->sem_ch_scux_ssif_access);
+                /* semaphore error check */
+                if (osOK != sem_ercd)
+                {
+                    /* set semaphore error */
+                    retval = EFAULT;
+                }
+                
+                if (ESUCCESS == retval)
+                {
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_info_drv->shared_info.sem_shared_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        if (SCUX_CLK_MLB_CLK == p_pin_clk_param->pin_clk)
+                        {
+                            /* set MLB_CLK */
+                            *(p_info_ch->p_scux_reg->ssipmd_cim) |= (SSIPMD_CIM_SSI0CKS_SET << p_pin_clk_param->ssif_ch_num);
+                        }
+                        else
+                        {
+                            /* set AUDIO_CLK */
+                            *(p_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI0CKS_SET << p_pin_clk_param->ssif_ch_num);
+                        }
+                    }
+                    
+                    sem_ercd = osSemaphoreRelease(p_info_drv->shared_info.sem_shared_access);
+                    /* semaphore error check */
+                    if (osOK != sem_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                }
+            }
+        }
+        else
+        {
+            retval = EPERM;
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetPinClk
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetPinMode
+* @brief         Set synchronous setting for each SSIP pin.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_pin_mode_param:synchronous setting parameter.
+* @retval        ESUCCESS:Operation successful.
+*                EPERM:Parameter is unexpected value.
+*                EFAUT:Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetPinMode(const int_t channel, const scux_ssif_pin_mode_t * const p_pin_mode_param) 
+{
+    int_t retval = ESUCCESS;
+    uint32_t ssipmd_reg;
+    uint32_t ssipmd_mask = 0;
+    uint32_t ssipmd_shift = 0;
+    osStatus sem_ercd;
+    int32_t  sem_wait_ercd;
+    scux_ssif_info_t * p_ssif_ch;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if ((NULL == p_info_drv) || (NULL == p_info_ch) || (NULL == p_pin_mode_param))
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        /* check SSIF channel number (disable setting for SSIF0) */
+        if (SCUX_SSIF_CH_NUM > p_pin_mode_param->ssif_ch_num)
+        {
+            p_ssif_ch = SCUX_GetSsifChInfo((int_t)p_pin_mode_param->ssif_ch_num);
+            if (NULL == p_ssif_ch)
+            {
+                retval = EFAULT;
+            }
+            else
+            {
+                /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                /* <-MISRA 10.6 */
+                /* semaphore error check */
+                if ((-1) == sem_wait_ercd)
+                {
+                    /* set semaphore error */
+                    retval = EFAULT;
+                }
+                else
+                {
+                    /* check clock source parameter */
+                    if ((SCUX_PIN_MODE_MIN < p_pin_mode_param->pin_mode) || (SCUX_PIN_MODE_MAX > p_pin_mode_param->pin_mode))
+                    {
+                        p_ssif_ch->pin_mode = p_pin_mode_param->pin_mode;
+                    }
+                    else
+                    {
+                        retval = EPERM;
+                    }
+                }
+                sem_ercd = osSemaphoreRelease(p_ssif_ch->sem_ch_scux_ssif_access);
+                /* semaphore error check */
+                if (osOK != sem_ercd)
+                {
+                    /* set semaphore error */
+                    retval = EFAULT;
+                }
+                
+                if (ESUCCESS == retval)
+                {
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_info_drv->shared_info.sem_shared_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        /* pin_mode setup to SSIF0 does not exist */
+                        if (SCUX_SSIF_CH_0 != p_pin_mode_param->ssif_ch_num)
+                        {
+                            switch (p_pin_mode_param->ssif_ch_num)
+                            {
+                                case SCUX_SSIF_CH_1 :
+                                    ssipmd_mask = SSIPMD_CIM_SSI1PMD_MASK;
+                                    ssipmd_shift = SSIPMD_CIM_SSI1PMD_SHIFT;
+                                break;
+                                
+                                case SCUX_SSIF_CH_2 :
+                                    ssipmd_mask = SSIPMD_CIM_SSI2PMD_MASK;
+                                    ssipmd_shift = SSIPMD_CIM_SSI2PMD_SHIFT;
+                                break;
+            
+                                case SCUX_SSIF_CH_3 :
+                                    ssipmd_mask = SSIPMD_CIM_SSI3PMD_MASK;
+                                    ssipmd_shift = SSIPMD_CIM_SSI3PMD_SHIFT;
+                                break;
+            
+                                case SCUX_SSIF_CH_4 :
+                                    ssipmd_mask = SSIPMD_CIM_SSI4PMD_MASK;
+                                    ssipmd_shift = SSIPMD_CIM_SSI4PMD_SHIFT;
+                                break;
+                                
+                                case SCUX_SSIF_CH_5 :
+                                    ssipmd_mask = SSIPMD_CIM_SSI5PMD_MASK;
+                                    ssipmd_shift = SSIPMD_CIM_SSI5PMD_SHIFT;
+                                break;                  
+                            
+                                default :
+                                    /* SCUX channel is 6 oe more */
+                                    retval = EPERM;
+                                break;
+                            }
+                        
+                            if (ESUCCESS == retval)
+                            {
+                                ssipmd_reg = *(p_info_ch->p_scux_reg->ssipmd_cim);
+                                ssipmd_reg &= ~ssipmd_mask;
+                            
+                                /* ->IPA R2.4.1 Even if pinmode and ssipmd_shift are max value, omission dose not occur. */
+                                *(p_info_ch->p_scux_reg->ssipmd_cim) = (ssipmd_reg | ((uint32_t)p_pin_mode_param->pin_mode << ssipmd_shift));
+                                /* <-IPA R2.4.1 */
+                            }
+                        }
+                    }
+                    
+                    sem_ercd = osSemaphoreRelease(p_info_drv->shared_info.sem_shared_access);
+                    /* semaphore error check */
+                    if (osOK != sem_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                }
+            }
+        }
+        else
+        {
+            retval = EPERM;
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetPinMode
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetSrcCfg
+* @brief         Set SRC paramter.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_src_param:SRC parameter.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlSetSrcCfg(const int_t channel, const scux_src_cfg_t * const p_src_param)
+{
+    scux_audio_channel_t audio_ch;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if ((NULL == p_info_ch) || (NULL == p_src_param))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        p_info_ch->src_cfg.src_enable = p_src_param->src_enable;
+        p_info_ch->src_cfg.use_ch = p_src_param->use_ch;
+        p_info_ch->src_cfg.word_len = p_src_param->word_len;
+        p_info_ch->src_cfg.mode_sync = p_src_param->mode_sync;
+        p_info_ch->src_cfg.input_rate_sync = p_src_param->input_rate_sync;
+        p_info_ch->src_cfg.input_clk_async = p_src_param->input_clk_async;
+        p_info_ch->src_cfg.input_div_async = p_src_param->input_div_async;
+        p_info_ch->src_cfg.output_rate_sync = p_src_param->output_rate_sync;
+        p_info_ch->src_cfg.output_clk_async = p_src_param->output_clk_async;
+        p_info_ch->src_cfg.output_div_async = p_src_param->output_div_async;
+        p_info_ch->src_cfg.delay_mode = p_src_param->delay_mode;
+        p_info_ch->src_cfg.wait_sample = p_src_param->wait_sample;
+        p_info_ch->src_cfg.min_rate_percentage = p_src_param->min_rate_percentage;
+        p_info_ch->src_cfg.output_ws = p_src_param->output_ws;
+        p_info_ch->src_cfg.input_ws = p_src_param->input_ws;
+        p_info_ch->src_cfg.freq_tioc3a = p_src_param->freq_tioc3a;
+        p_info_ch->src_cfg.freq_tioc4a = p_src_param->freq_tioc4a;
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_ch->src_cfg.select_in_data_ch[audio_ch] = p_src_param->select_in_data_ch[audio_ch];
+        }
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetSrcCfg
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetDvuCfg
+* @brief         Set DVU parameter.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_dvu_param:DVU parameter.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlSetDvuCfg(const int_t channel, const scux_dvu_cfg_t * const p_dvu_param)
+{
+    scux_audio_channel_t audio_ch;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if ((NULL == p_info_ch) || (NULL == p_dvu_param))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        p_info_ch->dvu_cfg.dvu_enable = p_dvu_param->dvu_enable;
+            
+        /* digital volume setting */
+        p_info_ch->dvu_cfg.dvu_digi_vol.digi_vol_enable = p_dvu_param->dvu_digi_vol.digi_vol_enable;
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch] = p_dvu_param->dvu_digi_vol.digi_vol[audio_ch];
+        }
+        
+        /* ramp volume setting */
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol_enable[audio_ch] = p_dvu_param->dvu_ramp_vol.ramp_vol_enable[audio_ch];
+        }
+        p_info_ch->dvu_cfg.dvu_ramp_vol.up_period = p_dvu_param->dvu_ramp_vol.up_period;
+        p_info_ch->dvu_cfg.dvu_ramp_vol.down_period = p_dvu_param->dvu_ramp_vol.down_period;
+        p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol = p_dvu_param->dvu_ramp_vol.ramp_vol;
+        p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_wait_time = p_dvu_param->dvu_ramp_vol.ramp_wait_time;
+        
+        /* zerocross mute setting */
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_ch->dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch] = p_dvu_param->dvu_zc_mute.zc_mute_enable[audio_ch];
+            p_info_ch->dvu_cfg.dvu_zc_mute.pcallback[audio_ch] = p_dvu_param->dvu_zc_mute.pcallback[audio_ch];
+        }
+        
+        p_info_ch->dvu_setup = true;
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetDvuCfg
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetDvuDigiVol
+* @brief         Set Digital volume parameter.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_dvu_param:Digital volume parameter.
+* @retval        ESUCCESS:Operation successful.
+*                EPERM:Parameter is unexpected value.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetDvuDigiVol(const int_t channel, const scux_dvu_digi_vol_t * const p_digi_vol_param)
+{
+    int_t retval = ESUCCESS;
+    int_t was_masked;
+    scux_audio_channel_t audio_ch;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if ((NULL == p_info_ch) || (NULL == p_digi_vol_param))
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        /* digital volume setting */
+        p_info_ch->dvu_cfg.dvu_digi_vol.digi_vol_enable = p_digi_vol_param->digi_vol_enable;
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch] = p_digi_vol_param->digi_vol[audio_ch];
+        }
+        
+        /* check digital volume */
+        for (audio_ch = SCUX_AUDIO_CH_0; ((ESUCCESS == retval) && (audio_ch < p_info_ch->src_cfg.use_ch)); audio_ch++)
+        {
+            if (SCUX_MAX_DIGITAL_VOLUME < p_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch])
+            {
+                retval = EPERM;
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+#if defined (__ICCARM__)
+            was_masked = __disable_irq_iar();
+#else
+            was_masked = __disable_irq();
+#endif
+
+            if (SCUX_CH_STOP != p_info_ch->ch_stat) 
+            {
+                p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 &= ~DVUER_DVU0_DVUEN_SET;
+                
+                /* set parameter for register */
+                SCUX_SetDigiVolRegister(p_info_ch);
+                    
+                p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET;
+            }   
+        
+            if (0 == was_masked)
+            {
+                __enable_irq();
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetDvuDigiVol
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetDvuRampVol
+* @brief         Set Digital volume parameter.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_dvu_param:Digital volume parameter.
+* @retval        ESUCCESS:Operation successful.
+*                EPERM:Parameter is unexpected value.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetDvuRampVol(const int_t channel, const scux_dvu_ramp_vol_t * const p_ramp_vol_param)
+{
+    int_t retval = ESUCCESS;
+    int_t was_masked;
+    scux_audio_channel_t audio_ch;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if ((NULL == p_info_ch) || (NULL == p_ramp_vol_param))
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        /* ramp volume setting */
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol_enable[audio_ch] = p_ramp_vol_param->ramp_vol_enable[audio_ch];
+        }
+        p_info_ch->dvu_cfg.dvu_ramp_vol.up_period = p_ramp_vol_param->up_period;
+        p_info_ch->dvu_cfg.dvu_ramp_vol.down_period = p_ramp_vol_param->down_period;
+        p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol = p_ramp_vol_param->ramp_vol;
+        p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_wait_time = p_ramp_vol_param->ramp_wait_time;
+        
+        /* check ramp volume */
+        /* check ramp down period */
+        if ((p_info_ch->dvu_cfg.dvu_ramp_vol.down_period <= SCUX_DVU_TIME_MIN) ||
+            (p_info_ch->dvu_cfg.dvu_ramp_vol.down_period >= SCUX_DVU_TIME_MAX))
+        {
+               retval = EPERM;
+        }
+                
+        if (ESUCCESS == retval)
+        {
+            /* check ramp up period */
+            if ((p_info_ch->dvu_cfg.dvu_ramp_vol.up_period <= SCUX_DVU_TIME_MIN) ||
+                (p_info_ch->dvu_cfg.dvu_ramp_vol.up_period >= SCUX_DVU_TIME_MAX))
+            {
+                retval = EPERM;
+            }
+        }
+                
+        if (ESUCCESS == retval)
+        {
+            /* check ramp volume */
+            if (SCUX_MAX_RAMP_VOLUME < p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol)
+            {
+                retval = EPERM;
+            }
+        }
+                
+        if (ESUCCESS != retval)
+        {
+            /* check wait time */
+            if (SCUX_MAX_WAIT_TIME < p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_wait_time)
+            {
+                retval = EPERM;
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+#if defined (__ICCARM__)
+            was_masked = __disable_irq_iar();
+#else
+            was_masked = __disable_irq();
+#endif
+
+            if ((SCUX_CH_STOP != p_info_ch->ch_stat) && (false != p_info_ch->first_ramp_flag))
+            {
+                p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 &= ~DVUER_DVU0_DVUEN_SET;
+                
+                /* set parameter for register */
+                SCUX_SetRampVolRegister(p_info_ch);
+                    
+                p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET;
+            }   
+            
+            /* an updating setting is used when a seting is updated before the first request is going */
+            p_info_ch->restart_ramp_flag = false;
+            
+            if (0 == was_masked)
+            {
+                __enable_irq();
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetDvuRampVol
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetDvuZerocrossMute
+* @brief         Set zerocross mute parameter.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_zc_mute_param:zerocross mute parameter.
+* @retval        ESUCCESS:Operation successful.
+*                EPERM:Parameter is unexpected value.
+*                EPERM:Rewrite callback pointer while waiting zerocross.
+******************************************************************************/
+
+int_t SCUX_IoctlSetDvuZerocrossMute(const int_t channel, const scux_zc_mute_t * const p_zc_mute_param)
+{
+    int_t retval = ESUCCESS;
+    int_t was_masked;
+    scux_audio_channel_t audio_ch;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if ((NULL == p_info_ch) || (NULL == p_zc_mute_param))
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        /* set zerocross mute paramter */
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_ch->dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch]= p_zc_mute_param->zc_mute_enable[audio_ch];
+            p_info_ch->dvu_cfg.dvu_zc_mute.pcallback[audio_ch] = p_zc_mute_param->pcallback[audio_ch];
+        }
+        
+#if defined (__ICCARM__)
+        was_masked = __disable_irq_iar();
+#else
+        was_masked = __disable_irq();
+#endif    
+
+        if (SCUX_CH_STOP != p_info_ch->ch_stat)
+        {
+            p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 &= ~DVUER_DVU0_DVUEN_SET;
+            
+            /* set parameter for register */
+            SCUX_SetZerocrossMuteRegister(p_info_ch);
+            
+            p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET;
+        }
+            
+        if (0 == was_masked)
+        {
+            __enable_irq();
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetDvuZerocrossMute
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetStopMute
+* @brief         Stop mute.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     audio_channel:Audio channel number.
+* @retval        ESUCCESS:Operation successful.
+*                EPERM:Parameter is unexpected value.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetStopMute(const int_t channel, const uint32_t audio_channel)
+{
+    int_t retval = ESUCCESS;
+    int_t was_masked;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if (NULL == p_info_ch)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        if (audio_channel >= (uint32_t)p_info_ch->src_cfg.use_ch)
+        {
+            retval = EPERM;
+        }
+        
+        if (ESUCCESS == retval)
+        {
+#if defined (__ICCARM__)
+            was_masked = __disable_irq_iar();
+#else
+            was_masked = __disable_irq();
+#endif
+
+            p_info_ch->dvu_mute_stat &= ~(1U << audio_channel);
+            p_info_ch->dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_channel] = false;
+            p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 &= ~DVUER_DVU0_DVUEN_SET;
+            p_info_ch->p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 &= ~(ZCMCR_DVU0_ZCEN_SET << audio_channel);
+            p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET;
+            
+            if (0 == was_masked)
+            {
+                __enable_irq();
+            }       
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetStopMute
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetMixCfg
+* @brief         Set MIX parameter.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_mix_param:MIX parameter.
+* @retval        ESUCCESS : Operation successful.
+*                EPERM : Transfer parameter is unexpected.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetMixCfg(const scux_mix_cfg_t * const p_mix_param)
+{
+    int_t retval = ESUCCESS;
+    int_t scux_ch;
+    int_t audio_ch;
+    int_t was_masked;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_drv) || (NULL == p_mix_param))
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+#if defined (__ICCARM__)
+        was_masked = __disable_irq_iar();
+#else
+        was_masked = __disable_irq();
+#endif
+
+        p_info_drv->shared_info.mixmode_ramp = p_mix_param->mixmode_ramp;
+        p_info_drv->shared_info.up_period = p_mix_param->up_period;
+        p_info_drv->shared_info.down_period = p_mix_param->down_period;
+        for (scux_ch = SCUX_CH_0; scux_ch < SCUX_CH_NUM; scux_ch++)
+        {
+            p_info_drv->shared_info.mix_vol[scux_ch] = p_mix_param->mix_vol[scux_ch];
+        }
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_drv->shared_info.select_out_data_ch[audio_ch] = p_mix_param->select_out_data_ch[audio_ch];
+        }
+            
+        for (scux_ch = SCUX_CH_0; ((ESUCCESS == retval) && (scux_ch < SCUX_CH_NUM)); scux_ch++)
+        {
+            /* check going channel number */
+            if (0U != (p_info_drv->shared_info.mix_run_ch & (1U << scux_ch)))
+            {
+                /* check ramp volume */
+                if (SCUX_MAX_RAMP_VOLUME < p_info_drv->shared_info.mix_vol[scux_ch])
+                {
+                    retval = EPERM;
+                }
+            }
+        }
+            
+        if (ESUCCESS == retval)
+        {
+            for (scux_ch = SCUX_CH_0; scux_ch < SCUX_CH_NUM; scux_ch++)
+            {
+                /* check going channel number */
+                if (0U != (p_info_drv->shared_info.mix_run_ch & (1U << scux_ch)))
+                {   
+                    /* set parameter for register */
+                    SCUX_SetMixVolRegister(scux_ch);
+                }
+            }
+            
+            p_info_drv->shared_info.mix_setup = true;
+        }
+        else
+        {
+            p_info_drv->shared_info.mix_setup = false;
+        }
+        
+        if (0 == was_masked)
+        {
+            __enable_irq();
+        }
+    }
+       
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetMixCfg
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetMixVol
+* @brief         Set MIX volume.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     mix_vol:MIX volume.
+* @retval        ESUCCESS : Operation successful.
+*                EPERM : Transfer parameter is unexpected.
+*                EFAULT: Internel error si occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetMixVol(const int_t channel, const uint32_t mix_vol)
+{
+    int_t retval = ESUCCESS;
+    int_t was_masked;
+    int32_t  sem_wait_ercd;
+    osStatus sem_ercd;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if (NULL == p_info_drv)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+        if (0 == R_ExceptionalMode())
+        {  
+            sem_wait_ercd = osSemaphoreWait(p_info_drv->shared_info.sem_shared_access, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_ercd)
+            {
+                /* set semaphore error */
+                retval = EFAULT;
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            p_info_drv->shared_info.mix_vol[channel] = mix_vol;
+            
+#if defined (__ICCARM__)
+            was_masked = __disable_irq_iar();
+#else
+            was_masked = __disable_irq();
+#endif
+
+            /* check going channel number */
+            if (0U != (p_info_drv->shared_info.mix_run_ch & (1U << channel)))
+            {
+                /* check ramp volume */
+                if (SCUX_MAX_RAMP_VOLUME < p_info_drv->shared_info.mix_vol[channel])
+                {
+                    retval = EPERM;
+                }
+                else
+                {               
+                    /* set parameter for register */
+                    SCUX_SetMixVolRegister(channel);
+                }
+            }
+            
+            if (0 == was_masked)
+            {
+                __enable_irq();
+            }
+        }
+        
+        if (0 == R_ExceptionalMode())
+        {  
+            sem_ercd = osSemaphoreRelease(p_info_drv->shared_info.sem_shared_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set semaphore error */
+                retval = EFAULT;
+            }
+        }
+    }
+        
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetMixVol
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetSsifCfg
+* @brief         Set SSIF parameter.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     p_ssif_param:SSIF parameter.
+* @retval        ESUCCESS : Operation successful.
+*                EBADF : SSIF channel has already used on other SCUX channel.
+*                EPERM : Transfer parameter is unexpected.
+*                EFAULT: Internel error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetSsifCfg(const scux_ssif_cfg_t * const p_ssif_param)
+{
+    int_t retval = ESUCCESS;
+    int32_t  sem_wait_ercd;
+    osStatus sem_ercd;
+    scux_ssif_info_t * p_ssif_ch;
+    
+    if (NULL == p_ssif_param)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        if (SCUX_SSIF_CH_NUM > p_ssif_param->ssif_ch_num)
+        {
+            p_ssif_ch = SCUX_GetSsifChInfo((int_t)p_ssif_param->ssif_ch_num);
+            if (NULL == p_ssif_ch)
+            {
+                retval = EFAULT;
+            }
+            else
+            {
+                /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                /* <-MISRA 10.6 */
+                /* semaphore error check */
+                if ((-1) == sem_wait_ercd)
+                {
+                    /* set semaphore error */
+                    retval = EFAULT;
+                }
+                else
+                {
+                    if (0 != p_ssif_ch->scux_channel)
+                    {
+                        retval = EBADF;
+                    }
+                    else
+                    {
+                        p_ssif_ch->ssif_cfg.ssif_ch_num = p_ssif_param->ssif_ch_num;
+                        p_ssif_ch->ssif_cfg.mode_master = p_ssif_param->mode_master;
+                        p_ssif_ch->ssif_cfg.select_audio_clk = p_ssif_param->select_audio_clk;
+                        p_ssif_ch->ssif_cfg.system_word = p_ssif_param->system_word;
+                        p_ssif_ch->ssif_cfg.sck_polarity_rise = p_ssif_param->sck_polarity_rise;
+                        p_ssif_ch->ssif_cfg.ws_polarity_high = p_ssif_param->ws_polarity_high;
+                        p_ssif_ch->ssif_cfg.padding_high = p_ssif_param->padding_high;
+                        p_ssif_ch->ssif_cfg.serial_data_align = p_ssif_param->serial_data_align;
+                        p_ssif_ch->ssif_cfg.ws_delay = p_ssif_param->ws_delay;
+                        p_ssif_ch->ssif_cfg.use_noise_cancel = p_ssif_param->use_noise_cancel;
+                        p_ssif_ch->ssif_cfg.use_tdm = p_ssif_param->use_tdm;
+                        p_ssif_ch->ssif_setup = true;
+                    }
+                }
+                
+                sem_ercd = osSemaphoreRelease(p_ssif_ch->sem_ch_scux_ssif_access);
+                /* semaphore error check */
+                if (osOK != sem_ercd)
+                {
+                    /* set semaphore error */
+                    retval = EFAULT;
+                }
+            }
+        }
+        else
+        {
+            retval = EPERM;
+        }
+    }
+            
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetMixVol
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlGetWriteStat
+* @brief         Get write request status.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_write_stat:Write request status.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlGetWriteStat(const int_t channel, uint32_t * const p_write_stat)
+{
+    int_t was_masked;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if ((NULL == p_info_ch) || (NULL == p_write_stat))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+#if defined (__ICCARM__)
+        was_masked = __disable_irq_iar();
+#else
+        was_masked = __disable_irq();
+#endif
+
+        if ((SCUX_CH_STOP == p_info_ch->ch_stat) || 
+            (SCUX_CH_STOP_WAIT == p_info_ch->ch_stat) || 
+            (SCUX_CH_STOP_WAIT_IDLE == p_info_ch->ch_stat))
+        {
+            *p_write_stat = SCUX_STAT_STOP;
+        }
+        else if ((SCUX_CH_TRANS_IDLE == p_info_ch->ch_stat) || (SCUX_CH_TRANS_RD == p_info_ch->ch_stat))
+        {
+            *p_write_stat = SCUX_STAT_IDLE;
+        }
+        else
+        {
+            *p_write_stat = SCUX_STAT_TRANS;
+        }
+        
+        if (0 == was_masked)
+        {
+            __enable_irq();
+        }
+    }
+        
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlGetWriteStat
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlGetReadStat
+* @brief         Get read request status.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_read_stat:Read request status.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlGetReadStat(const int_t channel, uint32_t * const p_read_stat)
+{
+    int_t was_masked;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+#if defined (__ICCARM__)
+    was_masked = __disable_irq_iar();
+#else
+    was_masked = __disable_irq();
+#endif
+
+    if ((NULL == p_info_ch) || (NULL == p_read_stat))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (SCUX_CH_STOP == p_info_ch->ch_stat)
+        {
+            *p_read_stat = SCUX_STAT_STOP;
+        }
+        else if ((SCUX_CH_TRANS_IDLE == p_info_ch->ch_stat) || 
+                 (SCUX_CH_TRANS_WR == p_info_ch->ch_stat) || 
+                 (SCUX_CH_STOP_WAIT_IDLE == p_info_ch->ch_stat))
+        {
+            *p_read_stat = SCUX_STAT_IDLE;
+        }
+        else
+        {
+            *p_read_stat = SCUX_STAT_TRANS;
+        }
+        
+        if (0 == was_masked)
+        {
+            __enable_irq();
+        }
+    }
+        
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlGetReadStat
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlGetDvuStat
+* @brief         Get DVU status.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_dvu_stat:DVU status.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlGetDvuStat(const int_t channel, uint32_t * const p_dvu_stat)
+{
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if ((NULL == p_info_ch) || (NULL == p_dvu_stat))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */   
+    }
+    else
+    {
+        *p_dvu_stat = (p_info_ch->p_scux_reg->p_dvu_reg->DVUSR_DVU0_0 & DVUSR_DVU0_VRSTS_MASK);
+    }
+        
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlGetDvuStat
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlGetMuteStat
+* @brief         Get MUTE status.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_mute_stat:MUTE status.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlGetMuteStat(const int_t channel, uint32_t * const p_mute_stat)
+{
+    int_t was_masked;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if ((NULL == p_info_ch) || (NULL == p_mute_stat))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+#if defined (__ICCARM__)
+        was_masked = __disable_irq_iar();
+#else
+        was_masked = __disable_irq();
+#endif
+
+        *p_mute_stat = p_info_ch->dvu_mute_stat;
+        
+        if (0 == was_masked)
+        {
+            __enable_irq();
+        }
+    }
+        
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlGetMuteStat
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlGetMixStat
+* @brief         Get MIX status.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_mix_stat:MIX status.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlGetMixStat(const int_t channel, uint32_t * const p_mix_stat)
+{
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if ((NULL == p_info_ch) || (NULL == p_mix_stat))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */   
+    }
+    else
+    {
+        *p_mix_stat = (*(p_info_ch->p_scux_reg->mixsr_mix0_0) & MIXSR_MIX0_MIXSTS_MASK);
+    }
+        
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlGetMixStat
+******************************************************************************/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_src/scux/scux_ver.c	Fri Oct 02 03:03:25 2015 +0000
@@ -0,0 +1,72 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         scux_ver.c
+* $Rev: 1645 $
+* $Date:: 2015-05-21 10:35:06 +0900#$
+* @brief        SCUX Driver get verion function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "cmsis_os.h"
+#include "scux_if.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* Ex. V2.12 -> MAJOR=2, MINOR=12 */
+#define SCUX_DRV_VER_MAJOR  (2u)
+#define SCUX_DRV_VER_MINOR  (2u)
+
+#define SCUX_DRV_VER_MASK   (0xFFu)
+#define SCUX_DRV_VER_SHIFT  (8u)
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_GetVersion
+* @brief         Get SCUX driver version.
+*
+*                Description:<br>
+*                
+* @param         none
+* @retval        driver version -
+*                    upper 8bit=MAJOR
+*                    lower 8bit=MINOR
+******************************************************************************/
+uint16_t R_SCUX_GetVersion(void)
+{
+    const uint16_t version =
+        ((SCUX_DRV_VER_MAJOR & SCUX_DRV_VER_MASK) << SCUX_DRV_VER_SHIFT)
+        | (SCUX_DRV_VER_MINOR & SCUX_DRV_VER_MASK);
+
+    return version;
+}
+/******************************************************************************
+End of function R_SCUX_GetVersion
+******************************************************************************/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api/R_BSP_Scux.h	Fri Oct 02 03:03:25 2015 +0000
@@ -0,0 +1,150 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          R_BSP_Scux.h
+* @brief         SCUX API
+******************************************************************************/
+
+#ifndef R_BSP_SCUX_H
+#define R_BSP_SCUX_H
+
+#include "R_BSP_SerialFamily.h"
+#include "R_BSP_ScuxDef.h"
+
+#define SAMPLING_RATE_8000HZ  (8000U)  /* Selects a sampling rate of 8 kHz. */
+#define SAMPLING_RATE_11025HZ (11025U) /* Selects a sampling rate of 11.025 kHz. */
+#define SAMPLING_RATE_12000HZ (12000U) /* Selects a sampling rate of 12 kHz. */
+#define SAMPLING_RATE_16000HZ (16000U) /* Selects a sampling rate of 16 kHz. */
+#define SAMPLING_RATE_22050HZ (22050U) /* Selects a sampling rate of 22.05 kHz. */
+#define SAMPLING_RATE_24000HZ (24000U) /* Selects a sampling rate of 24 kHz. */
+#define SAMPLING_RATE_32000HZ (32000U) /* Selects a sampling rate of 32 kHz. */
+#define SAMPLING_RATE_44100HZ (44100U) /* Selects a sampling rate of 44.1 kHz. */
+#define SAMPLING_RATE_48000HZ (48000U) /* Selects a sampling rate of 48 kHz. */
+#define SAMPLING_RATE_64000HZ (64000U) /* Selects a sampling rate of 64 kHz. */
+#define SAMPLING_RATE_88200HZ (88200U) /* Selects a sampling rate of 88.2 kHz. */
+#define SAMPLING_RATE_96000HZ (96000U) /* Selects a sampling rate of 96 kHz. */
+#define SELECT_IN_DATA_CH_0   (0U)     /* Specifies audio channel 0ch. */
+#define SELECT_IN_DATA_CH_1   (1U)     /* Specifies audio channel 1ch. */
+
+/** SRC parameter information */
+typedef struct
+{
+    bool                  src_enable;                       /**< SRC function enable setting */
+    scux_data_word_len_t  word_len;                         /**< Word length of the audio data to be used
+                                                                 by the SRC. */
+    bool                  mode_sync;                        /**< Synchronization mode */
+    uint32_t              input_rate;                       /**< Input sampling rate */
+    uint32_t              output_rate;                      /**< Output sampling rate */
+    uint32_t              select_in_data_ch[SCUX_USE_CH_2]; /**< For SRC's input data position swapping */
+} scux_src_usr_cfg_t;
+
+/** The SCUX module is made up of a sampling rate converter, a digital volume unit, and a mixer.
+ *  The SCUX driver can perform asynchronous and synchronous sampling rate conversions using the sampling rate
+ *  converter. 
+ *  The SCUX driver uses the DMA transfer mode to input and output audio data.
+ */
+class R_BSP_Scux : public R_BSP_SerialFamily {
+
+public:
+    /** Constructor: Initializes and opens the channel designated by the SCUX driver.
+     *
+     * @param channel SCUX channel number
+     * @param int_level Transfer interrupt priority level (0x00-0xF7; default = 0x80)
+     * @param max_write_num Maximum number of writes (1 to 128; default = 16)
+     * @param max_read_num Maximum number of reads (1 to 128; default = 16)
+     */
+    R_BSP_Scux(scux_ch_num_t channel, uint8_t int_level = 0x80, int32_t max_write_num = 16, int32_t max_read_num = 16);
+
+    /** Destructor: Closes the channel designated by the SCUX driver and exits.
+     *
+     */
+    virtual ~R_BSP_Scux(void);
+
+    /** Sets up the SCUX HW and starts operation, then starts accepting write/read requests.
+     * Allocates a DMA channel for read requests.
+     * The function also initializes the SCUX HW error state.
+     *
+     * @return Returns true if the function is successful. Returns false if the function fails.
+     */
+    bool TransStart(void);
+
+    /** Stops accepting write/read requests, flushes out all data in the SCUX that is requested for transfer,
+     *  then stops the HW operation.
+     *   If a transfer request is being processed, the function stops accepting write/read requests,
+     *   then performs preprocessing to stop the HW operation after flushing out all data in the SCUX
+     *   that is requested for transfer. 
+     *   If no transfer request is being processed, the function stops accepting write/read requests 
+     *   before stopping the HW operation.
+     * The function releases the DMA channel for read requests when the HW operation is stopped.
+     * It also calls the user-own callback function at the end of the transfer.
+     *
+     * @param callback Pointer to the callback function
+     *                 The SCUX driver places an error code indicating the execution result of FlushStop 
+     *                 in the argument of the callback function before calling the callback function. 
+     *                 The error code is set to 0 if FlushStop is successful. A negative number is set 
+     *                 if FlushStop fails.
+     * @return Returns true if the function is successful. Returns false if the function fails.
+     */
+    bool FlushStop(void (* const callback)(int32_t));
+
+    /** Discards all data in the SCUX that is requested for transfer before stopping the hardware operation
+     *  and stops accepting write/read requests. 
+     *  The function releases the DMA channel for read requests when the HW operation is stopped.
+     *
+     * @return Returns true if the function is successful. Returns false if the function fails.
+     */
+    bool ClearStop(void);
+
+    /** Sets up SRC parameters.
+     *
+     * @param p_src_param SRC parameter information
+     * @return Returns true if the function is successful. Returns false if the function fails.
+     */
+    bool SetSrcCfg(const scux_src_usr_cfg_t * const p_src_param);
+
+    /** Obtains the state information of the write request.
+     *
+     * @param p_write_stat Status of the write request
+     *        SCUX_STAT_STOP (0)  Acceptance of requests is stopped.
+     *        SCUX_STAT_IDLE (1)  Processing of all requests is completed and waiting for a request.
+     *        SCUX_STAT_TRANS(2)  Transfer in progress
+     * @return Returns true if the function is successful. Returns false if the function fails.
+     */
+    bool GetWriteStat(uint32_t * const p_write_stat);
+
+    /** Obtains the state information of the read request.
+     *
+     * @param p_read_stat ead request state
+     *        SCUX_STAT_STOP (0)  Acceptance of requests is stopped
+     *        SCUX_STAT_IDLE (1)  Processing of all requests is completed and waiting for a request.
+     *        SCUX_STAT_TRANS(2)  Transfer in progress
+     * @return Returns true if the function is successful. Returns false if the function fails.
+     */
+    bool GetReadStat(uint32_t * const p_read_stat);
+
+private:
+    void * instance;
+    void * ch_handle;
+    int32_t scux_ch;
+};
+#endif /* R_BSP_SCUX_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api/R_BSP_ScuxDef.h	Fri Oct 02 03:03:25 2015 +0000
@@ -0,0 +1,87 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          R_BSP_ScuxDef.h
+* @brief         SCUX defines
+******************************************************************************/
+
+#ifndef R_BSP_SCUXDEF_H
+#define R_BSP_SCUXDEF_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+/** SCUX channel number */
+typedef enum
+{
+    SCUX_CH_0 = 0,   /**< Specifies SCUX0. */
+    SCUX_CH_1 = 1,   /**< Specifies SCUX1. */
+    SCUX_CH_2 = 2,   /**< Specifies SCUX2. */
+    SCUX_CH_3 = 3,   /**< Specifies SCUX3. */
+    SCUX_CH_NUM = 4  /**< Number of SCUX channels. */
+} scux_ch_num_t;
+
+/** used audio channel number setting */
+typedef enum
+{
+    SCUX_USE_CH_1 = 1,   /**< used audio channel number is 1 */
+    SCUX_USE_CH_2 = 2,   /**< used audio channel number is 2 */
+    SCUX_USE_CH_4 = 4,   /**< used audio channel number is 4 */
+    SCUX_USE_CH_6 = 6,   /**< used audio channel number is 6 */
+    SCUX_USE_CH_8 = 8    /**< used audio channel number is 8 */
+} scux_use_channel_t;
+
+/** SCUX data word length */
+typedef enum
+{
+    SCUX_DATA_LEN_MIN      =(-1), /**< For data word length identification [unsettable] */
+    SCUX_DATA_LEN_24       = 0,   /**< Runs with a data word length of 24 bits. */
+    SCUX_DATA_LEN_16       = 1,   /**< Runs with a data word length of 16 bits. */
+    SCUX_DATA_LEN_16_TO_24 = 2,   /**< Outputs 16-bit data in 24-bit mode. */
+    SCUX_DATA_LEN_MAX      = 3    /**< For data word length identification [unsettable] */
+} scux_data_word_len_t;
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/** Status of the request */
+#define SCUX_STAT_STOP    0  /**< Acceptance of requests is stopped */
+#define SCUX_STAT_IDLE    1  /**< Processing of all requests is completed and waiting for a request. */
+#define SCUX_STAT_TRANS   2  /**< Transfer in progress */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* R_BSP_SCUXDEF_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/common/R_BSP_Scux.cpp	Fri Oct 02 03:03:25 2015 +0000
@@ -0,0 +1,454 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#include "r_bsp_cmn.h"
+#include "R_BSP_Scux.h"
+#include "scux_if.h"
+
+#define CH_ERR_NUM                  (-1)     /* Channel error number */
+#define INT_LEVEL_MAX               (0xF7)   /* The maximum value of the interrupt level */
+#define REQ_BUFF_NUM_MIN            (1)      /* The minimum value of the request buffer */
+#define REQ_BUFF_NUM_MAX            (128)    /* The maximum value of the request buffer */
+#define PATH_NAME_LENGTH            (3)      /* Path name length */
+#define PATH_TOP_PART               (0)      /* Path top part */
+#define CH_ID_PART                  (1)      /* Channel identifier part */
+#define TERM_CHAR_PART              (2)      /* Termination character part */
+#define PATH_SEPARATOR              ('\\')   /* Path separator */
+#define CHARACTER_0                 (0x30)   /* character 0 */
+#define INPUT_DIV_INIT_VALUE        (1000U)  /* The initial value of input divide ratio */
+#define OUTPUT_DIV_INIT_VALUE       (0U)     /* The initial value of output divide ratio  */
+#define INPUT_WS_INIT_VALUE         (1U)     /* The initial value of input WS frequency */
+#define OUTPUT_WS_INIT_VALUE        (96000U) /* The initial value of output WS frequency */
+#define FREQ_TIOC3A_INIT_VALUE      (1U)     /* The initial value of frequency of TIOC3 */
+#define FREQ_TIOC4A_INIT_VALUE      (1U)     /* The initial value of frequency of TIOC4 */
+#define WAIT_SAMPLE_INIT_VALUE      (0U)     /* The initial value of wait time */
+#define MIN_RATE_PER_INIT_VALUE     (98U)    /* The initial value of minimum rate */
+#define DIV_RATIO_CLK_AUDIO_22050HZ (1024U)  /* Divide ratio when the frequency is 22050Hz */
+#define DIV_RATIO_CLK_AUDIO_44100HZ (512U)   /* Divide ratio when the frequency is 44100Hz */
+#define DIV_RATIO_CLK_AUDIO_88200HZ (256U)   /* Divide ratio when the frequency is 88200Hz */
+#define DIV_RATIO_CLK_USB_24000HZ   (2000U)  /* Divide ratio when the frequency is 24000Hz */
+#define DIV_RATIO_CLK_USB_32000HZ   (1500U)  /* Divide ratio when the frequency is 36000Hz */
+#define DIV_RATIO_CLK_USB_48000HZ   (1000U)  /* Divide ratio when the frequency is 48000Hz */
+#define DIV_RATIO_CLK_USB_64000HZ   (750U)   /* Divide ratio when the frequency is 64000Hz */
+#define DIV_RATIO_CLK_USB_96000HZ   (500U)   /* Divide ratio when the frequency is 96000Hz */
+
+static bool set_src_init_cfg(scux_src_cfg_t * const src_cfg);
+
+R_BSP_Scux::R_BSP_Scux(scux_ch_num_t channel, uint8_t int_level, int32_t max_write_num, int32_t max_read_num) {
+    scux_channel_cfg_t scux_cfg;
+    int32_t result;
+    int32_t wk_errno;
+    bool    init_result;
+    char_t  path_name[PATH_NAME_LENGTH];
+
+    if (channel >= SCUX_CH_NUM) {
+        result = EERROR;
+    } else if (int_level > INT_LEVEL_MAX) {
+        result = EERROR;
+    } else if ((max_write_num < REQ_BUFF_NUM_MIN) || (max_write_num > REQ_BUFF_NUM_MAX)) {
+        result = EERROR;
+    } else if ((max_read_num < REQ_BUFF_NUM_MIN) || (max_read_num > REQ_BUFF_NUM_MAX)) {
+        result = EERROR;
+    } else {
+        result = R_BSP_CMN_Init();
+        if (result == ESUCCESS) {
+            scux_ch = (int32_t)channel;
+
+            scux_cfg.enabled       = true;
+            scux_cfg.int_level     = int_level;
+
+            switch (channel) {
+                case SCUX_CH_0:
+                    scux_cfg.route = SCUX_ROUTE_SRC0_MEM;
+                    break;
+                case SCUX_CH_1:
+                    scux_cfg.route = SCUX_ROUTE_SRC1_MEM;
+                    break;
+                case SCUX_CH_2:
+                    scux_cfg.route = SCUX_ROUTE_SRC2_MEM;
+                    break;
+                case SCUX_CH_3:
+                    scux_cfg.route = SCUX_ROUTE_SRC3_MEM;
+                    break;
+                default:
+                    /* NOTREACHED on At the time of a normal performance */
+                    scux_cfg.route = SCUX_ROUTE_SRC0_MEM;
+                    break;
+            }
+
+            init_result = set_src_init_cfg(&scux_cfg.src_cfg);
+            if (init_result == true) {
+                instance = R_SCUX_InitOne(scux_ch, &scux_cfg, &wk_errno);
+                if ((int32_t)instance != EERROR) {
+                    path_name[PATH_TOP_PART]  = PATH_SEPARATOR;
+                    path_name[CH_ID_PART]     = CHARACTER_0 + scux_ch;
+                    path_name[TERM_CHAR_PART] = '\0';
+
+                    ch_handle = (void *)R_SCUX_Open(instance, path_name, O_RDWR, 0, &wk_errno);
+                    if ((int32_t)ch_handle != EERROR) {
+                        write_init(ch_handle, (void *)&R_SCUX_WriteAsync, max_write_num);
+                        read_init(ch_handle, (void *)&R_SCUX_ReadAsync, max_read_num);
+                    } else {
+                        (void)R_SCUX_UnInitOne(scux_ch, instance, NULL);
+                        result = EERROR;
+                    }
+                } else {
+                    result = EERROR;
+                }
+            } else {
+                result = EERROR;
+            }
+        }
+    }
+
+    if (result != ESUCCESS) {
+        instance  = NULL;
+        ch_handle = NULL;
+        scux_ch   = CH_ERR_NUM;
+    }
+}
+
+R_BSP_Scux::~R_BSP_Scux(void) {
+    if (ch_handle != NULL) {
+        (void)R_SCUX_Close(ch_handle, NULL);
+    }
+
+    if ((scux_ch != CH_ERR_NUM) && (instance != NULL)) {
+        (void)R_SCUX_UnInitOne(scux_ch, instance, NULL);
+    }
+}
+
+bool R_BSP_Scux::TransStart(void) {
+    int32_t result;
+    bool    ret = true;
+
+    if (ch_handle == NULL) {
+        ret = false;
+    } else {
+        result = R_SCUX_Ioctl(ch_handle, SCUX_IOCTL_SET_START, NULL, NULL);
+        if (result != ESUCCESS) {
+            ret = false;
+        }
+    }
+
+    return ret;
+}
+
+bool R_BSP_Scux::FlushStop(void (* const callback)(int32_t)) {
+    int32_t result;
+    bool    ret = true;
+
+    if (ch_handle == NULL) {
+        ret = false;
+    } else if (callback == NULL) {
+        ret = false;
+    } else {
+        result = R_SCUX_Ioctl(ch_handle, SCUX_IOCTL_SET_FLUSH_STOP, (void *)callback, NULL);
+        if (result != ESUCCESS) {
+            ret = false;
+        }
+    }
+
+    return ret;
+}
+
+bool R_BSP_Scux::ClearStop(void) {
+    int32_t result;
+    bool    ret = true;
+
+    if (ch_handle == NULL) {
+        ret = false;
+    } else {
+        result = R_SCUX_Ioctl(ch_handle, SCUX_IOCTL_SET_CLEAR_STOP, NULL, NULL);
+        if (result != ESUCCESS) {
+            ret = false;
+        }
+    }
+
+    return ret;
+}
+
+bool R_BSP_Scux::SetSrcCfg(const scux_src_usr_cfg_t * const p_src_param) {
+    scux_src_cfg_t src_cfg;
+    int32_t result;
+    bool    init_result;
+    bool    ret = true;
+    int32_t i;
+
+    if (ch_handle == NULL) {
+        ret = false;
+    } else if (p_src_param == NULL) {
+        ret = false;
+    } else if ((p_src_param->mode_sync != false) && (p_src_param->src_enable == false)) {
+        ret = false;
+    } else {
+        init_result = set_src_init_cfg(&src_cfg);
+        if (init_result != true) {
+            ret = false;
+        } else {
+            src_cfg.src_enable = p_src_param->src_enable;
+            src_cfg.mode_sync  = p_src_param->mode_sync;
+
+            switch (p_src_param->word_len) {
+                case SCUX_DATA_LEN_24:
+                    /* fall through */
+                case SCUX_DATA_LEN_16:
+                    /* fall through */
+                case SCUX_DATA_LEN_16_TO_24:
+                    src_cfg.word_len = p_src_param->word_len;
+                    break;
+                default:
+                    ret = false;
+                    break;
+            }
+
+            if (ret == true) {
+                if (p_src_param->mode_sync != false) {
+                    switch (p_src_param->input_rate) {
+                        case SAMPLING_RATE_8000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_8;
+                            break;
+                        case SAMPLING_RATE_11025HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_11_025;
+                            break;
+                        case SAMPLING_RATE_12000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_12;
+                            break;
+                        case SAMPLING_RATE_16000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_16;
+                            break;
+                        case SAMPLING_RATE_22050HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_22_05;
+                            break;
+                        case SAMPLING_RATE_24000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_24;
+                            break;
+                        case SAMPLING_RATE_32000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_32;
+                            break;
+                        case SAMPLING_RATE_44100HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_44_1;
+                            break;
+                        case SAMPLING_RATE_48000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_48;
+                            break;
+                        case SAMPLING_RATE_64000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_64;
+                            break;
+                        case SAMPLING_RATE_88200HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_88_2;
+                            break;
+                        case SAMPLING_RATE_96000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_96;
+                            break;
+                        default:
+                            ret = false;
+                            break;
+                    }
+                } else {
+                    switch (p_src_param->input_rate) {
+                        case SAMPLING_RATE_22050HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_AUDIO_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_AUDIO_22050HZ;
+                            break;
+                        case SAMPLING_RATE_24000HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_USB_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_USB_24000HZ;
+                            break;
+                        case SAMPLING_RATE_32000HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_USB_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_USB_32000HZ;
+                            break;
+                        case SAMPLING_RATE_44100HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_AUDIO_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_AUDIO_44100HZ;
+                            break;
+                        case SAMPLING_RATE_48000HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_USB_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_USB_48000HZ;
+                            break;
+                        case SAMPLING_RATE_64000HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_USB_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_USB_64000HZ;
+                            break;
+                        case SAMPLING_RATE_88200HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_AUDIO_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_AUDIO_88200HZ;
+                            break;
+                        case SAMPLING_RATE_96000HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_USB_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_USB_96000HZ;
+                            break;
+                        default:
+                            ret = false;
+                            break;
+                    }
+                }
+            }
+
+            if (ret == true) {
+                if (p_src_param->mode_sync != false) {
+                    switch (p_src_param->output_rate) {
+                        case SAMPLING_RATE_44100HZ:
+                            src_cfg.output_rate_sync = SCUX_SYNC_RATE_44_1;
+                            break;
+                        case SAMPLING_RATE_48000HZ:
+                            src_cfg.output_rate_sync = SCUX_SYNC_RATE_48;
+                            break;
+                        case SAMPLING_RATE_96000HZ:
+                            src_cfg.output_rate_sync = SCUX_SYNC_RATE_96;
+                            break;
+                        default:
+                            ret = false;
+                            break;
+                    }
+                } else {
+                    switch (p_src_param->output_rate) {
+                        case SAMPLING_RATE_44100HZ:
+                            src_cfg.output_ws = SAMPLING_RATE_44100HZ;
+                            break;
+                        case SAMPLING_RATE_48000HZ:
+                            src_cfg.output_ws = SAMPLING_RATE_48000HZ;
+                            break;
+                        case SAMPLING_RATE_88200HZ:
+                            src_cfg.output_ws = SAMPLING_RATE_88200HZ;
+                            break;
+                        case SAMPLING_RATE_96000HZ:
+                            src_cfg.output_ws = SAMPLING_RATE_96000HZ;
+                            break;
+                        default:
+                            ret = false;
+                            break;
+                    }
+                }
+            }
+
+            if (ret == true) {
+                for (i = 0; i < SCUX_USE_CH_2; i++) {
+                    switch (p_src_param->select_in_data_ch[i]) {
+                        case SELECT_IN_DATA_CH_0:
+                            src_cfg.select_in_data_ch[i] = SCUX_AUDIO_CH_0;
+                            break;
+                        case SELECT_IN_DATA_CH_1:
+                            src_cfg.select_in_data_ch[i] = SCUX_AUDIO_CH_1;
+                            break;
+                        default:
+                            ret = false;
+                            break;
+                    }
+                }
+            }
+
+            if (ret == true) {
+                result = R_SCUX_Ioctl(ch_handle, SCUX_IOCTL_SET_SRC_CFG, (void *)&src_cfg, NULL);
+                if (result != ESUCCESS) {
+                    ret = false;
+                }
+            }
+        }
+    }
+
+    return ret;
+}
+
+bool R_BSP_Scux::GetWriteStat(uint32_t * const p_write_stat) {
+    int32_t result;
+    bool    ret = true;
+
+    if (ch_handle == NULL) {
+        ret = false;
+    } else if (p_write_stat == NULL) {
+        ret = false;
+    } else {
+        result = R_SCUX_Ioctl(ch_handle, SCUX_IOCTL_GET_WRITE_STAT, (void *)p_write_stat, NULL);
+        if (result != ESUCCESS) {
+            ret = false;
+        }
+    }
+
+    return ret;
+}
+
+bool R_BSP_Scux::GetReadStat(uint32_t * const p_read_stat) {
+    int32_t result;
+    bool    ret = true;
+
+    if (ch_handle == NULL) {
+        ret = false;
+    } else if (p_read_stat == NULL) {
+        ret = false;
+    } else {
+        result = R_SCUX_Ioctl(ch_handle, SCUX_IOCTL_GET_READ_STAT, (void *)p_read_stat, NULL);
+        if (result != ESUCCESS) {
+            ret = false;
+        }
+    }
+
+    return ret;
+}
+
+/**************************************************************************//**
+* Function Name: set_src_init_cfg
+* @brief         SRC configuration initialization.
+*
+*                Description:<br>
+*                
+* @param[in]     src_cfg SRC configuration. 
+* @retval        true  Setting success.
+*                false Setting fails.
+******************************************************************************/
+static bool set_src_init_cfg(scux_src_cfg_t * const src_cfg) {
+    bool ret = true;
+
+    if (src_cfg == NULL) {
+        ret = false;
+    } else {
+        src_cfg->src_enable                         = true;
+        src_cfg->use_ch                             = SCUX_USE_CH_2;
+        src_cfg->word_len                           = SCUX_DATA_LEN_16;
+        src_cfg->mode_sync                          = true;
+        src_cfg->input_rate_sync                    = SCUX_SYNC_RATE_48;
+        src_cfg->input_clk_async                    = SCUX_CLK_USB_X1;
+        src_cfg->input_div_async                    = INPUT_DIV_INIT_VALUE;
+        src_cfg->output_rate_sync                   = SCUX_SYNC_RATE_96;
+        src_cfg->output_clk_async                   = SCUX_CLK_SSIF0_WS;
+        src_cfg->output_div_async                   = OUTPUT_DIV_INIT_VALUE;
+        src_cfg->input_ws                           = INPUT_WS_INIT_VALUE;
+        src_cfg->output_ws                          = OUTPUT_WS_INIT_VALUE;
+        src_cfg->freq_tioc3a                        = FREQ_TIOC3A_INIT_VALUE;
+        src_cfg->freq_tioc4a                        = FREQ_TIOC4A_INIT_VALUE;
+        src_cfg->delay_mode                         = SCUX_DELAY_NORMAL;
+        src_cfg->wait_sample                        = WAIT_SAMPLE_INIT_VALUE;
+        src_cfg->min_rate_percentage                = MIN_RATE_PER_INIT_VALUE;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_0] = SCUX_AUDIO_CH_0;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_1] = SCUX_AUDIO_CH_1;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_2] = SCUX_AUDIO_CH_2;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_3] = SCUX_AUDIO_CH_3;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_4] = SCUX_AUDIO_CH_4;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_5] = SCUX_AUDIO_CH_5;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_6] = SCUX_AUDIO_CH_6;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_7] = SCUX_AUDIO_CH_7;
+    }
+
+    return ret;
+}