Revision 0:702bf7b2b7d8, committed 2015-06-01

Comitter:

dkato

Date:

Mon Jun 01 08:33:21 2015 +0000

Child:

1:c7469c0b50ac

Commit message:

first comit

Changed in this revision

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_inc/aioif.h	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,49 @@
+/******************************************************************************
+ *
+ * $Rev: 891 $
+ * $Date: 2012-12-14 19:28:37 +0900#$
+ *
+ * Description : ITRON support functions for IOIF Asynchronous I/O header file
+ *
+ * (C) Copyright RENESAS ELECTRONICS EUROPE Ltd 2012 All Rights Reserved
+ *****************************************************************************/
+
+#ifndef AIOIF_H
+#define AIOIF_H
+
+#include <ioif_aio.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct AHF_S
+{
+    struct aiocb *head;
+    struct aiocb *tail;
+    uint32_t flags;
+    osMutexId semid; /* Source Merge 08-81 */
+    osMutexDef_t* p_cmtx;
+    int32_t saved_int_mask;
+} AHF_S;
+
+#define AHF_CREATESEM   0x1 /* create a semaphore for locking */ /* Source Merge 08-82 */
+#define AHF_LOCKSEM     0x2 /* use a semaphore for locking */    /* Source Merge 08-82 */
+#define AHF_LOCKINT     0x4 /* use interrupts for locking */
+
+/* AHF (Asynchronous Helper Functions */
+int32_t ahf_create (AHF_S * const ahf, const uint32_t f); /* Source Merge 08-83 */
+void ahf_destroy (AHF_S const * const ahf);
+void ahf_addtail (AHF_S * const ahf, struct aiocb * const aio); /* Source Merge 08-04 */
+struct aiocb *ahf_removehead (AHF_S * const ahf);
+int32_t ahf_remove (AHF_S *ahf, struct aiocb *aio);
+struct aiocb *ahf_peekhead (AHF_S * const ahf);
+void ahf_cancelall (AHF_S * const ahf);
+void ahf_complete (AHF_S *ahf, struct aiocb * const aio);
+int32_t ahf_cancel (AHF_S * const ahf, struct aiocb * const aio);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_inc/bsp_drv_cmn.h	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,41 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          bsp_drv_cmn.h
+* $Rev: 891 $
+* $Date:: 2014-06-27 10:40:52 +0900#$
+* @brief         BSP Section settings
+******************************************************************************/
+
+#ifndef BSP_DRV_CMN_H
+#define BSP_DRV_CMN_H
+
+#if(1) /* mbed */
+#else
+#pragma arm section code="CODE_RDRV"
+#pragma arm section rodata="CONST_RDRV"
+#pragma arm section rwdata="DATA_RDRV"
+#pragma arm section zidata="BSS_RDRV"
+#endif
+
+#endif /* BSP_DRV_CMN_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_inc/bsp_util.h	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,71 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          bsp_util.h
+* $Rev: 891 $
+* $Date:: 2014-06-27 10:40:52 +0900#$
+* @brief         BSP Utilities
+******************************************************************************/
+
+#ifndef BSP_UTIL_H
+#define BSP_UTIL_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+/* ->MISRA 20.9,This header is no problem because it's based upon the standard of the ANSI. */
+#include <stdio.h>
+/* <-MISRA 20.9 */
+#include "bsp_util.h"
+#include "r_typedefs.h"
+#include "iodefine.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+int32_t R_ExceptionalMode(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _BSP_UTIL_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_inc/dma_if.h	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,397 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         dma_if.h
+* $Rev: 1318 $
+* $Date:: 2014-12-04 10:45:12 +0900#$
+* @brief        DMA Driver interface headers
+******************************************************************************/
+
+/*****************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 15.01.2013 1.00 First Release
+******************************************************************************/
+
+#ifndef DMA_IF_H
+#define DMA_IF_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+
+#include "cmsis_os.h"
+#include "r_errno.h"
+#include "r_typedefs.h"
+#include "ioif_aio.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+/*************************************************************************
+ User Includes
+*************************************************************************/
+
+/*************************************************************************
+ Defines
+*************************************************************************/
+
+/* for searching free channel */
+#define DMA_ALLOC_CH  (-1)
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+/* Number od DMA channel */
+typedef enum
+{
+    DMA_CH_0 = 0,
+    DMA_CH_1 = 1,
+    DMA_CH_2 = 2,
+    DMA_CH_3 = 3,
+    DMA_CH_4 = 4,
+    DMA_CH_5 = 5,
+    DMA_CH_6 = 6,
+    DMA_CH_7 = 7,
+    DMA_CH_8 = 8,
+    DMA_CH_9 = 9,
+    DMA_CH_10 = 10,
+    DMA_CH_11 = 11,
+    DMA_CH_12 = 12,
+    DMA_CH_13 = 13,
+    DMA_CH_14 = 14,
+    DMA_CH_15 = 15,
+    DMA_CH_NUM = 16  /* Number of DMA channel */
+} dma_ch_num_t;
+
+/* Unit Size of DMA transfer */
+typedef enum
+{
+    DMA_UNIT_MIN =(-1),
+    DMA_UNIT_1 = 0,   /* Unit Size of DMA transfer = 1byte */
+    DMA_UNIT_2 = 1,   /* Unit Size of DMA transfer = 2byte */
+    DMA_UNIT_4 = 2,   /* Unit Size of DMA transfer = 4byte */
+    DMA_UNIT_8 = 3,   /* Unit Size of DMA transfer = 8byte */
+    DMA_UNIT_16 = 4,  /* Unit Size of DMA transfer = 16byte */
+    DMA_UNIT_32 = 5,  /* Unit Size of DMA transfer = 32byte */
+    DMA_UNIT_64 = 6,  /* Unit Size of DMA transfer = 64byte */
+    DMA_UNIT_128 = 7, /* Unit Size of DMA transfer = 128byte */
+    DMA_UNIT_MAX = 8
+} dma_unit_size_t;
+
+/* DMA transfer resource */
+typedef enum
+{
+    DMA_RS_OSTIM0     = 0x023,   /* OS Timer ch0 */
+    DMA_RS_OSTIM1     = 0x027,   /* OS Timer ch1 */
+    DMA_RS_TGI0A      = 0x043,   /* Multi Function Timer Pulse Unit2 ch0 */
+    DMA_RS_TGI1A      = 0x047,   /* Multi Function Timer Pulse Unit2 ch1  */
+    DMA_RS_TGI2A      = 0x04B,   /* Multi Function Timer Pulse Unit2 ch2  */
+    DMA_RS_TGI3A      = 0x04F,   /* Multi Function Timer Pulse Unit2 ch3  */
+    DMA_RS_TGI4A      = 0x053,   /* Multi Function Timer Pulse Unit2 ch4  */
+    DMA_RS_TXI0       = 0x061,   /* FIFO Serial Communication Interface ch0 (TX) */
+    DMA_RS_RXI0       = 0x062,   /* FIFO Serial Communication Interface ch0 (RX) */
+    DMA_RS_TXI1       = 0x065,   /* FIFO Serial Communication Interface ch1 (TX) */
+    DMA_RS_RXI1       = 0x066,   /* FIFO Serial Communication Interface ch1 (RX) */
+    DMA_RS_TXI2       = 0x069,   /* FIFO Serial Communication Interface ch2 (TX) */
+    DMA_RS_RXI2       = 0x06A,   /* FIFO Serial Communication Interface ch2 (RX) */
+    DMA_RS_TXI3       = 0x06D,   /* FIFO Serial Communication Interface ch3 (TX) */
+    DMA_RS_RXI3       = 0x06E,   /* FIFO Serial Communication Interface ch3 (RX) */
+    DMA_RS_TXI4       = 0x071,   /* FIFO Serial Communication Interface ch4 (TX) */
+    DMA_RS_RXI4       = 0x072,   /* FIFO Serial Communication Interface ch4 (RX) */
+    DMA_RS_TXI5       = 0x075,   /* FIFO Serial Communication Interface ch5 (TX) */
+    DMA_RS_RXI5       = 0x076,   /* FIFO Serial Communication Interface ch5 (RX) */
+    DMA_RS_TXI6       = 0x079,   /* FIFO Serial Communication Interface ch6 (TX) */
+    DMA_RS_RXI6       = 0x07A,   /* FIFO Serial Communication Interface ch6 (RX) */
+    DMA_RS_TXI7       = 0x07D,   /* FIFO Serial Communication Interface ch7 (TX) */
+    DMA_RS_RXI7       = 0x07E,   /* FIFO Serial Communication Interface ch7 (RX) */
+    DMA_RS_USB0_DMA0  = 0x083,   /* USB Module0 ch0 */
+    DMA_RS_USB0_DMA1  = 0x087,   /* USB Module0 ch1 */
+    DMA_RS_USB1_DMA0  = 0x08B,   /* USB Module1 ch0 */
+    DMA_RS_USB1_DMA1  = 0x08F,   /* USB Module1 ch1 */
+    DMA_RS_ADEND      = 0x093,   /* A/D Converter */
+    DMA_RS_IEBBTD     = 0x0A3,   /* IEBus Controller (Data interrupt) */
+    DMA_RS_IEBBTV     = 0x0A7,   /* IEBus Controller (Vector interrupt) */
+    DMA_RS_IREADY     = 0x0AB,   /* CD-Rom Decoder */
+    DMA_RS_FLDT       = 0x0B3,   /* NAND Memory Controller (Data) */
+    DMA_RS_SDHI_0T    = 0x0C1,   /* SD Host Interface0 (TX) */
+    DMA_RS_SDHI_0R    = 0x0C2,   /* SD Host Interface0 (RX) */
+    DMA_RS_SDHI_1T    = 0x0C5,   /* SD Host Interface1 (RX) */
+    DMA_RS_SDHI_1R    = 0x0C6,   /* SD Host Interface1 (TX) */
+    DMA_RS_MMCT       = 0x0C9,   /* MMC Host Interface (TX) */
+    DMA_RS_MMCR       = 0x0CA,   /* MMC Host Interface (RX) */
+    DMA_RS_SSITXI0    = 0x0E1,   /* SSIF0 (TX) */
+    DMA_RS_SSIRXI0    = 0x0E2,   /* SSIF0 (RX) */
+    DMA_RS_SSITXI1    = 0x0E5,   /* SSIF1 (TX) */
+    DMA_RS_SSIRXI1    = 0x0E6,   /* SSIF1 (RX) */
+    DMA_RS_SSIRTI2    = 0x0EB,   /* SSIF2 (TX) */
+    DMA_RS_SSITXI3    = 0x0ED,   /* SSIF2 (RTX) */
+    DMA_RS_SSIRXI3    = 0x0EE,   /* SSIF3 (TX) */
+    DMA_RS_SSIRTI4    = 0x0F3,   /* SSIF4 (RTX) */
+    DMA_RS_SSITXI5    = 0x0F5,   /* SSIF5 (TX) */
+    DMA_RS_SSIRXI5    = 0x0F6,   /* SSIF5 (RX) */
+    DMA_RS_SCUTXI0    = 0x101,   /* SCUX (FFD0) */
+    DMA_RS_SCURXI0    = 0x102,   /* SCUX (FFU0) */
+    DMA_RS_SCUTXI1    = 0x105,   /* SCUX (FFD1) */
+    DMA_RS_SCURXI1    = 0x106,   /* SCUX (FFU1) */
+    DMA_RS_SCUTXI2    = 0x109,   /* SCUX (FFD2) */
+    DMA_RS_SCURXI2    = 0x10A,   /* SCUX (FFU2) */
+    DMA_RS_SCUTXI3    = 0x10D,   /* SCUX (FFD3) */
+    DMA_RS_SCURXI3    = 0x10E,   /* SCUX (FFU3) */
+    DMA_RS_SPTI0      = 0x121,   /* SPI0 (TX) */
+    DMA_RS_SPRI0      = 0x122,   /* SPI0 (RX) */
+    DMA_RS_SPTI1      = 0x125,   /* SPI1 (TX) */
+    DMA_RS_SPRI1      = 0x126,   /* SPI1 (RX) */
+    DMA_RS_SPTI2      = 0x129,   /* SPI2 (TX) */
+    DMA_RS_SPRI2      = 0x12A,   /* SPI2 (RX) */
+    DMA_RS_SPTI3      = 0x12B,   /* SPI3 (TX) */
+    DMA_RS_SPRI3      = 0x12E,   /* SPI3 (RX) */
+    DMA_RS_SPTI4      = 0x131,   /* SPI4 (TX) */
+    DMA_RS_SPRI4      = 0x132,   /* SPI4 (RX) */
+    DMA_RS_SPDIFTXI   = 0x141,   /* SPDIF (TX) */
+    DMA_RS_SPDIFRXI   = 0x142,   /* SPDIF (RX) */
+    DMA_RS_CMI1       = 0x147,   /* Motor Control PWM Timer ch1 */
+    DMA_RS_CMI2       = 0x14B,   /* Motor Control PWM Timer ch2 */
+    DMA_RS_MLBCI      = 0x14F,   /* Media Local Bus */
+    DMA_RS_SGDEI0     = 0x153,   /* Sound Generator0 */
+    DMA_RS_SGDEI1     = 0x157,   /* Sound Generator1 */
+    DMA_RS_SGDEI2     = 0x15B,   /* Sound Generator2 */
+    DMA_RS_SGDEI3     = 0x15F,   /* Sound Generator3 */
+    DMA_RS_SCITXI0    = 0x169,   /* Serial Communication Interface ch0 (TX) */
+    DMA_RS_SCIRXI0    = 0x16A,   /* Serial Communication Interface ch0 (RX) */
+    DMA_RS_SCITXI1    = 0x16D,   /* Serial Communication Interface ch1 (TX) */
+    DMA_RS_SCIRXI1    = 0x16E,   /* Serial Communication Interface ch1 (RX) */
+    DMA_RS_TI0        = 0x181,   /* IIC ch0 (TX) */
+    DMA_RS_RI0        = 0x182,   /* IIC ch0 (RX) */
+    DMA_RS_TI1        = 0x185,   /* IIC ch1 (TX) */
+    DMA_RS_RI1        = 0x186,   /* IIC ch1 (RX) */
+    DMA_RS_TI2        = 0x189,   /* IIC ch2 (TX) */
+    DMA_RS_RI2        = 0x18A,   /* IIC ch2 (RX) */
+    DMA_RS_TI3        = 0x18D,   /* IIC ch3 (TX) */
+    DMA_RS_RI3        = 0x18E,   /* IIC ch3 (RX) */
+    DMA_RS_LIN0_INT_T = 0x1A1,   /* LIN0 (TX) */
+    DMA_RS_LIN0_INT_R = 0x1A2,   /* LIN0 (RX) */
+    DMA_RS_LIN1_INT_T = 0x1A5,   /* LIN1 (TX) */
+    DMA_RS_LIN1_INT_R = 0x1A6,   /* LIN1 (RX) */
+    DMA_RS_IFEI0      = 0x1B1,   /* Pixel Format Converter ch0 (TX) */
+    DMA_RS_OFFI0      = 0x1B2,   /* Pixel Format Converter ch0 (TX) */
+    DMA_RS_IFEI1      = 0x1B5,   /* Pixel Format Converter ch1 (RX) */
+    DMA_RS_OFFI1      = 0x1B6    /* Pixel Format Converter ch1 (TX) */
+} dma_res_select_t;
+
+/* DMA transfer direction */
+typedef enum
+{
+    DMA_REQ_MIN =(-1),
+    DMA_REQ_SRC = 0, /* Read DMA */
+    DMA_REQ_DES = 1, /* Write DMA */
+    DMA_REQ_MAX = 2
+} dma_req_dir_t;
+
+/* Address count direction */
+typedef enum
+{
+    DMA_ADDR_MIN = (-1),
+    DMA_ADDR_INCREMENT = 0, /* Address Count Increment */
+    DMA_ADDR_FIX = 1,       /* Address Count Fix */
+    DMA_ADDR_MAX = 2
+} dma_addr_cnt_t;
+
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+
+/* DMA Init Parameter */
+typedef struct
+{
+    bool_t   channel[DMA_CH_NUM]; /* Set enable channel */
+    AIOCB    *p_aio;              /* set callback function (DMA error interrupt) */
+}dma_drv_init_t;
+
+/* DMA Setup Parameter */
+typedef struct
+{
+    dma_res_select_t   resource;     /* DMA Transfer Resource */
+    dma_req_dir_t      direction;    /* DMA Transfer Direction */
+    dma_unit_size_t    dst_width;    /* DMA Transfer Unit Size (Destination) */
+    dma_unit_size_t    src_width;    /* DMA Transfer Unit Size (Source) */
+    dma_addr_cnt_t     dst_cnt;      /* DMA Address Count (Destination) */
+    dma_addr_cnt_t     src_cnt;      /* DMA Address Count (Source) */
+    AIOCB              *p_aio;       /* set callback function (DMA end interrupt) */
+} dma_ch_setup_t;
+
+/* DMA Transfer Paramter */
+typedef struct
+{
+    void       *src_addr;    /* Sorce Address */
+    void       *dst_addr;    /* Destination Address */
+    uint32_t   count;        /* DMA Transfer Size */
+} dma_trans_data_t;
+
+/***********************************************************************************
+ Function Prototypes
+***********************************************************************************/
+
+/***********************************************************************************
+* ingroup API
+* This function initializes the driver and must be called at system start
+* up, prior to any required DMA functionality being available. This function
+* also sets the enable or disable for each DMA channel and DMA error call back 
+* function.
+*
+* param [in] p_dma_init_param - parameter of ch enable and DMA error callback function.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully initialized.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Init(const dma_drv_init_t * const p_dma_init_param, int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function shutdown the driver, making DMA functionality is no longer available.
+* It can be carried out only in calse of all channel free.
+*
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully uninitialized.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_UnInit(int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function allocates a DMA channel.
+* When channel is (-1), it looking for a free channel
+* When set channel to DMA channel number, a set channel is allocated
+*
+* param [in] channel     - allocate channel. (when channel is (-1), it looking for a 
+*                           free channel.)
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval channel number - successfully allocated.
+* retval -1             - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Alloc(const int_t channel, int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function close a DMA channel.
+*
+* param [in] channel     - close channel.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully allocate.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Free(const int_t channel, int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function set up a DMA transfer parameter.
+* before calling R_DMA_Start(), please carry out this function.
+*
+* param [in] channel     - set up channel.
+* param [in] p_ch_setup  - DMA transfer parameters.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully setup.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Setup(const int_t channel, const dma_ch_setup_t * const p_ch_setup, 
+                         int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function set up a DMA transfer address and start DMA.
+*
+* param [in] channel     - DMA start channel.
+* param [in] p_ch_setup  - DMA address parameters.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully DMA start.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Start(const int_t channel, const dma_trans_data_t * const p_dma_data, 
+                         int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function set up a continous DMA transfer address and start continuous DMA.
+*
+* param [in] channel     - continuous DMA start channel.
+* param [in] p_ch_setup  - continuous DMA address parameters.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully continuous DMA start.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_NextData(const int_t channel, const dma_trans_data_t * const p_dma_data, 
+                            int32_t * const p_errno);
+                            
+/***********************************************************************************
+* ingroup API
+* This function cancel DMA transfer.
+* Continous DMA also stops at the same time.
+* Please call this function during DMA transfer.
+*
+* param [in] channel     - chancel DMA start channel.
+* param [out] p_remain   - remain sizei of DMA transfer.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully cancel.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Cancel(const int_t channel, uint32_t * const p_remain, int32_t * const p_errno);
+
+
+/***********************************************************************************
+* ingroup API
+* This function get DMA driver version.
+*
+* param none
+*
+* retval driver version
+***********************************************************************************/
+
+extern uint16_t R_DMA_GetVersion(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* DMA_IF_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_inc/ioif_aio.h	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,103 @@
+/******************************************************************************
+ *
+ *  V. 2.03.00
+ * $Rev: 891 $
+ * $Date:: 2014-06-27 10:40:52 +0900#$
+ *
+ * Description : ioif_aio header file
+ *
+ * Copyright (C) 2009,2012 Renesas Electronics Corporation. All rights reserved.
+ *****************************************************************************/
+
+#ifndef IOIF_AIO_H
+#define IOIF_AIO_H
+
+/*************************************************************************
+ System Includes
+*************************************************************************/
+
+#include <cmsis_os.h>
+#include <posix_types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*************************************************************************
+ User Includes
+*************************************************************************/
+
+/*************************************************************************
+ Defines
+*************************************************************************/
+
+/* sigev_notify values */
+
+#define SIGEV_NONE      (1) /**< No notification */
+#define SIGEV_THREAD    (2) /**< A notification function is called in the driver's context */
+#define SIGEV_EVENT     (3) /**< An event flag is set */
+#define SIGEV_CALLBACK  (4) /**< An inter-process callback is made */
+
+/*************************************************************************
+ Constant Macros
+*************************************************************************/
+
+/*************************************************************************
+ Function Macros
+*************************************************************************/
+
+/*************************************************************************
+ Typedefs
+*************************************************************************/
+
+typedef void *      pthread_attr_t;     /**< unsupported */
+
+union sigval
+{
+    int             sival_int;          /**< Integer interpretation */
+    void *          sival_ptr;          /**< Pointer interpretation */
+};
+
+struct sigevent
+{
+    int             sigev_notify;       /**< SIGEV_NONE, SIGEV_THREAD, SIGEV_EVENT */
+    int             sigev_signo;        /**< signal or callback fp */
+    union sigval    sigev_value;        /**< user defined value to pass */
+    void            (*sigev_notify_function) (union sigval);
+                                        /**< notification function */
+};
+
+struct aiocb
+{
+    /* Implementation specific stuff */
+    struct aiocb *  pNext;              /**< next aio request */
+    struct aiocb *  pPrev;              /**< previous aio request */
+    ssize_t         aio_return;         /**< return value of operation */
+    int             aio_complete;       /**< non-zero when op is completed */
+
+    /* User parameters */
+    int             aio_fildes;         /**< FD for asynchronous op */
+    off_t           aio_offset;         /**< Absolute offset to seek to */
+    volatile void*  aio_buf;            /**< Buffer to read from/write to */
+    size_t          aio_nbytes;         /**< Number of bytes to read/write */
+    struct sigevent aio_sigevent;       /**< Signal to deliver */
+
+    /* Private implementation specific function pointer used by IOIF. Application should not set. */
+    ssize_t (*aio_iofn)(void *,void *,size_t,int);  /* synchronous I/O function */
+};
+typedef struct aiocb AIOCB;
+
+#if(1) /* mbed */
+#else
+struct timespec
+{
+    time_t   tv_sec;            /* Seconds.  */
+    long int tv_nsec;           /* Nanoseconds.  */
+};
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_inc/misratypes.h	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,189 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2009-2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/******************************************************************************
+ *
+ *  V. 2.03.00
+ * $Rev: 891 $
+ * $Date:: 2014-06-27 10:40:52 +0900#$
+ *
+ * Description : Types for MISRA compliant C code.
+ *
+ *****************************************************************************/
+
+#ifndef _MISRATYPES_H_INCLUDED_
+#define _MISRATYPES_H_INCLUDED_
+
+
+/***********************************************************************************
+ System Includes
+***********************************************************************************/
+#include <cmsis_os.h>
+
+/***********************************************************************************
+ User Includes
+***********************************************************************************/
+#include "r_typedefs.h"
+
+/***********************************************************************************
+ Defines
+***********************************************************************************/
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***********************************************************************************
+ Constant Macros
+***********************************************************************************/
+
+
+/***********************************************************************************
+ Function Macros
+***********************************************************************************/
+
+/* Use this macro for an unused function argument */
+#define UNUSED_ARG(var)  (void)unused_arg(&(var))
+
+/* Use this macro to check is a value of any type is an error code */
+#define ISERROR(val) iserror((int32_t)(val))
+
+/* Use this macro when assigning a function for a task */
+#define TO_FP_FUNCTION(val) to_fp_function(val)
+
+/***********************************************************************************
+ Typedefs
+***********************************************************************************/
+
+typedef void (*funcptr_t)(void);
+
+/***********************************************************************************
+ Enumerated Types
+***********************************************************************************/
+
+/***********************************************************************************
+ Function Prototypes
+***********************************************************************************/
+
+/* These functions are inlined by the SHC compiler in an optimise=1 build */
+static const void* unused_arg(const void* const var);
+static void *error_to_ptr(int32_t er);
+static bool_t iserror(int32_t ser);
+static funcptr_t to_fp_function(void (*val)(int32_t));
+
+/***********************************************************************************
+ Inline Functions
+***********************************************************************************/
+
+/**********************************************************************************
+Function Name:  unused_arg
+Description:    Used to prevent unused argument warnings from QA-C.
+                This function will be inlined by the SHC compiler and generate no code.
+                Use this function via the UNUSED_ARG macro.
+
+Parameters:     Pointer to unused argument
+
+Return value:   Passed in argument.
+***********************************************************************************/
+#if(1) /* mbed */
+static inline const void* unused_arg(const void* const var)
+#else
+#pragma inline unused_arg
+static const void* unused_arg(const void* const var)
+#endif
+{
+    return var;
+}
+
+/**********************************************************************************
+Function Name:  iserror
+Description:    Check if a value is an error code.  This is used instead of the HIOS
+                iserrno macro as that generates many warnings in QA-C.
+                This function will be inlined by the SHC compiler.
+                Use this function via the ISERROR macro.
+
+Parameters:     Value to check for error code
+
+Return value:   Non-zero if the value is an error code
+***********************************************************************************/
+
+#if(1) /* mbed */
+static inline bool_t iserror(const int32_t ser)
+#else
+#pragma inline iserror
+static bool_t iserror(const int32_t ser)
+#endif
+{
+    uint32_t er = (uint32_t) ser;
+    return er >= 0xffffff80u;
+}
+
+/**********************************************************************************
+Function Name:  error_to_ptr
+Description:    Convert an error code to a pointer so we can return an error from
+                IOIF driver functions such as open and initialise without getting
+                warnings from QA-C.
+                This function will be inlined by the SHC compiler.
+
+Parameters:     Error code
+
+Return value:   Error code converted to a pointer
+***********************************************************************************/
+#if(1) /* mbed */
+static inline void *error_to_ptr(const int32_t er)
+#else
+#pragma inline error_to_ptr
+static void *error_to_ptr(const int32_t er)
+#endif
+{
+    return (void*) er;
+}
+
+/**********************************************************************************
+Function Name:  to_fp_function
+Description:    Converts a void (*fn)(VP_INT) function pointer to a FP function pointer
+                without getting warnings from QA-C.
+                This function will be inlined by the SHC compiler.
+
+Parameters:     Function pointer as void (*fn)(VP_INT)
+
+Return value:   Functino pointer as a FP
+***********************************************************************************/
+#if(1) /* mbed */
+static inline funcptr_t to_fp_function(void (*val)(int32_t))
+#else
+#pragma inline to_fp_function
+static funcptr_t to_fp_function(void (*val)(int32_t))
+#endif
+{
+    /* QA-C will generate an error for this line as we are casting
+     * between different function pointer types.
+     */
+    return (funcptr_t)val;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MISRATYPES_H_INCLUDED_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_inc/posix_types.h	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,140 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2009,2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/******************************************************************************
+ *
+ *  V. 2.03.00
+ * $Rev: 891 $
+ * $Date:: 2014-06-27 10:40:52 +0900#$
+ *
+ * Description : POSIX types
+ *
+ *****************************************************************************/
+
+#ifndef POSIXTYPES_H_INCLUDED
+#define POSIXTYPES_H_INCLUDED
+
+/***********************************************************************************
+ System Includes
+***********************************************************************************/
+#if defined (__CC_ARM)
+#include    <time.h>
+#endif
+
+/***********************************************************************************
+ User Includes
+***********************************************************************************/
+
+
+/***********************************************************************************
+ Defines
+***********************************************************************************/
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* From <unistd.h> */
+#ifndef SEEK_SET
+#define SEEK_SET        0           /* from the biginning of file */
+#define SEEK_CUR        1           /* from the current position in file */
+#define SEEK_END        2           /* from the end of file */
+#endif
+
+/* <unistd.h> POSIX Standard: 2.10 file descriptors for stdin, stdout,
+  stderr not included with SHC. Therefore defined below. */
+#ifndef STDIN_FILENO
+    #define STDIN_FILENO (0)
+#endif
+
+#ifndef STDOUT_FILENO
+    #define STDOUT_FILENO (1)
+#endif
+
+#ifndef STDERR_FILENO
+    #define STDERR_FILENO (2)
+#endif
+
+
+/* These values must be as defined under open in the compiler manual
+ * otherwise the buffered file functions fopen() etc. will not work.
+ */
+#define O_ACCMODE       00000007
+#define O_RDONLY        00000001
+#define O_WRONLY        00000002
+#define O_RDWR          00000004
+#define O_CREAT         00000010
+#define O_EXCL          00000020
+#define O_TRUNC         00000040
+#define O_APPEND        00002000
+#define O_NONBLOCK      00004000
+#define O_SYNC          00010000
+
+/***********************************************************************************
+ Constant Macros
+***********************************************************************************/
+
+
+/***********************************************************************************
+ Function Macros
+***********************************************************************************/
+
+
+/***********************************************************************************
+ Typedefs and Structures
+***********************************************************************************/
+
+/* The POSIX standard states that:-
+    mode_t                              shall be an integer type.
+    nlink_t, uid_t, gid_t, and id_t     shall be integer types.
+    blkcnt_t and off_t                  shall be signed integer types.
+    fsblkcnt_t, fsfilcnt_t, and ino_t   shall be defined as unsigned integer types.
+    size_t                              shall be an unsigned integer type.
+    blksize_t, pid_t, and ssize_t       shall be signed integer types.
+    time_t and clock_t                  shall be integer or real-floating types.
+*/
+
+#if defined (__CC_ARM)
+#if !defined(__cplusplus) && defined(__STRICT_ANSI__)
+typedef unsigned long size_t;
+#endif
+typedef int             fsid_t;
+typedef long long       off_t;
+typedef unsigned int    mode_t;
+typedef unsigned int    ino_t;
+typedef int             nlink_t;
+typedef int             uid_t;
+typedef int             gid_t;
+typedef int             dev_t;
+typedef int             ssize_t;
+
+#elif defined (__GNUC__)
+#include <stdio.h>
+typedef long time_t;    /* Time in seconds. */
+typedef unsigned int mode_t;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_inc/r_errno.h	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,141 @@
+/****** ************************************************************************
+ *
+ * $Rev: 891 $
+ * $Date: 2012-12-07 20:36:39 +0900#$
+ *
+ * Description : errno for POSIX IEEE Std 1003.1-2001
+ *
+ * (C) Copyright RENESAS ELECTRONICS Ltd 2012 All Rights Reserved
+ *****************************************************************************/
+
+/* Detect if SHC include errno.h has been included first, this is not supported */
+#ifdef _ERRNO
+    #error Renesas/Sh/9_x_x/include/errno.h has been included before SDK errno.h. Please specify SDK include path first.
+#endif
+
+#ifndef SDK_ERRNO
+#define SDK_ERRNO
+
+/* Include std headers to override _errno with SDK version */
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <math.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define _REENTRANT 1
+
+/***********************************************************************************
+ System Includes
+***********************************************************************************/
+#ifdef EBADF
+    #undef EBADF
+#endif
+#ifdef EDOM
+    #undef EDOM
+#endif
+
+/* SDK errno extension, SDK returns 0 as success, and -1 when errno set */
+#define ESUCCESS    (0)
+#define EERROR      (-1)
+
+#define EBADF       (-17) /* Bad file descriptor */
+#define EINVAL      (-28) /* Invalid argument */
+#define ENOMEM      (-33) /* No memory available */
+#define ENOLCK      (-34) /* No lock available */
+#define ENOENT      (-42) /* No such file or directory */
+#define ETIMEDOUT   (-50) /* Timed out */
+#define EACCES      (-64) /* Access denied */
+#define EAGAIN      (-65) /* Resource unavailable. Try again */
+#define EBUSY       (-67) /* Device or resource busy */
+#define ECANCELED   (-68) /* Operation was cancelled */
+#define EDOM        (-69) /* Maths argument out of domain */
+#define EEXIST      (-70) /* File, directory or mount exists */
+#define EFBIG       (-71) /* File too big */
+#define EINPROGRESS (-72) /* Operation in progress */
+#define EIO         (-74) /* Input or Output error (possibly recoverable)*/
+#define EISDIR      (-75) /* Is a directory */
+#define EMFILE      (-76) /* Too many open files */
+#define ENAMETOOLONG (-77) /* File name too long */
+#define ENFILE      (-78) /* Too many files are open in the system */
+#define ENOBUFS     (-79) /* No buffers available */
+#define ENODEV      (-80) /* Not a valid device */
+#define ENOSPC      (-84) /* No space available on device */
+#define ENOTDIR     (-85) /* Not a directory */
+#define ENOTEMPTY   (-86) /* Directory not empty */
+#define ENOTSUP     (-87) /* Not supported */
+#define ENOTTY      (-88) /* No TTY available */
+#define ENXIO       (-89) /* Not valid IO address or device (unrecoverable)*/
+#define EPERM       (-90) /* Operation not permitted */
+#define EROFS       (-91) /* Read only file system */
+#define ESPIPE      (-92) /* Invalid seek on pipe */
+#define EXDEV       (-93) /* Device cross linked */
+#define ENOTSOCK    (-94) /* Not a socket */
+#define EMSGSIZE    (-95) /* Message too large */
+#define EINTR       (-96) /* Function interrupted */
+#define EFAULT      (-97) /* Section fault, bad address */
+#define EPIPE       (-98) /* Broken pipe */
+#define EALREADY    (-99) /* Connection already started */
+#define EDESTADDRREQ (-100) /* Destination address requred */
+#define EPROTOTYPE  (-101) /* Wrong protocol or codec type */
+#define ENOPROTOOPT (-102) /* Protocol or codec not available */
+#define EPROTONOSUPPORT (-103) /* Protocol or codec not supported */
+#define EOPNOTSUPP  (-104) /* Operation not supported */
+#define EAFNOSUPPORT (-105) /* Address family not supported */
+#define EADDRINUSE  (-106) /* Address already in use */
+#define EADDRNOTAVAIL (-107) /* Address not available */
+#define ECONNRESET  (-108) /* Connection reset */
+#define EISCONN     (-109) /* Connected */
+#define ENOTCONN    (-110) /* Not connected */
+#define ECONNREFUSED (-112) /* Connection refused */
+#define EPROCLIM    (-113) /* Too many processes */
+#define EUSERS      (-114) /* Too many users */
+#define EDEADLK     (-115) /* Resource deadlock would occur */
+#define EPROTO      (-116) /* Protocol or codec error */
+#define EOVERFLOW   (-117) /* Value too large to store in data type */
+#define ESRCH       (-118) /* No such task */
+#define EILSEQ      (-119) /* Illegal byte sequence format */
+#define EBADMSG     (-120) /* Bad message */
+#define ENOSYS      (-121) /* Function not supported */
+#define ECRC        (-122) /* CRC failure */
+#define EEOF        (-123) /* Position is End Of File */
+#define ESEEKPASTEND (-124) /* Seek past EOF */
+#define EMEDIUMTYPE (-127) /* Wrong medium type */
+#define ENOMEDIUM   (-128) /* No medium present */
+#define ESEEKRANGE  (-129) /* seek setting error */  /* Source Merge 11-1 */
+
+/***********************************************************************************
+ Defines
+***********************************************************************************/
+/* errno is a macro so it is re-entrant (per thread/task value) - this
+ * definition works with SH C libs.  The errno returns an l-value so
+ * it can be used on the left of an assignment as it is legal for an
+ * application to assign to errno.
+ *
+ * Note: Application code should not call ioif_get_errno directly. All
+ * access to errno should be made using the POSIX "errno" macro.
+*/
+extern int *ioif_get_errno(void);
+
+/* Remove SHC definitions so SDK can be used instead */
+#ifdef _errno
+    #undef _errno
+#endif
+
+#define _errno (*ioif_get_errno())
+
+#ifndef  errno
+    #define  errno _errno
+#endif
+
+#define iserrno(e)((unsigned int)(e) >= 0xffffff80UL)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_inc/ssif_if.h	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,279 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/******************************************************************************
+* File Name    : ssif_if.h
+* $Rev: 1032 $
+* $Date:: 2014-08-06 09:04:50 +0900#$
+* Description  : SSIF Driver API header
+******************************************************************************/
+
+#ifndef SSIF_IF_H
+#define SSIF_IF_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+#include "cmsis_os.h"
+
+#include "r_typedefs.h"
+#include "r_errno.h"
+#if(1) /* mbed */
+#include "misratypes.h"
+#include "aioif.h"
+#include "R_BSP_SsifDef.h"
+#else
+#include "ioif_public.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if(1) /* mbed */
+/******************************************************************************
+ Function Prototypes
+ *****************************************************************************/
+
+extern void* R_SSIF_InitOne(const int_t channel, void* const config_data, int32_t* const p_errno);
+extern int_t R_SSIF_UnInitOne(const int_t channel, void* const driver_instance, int32_t* const p_errno);
+extern int_t R_SSIF_Open(void* const p_driver_instance, const char_t* const p_path_name, const int_t flags, const int_t mode, int32_t* const p_errno);
+extern int_t R_SSIF_Close(void* const p_fd, int32_t* const p_errno);
+extern int_t R_SSIF_Ioctl(void* const p_fd, const int_t request, void* const p_buf, int32_t* const p_errno);
+extern int_t R_SSIF_WriteAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno);
+extern int_t R_SSIF_ReadAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno);
+extern int_t R_SSIF_Cancel(void* const p_fd, AIOCB* p_aio, int32_t* const p_errno);
+#else
+/******************************************************************************
+ Defines
+ *****************************************************************************/
+
+/******************************************************************************
+ Constant Macros
+ *****************************************************************************/
+#define SSIF_NUM_CHANS       (6u)    /**< Number of SSIF channels */
+
+#define SSIF_CFG_DISABLE_ROMDEC_DIRECT (0x0u)        /* Disable SSIRDR->STRMDIN0 route */
+#define SSIF_CFG_ENABLE_ROMDEC_DIRECT  (0xDEC0DEC1u) /* Enable  SSIRDR->STRMDIN0 route */
+
+/******************************************************************************
+ Function Macros
+ *****************************************************************************/
+
+/******************************************************************************
+ Enumerated Types
+ *****************************************************************************/
+
+/** SSICR:CKS(Clock source for oversampling) */
+typedef enum
+{
+    SSIF_CFG_CKS_AUDIO_X1  = 0,  /**< select AUDIO_X1   */
+    SSIF_CFG_CKS_AUDIO_CLK = 1   /**< select AUIDIO_CLK */
+} ssif_chcfg_cks_t; 
+
+/** SSICR:CHNL(Audio channels per system word) */
+typedef enum
+{
+    SSIF_CFG_MULTI_CH_1 = 0,     /**< 1ch within systemword (on tdm=0) */
+    SSIF_CFG_MULTI_CH_2 = 1,     /**< 2ch within systemword (on tdm=0) */
+    SSIF_CFG_MULTI_CH_3 = 2,     /**< 3ch within systemword (on tdm=0) */
+    SSIF_CFG_MULTI_CH_4 = 3      /**< 4ch within systemword (on tdm=0) */
+} ssif_chcfg_multi_ch_t;
+
+/** SSICR:DWL(Data word length) */
+typedef enum
+{
+    SSIF_CFG_DATA_WORD_8  = 0,   /**< Data word length 8  */
+    SSIF_CFG_DATA_WORD_16 = 1,   /**< Data word length 16 */
+    SSIF_CFG_DATA_WORD_18 = 2,   /**< Data word length 18 */
+    SSIF_CFG_DATA_WORD_20 = 3,   /**< Data word length 20 */
+    SSIF_CFG_DATA_WORD_22 = 4,   /**< Data word length 22 */
+    SSIF_CFG_DATA_WORD_24 = 5,   /**< Data word length 24 */
+    SSIF_CFG_DATA_WORD_32 = 6    /**< Data word length 32 */
+} ssif_chcfg_data_word_t;
+
+/** SSICR:SWL(System word length) */
+typedef enum
+{
+    SSIF_CFG_SYSTEM_WORD_8   = 0,    /**< System word length 8   */
+    SSIF_CFG_SYSTEM_WORD_16  = 1,    /**< System word length 16  */
+    SSIF_CFG_SYSTEM_WORD_24  = 2,    /**< System word length 24  */
+    SSIF_CFG_SYSTEM_WORD_32  = 3,    /**< System word length 32  */
+    SSIF_CFG_SYSTEM_WORD_48  = 4,    /**< System word length 48  */
+    SSIF_CFG_SYSTEM_WORD_64  = 5,    /**< System word length 64  */
+    SSIF_CFG_SYSTEM_WORD_128 = 6,    /**< System word length 128 */
+    SSIF_CFG_SYSTEM_WORD_256 = 7     /**< System word length 256 */
+} ssif_chcfg_system_word_t;
+
+/** SSICR:SCKP(Clock polarity) */
+typedef enum
+{
+    SSIF_CFG_FALLING = 0,    /**< Falling edge */
+    SSIF_CFG_RISING  = 1     /**< Rising edge  */
+} ssif_chcfg_clock_pol_t;
+
+/** SSICR:SWSP(Word select polarity) */
+typedef enum
+{
+    SSIF_CFG_WS_LOW  = 0,    /**< Low for ther 1st channel(not TDM) */
+    SSIF_CFG_WS_HIGH = 1     /**< High for the 1st channel(not TDM) */
+} ssif_chcfg_ws_pol_t;
+
+/** SSICR:SPDP(Serial padding polarity) */
+typedef enum
+{
+    SSIF_CFG_PADDING_LOW  = 0,   /**< Padding bits are low  */
+    SSIF_CFG_PADDING_HIGH = 1    /**< Padding bits are high */
+} ssif_chcfg_padding_pol_t;
+
+/** SSICR:SDTA(Serial data alignment) */
+typedef enum
+{
+    SSIF_CFG_DATA_FIRST    = 0,  /**< Data first         */
+    SSIF_CFG_PADDING_FIRST = 1   /**< Padding bits first */
+} ssif_chcfg_serial_alignment_t;
+
+/** SSICR:PDTA(Parallel data alignment) */
+typedef enum
+{
+    SSIF_CFG_LEFT  = 0,  /**< Left aligned  */
+    SSIF_CFG_RIGHT = 1   /**< Right aligned */
+} ssif_chcfg_parallel_alignment_t;
+
+/** SSICR:DEL(Serial data delay) */
+typedef enum
+{
+    SSIF_CFG_DELAY    = 0,   /**< 1 clock delay */
+    SSIF_CFG_NO_DELAY = 1    /**< No delay      */
+} ssif_chcfg_ws_delay_t;
+
+/** SSICR:CKDV(Serial oversampling clock division ratio) */
+typedef enum
+{
+    SSIF_CFG_CKDV_BITS_1   = 0,
+    SSIF_CFG_CKDV_BITS_2   = 1,
+    SSIF_CFG_CKDV_BITS_4   = 2,
+    SSIF_CFG_CKDV_BITS_8   = 3,
+    SSIF_CFG_CKDV_BITS_16  = 4,
+    SSIF_CFG_CKDV_BITS_32  = 5,
+    SSIF_CFG_CKDV_BITS_64  = 6,
+    SSIF_CFG_CKDV_BITS_128 = 7,
+    SSIF_CFG_CKDV_BITS_6   = 8,
+    SSIF_CFG_CKDV_BITS_12  = 9,
+    SSIF_CFG_CKDV_BITS_24  = 10,
+    SSIF_CFG_CKDV_BITS_48  = 11,
+    SSIF_CFG_CKDV_BITS_96  = 12
+} ssif_chcfg_ckdv_t;
+
+
+/** SNCR:SSIxNL(Serial sound interface channel x noise canceler enable) */
+typedef enum
+{
+    SSIF_CFG_DISABLE_NOISE_CANCEL = 0, /**< Not use noise cancel function */
+    SSIF_CFG_ENABLE_NOISE_CANCEL  = 1  /**< Use noise cancel function     */
+} ssif_chcfg_noise_cancel_t;
+
+
+/** SSITDMR:TDM(TDM mode) */
+typedef enum
+{
+    SSIF_CFG_DISABLE_TDM = 0,   /**< not TDM mode */
+    SSIF_CFG_ENABLE_TDM  = 1    /**< set TDM mode */
+} ssif_chcfg_tdm_t;
+
+/******************************************************************************
+ Structures
+ *****************************************************************************/
+
+typedef struct
+{
+    uint32_t    mode;               /* Enable/Disable SSIRDR->STRMDIN0 route */
+    void        (*p_cbfunc)(void);  /* SSIF error callback function          */
+} ssif_chcfg_romdec_t;
+
+/**< This structure contains the configuration settings */
+typedef struct
+{
+    bool_t                          enabled;             /* The enable flag for the channel       */
+    uint8_t                         int_level;           /* Interrupt priority for the channel    */
+    bool_t                          slave_mode;          /* Mode of operation                     */
+    uint32_t                        sample_freq;         /* Audio Sampling frequency(Hz)          */
+    ssif_chcfg_cks_t                clk_select;          /* SSICR-CKS : Audio clock select        */
+    ssif_chcfg_multi_ch_t           multi_ch;            /* SSICR-CHNL: Audio channels per system word */
+    ssif_chcfg_data_word_t          data_word;           /* SSICR-DWL : Data word length          */
+    ssif_chcfg_system_word_t        system_word;         /* SSICR-SWL : System word length        */
+    ssif_chcfg_clock_pol_t          bclk_pol;            /* SSICR-SCKP: Bit Clock polarity        */
+    ssif_chcfg_ws_pol_t             ws_pol;              /* SSICR-SWSP: Word Clock polarity       */
+    ssif_chcfg_padding_pol_t        padding_pol;         /* SSICR-SPDP: Padding polarity          */
+    ssif_chcfg_serial_alignment_t   serial_alignment;    /* SSICR-SDTA: Serial data alignment     */
+    ssif_chcfg_parallel_alignment_t parallel_alignment;  /* SSICR-PDTA: Parallel data alignment   */
+    ssif_chcfg_ws_delay_t           ws_delay;            /* SSICR-DEL : Serial clock delay        */
+    ssif_chcfg_noise_cancel_t       noise_cancel;        /* GPIO-SNCR : Noise cancel              */
+    ssif_chcfg_tdm_t                tdm_mode;            /* SSITDMR-TDM: TDM mode                 */
+    ssif_chcfg_romdec_t             romdec_direct;       /* DMA : SSIRDR->STRMDIN0 route settings */
+} ssif_channel_cfg_t;
+
+/******************************************************************************
+ IOCTLS
+ *****************************************************************************/
+
+#define SSIF_CONFIG_CHANNEL        (7)
+#define SSIF_GET_STATUS           (13)
+
+
+/******************************************************************************
+ External Data
+ *****************************************************************************/
+
+
+/******************************************************************************
+ Function Prototypes
+ *****************************************************************************/
+/**
+* @ingroup API
+*
+* This function returns a pointer to the function table of the SSIF driver.
+* This is intended to be used as a parameter in the ioif_start_device function.
+*
+* @retval IOIF_DRV_API* - Pointer to the table of functions supported by the
+* driver.
+*
+*/
+extern IOIF_DRV_API *R_SSIF_MakeCbTbl(void);
+#endif
+
+extern int_t R_SSIF_SWLtoLen(const ssif_chcfg_system_word_t ssicr_swl);
+
+extern int_t R_SSIF_Userdef_InitPinMux(const uint32_t ssif_ch);
+extern int_t R_SSIF_Userdef_SetClockDiv(const ssif_channel_cfg_t* const p_ch_cfg, ssif_chcfg_ckdv_t* const p_clk_div);
+
+extern uint16_t R_SSIF_GetVersion(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SSIF_IF_H */
+/*EOF*/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_src/dma/dma.c	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,1707 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         dma.c
+* $Rev: 1133 $
+* $Date:: 2014-09-08 14:33:59 +0900#$
+* @brief        DMA Driver internal functions
+******************************************************************************/
+
+/*****************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 15.01.2013 1.00 First Release
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+
+#include "dma.h"
+#include "aioif.h"
+#include "iodefine.h"
+#include "gic.h"
+#include "bsp_util.h"
+
+/******************************************************************************
+Private global driver management information
+******************************************************************************/
+
+/* driver management infrmation */
+static dma_info_drv_t gb_info_drv;
+
+/******************************************************************************
+Private global channel semaphore information
+******************************************************************************/
+
+/* driver semaphore name define */
+/* ->MISRA 8.8, 8.10, IPA M2.2.2 There is no problem in the description of declaration of 
+OS resource itself */
+osSemaphoreDef(sem_dma_ch0);
+osSemaphoreDef(sem_dma_ch1);
+osSemaphoreDef(sem_dma_ch2);
+osSemaphoreDef(sem_dma_ch3);
+osSemaphoreDef(sem_dma_ch4);
+osSemaphoreDef(sem_dma_ch5);
+osSemaphoreDef(sem_dma_ch6);
+osSemaphoreDef(sem_dma_ch7);
+osSemaphoreDef(sem_dma_ch8);
+osSemaphoreDef(sem_dma_ch9);
+osSemaphoreDef(sem_dma_ch10);
+osSemaphoreDef(sem_dma_ch11);
+osSemaphoreDef(sem_dma_ch12);
+osSemaphoreDef(sem_dma_ch13);
+osSemaphoreDef(sem_dma_ch14);
+osSemaphoreDef(sem_dma_ch15);
+/* <-MISRA 8.8, 8.10, IPA M2.2.2 */
+      
+/******************************************************************************
+Private function define (interrupt handler)
+******************************************************************************/
+
+static void R_DMA_End0InterruptHandler(void);
+static void R_DMA_End1InterruptHandler(void);
+static void R_DMA_End2InterruptHandler(void);
+static void R_DMA_End3InterruptHandler(void);
+static void R_DMA_End4InterruptHandler(void);
+static void R_DMA_End5InterruptHandler(void);
+static void R_DMA_End6InterruptHandler(void);
+static void R_DMA_End7InterruptHandler(void);
+static void R_DMA_End8InterruptHandler(void);
+static void R_DMA_End9InterruptHandler(void);
+static void R_DMA_End10InterruptHandler(void);
+static void R_DMA_End11InterruptHandler(void);
+static void R_DMA_End12InterruptHandler(void);
+static void R_DMA_End13InterruptHandler(void);
+static void R_DMA_End14InterruptHandler(void);
+static void R_DMA_End15InterruptHandler(void);
+static void R_DMA_ErrInterruptHandler(void);
+static void R_DMA_EndHandlerProcess(const int_t channel);
+
+/******************************************************************************
+ Function prototypes
+ *****************************************************************************/
+ 
+static void  DMA_OpenChannel(const int_t channel);
+
+/******************************************************************************
+* Function Name: DMA_GetDrvInstance
+* Description : Get pointer of gb_info_drv.
+* Arguments : *p_dma_info_drv -
+*                  Pointer of gb_info_drv is returned.
+* Return Value : None
+******************************************************************************/
+
+dma_info_drv_t *DMA_GetDrvInstance(void)
+{
+    
+    return &gb_info_drv;
+}
+
+/******************************************************************************
+End of function DMA_GetDrv_Instance
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_GetDrvChInfo
+* Description : Get pointer of gb_info_drv.info_ch[channel].
+* Arguments : *p_dma_info_drv -
+*                  Pointer of gb_info_drv is returned.
+* Return Value : None
+******************************************************************************/
+
+dma_info_ch_t *DMA_GetDrvChInfo(const int_t channel)
+{
+    
+    return &gb_info_drv.info_ch[channel];
+}
+
+/******************************************************************************
+End of function DMA_GetDrvChInfo
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_Initialize
+* Description : Initialize DMA driver.
+* Arguments : *p_dma_init_param -
+*                  Pointer of init parameters.
+*             sem_drv -
+*                  Driver semaphore ID.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                OS error num -
+*                  Registering handler failed.
+*                ENOMEM -
+*                  Making semaphore failed.
+******************************************************************************/
+
+int_t DMA_Initialize(const dma_drv_init_t * const p_dma_init_param, const osSemaphoreId sem_drv)
+{
+    int_t    retval = ESUCCESS;
+    int_t    ch_count;
+    uint32_t error_code;
+    bool_t   init_check_flag;
+    
+    /* ->MISRA 11.3, 11.4, IPA R3.6.2 This cast is needed for register access. */
+    /* address table of register set for each channel */
+    static volatile struct st_dmac_n *gb_dma_ch_register_addr_table[DMA_CH_NUM] = 
+        { &DMAC0,
+          &DMAC1,
+          &DMAC2,
+          &DMAC3,
+          &DMAC4,
+          &DMAC5,
+          &DMAC6,
+          &DMAC7,
+          &DMAC8,
+          &DMAC9,
+          &DMAC10,
+          &DMAC11,
+          &DMAC12,
+          &DMAC13,
+          &DMAC14,
+          &DMAC15 
+        };
+    /* <-MISRA 11.3, 11.4, IPA R3.6.2*/
+    
+    /* ->MISRA 11.3, 11.4, IPA R3.6.2 This cast is needed for register access. */
+    /* address table of register set for common register */
+    static volatile struct st_dmaccommon_n *gb_dma_common_register_addr_table[DMA_CH_NUM] = 
+        { &DMAC07,
+          &DMAC07,
+          &DMAC07,
+          &DMAC07,
+          &DMAC07,
+          &DMAC07,
+          &DMAC07,
+          &DMAC07,
+          &DMAC815,
+          &DMAC815,
+          &DMAC815,
+          &DMAC815,
+          &DMAC815,
+          &DMAC815,
+          &DMAC815,
+          &DMAC815 
+        };
+    /* <-MISRA 11.3, 11.4, IPA R3.6.2*/
+
+    /* ->MISRA 11.3, 11.4 This cast is needed for register access. */
+    /* address table of register set for DMARS */
+    static volatile uint32_t *gb_dmars_register_addr_table[DMA_CH_NUM] = 
+        { &DMACDMARS0,
+          &DMACDMARS0,
+          &DMACDMARS1,
+          &DMACDMARS1,
+          &DMACDMARS2,
+          &DMACDMARS2,
+          &DMACDMARS3,
+          &DMACDMARS3,
+          &DMACDMARS4,
+          &DMACDMARS4,
+          &DMACDMARS5,
+          &DMACDMARS5,
+          &DMACDMARS6,
+          &DMACDMARS6,
+          &DMACDMARS7,
+          &DMACDMARS7 
+        };
+    /* <-MISRA 11.3, 11.4 */
+    
+    /* Interrpt handlers table */
+    static const IRQHandler gb_dma_int_handler_table[DMA_CH_NUM] = 
+        { &R_DMA_End0InterruptHandler, /* DMA end interrupt for ch0 - ch15 */
+          &R_DMA_End1InterruptHandler,
+          &R_DMA_End2InterruptHandler,
+          &R_DMA_End3InterruptHandler,
+          &R_DMA_End4InterruptHandler,
+          &R_DMA_End5InterruptHandler,
+          &R_DMA_End6InterruptHandler,
+          &R_DMA_End7InterruptHandler,
+          &R_DMA_End8InterruptHandler,
+          &R_DMA_End9InterruptHandler,
+          &R_DMA_End10InterruptHandler,
+          &R_DMA_End11InterruptHandler,
+          &R_DMA_End12InterruptHandler,
+          &R_DMA_End13InterruptHandler,
+          &R_DMA_End14InterruptHandler,
+          &R_DMA_End15InterruptHandler
+        };
+    
+    /* Interrupt numbers table */
+    static const IRQn_Type gb_dma_int_num_table[DMA_CH_NUM] =
+        { DMAINT0_IRQn, /* DMA end interrupt for ch0 - ch15 */
+          DMAINT1_IRQn,
+          DMAINT2_IRQn,
+          DMAINT3_IRQn,
+          DMAINT4_IRQn,
+          DMAINT5_IRQn,
+          DMAINT6_IRQn,
+          DMAINT7_IRQn,
+          DMAINT8_IRQn,
+          DMAINT9_IRQn,
+          DMAINT10_IRQn,
+          DMAINT11_IRQn,
+          DMAINT12_IRQn,
+          DMAINT13_IRQn,
+          DMAINT14_IRQn,
+          DMAINT15_IRQn
+        };
+        
+    /* driver semaphore table define */
+    static const osSemaphoreDef_t *p_gb_semdef_ch[DMA_CH_NUM] = 
+        { 
+          osSemaphore(sem_dma_ch0),
+          osSemaphore(sem_dma_ch1),
+          osSemaphore(sem_dma_ch2),
+          osSemaphore(sem_dma_ch3),
+          osSemaphore(sem_dma_ch4),
+          osSemaphore(sem_dma_ch5),
+          osSemaphore(sem_dma_ch6),
+          osSemaphore(sem_dma_ch7),
+          osSemaphore(sem_dma_ch8),
+          osSemaphore(sem_dma_ch9),
+          osSemaphore(sem_dma_ch10),
+          osSemaphore(sem_dma_ch11),
+          osSemaphore(sem_dma_ch12),
+          osSemaphore(sem_dma_ch13),
+          osSemaphore(sem_dma_ch14),
+          osSemaphore(sem_dma_ch15)
+        };
+    
+    /* element of p_dma_init_param is copied to element of gb_info_drv */
+    gb_info_drv.p_err_aio = p_dma_init_param->p_aio;
+    
+    /* set driver semaphore ID */
+    gb_info_drv.sem_drv = sem_drv;
+    
+    /* set DMA error interrupt number */
+    gb_info_drv.err_irq_num = DMAERR_IRQn;
+    
+    /* init channel management information */
+    for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+    {
+        /* set channel number */
+        gb_info_drv.info_ch[ch_count].ch = ch_count;
+        
+        /* set DMA end interrupt number */
+        gb_info_drv.info_ch[ch_count].end_irq_num = gb_dma_int_num_table[ch_count];
+        
+        /* init next DMA setting flag */
+        gb_info_drv.info_ch[ch_count].next_dma_flag = false;
+        
+        if (1U == ((uint32_t)ch_count & CHECK_ODD_EVEN_MASK))
+        {
+            /* set shift number when channel is odd value */ 
+            gb_info_drv.info_ch[ch_count].shift_dmars = SHIFT_DMARS_ODD_CH;
+            /* set mask value when channel is odd value */
+            gb_info_drv.info_ch[ch_count].mask_dmars = MASK_DMARS_ODD_CH;
+        }
+        else
+        {
+            /* set shift number when channel is even value */ 
+            gb_info_drv.info_ch[ch_count].shift_dmars = SHIFT_DMARS_EVEN_CH;
+            /* set mask value when channel is even value */
+            gb_info_drv.info_ch[ch_count].mask_dmars = MASK_DMARS_EVEN_CH;
+        }
+        
+        /* init DMA setup flag */
+        gb_info_drv.info_ch[ch_count].setup_flag = false;
+        
+        /* ->MISRA 11.4 This cast is needed for register access. */
+        /* set DMA register address for each channel */
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg = gb_dma_ch_register_addr_table[ch_count];
+        /* set common resgiter for channel 0 - 7 */
+        gb_info_drv.info_ch[ch_count].p_dma_common_reg = gb_dma_common_register_addr_table[ch_count];
+        /* <-MISRA 11.4 */
+        
+        /* set DMARS register for each channel */
+        gb_info_drv.info_ch[ch_count].p_dma_dmars_reg = gb_dmars_register_addr_table[ch_count];
+    }
+    
+    /* init DMA registers */
+    for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+    {
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0SA_n =   N0SA_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1SA_n =   N1SA_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0DA_n =   N0DA_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1DA_n =   N1DA_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0TB_n =   N0TB_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1TB_n =   N1TB_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCTRL_n = CHCTRL_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCFG_n =  CHCFG_INIT_VALUE;
+        /* set DMA interval = 0 */
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHITVL_n = CHITVL_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHEXT_n =  CHEXT_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->NXLA_n =   NXLA_INIT_VALUE;
+        *(gb_info_drv.info_ch[ch_count].p_dma_dmars_reg)   =   DMARS_INIT_VALUE;
+    }
+    /* init common resgiter for channel 0 - 7 */
+    /* set interrupt output : pulse,
+       set round robin mode  */
+    gb_info_drv.info_ch[DMA_CH_0].p_dma_common_reg->DCTRL_0_7 = DCTRL_INIT_VALUE;
+    /* init common resgiter for channel 8 - 15 */
+    /* set interrupt output : pulse,
+       set round robin mode */
+    gb_info_drv.info_ch[HIGH_COMMON_REG_OFFSET].p_dma_common_reg->DCTRL_0_7 = DCTRL_INIT_VALUE;
+    
+    /* making channel semaphore */
+    init_check_flag = false;
+    ch_count = 0;
+    while (false == init_check_flag)
+    {
+        /* make semaphore */
+        gb_info_drv.info_ch[ch_count].sem_ch = osSemaphoreCreate(p_gb_semdef_ch[ch_count], 1);
+        if (NULL == gb_info_drv.info_ch[ch_count].sem_ch)
+        {
+            /* set error return value */
+            retval = ENOMEM;
+            init_check_flag = true;
+        }
+        
+        if ((DMA_CH_NUM - 1) == ch_count)
+        {
+            init_check_flag = true;
+        }
+        ch_count++;
+    }
+    
+    if (ESUCCESS == retval)
+    {
+        /* DMA end interrupt handler register */
+        init_check_flag = false;
+        ch_count = 0;
+        while (false == init_check_flag)
+        {
+            error_code = InterruptHandlerRegister(gb_info_drv.info_ch[ch_count].end_irq_num, 
+                                                  gb_dma_int_handler_table[ch_count]
+                                                  );
+            /* 0 is no error on InterruptHandlerRegister() */
+            if (0U != error_code)
+            {
+                retval = (int_t)error_code;
+                init_check_flag = true;
+            }
+            if ((DMA_CH_NUM - 1) == ch_count)
+            {
+                init_check_flag = true;
+            }
+            ch_count++;
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            /* DMA error interrupt handler register */
+            error_code = InterruptHandlerRegister(gb_info_drv.err_irq_num, 
+                                                  &R_DMA_ErrInterruptHandler
+                                                 );
+            /* 0 is no error on InterruptHandlerRegister() */
+            if (0U != error_code)
+            {
+                retval = (int_t)error_code;
+            }
+        }
+    }
+    
+    if (ESUCCESS == retval)
+    {
+        /* set DMA end interrupt level & priority */
+        for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+        {
+            /* set interrupt level (set edge trigger, 1-N model) */
+            GIC_SetLevelModel(gb_info_drv.info_ch[ch_count].end_irq_num, 1, 1);
+        }
+        /* set DMA error interrupt level (set edge trgger, 1-N model) */
+        GIC_SetLevelModel(gb_info_drv.err_irq_num, 1, 1);
+        /* DMA error interrupt enable */
+        GIC_EnableIRQ(gb_info_drv.err_irq_num);
+    }
+    
+    if (ESUCCESS == retval)
+    {
+        /* set channel status */
+        for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+        {
+            if ((bool_t)false != p_dma_init_param->channel[ch_count])
+            {
+                gb_info_drv.info_ch[ch_count].ch_stat = DMA_CH_INIT;
+            }
+            else
+            {
+                gb_info_drv.info_ch[ch_count].ch_stat = DMA_CH_UNINIT;
+            }
+        }
+        /* set driver status to DMA_DRV_INIT */
+        gb_info_drv.drv_stat = DMA_DRV_INIT;
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function DMA_Initialize
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_UnInitialize
+* Description : UnInitialize DMA driver.
+* Arguments : None.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                OS error num -
+*                  Unregistering handler failed,
+*                  or Semaphore release failed.
+******************************************************************************/
+
+int_t DMA_UnInitialize(void)
+{
+    int_t            retval = ESUCCESS;
+    int_t            ch_count;
+    uint32_t         error_code;
+    osStatus         sem_status;
+    bool_t           uninit_check_flag;
+
+    /* init DMA registers */
+    for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+    {
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCTRL_n = 0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCFG_n =  0;
+        *(gb_info_drv.info_ch[ch_count].p_dma_dmars_reg) =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0SA_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1SA_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0DA_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1DA_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0TB_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1TB_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHITVL_n = 0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHEXT_n =  0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->NXLA_n =   0;
+    }
+    /* init common resgiter for channel 0 - 7 */
+    gb_info_drv.info_ch[DMA_CH_0].p_dma_common_reg->DCTRL_0_7 = 0;
+    /* init common resgiter for channel 8 - 15 */
+    gb_info_drv.info_ch[HIGH_COMMON_REG_OFFSET].p_dma_common_reg->DCTRL_0_7 = 0;
+    
+    /* uninit DMA interrupt */
+    ch_count = 0;
+    uninit_check_flag = false;
+    while (false == uninit_check_flag)
+    {
+        /* disable DMA end interrupt */
+        GIC_DisableIRQ(gb_info_drv.info_ch[ch_count].end_irq_num);
+
+        /* unregister DMA end interrupt handler */
+        error_code = InterruptHandlerUnregister(gb_info_drv.info_ch[ch_count].end_irq_num);
+        /* 0 is no error on InterruptHandlerUnRegister() */
+        if (0U != error_code)
+        {
+            retval = (int_t)error_code;
+            uninit_check_flag = true;
+        }
+        if ((DMA_CH_NUM - 1) == ch_count)
+        {
+            uninit_check_flag = true;
+        }
+        ch_count++;
+    }
+    if (ESUCCESS == retval)
+    {
+        /* disable DMA error interrupt */
+        GIC_DisableIRQ(gb_info_drv.err_irq_num);
+        
+        /* unregister DMA interrupt error handler */
+        error_code = InterruptHandlerUnregister(gb_info_drv.err_irq_num);
+        /* 0 is no error on InterruptHandlerUnRegister() */
+        if (0U != error_code)
+        {
+            retval = (int_t)error_code;
+        }
+    }
+
+    if (ESUCCESS == retval)
+    {
+        /* delete channel semaphore */
+        ch_count = 0;
+        uninit_check_flag = false;
+        while (false == uninit_check_flag)
+        {
+            /* semaphore delete */
+            sem_status = osSemaphoreDelete(gb_info_drv.info_ch[ch_count].sem_ch);
+            if (osOK != sem_status)
+            {
+                /* set error return value */
+                retval = (int_t)sem_status;
+                uninit_check_flag = true;
+            }
+            if ((DMA_CH_NUM - 1) == ch_count)
+            {
+                uninit_check_flag = true;
+            }
+            ch_count++;
+        }
+    }
+    
+    if (ESUCCESS == retval)
+    {
+        /* set channel status to DMA_CH_UNINIT */
+        for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+        {
+            gb_info_drv.info_ch[ch_count].ch_stat = DMA_CH_UNINIT;
+        }
+        /* set driver status to DMA_DRV_UNINIT*/
+        gb_info_drv.drv_stat = DMA_DRV_UNINIT;
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function DMA_UnInitialize
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_OpenChannel
+* Description : DMA channel open.
+*               Set DMA channel status to DMA_CH_OPEN.
+* Arguments : channel -
+*                  Open channel number.
+* Return Value : None.
+******************************************************************************/
+
+static void DMA_OpenChannel(const int_t channel)
+{
+    /* set channel status to DMA_CH_OPEN */
+    gb_info_drv.info_ch[channel].ch_stat = DMA_CH_OPEN;
+    
+    return;
+}
+
+/******************************************************************************
+End of function DMA_OpenChannel
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_GetFreeChannel
+* Description : Find free DMA channel and Get DMA channel.
+* Arguments : None
+* Return Value :   channel -
+*                     Open channel number.
+*                  error code -
+*                     OS error num : Semaphore release failed.
+*                     EMFILE : When looking for a free channel, but a free channel
+*                              didn't exist.
+*                     EFAULT:  Wait semaphore failed.
+******************************************************************************/
+
+int_t DMA_GetFreeChannel(void)
+{
+    int_t           retval = EFAULT;
+    dma_info_ch_t   *dma_info_ch;
+    int_t           ch_alloc;
+    int_t           sem_wait_status;
+    osStatus        sem_release_status;
+    bool_t          ch_stat_check_flag;
+    
+    /* looking for free channel */
+    ch_stat_check_flag = false;
+    ch_alloc = 0;
+    while (false == ch_stat_check_flag)
+    {
+        dma_info_ch = DMA_GetDrvChInfo(ch_alloc);
+        /* start semaphore wait forever */
+        /* check carrying out on the task (0) */
+        if (0 == R_ExceptionalMode())
+        {
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+            sem_wait_status = osSemaphoreWait(dma_info_ch->sem_ch, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_status)
+            {
+                /* set error return value */
+                retval = EFAULT;
+                ch_stat_check_flag = true;
+            }
+        }
+                        
+        if (false == ch_stat_check_flag)
+        {
+            if (DMA_CH_INIT == dma_info_ch->ch_stat)
+            {
+                DMA_OpenChannel(ch_alloc);
+                retval = ch_alloc;
+                /* semaphore release */
+                /* check carrying out on the task (0) */
+                if (0 == R_ExceptionalMode())
+                {
+                    sem_release_status = osSemaphoreRelease(dma_info_ch->sem_ch);
+                    /* semaphore error check */
+                    if (osOK != sem_release_status)
+                    {
+                        /* set error return value */
+                        retval = (int_t)sem_release_status;
+                    }
+                }   
+                ch_stat_check_flag = true;
+            }
+            else
+            {
+                /* semaphore release */
+                /* check carrying out on the task (0) */
+                if (0 == R_ExceptionalMode())
+                {
+                    sem_release_status = osSemaphoreRelease(dma_info_ch->sem_ch);
+                    /* semaphore error check */
+                    if (osOK != sem_release_status)
+                    {
+                        /* set error return value */
+                        retval = (int_t)sem_release_status;
+                        ch_stat_check_flag = true;
+                    }
+                }
+            }
+            if (false ==  ch_stat_check_flag)
+            {
+                ch_alloc++;
+                /* not detected free channel */
+                if (DMA_CH_NUM == ch_alloc)
+                {
+                    /* set error return value */
+                    retval = EMFILE;
+                    ch_stat_check_flag = true;
+                }
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function DMA_GetFreeChannel
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_GetFixedChannel
+* Description : Get specified DMA channel number.
+* Arguments : channel -
+*                  Open channel number.
+* Return Value :   channel -
+*                     Open channel number.
+*                  error code -
+*                     OS error num : Semaphore release failed.
+*                     EBUSY : It has been allocated already in channel.
+*                     ENOTSUP : Channel status is DMA_CH_UNINIT.
+*                     EFAULT: Channel status is besides the status definded in 
+*                             dma_stat_ch_t.
+*                             Wait semaphore failed.
+******************************************************************************/
+
+int_t DMA_GetFixedChannel(const int_t channel)
+{
+    int_t           retval = ESUCCESS;
+    dma_info_ch_t   *dma_info_ch;
+    int_t           sem_wait_status;
+    osStatus        sem_release_status;
+    
+    /* allocate the specified number */
+    dma_info_ch = DMA_GetDrvChInfo(channel);
+    /* start semaphore wait forever */
+    /* check carrying out on the task (0) */
+    if (0 == R_ExceptionalMode())
+    {
+        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+        sem_wait_status = osSemaphoreWait(dma_info_ch->sem_ch, osWaitForever);
+        /* <-MISRA 10.6 */
+        /* semaphore error check */
+        if ((-1) == sem_wait_status)
+        {
+            /* set error return value */
+            retval = EFAULT;
+        }
+    }
+            
+    if (ESUCCESS == retval)
+    {
+        if (DMA_CH_INIT == dma_info_ch->ch_stat)
+        {
+            DMA_OpenChannel(channel);
+            /* return alloc channel number */
+            retval = channel;
+        }
+        else
+        {
+            /* set error return value */
+            switch (dma_info_ch->ch_stat)
+            {
+                case DMA_CH_UNINIT:
+                    retval = ENOTSUP; 
+                break;
+                /* These 2 cases are intentionally combined. */
+                case DMA_CH_OPEN:
+                case DMA_CH_TRANSFER:
+                    retval = EBUSY; 
+                break;
+                                    
+                default:
+                    retval = EFAULT; 
+                break;
+                                    
+            }
+        }
+        /* semaphore release */
+        /* check carrying out on the task (0) */
+        if (0 == R_ExceptionalMode())
+        {
+            sem_release_status = osSemaphoreRelease(dma_info_ch->sem_ch);
+            /* semaphore error check */
+            if (osOK != sem_release_status)
+            {
+                /* set error return value */
+                retval = (int_t)sem_release_status;
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function DMA_GetFixedChannel
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_CloseChannel
+* Description : DMA channel close.
+*               Set DMA channel status to DMA_CH_INIT.
+* Arguments : channel -
+*                  Close channel number.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_CloseChannel(const int_t channel)
+{
+    int_t  was_masked;
+    
+    /* disable all irq */
+    was_masked = __disable_irq();
+    /* clear DMARS register */
+    *(gb_info_drv.info_ch[channel].p_dma_dmars_reg) &= gb_info_drv.info_ch[channel].mask_dmars;
+    if (0 == was_masked)
+    {
+        /* enable all irq */
+        __enable_irq();
+        
+    }
+    /* set channel status to DMA_CH_INIT */
+    gb_info_drv.info_ch[channel].ch_stat = DMA_CH_INIT;
+    
+    return;
+}
+
+/******************************************************************************
+End of function DMA_CloseChannel
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_Setparam
+* Description : Set DMA transfer parameter to Register.
+* Arguments : channel -
+*                  Set up channel number.
+*             *p_ch_setup -
+*                  Set up parameters.
+*             *p_ch_cfg -
+*                  DMA channel config table parameters.
+*             *reqd
+*                  set vaule for REQD bit on CHCFG
+* Return Value : None.
+******************************************************************************/
+
+void DMA_SetParam(const int_t channel, const dma_ch_setup_t *const p_ch_setup, 
+                  const dma_ch_cfg_t * const p_ch_cfg, const uint32_t reqd)
+{
+    uint32_t  chcfg_sel;
+    uint32_t  value_dmars;
+    int_t     was_masked;
+    
+    /* set DMA transfer parameter to DMA channel infomation */
+    gb_info_drv.info_ch[channel].resource =  p_ch_setup->resource;
+    gb_info_drv.info_ch[channel].direction = p_ch_setup->direction;
+    gb_info_drv.info_ch[channel].src_width = p_ch_setup->src_width;
+    gb_info_drv.info_ch[channel].src_cnt =   p_ch_setup->src_cnt;
+    gb_info_drv.info_ch[channel].dst_width = p_ch_setup->dst_width;
+    gb_info_drv.info_ch[channel].dst_cnt =   p_ch_setup->dst_cnt;
+    gb_info_drv.info_ch[channel].p_end_aio = p_ch_setup->p_aio;
+    
+    /* disable all irq */
+    was_masked = __disable_irq();
+    /* set DMARS value and protect non change bit */
+    value_dmars = *(gb_info_drv.info_ch[channel].p_dma_dmars_reg);
+    value_dmars = ((value_dmars & gb_info_drv.info_ch[channel].mask_dmars) |
+                   (uint32_t)(p_ch_cfg->dmars << gb_info_drv.info_ch[channel].shift_dmars)); 
+    /* set DMARS register value */
+    *(gb_info_drv.info_ch[channel].p_dma_dmars_reg) = value_dmars;
+    if (0 == was_masked)
+    {
+        /* enable all irq */
+        __enable_irq();
+    }
+        
+    /* set CHCFG regsiter */
+    if (channel < HIGH_COMMON_REG_OFFSET)
+    {
+        chcfg_sel = (uint32_t)channel;
+    }
+    else
+    {
+        chcfg_sel = (uint32_t)(channel - HIGH_COMMON_REG_OFFSET);
+    }
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n 
+        = ((uint32_t)CHCFG_FIXED_VALUE |
+           /* ->MISRA 21.1 ,IPA R2.4.1 The value of every parameter won't be minus.
+              and the value after a shift will be less than 0x80000000 certainly. 
+           */
+           (((uint32_t)p_ch_setup->dst_cnt << CHCFG_SHIFT_DAD) & CHCFG_MASK_DAD) |
+           (((uint32_t)p_ch_setup->src_cnt << CHCFG_SHIFT_SAD) & CHCFG_MASK_SAD) |
+           (((uint32_t)p_ch_setup->dst_width << CHCFG_SHIFT_DDS) & CHCFG_MASK_DDS) |
+           (((uint32_t)p_ch_setup->src_width << CHCFG_SHIFT_SDS) & CHCFG_MASK_SDS) |
+           /* <-MISRA 21.1, IPA R2.4.1 */
+           p_ch_cfg->tm |
+           p_ch_cfg->lvl |
+           reqd |
+           chcfg_sel);
+           
+    /* set setup flag */
+    gb_info_drv.info_ch[channel].setup_flag = true;
+                     
+    return;
+}
+
+/******************************************************************************
+End of function DMA_SetParam
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_BusParam
+* Description : Set bus parameter for DMA.
+* Arguments : channel -
+*                  Set address channel number.
+*             *p_dma_data -
+*                  DMA transfer address parameter set.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_BusParam(const int_t channel, const dma_trans_data_t * const p_dma_data)
+{
+    uint32_t src_bus_addr = (uint32_t)p_dma_data->src_addr;
+    uint32_t dst_bus_addr = (uint32_t)p_dma_data->dst_addr;
+    uint32_t chext_value = (CHEXT_SET_DPR_NON_SECURE | CHEXT_SET_SPR_NON_SECURE);
+    
+    /* set bus parameter for SRC */
+    if ((DMA_EXTERNAL_BUS_END >= src_bus_addr)           ||
+        ((DMA_EXTERNAL_BUS_MIRROR_START <= src_bus_addr) &&
+         (DMA_EXTERNAL_BUS_MIRROR_END >= src_bus_addr)))
+        
+    {
+        chext_value |= CHEXT_SET_SCA_NORMAL;
+    }
+    else
+    {
+        chext_value |= CHEXT_SET_SCA_STRONG;
+    }
+    
+    /* set bus parameter for DST */
+    if ((DMA_EXTERNAL_BUS_END >= dst_bus_addr)           ||
+        ((DMA_EXTERNAL_BUS_MIRROR_START <= dst_bus_addr) &&
+         (DMA_EXTERNAL_BUS_MIRROR_END >= dst_bus_addr)))
+        
+    {
+        chext_value |= CHEXT_SET_DCA_NORMAL;
+    }
+    else
+    {
+        chext_value |= CHEXT_SET_DCA_STRONG;
+    }
+    
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHEXT_n = chext_value;
+    
+    return;
+}
+
+/******************************************************************************
+End of function DMA_BusParam
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_SetData
+* Description : Set DMA transfer address to Register.
+* Arguments : channel -
+*                  Set address channel number.
+*             *p_dma_data -
+*                  DMA transfer address parameter set.
+*             next_register_set -
+*                  Number of next register set.
+* Return Value : None.
+******************************************************************************/
+    
+void DMA_SetData(const int_t channel, const dma_trans_data_t * const p_dma_data, 
+                          const uint32_t next_register_set)
+{
+    if (0U == next_register_set)
+    {
+        /* set DMA transfer address parameters to next register set0 */
+        gb_info_drv.info_ch[channel].src_addr0 = p_dma_data->src_addr;
+        gb_info_drv.info_ch[channel].dst_addr0 = p_dma_data->dst_addr;
+        gb_info_drv.info_ch[channel].count0 =    p_dma_data->count;
+        
+        /* ->MISRA 11.3 This cast is needed for setting address to register. */
+        /* set DAM transfer addres to register */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N0SA_n = (uint32_t)p_dma_data->src_addr;
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N0DA_n = (uint32_t)p_dma_data->dst_addr;
+        /* <-MISRA 11.3 */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N0TB_n = p_dma_data->count;
+    }
+    else
+    {
+        /* set DMA transfer address parameters to next regiter set1 */
+        gb_info_drv.info_ch[channel].src_addr1 = p_dma_data->src_addr;
+        gb_info_drv.info_ch[channel].dst_addr1 = p_dma_data->dst_addr;
+        gb_info_drv.info_ch[channel].count1 =    p_dma_data->count;
+        
+        /* ->MISRA 11.3 This cast is needed for setting address to register. */
+        /* set DAM transfer addres to register */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N1SA_n = (uint32_t)p_dma_data->src_addr;
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N1DA_n = (uint32_t)p_dma_data->dst_addr;
+        /* <-MISRA 11.3 */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N1TB_n = p_dma_data->count;
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function DMA_SetData
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_SetNextData
+* Description : Set continuous DMA transfer setting.
+* Arguments : channel -
+*                  Set continuous DMA transfer channel number.
+*             *p_dma_data -
+*                  DMA transfer address parameter set.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_SetNextData(const int_t channel, const dma_trans_data_t * const p_dma_data)
+{
+    uint32_t  next_register_set;
+    
+    /* check number of next register set for next DMA transfer */
+    /* The reverse number in current number is set in next regsiter set of next DMA. */
+    if (0U == (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_SR))
+    {
+        next_register_set = 1U;
+    }
+    else
+    {
+        next_register_set = 0U;
+    }
+    
+    /* set DMA transfer address for next DMA */
+    DMA_SetData(channel, p_dma_data, next_register_set);
+    
+    /* start setting for next DMA */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n |= (uint32_t)(CHCFG_SET_REN | CHCFG_SET_RSW);
+    
+    /* set flag wich indicates that next DMA transfer set already */
+    gb_info_drv.info_ch[channel].next_dma_flag = true;
+
+    /* auto restart continous DMA */
+    if ((0U == (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_EN)) &&
+        (false == gb_info_drv.info_ch[channel].setup_flag))
+    {
+        /* auto restart DMA */
+        DMA_SetData(channel, p_dma_data, 0);
+        DMA_Start(channel, true);
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function DMA_Nextdata
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_Start
+* Description : Start DMA transfer.
+* Arguments : channel -
+*                  DMA transfer start channel number.
+*           :restart_flag -
+*                  Flag of DMA continous transfer auto restart.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_Start(const int_t channel, const bool_t restart_flag)
+{
+    if (false != restart_flag)
+    {
+        /* clear continous DMA setting */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &= 
+        ~(uint32_t)(CHCFG_SET_RSW | CHCFG_SET_RSEL | CHCFG_SET_REN);
+        gb_info_drv.info_ch[channel].next_dma_flag = false;
+    }
+    
+    /* clear setup flag */
+    gb_info_drv.info_ch[channel].setup_flag = false;
+    
+    /* reset DMA */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = CHCTRL_SET_SWRST;
+    
+    /* clear mask of DMA transfer end */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &= ~((uint32_t)CHCFG_SET_DEM);
+    
+    GIC_EnableIRQ(gb_info_drv.info_ch[channel].end_irq_num);
+    
+    /* start DMA transfer */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = CHCTRL_SET_SETEN;
+    
+    /* set channel status to DMA_CH_TRANSFER */
+    gb_info_drv.info_ch[channel].ch_stat = DMA_CH_TRANSFER;
+    
+    return;
+}
+
+/******************************************************************************
+End of function DMA_Start
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_Stop
+* Description : Stop DMA transfer.
+* Arguments : channel -
+*                  DMA transfer start channel number.
+*             *p_remain -
+*                  Remain data size of DMA transfer.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_Stop(const int_t channel, uint32_t * const p_remain)
+{
+    uint32_t  stop_wait_cnt;
+    
+    /* disable DMA end interrupt */
+    GIC_DisableIRQ(gb_info_drv.info_ch[channel].end_irq_num);
+    
+    /* stop DMA transfer */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = CHCTRL_SET_CLREN;
+    
+    /* wait DMA stop */
+    stop_wait_cnt = 0;
+    while ((0 != (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_TACT)) && 
+           (DMA_STOP_WAIT_MAX_CNT > stop_wait_cnt))
+    {
+        stop_wait_cnt++;
+    }    
+    
+    if (DMA_STOP_WAIT_MAX_CNT <= stop_wait_cnt)
+    {
+        /* NON_NOTICE_ASSERT: wait count is abnormal value (usually, a count is set to 0 or 1) */
+    }  
+    
+    /* get remain data size */
+    *p_remain = gb_info_drv.info_ch[channel].p_dma_ch_reg->CRTB_n;
+    
+    /* set mask of DMA transfer end */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n |= (uint32_t)CHCFG_SET_DEM;
+    
+    /* clear setting of continuous DMA */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &= ~(uint32_t)(CHCFG_SET_RSW | CHCFG_SET_RSEL);
+    
+    /* clear TC, END bit */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = (CHCTRL_SET_CLRTC | CHCTRL_SET_CLREND);
+    
+    /* clear flag wich indicates that next DMA transfer set already */
+    gb_info_drv.info_ch[channel].next_dma_flag = false;
+    
+    /* interrupt clear, if interrupt occured already */
+    GIC_ClearPendingIRQ(gb_info_drv.info_ch[channel].end_irq_num);
+    
+    /* set channel status to DMA_CH_OPEN */
+    gb_info_drv.info_ch[channel].ch_stat = DMA_CH_OPEN;
+    
+    return;
+}
+
+/******************************************************************************
+End of function DMA_Stop
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_SetErrCode
+* Description : Set error code to error code pointer.
+*               If error code pointer is NULL, nothing is done.
+* Arguments : error_code -
+*                  Error code.
+*             *p_errno -
+*                  Pointer of set error code.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_SetErrCode(const int_t error_code, int32_t * const p_errno)
+{
+    if (NULL != p_errno)
+    {
+        *p_errno = error_code;
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function DMA_SetErrCode
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_ErrInterruptHandler
+* Description : DMA error interrupt handler.
+*               Notify error information to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB member.
+******************************************************************************/
+
+static void R_DMA_ErrInterruptHandler(void)
+{
+    uint32_t dstat_er_0_7;
+    uint32_t dstat_er_8_15;
+    
+    if (NULL != gb_info_drv.p_err_aio)
+    {
+        /* get error channel number */
+        dstat_er_0_7  = gb_info_drv.info_ch[DMA_CH_0].p_dma_common_reg->DSTAT_ER_0_7;
+        dstat_er_8_15 = gb_info_drv.info_ch[HIGH_COMMON_REG_OFFSET].p_dma_common_reg->DSTAT_ER_0_7;
+        
+        /* set error infrmation */
+        gb_info_drv.p_err_aio->aio_sigevent.sigev_value.sival_int = (int_t)(dstat_er_0_7 | (dstat_er_8_15 << HIGH_COMMON_REG_OFFSET));
+        
+        /* set error code (EIO) */
+        gb_info_drv.p_err_aio->aio_return = EIO;
+        
+        /* call back to the module function which called DMA driver */
+        ahf_complete(NULL, gb_info_drv.p_err_aio);
+    }
+    else
+    {
+        ;
+        /* NON_NOTICE_ASSERT:<callback pointer is NULL> */
+    }
+    
+}
+
+/******************************************************************************
+End of function R_DMA_ErrInteruuptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End0InterruptHandler
+* Description : DMA end interrupt handler for channel 0.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End0InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_0);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End0InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End1InterruptHandler
+* Description : DMA end interrupt handler for channel 1.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End1InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_1);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End1InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End2InterruptHandler
+* Description : DMA end interrupt handler for channel 2.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End2InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_2);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End2InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End3InterruptHandler
+* Description : DMA end interrupt handler for channel 3.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End3InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_3);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End3InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End4InterruptHandler
+* Description : DMA end interrupt handler for channel 4.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End4InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_4);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End4InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End5InterruptHandler
+* Description : DMA end interrupt handler for channel 5.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End5InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_5);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End5InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End6InterruptHandler
+* Description : DMA end interrupt handler for channel 6.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End6InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_6);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End6InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End7InterruptHandler
+* Description : DMA end interrupt handler for channel 7.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End7InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_7);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End7InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End8InterruptHandler
+* Description : DMA end interrupt handler for channel 8.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End8InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_8);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End8InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End9InterruptHandler
+* Description : DMA end interrupt handler for channel 9.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End9InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_9);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End9InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End10InterruptHandler
+* Description : DMA end interrupt handler for channel 10.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End10InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_10);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End10InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End11InterruptHandler
+* Description : DMA end interrupt handler for channel 11.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End11InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_11);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End11InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End12InterruptHandler
+* Description : DMA end interrupt handler for channel 12.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End12InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_12);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End12InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End13InterruptHandler
+* Description : DMA end interrupt handler for channel 13.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End13InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_13);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End13InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End14InterruptHandler
+* Description : DMA end interrupt handler for channel 14.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End14InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_14);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End14InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End15InterruptHandler
+* Description : DMA end interrupt handler for channel 15.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End15InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_15);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End15InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_EndHandlerProcess
+* Description : DMA end interrupt handler process carry out.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : channel -
+*                  Open channel number.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+__inline static void R_DMA_EndHandlerProcess(const int_t channel)
+{
+    bool_t   store_next_dma_flag;
+    
+    if (NULL != gb_info_drv.info_ch[channel].p_end_aio)
+    {
+    
+        /* store next_dma_flag */
+        store_next_dma_flag = gb_info_drv.info_ch[channel].next_dma_flag;
+    
+        /* clear flag wich indicates that next DMA transfer set already */
+        gb_info_drv.info_ch[channel].next_dma_flag = false;
+    
+        if (false == store_next_dma_flag) 
+        {
+            /* DMA transfer complete */
+            /* mask DMA end interrupt */
+            GIC_DisableIRQ(gb_info_drv.info_ch[channel].end_irq_num);
+        
+            /* set channel status to DMA_CH_OPEN */
+            gb_info_drv.info_ch[channel].ch_stat = DMA_CH_OPEN;
+        
+            /* set mask of DMA transfer end */
+            gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n |= (uint32_t)CHCFG_SET_DEM;
+    
+            /* clear setting of continuous DMA */
+            gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &= ~(uint32_t)(CHCFG_SET_RSW | CHCFG_SET_RSEL);
+            
+            /* check EN bit is clear */
+            if (0U == (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_EN))
+            {
+                /* set error code (ESUCCESS) */
+                gb_info_drv.info_ch[channel].p_end_aio->aio_return = ESUCCESS;
+            }
+            else
+            {
+                /* set error code (EIO) */
+                gb_info_drv.info_ch[channel].p_end_aio->aio_return = EIO;
+            }
+        }
+        else
+        {
+            /* set next DMA already */
+            /* set error code (ESUCCESS) */
+            gb_info_drv.info_ch[channel].p_end_aio->aio_return = ESUCCESS;
+        }
+    
+        /* clear TC, END bit */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = (CHCTRL_SET_CLRTC | CHCTRL_SET_CLREND);
+
+        /* call back to the module function which called DMA driver */
+        ahf_complete(NULL, gb_info_drv.info_ch[channel].p_end_aio);
+        
+    }
+    else
+    {
+        ;
+        /* NON_NOTICE_ASSERT:<callback pointer is NULL> */
+    }
+    
+}
+
+/******************************************************************************
+End of function R_DMA_EndHandlerProcess
+******************************************************************************/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_src/dma/dma.h	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,264 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         dma.h
+* $Rev: 1317 $
+* $Date:: 2014-12-04 10:43:59 +0900#$
+* @brief        DMA Driver internal headers
+******************************************************************************/
+
+/*****************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 15.01.2013 1.00 First Release
+******************************************************************************/
+
+#ifndef DMA_H
+#define DMA_H
+
+/******************************************************************************
+Includes <System Includes>, "Project Includes"
+******************************************************************************/
+
+#include "dma_if.h" 
+#include "Renesas_RZ_A1.h"
+#include "bsp_drv_cmn.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* Number of channel configure table */
+#define DMA_CH_CONFIG_TABLE_NUM  (95U)
+
+/* Magic Number */
+#define SHIFT_DMARS_EVEN_CH      (0U)  /* Shift Value for DMARS Register access in Even ch */
+#define SHIFT_DMARS_ODD_CH       (16U) /* Shift Value for DMARS Register access in Odd ch */
+#define MASK_DMARS_EVEN_CH       (0xFFFF0000U) /* Mask value for DMARS Register in Even ch */
+#define MASK_DMARS_ODD_CH        (0x0000FFFFU) /* Mask value for DMARS Register in Odd ch */
+#define HIGH_COMMON_REG_OFFSET   (8)  /* for Common Register Access in ch 0-8 */
+#define CHECK_ODD_EVEN_MASK      (0x00000001U)  /* for check value of odd or even */
+#define DMA_STOP_WAIT_MAX_CNT    (10U) /* Loop count for DMA stop (usually, a count is set to 0 or 1) */
+
+/* Register Set Value */
+/* Init Value */
+#define N0SA_INIT_VALUE      (0U)          /* HW init value */
+#define N1SA_INIT_VALUE      (0U)          /* HW init value */
+#define N0DA_INIT_VALUE      (0U)          /* HW init value */
+#define N1DA_INIT_VALUE      (0U)          /* HW init value */
+#define N0TB_INIT_VALUE      (0U)          /* HW init value */
+#define N1TB_INIT_VALUE      (0U)          /* HW init value */
+#define CHCTRL_INIT_VALUE    (0U)          /* HW init value */
+#define CHCFG_INIT_VALUE     (0x01000000U) /* interrupt disable */
+#define CHITVL_INIT_VALUE    (0U)          /* DMA interval = 0 */
+#define CHEXT_INIT_VALUE     (0U)          /* HW init value */
+#define NXLA_INIT_VALUE      (0U)          /* HW init value */
+#define DCTRL_INIT_VALUE     (0x00000001U) /* interrupt output : pulse, round robin mode */
+#define DMARS_INIT_VALUE     (0U)          /* HW init value */
+/* Fixed Setting for CHCFG */
+#define CHCFG_FIXED_VALUE    (0x00000020U) /* register mode, not buffer sweep, interrupt detect when high pulse */
+
+/* Bit Value & Mask */
+/* CHSTAT */
+#define CHSTAT_MASK_SR         (0x00000080U)
+#define CHSTAT_MASK_END        (0x00000020U)
+#define CHSTAT_MASK_ER         (0x00000010U)
+#define CHSTAT_MASK_TACT       (0x00000004U)
+#define CHSTAT_MASK_EN         (0x00000001U)
+/* CHCTRL */
+#define CHCTRL_SET_CLRTC       (0x00000040U)
+#define CHCTRL_SET_CLREND      (0x00000020U)
+#define CHCTRL_SET_SWRST       (0x00000008U)
+#define CHCTRL_SET_CLREN       (0x00000002U)
+#define CHCTRL_SET_SETEN       (0x00000001U)
+/* CHCFG */
+#define CHCFG_SET_REN          (0x40000000U)
+#define CHCFG_MASK_REN         (0x40000000U)
+#define CHCFG_SET_RSW          (0x20000000U)
+#define CHCFG_MASK_RSW         (0x20000000U)
+#define CHCFG_SET_RSEL         (0x10000000U)
+#define CHCFG_MASK_RSEL        (0x10000000U)
+#define CHCFG_SET_DEM          (0x01000000U)
+#define CHCFG_MASK_DEM         (0x01000000U)
+#define CHCFG_MASK_DAD         (0x00200000U)
+#define CHCFG_MASK_SAD         (0x00100000U)
+#define CHCFG_MASK_DDS         (0x000f0000U)
+#define CHCFG_MASK_SDS         (0x0000f000U)
+#define CHCFG_SET_AM_LEVEL     (0x00000100U)
+#define CHCFG_SET_AM_BUS_CYCLE (0x00000200U)
+#define CHCFG_MASK_AM          (0x00000700U)
+#define CHCFG_SET_LVL_EDGE     (0x00000000U)
+#define CHCFG_SET_LVL_LEVEL    (0x00000040U)
+#define CHCFG_MASK_LVL         (0x00000040U)
+#define CHCFG_SET_REQD_SRC     (0x00000000U)
+#define CHCFG_SET_REQD_DST     (0x00000008U)
+#define CHCFG_MASK_REQD        (0x00000008U)
+#define CHCFG_SHIFT_DAD        (21U)
+#define CHCFG_SHIFT_SAD        (20U)
+#define CHCFG_SHIFT_DDS        (16U)
+#define CHCFG_SHIFT_SDS        (12U)
+/* CHEXT */
+#define CHEXT_SET_DCA_NORMAL      (0x00003000U)
+#define CHEXT_SET_DCA_STRONG      (0x00000000U)
+#define CHEXT_SET_DPR_NON_SECURE  (0x00000200U)
+#define CHEXT_SET_SCA_NORMAL      (0x00000030U)
+#define CHEXT_SET_SCA_STRONG      (0x00000000U)
+#define CHEXT_SET_SPR_NON_SECURE  (0x00000002U)
+
+
+/* REQD value in CHCFG is undecided on config table */
+/* used case of a resource is the same and two or more direction value exists.  */
+#define CHCFG_REQD_UNDEFINED   DMA_REQ_MAX
+
+/* Address of area which is the target of setting change */
+#define DMA_EXTERNAL_BUS_START         (0x00000000U)
+#define DMA_EXTERNAL_BUS_END           (0x1FFFFFFFU)
+#define DMA_EXTERNAL_BUS_MIRROR_START  (0x40000000U)
+#define DMA_EXTERNAL_BUS_MIRROR_END    (0x5FFFFFFFU)
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+/* DRV Status */
+typedef enum
+{
+    DMA_DRV_UNINIT = 0,   /* Uninit */
+    DMA_DRV_INIT   = 1    /* Init */
+} dma_stat_drv_t;
+
+/* Channel Status */
+typedef enum
+{
+    DMA_CH_UNINIT   = 0,   /* Uninit */
+    DMA_CH_INIT     = 1,   /* Init */
+    DMA_CH_OPEN     = 2,   /* Open */
+    DMA_CH_TRANSFER = 4    /* Transfer */
+} dma_stat_ch_t;
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+
+/* DMA Register (Common) */
+typedef struct
+{
+    volatile uint32_t  dctrl;            
+    volatile uint32_t  dstat_en;         
+    volatile uint32_t  dstat_er;         
+    volatile uint32_t  dstat_end;        
+    volatile uint32_t  dstat_tc;         
+    volatile uint32_t  dstat_sus;        
+} dma_reg_common_t;
+
+/* DMA Register (every Channel) */
+typedef struct
+{
+    volatile uint32_t  n0sa;        
+    volatile uint32_t  n0da;         
+    volatile uint32_t  n0tb;         
+    volatile uint32_t  n1sa;         
+    volatile uint32_t  n1da;         
+    volatile uint32_t  n1tb;         
+    volatile uint32_t  crsa;         
+    volatile uint32_t  crda;         
+    volatile uint32_t  crtb;         
+    volatile uint32_t  chstat;       
+    volatile uint32_t  chctrl;       
+    volatile uint32_t  chcfg;        
+    volatile uint32_t  chitvl;       
+    volatile uint32_t  chext;        
+    volatile uint32_t  nxla;        
+    volatile uint32_t  crla;         
+} dma_reg_ch_t;
+
+/* Information of Channel */
+typedef struct
+{
+    int_t              ch;                /* Channel Number */
+    dma_stat_ch_t      ch_stat;           /* Channel Status */
+    osSemaphoreId      sem_ch;            /* Channel Semaphore */
+    dma_res_select_t   resource;          /* DMA Transfer Resource */
+    dma_req_dir_t      direction;         /* DMA Transfer Direction */
+    dma_unit_size_t    src_width;         /* DMA Transfer Unit Size (Source) */
+    dma_addr_cnt_t     src_cnt;           /* DMA Address Count (Source) */
+    dma_unit_size_t    dst_width;         /* DMA Transfer Unit Size (Destination) */
+    dma_addr_cnt_t     dst_cnt;           /* DMA Address Count (Destination) */
+    void               *src_addr0;        /* Sorce Address (Next Register Set 0)*/
+    void               *dst_addr0;        /* Destination Address (Next Register Set 0)*/
+    uint32_t           count0;            /* DMA Transfer Size (Next Register Set 0)*/
+    void               *src_addr1;        /* Sorce Address (Next Register Set 1)*/
+    void               *dst_addr1;        /* Destination Address (Next Register Set 1)*/
+    uint32_t           count1;            /* DMA Transfer Size (Next Register Set 1)*/
+    IRQn_Type          end_irq_num;       /* DMA end interrupt number */
+    AIOCB              *p_end_aio;        /* set callback function (DMA end interrupt) */
+    bool_t             next_dma_flag;     /* Setting Flag of Continous DMA */
+    uint32_t           shift_dmars;       /* set SHIFT_DMARS_ODD_CH or SHIFT_DMARS_EVEN_CH */
+    uint32_t           mask_dmars;        /* set MASK_DMA_ODD_CH or MASK_DMARS_EVEN_CH */
+    bool_t             setup_flag;        /* incdicate called DMA_Setup() flag */
+    volatile struct st_dmac_n       *p_dma_ch_reg;     /* DMA Register for every channel */
+    volatile struct st_dmaccommon_n *p_dma_common_reg; /* DMA Register for common */
+    volatile uint32_t           *p_dma_dmars_reg;  /* DMARS Regsiter */
+} dma_info_ch_t;
+
+/* Information of Driver */
+typedef struct
+{
+    dma_stat_drv_t  drv_stat;            /* DRV Status */
+    AIOCB           *p_err_aio;          /* set callback function (DMA error interrupt) */
+    osSemaphoreId   sem_drv;             /* Driver Semaphore */
+    IRQn_Type       err_irq_num;         /* DMA error interrupt number */
+    dma_info_ch_t   info_ch[DMA_CH_NUM]; /* Enable Channel */
+} dma_info_drv_t;
+
+/* DMA Channel Configure Table */
+typedef struct
+{
+    dma_res_select_t   dmars;             /* Set Value for DMARS Register */
+    uint32_t           tm;                /* Set Value for TM Bit (CHCFG Register) */
+    uint32_t           lvl;               /* Set Value for LVL Bit (CHCFG Register) */
+    uint32_t           reqd;              /* Set Value for REQD (CHCFG Register) */
+} dma_ch_cfg_t;
+
+/***********************************************************************************
+ Function Prototypes
+***********************************************************************************/
+
+dma_info_drv_t *DMA_GetDrvInstance(void);
+dma_info_ch_t  *DMA_GetDrvChInfo(const int_t channel);
+int_t DMA_Initialize(const dma_drv_init_t * const p_dma_init_param, const osSemaphoreId sem_drv);
+int_t DMA_UnInitialize(void);
+int_t DMA_GetFreeChannel(void);
+int_t DMA_GetFixedChannel(const int_t channel);
+void  DMA_CloseChannel(const int_t channel);
+void  DMA_SetParam(const int_t channel, const dma_ch_setup_t * const p_ch_setup,
+                   const dma_ch_cfg_t * const p_ch_cfg, const uint32_t reqd);
+void  DMA_BusParam(const int_t channel, const dma_trans_data_t * const p_dma_data);
+void  DMA_SetData(const int_t channel, const dma_trans_data_t * const p_dma_data, 
+                 const uint32_t next_register_set);
+void  DMA_SetNextData(const int_t channel, const dma_trans_data_t * const p_dma_data);
+void  DMA_Start(const int_t channel, const bool_t restart_flag);
+void  DMA_Stop(const int_t channel, uint32_t * const p_remain);
+void  DMA_SetErrCode(const int_t error_code, int32_t * const p_errno);
+
+#endif /* DMA_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_src/dma/dma_if.c	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,1346 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         dma_if.c
+* $Rev: 1317 $
+* $Date:: 2014-12-04 10:43:59 +0900#$
+* @brief        DMA Driver interface functions
+******************************************************************************/
+
+/*****************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 15.01.2013 1.00 First Release
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+
+#include "dma.h"
+#include "bsp_util.h"
+
+/******************************************************************************
+Private global tables
+******************************************************************************/
+
+/******************************************************************************
+Private global driver semaphore information
+******************************************************************************/
+
+/* driver semaphore define */
+/* ->MISRA 8.8, 8.10, IPA M2.2.2 There is no problem in the description of declaration of 
+OS resource itself */
+osSemaphoreDef(sem_dma_drv);
+/* <-MISRA 8.8, 8.10, IPA M2.2.2 */
+
+/******************************************************************************
+* Function Name: R_DMA_Init
+* Description : Init DMA driver.
+*               Making driver semaphore and check parameter in this function.
+* Arguments : *p_dma_init_param -
+*                  Point of driver init parameter.
+*             *p_errno-
+*                  Pointer of error code.
+*                  When pointer is NULL, it isn't set error code.
+*                  error code -
+*                     OS error num : Registering handler failed.
+*                     ENOMEM : Making semaphore failed.
+*                     EPERM : Pointer of callback function which called in DMA 
+*                             error interrupt handler is NULL.
+*                     EFAULT : dma_init_param is NULL.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called.  */
+int_t R_DMA_Init(const dma_drv_init_t * const p_dma_init_param, int32_t * const p_errno) 
+/* <-IPA M1.1.1 */
+{
+    int_t         retval = ESUCCESS;
+    int_t         result_init;
+    osSemaphoreId sem_drv_create_id;
+    
+    DMA_SetErrCode(ESUCCESS, p_errno);
+    sem_drv_create_id = NULL;
+    
+    if (NULL == p_dma_init_param)
+    {
+        /* set error return value */
+        retval = (EERROR);
+        DMA_SetErrCode(EFAULT, p_errno);
+    }
+    
+    if (ESUCCESS == retval)
+    {
+        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+        if (NULL == p_dma_init_param->p_aio)
+        /* <-MISRA 1.2 */
+        {
+            /* set error return value */
+            retval = (EERROR);
+            DMA_SetErrCode(EPERM, p_errno);
+        }
+    }
+    
+    if (ESUCCESS == retval)
+    {
+        /* makeing driver semaphore */
+        /* make semaphore */
+        sem_drv_create_id = osSemaphoreCreate(osSemaphore(sem_dma_drv), 1);
+        if (NULL == sem_drv_create_id)
+        {
+            /* set error return value */
+            retval = (EERROR);
+            DMA_SetErrCode(ENOMEM, p_errno);
+        }
+    }
+    
+    if ((ESUCCESS == retval) && (NULL != sem_drv_create_id))
+    {
+        result_init = DMA_Initialize(p_dma_init_param, sem_drv_create_id);
+        if (ESUCCESS != result_init)
+        {
+            /* set error return value */
+            retval = (EERROR);
+            DMA_SetErrCode(result_init, p_errno);
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_Init
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_UnInit
+* Description : UnInit DMA driver.
+*               Delete driver semaphore and check parameter in this function.
+* Arguments : *p_errno-
+*                  Pointer of error code.
+*                  When pointer is NULL, it isn't set error code.
+*                  error code -
+*                     OS error num : Unegistering handler failed.
+*                     OS error num : Semaphore release failed.
+*                     OS error num : Semaphore delete failed.
+*                     EACCES : Driver status isn't DMA_DRV_INIT.
+*                     EBUSY : It has been allocated already in channel.
+*                     EFAULT : Wait semaphore failed.
+*                              Channel status is besides the status definded in 
+*                              dma_stat_ch_t.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_UnInit(int32_t * const p_errno) 
+/* <-IPA M1.1.1 */
+{
+    int_t          retval = ESUCCESS;
+    int_t          result_uninit;
+    dma_info_drv_t *dma_info_drv;
+    dma_info_ch_t  *dma_info_ch;
+    int_t          ch_count;
+    int32_t        sem_wait_status;
+    osStatus       sem_status;
+    bool_t         ch_stat_check_flag;
+    
+    DMA_SetErrCode(ESUCCESS, p_errno);
+
+    dma_info_drv = DMA_GetDrvInstance();
+    
+    /* start semaphore wait forever */
+    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+    sem_wait_status = osSemaphoreWait(dma_info_drv->sem_drv, osWaitForever);
+    /* <-MISRA 10.6 */
+    /* semaphore error check */
+    if ((-1) == sem_wait_status)
+    {
+        retval = EERROR;
+        DMA_SetErrCode(EFAULT, p_errno);
+    }
+    
+    /* check driver status */
+    if (ESUCCESS == retval)
+    {
+        if (DMA_DRV_INIT != dma_info_drv->drv_stat)
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EACCES, p_errno);
+        }
+        else
+        {
+            ch_stat_check_flag = false;
+            ch_count = 0;
+            while (false == ch_stat_check_flag)
+            {
+                /* check channel status */
+                dma_info_ch = DMA_GetDrvChInfo(ch_count);
+                if ((DMA_CH_UNINIT != dma_info_ch->ch_stat) &&
+                    (DMA_CH_INIT != dma_info_ch->ch_stat))
+                {
+                    /*  set error return value */
+                    retval = EERROR;
+                    /* check channel status is busy */
+                    switch (dma_info_ch->ch_stat)
+                    {
+                        /* These 2 cases are intentionally combined. */
+                        case DMA_CH_OPEN:
+                        case DMA_CH_TRANSFER:
+                            DMA_SetErrCode(EBUSY, p_errno); 
+                        break;
+                        
+                        default:
+                            DMA_SetErrCode(EFAULT, p_errno);
+                        break;
+                    }
+                }
+                
+                if ((DMA_CH_NUM - 1) == ch_count)
+                {
+                    /* channel status check end */
+                    ch_stat_check_flag = true;
+                }
+                ch_count++;
+            }
+        }
+        /* uninitialize DMA */
+        if (ESUCCESS == retval)
+        {
+            result_uninit = DMA_UnInitialize();
+            if (ESUCCESS != result_uninit)
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(result_uninit, p_errno);
+            }
+        }
+        /* semaphore release */
+        sem_status = osSemaphoreRelease(dma_info_drv->sem_drv);
+        if (osOK != sem_status)
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode((int_t)sem_status, p_errno);
+        }
+        
+        if ((osOK == sem_status) && (ESUCCESS == retval))
+        {
+            /* semaphore delete */
+            sem_status = osSemaphoreDelete(dma_info_drv->sem_drv);
+            if (osOK != sem_status)
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode((int_t)sem_status, p_errno);
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_UnInit
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_Alloc
+* Description : Open DMA channel.
+*               Check parameter in this function mainly.
+* Arguments : channel -
+*                  Open channel number.
+*                  If channel is (-1), it looking for free chanel and allocate.
+*             *p_errno -
+*                  Pointer of error code.
+*                  When pointer is NULL, it isn't set error code.
+*                  error code -
+*                     OS error num : Semaphore release failed.
+*                     EINVAL : Value of the ch is outside the range of 
+*                              DMA_ALLOC_CH(-1) <= ch < DMA_CH_NUM.
+*                     EACCES : Driver status isn't DMA_DRV_INIT.
+*                     EBUSY : It has been allocated already in channel.
+*                     EMFILE : When looking for a free channel, but a free channel
+*                              didn't exist.
+*                     ENOTSUP : Channel status is DMA_CH_UNINIT.
+*                     EFAULT: Channel status is besides the status definded in 
+*                             dma_stat_ch_t.
+*                             Wait semaphore failed.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Alloc(const int_t channel, int32_t * const p_errno) 
+/* <-IPA M1.1.1 */
+{
+    int_t           retval = ESUCCESS;
+    int_t           ercd = ESUCCESS;
+    int_t           get_ch_num;
+    dma_info_drv_t  *dma_info_drv;
+    int_t           sem_wait_status;
+    osStatus        sem_release_status;
+
+    DMA_SetErrCode(ESUCCESS, p_errno);
+
+    /* check driver status */
+    dma_info_drv = DMA_GetDrvInstance();
+    
+    /* start semaphore wait forever */
+    /* check carrying out on the task (0) */
+    if (0 == R_ExceptionalMode())
+    {
+        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+        sem_wait_status = osSemaphoreWait(dma_info_drv->sem_drv, osWaitForever);
+        /* <-MISRA 10.6 */
+        /* semaphore error check */
+        if ((-1) == sem_wait_status)
+        {
+            ercd = EFAULT;
+        }
+    }
+    
+    if (ESUCCESS == ercd)
+    {
+        if (DMA_DRV_INIT != dma_info_drv->drv_stat)
+        {
+            /* set error return value */
+            ercd =  EACCES;
+        }
+        else
+        {
+            /* check channel of argment */
+            if ((DMA_ALLOC_CH <= channel) && (channel < DMA_CH_NUM))
+            {
+                if (DMA_ALLOC_CH == channel)
+                {
+                    get_ch_num = DMA_GetFreeChannel();
+                }
+                else
+                {
+                    get_ch_num = DMA_GetFixedChannel(channel);
+                }
+                
+                /* check return number or error number */
+                if ((DMA_ALLOC_CH < get_ch_num) && (get_ch_num < DMA_CH_NUM))
+                {
+                    /* set channel number to return value */
+                    retval = get_ch_num;
+                }
+                else
+                {
+                    /* set error code to error value */
+                    ercd = get_ch_num;
+                }
+            }
+            else
+            {
+                /* set error return value */
+                ercd =  EINVAL;
+            }
+        }
+        /* semaphore release */
+        /* check carrying out on the task (0) */
+        if (0 == R_ExceptionalMode())
+        {
+            sem_release_status = osSemaphoreRelease(dma_info_drv->sem_drv);
+            if (osOK != sem_release_status)
+            {
+                /* set error return value */
+                ercd = (int_t)sem_release_status;
+            }
+        }
+    }
+    
+    /* occured error check */
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+        DMA_SetErrCode(ercd, p_errno);
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_Alloc
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_Free
+* Description : Close DMA channel.
+*               Check parameter in this function mainly.
+* Arguments : channel -
+*                  Close channel number.
+*             *p_errno -
+*                  Pointer of error code.
+*                  When pointer is NULL, it isn't set error code.
+*                  error code -
+*                     OS error num : Semaphore release failed.
+*                     EBADF : Channel status is DMA_CH_INIT.
+*                     EINVAL : Value of the ch is outside the range of 
+*                              (-1) < ch < (DMA_CH_NUM + 1).
+*                     EACCES : Driver status isn't DMA_DRV_INIT.
+*                     EBUSY : It has been start DMA transfer in channel.
+*                     ENOTSUP : Channel status is DMA_CH_UNINIT.
+*                     EFAULT: Channel status is besides the status definded in 
+*                             dma_stat_ch_t.
+*                             Wait semaphore failed.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Free(const int_t channel, int32_t *const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t           retval = ESUCCESS;
+    dma_info_drv_t  *dma_info_drv;
+    dma_info_ch_t   *dma_info_ch;
+    int_t           sem_wait_status;
+    osStatus        sem_release_status;
+    int_t           error_code;
+    
+    DMA_SetErrCode(ESUCCESS, p_errno);
+
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+         /* check driver status */
+        dma_info_drv = DMA_GetDrvInstance();
+        
+        /* start semaphore wait forever */
+        /* check carrying out on the task (0) */
+        if (0 == R_ExceptionalMode())
+        {
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+            sem_wait_status = osSemaphoreWait(dma_info_drv->sem_drv, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_status)
+            {
+                retval = EERROR;
+                DMA_SetErrCode(EFAULT, p_errno);
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            /* check driver status */
+            if (DMA_DRV_INIT == dma_info_drv->drv_stat)
+            {
+                dma_info_ch = DMA_GetDrvChInfo(channel);
+                /* start semaphore wait forever */
+                /* check carrying out on the task (0) */
+                if (0 == R_ExceptionalMode())
+                {
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_status = osSemaphoreWait(dma_info_ch->sem_ch, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_status)
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        DMA_SetErrCode(EFAULT, p_errno);
+                    }
+                }
+                
+                if (ESUCCESS == retval)
+                {
+                    if (DMA_CH_OPEN == dma_info_ch->ch_stat)
+                    {
+                        DMA_CloseChannel(channel);
+                    }
+                    else
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        switch (dma_info_ch->ch_stat)
+                        {
+                            case DMA_CH_UNINIT:
+                                error_code = ENOTSUP; 
+                            break;
+                            
+                            case DMA_CH_INIT:
+                                error_code = EBADF;
+                            break;
+                            
+                            case DMA_CH_TRANSFER:
+                                error_code = EBUSY; 
+                            break;
+                            
+                            default:
+                                error_code = EFAULT; 
+                            break;
+                        }
+                        DMA_SetErrCode(error_code, p_errno);
+                    }
+                    /* semaphore release */
+                    /* check carrying out on the task (0) */
+                    if (0 == R_ExceptionalMode())
+                    {
+                        sem_release_status = osSemaphoreRelease(dma_info_ch->sem_ch);
+                        /* semaphore error check */
+                        if (osOK != sem_release_status)
+                        {
+                            /* set error return value */
+                            retval = EERROR;
+                            DMA_SetErrCode((int_t)sem_release_status, p_errno);
+                        }
+                    }
+                }
+            }
+            else
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(EACCES, p_errno);
+            
+            }
+            /* semaphore release */
+            /* check carrying out on the task (0) */
+            if (0 == R_ExceptionalMode())
+            {
+                sem_release_status = osSemaphoreRelease(dma_info_drv->sem_drv);
+                if (osOK != sem_release_status)
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode((int_t)sem_release_status, p_errno);
+                }
+            }
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL, p_errno);
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_Free
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_Setup
+* Description : Setup DMA transfer parameter.
+*               Check parameter in this function mainly.
+* Arguments : channel -
+*                  Setup channel number.
+*             *p_ch_setup -
+*                  Set up parameters.
+*             *p_errno -
+*                  Pointer of error code.
+*                  When pointer is NULL, it isn't set error code.
+*                  error code -
+*                     OS error num : Semaphore release failed.
+*                     EBADF : Channel status is DMA_CH_INIT.
+*                     EINVAL : Value of the ch is outside the range of 
+*                              (-1) < ch < (DMA_CH_NUM + 1).
+*                     EBUSY : It has been start DMA transfer in channel.
+*                     ENOTSUP : Channel status is DMA_CH_UNINIT.
+*                     EPERM : The value in p_ch_setup isn't in the right range.
+*                     EFAULT: Channel status is besides the status definded in 
+*                             dma_stat_ch_t.
+*                             p_ch_setup is NULL.
+*                             Wait semaphore failed.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Setup(const int_t channel, const dma_ch_setup_t * const p_ch_setup, 
+                  int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t            retval = ESUCCESS;
+    dma_info_ch_t    *dma_info_ch;
+    int_t            sem_wait_status;
+    osStatus         sem_release_status;
+    int_t            error_code;
+    uint32_t         cfg_table_count;
+    dma_ch_cfg_t     ch_cfg_set_table;
+    uint32_t         set_reqd;
+    bool_t           check_table_flag;
+    
+    /* Resouce Configure Set Table */
+    static const dma_ch_cfg_t ch_cfg_table[DMA_CH_CONFIG_TABLE_NUM] =
+    {
+        {DMA_RS_OSTIM0,     CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_OSTIM1,     CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TGI0A,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TGI1A,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TGI2A,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TGI3A,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TGI4A,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI0,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI0,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI1,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI1,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI2,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI2,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI3,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI3,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI4,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI4,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI5,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI5,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI6,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI6,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI7,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI7,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_USB0_DMA0,  CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_USB0_DMA1,  CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_USB1_DMA0,  CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_USB1_DMA1,  CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_ADEND,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_IEBBTD,     CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_IEBBTV,     CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_IREADY,     CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_FLDT,       CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_SDHI_0T,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SDHI_0R,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SDHI_1T,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SDHI_1R,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_MMCT,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_MMCR,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SSITXI0,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SSIRXI0,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SSITXI1,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SSIRXI1,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SSIRTI2,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_SSITXI3,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SSIRXI3,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SSIRTI4,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_SSITXI5,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SSIRXI5,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SCUTXI0,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI0,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SCUTXI1,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI1,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SCUTXI2,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI2,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SCUTXI3,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI3,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SPTI0,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPRI0,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SPTI1,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPRI1,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SPTI2,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPRI2,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SPTI3,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPRI3,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SPTI4,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPRI4,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SPDIFTXI,   CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPDIFRXI,   CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_CMI1,       CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_CMI2,       CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_MLBCI,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_SGDEI0,     CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SGDEI1,     CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SGDEI2,     CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SGDEI3,     CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCUTXI0,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI0,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SCUTXI1,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI1,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TI0,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_RI0,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TI1,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_RI1,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TI2,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_RI2,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TI3,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_RI3,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_LIN0_INT_T, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_LIN0_INT_R, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_LIN1_INT_T, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_LIN1_INT_R, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_IFEI0,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_OFFI0,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_IFEI1,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_OFFI1,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  }
+    };
+    
+    DMA_SetErrCode(ESUCCESS, p_errno);
+    /* dummy init set_reqd */
+    set_reqd = CHCFG_REQD_UNDEFINED;
+    ch_cfg_set_table = ch_cfg_table[0];
+    
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+        if (NULL != p_ch_setup)
+        {
+            /* check setup parameter */
+            /* check AIOCB pointer */
+            if (NULL == p_ch_setup->p_aio)
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(EPERM, p_errno);
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                /* check DMA transfer unit size for destination */
+                if (((int_t)p_ch_setup->dst_width <= DMA_UNIT_MIN) || 
+                    ((int_t)p_ch_setup->dst_width >= DMA_UNIT_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM, p_errno);
+                }
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                /* check DMA transfer unit size for source */
+                if (((int_t)p_ch_setup->src_width <= DMA_UNIT_MIN) || 
+                    ((int_t)p_ch_setup->src_width >= DMA_UNIT_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM, p_errno);
+                }
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                /* check DMA address count direction for destination */
+                if (((int_t)p_ch_setup->dst_cnt <= DMA_ADDR_MIN) || 
+                    ((int_t)p_ch_setup->dst_cnt >= DMA_ADDR_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM, p_errno);
+                }
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                /* check DMA address count direction for source */
+                if (((int_t)(p_ch_setup->src_cnt) <= DMA_ADDR_MIN) || 
+                    ((int_t)p_ch_setup->src_cnt >= DMA_ADDR_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM, p_errno);
+                }
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                /* check DMA transfer direction */
+                if (((int_t)p_ch_setup->direction <= DMA_REQ_MIN) || 
+                    ((int_t)p_ch_setup->direction >= DMA_REQ_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM, p_errno);
+                }
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                /* check DMA transfer resouce */
+                check_table_flag = false;
+                cfg_table_count = 0;
+                while (false == check_table_flag)
+                {
+                    if (p_ch_setup->resource == ch_cfg_table[cfg_table_count].dmars)
+                    {
+                        /* check reqd is undefined */ 
+                        if (CHCFG_REQD_UNDEFINED == ch_cfg_table[cfg_table_count].reqd)
+                        {
+                            /* set reqd value on fixed value */
+                            if (DMA_REQ_SRC == p_ch_setup->direction)
+                            {
+                                set_reqd = CHCFG_SET_REQD_SRC;
+                            }
+                            else 
+                            {
+                                set_reqd = CHCFG_SET_REQD_DST;
+                            }
+                        }
+                        else
+                        {
+                            /* set reqd value in channel config table */
+                            set_reqd = ch_cfg_table[cfg_table_count].reqd;
+                        }
+                        /* set channel config table address for DMA_SetParam() */
+                        ch_cfg_set_table = ch_cfg_table[cfg_table_count];
+                        check_table_flag = true;
+                    }
+                    if (false == check_table_flag)
+                    {
+                        /* resource value did not exist in channel config table */
+                        if ((uint32_t)((sizeof(ch_cfg_table)/sizeof(dma_ch_cfg_t)) - 1U) == cfg_table_count)
+                        {
+                            /* set error return value */
+                            retval = EERROR;
+                            DMA_SetErrCode(EPERM, p_errno);
+                            check_table_flag = true;
+                        }
+                        cfg_table_count++;
+                    }
+                }
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                dma_info_ch = DMA_GetDrvChInfo(channel);
+                /* start semaphore wait forever */
+                /* check carrying out on the task (0) */
+                if (0 == R_ExceptionalMode())
+                {
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_status = osSemaphoreWait(dma_info_ch->sem_ch, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_status)
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        DMA_SetErrCode(EFAULT, p_errno);
+                    }
+                }
+                
+                if (ESUCCESS == retval)
+                {
+                    if (DMA_CH_OPEN == dma_info_ch->ch_stat)
+                    {
+                        /* set up parameter */
+                        DMA_SetParam(channel, p_ch_setup, &ch_cfg_set_table, set_reqd);
+                    }
+                    else
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        switch (dma_info_ch->ch_stat)
+                        {
+                            case DMA_CH_UNINIT:
+                                error_code = ENOTSUP; 
+                            break;
+                             
+                            case DMA_CH_INIT:
+                                error_code = EBADF;
+                            break;
+                        
+                            case DMA_CH_TRANSFER:
+                                error_code = EBUSY; 
+                            break;
+                        
+                            default:
+                                error_code = EFAULT; 
+                            break;
+                        }
+                        DMA_SetErrCode(error_code, p_errno);
+                    }
+                    /* semaphore release */
+                    /* check carrying out on the task (0) */
+                    if (0 == R_ExceptionalMode())
+                    {
+                        sem_release_status = osSemaphoreRelease(dma_info_ch->sem_ch);
+                        /* semaphore error check */
+                        if (osOK != sem_release_status)
+                        {
+                            /* set error return value */
+                            retval = EERROR;
+                            DMA_SetErrCode((int_t)sem_release_status, p_errno);
+                        }
+                    }
+                }
+            }
+        }
+        else
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EFAULT, p_errno);
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL, p_errno);        
+    }
+    
+    return retval;
+    
+}
+
+/******************************************************************************
+End of function R_DMA_SetParam
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_Start
+* Description : Start DMA transfer.
+*               Check parameter in this function mainly.
+* Arguments : channel -
+*                  DMA start channel number.
+*             *p_dma_data -
+*                  DMA address parameters.
+*             *p_errno -
+*                  Pointer of error code.
+*                  When pointer is NULL, it isn't set error code.
+*                  error code -
+*                     OS error num : Semaphore release failed.
+*                     EBADF : Channel status is DMA_CH_INIT.
+*                     EINVAL : Value of the ch is outside the range of 
+*                              (-1) < ch < (DMA_CH_NUM + 1).
+*                     EBUSY : It has been start DMA transfer in channel.
+*                     ENOTSUP : Channel status is DMA_CH_UNINIT.
+*                     EPERM : The value in p_ch_setup isn't in the right range.
+*                     EFAULT: Channel status is besides the status definded in 
+*                             dma_stat_ch_t.
+*                             p_dma_data is NULL.
+*                             Wait semaphore release.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Start(const int_t channel, const dma_trans_data_t * const p_dma_data, 
+                  int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t          retval = ESUCCESS;
+    dma_info_ch_t  *dma_info_ch;
+    int_t          sem_wait_status;
+    osStatus       sem_release_status;
+    int_t          error_code;
+    
+    DMA_SetErrCode(ESUCCESS, p_errno);
+    
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+        if (NULL != p_dma_data)
+        {
+            /* check address parameter */
+            /* check DMA transfer count destination address is 0 */
+            if (0U == p_dma_data->count)
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(EPERM, p_errno);
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                dma_info_ch = DMA_GetDrvChInfo(channel);
+                /* start semaphore wait forever */
+                /* check carrying out on the task (0) */
+                if (0 == R_ExceptionalMode())
+                {
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_status = osSemaphoreWait(dma_info_ch->sem_ch, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_status)
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        DMA_SetErrCode(EFAULT, p_errno);
+                    }
+                }
+                
+                if (ESUCCESS == retval)
+                {
+                    if (DMA_CH_OPEN == dma_info_ch->ch_stat)
+                    {
+                        /* set bus paramter for DMA */
+                        DMA_BusParam(channel, p_dma_data);
+                        /* set up address parameter */
+                        /* Next register set is 0 */
+                        DMA_SetData(channel, p_dma_data, 0);
+                        /* DMA transfer start */
+                        DMA_Start(channel, false);
+                    }
+                    else
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        switch (dma_info_ch->ch_stat)
+                        {
+                            case DMA_CH_UNINIT:
+                                error_code = ENOTSUP; 
+                             break;
+                             
+                             case DMA_CH_INIT:
+                                error_code = EBADF;
+                             break;
+                        
+                            case DMA_CH_TRANSFER:
+                                error_code = EBUSY; 
+                            break;
+                        
+                            default:
+                                error_code = EFAULT; 
+                             break;
+                        }
+                        DMA_SetErrCode(error_code, p_errno);
+                    }
+                    /* semaphore release */
+                    /* check carrying out on the task (0) */
+                    if (0 == R_ExceptionalMode())
+                    {
+                        sem_release_status = osSemaphoreRelease(dma_info_ch->sem_ch);
+                        /* semaphore error check */
+                        if (osOK != sem_release_status)
+                        {
+                            /* set error return value */
+                            retval = EERROR;
+                            DMA_SetErrCode((int_t)sem_release_status, p_errno);
+                        }
+                    }
+                }
+            }
+        }
+        else
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EFAULT, p_errno);
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL, p_errno);        
+    }
+    
+    return retval;
+    
+}
+
+/******************************************************************************
+End of function R_DMA_Start
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_NextData
+* Description : Set continous DMA mode.
+*               Check parameter in this function mainly.
+* Arguments : channel -
+*                  Continuous DMA channel number.
+*             *p_dma_data -
+*                  DMA address parameters.
+*             *p_errno -
+*                  Pointer of error code.
+*                  When pointer is NULL, it isn't set error code.
+*                  error code -
+*                     OS error num : Semaphore release failed.
+*                     EBADF : Channel status is DMA_CH_INIT.
+*                     EINVAL : Value of the ch is outside the range of 
+*                              (-1) < ch < (DMA_CH_NUM + 1).
+*                     EBUSY : It has been set continous DMA transfer.
+*                     ENOTSUP : Channel status is DMA_CH_UNINIT.
+*                     EPERM : The value in p_ch_setup isn't in the right range.
+*                     EFAULT: Channel status is besides the status definded in 
+*                             dma_stat_ch_t.
+*                             p_dma_data is NULL.
+*                             Wait semaphore failed.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_NextData(const int_t channel, const dma_trans_data_t * const p_dma_data, 
+                     int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t          retval = ESUCCESS;
+    dma_info_ch_t  *dma_info_ch;
+    int_t          sem_wait_status;
+    osStatus       sem_release_status;
+    int_t          error_code;
+    
+    DMA_SetErrCode(ESUCCESS, p_errno);
+    
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+        if (NULL != p_dma_data)
+        {
+            /* check address parameter */
+            /* check DMA transfer count destination address is 0 */
+            if (0U == p_dma_data->count)
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(EPERM, p_errno);
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                dma_info_ch = DMA_GetDrvChInfo(channel);
+                /* check carrying out on the task (0) */
+                if (0 == R_ExceptionalMode())
+                {
+                    /* start semaphore wait forever */
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_status = osSemaphoreWait(dma_info_ch->sem_ch, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_status)
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        DMA_SetErrCode(EFAULT, p_errno);
+                    }
+                }
+                    
+                if (ESUCCESS == retval)
+                {
+                    if ((DMA_CH_OPEN == dma_info_ch->ch_stat) ||
+                        (DMA_CH_TRANSFER == dma_info_ch->ch_stat))
+                    {
+                        if (false == dma_info_ch->next_dma_flag)
+                        {
+                            /* set up address parameter for continous DMA*/
+                            DMA_SetNextData(channel, p_dma_data);
+                        }
+                        else
+                        {
+                            /* set error return value */
+                            retval = EERROR;
+                            DMA_SetErrCode(EBUSY, p_errno);
+                        }
+                    }
+                    else
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        switch (dma_info_ch->ch_stat)
+                        {
+                            case DMA_CH_UNINIT:
+                                error_code = ENOTSUP; 
+                            break;
+                            
+                            case DMA_CH_INIT:
+                                error_code = EBADF;
+                            break;
+                            
+                            default:
+                                error_code = EFAULT; 
+                            break;
+                        }
+                        DMA_SetErrCode(error_code, p_errno);
+                    }
+
+                    /* check carrying out on the task (0) */
+                    if (0 == R_ExceptionalMode()) 
+                    {
+                        /* semaphore release */
+                        sem_release_status = osSemaphoreRelease(dma_info_ch->sem_ch);
+                        /* semaphore error check */
+                        if (osOK != sem_release_status)
+                        {
+                            /* set error return value */
+                            retval = EERROR;
+                            DMA_SetErrCode((int_t)sem_release_status, p_errno);
+                        }
+                    }
+                }
+            }
+        }
+        else
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EFAULT, p_errno);
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL, p_errno);        
+    }
+    
+    return retval;
+    
+}
+
+/******************************************************************************
+End of function R_DMA_NextData
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_Cancel
+* Description : Cancel DMA transfer.
+*               Check parameter in this function mainly.
+* Arguments : channel -
+*                  Cancel DMA channel number.
+*             *p_remain -
+*                  Remain data size of DMA transfer when it stopping.
+*             *p_errno -
+*                  Pointer of error code.
+*                  When pointer is NULL, it isn't set error code.
+*                  error code -
+*                     OS error num : Semaphore release failed.
+*                     EBADF : Channel status is DMA_CH_INIT or DMA_CH_OPEN.
+*                             (DMA stopped)
+*                     EINVAL : Value of the ch is outside the range of 
+*                              (-1) < ch < (DMA_CH_NUM + 1).
+*                     ENOTSUP : Channel status is DMA_CH_UNINIT.
+*                     EFAULT: Channel status is besides the status definded in 
+*                             dma_stat_ch_t.
+*                             p_remain is NULL.
+*                             Wait semaphhore failed.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Cancel(const int_t channel, uint32_t * const p_remain, int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t          retval = ESUCCESS;
+    dma_info_ch_t  *dma_info_ch;
+    int_t          sem_wait_status;
+    osStatus       sem_release_status;
+    int_t          error_code;
+    
+    DMA_SetErrCode(ESUCCESS, p_errno);
+    
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+        /* check whether p_remain is NULL */
+        if (NULL != p_remain)
+        {
+            dma_info_ch = DMA_GetDrvChInfo(channel);
+            
+            if (0 == R_ExceptionalMode())
+            {
+                /* start semaphore wait forever */
+                /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                sem_wait_status = osSemaphoreWait(dma_info_ch->sem_ch, osWaitForever);
+                /* <-MISRA 10.6 */
+                /* semaphore error check */
+                if ((-1) == sem_wait_status)
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EFAULT, p_errno);
+                }
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                if (DMA_CH_TRANSFER == dma_info_ch->ch_stat)
+                {
+                    /* set up address parameter for continous DMA*/
+                    DMA_Stop(channel, p_remain);
+                }
+                else
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    switch (dma_info_ch->ch_stat)
+                    {
+                        case DMA_CH_UNINIT:
+                            error_code = ENOTSUP; 
+                        break;
+                        
+                        case DMA_CH_INIT:
+                            error_code = EBADF;
+                        break;
+                        
+                        case DMA_CH_OPEN:
+                            error_code = EBADF;
+                        break;
+                        
+                        default:
+                            error_code = EFAULT; 
+                        break;
+                    }
+                    DMA_SetErrCode(error_code, p_errno);
+                }
+                
+                if (0 == R_ExceptionalMode())
+                {
+                    /* semaphore release */
+                    sem_release_status = osSemaphoreRelease(dma_info_ch->sem_ch);
+                    /* semaphore error check */
+                    if (osOK != sem_release_status)
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        DMA_SetErrCode((int_t)sem_release_status, p_errno);
+                    }
+                }
+            }
+        }
+        else
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EFAULT, p_errno);
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL, p_errno);
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_Cancel
+******************************************************************************/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_src/dma/dma_ver.c	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,72 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         dma_ver.c
+* $Rev: 1070 $
+* $Date:: 2014-08-21 14:04:31 +0900#$
+* @brief        DMA Driver get verion function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "cmsis_os.h"
+#include "dma_if.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* Ex. V2.12 -> MAJOR=2, MINOR=12 */
+#define DMA_DRV_VER_MAJOR  (2u)
+#define DMA_DRV_VER_MINOR  (1u)
+
+#define DMA_DRV_VER_MASK   (0xFFu)
+#define DMA_DRV_VER_SHIFT  (8u)
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_GetVersion
+* @brief         Get DMA driver version.
+*
+*                Description:<br>
+*                
+* @param         none
+* @retval        driver version -
+*                    upper 8bit=MAJOR
+*                    lower 8bit=MINOR
+******************************************************************************/
+uint16_t R_DMA_GetVersion(void)
+{
+    const uint16_t version =
+        ((DMA_DRV_VER_MAJOR & DMA_DRV_VER_MASK) << DMA_DRV_VER_SHIFT)
+        | (DMA_DRV_VER_MINOR & DMA_DRV_VER_MASK);
+
+    return version;
+}
+/******************************************************************************
+End of function R_DMA_GetVersion
+******************************************************************************/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_src/ioif/aioif.c	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,418 @@
+/******************************************************************************
+ *
+ * $Rev: 891 $
+ * $Date: 2012-12-18 11:09:19 +0900#$
+ *
+ * Description : ITRON support functions for IOIF Asynchronous I/O header file
+ *
+ * (C) Copyright RENESAS ELECTRONICS EUROPE Ltd 2012 All Rights Reserved
+ *****************************************************************************/
+
+/*************************************************************************
+ System Includes
+*************************************************************************/
+
+#include <r_errno.h>
+#include <cmsis_os.h>
+#include <aioif.h>
+#if(1) /* mbed */
+#include "cmsis.h"
+#else
+#include <ipcb.h>
+#include <ioif_aio_helper.h>
+#endif
+#include <misratypes.h>
+#include "bsp_drv_cmn.h"
+
+/*************************************************************************
+ OS Resources
+*************************************************************************/
+
+
+/*************************************************************************
+ Functions
+*************************************************************************/
+static void ahf_lock(AHF_S * const ahf);
+static void ahf_unlock(AHF_S * const ahf);
+
+static void ahf_lock(AHF_S * const ahf)
+{
+    if(ahf->flags & AHF_LOCKSEM)
+    {
+        osMutexWait(ahf->semid, 0);
+    }
+    else if (ahf->flags & AHF_LOCKINT)
+    {
+        ahf->saved_int_mask = __disable_irq();
+    }
+    else
+    {
+        ;   /* MISRA compliance. */
+    }
+}
+
+static void ahf_unlock(AHF_S * const ahf)
+{
+    if(ahf->flags & AHF_LOCKSEM)
+    {
+        osMutexRelease(ahf->semid);
+    }
+    else if (ahf->flags & AHF_LOCKINT)
+    {
+        if (0 == ahf->saved_int_mask)
+        {
+            __enable_irq();
+        }
+    }
+    else
+    {
+        ;   /* MISRA compliance. */
+    }
+}
+
+/***********************************************************************************
+Function Name:         ahf_create
+
+Description:    Creates an empty aio control queue pointer.
+                Creates a mutex if AHF_CREATESEM bit flag is set.
+
+Parameters:     ahf  - aio queue structure pointer.
+                f    - flag indicating that at semaphore is to be created.
+
+Return value:   0 on success.   negative error code on error.
+***********************************************************************************/
+int32_t ahf_create (AHF_S * const ahf, const uint32_t f)
+{
+    osMutexDef_t* p_mutex_def;
+    uint32_t*     p_mutex_data;
+
+    if (ahf == NULL)
+    {
+        return EFAULT;
+    }
+
+    ahf->head = NULL;
+    ahf->tail = NULL;
+    ahf->flags = f;
+
+    /* create the mutex if required */
+    if (f & AHF_CREATESEM)
+    {
+        p_mutex_def = calloc(1, sizeof(osMutexDef_t));
+        if ( NULL == p_mutex_def )
+        {
+            return ENOMEM;
+        }
+        p_mutex_data = calloc(3, sizeof(uint32_t));
+        if ( NULL == p_mutex_data )
+        {
+            free(p_mutex_def);
+            return ENOMEM;
+        }
+        p_mutex_def->mutex = p_mutex_data;
+        ahf->p_cmtx = p_mutex_def;
+        ahf->semid = osMutexCreate (p_mutex_def);
+        if ( NULL == ahf->semid )
+        {
+            free(p_mutex_data);
+            free(p_mutex_def);
+            return ENOMEM;
+        }
+    }
+
+    return 0;
+}
+
+/***********************************************************************************
+Function Name:         ahf_destroy
+
+Description:    Delete aio control block mutex (if it exists).
+                Note: This function does not delete the aio control block queue.
+
+Parameters:     ahf  - aio queue structure pointer.
+
+Return value:   void
+
+***********************************************************************************/
+void ahf_destroy (AHF_S const * const ahf)
+{
+    if (ahf == NULL)
+    {
+        return; 
+    }
+     
+    if (ahf->flags & AHF_CREATESEM)
+    {
+        osMutexDelete (ahf->semid);
+        free(ahf->p_cmtx->mutex);
+        free(ahf->p_cmtx);
+    }
+}
+
+/***********************************************************************************
+Function Name:         ahf_addtail
+
+Description:    Add an aio control block to the queue.
+
+Parameters:     ahf  - aio queue structure pointer.
+                aio  - pointer to queue structure.
+
+Return value:   void
+
+***********************************************************************************/
+void ahf_addtail (AHF_S * const ahf, struct aiocb * const aio)
+{
+    if (ahf == NULL)
+    {
+        return; 
+    }
+     
+    ahf_lock (ahf);
+    if (ahf->tail != NULL)
+    {
+        ahf->tail->pNext = aio;
+    }
+    aio->pPrev = ahf->tail;
+    aio->pNext = NULL;
+    ahf->tail = aio;
+    if (ahf->head == NULL)
+    {
+        /* list was empty */
+        ahf->head = aio;
+    }
+
+    ahf_unlock (ahf);
+}
+
+/***********************************************************************************
+Function Name:         ahf_removehead
+
+Description:    Remove an aio control block from the queue.
+
+Parameters:     ahf  - aio queue structure pointer.
+
+Return value:   aio control block, or NULL if queue is empty.
+
+***********************************************************************************/
+struct aiocb *ahf_removehead (AHF_S * const ahf)
+{
+    struct aiocb *aio;
+    
+    if (ahf == NULL)
+    {
+        return(NULL);   
+    }
+     
+    ahf_lock (ahf);
+
+    aio = ahf->head;
+    if (aio != NULL)
+    {
+        ahf->head = aio->pNext;
+        if (aio->pNext != NULL)
+        {
+            aio->pNext->pPrev = NULL;
+        }
+        if (ahf->tail == aio)
+        {
+            /* the list is now empty */
+            ahf->tail = NULL;
+        }
+    }
+
+    ahf_unlock (ahf);
+    return aio;
+}
+
+/***********************************************************************************
+Function Name:         ahf_peekhead
+
+Description:    Get an aio control block from the queue, but do not remove from the queue.
+
+Parameters:     ahf  - aio queue structure pointer.
+
+Return value:   aio control block, or NULL if queue is empty.
+
+***********************************************************************************/
+struct aiocb *ahf_peekhead (AHF_S * const ahf)
+{
+    struct aiocb *aio;
+
+    ahf_lock (ahf);
+
+    aio = ahf->head;
+
+    ahf_unlock (ahf);
+    return aio;
+}
+
+/***********************************************************************************
+Function Name:         ahf_cancelall
+
+Description:    Empty an aio control block queue.
+
+Parameters:     ahf  - aio queue structure pointer.
+
+Return value:   void
+
+***********************************************************************************/
+void ahf_cancelall (AHF_S * const ahf)
+{
+    struct aiocb *cur, *next;
+
+    ahf_lock (ahf);
+
+    /* cancel all pending requests */
+    cur = ahf->head;
+    while (cur != NULL)
+    {
+        next = cur->pNext;
+        cur->aio_return = ECANCELED;
+        ahf_complete (ahf, cur);
+        cur = next;
+    }
+    /* mark the list as empty */
+    ahf->head = NULL;
+    ahf->tail = NULL;
+
+    ahf_unlock (ahf);
+}
+
+/***********************************************************************************
+Function Name:         ahf_complete
+
+Description:    Flag that the operation is complete.
+                If required by the sigev_notify variable contents, the calling task is
+                notified.
+                If a notify was setup, it is signalled.
+                
+Parameters:     ahf  - aio queue structure pointer.
+                aio  - pointer to queue structure.
+
+Return value:   0 on success.   negative error code on error.
+
+***********************************************************************************/
+void ahf_complete (AHF_S *ahf, struct aiocb * const aio)
+{
+#if(1) /* mbed */
+#else
+    int rv;
+#endif
+    UNUSED_ARG(ahf);
+
+    if (NULL == aio)
+    {
+        return;
+    }
+
+    /* Flag that the operation is complete */
+    /*  This function must be here
+        because another task may release AIOCB block
+        after the task changed by an iTRON function in the switch statement */
+    aio->aio_complete = 1;
+    switch (aio->aio_sigevent.sigev_notify)
+    {
+    case SIGEV_EVENT:
+         osSignalSet ((osThreadId)aio->aio_sigevent.sigev_value.sival_int,
+             (int32_t)aio->aio_sigevent.sigev_signo);
+        break;
+
+    case SIGEV_THREAD:
+        if (aio->aio_sigevent.sigev_notify_function)
+        {
+            (aio->aio_sigevent.sigev_notify_function)
+                (aio->aio_sigevent.sigev_value);
+        }
+        break;
+
+#if(1) /* mbed */
+#else
+    case SIGEV_CALLBACK:
+        rv = ipcb_callback ((ipcb_id_t*)aio->aio_sigevent.sigev_signo, &aio->aio_sigevent);
+        break;
+#endif
+
+    default:
+        /* No notify function */
+        break;
+
+    }
+
+    /* Wakeup any suspended tasks */
+#if(1) /* mbed */
+#else
+    aio_complete_suspended(aio);
+#endif
+}
+
+/***********************************************************************************
+Function Name:         ahf_cancel
+
+Description:    Remove an aio control block from the queue.
+                Signal completion to the calling task and wake it up.
+                If aio is NULL, cancel all.
+                
+Parameters:     ahf  - aio queue structure pointer.
+                aio  - pointer to queue structure.
+
+Return value:   0 on success.   negative error code on error.
+
+***********************************************************************************/
+int32_t ahf_cancel (AHF_S * const ahf, struct aiocb * const aio)
+{
+    struct aiocb *cur;
+    int32_t rv = EINVAL;
+
+    if (ahf == NULL)
+    {
+        return EFAULT;  
+    }
+     
+    /* If aio is NULL, must cancel all. */
+    if(NULL == aio)
+    {
+        ahf_cancelall(ahf);
+        rv = 0;
+    }
+    
+    else
+    {
+        ahf_lock (ahf);
+
+        cur = ahf->head;
+        while ((cur != NULL) && (cur != aio))
+        {
+            cur = cur->pNext;
+        }
+
+        if (cur == aio)
+        {
+            if (aio->pPrev != NULL)
+            {
+                aio->pPrev->pNext = aio->pNext;
+            }
+
+            if (aio->pNext != NULL)
+            {
+                aio->pNext->pPrev = aio->pPrev;
+            }
+
+            if (ahf->head == cur)
+            {
+                ahf->head = cur->pNext;
+            }
+
+            if (ahf->tail == cur)
+            {
+                ahf->tail = cur->pPrev;
+            }
+
+            cur->aio_return = ECANCELED;
+            ahf_complete (ahf, aio);
+            rv = 0;
+        }
+
+        ahf_unlock (ahf);
+    }
+    return rv;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_src/ssif/ssif.c	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,1429 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : ssif.c
+* $Rev: 891 $
+* $Date:: 2014-06-27 10:40:52 +0900#$
+* Description : SSIF driver functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "ssif.h"
+#include "iodefine.h"
+#include "ssif_int.h"
+#include "Renesas_RZ_A1.h"
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Exported global variables (to be accessed by other files)
+*******************************************************************************/
+/* ->MISRA 8.8, MISRA 8.10, IPA M2.2.2 : These declare statements are dependent on CMSIS-RTOS */
+osSemaphoreDef(ssif_ch0_access);
+osSemaphoreDef(ssif_ch1_access);
+osSemaphoreDef(ssif_ch2_access);
+osSemaphoreDef(ssif_ch3_access);
+osSemaphoreDef(ssif_ch4_access);
+osSemaphoreDef(ssif_ch5_access);
+/* <-MISRA 8.8, MISRA 8.10, IPA M2.2.2 */
+
+ssif_info_drv_t g_ssif_info_drv;
+
+volatile struct st_ssif* const g_ssireg[SSIF_NUM_CHANS] = SSIF_ADDRESS_LIST;
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static int_t SSIF_InitChannel(ssif_info_ch_t* const p_info_ch);
+static void SSIF_UnInitChannel(ssif_info_ch_t* const p_info_ch);
+static int_t SSIF_UpdateChannelConfig(ssif_info_ch_t* const p_info_ch,
+                                      const ssif_channel_cfg_t* const p_ch_cfg);
+static int_t SSIF_SetCtrlParams(const ssif_info_ch_t* const p_info_ch);
+static int_t SSIF_CheckChannelCfg(const ssif_channel_cfg_t* const p_ch_cfg);
+static int_t SSIF_CheckWordSize(const ssif_info_ch_t* const p_info_ch);
+static void SSIF_Reset(const uint32_t ssif_ch);
+
+static const uint32_t gb_cpg_stbcr_bit[SSIF_NUM_CHANS] =
+{
+    CPG_STBCR11_BIT_MSTP115,    /* SSIF0 */
+    CPG_STBCR11_BIT_MSTP114,    /* SSIF1 */
+    CPG_STBCR11_BIT_MSTP113,    /* SSIF2 */
+    CPG_STBCR11_BIT_MSTP112,    /* SSIF3 */
+    CPG_STBCR11_BIT_MSTP111,    /* SSIF4 */
+    CPG_STBCR11_BIT_MSTP110     /* SSIF5 */
+};
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)                       
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: SSIF_Initialise
+* @brief         Initialize the SSIF driver's internal data
+*
+*                Description:<br>
+*                
+* @param[in]     p_cfg_data :pointer of several parameters array per channels
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+#if(1) /* mbed */
+int_t SSIF_InitialiseOne(const int_t channel, const ssif_channel_cfg_t* const p_cfg_data)
+{
+    int_t           ercd = ESUCCESS;
+    ssif_info_ch_t* p_info_ch;
+
+    if (NULL == p_cfg_data)
+    {
+        ercd = EFAULT;
+    }
+    else if (false == p_cfg_data->enabled)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        p_info_ch = &g_ssif_info_drv.info_ch[channel];
+        p_info_ch->channel = channel;
+        p_info_ch->enabled = p_cfg_data->enabled;
+
+        /* copy config data to channel info */
+        ercd = SSIF_UpdateChannelConfig(p_info_ch, p_cfg_data);
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = SSIF_InitChannel(p_info_ch);
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            SSIF_InterruptInit(channel, p_cfg_data->int_level);
+        }
+    }
+
+    return ercd;
+}
+
+#else
+int_t SSIF_Initialise(const ssif_channel_cfg_t* const p_cfg_data)
+{
+    uint32_t        ssif_ch;
+    int_t           ercd = ESUCCESS;
+    ssif_info_ch_t* p_info_ch;
+
+    if (NULL == p_cfg_data)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        for (ssif_ch = 0; (ssif_ch < SSIF_NUM_CHANS) && (ESUCCESS == ercd); ssif_ch++)
+        {
+            p_info_ch = &g_ssif_info_drv.info_ch[ssif_ch];
+            p_info_ch->channel = ssif_ch;
+            p_info_ch->enabled = p_cfg_data[ssif_ch].enabled;
+            
+            if (false != p_info_ch->enabled)
+            {
+                /* copy config data to channel info */
+                ercd = SSIF_UpdateChannelConfig(p_info_ch, &p_cfg_data[ssif_ch]);
+
+                if (ESUCCESS == ercd)
+                {
+                    ercd = SSIF_InitChannel(p_info_ch);
+                }
+            }
+        } 
+
+        if (ESUCCESS == ercd)
+        {
+            for (ssif_ch = 0; ssif_ch < SSIF_NUM_CHANS; ssif_ch++)
+            {
+                p_info_ch = &g_ssif_info_drv.info_ch[ssif_ch];
+
+                if (false != p_info_ch->enabled)
+                {
+                    SSIF_InterruptInit(ssif_ch, p_cfg_data[ssif_ch].int_level);
+                }
+            }
+        }
+    }
+
+    return ercd;
+}
+#endif
+
+/******************************************************************************
+* Function Name: SSIF_UnInitialise
+* @brief         UnInitialize the SSIF driver's internal data
+*
+*                Description:<br>
+*                
+* @param         none
+* @retval        ESUCCESS   :Success.
+******************************************************************************/
+#if(1) /* mbed */
+int_t SSIF_UnInitialiseOne(const int_t channel)
+{
+    const int_t     ercd = ESUCCESS;
+    ssif_info_ch_t* p_info_ch;
+
+    p_info_ch = &g_ssif_info_drv.info_ch[channel];
+
+    if (false != p_info_ch->enabled)
+    {
+        SSIF_UnInitChannel(p_info_ch);
+    }
+
+    return ercd;
+}
+#else
+int_t SSIF_UnInitialise(void)
+{
+    uint32_t        ssif_ch;
+    const int_t     ercd = ESUCCESS;
+    ssif_info_ch_t* p_info_ch;
+
+    for (ssif_ch = 0; ssif_ch < SSIF_NUM_CHANS; ssif_ch++)
+    {
+        p_info_ch = &g_ssif_info_drv.info_ch[ssif_ch];
+
+        if (false != p_info_ch->enabled)
+        {
+            SSIF_UnInitChannel(p_info_ch);
+        }
+    }
+
+    return ercd;
+}
+#endif
+
+/******************************************************************************
+* Function Name: SSIF_EnableChannel
+* @brief         Enable the SSIF channel
+*
+*                Description:<br>
+*                
+* @param[in,out] p_info_ch  :channel object
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_EnableChannel(ssif_info_ch_t* const p_info_ch)
+{
+    int_t ercd = ESUCCESS;
+    int_t was_masked;
+    uint32_t ssif_ch;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (ssif_ch >= SSIF_NUM_CHANS)
+        {
+            ercd = EFAULT;
+        }
+        else 
+        {
+            /* check channel open flag(duplex) */
+            if ((O_RDWR == p_info_ch->openflag)
+                && (false == p_info_ch->is_full_duplex))
+            {
+                ercd = EINVAL;
+            }
+
+            /* check channel open flag(romdec direct input) */
+            if (ESUCCESS == ercd)
+            {
+                if ((O_RDONLY != p_info_ch->openflag)
+                    && (SSIF_CFG_ENABLE_ROMDEC_DIRECT
+                        == p_info_ch->romdec_direct.mode))
+                {
+                    ercd = EINVAL;
+                }
+            }
+
+            /* enable the SSIF clock */
+            if (ESUCCESS == ercd)
+            {
+                was_masked = __disable_irq();
+
+                /* ->IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on writing to 8bit register. */
+                CPGSTBCR11 &= (uint8_t)~((uint8_t)gb_cpg_stbcr_bit[ssif_ch]);
+                /* <-IPA R2.4.2 */
+
+                if (0 == was_masked)
+                {
+                    __enable_irq();
+                }
+            }
+
+            /* configure channel hardware */
+            if (ESUCCESS == ercd)
+            {
+                /* software reset */
+                SSIF_Reset(ssif_ch);
+
+                /* Set control parameters */
+                ercd = SSIF_SetCtrlParams(p_info_ch);
+            }
+
+            /* allocate and setup/start DMA transfer */
+            if (ESUCCESS == ercd)
+            {
+                ercd = SSIF_InitDMA(p_info_ch);
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_DisableChannel
+* @brief         Disable the SSIF channel
+*
+*                Description:<br>
+*                
+* @param[in,out] p_info_ch  :channel object
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_DisableChannel(ssif_info_ch_t* const p_info_ch)
+{
+    uint32_t dummy_read;
+    int_t   was_masked;
+    int_t   ret = ESUCCESS;
+    uint32_t ssif_ch;
+
+    if (NULL == p_info_ch)
+    {
+        ret = EFAULT;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (ssif_ch >= SSIF_NUM_CHANS)
+        {
+            ret = EFAULT;
+        }
+        else
+        {
+            SSIF_DisableErrorInterrupt(ssif_ch);
+
+            /* TEN and REN are disable */
+            g_ssireg[ssif_ch]->SSICR &= ~(SSIF_CR_BIT_TEN | SSIF_CR_BIT_REN);
+
+            /* Reset FIFO */
+            g_ssireg[ssif_ch]->SSIFCR |= (SSIF_FCR_BIT_TFRST | SSIF_FCR_BIT_RFRST);
+            dummy_read = g_ssireg[ssif_ch]->SSIFCR;
+            UNUSED_ARG(dummy_read);
+            g_ssireg[ssif_ch]->SSIFCR &= ~(SSIF_FCR_BIT_TFRST | SSIF_FCR_BIT_RFRST);
+
+            /* free DMA resources */
+            SSIF_UnInitDMA(p_info_ch);
+
+            /* clear status reg */
+            g_ssireg[ssif_ch]->SSISR = 0u; /* ALL CLEAR */
+
+            /* disable ssif clock */
+            was_masked = __disable_irq();
+
+            /* ->IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on writing to 8bit register. */
+            CPGSTBCR11 |= (uint8_t)gb_cpg_stbcr_bit[ssif_ch];
+            /* <-IPA R2.4.2 */
+
+            if (0 == was_masked)
+            {
+                __enable_irq();
+            }
+
+            /* cancel event to ongoing request */
+            if (NULL != p_info_ch->p_aio_tx_curr)
+            {
+                p_info_ch->p_aio_tx_curr->aio_return = ECANCELED;
+                ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_curr);
+                p_info_ch->p_aio_tx_curr = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_tx_next)
+            {
+                p_info_ch->p_aio_tx_next->aio_return = ECANCELED;
+                ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_next);
+                p_info_ch->p_aio_tx_next = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_rx_curr)
+            {
+                p_info_ch->p_aio_rx_curr->aio_return = ECANCELED;
+                ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_curr);
+                p_info_ch->p_aio_rx_curr = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_rx_next)
+            {
+                p_info_ch->p_aio_rx_next->aio_return = ECANCELED;
+                ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_next);
+                p_info_ch->p_aio_rx_next = NULL;
+            }
+        }
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_ErrorRecovery
+* @brief         Restart the SSIF channel
+*
+*                Description:<br>
+*                When normal mode<br>
+*                  Stop and restart DMA transfer.<br>
+*                When ROMDEC direct input mode<br>
+*                  Stop DMA transfer, and execute callback function.<br>
+*                Note: This function execute in interrupt context.
+* @param[in,out] p_info_ch  :channel object
+* @retval        none
+******************************************************************************/
+void SSIF_ErrorRecovery(ssif_info_ch_t* const p_info_ch)
+{
+    uint32_t dummy_read;
+    int_t   ercd = ESUCCESS;
+    uint32_t ssif_ch;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (ssif_ch >= SSIF_NUM_CHANS)
+        {
+            ercd = EFAULT;
+        }
+        else
+        {
+            /* disable DMA end interrupt */
+            g_ssireg[ssif_ch]->SSIFCR &= ~((uint32_t)SSIF_FCR_BIT_TIE | SSIF_FCR_BIT_RIE);
+
+            SSIF_DisableErrorInterrupt(ssif_ch);
+
+            /* TEN and REN are disable */
+            g_ssireg[ssif_ch]->SSICR &= ~(SSIF_CR_BIT_TEN | SSIF_CR_BIT_REN);
+
+            /* Reset FIFO */
+            g_ssireg[ssif_ch]->SSIFCR |= (SSIF_FCR_BIT_TFRST | SSIF_FCR_BIT_RFRST);
+            dummy_read = g_ssireg[ssif_ch]->SSIFCR;
+            UNUSED_ARG(dummy_read);
+            g_ssireg[ssif_ch]->SSIFCR &= ~(SSIF_FCR_BIT_TFRST | SSIF_FCR_BIT_RFRST);
+
+            /* pause DMA transfer */
+            SSIF_CancelDMA(p_info_ch);
+
+            /* clear status reg */
+            g_ssireg[ssif_ch]->SSISR = 0u; /* ALL CLEAR */
+
+            /* cancel event to ongoing request */
+            if (NULL != p_info_ch->p_aio_tx_curr)
+            {
+                p_info_ch->p_aio_tx_curr->aio_return = EIO;
+                ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_curr);
+                p_info_ch->p_aio_tx_curr = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_tx_next)
+            {
+                p_info_ch->p_aio_tx_next->aio_return = EIO;
+                ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_next);
+                p_info_ch->p_aio_tx_next = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_rx_curr)
+            {
+                p_info_ch->p_aio_rx_curr->aio_return = EIO;
+                ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_curr);
+                p_info_ch->p_aio_rx_curr = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_rx_next)
+            {
+                p_info_ch->p_aio_rx_next->aio_return = EIO;
+                ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_next);
+                p_info_ch->p_aio_rx_next = NULL;
+            }
+        }
+
+        /* configure channel hardware */
+        if (ESUCCESS == ercd)
+        {
+            /* software reset */
+            SSIF_Reset(ssif_ch);
+
+            /* Set control parameters */
+            ercd = SSIF_SetCtrlParams(p_info_ch);
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            if (SSIF_CFG_ENABLE_ROMDEC_DIRECT
+                != p_info_ch->romdec_direct.mode)
+            {
+                /* setup/restart DMA transfer */
+                ercd = SSIF_RestartDMA(p_info_ch);
+            }
+            else
+            {
+                /* execute callback function */
+                if (NULL != p_info_ch->romdec_direct.p_cbfunc)
+                {
+                    (*p_info_ch->romdec_direct.p_cbfunc)();
+                }
+            }
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        /* NON_NOTICE_ASSERT: cannot restart channel */
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_PostAsyncIo
+* @brief         Enqueue asynchronous read/write request
+*
+*                Description:<br>
+*                
+* @param[in,out] p_info_ch  :channel object
+* @param[in,out] p_aio      :aio control block of read/write request
+* @retval        none
+******************************************************************************/
+void SSIF_PostAsyncIo(ssif_info_ch_t* const p_info_ch, AIOCB* const p_aio)
+{
+    if ((NULL == p_info_ch) || (NULL == p_aio))
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        if (SSIF_ASYNC_W == p_aio->aio_return)
+        {
+            ahf_addtail(&p_info_ch->tx_que, p_aio);
+        }
+        else if (SSIF_ASYNC_R == p_aio->aio_return)
+        {
+            ahf_addtail(&p_info_ch->rx_que, p_aio);
+        }
+        else
+        {
+            /* NON_NOTICE_ASSERT: illegal request type */
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_PostAsyncCancel
+* @brief         Cancel read or write request(s)
+*
+*                Description:<br>
+*                
+* @param[in,out] p_info_ch  :channel object
+* @param[in,out] p_aio      :aio control block to cancel or NULL to cancel all.
+* @retval        none
+******************************************************************************/
+void SSIF_PostAsyncCancel(ssif_info_ch_t* const p_info_ch, AIOCB* const p_aio)
+{
+    int32_t ioif_ret;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        if (NULL == p_aio)
+        {
+            ahf_cancelall(&p_info_ch->tx_que);
+            ahf_cancelall(&p_info_ch->rx_que);
+        }
+        else
+        {
+            ioif_ret = ahf_cancel(&p_info_ch->tx_que, p_aio);
+            if (ESUCCESS != ioif_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected aioif error */
+            }
+
+            ioif_ret = ahf_cancel(&p_info_ch->rx_que, p_aio);
+            if (ESUCCESS != ioif_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected aioif error */
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_IOCTL_ConfigChannel
+* @brief         Save configuration to the SSIF driver.
+*
+*                Description:<br>
+*                Update channel object.
+* @param[in,out] p_info_ch  :channel object
+* @param[in]     p_ch_cfg   :SSIF channel configuration parameter
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_IOCTL_ConfigChannel(ssif_info_ch_t* const p_info_ch,
+                                const ssif_channel_cfg_t* const p_ch_cfg)
+{
+    int_t    ercd;
+
+    if ((NULL == p_info_ch) || (NULL == p_ch_cfg))
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        /* stop DMA transfer */
+        ercd = SSIF_DisableChannel(p_info_ch);
+
+        if (ESUCCESS == ercd)
+        {
+            /* copy config data to channel info */
+            ercd = SSIF_UpdateChannelConfig(p_info_ch, p_ch_cfg);
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            /* restart DMA transfer */
+            ercd = SSIF_EnableChannel(p_info_ch);
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_IOCTL_GetStatus
+* @brief         Get a value of SSISR register.
+*
+*                Description:<br>
+*                
+* @param[in]     p_info_ch  :channel object
+* @param[in,out] p_status   :pointer of status value
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_IOCTL_GetStatus(const ssif_info_ch_t* const p_info_ch, uint32_t* const p_status)
+{
+    int_t ret = ESUCCESS;
+
+    if ((NULL == p_info_ch) || (NULL == p_status))
+    {
+        ret = EFAULT;
+    }
+    else
+    {
+        *p_status = g_ssireg[p_info_ch->channel]->SSISR;
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_SWLtoLen
+* @brief         Convert SSICR:SWL bits to system word length
+*
+*                Description:<br>
+*                
+* @param[in]     ssicr_swl  :SSICR register SWL field value(0 to 7)
+* @retval        8 to 256   :system word length(byte)
+******************************************************************************/
+int_t SSIF_SWLtoLen(const ssif_chcfg_system_word_t ssicr_swl)
+{
+    /* -> IPA M1.10.1 : This is conversion table that can't be macro-coding. */
+    static const int_t decode_enum_swl[SSIF_CFG_SYSTEM_WORD_256+1] = {
+        8,      /* SSIF_CFG_SYSTEM_WORD_8   */
+        16,     /* SSIF_CFG_SYSTEM_WORD_16  */
+        24,     /* SSIF_CFG_SYSTEM_WORD_24  */
+        32,     /* SSIF_CFG_SYSTEM_WORD_32  */
+        48,     /* SSIF_CFG_SYSTEM_WORD_48  */
+        64,     /* SSIF_CFG_SYSTEM_WORD_64  */
+        128,    /* SSIF_CFG_SYSTEM_WORD_128 */
+        256     /* SSIF_CFG_SYSTEM_WORD_256 */
+    };
+    /* <- IPA M1.10.1 */
+
+    return decode_enum_swl[ssicr_swl];
+}
+
+/******************************************************************************
+* Function Name: SSIF_DWLtoLen
+* @brief         Convert SSICR:DWL bits to data word length
+*
+*                Description:<br>
+*                
+* @param[in]     ssicr_dwl  :SSICR register DWL field value(0 to 6)
+* @retval        8 to 32    :data word length(byte)
+******************************************************************************/
+int_t SSIF_DWLtoLen(const ssif_chcfg_data_word_t ssicr_dwl)
+{
+    /* -> IPA M1.10.1 : This is conversion table that can't be macro-coding. */
+    static const int_t decode_enum_dwl[SSIF_CFG_DATA_WORD_32+1] = {
+        8,   /* SSIF_CFG_DATA_WORD_8  */
+        16,  /* SSIF_CFG_DATA_WORD_16 */
+        18,  /* SSIF_CFG_DATA_WORD_18 */
+        20,  /* SSIF_CFG_DATA_WORD_20 */
+        22,  /* SSIF_CFG_DATA_WORD_22 */
+        24,  /* SSIF_CFG_DATA_WORD_24 */
+        32   /* SSIF_CFG_DATA_WORD_32 */
+    };
+    /* <- IPA M1.10.1 */
+
+    return decode_enum_dwl[ssicr_dwl];
+}
+
+/******************************************************************************
+Private functions                                                               
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: SSIF_InitChannel
+* @brief         Initialize for the SSIF channel
+*
+*                Description:<br>
+*                Create semaphore and queue for channel.<br>
+*                And setup SSIF pin.
+* @param[in,out] p_info_ch  :channel object
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+static int_t SSIF_InitChannel(ssif_info_ch_t* const p_info_ch)
+{
+    int32_t os_ret;
+    uint32_t ssif_ch;
+    int_t ercd = ESUCCESS;
+    static const osSemaphoreDef_t* semdef_access[SSIF_NUM_CHANS] =
+    {
+        osSemaphore(ssif_ch0_access),
+        osSemaphore(ssif_ch1_access),
+        osSemaphore(ssif_ch2_access),
+        osSemaphore(ssif_ch3_access),
+        osSemaphore(ssif_ch4_access),
+        osSemaphore(ssif_ch5_access)
+    };
+    static const bool_t is_duplex_ch[SSIF_NUM_CHANS] =
+    {
+        true,   /* SSIF0 is full duplex channel */
+        true,   /* SSIF1 is full duplex channel */
+        false,  /* SSIF2 is half duplex channel */
+        true,   /* SSIF3 is full duplex channel */
+        false,  /* SSIF4 is half duplex channel */
+        true    /* SSIF5 is full duplex channel */
+    };
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        p_info_ch->is_full_duplex = is_duplex_ch[ssif_ch];
+
+        /* Create sem_access semaphore */
+        p_info_ch->sem_access = osSemaphoreCreate(semdef_access[ssif_ch], 1);
+
+        if (NULL == p_info_ch->sem_access)
+        {
+            ercd = ENOMEM;
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = ahf_create(&p_info_ch->tx_que, AHF_LOCKINT);
+            if (ESUCCESS != ercd)
+            {
+                ercd = ENOMEM;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = ahf_create(&p_info_ch->rx_que, AHF_LOCKINT);
+            if (ESUCCESS != ercd)
+            {
+                ercd = ENOMEM;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            /* set channel initialize */
+            p_info_ch->openflag = 0;
+
+            p_info_ch->p_aio_tx_curr = NULL;       /* tx request pointer */
+            p_info_ch->p_aio_tx_next = NULL;       /* tx request pointer */
+            p_info_ch->p_aio_rx_curr = NULL;       /* rx request pointer */
+            p_info_ch->p_aio_rx_next = NULL;       /* rx request pointer */
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = R_SSIF_Userdef_InitPinMux(ssif_ch);
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            p_info_ch->ch_stat = SSIF_CHSTS_INIT;
+        }
+        else
+        {
+            if (NULL != p_info_ch->sem_access)
+            {
+                os_ret = osSemaphoreDelete(p_info_ch->sem_access);
+                if (osOK != os_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected semaphore error */
+                }
+                p_info_ch->sem_access = NULL;
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_UnInitChannel
+* @brief         Uninitialise the SSIF channel.
+*
+*                Description:<br>
+*                
+* @param[in,out] p_info_ch  :channel object
+* @retval        none
+******************************************************************************/
+static void SSIF_UnInitChannel(ssif_info_ch_t* const p_info_ch)
+{
+    int32_t os_ret;
+    int_t was_masked;
+    uint32_t ssif_ch;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (SSIF_CHSTS_INIT != p_info_ch->ch_stat)
+        {
+            /* NON_NOTICE_ASSERT: unexpected channel status */
+        }
+
+        p_info_ch->ch_stat = SSIF_CHSTS_UNINIT;
+
+        SSIF_DisableErrorInterrupt(ssif_ch);
+
+        was_masked = __disable_irq();
+
+        /* delete the tx queue */
+        ahf_cancelall(&p_info_ch->tx_que);
+        ahf_destroy(&p_info_ch->tx_que);
+
+        /* delete the rx queue */
+        ahf_cancelall(&p_info_ch->rx_que);
+        ahf_destroy(&p_info_ch->rx_que);
+
+        /* delete the private semaphore */
+        os_ret = osSemaphoreDelete(p_info_ch->sem_access);
+        if (osOK != os_ret)
+        {
+            /* NON_NOTICE_ASSERT: unexpected semaphore error */
+        }
+
+        SSIF_InterruptShutdown(ssif_ch);
+
+        if (0 == was_masked)
+        {
+            __enable_irq();
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_UpdateChannelConfig
+* @brief         Save configuration to the SSIF driver.
+*
+*                Description:<br>
+*                Update channel object.
+* @param[in,out] p_info_ch  :channel object
+* @param[in]     p_ch_cfg   :SSIF channel configuration parameter
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+static int_t SSIF_UpdateChannelConfig(ssif_info_ch_t* const p_info_ch,
+                                      const ssif_channel_cfg_t* const p_ch_cfg)
+{
+    int_t ercd;
+
+    if ((NULL == p_info_ch) || (NULL == p_ch_cfg))
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        ercd = SSIF_CheckChannelCfg(p_ch_cfg);
+
+        if (ESUCCESS == ercd)
+        {
+            p_info_ch->slave_mode = p_ch_cfg->slave_mode;
+
+            if (false != p_info_ch->slave_mode)
+            {
+                /* slave mode */
+                p_info_ch->clock_direction = SSIF_CFG_CLOCK_IN;
+                p_info_ch->ws_direction = SSIF_CFG_WS_IN;
+            }
+            else
+            {
+                /* master mode */
+                p_info_ch->clock_direction = SSIF_CFG_CLOCK_OUT;
+                p_info_ch->ws_direction = SSIF_CFG_WS_OUT;
+
+                /* when master mode, always disable noise cancel */
+                p_info_ch->noise_cancel = SSIF_CFG_DISABLE_NOISE_CANCEL;
+            }
+
+            p_info_ch->sample_freq        = p_ch_cfg->sample_freq;
+
+            p_info_ch->clk_select         = p_ch_cfg->clk_select;
+            p_info_ch->multi_ch           = p_ch_cfg->multi_ch;
+            p_info_ch->data_word          = p_ch_cfg->data_word;
+            p_info_ch->system_word        = p_ch_cfg->system_word;
+            p_info_ch->bclk_pol           = p_ch_cfg->bclk_pol;
+            p_info_ch->ws_pol             = p_ch_cfg->ws_pol;
+            p_info_ch->padding_pol        = p_ch_cfg->padding_pol;
+            p_info_ch->serial_alignment   = p_ch_cfg->serial_alignment;
+            p_info_ch->parallel_alignment = p_ch_cfg->parallel_alignment;
+            p_info_ch->ws_delay           = p_ch_cfg->ws_delay;
+            p_info_ch->noise_cancel       = p_ch_cfg->noise_cancel;
+            p_info_ch->tdm_mode           = p_ch_cfg->tdm_mode;
+            p_info_ch->romdec_direct.mode     = p_ch_cfg->romdec_direct.mode;
+            p_info_ch->romdec_direct.p_cbfunc = p_ch_cfg->romdec_direct.p_cbfunc;
+
+            if (SSIF_CFG_ENABLE_TDM == p_info_ch->tdm_mode)
+            {
+                /* check combination of parameters */
+                if ((SSIF_CFG_MULTI_CH_1 == p_info_ch->multi_ch)
+                    || (SSIF_CFG_WS_HIGH == p_info_ch->ws_pol))
+                {
+                    ercd = EINVAL;
+                }
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = SSIF_CheckWordSize(p_info_ch);
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            if (false == p_info_ch->slave_mode)
+            {
+                /* Master: call user own clock setting function */
+                ercd = R_SSIF_Userdef_SetClockDiv(p_ch_cfg, &p_info_ch->clk_div);
+            }
+            else
+            {
+                /* Slave: set dummy value for clear */
+                p_info_ch->clk_div = SSIF_CFG_CKDV_BITS_1;
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_SetCtrlParams
+* @brief         Set SSIF configuration to hardware.
+*
+*                Description:<br>
+*                Update SSICR register.
+* @param[in]     p_info_ch  :channel object
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+static int_t SSIF_SetCtrlParams(const ssif_info_ch_t* const p_info_ch)
+{
+    int_t ret = ESUCCESS;
+    int_t was_masked;
+    uint32_t ssif_ch;
+    static const uint32_t gpio_sncr_bit[SSIF_NUM_CHANS] =
+    {
+        GPIO_SNCR_BIT_SSI0NCE,  /* SSIF0 */
+        GPIO_SNCR_BIT_SSI1NCE,  /* SSIF1 */
+        GPIO_SNCR_BIT_SSI2NCE,  /* SSIF2 */
+        GPIO_SNCR_BIT_SSI3NCE,  /* SSIF3 */
+        GPIO_SNCR_BIT_SSI4NCE,  /* SSIF4 */
+        GPIO_SNCR_BIT_SSI5NCE   /* SSIF5 */
+    };
+
+    if (NULL == p_info_ch)
+    {
+        ret = EFAULT;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        /* ALL CLEAR */
+        g_ssireg[ssif_ch]->SSICR = 0u;
+        g_ssireg[ssif_ch]->SSISR = 0u;
+        g_ssireg[ssif_ch]->SSIFCCR = 0u;
+
+        g_ssireg[ssif_ch]->SSICR = (uint32_t)(
+             ((uint32_t)(p_info_ch->clk_select)         << SSIF_CR_SHIFT_CKS) |
+             ((uint32_t)(p_info_ch->multi_ch)           << SSIF_CR_SHIFT_CHNL) |
+             ((uint32_t)(p_info_ch->data_word)          << SSIF_CR_SHIFT_DWL) |
+             ((uint32_t)(p_info_ch->system_word)        << SSIF_CR_SHIFT_SWL) |
+             ((uint32_t)(p_info_ch->bclk_pol)           << SSIF_CR_SHIFT_SCKP) |
+             ((uint32_t)(p_info_ch->ws_pol)             << SSIF_CR_SHIFT_SWSP) |
+             ((uint32_t)(p_info_ch->padding_pol)        << SSIF_CR_SHIFT_SPDP) |
+             ((uint32_t)(p_info_ch->serial_alignment)   << SSIF_CR_SHIFT_SDTA) |
+             ((uint32_t)(p_info_ch->parallel_alignment) << SSIF_CR_SHIFT_PDTA) |
+             ((uint32_t)(p_info_ch->ws_delay)           << SSIF_CR_SHIFT_DEL) |
+             ((uint32_t)(p_info_ch->clock_direction)    << SSIF_CR_SHIFT_SCKD) |
+             ((uint32_t)(p_info_ch->ws_direction)       << SSIF_CR_SHIFT_SWSD) |
+             ((uint32_t)(p_info_ch->clk_div)            << SSIF_CR_SHIFT_CKDV)
+             );
+
+        g_ssireg[ssif_ch]->SSITDMR = ((uint32_t)(p_info_ch->tdm_mode) << SSIF_TDMR_SHIFT_TDM);
+
+        /* change SNCR register: enter exclusive */
+        was_masked = __disable_irq();
+
+        if ((SSIF_CFG_ENABLE_NOISE_CANCEL == p_info_ch->noise_cancel)
+            && (false != p_info_ch->slave_mode))
+        {
+            /* ENABLE_NOISE_CANCEL && slave mode */
+            GPIO.SNCR |= (uint32_t)gpio_sncr_bit[ssif_ch];
+        }
+        else
+        {
+            /* DISABLE_NOISE_CANCEL || master mode */
+            GPIO.SNCR &= ~((uint32_t)gpio_sncr_bit[ssif_ch]);
+        }
+
+        /* change SNCR register: exit exclusive */
+        if (0 == was_masked)
+        {
+            __enable_irq();
+        }
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_CheckChannelCfg
+* @brief         Check channel configuration parameters are valid or not.
+*
+*                Description:<br>
+*                
+* @param[in]     p_ch_cfg     :channel configuration
+* @retval        ESUCCESS     :Success.
+* @retval        error code   :Failure.
+******************************************************************************/
+static int_t SSIF_CheckChannelCfg(const ssif_channel_cfg_t* const p_ch_cfg)
+{
+    int_t ret = ESUCCESS;
+
+    if (NULL == p_ch_cfg)
+    {
+        ret = EFAULT;
+    }
+    else
+    {
+        switch (p_ch_cfg->clk_select)
+        {
+        case SSIF_CFG_CKS_AUDIO_X1:
+            /* fall through */
+        case SSIF_CFG_CKS_AUDIO_CLK:
+            /* do nothing */
+            break;
+        default:
+            ret = EINVAL;
+            break;
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->multi_ch)
+            {
+            case SSIF_CFG_MULTI_CH_1:
+                /* fall through */
+            case SSIF_CFG_MULTI_CH_2:
+                /* fall through */
+            case SSIF_CFG_MULTI_CH_3:
+                /* fall through */
+            case SSIF_CFG_MULTI_CH_4:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->data_word)
+            {
+            case SSIF_CFG_DATA_WORD_8:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_16:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_18:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_20:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_22:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_24:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_32:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->system_word)
+            {
+            case SSIF_CFG_SYSTEM_WORD_8:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_16:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_24:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_32:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_48:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_64:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_128:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_256:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->bclk_pol)
+            {
+            case SSIF_CFG_FALLING:
+                /* fall through */
+            case SSIF_CFG_RISING:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->ws_pol)
+            {
+            case SSIF_CFG_WS_LOW:
+                /* fall through */
+            case SSIF_CFG_WS_HIGH:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->padding_pol)
+            {
+            case SSIF_CFG_PADDING_LOW:
+                /* fall through */
+            case SSIF_CFG_PADDING_HIGH:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->serial_alignment)
+            {
+            case SSIF_CFG_DATA_FIRST:
+                /* fall through */
+            case SSIF_CFG_PADDING_FIRST:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->parallel_alignment)
+            {
+            case SSIF_CFG_LEFT:
+                /* fall through */
+            case SSIF_CFG_RIGHT:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->ws_delay)
+            {
+            case SSIF_CFG_DELAY:
+                /* fall through */
+            case SSIF_CFG_NO_DELAY:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->noise_cancel)
+            {
+            case SSIF_CFG_DISABLE_NOISE_CANCEL:
+                /* fall through */
+            case SSIF_CFG_ENABLE_NOISE_CANCEL:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->tdm_mode)
+            {
+            case SSIF_CFG_DISABLE_TDM:
+                /* fall through */
+            case SSIF_CFG_ENABLE_TDM:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->romdec_direct.mode)
+            {
+            case SSIF_CFG_DISABLE_ROMDEC_DIRECT:
+                /* fall through */
+            case SSIF_CFG_ENABLE_ROMDEC_DIRECT:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_CheckWordSize
+* @brief         Check system word size whether that is valid or not.
+*
+*                Description:<br>
+*                if system_words couldn't involve specified number of<br>
+*                data_words then error.
+* @param[in]     p_info_ch    :channel object
+* @retval        ESUCCESS     :Success.
+* @retval        error code   :Failure.
+******************************************************************************/
+static int_t SSIF_CheckWordSize(const ssif_info_ch_t* const p_info_ch)
+{
+    uint32_t ssicr_chnl;
+    uint32_t dw_per_sw;
+    uint32_t datawd_len;
+    uint32_t syswd_len;
+    int_t ret = ESUCCESS;
+
+    if (NULL == p_info_ch)
+    {
+        ret = EFAULT;
+    }
+    else
+    {
+        ssicr_chnl = p_info_ch->multi_ch;
+        /* ->MISRA 13.7 : This is verbose error check by way of precaution */
+        if (SSIF_CFG_MULTI_CH_4 < ssicr_chnl)
+        /* <-MISRA 13.7 */
+        {
+            ret = EINVAL;
+        }
+        else
+        {
+            /* data_words number per system_words */
+            if (SSIF_CFG_ENABLE_TDM == p_info_ch->tdm_mode)
+            {
+                /* When TDM Mode data_word number per system_words fixed to 1 */
+                dw_per_sw = 1u;
+            }
+            else
+            {
+                /* When not TDM data_word number per system_words depends CHNL */
+                dw_per_sw = ssicr_chnl + 1u;
+            }
+
+            /* size of data_words */
+            datawd_len = (uint32_t)SSIF_DWLtoLen(p_info_ch->data_word);
+
+            if (0u == datawd_len)
+            {
+                ret = EINVAL;
+            }
+            else
+            {
+                /* size of system_words */
+                syswd_len = (uint32_t)SSIF_SWLtoLen(p_info_ch->system_word);
+
+                if (syswd_len < (datawd_len * dw_per_sw))
+                {
+                    ret = EINVAL;
+                }
+            }
+        }
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_Reset
+* @brief         SSIF software reset
+*
+*                Description:<br>
+*                
+* @param[in]     ssif_ch       :SSIF channel
+* @retval        none
+******************************************************************************/
+static void SSIF_Reset(const uint32_t ssif_ch)
+{
+    int_t was_masked;
+    uint8_t dummy_read_u8;
+    static const uint32_t cpg_swrst_bit[SSIF_NUM_CHANS] =
+    {
+        CPG_SWRSTCR1_BIT_SRST16,    /* SSIF0 */
+        CPG_SWRSTCR1_BIT_SRST15,    /* SSIF1 */
+        CPG_SWRSTCR1_BIT_SRST14,    /* SSIF2 */
+        CPG_SWRSTCR1_BIT_SRST13,    /* SSIF3 */
+        CPG_SWRSTCR1_BIT_SRST12,    /* SSIF4 */
+        CPG_SWRSTCR1_BIT_SRST11     /* SSIF5 */
+    };
+
+    /* change register: enter exclusive */
+    was_masked = __disable_irq();
+
+    /* SW Reset ON */
+    /* ->IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on accessing to 8bit register. */
+    CPGSWRSTCR1 |= (uint8_t)cpg_swrst_bit[ssif_ch];
+    dummy_read_u8 = CPGSWRSTCR1;
+    /* <-IPA R2.4.2 */
+    UNUSED_ARG(dummy_read_u8);
+
+    /* SW Reset OFF */
+    /* ->IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on accessing to 8bit register. */
+    CPGSWRSTCR1 &= (uint8_t)~((uint8_t)cpg_swrst_bit[ssif_ch]);
+    dummy_read_u8 = CPGSWRSTCR1;
+    /* <-IPA R2.4.2 */
+    UNUSED_ARG(dummy_read_u8);
+
+    /* change register: exit exclusive */
+    if (0 == was_masked)
+    {
+        __enable_irq();
+    }
+
+    return;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_src/ssif/ssif.h	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,266 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/******************************************************************************
+* File Name    : ssif.h
+* $Rev: 891 $
+* $Date:: 2014-06-27 10:40:52 +0900#$
+* Description  : SSIF driver functions header
+******************************************************************************/
+
+#ifndef SSIF_H
+#define SSIF_H
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "aioif.h"
+#include "iodefine.h"
+#include "ssif_if.h"
+#include "bsp_drv_cmn.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+#define SSIF_CHNUM_0    (0u)
+#define SSIF_CHNUM_1    (1u)
+#define SSIF_CHNUM_2    (2u)
+#define SSIF_CHNUM_3    (3u)
+#define SSIF_CHNUM_4    (4u)
+#define SSIF_CHNUM_5    (5u)
+
+#define SSIF_CHSTR_0 "\\0"
+#define SSIF_CHSTR_1 "\\1"
+#define SSIF_CHSTR_2 "\\2"
+#define SSIF_CHSTR_3 "\\3"
+#define SSIF_CHSTR_4 "\\4"
+#define SSIF_CHSTR_5 "\\5"
+
+#define SSIF_MAX_PATH_LEN           (32u)
+
+#define SSIF_CR_SHIFT_CKS   (30u)
+#define SSIF_CR_SHIFT_TUIEN (29u)
+#define SSIF_CR_SHIFT_TOIEN (28u)
+#define SSIF_CR_SHIFT_RUIEN (27u)
+#define SSIF_CR_SHIFT_ROIEN (26u)
+#define SSIF_CR_SHIFT_IIEN  (25u)
+#define SSIF_CR_SHIFT_CHNL  (22u)
+#define SSIF_CR_SHIFT_DWL   (19u)
+#define SSIF_CR_SHIFT_SWL   (16u)
+#define SSIF_CR_SHIFT_SCKD  (15u)
+#define SSIF_CR_SHIFT_SWSD  (14u)
+#define SSIF_CR_SHIFT_SCKP  (13u)
+#define SSIF_CR_SHIFT_SWSP  (12u)
+#define SSIF_CR_SHIFT_SPDP  (11u)
+#define SSIF_CR_SHIFT_SDTA  (10u)
+#define SSIF_CR_SHIFT_PDTA  ( 9u)
+#define SSIF_CR_SHIFT_DEL   ( 8u)
+#define SSIF_CR_SHIFT_CKDV  ( 4u)
+#define SSIF_CR_SHIFT_MUEN  ( 3u)
+#define SSIF_CR_SHIFT_TEN   ( 1u)
+#define SSIF_CR_SHIFT_REN   ( 0u)
+
+#define SSIF_CR_BIT_CKS     (1u << SSIF_CR_SHIFT_CKS)
+#define SSIF_CR_BIT_TUIEN   (1u << SSIF_CR_SHIFT_TUIEN)
+#define SSIF_CR_BIT_TOIEN   (1u << SSIF_CR_SHIFT_TOIEN)
+#define SSIF_CR_BIT_RUIEN   (1u << SSIF_CR_SHIFT_RUIEN)
+#define SSIF_CR_BIT_ROIEN   (1u << SSIF_CR_SHIFT_ROIEN)
+#define SSIF_CR_BIT_IIEN    (1u << SSIF_CR_SHIFT_IIEN)
+#define SSIF_CR_BITS_CHNL   (3u << SSIF_CR_SHIFT_CHNL)
+#define SSIF_CR_BITS_DWL    (7u << SSIF_CR_SHIFT_DWL)
+#define SSIF_CR_BITS_SWL    (7u << SSIF_CR_SHIFT_SWL)
+#define SSIF_CR_BIT_SCKD    (1u << SSIF_CR_SHIFT_SCKD)
+#define SSIF_CR_BIT_SWSD    (1u << SSIF_CR_SHIFT_SWSD)
+#define SSIF_CR_BIT_SCKP    (1u << SSIF_CR_SHIFT_SCKP)
+#define SSIF_CR_BIT_SWSP    (1u << SSIF_CR_SHIFT_SWSP)
+#define SSIF_CR_BIT_SPDP    (1u << SSIF_CR_SHIFT_SPDP)
+#define SSIF_CR_BIT_SDTA    (1u << SSIF_CR_SHIFT_SDTA)
+#define SSIF_CR_BIT_PDTA    (1u << SSIF_CR_SHIFT_PDTA)
+#define SSIF_CR_BIT_DEL     (1u << SSIF_CR_SHIFT_DEL)
+#define SSIF_CR_BITS_CKDV   (0xfu << SSIF_CR_SHIFT_CKDV)
+#define SSIF_CR_BIT_MUEN    (1u << SSIF_CR_SHIFT_MUEN)
+#define SSIF_CR_BIT_TEN     (1u << SSIF_CR_SHIFT_TEN)
+#define SSIF_CR_BIT_REN     (1u << SSIF_CR_SHIFT_REN)
+#define SSIF_CR_INT_ERR_MASK    (SSIF_CR_BIT_TUIEN | SSIF_CR_BIT_TOIEN | SSIF_CR_BIT_RUIEN | SSIF_CR_BIT_ROIEN)
+
+#define SSIF_SR_SHIFT_TUIRQ (29u)
+#define SSIF_SR_SHIFT_TOIRQ (28u)
+#define SSIF_SR_SHIFT_RUIRQ (27u)
+#define SSIF_SR_SHIFT_ROIRQ (26u)
+#define SSIF_SR_SHIFT_IIRQ  (25u)
+#define SSIF_SR_SHIFT_IDST  ( 0u)
+
+#define SSIF_SR_BIT_TUIRQ   (1u << SSIF_SR_SHIFT_TUIRQ)
+#define SSIF_SR_BIT_TOIRQ   (1u << SSIF_SR_SHIFT_TOIRQ)
+#define SSIF_SR_BIT_RUIRQ   (1u << SSIF_SR_SHIFT_RUIRQ)
+#define SSIF_SR_BIT_ROIRQ   (1u << SSIF_SR_SHIFT_ROIRQ)
+#define SSIF_SR_BIT_IIRQ    (1u << SSIF_SR_SHIFT_IIRQ)
+#define SSIF_SR_BIT_IDST    (1u << SSIF_SR_SHIFT_IDST)
+#define SSIF_SR_INT_ERR_MASK    (SSIF_SR_BIT_TUIRQ | SSIF_SR_BIT_TOIRQ | SSIF_SR_BIT_RUIRQ | SSIF_SR_BIT_ROIRQ)
+
+#define SSIF_FCR_SHIFT_TIE      (3u)
+#define SSIF_FCR_SHIFT_RIE      (2u)
+#define SSIF_FCR_SHIFT_TFRST    (1u)
+#define SSIF_FCR_SHIFT_RFRST    (0u)
+
+#define SSIF_FCR_BIT_TIE   (1u << SSIF_FCR_SHIFT_TIE)
+#define SSIF_FCR_BIT_RIE   (1u << SSIF_FCR_SHIFT_RIE)
+#define SSIF_FCR_BIT_TFRST (1u << SSIF_FCR_SHIFT_TFRST)
+#define SSIF_FCR_BIT_RFRST (1u << SSIF_FCR_SHIFT_RFRST)
+
+#define SSIF_TDMR_SHIFT_CONT    (8u)
+#define SSIF_TDMR_SHIFT_TDM     (0u)
+
+#define SSIF_TDMR_BIT_CONT (1u << SSIF_TDMR_SHIFT_CONT)
+#define SSIF_TDMR_BIT_TDM  (1u << SSIF_TDMR_SHIFT_TDM)
+
+/* noise canceled bit */
+#define GPIO_SNCR_BIT_SSI5NCE  (1u << 5)
+#define GPIO_SNCR_BIT_SSI4NCE  (1u << 4)
+#define GPIO_SNCR_BIT_SSI3NCE  (1u << 3)
+#define GPIO_SNCR_BIT_SSI2NCE  (1u << 2)
+#define GPIO_SNCR_BIT_SSI1NCE  (1u << 1)
+#define GPIO_SNCR_BIT_SSI0NCE  (1u << 0)
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+typedef enum {
+    SSIF_DRVSTS_UNINIT = 0,
+    SSIF_DRVSTS_INIT
+} ssif_drv_stat_t;
+
+typedef enum
+{
+    SSIF_CHSTS_UNINIT = 0,
+    SSIF_CHSTS_INIT,
+    SSIF_CHSTS_OPEN
+} ssif_ch_stat_t;
+
+typedef enum
+{
+    SSIF_ASYNC_W = 0,
+    SSIF_ASYNC_R
+} ssif_rw_mode_t;
+
+/** Serial bit clock direction */
+typedef enum
+{
+    SSIF_CFG_CLOCK_IN  = 0,  /**< Clock IN - Slave mode */
+    SSIF_CFG_CLOCK_OUT = 1   /**< Clock OUT - Master mode */
+} ssif_chcfg_clock_dir_t;
+
+
+/** Serial word select direction */
+typedef enum
+{
+    SSIF_CFG_WS_IN  = 0,     /**< Word select IN - Slave mode */
+    SSIF_CFG_WS_OUT = 1      /**< Word select OUT - Master mode */
+} ssif_chcfg_ws_dir_t;
+
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+typedef struct ssif_info_ch
+{
+    uint32_t    channel;
+    bool_t      enabled;
+    bool_t      slave_mode;
+    uint32_t    sample_freq;
+    ssif_ch_stat_t ch_stat;
+    osSemaphoreId  sem_access;
+    AHF_S       tx_que;
+    AHF_S       rx_que;
+    int_t       dma_rx_ch;
+    int_t       dma_tx_ch;
+    bool_t      is_full_duplex;         /* full/half duplex */
+    int_t       openflag;
+    AIOCB*      p_aio_tx_curr;
+    AIOCB*      p_aio_tx_next;
+    AIOCB*      p_aio_rx_curr;
+    AIOCB*      p_aio_rx_next;
+    ssif_chcfg_cks_t                clk_select;
+    ssif_chcfg_multi_ch_t           multi_ch;
+    ssif_chcfg_data_word_t          data_word;
+    ssif_chcfg_system_word_t        system_word;
+    ssif_chcfg_clock_dir_t          clock_direction;
+    ssif_chcfg_ws_dir_t             ws_direction;
+    ssif_chcfg_clock_pol_t          bclk_pol;
+    ssif_chcfg_ws_pol_t             ws_pol;
+    ssif_chcfg_padding_pol_t        padding_pol;
+    ssif_chcfg_serial_alignment_t   serial_alignment;
+    ssif_chcfg_parallel_alignment_t parallel_alignment;
+    ssif_chcfg_ws_delay_t           ws_delay;
+    ssif_chcfg_noise_cancel_t       noise_cancel;
+    ssif_chcfg_tdm_t                tdm_mode;
+    ssif_chcfg_ckdv_t               clk_div;
+    ssif_chcfg_romdec_t             romdec_direct;
+} ssif_info_ch_t;
+
+
+typedef struct ssif_info_drv
+{
+    ssif_drv_stat_t drv_stat;
+    ssif_info_ch_t  info_ch[SSIF_NUM_CHANS];
+} ssif_info_drv_t;
+
+extern volatile struct st_ssif* const g_ssireg[SSIF_NUM_CHANS];
+
+/******************************************************************************
+ Function Prototypes
+ *****************************************************************************/
+#if(1) /* mbed */
+int_t SSIF_InitialiseOne(const int_t channel, const ssif_channel_cfg_t* const p_cfg_data);
+int_t SSIF_UnInitialiseOne(const int_t channel);
+#else
+int_t SSIF_Initialise(const ssif_channel_cfg_t* const p_cfg_data);
+int_t SSIF_UnInitialise(void);
+#endif
+int_t SSIF_EnableChannel(ssif_info_ch_t* const p_info_ch);
+int_t SSIF_DisableChannel(ssif_info_ch_t* const p_info_ch);
+void  SSIF_ErrorRecovery(ssif_info_ch_t* const p_info_ch);
+
+void SSIF_PostAsyncIo(ssif_info_ch_t* const p_info_ch, AIOCB* const p_aio);
+void SSIF_PostAsyncCancel(ssif_info_ch_t* const p_info_ch, AIOCB* const p_aio);
+
+int_t SSIF_IOCTL_ConfigChannel(ssif_info_ch_t* const p_info_ch,
+                const ssif_channel_cfg_t* const p_ch_cfg);
+int_t SSIF_IOCTL_GetStatus(const ssif_info_ch_t* const p_info_ch, uint32_t* const p_status);
+
+int_t SSIF_InitDMA(ssif_info_ch_t* const p_info_ch);
+void SSIF_UnInitDMA(ssif_info_ch_t* const p_info_ch);
+void SSIF_CancelDMA(const ssif_info_ch_t* const p_info_ch);
+int_t SSIF_RestartDMA(ssif_info_ch_t* const p_info_ch);
+
+int_t SSIF_SWLtoLen(const ssif_chcfg_system_word_t ssicr_swl);
+int_t SSIF_DWLtoLen(const ssif_chcfg_data_word_t ssicr_dwl);
+
+extern ssif_info_drv_t g_ssif_info_drv;
+
+#endif /* SSIF_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_src/ssif/ssif_cfg.c	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,555 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : ssif_cfg.c
+* $Rev: 891 $
+* $Date:: 2014-06-27 10:40:52 +0900#$
+* Description : SSIF driver userown functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "dma_if.h"
+#include "ssif_if.h"
+#include "iodefine.h"
+#include "Renesas_RZ_A1.h"
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+/***** Audio Clock Source Configurations *****/
+/* AUDIO_X1 : Connect to CPU Board X8(22579200Hz) */
+#define SSIF_AUDIO_X1  (22579200u)
+
+/* AUDIO_CLK: Connect to option board J7(no clock on board) */
+#define SSIF_AUDIO_CLK (0u)
+
+/* SSICR CKDV divieded value */
+#define SSIF_AUDIO_CLK_DIV_1    (1u)
+#define SSIF_AUDIO_CLK_DIV_2    (2u)
+#define SSIF_AUDIO_CLK_DIV_4    (4u)
+#define SSIF_AUDIO_CLK_DIV_8    (8u)
+#define SSIF_AUDIO_CLK_DIV_16   (16u)
+#define SSIF_AUDIO_CLK_DIV_32   (32u)
+#define SSIF_AUDIO_CLK_DIV_64   (64u)
+#define SSIF_AUDIO_CLK_DIV_128  (128u)
+#define SSIF_AUDIO_CLK_DIV_6    (6u)
+#define SSIF_AUDIO_CLK_DIV_12   (12u)
+#define SSIF_AUDIO_CLK_DIV_24   (24u)
+#define SSIF_AUDIO_CLK_DIV_48   (48u)
+#define SSIF_AUDIO_CLK_DIV_96   (96u)
+
+/* SSIF channel number */
+#define SSIF_CHNUM_0    (0u)
+#define SSIF_CHNUM_1    (1u)
+#define SSIF_CHNUM_2    (2u)
+#define SSIF_CHNUM_3    (3u)
+#define SSIF_CHNUM_4    (4u)
+#define SSIF_CHNUM_5    (5u)
+
+/* misc constant value */
+#define SSIF_I2S_LR_CH  (2u)
+
+/*******************************************************************************
+Exported global variables (to be accessed by other files)
+*******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_SSIF_Userdef_InitPinMux
+* @brief         This function initialise pin multiplex settings.
+*
+*                Description:<br>
+*                R7S72100 Boards depended pin connections bellow<br>
+*                Clock settings<br>
+*                  AUDIO_X1 : Private use pin(nothing to do)<br>
+*                  AUDIO_X2 : No connection<br>
+*                  AUDIO_CLK: Working with SSIF5<br>
+*                Channel settings<br>
+*                  SSIF0    : Fully connected to WM8978<br>
+*                  SSIF1    : Read only (NC:SSITxD1) connected to CD Deck<br>
+*                  SSIF2    : No connection<br>
+*                  SSIF3    : Write only (NC:SSIRxD3) connected to AK4353<br>
+*                  SSIF4    : Fully connected to AK4353<br>
+*                  SSIF5    : Fully connected to HCI
+* @param[in]     ssif_ch      :channel number.
+* @retval        ESUCCESS     :Success.
+* @retval        error code   :Failure.
+******************************************************************************/
+int_t R_SSIF_Userdef_InitPinMux(const uint32_t ssif_ch)
+{
+#if(1) /* mbed */
+    UNUSED_ARG(ssif_ch);
+
+    return ESUCCESS;
+#else
+    int_t ercd = ESUCCESS;
+    int_t was_masked;
+
+    was_masked = __disable_irq();
+
+    /* -> IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on writing to 16bit register. */
+    switch (ssif_ch)
+    {
+        case SSIF_CHNUM_0:
+            /* SSISCK0(P4_4, Alternative Mode 5,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N4);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS0(P4_5, Alternative Mode 5,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N5);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIRxD0(P4_6, Alternative Mode 5,Input) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N6);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N6);
+
+            /* SSITxD0(P4_7, Alternative Mode 5,Output) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N7);
+
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N7);
+
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PM4    &= (uint16_t)~(GPIO_BIT_N7);
+            break;
+
+        case SSIF_CHNUM_1:
+            /* SSISCK1(P3_4, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC3  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC3   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCE3  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCAE3 &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PIPC3  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS1(P3_5, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC3  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC3   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCE3  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCAE3 &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PIPC3 |=  (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIRxD1(P3_6, Alternative Mode 3,Input) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFC3   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCE3  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCAE3 &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PIPC3  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N6);
+
+            /* SSITxD1:  no connection */
+            break;
+
+        case SSIF_CHNUM_2:
+            /* SSISCK2:  no connection */
+            /* SSIWS2:   no connection */
+            /* SSIDATA2: no connection */
+            break;
+
+        case SSIF_CHNUM_3:
+            /* SSISCK3(P4_12, Alternative Mode 6,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N12);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PFC4   |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N12);
+
+            GPIO.PIPC4  |= (uint16_t) GPIO_BIT_N12;
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N12);
+
+            /* SSIWS3(P4_13, Alternative Mode 6,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N13);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PFC4   |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N13);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N13);
+
+            /* SSIRxD3:  no connection */
+
+            /* SSITxD3(P4_15, Alternative Mode 6,Output) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N15);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N15);
+
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PFC4   |= (uint16_t) (GPIO_BIT_N15);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N15);
+
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N15);
+            GPIO.PM4    &= (uint16_t)~(GPIO_BIT_N15);
+            break;
+
+        case SSIF_CHNUM_4:
+            /* SSISCK4(P11_4, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC11  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC11  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM11    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC11   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC11  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC11  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC11   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCE11  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCAE11 &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PIPC11  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC11   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS4(P11_5, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC11  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC11  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM11    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC11   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC11  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC11  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC11   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCE11  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCAE11 &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PIPC11  |= (uint16_t) GPIO_BIT_N5;
+            GPIO.PMC11   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIDATA4(P11_6, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC11  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC11  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM11    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC11   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC11  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC11  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFC11   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCE11  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCAE11 &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PIPC11  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC11   |= (uint16_t) (GPIO_BIT_N6);
+            break;
+
+        case SSIF_CHNUM_5:
+            /* SSISCK5(P2_4, Alternative Mode 4,InputOutput) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC2  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PIPC2  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS5(P2_5, Alternative Mode 4,InputOutput) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC2  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PIPC2  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIRxD5(P2_6, Alternative Mode 4,Input) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PIPC2  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N6);
+
+            /* SSITxD5(P2_7, Alternative Mode 4,Output) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N7);
+
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N7);
+
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PM2    &= (uint16_t)~(GPIO_BIT_N7);
+
+            /* AUDIO_CLK(P3_1, Alternative Mode 6,Input) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N1);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N1);
+
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PFC3   |= (uint16_t) (GPIO_BIT_N1);
+            GPIO.PFCE3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PFCAE3 |= (uint16_t) (GPIO_BIT_N1);
+
+            GPIO.PIPC3  |= (uint16_t) (GPIO_BIT_N1);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N1);
+            break;
+
+        default:
+            ercd = EINVAL;
+            break;
+    }
+    /* <- IPA R2.4.2 */
+
+    if (0 == was_masked)
+    {
+        __enable_irq();
+    }
+
+    return ercd;
+#endif
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_Userdef_SetClockDiv
+* @brief         This function make a value of divieded audio clock.
+*
+*                Description:<br>
+*
+* @param[in]     p_ch_cfg     :pointer of channel configuration parameter.
+* @param[in,out] p_clk_div    :pointer of SSICR register CKDV value
+* @retval        ESUCCESS     :Success.
+* @retval        error code   :Failure.
+******************************************************************************/
+int_t R_SSIF_Userdef_SetClockDiv(const ssif_channel_cfg_t* const p_ch_cfg, ssif_chcfg_ckdv_t* const p_clk_div)
+{
+    uint32_t input_clk;
+    uint32_t dot_clk;
+    uint32_t n_syswd_per_smp;
+    uint32_t syswd_len;
+    uint32_t smp_freq;
+    uint32_t result;
+    uint32_t division;
+    int_t ret = ESUCCESS;
+
+    if ((NULL == p_ch_cfg) || (NULL == p_clk_div))
+    {
+        ret = EFAULT;
+    }
+    else
+    {
+        if (SSIF_CFG_CKS_AUDIO_X1 == p_ch_cfg->clk_select)
+        {
+            input_clk = SSIF_AUDIO_X1;
+        }
+        else if (SSIF_CFG_CKS_AUDIO_CLK == p_ch_cfg->clk_select)
+        {
+            input_clk = SSIF_AUDIO_CLK;
+        }
+        else
+        {
+            input_clk = 0u;
+        }
+
+        if (0u == input_clk)
+        {
+            ret = EINVAL;
+        }
+     
+        if (ESUCCESS == ret)
+        {
+            syswd_len = (uint32_t)R_SSIF_SWLtoLen(p_ch_cfg->system_word);
+            smp_freq = p_ch_cfg->sample_freq;
+
+            if (SSIF_CFG_DISABLE_TDM == p_ch_cfg->tdm_mode)
+            {
+                /* I2S format has 2 system_words */
+                n_syswd_per_smp = SSIF_I2S_LR_CH;
+            }
+            else
+            {
+                /* TDM frame has [(CHNL+1) * 2] system_words */
+                n_syswd_per_smp = (((uint32_t)p_ch_cfg->multi_ch) + 1) * SSIF_I2S_LR_CH;
+            }
+
+            dot_clk = syswd_len * n_syswd_per_smp * smp_freq;
+
+            if (0u == dot_clk)
+            {
+                ret = EINVAL;
+            }
+            else
+            {
+                /* check if input audio clock can be divided by dotclock */
+                result = input_clk % dot_clk;
+
+                if (0u != result)
+                {
+                    /* cannot create dotclock from input audio clock */
+                    ret = EINVAL;
+                }
+                else
+                {
+                    division = input_clk / dot_clk;
+
+                    switch (division)
+                    {
+                    case SSIF_AUDIO_CLK_DIV_1:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_1;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_2:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_2;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_4:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_4;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_8:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_8;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_16:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_16;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_32:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_32;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_64:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_64;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_128:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_128;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_6:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_6;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_12:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_12;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_24:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_24;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_48:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_48;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_96:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_96;
+                        break;
+                    default:
+                        ret = EINVAL;
+                        break;
+                    }
+                }
+            }
+        }
+    }
+
+    return ret;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_src/ssif/ssif_dma.c	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,835 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : ssif_dma.c
+* $Rev: 891 $
+* $Date:: 2014-06-27 10:40:52 +0900#$
+* Description : SSIF driver DMA functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "ssif.h"
+#include "iodefine.h"
+#include "ssif_int.h"
+#include "dma_if.h"
+#include "Renesas_RZ_A1.h"
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define SSIF_DUMMY_DMA_BUF_SIZE (4096u)
+#define SSIF_I2S_LR_CH          (2u)
+
+#define SSIF_ROMDEC_DMA_SIZE    (2352u)
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Exported global variables (to be accessed by other files)
+*******************************************************************************/
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+static void SSIF_DMA_TxCallback(union sigval param);
+static void SSIF_DMA_RxCallback(union sigval param);
+
+static const dma_res_select_t gb_ssif_dma_tx_resource[SSIF_NUM_CHANS] =
+{
+    DMA_RS_SSITXI0,
+    DMA_RS_SSITXI1,
+    DMA_RS_SSIRTI2,
+    DMA_RS_SSITXI3,
+    DMA_RS_SSIRTI4,
+    DMA_RS_SSITXI5
+};
+
+static const dma_res_select_t gb_ssif_dma_rx_resource[SSIF_NUM_CHANS] =
+{
+    DMA_RS_SSIRXI0,
+    DMA_RS_SSIRXI1,
+    DMA_RS_SSIRTI2,
+    DMA_RS_SSIRXI3,
+    DMA_RS_SSIRTI4,
+    DMA_RS_SSIRXI5
+};
+
+static AIOCB gb_ssif_dma_tx_end_aiocb[SSIF_NUM_CHANS];
+static AIOCB gb_ssif_dma_rx_end_aiocb[SSIF_NUM_CHANS];
+
+static dma_trans_data_t gb_ssif_txdma_dummy_trparam[SSIF_NUM_CHANS];
+static dma_trans_data_t gb_ssif_rxdma_dummy_trparam[SSIF_NUM_CHANS];
+
+static uint32_t ssif_tx_dummy_buf[SSIF_DUMMY_DMA_BUF_SIZE];
+static uint32_t ssif_rx_dummy_buf[SSIF_DUMMY_DMA_BUF_SIZE];
+
+/******************************************************************************
+* Function Name: SSIF_InitDMA
+* @brief         Allocate and Setup DMA_CH for specified SSIF channel.
+*
+*                Description:<br>
+*                
+* @param[in,out] p_info_ch  :channel object.
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_InitDMA(ssif_info_ch_t* const p_info_ch)
+{
+    int_t ercd = ESUCCESS;
+    int_t dma_ret;
+    uint32_t ssif_ch;
+    int32_t dma_ercd;
+    dma_ch_setup_t  dma_ch_setup;
+    uint32_t n_datawd_per_smp;
+    uint32_t byte_per_smp;
+    uint32_t dummy_smp_count;
+    uint32_t dummy_dma_size = 0u;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        /* calculate dummy dma transfer size */
+        n_datawd_per_smp = (uint32_t)(p_info_ch->multi_ch + 1) * SSIF_I2S_LR_CH;
+        byte_per_smp = n_datawd_per_smp * (uint32_t)SSIF_DWLtoLen(p_info_ch->data_word);
+
+        if (0u == byte_per_smp)
+        {
+            ercd = EFAULT;
+        }
+        else
+        {
+            dummy_smp_count = SSIF_DUMMY_DMA_BUF_SIZE / byte_per_smp;
+            dummy_dma_size = dummy_smp_count * byte_per_smp;
+
+            if (0u == dummy_dma_size)
+            {
+                ercd = EFAULT;
+            }
+        }
+
+        /* allocate DMA Channel for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY == p_info_ch->openflag)
+            {
+                p_info_ch->dma_tx_ch = -1;
+            }
+            else
+            {
+                dma_ret = R_DMA_Alloc(DMA_ALLOC_CH, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    p_info_ch->dma_tx_ch = -1;
+                    ercd = ENOMEM;
+                }
+                else
+                {
+                    p_info_ch->dma_tx_ch = dma_ret;
+                    ercd = ESUCCESS;
+                }
+            }
+        }
+
+        /* allocate DMA Channel for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY == p_info_ch->openflag)
+            {
+                p_info_ch->dma_rx_ch = -1;
+            }
+            else
+            {
+                dma_ret = R_DMA_Alloc(DMA_ALLOC_CH, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    p_info_ch->dma_rx_ch = -1;
+                    ercd = ENOMEM;
+                }
+                else
+                {
+                    p_info_ch->dma_rx_ch = dma_ret;
+                    ercd = ESUCCESS;
+                }
+            }
+        }
+
+        /* setup DMA channel for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY != p_info_ch->openflag)
+            {
+                AIOCB* const p_tx_aio = &gb_ssif_dma_tx_end_aiocb[ssif_ch];
+                p_tx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+                p_tx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch;
+                p_tx_aio->aio_sigevent.sigev_notify_function = &SSIF_DMA_TxCallback;
+
+                dma_ch_setup.resource = gb_ssif_dma_tx_resource[ssif_ch];
+                dma_ch_setup.direction = DMA_REQ_DES;
+                dma_ch_setup.dst_width = DMA_UNIT_4;
+                dma_ch_setup.src_width = DMA_UNIT_4;
+                dma_ch_setup.dst_cnt = DMA_ADDR_FIX;
+                dma_ch_setup.src_cnt = DMA_ADDR_INCREMENT;
+                dma_ch_setup.p_aio = p_tx_aio;
+
+                dma_ret = R_DMA_Setup(p_info_ch->dma_tx_ch, &dma_ch_setup, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT;
+                }
+            }
+        }
+
+        /* setup DMA channel for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY != p_info_ch->openflag)
+            {
+                AIOCB* const p_rx_aio = &gb_ssif_dma_rx_end_aiocb[ssif_ch];
+                p_rx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+                p_rx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch;
+                p_rx_aio->aio_sigevent.sigev_notify_function = &SSIF_DMA_RxCallback;
+
+                dma_ch_setup.resource = gb_ssif_dma_rx_resource[ssif_ch];
+                dma_ch_setup.direction = DMA_REQ_SRC;
+                dma_ch_setup.dst_width = DMA_UNIT_4;
+                dma_ch_setup.src_width = DMA_UNIT_4;
+                dma_ch_setup.src_cnt = DMA_ADDR_FIX;
+                dma_ch_setup.p_aio = p_rx_aio;
+
+                if (SSIF_CFG_ENABLE_ROMDEC_DIRECT
+                    != p_info_ch->romdec_direct.mode)
+                {
+                    dma_ch_setup.dst_cnt = DMA_ADDR_INCREMENT;
+                }
+                else
+                {
+                    dma_ch_setup.dst_cnt = DMA_ADDR_FIX;
+                }
+
+                dma_ret = R_DMA_Setup(p_info_ch->dma_rx_ch, &dma_ch_setup, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT;
+                }
+            }
+        }
+
+        /* start DMA dummy transfer for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY != p_info_ch->openflag)
+            {
+                /* setup short dummy transfer */
+                gb_ssif_txdma_dummy_trparam[ssif_ch].src_addr = (void*)&ssif_tx_dummy_buf[0];
+                gb_ssif_txdma_dummy_trparam[ssif_ch].dst_addr = (void*)&g_ssireg[ssif_ch]->SSIFTDR;
+                gb_ssif_txdma_dummy_trparam[ssif_ch].count = dummy_dma_size;
+
+                dma_ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT;
+                }
+                else
+                {
+                    dma_ret = R_DMA_Start(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &dma_ercd);
+                    if (EERROR == dma_ret)
+                    {
+                        ercd = EFAULT;
+                    }
+                }
+            }
+        }
+
+        /* start DMA dummy transfer for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY != p_info_ch->openflag)
+            {
+                if (SSIF_CFG_ENABLE_ROMDEC_DIRECT
+                    != p_info_ch->romdec_direct.mode)
+                {
+                    /* setup short dummy transfer */
+                    gb_ssif_rxdma_dummy_trparam[ssif_ch].src_addr = (void*)&g_ssireg[ssif_ch]->SSIFRDR;
+                    gb_ssif_rxdma_dummy_trparam[ssif_ch].dst_addr = (void*)&ssif_rx_dummy_buf[0];
+                    gb_ssif_rxdma_dummy_trparam[ssif_ch].count = dummy_dma_size;
+                }
+                else
+                {
+                    /* setup ROMDEC direct input transfer */
+                    gb_ssif_rxdma_dummy_trparam[ssif_ch].src_addr = (void*)&g_ssireg[ssif_ch]->SSIFRDR;
+                    gb_ssif_rxdma_dummy_trparam[ssif_ch].dst_addr = (void*)&ROMDEC.STRMDIN0;
+                    gb_ssif_rxdma_dummy_trparam[ssif_ch].count = SSIF_ROMDEC_DMA_SIZE;
+                }
+
+                dma_ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT;
+                }
+                else
+                {
+                    dma_ret = R_DMA_Start(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &dma_ercd);
+                    if (EERROR == dma_ret)
+                    {
+                        ercd = EFAULT;
+                    }
+                }
+            }
+        }
+
+        /* enable ssif transfer */
+        if (ESUCCESS == ercd)
+        {
+            /* clear status and enable error interrupt */
+            SSIF_EnableErrorInterrupt(ssif_ch);
+
+            /* enable end interrupt */
+            g_ssireg[ssif_ch]->SSIFCR |= SSIF_FCR_BIT_TIE | SSIF_FCR_BIT_RIE;
+
+            if (O_RDWR == p_info_ch->openflag)
+            {
+                /* start write and read DMA at the same time */
+                g_ssireg[ssif_ch]->SSICR  |= SSIF_CR_BIT_TEN | SSIF_CR_BIT_REN;
+            }
+            else if (O_WRONLY == p_info_ch->openflag)
+            {
+                /* start write DMA only */
+                g_ssireg[ssif_ch]->SSICR  |= SSIF_CR_BIT_TEN;
+            }
+            else if (O_RDONLY == p_info_ch->openflag)
+            {
+                /* start read DMA only */
+                g_ssireg[ssif_ch]->SSICR  |= SSIF_CR_BIT_REN;
+            }
+            else
+            {
+                ercd = EINVAL;
+            }
+        }
+
+        /* cleanup dma resources when error occured */
+        if (ESUCCESS != ercd)
+        {
+            if (-1 != p_info_ch->dma_tx_ch)
+            {
+                uint32_t remain;
+                dma_ret = R_DMA_Cancel(p_info_ch->dma_tx_ch, &remain, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected dma error */
+                }
+            }
+
+            if (-1 != p_info_ch->dma_rx_ch)
+            {
+                uint32_t remain;
+                dma_ret = R_DMA_Cancel(p_info_ch->dma_rx_ch, &remain, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected dma error */
+                }
+            }
+
+            if (-1 != p_info_ch->dma_tx_ch)
+            {
+                dma_ret = R_DMA_Free(p_info_ch->dma_tx_ch, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected dma error */
+                }
+                p_info_ch->dma_tx_ch = -1;
+            }
+
+            if (-1 != p_info_ch->dma_rx_ch)
+            {
+                dma_ret = R_DMA_Free(p_info_ch->dma_rx_ch, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected dma error */
+                }
+                p_info_ch->dma_rx_ch = -1;
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_UnInitDMA
+* @brief         Free DMA_CH for specified SSIF channel.
+*
+*                Description:<br>
+*                
+* @param[in,out] p_info_ch  :channel object.
+* @retval        none
+******************************************************************************/
+void SSIF_UnInitDMA(ssif_info_ch_t* const p_info_ch)
+{
+    int_t dma_ret;
+    int32_t dma_ercd;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        if (-1 != p_info_ch->dma_tx_ch)
+        {
+            uint32_t remain;
+            dma_ret = R_DMA_Cancel(p_info_ch->dma_tx_ch, &remain, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+        }
+
+        if (-1 != p_info_ch->dma_rx_ch)
+        {
+            uint32_t remain;
+            dma_ret = R_DMA_Cancel(p_info_ch->dma_rx_ch, &remain, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+        }
+
+        if (-1 != p_info_ch->dma_tx_ch)
+        {
+            dma_ret = R_DMA_Free(p_info_ch->dma_tx_ch, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+            p_info_ch->dma_tx_ch = -1;
+        }
+
+        if (-1 != p_info_ch->dma_rx_ch)
+        {
+            dma_ret = R_DMA_Free(p_info_ch->dma_rx_ch, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+            p_info_ch->dma_rx_ch = -1;
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_RestartDMA
+* @brief         Setup DMA_CH for specified SSIF channel(without allocate)
+*
+*                Description:<br>
+*                
+* @param[in,out] p_info_ch  :channel object.
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_RestartDMA(ssif_info_ch_t* const p_info_ch)
+{
+    int_t ercd = ESUCCESS;
+    int_t dma_ret;
+    uint32_t ssif_ch;
+    int32_t dma_ercd;
+    dma_ch_setup_t  dma_ch_setup;
+    uint32_t n_datawd_per_smp;
+    uint32_t byte_per_smp;
+    uint32_t dummy_smp_count;
+    uint32_t dummy_dma_size = 0u;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        /* calculate dummy dma transfer size */
+        n_datawd_per_smp = (uint32_t)(p_info_ch->multi_ch + 1) * SSIF_I2S_LR_CH;
+        byte_per_smp = n_datawd_per_smp * (uint32_t)SSIF_DWLtoLen(p_info_ch->data_word);
+
+        if (0u == byte_per_smp)
+        {
+            ercd = EFAULT;
+        }
+        else
+        {
+            dummy_smp_count = SSIF_DUMMY_DMA_BUF_SIZE / byte_per_smp;
+            dummy_dma_size = dummy_smp_count * byte_per_smp;
+
+            if (0u == dummy_dma_size)
+            {
+                ercd = EFAULT;
+            }
+        }
+
+        /* setup DMA channel for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY != p_info_ch->openflag)
+            {
+                AIOCB* const p_tx_aio = &gb_ssif_dma_tx_end_aiocb[ssif_ch];
+                p_tx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+                p_tx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch;
+                p_tx_aio->aio_sigevent.sigev_notify_function = &SSIF_DMA_TxCallback;
+
+                dma_ch_setup.resource = gb_ssif_dma_tx_resource[ssif_ch];
+                dma_ch_setup.direction = DMA_REQ_DES;
+                dma_ch_setup.dst_width = DMA_UNIT_4;
+                dma_ch_setup.src_width = DMA_UNIT_4;
+                dma_ch_setup.dst_cnt = DMA_ADDR_FIX;
+                dma_ch_setup.src_cnt = DMA_ADDR_INCREMENT;
+                dma_ch_setup.p_aio = p_tx_aio;
+
+                dma_ret = R_DMA_Setup(p_info_ch->dma_tx_ch, &dma_ch_setup, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT;
+                }
+            }
+        }
+
+        /* setup DMA channel for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY != p_info_ch->openflag)
+            {
+                AIOCB* const p_rx_aio = &gb_ssif_dma_rx_end_aiocb[ssif_ch];
+                p_rx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+                p_rx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch;
+                p_rx_aio->aio_sigevent.sigev_notify_function = &SSIF_DMA_RxCallback;
+
+                dma_ch_setup.resource = gb_ssif_dma_rx_resource[ssif_ch];
+                dma_ch_setup.direction = DMA_REQ_SRC;
+                dma_ch_setup.dst_width = DMA_UNIT_4;
+                dma_ch_setup.src_width = DMA_UNIT_4;
+                dma_ch_setup.dst_cnt = DMA_ADDR_INCREMENT;
+                dma_ch_setup.src_cnt = DMA_ADDR_FIX;
+                dma_ch_setup.p_aio = p_rx_aio;
+
+                dma_ret = R_DMA_Setup(p_info_ch->dma_rx_ch, &dma_ch_setup, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT;
+                }
+            }
+        }
+
+        /* start DMA dummy transfer for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY != p_info_ch->openflag)
+            {
+                /* setup short dummy transfer */
+                gb_ssif_txdma_dummy_trparam[ssif_ch].src_addr = (void*)&ssif_tx_dummy_buf[0];
+                gb_ssif_txdma_dummy_trparam[ssif_ch].dst_addr = (void*)&g_ssireg[ssif_ch]->SSIFTDR;
+                gb_ssif_txdma_dummy_trparam[ssif_ch].count = dummy_dma_size;
+
+                dma_ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT;
+                }
+                else
+                {
+                    dma_ret = R_DMA_Start(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &dma_ercd);
+                    if (EERROR == dma_ret)
+                    {
+                        ercd = EFAULT;
+                    }
+                }
+            }
+        }
+
+        /* start DMA dummy transfer for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY != p_info_ch->openflag)
+            {
+                /* setup short dummy transfer */
+                gb_ssif_rxdma_dummy_trparam[ssif_ch].src_addr = (void*)&g_ssireg[ssif_ch]->SSIFRDR;
+                gb_ssif_rxdma_dummy_trparam[ssif_ch].dst_addr = (void*)&ssif_rx_dummy_buf[0];
+                gb_ssif_rxdma_dummy_trparam[ssif_ch].count = dummy_dma_size;
+
+                dma_ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT;
+                }
+                else
+                {
+                    dma_ret = R_DMA_Start(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &dma_ercd);
+                    if (EERROR == dma_ret)
+                    {
+                        ercd = EFAULT;
+                    }
+                }
+            }
+        }
+
+        /* enable ssif transfer */
+        if (ESUCCESS == ercd)
+        {
+            /* clear status and enable error interrupt */
+            SSIF_EnableErrorInterrupt(ssif_ch);
+
+            /* enable end interrupt */
+            g_ssireg[ssif_ch]->SSIFCR |= SSIF_FCR_BIT_TIE | SSIF_FCR_BIT_RIE;
+
+            if (O_RDWR == p_info_ch->openflag)
+            {
+                /* start write and read DMA at the same time */
+                g_ssireg[ssif_ch]->SSICR  |= SSIF_CR_BIT_TEN | SSIF_CR_BIT_REN;
+            }
+            else if (O_WRONLY == p_info_ch->openflag)
+            {
+                /* start write DMA only */
+                g_ssireg[ssif_ch]->SSICR  |= SSIF_CR_BIT_TEN;
+            }
+            else if (O_RDONLY == p_info_ch->openflag)
+            {
+                /* start read DMA only */
+                g_ssireg[ssif_ch]->SSICR  |= SSIF_CR_BIT_REN;
+            }
+            else
+            {
+                ercd = EINVAL;
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_CancelDMA
+* @brief         Pause DMA transfer for specified SSIF channel.
+*
+*                Description:<br>
+*                
+* @param[in,out] p_info_ch  :channel object.
+* @retval        none
+******************************************************************************/
+void SSIF_CancelDMA(const ssif_info_ch_t* const p_info_ch)
+{
+    int_t dma_ret;
+    int32_t dma_ercd;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        if (-1 != p_info_ch->dma_tx_ch)
+        {
+            uint32_t remain;
+            dma_ret = R_DMA_Cancel(p_info_ch->dma_tx_ch, &remain, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+        }
+
+        if (-1 != p_info_ch->dma_rx_ch)
+        {
+            uint32_t remain;
+            dma_ret = R_DMA_Cancel(p_info_ch->dma_rx_ch, &remain, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+Private functions                                                               
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: SSIF_DMA_TxCallback
+* @brief         DMA callback function
+*
+*                Description:<br>
+*                
+* @param[in]     param      :callback param
+* @retval        none
+******************************************************************************/
+static void SSIF_DMA_TxCallback(const union sigval param)
+{
+    ssif_info_ch_t* const p_info_ch = param.sival_ptr;
+    uint32_t ssif_ch;
+    dma_trans_data_t dma_data_next;
+    int_t ercd = ESUCCESS;
+    int_t ret;
+
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (NULL == p_info_ch->p_aio_tx_curr)
+        {
+            /* now complete dummy transfer, It isn't neccessary to signal. */
+        }
+        else
+        {
+            /* now complete user request transfer, Signal to application */
+
+            /* return aio complete */
+            p_info_ch->p_aio_tx_curr->aio_return = (ssize_t)p_info_ch->p_aio_tx_curr->aio_nbytes;
+            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_curr);
+        }
+
+        /* copy next to curr(even if it's NULL) */
+        p_info_ch->p_aio_tx_curr = p_info_ch->p_aio_tx_next;
+
+        /* get next request(It's maybe NULL) */
+        p_info_ch->p_aio_tx_next = ahf_removehead(&p_info_ch->tx_que);
+
+        if (NULL != p_info_ch->p_aio_tx_next)
+        {
+            /* add user request */
+            dma_data_next.dst_addr = (void*)&g_ssireg[ssif_ch]->SSIFTDR;
+            dma_data_next.src_addr = (void*)p_info_ch->p_aio_tx_next->aio_buf;
+            dma_data_next.count = (uint32_t)p_info_ch->p_aio_tx_next->aio_nbytes;
+
+            ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &dma_data_next, &ercd);
+            if (EERROR == ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected DMA error */
+            }
+        }
+        else
+        {
+            /* add dummy request */
+            ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &ercd);
+            if (EERROR == ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected DMA error */
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_DMA_RxCallback
+* @brief         DMA callback function
+*
+*                Description:<br>
+*                
+* @param[in]     param      :callback param
+* @retval        none
+******************************************************************************/
+static void SSIF_DMA_RxCallback(const union sigval param)
+{
+    ssif_info_ch_t* const p_info_ch = param.sival_ptr;
+    uint32_t ssif_ch;
+    dma_trans_data_t dma_data_next;
+    int_t ercd = ESUCCESS;
+    int_t ret;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (NULL == p_info_ch->p_aio_rx_curr)
+        {
+            /* now complete dummy transfer, It isn't neccessary to signal. */
+        }
+        else
+        {
+            /* now complete user request transfer, Signal to application */
+
+            /* return aio complete */
+            p_info_ch->p_aio_rx_curr->aio_return = (ssize_t)p_info_ch->p_aio_rx_curr->aio_nbytes;
+            ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_curr);
+        }
+
+        /* copy next to curr(even if it's NULL) */
+        p_info_ch->p_aio_rx_curr = p_info_ch->p_aio_rx_next;
+
+        /* get next request(It's maybe NULL) */
+        p_info_ch->p_aio_rx_next = ahf_removehead(&p_info_ch->rx_que);
+
+        if (NULL != p_info_ch->p_aio_rx_next)
+        {
+            /* add user request */
+            dma_data_next.src_addr = (void*)&g_ssireg[ssif_ch]->SSIFRDR;
+            dma_data_next.dst_addr = (void*)p_info_ch->p_aio_rx_next->aio_buf;
+            dma_data_next.count = (uint32_t)p_info_ch->p_aio_rx_next->aio_nbytes;
+
+            ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &dma_data_next, &ercd);
+            if (EERROR == ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected DMA error */
+            }
+        }
+        else
+        {
+            /* add dummy request */
+            ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &ercd);
+            if (EERROR == ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected DMA error */
+            }
+        }
+    }
+
+    return;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_src/ssif/ssif_if.c	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,896 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : ssif_if.c
+* $Rev: 891 $
+* $Date:: 2014-06-27 10:40:52 +0900#$
+* Description : SSIF driver interface functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "cmsis_os.h"
+#if(1) /* mbed */
+#else
+#include "ioif_public.h"
+#endif
+#include "ssif.h"
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+#if(1) /* mbed */
+static ssif_drv_stat_t ch_drv_stat[SSIF_NUM_CHANS] = {SSIF_DRVSTS_UNINIT};
+#else
+static void* R_SSIF_Init(void* const config_data, int32_t* const p_errno);
+static int_t R_SSIF_UnInit(void* const driver_instance, int32_t* const p_errno);
+static int_t R_SSIF_Open(void* const p_driver_instance, const char_t* const p_path_name, const int_t flags, const int_t mode, int32_t* const p_errno);
+static int_t R_SSIF_Close(void* const p_fd, int32_t* const p_errno);
+static int_t R_SSIF_Ioctl(void* const p_fd, const int_t request, void* const p_buf, int32_t* const p_errno);
+static int_t R_SSIF_WriteAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno);
+static int_t R_SSIF_ReadAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno);
+static int_t R_SSIF_Cancel(void* const p_fd, AIOCB* p_aio, int32_t* const p_errno);
+#endif
+
+static size_t SSIF_StrnLen(const char_t p_str[], const size_t maxlen);
+static int32_t SSIF_Strncmp(const char_t p_str1[], const char_t p_str2[], const uint32_t maxlen);
+static void   SSIF_SetErrCode(const int_t error_code, int32_t* const p_errno);
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+#if(1) /* mbed */
+#else
+/******************************************************************************
+* Function Name: R_SSIF_MakeCbTbl
+* @brief         Make the SSIF driver function callback table
+*
+*                Description:<br>
+*                
+* @param         none
+* @retval        pointer of SSIF driver function callback table
+******************************************************************************/
+/* ->IPA M1.1.1 : This is liblary funciotn that is called from other module. */
+IOIF_DRV_API* R_SSIF_MakeCbTbl(void)
+/* <-IPA M1.1.1 */
+{
+    static IOIF_DRV_API ssif_apitbl;
+
+    /* ->MISRA 16.4, IPA M4.5.1 : This is IOIF library API type definitnon that can't be modified. */
+    ssif_apitbl.family = IOIF_SERIAL_FAMILY;
+    ssif_apitbl.fns.serial.initialise   = &R_SSIF_Init;
+    ssif_apitbl.fns.serial.uninitialise = &R_SSIF_UnInit;
+    ssif_apitbl.fns.serial.open         = &R_SSIF_Open;
+    ssif_apitbl.fns.serial.close        = &R_SSIF_Close;
+    ssif_apitbl.fns.serial.ioctl        = &R_SSIF_Ioctl;
+    ssif_apitbl.fns.serial.read_a       = &R_SSIF_ReadAsync;
+    ssif_apitbl.fns.serial.write_a      = &R_SSIF_WriteAsync;
+    ssif_apitbl.fns.serial.cancel       = &R_SSIF_Cancel;
+    /* <-MISRA 16.4, IPA M4.5.1 */
+
+    return &ssif_apitbl;
+}
+#endif
+
+/******************************************************************************
+* Function Name: R_SSIF_SWLtoLen
+* @brief         Convert SSICR:SWL bits to system word length
+*
+*                Description:<br>
+*                
+* @param[in]     ssicr_swl  :SSICR register SWL field value(0 to 7)
+* @retval        8 to 256   :system word length(byte)
+******************************************************************************/
+int_t R_SSIF_SWLtoLen(const ssif_chcfg_system_word_t ssicr_swl)
+{
+    return SSIF_SWLtoLen(ssicr_swl);
+}
+
+/******************************************************************************
+Private functions
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_SSIF_Init
+* @brief         Initialise the SSIF driver.
+*
+*                Description:<br>
+*                
+* @param[in]     config_data :pointer of several parameters array per channels
+* @param[in,out] p_errno     :pointer of error code
+* @retval        not ERRROR  :driver instance.
+* @retval        EERROR      :Failure.
+******************************************************************************/
+/* ->MISRA 16.7, IPA M1.11.1 : This is IOIF library API type definitnon that can't be modified. */
+#if(1) /* mbed */
+void* R_SSIF_InitOne(const int_t channel, void* const config_data, int32_t* const p_errno)
+/* <-MISRA 16.7, IPA M1.11.1 */
+{
+    int_t ercd;
+    void* p_ret = (void*)EERROR;
+
+    if (NULL == config_data)
+    {
+        ercd = EFAULT;
+    }
+    else if (channel >= SSIF_NUM_CHANS)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        ch_drv_stat[channel] = SSIF_DRVSTS_INIT;
+
+        ercd = SSIF_InitialiseOne(channel, (ssif_channel_cfg_t*)config_data);
+
+        if (ESUCCESS == ercd)
+        {
+            p_ret = (void*)&g_ssif_info_drv;
+        }
+        else
+        {
+            ch_drv_stat[channel] = SSIF_DRVSTS_UNINIT;
+        }
+    }
+
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return p_ret;
+}
+#else
+static void* R_SSIF_Init(void* const config_data, int32_t* const p_errno)
+/* <-MISRA 16.7, IPA M1.11.1 */
+{
+    int_t ercd;
+    void* p_ret = (void*)EERROR;
+
+    if (NULL == config_data)
+    {
+        ercd = EFAULT;
+    }
+    else if (SSIF_DRVSTS_UNINIT != g_ssif_info_drv.drv_stat)
+    {
+        ercd = EBUSY;
+    }
+    else
+    {
+        g_ssif_info_drv.drv_stat = SSIF_DRVSTS_INIT;
+
+        ercd = SSIF_Initialise((ssif_channel_cfg_t*)config_data);
+
+        if (ESUCCESS == ercd)
+        {
+            p_ret = (void*)&g_ssif_info_drv;
+        }
+        else
+        {
+            g_ssif_info_drv.drv_stat = SSIF_DRVSTS_UNINIT;
+        }
+    }
+
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return p_ret;
+}
+#endif
+
+/******************************************************************************
+* Function Name: R_SSIF_UnInit
+* @brief         Uninitialise the SSIF deiver.
+*
+*                Description:<br>
+*                
+* @param[in,out] driver_instance :driver instance which was returned by<br>
+                                  R_SSIF_Init
+* @param[in,out] p_errno         :pointer of error code
+* @retval        ESUCCESS        :Success.
+* @retval        EERROR          :Failure.
+******************************************************************************/
+#if(1) /* mbed */
+int_t R_SSIF_UnInitOne(const int_t channel, void* const driver_instance, int32_t* const p_errno)
+{
+    int_t   ercd;
+    int_t   ret = ESUCCESS;
+    ssif_info_drv_t* const p_info_drv   = driver_instance;
+
+    if (NULL == p_info_drv)
+    {
+        ercd = EFAULT;
+    }
+    else if (channel >= SSIF_NUM_CHANS)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (SSIF_DRVSTS_INIT != ch_drv_stat[channel])
+        {
+            ercd = EFAULT;
+        }
+        else
+        {
+            ercd = SSIF_UnInitialiseOne(channel);
+            ch_drv_stat[channel] = SSIF_DRVSTS_UNINIT;
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+#else
+static int_t R_SSIF_UnInit(void* const driver_instance, int32_t* const p_errno)
+{
+    int_t   ercd;
+    int_t   ret = ESUCCESS;
+    ssif_info_drv_t* const p_info_drv   = driver_instance;
+
+    if (NULL == p_info_drv)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (SSIF_DRVSTS_INIT != p_info_drv->drv_stat)
+        {
+            ercd = EFAULT;
+        }
+        else
+        {
+            ercd = SSIF_UnInitialise();
+            p_info_drv->drv_stat = SSIF_DRVSTS_UNINIT;
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+#endif
+
+/******************************************************************************
+* Function Name: R_SSIF_Open
+* @brief         Open an SSIF channel
+*
+*                Description:<br>
+*                
+* @param[in,out] p_drv_instance :driver instance which was returned by<br>
+                                 R_SSIF_Init
+* @param[in]     p_path_name    :string of channel
+* @param[in]     flags          :access mode whether the channel is opened<br>
+                                 for a read or a write
+* @param[in]     mode           :not used
+* @param[in,out] p_errno        :pointer of error code
+* @retval        not EERROR     :channel handle
+* @retval        EERROR         :Failure.
+******************************************************************************/
+#if(1) /* mbed */
+int_t R_SSIF_Open(void* const p_driver_instance, const char_t* const p_path_name, const int_t flags, const int_t mode, int32_t* const p_errno)
+#else
+static int_t R_SSIF_Open(void* const p_driver_instance, const char_t* const p_path_name, const int_t flags, const int_t mode, int32_t* const p_errno)
+#endif
+{
+    uint32_t ssif_ch;
+    void* p_channelHandle;
+    size_t len;
+    size_t req_path_len;
+    ssif_info_drv_t* const p_info_drv = p_driver_instance;
+    ssif_info_ch_t* p_info_ch = NULL;
+    int_t ret;
+    int_t ercd = ESUCCESS;
+    osStatus os_ercd;
+    int32_t os_ret;
+    static const char_t* const ch_name_string[SSIF_NUM_CHANS] =
+    {
+        SSIF_CHSTR_0,
+        SSIF_CHSTR_1,
+        SSIF_CHSTR_2,
+        SSIF_CHSTR_3,
+        SSIF_CHSTR_4,
+        SSIF_CHSTR_5
+    };
+
+    UNUSED_ARG(mode);
+
+    if ((NULL == p_info_drv) || (NULL == p_path_name))
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        req_path_len = strlen(p_path_name);
+        if (0u == req_path_len)
+        {
+            ercd = ENOENT;
+        }
+
+#if(1) /* mbed */
+#else
+        if (ESUCCESS == ercd)
+        {
+            if (SSIF_DRVSTS_INIT != p_info_drv->drv_stat)
+            {
+                ercd = EFAULT;
+            }
+        }
+#endif
+
+        if (ESUCCESS == ercd)
+        {
+            /* Serch the same pathname */
+            for (ssif_ch = 0u; (ssif_ch < SSIF_NUM_CHANS) && (p_info_ch == NULL); ssif_ch++)
+            {
+                len = SSIF_StrnLen(ch_name_string[ssif_ch], SSIF_MAX_PATH_LEN);
+
+                if (req_path_len < len)
+                {
+                    len = req_path_len;
+                }
+
+                if (0 == SSIF_Strncmp(p_path_name, ch_name_string[ssif_ch], len))
+                {
+                    /* found a match */
+                    p_info_ch = &p_info_drv->info_ch[ssif_ch];
+                }
+            }
+        }
+    }
+
+    if (NULL == p_info_ch)
+    {
+        ercd = ENOENT;
+    }
+    else
+    {
+        if (ESUCCESS == ercd)
+        {
+            if (false == p_info_ch->enabled)
+            {
+                ercd = ENOTSUP;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            if (SSIF_CHSTS_INIT != p_info_ch->ch_stat)
+            {
+                ercd = EBADF;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            /* ->MISRA 10.6 : This macro is defined by CMSIS-RTOS that can't be modified. */
+            os_ret = osSemaphoreWait(p_info_ch->sem_access, osWaitForever);
+            /* <-MISRA 10.6 */
+
+            if ((-1) == os_ret)
+            {
+                ercd = EFAULT;
+            }
+            else
+            {
+                p_info_ch->openflag = flags;
+                p_info_ch->p_aio_tx_curr = NULL;
+                p_info_ch->p_aio_rx_curr = NULL;
+
+                ercd = SSIF_EnableChannel(p_info_ch);
+
+                if (ESUCCESS == ercd)
+                {
+                    p_info_ch->ch_stat = SSIF_CHSTS_OPEN;
+                }
+            }
+            os_ercd = osSemaphoreRelease(p_info_ch->sem_access);
+            if (osOK != os_ercd)
+            {
+                ercd = EFAULT;
+            }
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    else
+    {
+        p_channelHandle = (void*)p_info_ch;
+        ret = (int_t)p_channelHandle;
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_Close
+* @brief         Close an SSIF channel.
+*
+*                Description:<br>
+*                
+* @param[in,out] p_fd       :channel handle which was returned by R_SSIF_Open
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+#if(1) /* mbed */
+int_t R_SSIF_Close(void* const p_fd, int32_t* const p_errno)
+#else
+static int_t R_SSIF_Close(void* const p_fd, int32_t* const p_errno)
+#endif
+{
+    ssif_info_ch_t* const p_info_ch = p_fd;
+    int_t ret = ESUCCESS;
+    int_t ercd;
+    osStatus os_ercd;
+    int32_t os_ret;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        /* ->MISRA 10.6 : This macro is defined by CMSIS-RTOS that can't be modified. */
+        /* Get semaphore to access the channel data */
+        os_ret = osSemaphoreWait(p_info_ch->sem_access, osWaitForever);
+        /* <-MISRA 10.6 */
+
+        if ((-1) == os_ret)
+        {
+            ercd = EFAULT;
+        }
+        else
+        {
+            if (SSIF_CHSTS_OPEN != p_info_ch->ch_stat)
+            {
+                ercd = EFAULT;
+            }
+            else
+            {
+                SSIF_PostAsyncCancel(p_info_ch, NULL);
+
+                ercd = SSIF_DisableChannel(p_info_ch);
+
+                if (ESUCCESS == ercd)
+                {
+                    p_info_ch->ch_stat = SSIF_CHSTS_INIT;
+                }
+            }
+
+            /* Relese semaphore */
+            os_ercd = osSemaphoreRelease(p_info_ch->sem_access);
+
+            if (osOK != os_ercd)
+            {
+                ercd = EFAULT;
+            }
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_Ioctl 
+* @brief         IOCTL function of the SSIF deiver
+*
+*                Description:<br>
+*                
+* @param[in,out] p_fd       :channel handle which was returned by R_SSIF_Open
+* @param[in]     request    :IOCTL request code
+* @param[in,out] p_buf      :Meaning depends upon request.
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+#if(1) /* mbed */
+int_t R_SSIF_Ioctl(void* const p_fd, const int_t request, void* const p_buf, int32_t* const p_errno)
+#else
+static int_t R_SSIF_Ioctl(void* const p_fd, const int_t request, void* const p_buf, int32_t* const p_errno)
+#endif
+{
+    ssif_info_ch_t* const p_info_ch = p_fd;
+    int_t   ret = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    osStatus os_ercd;
+    int32_t os_ret;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (SSIF_CHSTS_OPEN != p_info_ch->ch_stat)
+        {
+            ercd = EFAULT;
+        }
+        else
+        {
+            /* ->MISRA 10.6 : This macro is defined by CMSIS-RTOS that can't be modified. */
+            os_ret = osSemaphoreWait(p_info_ch->sem_access, osWaitForever);
+            /* <-MISRA 10.6 */
+
+            if ((-1) == os_ret)
+            {
+                ercd = EFAULT;
+            }
+
+            if (ESUCCESS == ercd)
+            {
+                switch (request)
+                {
+                    case SSIF_CONFIG_CHANNEL:
+                    {
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            ssif_channel_cfg_t* const ch_info = (ssif_channel_cfg_t*)p_buf;
+                            ercd = SSIF_IOCTL_ConfigChannel(p_info_ch, ch_info);
+                        }
+                        break;
+                    }
+
+                    case SSIF_GET_STATUS:
+                    {
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            ercd = SSIF_IOCTL_GetStatus(p_info_ch, (uint32_t*)p_buf);
+                        }
+                        break;
+                    }
+
+                    default:
+                    {
+                        ercd = EINVAL;
+                        break;
+                    }
+                } /* switch */
+            }
+        }
+
+        os_ercd = osSemaphoreRelease(p_info_ch->sem_access);
+        if (osOK != os_ercd)
+        {
+            ercd = EFAULT;
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_WriteAsync
+* @brief         Enqueue asynchronous write request
+*
+*                Description:<br>
+*                
+* @param[in,out] p_fd       :channel handle which was returned by R_SSIF_Open
+* @param[in]     p_aio      :aio control block of write request
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+#if(1) /* mbed */
+int_t R_SSIF_WriteAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno)
+#else
+static int_t R_SSIF_WriteAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno)
+#endif
+{
+    ssif_info_ch_t* const p_info_ch = p_fd;
+    int_t   ret = ESUCCESS;
+    int_t ercd = ESUCCESS;
+
+    if ((NULL == p_info_ch) || (NULL == p_aio))
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (((uint32_t)O_RDONLY) == ((uint32_t)p_info_ch->openflag & O_ACCMODE))
+        {
+            ercd = EACCES;
+        }
+        else if (0u == p_aio->aio_nbytes)
+        {
+            ercd = EINVAL;
+        }
+        else
+        {
+            p_aio->aio_return = SSIF_ASYNC_W;
+            SSIF_PostAsyncIo(p_info_ch, p_aio);
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_ReadAsync
+* @brief         Enqueue asynchronous read request
+*
+*                Description:<br>
+*                
+* @param[in,out] p_fd       :channel handle which was returned by R_SSIF_Open
+* @param[in]     p_aio      :aio control block of read request
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+#if(1) /* mbed */
+int_t R_SSIF_ReadAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno)
+#else
+static int_t R_SSIF_ReadAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno)
+#endif
+{
+    ssif_info_ch_t* const p_info_ch = p_fd;
+    int_t   ret = ESUCCESS;
+    int_t ercd = ESUCCESS;
+
+    if ((NULL == p_info_ch) || (NULL == p_aio))
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if ((O_WRONLY == ((uint32_t)p_info_ch->openflag & O_ACCMODE))
+            || (SSIF_CFG_ENABLE_ROMDEC_DIRECT
+                == p_info_ch->romdec_direct.mode))
+        {
+            ercd = EACCES;
+        }
+        else if (0u == p_aio->aio_nbytes)
+        {
+            ercd = EINVAL;
+        }
+        else
+        {
+            p_aio->aio_return = SSIF_ASYNC_R;
+            SSIF_PostAsyncIo(p_info_ch, p_aio);
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_Cancel
+* @brief         Cancel read or write request(s)
+*
+*                Description:<br>
+*                
+* @param[in,out] p_fd       :channel handle which was returned by R_SSIF_Open
+* @param[in]     p_aio      :aio control block to cancel or NULL to cancel all.
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+#if(1) /* mbed */
+int_t R_SSIF_Cancel(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno)
+#else
+static int_t R_SSIF_Cancel(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno)
+#endif
+{
+    ssif_info_ch_t* const p_info_ch = p_fd;
+    int_t ret = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    osStatus os_ercd;
+    int32_t os_ret;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        /* ->MISRA 10.6 : This macro is defined by CMSIS-RTOS that can't be modified. */
+        /* Get semaphore to access the channel data */
+        os_ret = osSemaphoreWait(p_info_ch->sem_access, osWaitForever);
+        /* <-MISRA 10.6 */
+
+        if ((-1) == os_ret)
+        {
+            ercd = EFAULT;
+        }
+        else
+        {
+            if (SSIF_CHSTS_OPEN != p_info_ch->ch_stat)
+            {
+                ercd = EFAULT;
+            }
+            else
+            {
+                SSIF_PostAsyncCancel(p_info_ch, p_aio);
+            }
+
+            os_ercd = osSemaphoreRelease(p_info_ch->sem_access);
+
+            if (osOK != os_ercd)
+            {
+                ercd = EFAULT;
+            }
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_StrnLen 
+* @brief         computes the length of the string
+*
+*                Description:<br>
+*                
+* @param[in]     p_str      :pointer of string.
+* @param[in]     maxlen     :maximum length of inspection
+* @retval        < maxlen   :number of characters in the string
+* @retval        maxlen     :string is longer than maxlen
+******************************************************************************/
+static size_t SSIF_StrnLen(const char_t p_str[], const size_t maxlen)
+{
+    size_t len;
+
+    if (NULL == p_str)
+    {
+        len = 0;
+    }
+    else
+    {
+        for (len = 0; len < maxlen; len++)
+        {
+            if ((int_t)p_str[len] == '\0')
+            {
+                break;
+            }
+        }
+    }
+
+    return len;
+}
+
+/******************************************************************************
+* Function Name: SSIF_Strncmp
+* @brief         Compare two strings
+*
+*                Description:<br>
+*                
+* @param[in]     p_str1     :pointer of string1
+* @param[in]     p_str2     :pointer of string2
+* @param[in]     maxlen     :maximum length of comparison
+* @retval        zero       :strings are same.
+* @retval        non zero   :strings are different.
+******************************************************************************/
+static int32_t SSIF_Strncmp(const char_t p_str1[], const char_t p_str2[], const uint32_t maxlen)
+{
+    int32_t result = 0;
+    uint32_t index;
+
+    if ((NULL == p_str1) || (NULL == p_str2))
+    {
+        result = -1;
+    }
+    else
+    {
+        for (index = 0; index < maxlen; index++)
+        {
+            /* compare charctor */
+            result = ((int_t)p_str1[index]) - ((int_t)p_str2[index]);
+            if ((result != 0)
+                || ((int_t)p_str1[index] == '\0')
+                || ((int_t)p_str2[index] == '\0'))
+            {
+                /* "charactor mismatch" or "end of string" */
+                break;
+            }
+        }
+    }
+
+    return result;
+}
+
+/******************************************************************************
+* Function Name: SSIF_SetErrCode
+* @brief         Set error code to error code pointer.
+*
+*                Description:<br>
+*                If error code pointer is NULL, do nothing.
+* @param[in]     error_code :Error code.
+* @param[in,out] p_errno    :Pointer of set error code.
+* @retval        none
+******************************************************************************/
+static void SSIF_SetErrCode(const int_t error_code, int32_t* const p_errno)
+{
+    if (NULL != p_errno)
+    {
+        *p_errno = error_code;
+    }
+
+    return;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_src/ssif/ssif_int.c	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,354 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : ssif_int.c
+* $Rev: 891 $
+* $Date:: 2014-06-27 10:40:52 +0900#$
+* Description : SSIF driver interrupt functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "ssif.h"
+#include "ssif_int.h"
+#include "Renesas_RZ_A1.h"
+#include "gic.h"
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define SSIF_INT_PER_CH     (4u)
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+/******************************************************************************
+ Function prototypes
+ *****************************************************************************/
+
+static void SSIF_ERI0_Handler(void);
+static void SSIF_ERI1_Handler(void);
+static void SSIF_ERI2_Handler(void);
+static void SSIF_ERI3_Handler(void);
+static void SSIF_ERI4_Handler(void);
+static void SSIF_ERI5_Handler(void);
+
+static void SSIF_ERI_Handler(const uint32_t ssif_ch);
+
+/******************************************************************************
+* Function Name: SSIF_InterruptInit
+* @brief         Initialize interrupt setting for SSIF channel.
+*
+*                Description:<br>
+*                Enable interrupt and register interrupt handler.
+* @param[in]     ssif_ch    :SSIF channel
+* @param[in]     int_level  :GIC priority level of interrupt
+* @retval        none
+******************************************************************************/
+void SSIF_InterruptInit(const uint32_t ssif_ch, const uint8_t int_level)
+{
+    uint32_t ret;
+
+    switch (ssif_ch)
+    {
+        case SSIF_CHNUM_0:
+            ret = InterruptHandlerRegister(SSII0_IRQn, &SSIF_ERI0_Handler);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            GIC_SetPriority(SSII0_IRQn, int_level);
+            GIC_SetPriority(SSIRXI0_IRQn, int_level);
+            GIC_SetPriority(SSITXI0_IRQn, int_level);
+            GIC_EnableIRQ(SSII0_IRQn);
+            GIC_EnableIRQ(SSIRXI0_IRQn);
+            GIC_EnableIRQ(SSITXI0_IRQn);
+            break;
+        case SSIF_CHNUM_1:
+            ret = InterruptHandlerRegister(SSII1_IRQn, &SSIF_ERI1_Handler);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            GIC_SetPriority(SSII1_IRQn, int_level);
+            GIC_SetPriority(SSIRXI1_IRQn, int_level);
+            GIC_SetPriority(SSITXI1_IRQn, int_level);
+            GIC_EnableIRQ(SSII1_IRQn);
+            GIC_EnableIRQ(SSIRXI1_IRQn);
+            GIC_EnableIRQ(SSITXI1_IRQn);
+            break;
+        case SSIF_CHNUM_2:
+            ret = InterruptHandlerRegister(SSII2_IRQn, &SSIF_ERI2_Handler);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            GIC_SetPriority(SSII2_IRQn, int_level);
+            GIC_SetPriority(SSIRTI2_IRQn, int_level);
+            GIC_EnableIRQ(SSII2_IRQn);
+            GIC_EnableIRQ(SSIRTI2_IRQn);
+            break;
+        case SSIF_CHNUM_3:
+            ret = InterruptHandlerRegister(SSII3_IRQn, &SSIF_ERI3_Handler);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            GIC_SetPriority(SSII3_IRQn, int_level);
+            GIC_SetPriority(SSIRXI3_IRQn, int_level);
+            GIC_SetPriority(SSITXI3_IRQn, int_level);
+            GIC_EnableIRQ(SSII3_IRQn);
+            GIC_EnableIRQ(SSIRXI3_IRQn);
+            GIC_EnableIRQ(SSITXI3_IRQn);
+            break;
+        case SSIF_CHNUM_4:
+            ret = InterruptHandlerRegister(SSII4_IRQn, &SSIF_ERI4_Handler);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            GIC_SetPriority(SSII4_IRQn, int_level);
+            GIC_SetPriority(SSIRTI4_IRQn, int_level);
+            GIC_EnableIRQ(SSII4_IRQn);
+            GIC_EnableIRQ(SSIRTI4_IRQn);
+            break;
+        case SSIF_CHNUM_5:
+            ret = InterruptHandlerRegister(SSII5_IRQn, &SSIF_ERI5_Handler);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            GIC_SetPriority(SSII5_IRQn, int_level);
+            GIC_SetPriority(SSIRXI5_IRQn, int_level);
+            GIC_SetPriority(SSITXI5_IRQn, int_level);
+            GIC_EnableIRQ(SSII5_IRQn);
+            GIC_EnableIRQ(SSIRXI5_IRQn);
+            GIC_EnableIRQ(SSITXI5_IRQn);
+            break;
+        /* ->IPA R3.5.2 : There is nothing to do when unusual conditons. */
+        default:
+            /* NON_NOTICE_ASSERT: Illegal channel number */
+            break;
+        /* <-IPA R3.5.2 */
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_InterruptShutdown
+* @brief         Uninitialize interrupt setting for SSIF channel.
+*
+*                Description:<br>
+*                Disable interrupt and unregister interrupt handler 
+* @param[in]     ssif_ch    :SSIF channel
+* @retval        none
+******************************************************************************/
+void SSIF_InterruptShutdown(const uint32_t ssif_ch)
+{
+    uint32_t ret;
+
+    switch (ssif_ch)
+    {
+        case SSIF_CHNUM_0:
+            GIC_DisableIRQ(SSII0_IRQn);
+            GIC_DisableIRQ(SSIRXI0_IRQn);
+            GIC_DisableIRQ(SSITXI0_IRQn);
+            ret = InterruptHandlerUnregister(SSII0_IRQn);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            break;
+        case SSIF_CHNUM_1:
+            GIC_DisableIRQ(SSII1_IRQn);
+            GIC_DisableIRQ(SSIRXI1_IRQn);
+            GIC_DisableIRQ(SSITXI1_IRQn);
+            ret = InterruptHandlerUnregister(SSII1_IRQn);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            break;
+        case SSIF_CHNUM_2:
+            GIC_DisableIRQ(SSII2_IRQn);
+            GIC_DisableIRQ(SSIRTI2_IRQn);
+            ret = InterruptHandlerUnregister(SSII2_IRQn);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            break;
+        case SSIF_CHNUM_3:
+            GIC_DisableIRQ(SSII3_IRQn);
+            GIC_DisableIRQ(SSIRXI3_IRQn);
+            GIC_DisableIRQ(SSITXI3_IRQn);
+            ret = InterruptHandlerUnregister(SSII3_IRQn);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            break;
+        case SSIF_CHNUM_4:
+            GIC_DisableIRQ(SSII4_IRQn);
+            GIC_DisableIRQ(SSIRTI4_IRQn);
+            ret = InterruptHandlerUnregister(SSII4_IRQn);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            break;
+        case SSIF_CHNUM_5:
+            GIC_DisableIRQ(SSII5_IRQn);
+            GIC_DisableIRQ(SSIRXI5_IRQn);
+            GIC_DisableIRQ(SSITXI5_IRQn);
+            ret = InterruptHandlerUnregister(SSII5_IRQn);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            break;
+        /* ->IPA R3.5.2 : There is nothing to do when unusual conditons. */
+        default:
+            /* NON_NOTICE_ASSERT: Illegal channel number */
+            break;
+        /* <-IPA R3.5.2 */
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_EnableErrorInterrupt
+* @brief         Enable the SSIF channel error interrupt
+*
+*                Description:<br>
+*                
+* @param[in]     ssif_ch    :SSIF channel
+* @retval        none
+******************************************************************************/
+void SSIF_EnableErrorInterrupt(const uint32_t ssif_ch)
+{
+    /* clear error status */
+    g_ssireg[ssif_ch]->SSISR = 0u;
+
+    /* enable error interrupt */
+    g_ssireg[ssif_ch]->SSICR |= SSIF_CR_INT_ERR_MASK;
+ 
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_DisableErrorInterrupt
+* @brief         Disable the SSIF channel error interrupt
+*
+*                Description:<br>
+*                
+* @param[in]     ssif_ch    :SSIF channel
+* @retval        none
+******************************************************************************/
+void SSIF_DisableErrorInterrupt(const uint32_t ssif_ch)
+{
+    /* disable error interrupt */
+    g_ssireg[ssif_ch]->SSICR &= ~(SSIF_CR_INT_ERR_MASK);
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_ERI<n>_Handler
+* @brief         SSIF error interrupt handler per channel
+*
+*                Description:<br>
+*                
+* @param         none
+* @retval        none
+******************************************************************************/
+
+static void SSIF_ERI0_Handler(void)
+{
+    SSIF_ERI_Handler(SSIF_CHNUM_0);
+    return;
+}
+
+static void SSIF_ERI1_Handler(void)
+{
+    SSIF_ERI_Handler(SSIF_CHNUM_1);
+    return;
+}
+
+static void SSIF_ERI2_Handler(void)
+{
+    SSIF_ERI_Handler(SSIF_CHNUM_2);
+    return;
+}
+
+static void SSIF_ERI3_Handler(void)
+{
+    SSIF_ERI_Handler(SSIF_CHNUM_3);
+    return;
+}
+
+static void SSIF_ERI4_Handler(void)
+{
+    SSIF_ERI_Handler(SSIF_CHNUM_4);
+    return;
+}
+
+static void SSIF_ERI5_Handler(void)
+{
+    SSIF_ERI_Handler(SSIF_CHNUM_5);
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_ERI_Handler
+* @brief         SSIF error interrupt handler common function
+*
+*                Description:<br>
+*                
+* @param[in]     ssif_ch    :SSIF channel
+* @retval        none
+******************************************************************************/
+
+static void SSIF_ERI_Handler(const uint32_t ssif_ch)
+{
+    ssif_info_ch_t* const p_info_ch = &g_ssif_info_drv.info_ch[ssif_ch];
+
+    if (0u != (g_ssireg[ssif_ch]->SSISR & SSIF_SR_INT_ERR_MASK))
+    {
+        /* Restart or Callback */
+        SSIF_ErrorRecovery(p_info_ch);
+    }
+
+    return;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_src/ssif/ssif_int.h	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,61 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/******************************************************************************
+* File Name    : ssif_int.h
+* $Rev: 891 $
+* $Date:: 2014-06-27 10:40:52 +0900#$
+* Description  : SSIF driver interrupt functions header
+******************************************************************************/
+
+#ifndef SSIF_INT_H
+#define SSIF_INT_H
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "r_typedefs.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+
+/******************************************************************************
+ Function Prototypes
+ *****************************************************************************/
+void SSIF_InterruptInit(const uint32_t ssif_ch, const uint8_t int_level);
+void SSIF_InterruptShutdown(const uint32_t ssif_ch);
+
+void SSIF_EnableErrorInterrupt(const uint32_t ssif_ch);
+void SSIF_DisableErrorInterrupt(const uint32_t ssif_ch);
+
+#endif /* SSIF_INT_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_src/ssif/ssif_ver.c	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,72 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         ssif_ver.c
+* $Rev: 1070 $
+* $Date:: 2014-08-21 14:04:31 +0900#$
+* @brief        SSIF Driver get verion function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "cmsis_os.h"
+#include "ssif_if.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* Ex. V2.12 -> MAJOR=2, MINOR=12 */
+#define SSIF_DRV_VER_MAJOR  (2u)
+#define SSIF_DRV_VER_MINOR  (1u)
+
+#define SSIF_DRV_VER_MASK   (0xFFu)
+#define SSIF_DRV_VER_SHIFT  (8u)
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SSIF_GetVersion
+* @brief         Get SSIF driver version.
+*
+*                Description:<br>
+*                
+* @param         none
+* @retval        driver version -
+*                    upper 8bit=MAJOR
+*                    lower 8bit=MINOR
+******************************************************************************/
+uint16_t R_SSIF_GetVersion(void)
+{
+    const uint16_t version =
+        ((SSIF_DRV_VER_MAJOR & SSIF_DRV_VER_MASK) << SSIF_DRV_VER_SHIFT)
+        | (SSIF_DRV_VER_MINOR & SSIF_DRV_VER_MASK);
+
+    return version;
+}
+/******************************************************************************
+End of function R_SSIF_GetVersion
+******************************************************************************/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/version.txt	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,1 @@
+V2.02
\ No newline at end of file

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api/R_BSP_SerialFamily.h	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,126 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#ifndef R_BSP_SERIAL_H
+#define R_BSP_SERIAL_H
+
+#include <stdint.h>
+#include "rtos.h"
+
+typedef void (*rbsp_notify_func_t)(void * p_data, int32_t result, void * p_app_data);
+
+typedef struct {
+    rbsp_notify_func_t  p_notify_func;
+    void *              p_app_data;
+} rbsp_data_conf_t;
+
+/**
+ * A class to communicate a R_BSP_SerialFamily
+ */
+class R_BSP_SerialFamily {
+
+public:
+
+    /** Write count bytes to the file associated
+     *
+     * @param p_data Location of the data.
+     * @param data_size Number of bytes to write.
+     * @param p_data_conf Asynchronous control block structure.
+     * @return Number of bytes written on success. negative number on error.
+     */
+    int32_t write(void * const p_data, uint32_t data_size, const rbsp_data_conf_t * const p_data_conf = NULL);
+
+    /** Read count bytes to the file associated
+     *
+     * @param p_data Location of the data.
+     * @param data_size Number of bytes to read.
+     * @param p_data_conf Asynchronous control block structure.
+     * @return Number of bytes read on success. negative number on error.
+     */
+    int32_t read(void * const p_data, uint32_t data_size, const rbsp_data_conf_t * const p_data_conf = NULL);
+
+protected:
+
+    /** Constructor
+     *
+     */
+    R_BSP_SerialFamily();
+
+    /** Destructor
+     *
+     */
+    virtual ~R_BSP_SerialFamily();
+
+    /** Write init
+     *
+     * @param handle channel handle.
+     * @param p_func_a Pointer of write function.
+     * @param max_buff_num The upper limit of write buffer.
+     */
+    void write_init(void * handle, void * p_func_a, int32_t max_buff_num = 16) {
+        init(&write_ctl, handle, p_func_a, max_buff_num);
+    };
+
+    /** Read init
+     *
+     * @param handle channel handle.
+     * @param p_func_a Pointer of read function.
+     * @param max_buff_num The upper limit of read buffer.
+     */
+    void read_init(void * handle, void * p_func_a, int32_t max_buff_num = 16) {
+        init(&read_ctl, handle, p_func_a, max_buff_num);
+    };
+private:
+    typedef struct {
+        rbsp_notify_func_t  p_cb_func;
+        void *              p_cb_data;
+        Semaphore *         p_sem;
+        void *              p_aio;
+    } rbsp_sival_t;
+
+    typedef struct {
+        void *              ch_handle;
+        void *              p_async_func;
+        void *              p_aio_top;
+        int32_t             index;
+        rbsp_sival_t *      p_sival_top;
+        Semaphore *         p_sem_ctl;
+        int32_t             MaxNum;
+    } rbsp_serial_ctl_t;
+
+    typedef struct {
+        Semaphore *         p_sem;
+        int32_t             result;
+    } rbsp_sync_t;
+
+    void init(rbsp_serial_ctl_t * p_ctl, void * handle, void * p_func_a, int32_t max_buff_num);
+    static int32_t sync_trans(rbsp_serial_ctl_t * p_ctl, void * const p_data, uint32_t data_size);
+    static void callback_sync_trans(void * p_data, int32_t result, void * p_app_data);
+    static int32_t aio_trans(rbsp_serial_ctl_t * const p_ctl, void * const p_data, uint32_t data_size,
+                             const rbsp_data_conf_t * const p_data_conf);
+    static void callback_aio_trans(union sigval signo);
+
+    rbsp_serial_ctl_t write_ctl;
+    rbsp_serial_ctl_t read_ctl;
+};
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api/R_BSP_Ssif.h	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,77 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#ifndef R_BSP_SSIF_H
+#define R_BSP_SSIF_H
+
+#include <stdint.h>
+#include "R_BSP_SerialFamily.h"
+#include "R_BSP_SsifDef.h"
+#include "rtos.h"
+#include "ssif_api.h"
+
+/** A class to communicate a SSIF
+ *
+ */
+class SSIF : public R_BSP_SerialFamily {
+
+public:
+
+    /** Constructor
+     *
+     * @param sck SSIF serial bit clock
+     * @param ws  SSIF word selection
+     * @param tx  SSIF serial data output
+     * @param rx  SSIF serial data input
+     * @param int_level     Interupt priority (SSIF)
+     * @param max_write_num The upper limit of write buffer (SSIF)
+     * @param max_read_num  The upper limit of read buffer (SSIF)
+     */
+    SSIF(PinName sck, PinName ws, PinName tx, PinName rx, uint8_t int_level = 0x80, int32_t max_write_num = 16, int32_t max_read_num = 16);
+
+    /** Destructor
+     *
+     */
+    virtual ~SSIF();
+
+    /** Save configuration to the SSIF driver
+     *
+     * @param p_ch_cfg SSIF channel configuration parameter
+     * @return true = success, false = failure
+     */
+    bool ConfigChannel(const ssif_channel_cfg_t* const p_ch_cfg);
+
+    /** Get a value of SSISR register
+     *
+     * @param p_status Pointer of status value
+     * @return true = success, false = failure
+     */
+    bool GetStatus(uint32_t* const p_status);
+
+private:
+    void * instance;
+    void * ch_handle;
+    ssif_channel_cfg_t  ssif_cfg;
+    int32_t ssif_ch;
+};
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api/R_BSP_SsifDef.h	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,216 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#ifndef R_BSP_SSIF_DEF_H
+#define R_BSP_SSIF_DEF_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/******************************************************************************
+ Defines
+ *****************************************************************************/
+
+/******************************************************************************
+ Constant Macros
+ *****************************************************************************/
+#define SSIF_NUM_CHANS       (6u)    /**< Number of SSIF channels */
+
+#define SSIF_CFG_DISABLE_ROMDEC_DIRECT (0x0u)        /* Disable SSIRDR->STRMDIN0 route */
+#define SSIF_CFG_ENABLE_ROMDEC_DIRECT  (0xDEC0DEC1u) /* Enable  SSIRDR->STRMDIN0 route */
+
+/******************************************************************************
+ Function Macros
+ *****************************************************************************/
+
+/******************************************************************************
+ Enumerated Types
+ *****************************************************************************/
+
+/** SSICR:CKS(Clock source for oversampling) */
+typedef enum
+{
+    SSIF_CFG_CKS_AUDIO_X1  = 0,  /**< select AUDIO_X1   */
+    SSIF_CFG_CKS_AUDIO_CLK = 1   /**< select AUIDIO_CLK */
+} ssif_chcfg_cks_t; 
+
+/** SSICR:CHNL(Audio channels per system word) */
+typedef enum
+{
+    SSIF_CFG_MULTI_CH_1 = 0,     /**< 1ch within systemword (on tdm=0) */
+    SSIF_CFG_MULTI_CH_2 = 1,     /**< 2ch within systemword (on tdm=0) */
+    SSIF_CFG_MULTI_CH_3 = 2,     /**< 3ch within systemword (on tdm=0) */
+    SSIF_CFG_MULTI_CH_4 = 3      /**< 4ch within systemword (on tdm=0) */
+} ssif_chcfg_multi_ch_t;
+
+/** SSICR:DWL(Data word length) */
+typedef enum
+{
+    SSIF_CFG_DATA_WORD_8  = 0,   /**< Data word length 8  */
+    SSIF_CFG_DATA_WORD_16 = 1,   /**< Data word length 16 */
+    SSIF_CFG_DATA_WORD_18 = 2,   /**< Data word length 18 */
+    SSIF_CFG_DATA_WORD_20 = 3,   /**< Data word length 20 */
+    SSIF_CFG_DATA_WORD_22 = 4,   /**< Data word length 22 */
+    SSIF_CFG_DATA_WORD_24 = 5,   /**< Data word length 24 */
+    SSIF_CFG_DATA_WORD_32 = 6    /**< Data word length 32 */
+} ssif_chcfg_data_word_t;
+
+/** SSICR:SWL(System word length) */
+typedef enum
+{
+    SSIF_CFG_SYSTEM_WORD_8   = 0,    /**< System word length 8   */
+    SSIF_CFG_SYSTEM_WORD_16  = 1,    /**< System word length 16  */
+    SSIF_CFG_SYSTEM_WORD_24  = 2,    /**< System word length 24  */
+    SSIF_CFG_SYSTEM_WORD_32  = 3,    /**< System word length 32  */
+    SSIF_CFG_SYSTEM_WORD_48  = 4,    /**< System word length 48  */
+    SSIF_CFG_SYSTEM_WORD_64  = 5,    /**< System word length 64  */
+    SSIF_CFG_SYSTEM_WORD_128 = 6,    /**< System word length 128 */
+    SSIF_CFG_SYSTEM_WORD_256 = 7     /**< System word length 256 */
+} ssif_chcfg_system_word_t;
+
+/** SSICR:SCKP(Clock polarity) */
+typedef enum
+{
+    SSIF_CFG_FALLING = 0,    /**< Falling edge */
+    SSIF_CFG_RISING  = 1     /**< Rising edge  */
+} ssif_chcfg_clock_pol_t;
+
+/** SSICR:SWSP(Word select polarity) */
+typedef enum
+{
+    SSIF_CFG_WS_LOW  = 0,    /**< Low for ther 1st channel(not TDM) */
+    SSIF_CFG_WS_HIGH = 1     /**< High for the 1st channel(not TDM) */
+} ssif_chcfg_ws_pol_t;
+
+/** SSICR:SPDP(Serial padding polarity) */
+typedef enum
+{
+    SSIF_CFG_PADDING_LOW  = 0,   /**< Padding bits are low  */
+    SSIF_CFG_PADDING_HIGH = 1    /**< Padding bits are high */
+} ssif_chcfg_padding_pol_t;
+
+/** SSICR:SDTA(Serial data alignment) */
+typedef enum
+{
+    SSIF_CFG_DATA_FIRST    = 0,  /**< Data first         */
+    SSIF_CFG_PADDING_FIRST = 1   /**< Padding bits first */
+} ssif_chcfg_serial_alignment_t;
+
+/** SSICR:PDTA(Parallel data alignment) */
+typedef enum
+{
+    SSIF_CFG_LEFT  = 0,  /**< Left aligned  */
+    SSIF_CFG_RIGHT = 1   /**< Right aligned */
+} ssif_chcfg_parallel_alignment_t;
+
+/** SSICR:DEL(Serial data delay) */
+typedef enum
+{
+    SSIF_CFG_DELAY    = 0,   /**< 1 clock delay */
+    SSIF_CFG_NO_DELAY = 1    /**< No delay      */
+} ssif_chcfg_ws_delay_t;
+
+/** SSICR:CKDV(Serial oversampling clock division ratio) */
+typedef enum
+{
+    SSIF_CFG_CKDV_BITS_1   = 0,
+    SSIF_CFG_CKDV_BITS_2   = 1,
+    SSIF_CFG_CKDV_BITS_4   = 2,
+    SSIF_CFG_CKDV_BITS_8   = 3,
+    SSIF_CFG_CKDV_BITS_16  = 4,
+    SSIF_CFG_CKDV_BITS_32  = 5,
+    SSIF_CFG_CKDV_BITS_64  = 6,
+    SSIF_CFG_CKDV_BITS_128 = 7,
+    SSIF_CFG_CKDV_BITS_6   = 8,
+    SSIF_CFG_CKDV_BITS_12  = 9,
+    SSIF_CFG_CKDV_BITS_24  = 10,
+    SSIF_CFG_CKDV_BITS_48  = 11,
+    SSIF_CFG_CKDV_BITS_96  = 12
+} ssif_chcfg_ckdv_t;
+
+
+/** SNCR:SSIxNL(Serial sound interface channel x noise canceler enable) */
+typedef enum
+{
+    SSIF_CFG_DISABLE_NOISE_CANCEL = 0, /**< Not use noise cancel function */
+    SSIF_CFG_ENABLE_NOISE_CANCEL  = 1  /**< Use noise cancel function     */
+} ssif_chcfg_noise_cancel_t;
+
+
+/** SSITDMR:TDM(TDM mode) */
+typedef enum
+{
+    SSIF_CFG_DISABLE_TDM = 0,   /**< not TDM mode */
+    SSIF_CFG_ENABLE_TDM  = 1    /**< set TDM mode */
+} ssif_chcfg_tdm_t;
+
+/******************************************************************************
+ Structures
+ *****************************************************************************/
+
+typedef struct
+{
+    uint32_t    mode;               /* Enable/Disable SSIRDR->STRMDIN0 route */
+    void        (*p_cbfunc)(void);  /* SSIF error callback function          */
+} ssif_chcfg_romdec_t;
+
+/**< This structure contains the configuration settings */
+typedef struct
+{
+    bool                            enabled;             /* The enable flag for the channel       */
+    uint8_t                         int_level;           /* Interrupt priority for the channel    */
+    bool                            slave_mode;          /* Mode of operation                     */
+    uint32_t                        sample_freq;         /* Audio Sampling frequency(Hz)          */
+    ssif_chcfg_cks_t                clk_select;          /* SSICR-CKS : Audio clock select        */
+    ssif_chcfg_multi_ch_t           multi_ch;            /* SSICR-CHNL: Audio channels per system word */
+    ssif_chcfg_data_word_t          data_word;           /* SSICR-DWL : Data word length          */
+    ssif_chcfg_system_word_t        system_word;         /* SSICR-SWL : System word length        */
+    ssif_chcfg_clock_pol_t          bclk_pol;            /* SSICR-SCKP: Bit Clock polarity        */
+    ssif_chcfg_ws_pol_t             ws_pol;              /* SSICR-SWSP: Word Clock polarity       */
+    ssif_chcfg_padding_pol_t        padding_pol;         /* SSICR-SPDP: Padding polarity          */
+    ssif_chcfg_serial_alignment_t   serial_alignment;    /* SSICR-SDTA: Serial data alignment     */
+    ssif_chcfg_parallel_alignment_t parallel_alignment;  /* SSICR-PDTA: Parallel data alignment   */
+    ssif_chcfg_ws_delay_t           ws_delay;            /* SSICR-DEL : Serial clock delay        */
+    ssif_chcfg_noise_cancel_t       noise_cancel;        /* GPIO-SNCR : Noise cancel              */
+    ssif_chcfg_tdm_t                tdm_mode;            /* SSITDMR-TDM: TDM mode                 */
+    ssif_chcfg_romdec_t             romdec_direct;       /* DMA : SSIRDR->STRMDIN0 route settings */
+} ssif_channel_cfg_t;
+
+/******************************************************************************
+ IOCTLS
+ *****************************************************************************/
+
+#define SSIF_CONFIG_CHANNEL        (7)
+#define SSIF_GET_STATUS           (13)
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* R_BSP_SSIF_DEF_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/common/R_BSP_SerialFamily.cpp	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,158 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#include "cmsis_os.h"
+#include "r_typedefs.h"
+#include "r_errno.h"
+#include "misratypes.h"
+#include "aioif.h"
+#include "R_BSP_SerialFamily.h"
+
+typedef int32_t (*rbsp_read_write_a_func_t)(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno);
+
+R_BSP_SerialFamily::R_BSP_SerialFamily() {
+}
+
+R_BSP_SerialFamily::~R_BSP_SerialFamily() {
+    if (write_ctl.MaxNum != 0) {
+        delete [] (rbsp_sival_t *)write_ctl.p_sival_top;
+        delete [] (AIOCB *)write_ctl.p_aio_top;
+        delete write_ctl.p_sem_ctl;
+    }
+    if (read_ctl.MaxNum != 0) {
+        delete [] (rbsp_sival_t *)read_ctl.p_sival_top;
+        delete [] (AIOCB *)read_ctl.p_aio_top;
+        delete read_ctl.p_sem_ctl;
+    }
+}
+
+void R_BSP_SerialFamily::init(rbsp_serial_ctl_t * p_ctl, void * handle, void * p_func_a, int32_t max_buff_num) {
+    if (handle != NULL) {
+        p_ctl->ch_handle    = handle;
+        p_ctl->MaxNum       = max_buff_num;
+        p_ctl->p_aio_top    = NULL;
+        p_ctl->index        = 0;
+        p_ctl->p_async_func = p_func_a;
+        if (p_ctl->MaxNum != 0) {
+            p_ctl->p_sem_ctl    = new Semaphore(p_ctl->MaxNum);
+            p_ctl->p_aio_top    = new AIOCB[p_ctl->MaxNum];
+            p_ctl->p_sival_top  = new rbsp_sival_t[p_ctl->MaxNum];
+        }
+    }
+}
+
+int32_t R_BSP_SerialFamily::write(void * const p_data, uint32_t data_size, const rbsp_data_conf_t * const p_data_conf) {
+    if (p_data_conf == NULL) {
+        return sync_trans(&write_ctl, p_data, data_size);
+    } else {
+        return aio_trans(&write_ctl, p_data, data_size, p_data_conf);
+    }
+}
+
+int32_t R_BSP_SerialFamily::read(void * const p_data, uint32_t data_size, const rbsp_data_conf_t * const p_data_conf) {
+    if (p_data_conf == NULL) {
+        return sync_trans(&read_ctl, p_data, data_size);
+    } else {
+        return aio_trans(&read_ctl, p_data, data_size, p_data_conf);
+    }
+}
+
+/* static */ int32_t R_BSP_SerialFamily::sync_trans(rbsp_serial_ctl_t * p_ctl, void * const p_data, uint32_t data_size) {
+    rbsp_sync_t sync_info;
+    rbsp_data_conf_t data_conf;
+    Semaphore * p_sem_wait = new Semaphore(0);
+
+    if (p_sem_wait != NULL) {
+        sync_info.p_sem  = p_sem_wait;
+        sync_info.result = -1;
+
+        data_conf.p_notify_func = &callback_sync_trans;
+        data_conf.p_app_data    = &sync_info;
+
+        aio_trans(p_ctl, p_data, data_size, &data_conf);
+        p_sem_wait->wait(osWaitForever);
+        delete p_sem_wait;
+    }
+
+    return sync_info.result;
+}
+
+/* static */ void R_BSP_SerialFamily::callback_sync_trans(void * p_data, int32_t result, void * p_app_data) {
+    rbsp_sync_t * p_sync_info = (rbsp_sync_t *)p_app_data;
+
+    p_sync_info->result = result;
+    p_sync_info->p_sem->release();
+}
+
+/* static */ int32_t R_BSP_SerialFamily::aio_trans(rbsp_serial_ctl_t * const p_ctl,
+               void * const p_data, uint32_t data_size, const rbsp_data_conf_t * const p_data_conf) {
+    int32_t wk_errno;
+    AIOCB * p_rbsp_aio;
+    rbsp_sival_t * p_sival;
+    rbsp_read_write_a_func_t p_func = (rbsp_read_write_a_func_t)p_ctl->p_async_func;
+
+    if ((p_data_conf == NULL) || (p_data == NULL)) {
+        wk_errno = ENOSPC;
+    } else if (p_ctl->p_sem_ctl->wait(osWaitForever) == -1) {
+        wk_errno = EIO;
+    } else {
+        p_rbsp_aio = (AIOCB *)p_ctl->p_aio_top + p_ctl->index;
+        p_sival    = p_ctl->p_sival_top + p_ctl->index;
+
+        p_sival->p_cb_func     = p_data_conf->p_notify_func;
+        p_sival->p_cb_data     = p_data_conf->p_app_data;
+        p_sival->p_sem         = p_ctl->p_sem_ctl;
+        p_sival->p_aio         = p_rbsp_aio;
+
+        p_rbsp_aio->aio_fildes = 0;
+        p_rbsp_aio->aio_buf    = p_data;
+        p_rbsp_aio->aio_nbytes = data_size;
+        p_rbsp_aio->aio_offset = 0;
+        p_rbsp_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+        p_rbsp_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_sival;
+        p_rbsp_aio->aio_sigevent.sigev_notify_function = &callback_aio_trans;
+        p_func(p_ctl->ch_handle, p_rbsp_aio, &wk_errno);
+
+        if (wk_errno == ESUCCESS) {
+            if ((p_ctl->index + 1) >= p_ctl->MaxNum) {
+                p_ctl->index = 0;
+            } else {
+                p_ctl->index++;
+            }
+        } else {
+            p_ctl->p_sem_ctl->release();
+        }
+    }
+
+    return wk_errno;
+}
+
+/* static */ void R_BSP_SerialFamily::callback_aio_trans(union sigval signo) {
+    rbsp_sival_t * p_sival = (rbsp_sival_t *)signo.sival_ptr;
+    AIOCB * p_aio_result = (AIOCB *)p_sival->p_aio;
+
+    if ((p_sival->p_cb_func != NULL) && (p_aio_result != NULL)) {
+        p_sival->p_cb_func((void *)p_aio_result->aio_buf, p_aio_result->aio_return, p_sival->p_cb_data);
+    }
+    p_sival->p_sem->release();
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/common/R_BSP_Ssif.cpp	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,93 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#include "r_bsp_cmn.h"
+#include "R_BSP_Ssif.h"
+#include "ssif_if.h"
+
+SSIF::SSIF(PinName sck, PinName ws, PinName tx, PinName rx, uint8_t int_level, int32_t max_write_num, int32_t max_read_num) {
+    int32_t wk_errno;
+    int32_t wk_channel;
+    char_t  path_name[3];
+
+    wk_channel = ssif_init(sck, ws, tx, rx);
+    if (wk_channel != NC) {
+        R_BSP_CMN_Init();
+
+        ssif_ch      = wk_channel;
+        ch_handle    = 0;
+
+        ssif_cfg.enabled                = true;
+        ssif_cfg.int_level              = 0x78;
+        ssif_cfg.slave_mode             = true;
+        ssif_cfg.sample_freq            = 44100u;
+        ssif_cfg.clk_select             = SSIF_CFG_CKS_AUDIO_X1;
+        ssif_cfg.multi_ch               = SSIF_CFG_MULTI_CH_1;
+        ssif_cfg.data_word              = SSIF_CFG_DATA_WORD_16;
+        ssif_cfg.system_word            = SSIF_CFG_SYSTEM_WORD_32;
+        ssif_cfg.bclk_pol               = SSIF_CFG_FALLING;
+        ssif_cfg.ws_pol                 = SSIF_CFG_WS_LOW;
+        ssif_cfg.padding_pol            = SSIF_CFG_PADDING_LOW;
+        ssif_cfg.serial_alignment       = SSIF_CFG_DATA_FIRST;
+        ssif_cfg.parallel_alignment     = SSIF_CFG_LEFT;
+        ssif_cfg.ws_delay               = SSIF_CFG_DELAY;
+        ssif_cfg.noise_cancel           = SSIF_CFG_DISABLE_NOISE_CANCEL;
+        ssif_cfg.tdm_mode               = SSIF_CFG_DISABLE_TDM;
+        ssif_cfg.romdec_direct.mode     = SSIF_CFG_DISABLE_ROMDEC_DIRECT;
+        ssif_cfg.romdec_direct.p_cbfunc = NULL;
+
+        instance = R_SSIF_InitOne(ssif_ch, &ssif_cfg, &wk_errno);
+        if (wk_errno != -1) {
+            path_name[0] = '\\';
+            path_name[1] = 0x30 + ssif_ch;
+            path_name[2] = '\0';
+
+            ch_handle = (void *)R_SSIF_Open(instance, path_name, O_RDWR, 0, &wk_errno);
+            write_init(ch_handle, (void *)&R_SSIF_WriteAsync, max_write_num);
+            read_init(ch_handle, (void *)&R_SSIF_ReadAsync, max_read_num);
+        } else {
+            instance = NULL;
+        }
+    }
+}
+
+SSIF::~SSIF() {
+    // do nothing
+}
+
+bool SSIF::ConfigChannel(const ssif_channel_cfg_t* const p_ch_cfg) {
+    int32_t wk_errno;
+
+    R_SSIF_Ioctl(ch_handle, SSIF_CONFIG_CHANNEL, (void *)p_ch_cfg, &wk_errno);
+
+    return (wk_errno == ESUCCESS);
+}
+
+bool SSIF::GetStatus(uint32_t* const p_status) {
+    int32_t wk_errno;
+
+    R_SSIF_Ioctl(ch_handle, SSIF_CONFIG_CHANNEL, (void *)p_status, &wk_errno);
+
+    return (wk_errno == ESUCCESS);
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/Renesas_RZ_A1.h	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,25 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#include "MBRZA1H.h"
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/bsp_util.c	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,132 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         bsp_util.c
+* $Rev: 891 $
+* $Date:: 2014-06-27 10:40:52 +0900#$
+* @brief        BSP Utilities
+******************************************************************************/
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    rt_CMSIS.c
+ *      Purpose: CMSIS RTOS API
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used 
+ *    to endorse or promote products derived from this software without 
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "cmsis_os.h"
+#include "Renesas_RZ_A1.h"
+#include "bsp_util.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+extern uint32_t IRQNestLevel; /* Indicates whether inside an ISR, and the depth of nesting.  0 = not in ISR. */
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_ExceptionalMode
+* @brief         Get current context
+*
+*                Description:<br>
+*                
+* @param         none
+* @retval 0      Current context is non-task
+* @retval 1      Current context is task
+******************************************************************************/
+int32_t R_ExceptionalMode(void)
+{
+    int32_t ret = 0;
+
+    switch(__get_CPSR() & 0x1fu)
+    {
+    case MODE_USR:
+        break;
+    case MODE_SYS:
+        break;
+    case MODE_SVC:
+        if (IRQNestLevel == 0)
+        {
+            /* handling a regular service call */
+        }
+        else
+        {
+            /* handling an ISR in SVC mode */
+            ret = 1;
+        }
+        break;
+    default:
+        ret = 1;
+        break;
+    }
+    return ret;
+}
+
+/******************************************************************************
+End of file
+******************************************************************************/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/r_bsp_cmn.c	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,84 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#include <stdio.h>
+#include "dma_if.h"
+
+
+static bool_t dma_init_end = false;
+static dma_drv_init_t dma_init_param;
+void userdef_dma_error_callback(union sigval signo);
+static AIOCB dma_err_aio;
+
+int32_t R_BSP_CMN_Init(void) {
+    int32_t retval = ESUCCESS;
+
+    if (dma_init_end == false) {
+        dma_init_end = true;
+        /***********************************************************************/
+        /* Initialise DMA */
+        /***********************************************************************/
+
+        dma_init_param.channel[DMA_CH_0] = true;
+        dma_init_param.channel[DMA_CH_1] = true;
+        dma_init_param.channel[DMA_CH_2] = true;
+        dma_init_param.channel[DMA_CH_3] = true;
+        dma_init_param.channel[DMA_CH_4] = true;
+        dma_init_param.channel[DMA_CH_5] = true;
+        dma_init_param.channel[DMA_CH_6] = true;
+        dma_init_param.channel[DMA_CH_7] = true;
+        dma_init_param.channel[DMA_CH_8] = true;
+        dma_init_param.channel[DMA_CH_9] = true;
+        dma_init_param.channel[DMA_CH_10] = true;
+        dma_init_param.channel[DMA_CH_11] = true;
+        dma_init_param.channel[DMA_CH_12] = true;
+        dma_init_param.channel[DMA_CH_13] = true;
+        dma_init_param.channel[DMA_CH_14] = true;
+        dma_init_param.channel[DMA_CH_15] = true;
+
+        dma_err_aio.aio_sigevent.sigev_notify = SIGEV_THREAD;
+        dma_err_aio.aio_sigevent.sigev_notify_function = &userdef_dma_error_callback;
+        dma_init_param.p_aio = &dma_err_aio;
+
+        retval = R_DMA_Init(&dma_init_param, NULL);
+        if (retval != ESUCCESS) {
+            dma_init_end = false;
+        }
+    }
+
+    return retval;
+}
+
+/**************************************************************************//**
+* Function Name: userdef_dma_error_callback
+* @brief         DMA driver : error callback function
+*
+*                Description:<br>
+*                DMA error interrupt callback function
+* @param[in]     signo.sival_int : bitmap of error channel(bit0=ch0)
+* @retval        none
+******************************************************************************/
+void userdef_dma_error_callback(union sigval signo) {
+    printf("DMAERR MAP:0x%02x\n", signo.sival_int);
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/r_bsp_cmn.h	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,48 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+
+#ifndef R_BSP_CMN_H
+#define R_BSP_CMN_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+
+#include "cmsis_os.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/***********************************************************************************
+ Function Prototypes
+***********************************************************************************/
+extern int32_t R_BSP_CMN_Init(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* R_BSP_CMN_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/ssif_api.c	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,154 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#include "ssif_api.h"
+
+static const PinMap PinMap_SSIF_SCK[] = {
+//   pin      ch     func
+    {P2_8   , 0    , 4},
+    {P4_4   , 0    , 5},
+    {P3_4   , 1    , 3},
+    {P7_1   , 1    , 6},
+    {P10_12 , 1    , 2},
+    {P7_5   , 2    , 6},
+    {P9_5   , 2    , 3},
+    {P4_12  , 3    , 6},
+    {P7_8   , 3    , 2},
+    {P7_12  , 4    , 2},
+    {P8_12  , 4    , 8},
+    {P11_4  , 4    , 3},
+    {P2_4   , 5    , 4},
+    {P4_8   , 5    , 5},
+    {P8_8   , 5    , 8},
+    {NC     , NC   , 0}
+};
+
+static const PinMap PinMap_SSIF_WS[] = {
+//   pin      ch     func
+    {P2_9   , 0    , 4},
+    {P4_5   , 0    , 5},
+    {P3_5   , 1    , 3},
+    {P7_2   , 1    , 6},
+    {P10_13 , 1    , 2},
+    {P7_6   , 2    , 6},
+    {P9_6   , 2    , 3},
+    {P4_13  , 3    , 6},
+    {P7_9   , 3    , 2},
+    {P7_13  , 4    , 2},
+    {P8_13  , 4    , 8},
+    {P11_5  , 4    , 3},
+    {P2_5   , 5    , 4},
+    {P4_9   , 5    , 5},
+    {P8_9   , 5    , 8},
+    {NC     , NC   , 0}
+};
+
+static const PinMap PinMap_SSIF_TxD[] = {
+//   pin      ch     func
+    {P2_11  , 0    , 4},
+    {P4_7   , 0    , 5},
+    {P7_4   , 1    , 6},
+    {P10_15 , 1    , 2},
+    {P7_7   , 2    , 6},  /* SSIDATA2 */
+    {P9_7   , 2    , 3},  /* SSIDATA2 */
+    {P4_15  , 3    , 6},
+    {P7_11  , 3    , 2},
+    {P6_1   , 4    , 6},  /* SSIDATA4 */
+    {P7_14  , 4    , 2},  /* SSIDATA4 */
+    {P8_14  , 4    , 8},  /* SSIDATA4 */
+    {P11_6  , 4    , 3},  /* SSIDATA4 */
+    {P2_7   , 5    , 4},
+    {P4_11  , 5    , 5},
+    {P8_10  , 5    , 8},
+    {NC     , NC   , 0}
+};
+
+static const PinMap PinMap_SSIF_RxD[] = {
+//   pin      ch     func
+    {P2_10  , 0    , 4},
+    {P4_6   , 0    , 5},
+    {P3_7   , 1    , 3},
+    {P7_3   , 1    , 6},
+    {P10_14 , 1    , 2},
+    {P10_14 , 1    , 2},
+    {P7_7   , 2    , 6},  /* SSIDATA2 */
+    {P9_7   , 2    , 3},  /* SSIDATA2 */
+    {P4_14  , 3    , 6},
+    {P7_10  , 3    , 2},
+    {P7_10  , 3    , 2},
+    {P6_1   , 4    , 6},  /* SSIDATA4 */
+    {P7_14  , 4    , 2},  /* SSIDATA4 */
+    {P8_14  , 4    , 8},  /* SSIDATA4 */
+    {P11_6  , 4    , 3},  /* SSIDATA4 */
+    {P2_6   , 5    , 4},
+    {P4_10  , 5    , 5},
+    {NC     , NC   , 0}
+};
+
+static inline void ssif_power_enable(uint32_t ssif_ch) {
+    volatile uint8_t dummy;
+
+    switch (ssif_ch) {
+        case 0:
+            CPGSTBCR11 &= ~(0x20);
+            break;
+        case 1:
+            CPGSTBCR11 &= ~(0x10);
+            break;
+        case 2:
+            CPGSTBCR11 &= ~(0x08);
+            break;
+        case 3:
+            CPGSTBCR11 &= ~(0x04);
+            break;
+        case 4:
+            CPGSTBCR11 &= ~(0x02);
+            break;
+        case 5:
+            CPGSTBCR11 &= ~(0x01);
+            break;
+    }
+    dummy = CPGSTBCR11;
+}
+
+int32_t ssif_init(PinName sck, PinName ws, PinName tx, PinName rx) {
+    /* determine the ssif to use */
+    uint32_t ssif_sck = pinmap_peripheral(sck, PinMap_SSIF_SCK);
+    uint32_t ssif_ws  = pinmap_peripheral(ws,  PinMap_SSIF_WS);
+    uint32_t ssif_tx  = pinmap_peripheral(tx,  PinMap_SSIF_TxD);
+    uint32_t ssif_rx  = pinmap_peripheral(rx,  PinMap_SSIF_RxD);
+    uint32_t ssif_ch  = pinmap_merge(ssif_tx, ssif_rx);
+
+    if ((ssif_ch == ssif_sck) && (ssif_ch == ssif_ws)) {
+        ssif_power_enable(ssif_ch);
+        pinmap_pinout(sck, PinMap_SSIF_SCK);
+        pinmap_pinout(ws,  PinMap_SSIF_WS);
+        pinmap_pinout(tx,  PinMap_SSIF_TxD);
+        pinmap_pinout(rx,  PinMap_SSIF_RxD);
+    } else {
+        ssif_ch = NC;
+    }
+
+    return (int32_t)ssif_ch;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/ssif_api.h	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,39 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#ifndef MBED_SSIF_API_H
+#define MBED_SSIF_API_H
+
+#include "pinmap.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int32_t ssif_init(PinName sck, PinName ws, PinName tx, PinName rx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif