RZ/A1H CMSIS-RTOS RTX BSP for GR-PEACH.

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Fork of R_BSP by Daiki Kato

SSIF

The SSIF driver implements transmission and reception functionality which uses the SSIF in the RZ/A Series.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Ssif.h"
00003 #include "sine_data_tbl.h"
00004 
00005 //I2S send only, The upper limit of write buffer is 8.
00006 R_BSP_Ssif ssif(P4_4, P4_5, P4_7, P4_6, 0x80, 8, 0);
00007 
00008 static void callback_ssif_write_end(void * p_data, int32_t result, void * p_app_data) {
00009     if (result < 0) {
00010         printf("ssif write callback error %d\n", result);
00011     }
00012 }
00013 
00014 int main() {
00015     rbsp_data_conf_t   ssif_write_end_conf = {&callback_ssif_write_end, NULL};
00016     ssif_channel_cfg_t ssif_cfg;
00017     int32_t            result;
00018 
00019     //I2S Master, 44.1kHz, 16bit, 2ch
00020     ssif_cfg.enabled                = true;
00021     ssif_cfg.int_level              = 0x78;
00022     ssif_cfg.slave_mode             = false;
00023     ssif_cfg.sample_freq            = 44100u;
00024     ssif_cfg.clk_select             = SSIF_CFG_CKS_AUDIO_X1;
00025     ssif_cfg.multi_ch               = SSIF_CFG_MULTI_CH_1;
00026     ssif_cfg.data_word              = SSIF_CFG_DATA_WORD_16;
00027     ssif_cfg.system_word            = SSIF_CFG_SYSTEM_WORD_32;
00028     ssif_cfg.bclk_pol               = SSIF_CFG_FALLING;
00029     ssif_cfg.ws_pol                 = SSIF_CFG_WS_LOW;
00030     ssif_cfg.padding_pol            = SSIF_CFG_PADDING_LOW;
00031     ssif_cfg.serial_alignment       = SSIF_CFG_DATA_FIRST;
00032     ssif_cfg.parallel_alignment     = SSIF_CFG_LEFT;
00033     ssif_cfg.ws_delay               = SSIF_CFG_DELAY;
00034     ssif_cfg.noise_cancel           = SSIF_CFG_DISABLE_NOISE_CANCEL;
00035     ssif_cfg.tdm_mode               = SSIF_CFG_DISABLE_TDM;
00036     ssif_cfg.romdec_direct.mode     = SSIF_CFG_DISABLE_ROMDEC_DIRECT;
00037     ssif_cfg.romdec_direct.p_cbfunc = NULL;
00038     result = ssif.ConfigChannel(&ssif_cfg);
00039     if (result < 0) {
00040         printf("ssif config error %d\n", result);
00041     }
00042 
00043     while (1) {
00044         //The upper limit of write buffer is 8.
00045         result = ssif.write((void *)sin_data_44100Hz_16bit_2ch, 
00046                             sizeof(sin_data_44100Hz_16bit_2ch), &ssif_write_end_conf);
00047         if (result < 0) {
00048             printf("ssif write api error %d\n", result);
00049         }
00050     }
00051 }

API

Import library

Public Member Functions

R_BSP_Ssif (PinName sck, PinName ws, PinName tx, PinName rx, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor.
virtual ~R_BSP_Ssif ()
Destructor.
int32_t GetSsifChNo (void)
Get a value of SSIF channel number.
bool ConfigChannel (const ssif_channel_cfg_t *const p_ch_cfg)
Save configuration to the SSIF driver.
bool GetStatus (uint32_t *const p_status)
Get a value of SSISR register.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Interface

See the Pinout page for more details


SCUX

The SCUX module consists of a sampling rate converter, a digital volume unit, and a mixer.
The SCUX driver can perform asynchronous and synchronous sampling rate conversions using the sampling rate converter. The SCUX driver uses the DMA transfer mode to input and output audio data.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Scux.h"
00003 #include "USBHostMSD.h"
00004 
00005 R_BSP_Scux scux(SCUX_CH_0);
00006 
00007 #define WRITE_SAMPLE_NUM (128)
00008 #define READ_SAMPLE_NUM  (2048)
00009 
00010 const short sin_data[WRITE_SAMPLE_NUM] = {
00011  0x0000,0x0000,0x0C8C,0x0C8C,0x18F9,0x18F9,0x2528,0x2528
00012 ,0x30FB,0x30FB,0x3C56,0x3C56,0x471C,0x471C,0x5133,0x5133
00013 ,0x5A82,0x5A82,0x62F1,0x62F1,0x6A6D,0x6A6D,0x70E2,0x70E2
00014 ,0x7641,0x7641,0x7A7C,0x7A7C,0x7D89,0x7D89,0x7F61,0x7F61
00015 ,0x7FFF,0x7FFF,0x7F61,0x7F61,0x7D89,0x7D89,0x7A7C,0x7A7C
00016 ,0x7641,0x7641,0x70E2,0x70E2,0x6A6D,0x6A6D,0x62F1,0x62F1
00017 ,0x5A82,0x5A82,0x5133,0x5133,0x471C,0x471C,0x3C56,0x3C56
00018 ,0x30FB,0x30FB,0x2528,0x2528,0x18F9,0x18F9,0x0C8C,0x0C8C
00019 ,0x0000,0x0000,0xF374,0xF374,0xE707,0xE707,0xDAD8,0xDAD8
00020 ,0xCF05,0xCF05,0xC3AA,0xC3AA,0xB8E4,0xB8E4,0xAECD,0xAECD
00021 ,0xA57E,0xA57E,0x9D0F,0x9D0F,0x9593,0x9593,0x8F1E,0x8F1E
00022 ,0x89BF,0x89BF,0x8584,0x8584,0x8277,0x8277,0x809F,0x809F
00023 ,0x8001,0x8001,0x809F,0x809F,0x8277,0x8277,0x8584,0x8584
00024 ,0x89BF,0x89BF,0x8F1E,0x8F1E,0x9593,0x9593,0x9D0F,0x9D0F
00025 ,0xA57E,0xA57E,0xAECD,0xAECD,0xB8E4,0xB8E4,0xC3AA,0xC3AA
00026 ,0xCF05,0xCF05,0xDAD8,0xDAD8,0xE707,0xE707,0xF374,0xF374
00027 };
00028 
00029 #if defined(__ICCARM__)
00030 #pragma data_alignment=4
00031 short write_buff[WRITE_SAMPLE_NUM]@ ".mirrorram";
00032 #pragma data_alignment=4
00033 short read_buff[READ_SAMPLE_NUM]@ ".mirrorram";
00034 #else
00035 short write_buff[WRITE_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00036 short read_buff[READ_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00037 #endif
00038 
00039 void scux_setup(void);
00040 void write_task(void const*);
00041 void file_output_to_usb(void);
00042 
00043 int main(void) {
00044     // set up SRC parameters.
00045     scux_setup();
00046 
00047     printf("Sampling rate conversion Start.\n");
00048     // start accepting transmit/receive requests.
00049     scux.TransStart();
00050 
00051     // create a new thread to write to SCUX.
00052     Thread writeTask(write_task, NULL, osPriorityNormal, 1024 * 4);
00053 
00054     // receive request to the SCUX driver.
00055     scux.read(read_buff, sizeof(read_buff));
00056     printf("Sampling rate conversion End.\n");
00057 
00058     // output binary file to USB port 0.
00059     file_output_to_usb();
00060 }
00061 
00062 void scux_setup(void) {
00063     scux_src_usr_cfg_t src_cfg;
00064 
00065     src_cfg.src_enable           = true;
00066     src_cfg.word_len             = SCUX_DATA_LEN_16;
00067     src_cfg.mode_sync            = true;
00068     src_cfg.input_rate           = SAMPLING_RATE_48000HZ;
00069     src_cfg.output_rate          = SAMPLING_RATE_96000HZ;
00070     src_cfg.select_in_data_ch[0] = SELECT_IN_DATA_CH_0;
00071     src_cfg.select_in_data_ch[1] = SELECT_IN_DATA_CH_1;
00072 
00073     scux.SetSrcCfg(&src_cfg);
00074 }
00075 
00076 void scux_flush_callback(int scux_ch) {
00077     // do nothing
00078 }
00079 
00080 void write_task(void const*) {
00081     memcpy(write_buff, sin_data, sizeof(write_buff));
00082     // send request to the SCUX driver.
00083     scux.write(write_buff, sizeof(write_buff));
00084 
00085     // stop the acceptance of transmit/receive requests.
00086     scux.FlushStop(&scux_flush_callback);
00087 }
00088 
00089 void file_output_to_usb(void) {
00090     FILE * fp = NULL;
00091     int i;
00092 
00093     USBHostMSD msd("usb");
00094 
00095     // try to connect a MSD device
00096     for(i = 0; i < 10; i++) {
00097         if (msd.connect()) {
00098             break;
00099         }
00100         wait(0.5);
00101     }
00102 
00103     if (msd.connected()) {
00104         fp = fopen("/usb/scux_input.dat", "rb");
00105         if (fp == NULL) {
00106             fp = fopen("/usb/scux_input.dat", "wb");
00107             if (fp != NULL) {
00108                 fwrite(write_buff, sizeof(short), WRITE_SAMPLE_NUM, fp);
00109                 fclose(fp);
00110                 printf("Output binary file(Input data) to USB.\n");
00111             } else {
00112                 printf("Failed to output binary file(Input data).\n");
00113             }
00114         } else {
00115             printf("Binary file(Input data) exists.\n");
00116             fclose(fp);
00117         }
00118 
00119         fp = fopen("/usb/scux_output.dat", "rb");
00120         if (fp == NULL) {
00121             fp = fopen("/usb/scux_output.dat", "wb");
00122             if (fp != NULL) {
00123                 fwrite(read_buff, sizeof(short), READ_SAMPLE_NUM, fp);
00124                 fclose(fp);
00125                 printf("Output binary file(Output data) to USB.\n");
00126             } else {
00127                 printf("Failed to output binary file(Output data).\n");
00128             }
00129         } else {
00130             printf("Binary file(Output data) exists.\n");
00131             fclose(fp);
00132         }
00133     } else {
00134         printf("Failed to connect to the USB device.\n");
00135     }
00136 } 

API

Import library

Public Member Functions

R_BSP_Scux ( scux_ch_num_t channel, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor: Initializes and opens the channel designated by the SCUX driver.
virtual ~R_BSP_Scux (void)
Destructor: Closes the channel designated by the SCUX driver and exits.
bool TransStart (void)
Sets up the SCUX HW and starts operation, then starts accepting write/read requests.
bool FlushStop (void(*const callback)(int32_t))
Stops accepting write/read requests, flushes out all data in the SCUX that is requested for transfer, then stops the HW operation.
bool ClearStop (void)
Discards all data in the SCUX that is requested for transfer before stopping the hardware operation and stops accepting write/read requests.
bool SetSrcCfg (const scux_src_usr_cfg_t *const p_src_param)
Sets up SRC parameters.
bool GetWriteStat (uint32_t *const p_write_stat)
Obtains the state information of the write request.
bool GetReadStat (uint32_t *const p_read_stat)
Obtains the state information of the read request.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Write request state transition diagram

/media/uploads/dkato/scux_write_state_transition.png

Read request state transition diagram

/media/uploads/dkato/scux_read_state_transition.png

Committer:
dkato
Date:
Tue May 31 01:45:35 2016 +0000
Revision:
11:fb9eda52224e
Parent:
7:30ebba78fff0
"inline" of the ssif_init function is removed.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 6:aa1fc6a5cc2a 1 /*******************************************************************************
dkato 6:aa1fc6a5cc2a 2 * DISCLAIMER
dkato 6:aa1fc6a5cc2a 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 6:aa1fc6a5cc2a 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 6:aa1fc6a5cc2a 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 6:aa1fc6a5cc2a 6 * all applicable laws, including copyright laws.
dkato 6:aa1fc6a5cc2a 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 6:aa1fc6a5cc2a 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 6:aa1fc6a5cc2a 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 6:aa1fc6a5cc2a 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 6:aa1fc6a5cc2a 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 6:aa1fc6a5cc2a 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 6:aa1fc6a5cc2a 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 6:aa1fc6a5cc2a 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 6:aa1fc6a5cc2a 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 6:aa1fc6a5cc2a 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 6:aa1fc6a5cc2a 17 * and to discontinue the availability of this software. By using this software,
dkato 6:aa1fc6a5cc2a 18 * you agree to the additional terms and conditions found by accessing the
dkato 6:aa1fc6a5cc2a 19 * following link:
dkato 6:aa1fc6a5cc2a 20 * http://www.renesas.com/disclaimer*
dkato 6:aa1fc6a5cc2a 21 * Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
dkato 6:aa1fc6a5cc2a 22 *******************************************************************************/
dkato 6:aa1fc6a5cc2a 23
dkato 6:aa1fc6a5cc2a 24 #include "r_bsp_cmn.h"
dkato 6:aa1fc6a5cc2a 25 #include "R_BSP_Scux.h"
dkato 6:aa1fc6a5cc2a 26 #include "scux_if.h"
dkato 6:aa1fc6a5cc2a 27
dkato 6:aa1fc6a5cc2a 28 #define CH_ERR_NUM (-1) /* Channel error number */
dkato 6:aa1fc6a5cc2a 29 #define INT_LEVEL_MAX (0xF7) /* The maximum value of the interrupt level */
dkato 6:aa1fc6a5cc2a 30 #define REQ_BUFF_NUM_MIN (1) /* The minimum value of the request buffer */
dkato 6:aa1fc6a5cc2a 31 #define REQ_BUFF_NUM_MAX (128) /* The maximum value of the request buffer */
dkato 6:aa1fc6a5cc2a 32 #define INPUT_DIV_INIT_VALUE (1000U) /* The initial value of input divide ratio */
dkato 6:aa1fc6a5cc2a 33 #define OUTPUT_DIV_INIT_VALUE (0U) /* The initial value of output divide ratio */
dkato 6:aa1fc6a5cc2a 34 #define INPUT_WS_INIT_VALUE (1U) /* The initial value of input WS frequency */
dkato 6:aa1fc6a5cc2a 35 #define OUTPUT_WS_INIT_VALUE (96000U) /* The initial value of output WS frequency */
dkato 6:aa1fc6a5cc2a 36 #define FREQ_TIOC3A_INIT_VALUE (1U) /* The initial value of frequency of TIOC3 */
dkato 6:aa1fc6a5cc2a 37 #define FREQ_TIOC4A_INIT_VALUE (1U) /* The initial value of frequency of TIOC4 */
dkato 6:aa1fc6a5cc2a 38 #define WAIT_SAMPLE_INIT_VALUE (0U) /* The initial value of wait time */
dkato 6:aa1fc6a5cc2a 39 #define MIN_RATE_PER_INIT_VALUE (98U) /* The initial value of minimum rate */
dkato 6:aa1fc6a5cc2a 40 #define DIV_RATIO_CLK_AUDIO_22050HZ (1024U) /* Divide ratio when the frequency is 22050Hz */
dkato 6:aa1fc6a5cc2a 41 #define DIV_RATIO_CLK_AUDIO_44100HZ (512U) /* Divide ratio when the frequency is 44100Hz */
dkato 6:aa1fc6a5cc2a 42 #define DIV_RATIO_CLK_AUDIO_88200HZ (256U) /* Divide ratio when the frequency is 88200Hz */
dkato 6:aa1fc6a5cc2a 43 #define DIV_RATIO_CLK_USB_24000HZ (2000U) /* Divide ratio when the frequency is 24000Hz */
dkato 6:aa1fc6a5cc2a 44 #define DIV_RATIO_CLK_USB_32000HZ (1500U) /* Divide ratio when the frequency is 36000Hz */
dkato 6:aa1fc6a5cc2a 45 #define DIV_RATIO_CLK_USB_48000HZ (1000U) /* Divide ratio when the frequency is 48000Hz */
dkato 6:aa1fc6a5cc2a 46 #define DIV_RATIO_CLK_USB_64000HZ (750U) /* Divide ratio when the frequency is 64000Hz */
dkato 6:aa1fc6a5cc2a 47 #define DIV_RATIO_CLK_USB_96000HZ (500U) /* Divide ratio when the frequency is 96000Hz */
dkato 6:aa1fc6a5cc2a 48
dkato 6:aa1fc6a5cc2a 49 static bool set_src_init_cfg(scux_src_cfg_t * const src_cfg);
dkato 6:aa1fc6a5cc2a 50
dkato 6:aa1fc6a5cc2a 51 R_BSP_Scux::R_BSP_Scux(scux_ch_num_t channel, uint8_t int_level, int32_t max_write_num, int32_t max_read_num) {
dkato 6:aa1fc6a5cc2a 52 scux_channel_cfg_t scux_cfg;
dkato 6:aa1fc6a5cc2a 53 int32_t result;
dkato 6:aa1fc6a5cc2a 54 bool init_result;
dkato 6:aa1fc6a5cc2a 55
dkato 6:aa1fc6a5cc2a 56 if (channel >= SCUX_CH_NUM) {
dkato 6:aa1fc6a5cc2a 57 result = EERROR;
dkato 6:aa1fc6a5cc2a 58 } else if (int_level > INT_LEVEL_MAX) {
dkato 6:aa1fc6a5cc2a 59 result = EERROR;
dkato 6:aa1fc6a5cc2a 60 } else if ((max_write_num < REQ_BUFF_NUM_MIN) || (max_write_num > REQ_BUFF_NUM_MAX)) {
dkato 6:aa1fc6a5cc2a 61 result = EERROR;
dkato 6:aa1fc6a5cc2a 62 } else if ((max_read_num < REQ_BUFF_NUM_MIN) || (max_read_num > REQ_BUFF_NUM_MAX)) {
dkato 6:aa1fc6a5cc2a 63 result = EERROR;
dkato 6:aa1fc6a5cc2a 64 } else {
dkato 6:aa1fc6a5cc2a 65 result = R_BSP_CMN_Init();
dkato 6:aa1fc6a5cc2a 66 if (result == ESUCCESS) {
dkato 6:aa1fc6a5cc2a 67 scux_ch = (int32_t)channel;
dkato 6:aa1fc6a5cc2a 68
dkato 6:aa1fc6a5cc2a 69 scux_cfg.enabled = true;
dkato 6:aa1fc6a5cc2a 70 scux_cfg.int_level = int_level;
dkato 6:aa1fc6a5cc2a 71
dkato 6:aa1fc6a5cc2a 72 switch (channel) {
dkato 6:aa1fc6a5cc2a 73 case SCUX_CH_0:
dkato 6:aa1fc6a5cc2a 74 scux_cfg.route = SCUX_ROUTE_SRC0_MEM;
dkato 6:aa1fc6a5cc2a 75 break;
dkato 6:aa1fc6a5cc2a 76 case SCUX_CH_1:
dkato 6:aa1fc6a5cc2a 77 scux_cfg.route = SCUX_ROUTE_SRC1_MEM;
dkato 6:aa1fc6a5cc2a 78 break;
dkato 6:aa1fc6a5cc2a 79 case SCUX_CH_2:
dkato 6:aa1fc6a5cc2a 80 scux_cfg.route = SCUX_ROUTE_SRC2_MEM;
dkato 6:aa1fc6a5cc2a 81 break;
dkato 6:aa1fc6a5cc2a 82 case SCUX_CH_3:
dkato 6:aa1fc6a5cc2a 83 scux_cfg.route = SCUX_ROUTE_SRC3_MEM;
dkato 6:aa1fc6a5cc2a 84 break;
dkato 6:aa1fc6a5cc2a 85 default:
dkato 6:aa1fc6a5cc2a 86 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 87 scux_cfg.route = SCUX_ROUTE_SRC0_MEM;
dkato 6:aa1fc6a5cc2a 88 break;
dkato 6:aa1fc6a5cc2a 89 }
dkato 6:aa1fc6a5cc2a 90
dkato 6:aa1fc6a5cc2a 91 init_result = set_src_init_cfg(&scux_cfg.src_cfg);
dkato 7:30ebba78fff0 92 if (init_result != false) {
dkato 7:30ebba78fff0 93 init_result = init_channel(R_SCUX_MakeCbTbl_mbed(), (int32_t)channel, &scux_cfg, max_write_num, max_read_num);
dkato 7:30ebba78fff0 94 if (init_result == false) {
dkato 6:aa1fc6a5cc2a 95 result = EERROR;
dkato 6:aa1fc6a5cc2a 96 }
dkato 6:aa1fc6a5cc2a 97 } else {
dkato 6:aa1fc6a5cc2a 98 result = EERROR;
dkato 6:aa1fc6a5cc2a 99 }
dkato 6:aa1fc6a5cc2a 100 }
dkato 6:aa1fc6a5cc2a 101 }
dkato 6:aa1fc6a5cc2a 102
dkato 6:aa1fc6a5cc2a 103 if (result != ESUCCESS) {
dkato 6:aa1fc6a5cc2a 104 scux_ch = CH_ERR_NUM;
dkato 6:aa1fc6a5cc2a 105 }
dkato 6:aa1fc6a5cc2a 106 }
dkato 6:aa1fc6a5cc2a 107
dkato 6:aa1fc6a5cc2a 108 R_BSP_Scux::~R_BSP_Scux(void) {
dkato 6:aa1fc6a5cc2a 109 }
dkato 6:aa1fc6a5cc2a 110
dkato 6:aa1fc6a5cc2a 111 bool R_BSP_Scux::TransStart(void) {
dkato 7:30ebba78fff0 112 return ioctl(SCUX_IOCTL_SET_START, NULL);
dkato 6:aa1fc6a5cc2a 113 }
dkato 6:aa1fc6a5cc2a 114
dkato 6:aa1fc6a5cc2a 115 bool R_BSP_Scux::FlushStop(void (* const callback)(int32_t)) {
dkato 7:30ebba78fff0 116 return ioctl(SCUX_IOCTL_SET_FLUSH_STOP, (void *)callback);
dkato 6:aa1fc6a5cc2a 117 }
dkato 6:aa1fc6a5cc2a 118
dkato 6:aa1fc6a5cc2a 119 bool R_BSP_Scux::ClearStop(void) {
dkato 7:30ebba78fff0 120 return ioctl(SCUX_IOCTL_SET_CLEAR_STOP, NULL);
dkato 6:aa1fc6a5cc2a 121 }
dkato 6:aa1fc6a5cc2a 122
dkato 6:aa1fc6a5cc2a 123 bool R_BSP_Scux::SetSrcCfg(const scux_src_usr_cfg_t * const p_src_param) {
dkato 6:aa1fc6a5cc2a 124 scux_src_cfg_t src_cfg;
dkato 6:aa1fc6a5cc2a 125 bool init_result;
dkato 6:aa1fc6a5cc2a 126 bool ret = true;
dkato 6:aa1fc6a5cc2a 127 int32_t i;
dkato 6:aa1fc6a5cc2a 128
dkato 7:30ebba78fff0 129 if (scux_ch == CH_ERR_NUM) {
dkato 6:aa1fc6a5cc2a 130 ret = false;
dkato 6:aa1fc6a5cc2a 131 } else if (p_src_param == NULL) {
dkato 6:aa1fc6a5cc2a 132 ret = false;
dkato 6:aa1fc6a5cc2a 133 } else if ((p_src_param->mode_sync != false) && (p_src_param->src_enable == false)) {
dkato 6:aa1fc6a5cc2a 134 ret = false;
dkato 6:aa1fc6a5cc2a 135 } else {
dkato 6:aa1fc6a5cc2a 136 init_result = set_src_init_cfg(&src_cfg);
dkato 6:aa1fc6a5cc2a 137 if (init_result != true) {
dkato 6:aa1fc6a5cc2a 138 ret = false;
dkato 6:aa1fc6a5cc2a 139 } else {
dkato 6:aa1fc6a5cc2a 140 src_cfg.src_enable = p_src_param->src_enable;
dkato 6:aa1fc6a5cc2a 141 src_cfg.mode_sync = p_src_param->mode_sync;
dkato 6:aa1fc6a5cc2a 142
dkato 6:aa1fc6a5cc2a 143 switch (p_src_param->word_len) {
dkato 6:aa1fc6a5cc2a 144 case SCUX_DATA_LEN_24:
dkato 6:aa1fc6a5cc2a 145 /* fall through */
dkato 6:aa1fc6a5cc2a 146 case SCUX_DATA_LEN_16:
dkato 6:aa1fc6a5cc2a 147 /* fall through */
dkato 6:aa1fc6a5cc2a 148 case SCUX_DATA_LEN_16_TO_24:
dkato 6:aa1fc6a5cc2a 149 src_cfg.word_len = p_src_param->word_len;
dkato 6:aa1fc6a5cc2a 150 break;
dkato 6:aa1fc6a5cc2a 151 default:
dkato 6:aa1fc6a5cc2a 152 ret = false;
dkato 6:aa1fc6a5cc2a 153 break;
dkato 6:aa1fc6a5cc2a 154 }
dkato 6:aa1fc6a5cc2a 155
dkato 6:aa1fc6a5cc2a 156 if (ret == true) {
dkato 6:aa1fc6a5cc2a 157 if (p_src_param->mode_sync != false) {
dkato 6:aa1fc6a5cc2a 158 switch (p_src_param->input_rate) {
dkato 6:aa1fc6a5cc2a 159 case SAMPLING_RATE_8000HZ:
dkato 6:aa1fc6a5cc2a 160 src_cfg.input_rate_sync = SCUX_SYNC_RATE_8;
dkato 6:aa1fc6a5cc2a 161 break;
dkato 6:aa1fc6a5cc2a 162 case SAMPLING_RATE_11025HZ:
dkato 6:aa1fc6a5cc2a 163 src_cfg.input_rate_sync = SCUX_SYNC_RATE_11_025;
dkato 6:aa1fc6a5cc2a 164 break;
dkato 6:aa1fc6a5cc2a 165 case SAMPLING_RATE_12000HZ:
dkato 6:aa1fc6a5cc2a 166 src_cfg.input_rate_sync = SCUX_SYNC_RATE_12;
dkato 6:aa1fc6a5cc2a 167 break;
dkato 6:aa1fc6a5cc2a 168 case SAMPLING_RATE_16000HZ:
dkato 6:aa1fc6a5cc2a 169 src_cfg.input_rate_sync = SCUX_SYNC_RATE_16;
dkato 6:aa1fc6a5cc2a 170 break;
dkato 6:aa1fc6a5cc2a 171 case SAMPLING_RATE_22050HZ:
dkato 6:aa1fc6a5cc2a 172 src_cfg.input_rate_sync = SCUX_SYNC_RATE_22_05;
dkato 6:aa1fc6a5cc2a 173 break;
dkato 6:aa1fc6a5cc2a 174 case SAMPLING_RATE_24000HZ:
dkato 6:aa1fc6a5cc2a 175 src_cfg.input_rate_sync = SCUX_SYNC_RATE_24;
dkato 6:aa1fc6a5cc2a 176 break;
dkato 6:aa1fc6a5cc2a 177 case SAMPLING_RATE_32000HZ:
dkato 6:aa1fc6a5cc2a 178 src_cfg.input_rate_sync = SCUX_SYNC_RATE_32;
dkato 6:aa1fc6a5cc2a 179 break;
dkato 6:aa1fc6a5cc2a 180 case SAMPLING_RATE_44100HZ:
dkato 6:aa1fc6a5cc2a 181 src_cfg.input_rate_sync = SCUX_SYNC_RATE_44_1;
dkato 6:aa1fc6a5cc2a 182 break;
dkato 6:aa1fc6a5cc2a 183 case SAMPLING_RATE_48000HZ:
dkato 6:aa1fc6a5cc2a 184 src_cfg.input_rate_sync = SCUX_SYNC_RATE_48;
dkato 6:aa1fc6a5cc2a 185 break;
dkato 6:aa1fc6a5cc2a 186 case SAMPLING_RATE_64000HZ:
dkato 6:aa1fc6a5cc2a 187 src_cfg.input_rate_sync = SCUX_SYNC_RATE_64;
dkato 6:aa1fc6a5cc2a 188 break;
dkato 6:aa1fc6a5cc2a 189 case SAMPLING_RATE_88200HZ:
dkato 6:aa1fc6a5cc2a 190 src_cfg.input_rate_sync = SCUX_SYNC_RATE_88_2;
dkato 6:aa1fc6a5cc2a 191 break;
dkato 6:aa1fc6a5cc2a 192 case SAMPLING_RATE_96000HZ:
dkato 6:aa1fc6a5cc2a 193 src_cfg.input_rate_sync = SCUX_SYNC_RATE_96;
dkato 6:aa1fc6a5cc2a 194 break;
dkato 6:aa1fc6a5cc2a 195 default:
dkato 6:aa1fc6a5cc2a 196 ret = false;
dkato 6:aa1fc6a5cc2a 197 break;
dkato 6:aa1fc6a5cc2a 198 }
dkato 6:aa1fc6a5cc2a 199 } else {
dkato 6:aa1fc6a5cc2a 200 switch (p_src_param->input_rate) {
dkato 6:aa1fc6a5cc2a 201 case SAMPLING_RATE_22050HZ:
dkato 6:aa1fc6a5cc2a 202 src_cfg.input_clk_async = SCUX_CLK_AUDIO_X1;
dkato 6:aa1fc6a5cc2a 203 src_cfg.input_div_async = DIV_RATIO_CLK_AUDIO_22050HZ;
dkato 6:aa1fc6a5cc2a 204 break;
dkato 6:aa1fc6a5cc2a 205 case SAMPLING_RATE_24000HZ:
dkato 6:aa1fc6a5cc2a 206 src_cfg.input_clk_async = SCUX_CLK_USB_X1;
dkato 6:aa1fc6a5cc2a 207 src_cfg.input_div_async = DIV_RATIO_CLK_USB_24000HZ;
dkato 6:aa1fc6a5cc2a 208 break;
dkato 6:aa1fc6a5cc2a 209 case SAMPLING_RATE_32000HZ:
dkato 6:aa1fc6a5cc2a 210 src_cfg.input_clk_async = SCUX_CLK_USB_X1;
dkato 6:aa1fc6a5cc2a 211 src_cfg.input_div_async = DIV_RATIO_CLK_USB_32000HZ;
dkato 6:aa1fc6a5cc2a 212 break;
dkato 6:aa1fc6a5cc2a 213 case SAMPLING_RATE_44100HZ:
dkato 6:aa1fc6a5cc2a 214 src_cfg.input_clk_async = SCUX_CLK_AUDIO_X1;
dkato 6:aa1fc6a5cc2a 215 src_cfg.input_div_async = DIV_RATIO_CLK_AUDIO_44100HZ;
dkato 6:aa1fc6a5cc2a 216 break;
dkato 6:aa1fc6a5cc2a 217 case SAMPLING_RATE_48000HZ:
dkato 6:aa1fc6a5cc2a 218 src_cfg.input_clk_async = SCUX_CLK_USB_X1;
dkato 6:aa1fc6a5cc2a 219 src_cfg.input_div_async = DIV_RATIO_CLK_USB_48000HZ;
dkato 6:aa1fc6a5cc2a 220 break;
dkato 6:aa1fc6a5cc2a 221 case SAMPLING_RATE_64000HZ:
dkato 6:aa1fc6a5cc2a 222 src_cfg.input_clk_async = SCUX_CLK_USB_X1;
dkato 6:aa1fc6a5cc2a 223 src_cfg.input_div_async = DIV_RATIO_CLK_USB_64000HZ;
dkato 6:aa1fc6a5cc2a 224 break;
dkato 6:aa1fc6a5cc2a 225 case SAMPLING_RATE_88200HZ:
dkato 6:aa1fc6a5cc2a 226 src_cfg.input_clk_async = SCUX_CLK_AUDIO_X1;
dkato 6:aa1fc6a5cc2a 227 src_cfg.input_div_async = DIV_RATIO_CLK_AUDIO_88200HZ;
dkato 6:aa1fc6a5cc2a 228 break;
dkato 6:aa1fc6a5cc2a 229 case SAMPLING_RATE_96000HZ:
dkato 6:aa1fc6a5cc2a 230 src_cfg.input_clk_async = SCUX_CLK_USB_X1;
dkato 6:aa1fc6a5cc2a 231 src_cfg.input_div_async = DIV_RATIO_CLK_USB_96000HZ;
dkato 6:aa1fc6a5cc2a 232 break;
dkato 6:aa1fc6a5cc2a 233 default:
dkato 6:aa1fc6a5cc2a 234 ret = false;
dkato 6:aa1fc6a5cc2a 235 break;
dkato 6:aa1fc6a5cc2a 236 }
dkato 6:aa1fc6a5cc2a 237 }
dkato 6:aa1fc6a5cc2a 238 }
dkato 6:aa1fc6a5cc2a 239
dkato 6:aa1fc6a5cc2a 240 if (ret == true) {
dkato 6:aa1fc6a5cc2a 241 if (p_src_param->mode_sync != false) {
dkato 6:aa1fc6a5cc2a 242 switch (p_src_param->output_rate) {
dkato 6:aa1fc6a5cc2a 243 case SAMPLING_RATE_44100HZ:
dkato 6:aa1fc6a5cc2a 244 src_cfg.output_rate_sync = SCUX_SYNC_RATE_44_1;
dkato 6:aa1fc6a5cc2a 245 break;
dkato 6:aa1fc6a5cc2a 246 case SAMPLING_RATE_48000HZ:
dkato 6:aa1fc6a5cc2a 247 src_cfg.output_rate_sync = SCUX_SYNC_RATE_48;
dkato 6:aa1fc6a5cc2a 248 break;
dkato 6:aa1fc6a5cc2a 249 case SAMPLING_RATE_96000HZ:
dkato 6:aa1fc6a5cc2a 250 src_cfg.output_rate_sync = SCUX_SYNC_RATE_96;
dkato 6:aa1fc6a5cc2a 251 break;
dkato 6:aa1fc6a5cc2a 252 default:
dkato 6:aa1fc6a5cc2a 253 ret = false;
dkato 6:aa1fc6a5cc2a 254 break;
dkato 6:aa1fc6a5cc2a 255 }
dkato 6:aa1fc6a5cc2a 256 } else {
dkato 6:aa1fc6a5cc2a 257 switch (p_src_param->output_rate) {
dkato 6:aa1fc6a5cc2a 258 case SAMPLING_RATE_44100HZ:
dkato 6:aa1fc6a5cc2a 259 src_cfg.output_ws = SAMPLING_RATE_44100HZ;
dkato 6:aa1fc6a5cc2a 260 break;
dkato 6:aa1fc6a5cc2a 261 case SAMPLING_RATE_48000HZ:
dkato 6:aa1fc6a5cc2a 262 src_cfg.output_ws = SAMPLING_RATE_48000HZ;
dkato 6:aa1fc6a5cc2a 263 break;
dkato 6:aa1fc6a5cc2a 264 case SAMPLING_RATE_88200HZ:
dkato 6:aa1fc6a5cc2a 265 src_cfg.output_ws = SAMPLING_RATE_88200HZ;
dkato 6:aa1fc6a5cc2a 266 break;
dkato 6:aa1fc6a5cc2a 267 case SAMPLING_RATE_96000HZ:
dkato 6:aa1fc6a5cc2a 268 src_cfg.output_ws = SAMPLING_RATE_96000HZ;
dkato 6:aa1fc6a5cc2a 269 break;
dkato 6:aa1fc6a5cc2a 270 default:
dkato 6:aa1fc6a5cc2a 271 ret = false;
dkato 6:aa1fc6a5cc2a 272 break;
dkato 6:aa1fc6a5cc2a 273 }
dkato 6:aa1fc6a5cc2a 274 }
dkato 6:aa1fc6a5cc2a 275 }
dkato 6:aa1fc6a5cc2a 276
dkato 6:aa1fc6a5cc2a 277 if (ret == true) {
dkato 6:aa1fc6a5cc2a 278 for (i = 0; i < SCUX_USE_CH_2; i++) {
dkato 6:aa1fc6a5cc2a 279 switch (p_src_param->select_in_data_ch[i]) {
dkato 6:aa1fc6a5cc2a 280 case SELECT_IN_DATA_CH_0:
dkato 6:aa1fc6a5cc2a 281 src_cfg.select_in_data_ch[i] = SCUX_AUDIO_CH_0;
dkato 6:aa1fc6a5cc2a 282 break;
dkato 6:aa1fc6a5cc2a 283 case SELECT_IN_DATA_CH_1:
dkato 6:aa1fc6a5cc2a 284 src_cfg.select_in_data_ch[i] = SCUX_AUDIO_CH_1;
dkato 6:aa1fc6a5cc2a 285 break;
dkato 6:aa1fc6a5cc2a 286 default:
dkato 6:aa1fc6a5cc2a 287 ret = false;
dkato 6:aa1fc6a5cc2a 288 break;
dkato 6:aa1fc6a5cc2a 289 }
dkato 6:aa1fc6a5cc2a 290 }
dkato 6:aa1fc6a5cc2a 291 }
dkato 6:aa1fc6a5cc2a 292
dkato 6:aa1fc6a5cc2a 293 if (ret == true) {
dkato 7:30ebba78fff0 294 ret = ioctl(SCUX_IOCTL_SET_SRC_CFG, (void *)&src_cfg);
dkato 6:aa1fc6a5cc2a 295 }
dkato 6:aa1fc6a5cc2a 296 }
dkato 6:aa1fc6a5cc2a 297 }
dkato 6:aa1fc6a5cc2a 298
dkato 6:aa1fc6a5cc2a 299 return ret;
dkato 6:aa1fc6a5cc2a 300 }
dkato 6:aa1fc6a5cc2a 301
dkato 6:aa1fc6a5cc2a 302 bool R_BSP_Scux::GetWriteStat(uint32_t * const p_write_stat) {
dkato 7:30ebba78fff0 303 return ioctl(SCUX_IOCTL_GET_WRITE_STAT, (void *)p_write_stat);
dkato 6:aa1fc6a5cc2a 304 }
dkato 6:aa1fc6a5cc2a 305
dkato 6:aa1fc6a5cc2a 306 bool R_BSP_Scux::GetReadStat(uint32_t * const p_read_stat) {
dkato 7:30ebba78fff0 307 return ioctl(SCUX_IOCTL_GET_READ_STAT, (void *)p_read_stat);
dkato 6:aa1fc6a5cc2a 308 }
dkato 6:aa1fc6a5cc2a 309
dkato 6:aa1fc6a5cc2a 310 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 311 * Function Name: set_src_init_cfg
dkato 6:aa1fc6a5cc2a 312 * @brief SRC configuration initialization.
dkato 6:aa1fc6a5cc2a 313 *
dkato 6:aa1fc6a5cc2a 314 * Description:<br>
dkato 6:aa1fc6a5cc2a 315 *
dkato 6:aa1fc6a5cc2a 316 * @param[in] src_cfg SRC configuration.
dkato 6:aa1fc6a5cc2a 317 * @retval true Setting success.
dkato 6:aa1fc6a5cc2a 318 * false Setting fails.
dkato 6:aa1fc6a5cc2a 319 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 320 static bool set_src_init_cfg(scux_src_cfg_t * const src_cfg) {
dkato 6:aa1fc6a5cc2a 321 bool ret = true;
dkato 6:aa1fc6a5cc2a 322
dkato 6:aa1fc6a5cc2a 323 if (src_cfg == NULL) {
dkato 6:aa1fc6a5cc2a 324 ret = false;
dkato 6:aa1fc6a5cc2a 325 } else {
dkato 6:aa1fc6a5cc2a 326 src_cfg->src_enable = true;
dkato 6:aa1fc6a5cc2a 327 src_cfg->use_ch = SCUX_USE_CH_2;
dkato 6:aa1fc6a5cc2a 328 src_cfg->word_len = SCUX_DATA_LEN_16;
dkato 6:aa1fc6a5cc2a 329 src_cfg->mode_sync = true;
dkato 6:aa1fc6a5cc2a 330 src_cfg->input_rate_sync = SCUX_SYNC_RATE_48;
dkato 6:aa1fc6a5cc2a 331 src_cfg->input_clk_async = SCUX_CLK_USB_X1;
dkato 6:aa1fc6a5cc2a 332 src_cfg->input_div_async = INPUT_DIV_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 333 src_cfg->output_rate_sync = SCUX_SYNC_RATE_96;
dkato 6:aa1fc6a5cc2a 334 src_cfg->output_clk_async = SCUX_CLK_SSIF0_WS;
dkato 6:aa1fc6a5cc2a 335 src_cfg->output_div_async = OUTPUT_DIV_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 336 src_cfg->input_ws = INPUT_WS_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 337 src_cfg->output_ws = OUTPUT_WS_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 338 src_cfg->freq_tioc3a = FREQ_TIOC3A_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 339 src_cfg->freq_tioc4a = FREQ_TIOC4A_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 340 src_cfg->delay_mode = SCUX_DELAY_NORMAL;
dkato 6:aa1fc6a5cc2a 341 src_cfg->wait_sample = WAIT_SAMPLE_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 342 src_cfg->min_rate_percentage = MIN_RATE_PER_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 343 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_0] = SCUX_AUDIO_CH_0;
dkato 6:aa1fc6a5cc2a 344 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_1] = SCUX_AUDIO_CH_1;
dkato 6:aa1fc6a5cc2a 345 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_2] = SCUX_AUDIO_CH_2;
dkato 6:aa1fc6a5cc2a 346 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_3] = SCUX_AUDIO_CH_3;
dkato 6:aa1fc6a5cc2a 347 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_4] = SCUX_AUDIO_CH_4;
dkato 6:aa1fc6a5cc2a 348 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_5] = SCUX_AUDIO_CH_5;
dkato 6:aa1fc6a5cc2a 349 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_6] = SCUX_AUDIO_CH_6;
dkato 6:aa1fc6a5cc2a 350 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_7] = SCUX_AUDIO_CH_7;
dkato 6:aa1fc6a5cc2a 351 }
dkato 6:aa1fc6a5cc2a 352
dkato 6:aa1fc6a5cc2a 353 return ret;
dkato 6:aa1fc6a5cc2a 354 }