Renesas
Video library for GR-PEACH
Dependents: Trace_Program2 GR-PEACH_Camera_in_barcode GR-PEACH_LCD_sample GR-PEACH_LCD_4_3inch_sample ... more
Video ｌibrary for GR-PEACH.
Hello World!
Import programGR-PEACH_Camera_in
Camera in sample for GR-PEACH. This sample works on GR-LYCHEE besides GR-PEACH.
Last commit 28 Dec 2018 by 
Renesas
API
Import library
Interface
See the Pinout page for more details
Revision 0:853f5b7408a7, committed 2015-06-26
- Comitter:
- dkato
- Date:
- Fri Jun 26 02:17:53 2015 +0000
- Child:
- 1:fe90cfd5fe25
- Commit message:
- first commit
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/DisplayBace.h Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,507 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+ * @file DisplayBase.h
+ * @brief Display driver wrapper class for GR-PEACH
+******************************************************************************/
+
+#ifndef MBED_DISPLAYBASE_H
+#define MBED_DISPLAYBASE_H
+
+#include "pinmap.h"
+
+/*! @class DisplayBase
+ * @brief Display driver wrapper class for GR-PEACH
+ */
+class DisplayBase
+{
+
+public:
+ /*! @enum video_input_channel_t
+ @brief Video input channel select
+ */
+ typedef enum {
+ VIDEO_INPUT_CHANNEL_0 = 0, /*!< Video input channel 0 */
+ VIDEO_INPUT_CHANNEL_1 /*!< Video input channel 1 */
+ } video_input_channel_t;
+
+ /*! @enum graphics_layer_t
+ @brief Graphics layer select
+ */
+ typedef enum {
+ GRAPHICS_LAYER_0 = 0, /*!< Graphics layer 0 */
+ GRAPHICS_LAYER_1, /*!< Graphics layer 1 */
+ GRAPHICS_LAYER_2, /*!< Graphics layer 2 */
+ GRAPHICS_LAYER_3 /*!< Graphics layer 3 */
+ } graphics_layer_t;
+
+ /*! @enum graphics_error_t
+ @brief Error codes
+ */
+ typedef enum {
+ GRAPHICS_OK = 0, /*!< Normal termination */
+ GRAPHICS_VDC5_ERR = -1, /*!< VDC5 driver error */
+ GRAPHICS_FORMA_ERR = -2, /*!< Not support format */
+ GRAPHICS_LAYER_ERR = -3, /*!< Invalid layer ID error */
+ GRAPHICS_CHANNLE_ERR = -4, /*!< Invalid channel error */
+ GRAPHICS_VIDEO_NTSC_SIZE_ERR = -5, /*!< Video write size(vw) error */
+ GRAPHICS_VIDEO_PAL_SIZE_ERR = -6, /*!< Video Write size(vw) error */
+ GRAPHICS_PARAM_RANGE_ERR = -7 /*!< Parameter range error */
+ } graphics_error_t;
+
+ /*! @enum graphics_format_t
+ @brief Graphics layer read format selects
+ */
+ typedef enum {
+ GRAPHICS_FORMAT_YCBCR422 = 0, /*!< YCbCr422 (2byte / px) */
+ GRAPHICS_FORMAT_RGB565, /*!< RGB565 (2byte / px) */
+ GRAPHICS_FORMAT_RGB888, /*!< RGB888 (4byte / px) */
+ GRAPHICS_FORMAT_ARGB8888 /*!< ARGB8888 (4byte / px) */
+ } graphics_format_t;
+
+ /*! @enum video_format_t
+ @brief Video writing format selects
+ */
+ typedef enum {
+ VIDEO_FORMAT_YCBCR422 = 0, /*!< YCbCr422 (2byte / px) */
+ VIDEO_FORMAT_RGB565, /*!< RGB565 (2byte / px) */
+ VIDEO_FORMAT_RGB888 /*!< RGB888 (4byte / px) */
+ } video_format_t;
+
+ /*! @enum wr_rd_swa_t
+ @brief Frame buffer swap setting
+ */
+ typedef enum {
+ WR_RD_WRSWA_NON = 0, /*!< Not swapped: 1-2-3-4-5-6-7-8 */
+ WR_RD_WRSWA_8BIT, /*!< Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */
+ WR_RD_WRSWA_16BIT, /*!< Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */
+ WR_RD_WRSWA_16_8BIT, /*!< Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */
+ WR_RD_WRSWA_32BIT, /*!< Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */
+ WR_RD_WRSWA_32_8BIT, /*!< Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */
+ WR_RD_WRSWA_32_16BIT, /*!< Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */
+ WR_RD_WRSWA_32_16_8BIT, /*!< Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */
+ } wr_rd_swa_t;
+
+ /*! @enum lcd_tcon_pin_t
+ @brief LCD tcon output pin selects
+ */
+ typedef enum {
+ LCD_TCON_PIN_NON = -1, /*!< Not using output */
+ LCD_TCON_PIN_0, /*!< LCD_TCON0 */
+ LCD_TCON_PIN_1, /*!< LCD_TCON1 */
+ LCD_TCON_PIN_2 /*!< LCD_TCON2 */
+ } lcd_tcon_pin_t;
+
+ /*! @enum lcd_outformat_t
+ @brief LCD output format selects
+ */
+ typedef enum {
+ LCD_OUTFORMAT_RGB888 = 0, /*!< RGB888 or LVDS */
+ LCD_OUTFORMAT_RGB666, /*!< RGB666 */
+ LCD_OUTFORMAT_RGB565 /*!< RGB565 */
+ } lcd_outformat_t;
+
+ /*! @enum edge_t
+ @brief Edge of a signal
+ */
+ typedef enum {
+ EDGE_RISING = 0, /*!< Rising edge */
+ EDGE_FALLING = 1 /*!< Falling edge */
+ } edge_t;
+
+ /*! @enum lcd_type_t
+ @brief LCD type
+ */
+ typedef enum {
+ LCD_TYPE_LVDS = 0, /*!< LVDS control */
+ LCD_TYPE_PARALLEL_RGB /*!< RGB parallel signal control */
+ } lcd_type_t;
+
+ /*! @enum sig_pol_t
+ @brief Polarity of a signal
+ */
+ typedef enum {
+ SIG_POL_NOT_INVERTED = 0, /*!< Not inverted */
+ SIG_POL_INVERTED /*!< Inverted */
+ } sig_pol_t;
+
+ /*! @enum int_type_t
+ @brief Interrupt type
+ */
+ typedef enum {
+ INT_TYPE_S0_VI_VSYNC = 0, /*!< Vsync signal input to scaler 0 */
+ INT_TYPE_S0_LO_VSYNC, /*!< Vsync signal output from scaler 0 */
+ INT_TYPE_S0_VSYNCERR, /*!< Missing Vsync signal for scaler 0 */
+ INT_TYPE_VLINE, /*!< Specified line signal for panel output in graphics 3 */
+ INT_TYPE_S0_VFIELD, /*!< Field end signal for recording function in scaler 0 */
+ INT_TYPE_IV1_VBUFERR, /*!< Frame buffer write overflow signal for scaler 0 */
+ INT_TYPE_IV3_VBUFERR, /*!< Frame buffer read underflow signal for graphics 0 */
+ INT_TYPE_IV5_VBUFERR, /*!< Frame buffer read underflow signal for graphics 2 */
+ INT_TYPE_IV6_VBUFERR, /*!< Frame buffer read underflow signal for graphics 3 */
+ INT_TYPE_S0_WLINE, /*!< Write specification line signal input to scaling-down control block in scaler 0 */
+ INT_TYPE_S1_VI_VSYNC, /*!< Vsync signal input to scaler 1 */
+ INT_TYPE_S1_LO_VSYNC, /*!< Vsync signal output from scaler 1 */
+ INT_TYPE_S1_VSYNCERR, /*!< Missing Vsync signal for scaler 1 */
+ INT_TYPE_S1_VFIELD, /*!< Field end signal for recording function in scaler 1 */
+ INT_TYPE_IV2_VBUFERR, /*!< Frame buffer write overflow signal for scaler 1 */
+ INT_TYPE_IV4_VBUFERR, /*!< Frame buffer read underflow signal for graphics 1 */
+ INT_TYPE_S1_WLINE, /*!< Write specification line signal input to scaling-down control block in scaler 1 */
+ INT_TYPE_OIR_VI_VSYNC, /*!< Vsync signal input to output image generator */
+ INT_TYPE_OIR_LO_VSYNC, /*!< Vsync signal output from output image generator */
+ INT_TYPE_OIR_VLINE, /*!< Specified line signal for panel output in output image generator */
+ INT_TYPE_OIR_VFIELD, /*!< Field end signal for recording function in output image generator */
+ INT_TYPE_IV7_VBUFERR, /*!< Frame buffer write overflow signal for output image generator */
+ INT_TYPE_IV8_VBUFERR, /*!< Frame buffer read underflow signal for graphics (OIR) */
+ INT_TYPE_NUM /*!< The number of VDC5 interrupt types */
+ } int_type_t;
+
+ /*! @enum graphics_video_col_sys_t
+ @brief Video color system
+ */
+ typedef enum {
+ COL_SYS_NTSC_358 = 0, /*!< NTSC-3.58 */
+ COL_SYS_NTSC_443 = 1, /*!< NTSC-4.43 */
+ COL_SYS_PAL_443 = 2, /*!< PAL-4.43 */
+ COL_SYS_PAL_M = 3, /*!< PAL-M */
+ COL_SYS_PAL_N = 4, /*!< PAL-N */
+ COL_SYS_SECAM = 5, /*!< SECAM */
+ COL_SYS_NTSC_443_60 = 6, /*!< NTSC-4.43 (60Hz) */
+ COL_SYS_PAL_60 = 7, /*!< PAL-60 */
+ } graphics_video_col_sys_t;
+
+ /*! @enum video_input_sel_t
+ @brief External Input select
+ */
+ typedef enum {
+ INPUT_SEL_VDEC = 0, /*!< Video decoder output signals */
+ INPUT_SEL_EXT = 1 /*!< Signals supplied via the external input pins */
+ } video_input_sel_t;
+
+ /*! @enum video_extin_format_t
+ @brief External input format select
+ */
+ typedef enum {
+ VIDEO_EXTIN_FORMAT_RGB888 = 0, /*!< RGB888 Not support */
+ VIDEO_EXTIN_FORMAT_RGB666, /*!< RGB666 */
+ VIDEO_EXTIN_FORMAT_RGB565, /*!< RGB565 */
+ VIDEO_EXTIN_FORMAT_BT656, /*!< BT6556 */
+ VIDEO_EXTIN_FORMAT_BT601, /*!< BT6501 */
+ VIDEO_EXTIN_FORMAT_YCBCR422, /*!< YCbCr422 */
+ VIDEO_EXTIN_FORMAT_YCBCR444, /*!< YCbCr444 Not support */
+ } video_extin_format_t;
+
+ /*! @enum onoff_t
+ @brief On/off
+ */
+ typedef enum {
+ OFF = 0, /*!< Off */
+ ON = 1 /*!< On */
+ } onoff_t;
+
+ /*! @enum extin_input_line_t
+ @brief Number of lines for BT.656 external input
+ */
+ typedef enum {
+ EXTIN_LINE_525 = 0, /*!< 525 lines */
+ EXTIN_LINE_625 = 1 /*!< 625 lines */
+ } extin_input_line_t;
+
+ /*! @enum extin_h_pos_t
+ @brief Y/Cb/Y/Cr data string start timing
+ */
+ typedef enum {
+ EXTIN_H_POS_CBYCRY = 0, /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */
+ EXTIN_H_POS_YCRYCB, /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */
+ EXTIN_H_POS_CRYCBY, /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */
+ EXTIN_H_POS_YCBYCR, /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */
+ EXTIN_H_POS_NUM
+ } extin_h_pos_t;
+
+ /*! @struct rect_t
+ @brief The relative position within the graphics display area
+ */
+ typedef struct {
+ unsigned short vs; /*!< Vertical start pos */
+ unsigned short vw; /*!< Vertical width (height) */
+ unsigned short hs; /*!< Horizontal start pos */
+ unsigned short hw; /*!< Horizontal width */
+ } rect_t;
+
+ /*! @struct lcd_config_t
+ @brief LCD configuration
+ */
+ typedef struct {
+ lcd_type_t lcd_type; /*!< LVDS or Pararel RGB */
+ double intputClock; /*!< P1 clk [MHz] ex. 66.67f */
+ double outputClock; /*!< LCD clk [MHz] ex. 33.33f */
+
+ lcd_outformat_t lcd_outformat; /*!< Output format select */
+ edge_t lcd_edge; /*!< Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+
+ unsigned short h_toatal_period; /*!< Free-running Hsync period */
+ unsigned short v_toatal_period; /*!< Free-running Vsync period */
+ unsigned short h_disp_widht; /*!< LCD display area size, horizontal width */
+ unsigned short v_disp_widht; /*!< LCD display area size, vertical width */
+ unsigned short h_back_porch; /*!< LCD display horizontal back porch period */
+ unsigned short v_back_porch; /*!< LCD display vertical back porch period */
+
+ lcd_tcon_pin_t h_sync_port; /*!< TCONn or Not use(-1) */
+ sig_pol_t h_sync_port_polarity; /*!< Polarity inversion control of signal */
+ unsigned short h_sync_width; /*!< Hsync width */
+
+ lcd_tcon_pin_t v_sync_port; /*!< TCONn or Not use(-1) */
+ sig_pol_t v_sync_port_polarity; /*!< Polarity inversion control of signal */
+ unsigned short v_sync_width; /*!< Vsync width */
+
+ lcd_tcon_pin_t de_port; /*!< TCONn or Not use(-1) */
+ sig_pol_t de_port_polarity; /*!< Polarity inversion control of signal */
+ } lcd_config_t;
+
+ /*! @struct video_ext_in_config_t
+ @brief Digital Video Input configuration
+ */
+ typedef struct {
+ video_extin_format_t inp_format; /*!< External Input Format Select */
+ edge_t inp_pxd_edge; /*!< Clock Edge Select for Capturing External Input Video Image */
+ edge_t inp_vs_edge; /*!< Clock Edge Select for Capturing External Input Vsync Signal */
+ edge_t inp_hs_edge; /*!< Clock Edge Select for Capturing External Input Hsync Signal */
+ onoff_t inp_endian_on; /*!< External Input B/R Signal Swap On/Off Control */
+ onoff_t inp_swap_on; /*!< External Input Bit Endian Change On/Off Control */
+ sig_pol_t inp_vs_inv; /*!< External Input Vsync Signal DV_VSYNC Inversion Control */
+ sig_pol_t inp_hs_inv; /*!< External Input Hsync Signal DV_HSYNC Inversion Control */
+ extin_input_line_t inp_f525_625; /*!< Number of lines for BT.656 external input */
+ extin_h_pos_t inp_h_pos; /*!< Y/Cb/Y/Cr data string start timing to Hsync reference */
+ unsigned short cap_vs_pos; /*!< Capture start position from Vsync */
+ unsigned short cap_hs_pos; /*!< Capture start position form Hsync */
+ unsigned short cap_width; /*!< Capture width */
+ unsigned short cap_height; /*!< Capture height should be a multiple of 4.*/
+ } video_ext_in_config_t;
+
+ /** Constructor method of display base object
+ */
+ DisplayBase( void );
+
+ /** Graphics initialization processing<br>
+ * If not using display, set NULL in parameter.
+ * @param[in] lcd_config : LCD configuration
+ * @retval Error code
+ */
+ graphics_error_t Graphics_init( lcd_config_t * lcd_config );
+
+ /** Graphics Video initialization processing<br>
+ * If setting INPUT_SEL_VDEC in video_input_sel parameter, set NULL in video_ext_in_config parameter.
+ * @param[in] video_input_sel : Input select
+ * @param[in] video_ext_in_config : Video configuration
+ * @retval error code
+ */
+ graphics_error_t Graphics_Video_init( video_input_sel_t video_input_sel, video_ext_in_config_t * video_ext_in_config );
+
+ /** LCD output port initialization processing
+ * @param[in] pin : Pin assign for LCD output
+ * @param[in] pin_count : Total number of pin assign
+ * @retval Error code
+ */
+ graphics_error_t Graphics_Lcd_Port_Init( PinName *pin, unsigned int pin_count );
+
+ /** LVDS output port initialization processing
+ * @param[in] pin : Pin assign for LVDS output
+ * @param[in] pin_count : Total number of pin assign
+ * @retval Error code
+ */
+ graphics_error_t Graphics_Lvds_Port_Init( PinName *pin, unsigned int pin_count );
+
+ /** Digital video input port initialization processing
+ * @param[in] pin : Pin assign for digital video input port
+ * @param[in] pin_count : Total number of pin assign
+ * @retval Error code
+ */
+ graphics_error_t Graphics_Dvinput_Port_Init( PinName *pin, unsigned int pin_count );
+
+ /** Interrupt callback setup
+ * This function performs the following processing:
+ * - Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.<br>
+ * - Registers the specified interrupt callback function.<br>
+ * - Disables the interrupt when the pointer to the corresponding interrupt callback function is not specified.<br>
+ * @param[in] Graphics_Irq_Handler_Set : VDC5 interrupt type
+ * @param[in] num : Interrupt line number
+ * @param[in] callback : Interrupt callback function pointer
+ * @retval Error code
+ */
+ graphics_error_t Graphics_Irq_Handler_Set( int_type_t Graphics_Irq_Handler_Set, unsigned short num, void (* callback)(int_type_t) );
+
+ /** Start the graphics surface read process
+ * @param[in] layer_id : Graphics layer ID <br />
+ * - GRAPHICS_LAYER_0 : Layer 0
+ * - GRAPHICS_LAYER_1 : Layer 1
+ * - GRAPHICS_LAYER_2 : Layer 2
+ * - GRAPHICS_LAYER_3 : Layer 3
+ * @retval Error code
+ */
+ graphics_error_t Graphics_Start( graphics_layer_t layer_id );
+
+ /** Stop the graphics surface read process
+ * @param[in] layer_id : Graphics layer ID <br />
+ * - GRAPHICS_LAYER_0 : Layer 0
+ * - GRAPHICS_LAYER_1 : Layer 1
+ * - GRAPHICS_LAYER_2 : Layer 2
+ * - GRAPHICS_LAYER_3 : Layer 3
+ * @retval Error code
+ */
+ graphics_error_t Graphics_Stop( graphics_layer_t layer_id );
+
+ /** Start the video surface write process
+ * @param[in] video_input_channel : Video input channel <br />
+ * - VIDEO_INPUT_CHANNEL_0 : Video channel 0
+ * - VIDEO_INPUT_CHANNEL_1 : Video channel 1
+ * @retval Error code
+ */
+ graphics_error_t Video_Start ( video_input_channel_t video_input_channel );
+
+ /** Stop the video surface write process
+ * @param[in] video_input_channel : Video input channel <br />
+ * - VIDEO_INPUT_CHANNEL_0 : Video channel 0
+ * - VIDEO_INPUT_CHANNEL_1 : Video channel 1
+ * @retval Error code
+ */
+ graphics_error_t Video_Stop ( video_input_channel_t video_input_channel );
+
+ /** Graphics surface read process setting
+ * @param[in] layer_id : Graphics layer ID <br />
+ * - GRAPHICS_LAYER_0 : Layer 0
+ * - GRAPHICS_LAYER_1 : Layer 1
+ * - GRAPHICS_LAYER_2 : Layer 2
+ * - GRAPHICS_LAYER_3 : Layer 3
+ * @param[in] framebuff : Base address of the frame buffer(Not set NULL)
+ * @param[in] fb_stride : Line offset address of the frame buffer[byte] <br />
+ * Frame buffer stride should be set to a multiple of 32 or 128
+ * in accordance with the frame buffer burst transfer mode.
+ * @param[in] gr_format : Format of the frame buffer read signal <br />
+ * - VIDEO_FORMAT_YCBCR422 : YCBCR422 (2byte/px)
+ * - VIDEO_FORMAT_RGB565 : RGB565 (2byte/px)
+ * - VIDEO_FORMAT_RGB888 : RGB888 (4byte/px)
+ * - VIDEO_FORMAT_ARGB8888 : ARGB8888 (4byte/px)
+ * @param[in] wr_rd_swa : frame buffer swap setting <br />
+ * - WR_RD_WRSWA_NON : Not swapped: 1-2-3-4-5-6-7-8
+ * - WR_RD_WRSWA_8BIT : Swapped in 8-bit units: 2-1-4-3-6-5-8-7
+ * - WR_RD_WRSWA_16BIT : Swapped in 16-bit units: 3-4-1-2-7-8-5-6
+ * - WR_RD_WRSWA_16_8BIT : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5
+ * - WR_RD_WRSWA_32BIT : Swapped in 32-bit units: 5-6-7-8-1-2-3-4
+ * - WR_RD_WRSWA_32_8BIT : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3
+ * - WR_RD_WRSWA_32_16BIT : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2
+ * - WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1
+ * @param[in] gr_rect : Graphics display area
+ * @retval Error code
+ */
+ graphics_error_t Graphics_Read_Setting (
+ graphics_layer_t layer_id,
+ void * framebuff,
+ unsigned int fb_stride,
+ graphics_format_t gr_format,
+ wr_rd_swa_t wr_rd_swa,
+ rect_t * gr_rect );
+
+ /** Graphics surface read buffer change process
+ * @param[in] layer_id : Graphics layer ID <br />
+ * - GRAPHICS_LAYER_0 : Layer 0
+ * - GRAPHICS_LAYER_1 : Layer 1
+ * - GRAPHICS_LAYER_2 : Layer 2
+ * - GRAPHICS_LAYER_3 : Layer 3
+ * @param[in] framebuff : Base address of the frame buffer(Not set NULL)
+ * @retval Error code
+ */
+ graphics_error_t Graphics_Read_Change (
+ graphics_layer_t layer_id,
+ void * framebuff);
+
+ /** Video surface write process setting
+ * @param[in] video_input_channel : Video input channel <br />
+ * If using digital input, this parameter is not referenced. <br />
+ * - VIDEO_INPUT_CHANNEL_0 : Video channel 0
+ * - VIDEO_INPUT_CHANNEL_1 : Video channel 1
+ * @param[in] col_sys : Analog video signal color system <br />
+ * If using digital input, this parameter is not referenced. <br />
+ * - COL_SYS_NTSC_358 : NTSC-3.58
+ * - COL_SYS_NTSC_443 : NTSC-4.43
+ * - COL_SYS_PAL_443 : PAL-4.43
+ * - COL_SYS_PAL_M : PAL-M
+ * - COL_SYS_PAL_N : PAL-N
+ * - COL_SYS_SECAM : SECAM
+ * - COL_SYS_NTSC_443_60 : NTSC-4.43 (60Hz)
+ * - COL_SYS_PAL_60 : PAL-60
+ * @param[in] framebuff : Base address of the frame buffer(Not set NULL)
+ * @param[in] fb_stride : Line offset address of the frame buffer[byte] <br />
+ * Frame buffer stride should be set to a multiple of 32 or 128
+ * in accordance with the frame buffer burst transfer mode.
+ * @param[in] video_format : Frame buffer video-signal writing format <br />
+ * - VIDEO_FORMAT_YCBCR422 : YCBCR422 (2byte/px)
+ * - VIDEO_FORMAT_RGB565 : RGB565 (2byte/px)
+ * - VIDEO_FORMAT_RGB888 : RGB888 (4byte/px)
+ * @param[in] wr_rd_swa : frame buffer swap setting <br />
+ * - WR_RD_WRSWA_NON : Not swapped: 1-2-3-4-5-6-7-8
+ * - WR_RD_WRSWA_8BIT : Swapped in 8-bit units: 2-1-4-3-6-5-8-7
+ * - WR_RD_WRSWA_16BIT : Swapped in 16-bit units: 3-4-1-2-7-8-5-6
+ * - WR_RD_WRSWA_16_8BIT : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5
+ * - WR_RD_WRSWA_32BIT : Swapped in 32-bit units: 5-6-7-8-1-2-3-4
+ * - WR_RD_WRSWA_32_8BIT : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3
+ * - WR_RD_WRSWA_32_16BIT : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2
+ * - WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1
+ * @param[in] video_write_buff_vw : Output height[px] <br />
+ * - NTSC format : Max height is 480[px]
+ * - PAL format : Max height is 520[px]
+ * @param[in] video_write_buff_hw : Output width[px] <br />
+ * - Max width : 800[px]
+ * @retval Error code
+ */
+ graphics_error_t Video_Write_Setting (
+ video_input_channel_t video_input_channel,
+ graphics_video_col_sys_t col_sys,
+ void * framebuff,
+ unsigned int fb_stride,
+ video_format_t video_format,
+ wr_rd_swa_t wr_rd_swa,
+ unsigned short video_write_buff_vw,
+ unsigned short video_write_buff_hw );
+
+ /** Video surface write buffer change process
+ * @param[in] video_input_channel : Video input channel <br />
+ * - VIDEO_INPUT_CHANNEL_0 : Video channel 0
+ * - VIDEO_INPUT_CHANNEL_1 : Video channel 1
+ * @param[in] framebuff : Base address of the frame buffer(Not set NULL)
+ * @param[in] fb_stride : Line offset address of the frame buffer <br />
+ * Frame buffer stride should be set to a multiple of 32 or 128
+ * in accordance with the frame buffer burst transfer mode.
+ * @retval Error code
+ */
+ graphics_error_t Video_Write_Change (
+ video_input_channel_t video_input_channel,
+ void * framebuff,
+ uint32_t fb_stride );
+
+protected:
+ lcd_config_t _lcd_config;
+ video_input_sel_t _video_input_sel;
+ video_ext_in_config_t _video_ext_in_config;
+};
+
+
+#endif /* MBED_DISPLAYBASE_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/DisplayBase.cpp Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,439 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+#include <string.h>
+#include "DisplayBace.h"
+#include "gr_peach_vdc5.h"
+
+/**************************************************************************//**
+ * @brief Constructor of the DisplayBase class
+ * @param[in] None
+ * @retval None
+******************************************************************************/
+DisplayBase::DisplayBase( void )
+{
+ /* Lcd setting (default) */
+ _lcd_config.lcd_type = LCD_TYPE_PARALLEL_RGB; /* LVDS or Pararel RGB */
+ _lcd_config.intputClock = 66.67f; /* P1 clk [MHz] ex. 66.67 */
+ _lcd_config.outputClock = 40.00f; /* LCD clk [MHz] ex. 33.33 */
+
+ _lcd_config.lcd_outformat = LCD_OUTFORMAT_RGB888; /* Output format select */
+ _lcd_config.lcd_edge = EDGE_FALLING; /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+
+ _lcd_config.h_toatal_period = (800u + 40u + 128u+ 88u); /* Free-running Hsync period */
+ _lcd_config.v_toatal_period = (600u + 1u + 4u + 23u); /* Free-running Vsync period */
+ _lcd_config.h_disp_widht = 800u; /* LCD display area size, horizontal width */
+ _lcd_config.v_disp_widht = 600u; /* LCD display area size, vertical width */
+ _lcd_config.h_back_porch = (128u+ 88u); /* LCD display horizontal back porch period */
+ _lcd_config.v_back_porch = (4u + 23u); /* LCD display vertical back porch period */
+
+ _lcd_config.h_sync_port = LCD_TCON_PIN_0; /* TCONn or Not use(-1) */
+ _lcd_config.h_sync_port_polarity = SIG_POL_NOT_INVERTED; /* Polarity inversion control of signal */
+ _lcd_config.h_sync_width = 128u; /* Hsync width */
+
+ _lcd_config.v_sync_port = LCD_TCON_PIN_1; /* TCONn or Not use(-1) */
+ _lcd_config.v_sync_port_polarity = SIG_POL_NOT_INVERTED; /* Polarity inversion control of signal */
+ _lcd_config.v_sync_width = 4u; /* Vsync width */
+
+ _lcd_config.de_port = LCD_TCON_PIN_NON; /* TCONn or Not use(-1) */
+ _lcd_config.de_port_polarity = SIG_POL_NOT_INVERTED; /* Polarity inversion control of signal */
+
+ /* Digital video input setting (default) */
+ _video_input_sel = INPUT_SEL_VDEC; /* Video decoder output signals */
+ _video_ext_in_config.inp_format = VIDEO_EXTIN_FORMAT_BT601;
+ _video_ext_in_config.inp_pxd_edge = EDGE_RISING; /* Clock edge select for capturing data */
+ _video_ext_in_config.inp_vs_edge = EDGE_RISING; /* Clock edge select for capturing Vsync signals */
+ _video_ext_in_config.inp_hs_edge = EDGE_RISING; /* Clock edge select for capturing Hsync signals */
+ _video_ext_in_config.inp_endian_on = OFF; /* External input bit endian change on/off */
+ _video_ext_in_config.inp_swap_on = OFF; /* External input B/R signal swap on/off */
+ _video_ext_in_config.inp_vs_inv = SIG_POL_NOT_INVERTED; /* External input DV_VSYNC inversion control */
+ _video_ext_in_config.inp_hs_inv = SIG_POL_INVERTED; /* External input DV_HSYNC inversion control */
+ _video_ext_in_config.inp_f525_625 = EXTIN_LINE_525; /* Number of lines for BT.656 external input */
+ _video_ext_in_config.inp_h_pos = EXTIN_H_POS_CRYCBY; /* Y/Cb/Y/Cr data string start timing to Hsync reference */
+ _video_ext_in_config.cap_vs_pos = 6u; /* Capture start position from Vsync */
+ _video_ext_in_config.cap_hs_pos = 302u; /* Capture start position form Hsync */
+ _video_ext_in_config.cap_width = 640u; /* Capture width */
+ _video_ext_in_config.cap_height = 468u; /* Capture height should be a multiple of 4 */
+} /* End of constructor method () */
+
+/**************************************************************************//**
+ * @brief Graphics initialization processing
+ * @param[in] lcd_config : LCD configuration
+ * @retval error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_init( lcd_config_t * lcd_config )
+{
+ if( lcd_config != NULL ) {
+ _lcd_config.lcd_type = lcd_config->lcd_type; /* LVDS or Pararel RGB */
+ _lcd_config.intputClock = lcd_config->intputClock; /* P1 clk [MHz] ex. 66.67 */
+ _lcd_config.outputClock = lcd_config->outputClock; /* LCD clk [MHz] ex. 33.33 */
+
+ _lcd_config.lcd_outformat = lcd_config->lcd_outformat; /* Output format select */
+ _lcd_config.lcd_edge = lcd_config->lcd_edge; /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+
+ _lcd_config.h_toatal_period = lcd_config->h_toatal_period; /* Free-running Hsync period */
+ _lcd_config.v_toatal_period = lcd_config->v_toatal_period; /* Free-running Vsync period */
+ _lcd_config.h_disp_widht = lcd_config->h_disp_widht; /* LCD display area size, horizontal width */
+ _lcd_config.v_disp_widht = lcd_config->v_disp_widht; /* LCD display area size, vertical width */
+ _lcd_config.h_back_porch = lcd_config->h_back_porch; /* LCD display horizontal back porch period */
+ _lcd_config.v_back_porch = lcd_config->v_back_porch; /* LCD display vertical back porch period */
+
+ _lcd_config.h_sync_port = lcd_config->h_sync_port; /* TCONn or Not use(-1) */
+ _lcd_config.h_sync_port_polarity = lcd_config->h_sync_port_polarity;/* Polarity inversion control of signal */
+ _lcd_config.h_sync_width = lcd_config->h_sync_width; /* Hsync width */
+
+ _lcd_config.v_sync_port = lcd_config->v_sync_port; /* TCONn or Not use(-1) */
+ _lcd_config.v_sync_port_polarity = lcd_config->v_sync_port_polarity;/* Polarity inversion control of signal */
+ _lcd_config.v_sync_width = lcd_config->v_sync_width; /* Vsync width */
+
+ _lcd_config.de_port = lcd_config->de_port; /* TCONn or Not use(-1) */
+ _lcd_config.de_port_polarity = lcd_config->de_port_polarity; /* Polarity inversion control of signal */
+ }
+
+ return (graphics_error_t)DRV_Graphics_Init( (drv_lcd_config_t *)&_lcd_config );
+} /* End of method Graphics_init() */
+
+/**************************************************************************//**
+ * @brief Graphics Video initialization processing
+ * @param[in] video_input_sel : Input select
+ * @param[in] video_ext_in_config : Digtal video input configuration
+ * @retval error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Video_init( video_input_sel_t video_input_sel, video_ext_in_config_t * video_ext_in_config )
+{
+ graphics_error_t error = GRAPHICS_OK;
+
+ if( _video_input_sel == INPUT_SEL_VDEC || _video_input_sel == INPUT_SEL_EXT ) {
+ _video_input_sel = video_input_sel;
+ } else {
+ error = GRAPHICS_PARAM_RANGE_ERR;
+ }
+
+ if( error == GRAPHICS_OK ) {
+ if( video_ext_in_config != NULL ) {
+ /* Signals supplied via the external input pins */
+ /* if using Video decoder output signals, not using value. */
+ _video_ext_in_config.inp_format = video_ext_in_config->inp_format;
+ _video_ext_in_config.inp_pxd_edge = video_ext_in_config->inp_pxd_edge;
+ _video_ext_in_config.inp_vs_edge = video_ext_in_config->inp_vs_edge;
+ _video_ext_in_config.inp_hs_edge = video_ext_in_config->inp_hs_edge;
+ _video_ext_in_config.inp_endian_on = video_ext_in_config->inp_endian_on;
+ _video_ext_in_config.inp_swap_on = video_ext_in_config->inp_swap_on;
+ _video_ext_in_config.inp_vs_inv = video_ext_in_config->inp_vs_inv;
+ _video_ext_in_config.inp_hs_inv = video_ext_in_config->inp_hs_inv;
+ _video_ext_in_config.inp_f525_625 = video_ext_in_config->inp_f525_625;
+ _video_ext_in_config.inp_h_pos = video_ext_in_config->inp_h_pos;
+ _video_ext_in_config.cap_vs_pos = video_ext_in_config->cap_vs_pos;
+ _video_ext_in_config.cap_hs_pos = video_ext_in_config->cap_hs_pos;
+ _video_ext_in_config.cap_width = video_ext_in_config->cap_width;
+ _video_ext_in_config.cap_height = video_ext_in_config->cap_height;
+ }
+ }
+ return (graphics_error_t)DRV_Graphics_Video_init( (drv_video_input_sel_t)video_input_sel,
+ (drv_video_ext_in_config_t *)&_video_ext_in_config );
+} /* End of method Graphics_Video_init() */
+
+/**************************************************************************//**
+ * @brief LCD I/O initialization processing
+ * @param[in] pin : Pointer of the pin assignment
+ * @param[in] pin_count : Total number of the pin assignment
+ * @retval error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Lcd_Port_Init( PinName *pin, unsigned int pin_count )
+{
+ return (graphics_error_t)DRV_Graphics_Lcd_Port_Init( pin, pin_count );
+} /* End of method Graphics_Lcd_Port_Init() */
+
+/**************************************************************************//**
+ * @brief LVDS I/O port initialization processing
+ * @param[in] pin : Pointer of the pin assignment
+ * @param[in] pin_count : Total number of the pin assignment
+ * @retval error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Lvds_Port_Init( PinName *pin, unsigned int pin_count )
+{
+ return (graphics_error_t)DRV_Graphics_Lvds_Port_Init( pin, pin_count );
+} /* End of method Graphics_Lvds_Port_Init() */
+
+/**************************************************************************//**
+ * @brief Digital video input I/O port initialization processing
+ * @param[in] pin : Pointer of the pin assignment
+ * @param[in] pin_count : Total number of the pin assignment
+ * @retval error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Dvinput_Port_Init( PinName *pin, unsigned int pin_count )
+{
+ return (graphics_error_t)DRV_Graphics_Dvinput_Port_Init( pin, pin_count );
+} /* End of method Graphics_Dvinput_Port_Init() */
+
+/**************************************************************************//**
+ * @brief IRQ interrupt handler setting
+ * @param[in] irq : VDC5 interrupt type
+ * @param[in] num : Interrupt line number
+ * @param[in] * callback : Interrupt callback function pointer
+ * @retval error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Irq_Handler_Set( int_type_t irq, unsigned short num, void (* callback)(int_type_t) )
+{
+ return (graphics_error_t)DRV_Graphics_Irq_Handler_Set( (vdc5_int_type_t)irq, num, (void (*)(vdc5_int_type_t))callback );
+} /* End of method Graphics_Irq_Handler_Set() */
+
+/**************************************************************************//**
+ * @brief Graphics surface read start processing
+ * @param[in] layer_id : Graphics layer ID
+ * @retval error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Start( graphics_layer_t layer_id )
+{
+ return (graphics_error_t)DRV_Graphics_Start( (drv_graphics_layer_t)layer_id );
+} /* End of method Graphics_Start() */
+
+/**************************************************************************//**
+ * @brief Graphics surface read stop processing
+ * @param[in] layer_id : Graphics layer ID
+ * @retval error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Stop( graphics_layer_t layer_id )
+{
+ return (graphics_error_t)DRV_Graphics_Stop( (drv_graphics_layer_t)layer_id );
+} /* End of method Graphics_Stop() */
+
+/**************************************************************************//**
+ * @brief Video surface write start processing
+ * @param[in] video_input_channel : Video input channel
+ * @retval error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Video_Start( video_input_channel_t video_input_channel )
+{
+ graphics_error_t error = GRAPHICS_OK;
+
+ /* Digital video inputs : supporting video_input_channel 0 only. */
+ if( _video_input_sel == INPUT_SEL_EXT && video_input_channel == VIDEO_INPUT_CHANNEL_1 ) {
+ error = GRAPHICS_PARAM_RANGE_ERR;
+ }
+
+ if( error == GRAPHICS_OK ) {
+ error = (graphics_error_t)DRV_Video_Start( (drv_video_input_channel_t)video_input_channel );
+ }
+ return error;
+} /* End of method Video_Start() */
+
+/**************************************************************************//**
+ * @brief Video surface write stop processing
+ * @param[in] video_input_channel : Video input channel
+ * @retval error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Video_Stop( video_input_channel_t video_input_channel )
+{
+ graphics_error_t error = GRAPHICS_OK;
+
+ /* Digital video inputs : supporting video_input_channel 0 only. */
+ if( _video_input_sel == INPUT_SEL_EXT && video_input_channel == VIDEO_INPUT_CHANNEL_1 ) {
+ error = GRAPHICS_PARAM_RANGE_ERR;
+ }
+
+ if( error == GRAPHICS_OK ) {
+ error = (graphics_error_t)DRV_Video_Stop(
+ (drv_video_input_channel_t)video_input_channel );
+ }
+ return error;
+} /* End of method Video_Stop() */
+
+/**************************************************************************//**
+ * @brief Graphics surface read process setting
+ *
+ * Description:<br>
+ * This function supports the following 4 image format.
+ * YCbCr422, RGB565, RGB888, ARGB8888
+ * @param[in] layer_id : Graphics layer ID
+ * @param[in] framebuff : Base address of the frame buffer
+ * @param[in] fb_stride : Line offset address of the frame buffer
+ * @param[in] gr_format : Format of the frame buffer read signal
+ * @param[in] wr_rd_swa : frame buffer swap setting
+ * - WR_RD_WRSWA_NON : Not swapped: 1-2-3-4-5-6-7-8
+ * - WR_RD_WRSWA_8BIT : Swapped in 8-bit units: 2-1-4-3-6-5-8-7
+ * - WR_RD_WRSWA_16BIT : Swapped in 16-bit units: 3-4-1-2-7-8-5-6
+ * - WR_RD_WRSWA_16_8BIT : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5
+ * - WR_RD_WRSWA_32BIT : Swapped in 32-bit units: 5-6-7-8-1-2-3-4
+ * - WR_RD_WRSWA_32_8BIT : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3
+ * - WR_RD_WRSWA_32_16BIT : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2
+ * - WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1
+ * @param[in] gr_rect : Graphics display area
+ * @retval Error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Read_Setting(
+ graphics_layer_t layer_id,
+ void * framebuff,
+ unsigned int fb_stride,
+ graphics_format_t gr_format,
+ wr_rd_swa_t wr_rd_swa,
+ rect_t * gr_rect )
+{
+ rect_t rect;
+
+ rect.hs = gr_rect->hs + _lcd_config.h_back_porch;
+ rect.vs = gr_rect->vs + _lcd_config.v_back_porch;
+ rect.hw = gr_rect->hw;
+ rect.vw = gr_rect->vw;
+
+ return (graphics_error_t)DRV_Graphics_Read_Setting(
+ (drv_graphics_layer_t)layer_id,
+ framebuff,
+ fb_stride,
+ (drv_graphics_format_t)gr_format,
+ (drv_wr_rd_swa_t)wr_rd_swa,
+ (drv_rect_t *)&rect );
+} /* End of method Graphics_Read_Setting() */
+
+/**************************************************************************//**
+ * @brief Graphics surface read process changing
+ *
+ * Description:<br>
+ * This function is used to swap buffers.
+ *
+ * @param[in] layer_id : Graphics layer ID
+ * @param[in] framebuff : Base address of the frame buffer
+ * @retval Error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Read_Change ( graphics_layer_t layer_id, void * framebuff)
+{
+ return (graphics_error_t)DRV_Graphics_Read_Change(
+ (drv_graphics_layer_t)layer_id, framebuff );
+} /* End of method Graphics_Read_Change() */
+
+/**************************************************************************//**
+ * @brief Video surface write process setting
+ * This function set the video write process. Input form is weave
+ * (progressive) mode fixed.
+ * This function supports the following 3 image format.
+ * YCbCr422, RGB565, RGB888
+ * @param[in] video_input_ch : Video input channel
+ * @param[in] col_sys : Analog video signal color system
+ * @param[in] adc_vinsel : Video input pin
+ * @param[in] framebuff : Base address of the frame buffer
+ * @param[in] fb_stride [byte] : Line offset address of the frame buffer
+ * @param[in] video_format : Frame buffer video-signal writing format
+ * - VIDEO_FORMAT_YCBCR422 : YCBCR422 (2byte/px)
+ * - VIDEO_FORMAT_RGB565 : RGB565 (2byte/px)
+ * - VIDEO_FORMAT_RGB888 : RGB888 (4byte/px)
+ * @param[in] wr_rd_swa : frame buffer swap setting
+ * - WR_RD_WRSWA_NON : Not swapped: 1-2-3-4-5-6-7-8
+ * - WR_RD_WRSWA_8BIT : Swapped in 8-bit units: 2-1-4-3-6-5-8-7
+ * - WR_RD_WRSWA_16BIT : Swapped in 16-bit units: 3-4-1-2-7-8-5-6
+ * - WR_RD_WRSWA_16_8BIT : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5
+ * - WR_RD_WRSWA_32BIT : Swapped in 32-bit units: 5-6-7-8-1-2-3-4
+ * - WR_RD_WRSWA_32_8BIT : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3
+ * - WR_RD_WRSWA_32_16BIT : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2
+ * - WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1
+ * @param[in] video_write_size_vw [px]: output v width
+ * @param[in] video_write_size_hw [px]: output h width
+ * @retval Error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Video_Write_Setting(
+ video_input_channel_t video_input_channel,
+ graphics_video_col_sys_t col_sys,
+ void * framebuff,
+ unsigned int fb_stride,
+ video_format_t video_format,
+ wr_rd_swa_t wr_rd_swa,
+ unsigned short write_buff_vw,
+ unsigned short write_buff_hw )
+{
+ graphics_error_t error = GRAPHICS_OK;
+
+ if( _video_input_sel == INPUT_SEL_VDEC ) {
+ if( col_sys == COL_SYS_NTSC_358 || col_sys == COL_SYS_NTSC_443 || col_sys == COL_SYS_NTSC_443_60 ) {
+ if( (write_buff_vw / 2u) > 240u ) {
+ error = GRAPHICS_VIDEO_NTSC_SIZE_ERR;
+ }
+ } else {
+ if( (write_buff_vw / 2u) > 280u ) {
+ error = GRAPHICS_VIDEO_PAL_SIZE_ERR;
+ }
+ }
+
+ if( write_buff_hw > 800u ) {
+ error = GRAPHICS_PARAM_RANGE_ERR;
+ }
+ if( error == GRAPHICS_OK ) {
+ error = (graphics_error_t)DRV_Video_Write_Setting(
+ (drv_video_input_channel_t)video_input_channel,
+ (drv_graphics_video_col_sys_t)col_sys,
+ framebuff,
+ fb_stride,
+ (drv_video_format_t)video_format,
+ (drv_wr_rd_swa_t)wr_rd_swa,
+ write_buff_vw,
+ write_buff_hw);
+ }
+ } else if( _video_input_sel == INPUT_SEL_EXT ) {
+ rect_t cap_area;
+
+ cap_area.hs = _video_ext_in_config.cap_hs_pos * 2;
+ cap_area.hw = _video_ext_in_config.cap_width * 2;
+ cap_area.vs = _video_ext_in_config.cap_vs_pos;
+ cap_area.vw = _video_ext_in_config.cap_height;
+
+ error = (graphics_error_t) DRV_Video_Write_Setting_Digital(
+ framebuff,
+ fb_stride,
+ (drv_video_format_t)video_format,
+ (drv_wr_rd_swa_t)wr_rd_swa,
+ write_buff_vw,
+ write_buff_hw,
+ (drv_rect_t *)&cap_area );
+ } else {
+ error = GRAPHICS_PARAM_RANGE_ERR;
+ }
+ return error;
+} /* End of method Video_Write_Setting() */
+
+/**************************************************************************//**
+ * @brief Graphics surface write process changing
+ * This function is used to swap buffers of the weave write processing.
+ * @param[in] video_input_ch : Video input channle
+ * @param[in] framebuff : Base address of the frame buffer
+ * @param[in] fb_stride : Line offset address of the frame buffer
+ * @retval Error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Video_Write_Change (
+ video_input_channel_t video_input_channel, void * framebuff, uint32_t fb_stride )
+{
+ return (graphics_error_t)DRV_Video_Write_Change(
+ (drv_video_input_channel_t)video_input_channel, framebuff, fb_stride );
+} /* End of method Video_Write_Change() */
+
+/* End of file */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/common/lcd_panel/lcd_analog_rgb_ch0.c Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,172 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file lcd_analog_rgb_ch0.c
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief LCD panel for vdc5 channel 0 function
+******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include <string.h>
+
+#include "r_typedefs.h"
+
+#include "r_vdc5.h"
+
+#include "iodefine.h"
+#include "lcd_panel.h"
+
+#if (LCD_VDC5_CH0_PANEL==1)
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* Port 11 */
+#define LCD_PORT11_5TH (0xE0FFu)
+/* Port 10 */
+#define LCD_PORT10_5TH (0xFFFFu)
+
+#define FH_1_2_CYCLE (2u)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+ * @brief LCD panel I/O port setup (VDC5 channel 0)
+ * @param[in] void
+ * @retval None
+******************************************************************************/
+void GRAPHICS_SetLcdPanel_Ch0 (void)
+{
+ volatile uint32_t dummy_read;
+ uint32_t reg_data;
+
+ /* Analog RGB D-sub15 (RGB888)
+ : LCD0_CLK ... P11_15, 5th alternative function
+ HSYNC : LCD0_TCON0 ... P11_14, 5th alternative function
+ VSYNC : LCD0_TCON1 ... P11_13, 5th alternative function
+ LCD0_DATA
+ R[7:0] : LCD0_DATA[23:16] ... P10_0 ~ P10_7, 5th alternative function
+ G[7:0] : LCD0_DATA[15:8] ... P10_8 ~ P10_15, 5th alternative function
+ B[7:0] : LCD0_DATA[7:0] ... P11_0 ~ P11_7, 5th alternative function
+ */
+ /* Port 11 */
+ reg_data = (uint32_t)GPIO.PMC11 & (uint32_t)~LCD_PORT11_5TH;
+ GPIO.PMC11 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PMC11;
+ dummy_read = reg_data;
+ /* PFCAE11, PFCE11, PFC11 ... 5th alternative function
+ PIPC11, PMC11
+ b15:b13 : P11_15 ~ P11_13
+ b7:b0 : P11_7 ~ P11_0 */
+ reg_data = (uint32_t)GPIO.PFCAE11 | (uint32_t)LCD_PORT11_5TH;
+ GPIO.PFCAE11 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PFCE11 & (uint32_t)~LCD_PORT11_5TH;
+ GPIO.PFCE11 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PFC11 & (uint32_t)~LCD_PORT11_5TH;
+ GPIO.PFC11 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PIPC11 | (uint32_t)LCD_PORT11_5TH;
+ GPIO.PIPC11 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PMC11 | (uint32_t)LCD_PORT11_5TH;
+ GPIO.PMC11 = (uint16_t)reg_data;
+
+ /* Port 10 */
+ reg_data = (uint32_t)GPIO.PMC10 & (uint32_t)~LCD_PORT10_5TH;
+ GPIO.PMC10 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PMC10;
+ dummy_read = reg_data;
+ /* PFCAE10, PFCE10, PFC10 ... 5th alternative function
+ PIPC10, PMC10
+ b15:b0 : P10_15 ~ P10_0 */
+ reg_data = (uint32_t)GPIO.PFCAE10 | (uint32_t)LCD_PORT10_5TH;
+ GPIO.PFCAE10 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PFCE10 & (uint32_t)~LCD_PORT10_5TH;
+ GPIO.PFCE10 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PFC10 & (uint32_t)~LCD_PORT10_5TH;
+ GPIO.PFC10 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PIPC10 | (uint32_t)LCD_PORT10_5TH;
+ GPIO.PIPC10 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PMC10 | (uint32_t)LCD_PORT10_5TH;
+ GPIO.PMC10 = (uint16_t)reg_data;
+} /* End of function GRAPHICS_SetLcdPanel_Ch0() */
+
+/**************************************************************************//**
+ * @brief LCD TCON setup parameter acquisition processing (VDC5 channel 0)
+ * @param[out] outctrl : Address of the area for storing the LCD TCON timing setup data table
+ * @retval None
+******************************************************************************/
+void GRAPHICS_SetLcdTconSettings_Ch0 (const vdc5_lcd_tcon_timing_t * * const outctrl)
+{
+ /* Analog RGB D-sub15 (RGB888), SVGA signal 800x600 */
+ /* TCON timing setting, VS */
+ static const vdc5_lcd_tcon_timing_t lcd_tcon_timing_VS = {
+ (uint16_t)(LCD_CH0_S_VSYNC * FH_1_2_CYCLE), /* Signal pulse start position */
+ (uint16_t)(LCD_CH0_W_VSYNC * FH_1_2_CYCLE), /* Pulse width */
+ VDC5_LCD_TCON_POLMD_NORMAL,
+ VDC5_LCD_TCON_REFSEL_HSYNC,
+ LCD_CH0_POL_VSYNC, /* Polarity inversion control of signal */
+ VDC5_LCD_TCON_PIN_1, /* Output pin for LCD driving signal */
+ LCD_CH0_OUT_EDGE /* Output phase control of signal */
+ };
+ /* TCON timing setting, HS */
+ static const vdc5_lcd_tcon_timing_t lcd_tcon_timing_HS = {
+ (uint16_t)LCD_CH0_S_HSYNC, /* Signal pulse start position */
+ (uint16_t)LCD_CH0_W_HSYNC, /* Pulse width */
+ VDC5_LCD_TCON_POLMD_NORMAL,
+ VDC5_LCD_TCON_REFSEL_HSYNC, /* Signal operating reference select */
+ LCD_CH0_POL_HSYNC, /* Polarity inversion control of signal */
+ VDC5_LCD_TCON_PIN_0, /* Output pin for LCD driving signal */
+ LCD_CH0_OUT_EDGE /* Output phase control of signal */
+ };
+
+ if (outctrl != NULL) {
+ outctrl[VDC5_LCD_TCONSIG_STVA_VS] = &lcd_tcon_timing_VS; /* STVA/VS: Vsync */
+ outctrl[VDC5_LCD_TCONSIG_STVB_VE] = NULL; /* STVB/VE: Not used */
+ outctrl[VDC5_LCD_TCONSIG_STH_SP_HS] = &lcd_tcon_timing_HS; /* STH/SP/HS: Hsync */
+ outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = NULL; /* STB/LP/HE: Not used */
+ outctrl[VDC5_LCD_TCONSIG_CPV_GCK] = NULL; /* CPV/GCK: Not used */
+ outctrl[VDC5_LCD_TCONSIG_POLA] = NULL; /* POLA: Not used */
+ outctrl[VDC5_LCD_TCONSIG_POLB] = NULL; /* POLB: Not used */
+ outctrl[VDC5_LCD_TCONSIG_DE] = NULL; /* DE: Not used */
+ }
+} /* End of function GRAPHICS_SetLcdTconSettings_Ch0() */
+
+#endif /* LCD_VDC5_CH0_PANEL==LCD_CH0_PANEL_ANALOG_RGB */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/common/lcd_panel/lcd_analog_rgb_ch1.c Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,238 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file lcd_analog_rgb_ch1.c
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief LCD panel for vdc5 channel 1 function
+******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include <string.h>
+
+#include "r_typedefs.h"
+
+#include "r_vdc5.h"
+
+#include "iodefine.h"
+#include "lcd_panel.h"
+
+#if (LCD_VDC5_CH1_PANEL==1)
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* Port 4 */
+#define LCD_PORT4_2ND (0x5400u)
+/* Port 9 */
+#define LCD_PORT9_1ST (0x00FCu)
+/* Port 5 */
+#define LCD_PORT5_7TH (0x0600u)
+#define LCD_PORT5_2ND (0x00FFu)
+/* Port 2 */
+#define LCD_PORT2_7TH (0xF000u)
+#define LCD_PORT2_6TH (0x0F00u)
+
+#define FH_1_2_CYCLE (2u)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+ * @brief LCD panel I/O port setup (VDC5 channel 1)
+ * @param[in] void
+ * @retval None
+******************************************************************************/
+void GRAPHICS_SetLcdPanel_Ch1 (void)
+{
+ volatile uint32_t dummy_read;
+ uint32_t reg_data;
+
+ /* Analog RGB D-sub15 (RGB888)
+ VSYNC : LCD1_TCON1 ... P4_14, 2nd alternative function
+ : LCD1_CLK ... P4_12, 2nd alternative function
+ HSYNC : LCD1_TCON5 ... P4_10, 2nd alternative function
+ LCD1_DATA
+ R[7:0] : LCD1_DATA[23:18] ... P9_7 ~ P9_2, 1st alternative function
+ : [17:16] ... P5_10 ~ P5_9, 7th alternative function
+ G[7:0] : LCD1_DATA[15:12] ... P2_15 ~ P2_12, 7th alternative function
+ : [11:8] ... P2_11 ~ P2_8, 6th alternative function
+ B[7:0] : LCD1_DATA[7:0] ... P5_7 ~ P5_0, 2nd alternative function
+ */
+ /* Port 4 */
+ reg_data = (uint32_t)GPIO.PMC4 & (uint32_t)~LCD_PORT4_2ND;
+ GPIO.PMC4 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PMC4;
+ dummy_read = reg_data;
+ /* PFCAE4, PFCE4, PFC4 ... 2nd alternative function
+ PIPC4, PMC4
+ b14 : P4_14
+ b12 : P4_12
+ b10 : P4_10 */
+ reg_data = (uint32_t)GPIO.PFCAE4 & (uint32_t)~LCD_PORT4_2ND;
+ GPIO.PFCAE4 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PFCE4 & (uint32_t)~LCD_PORT4_2ND;
+ GPIO.PFCE4 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PFC4 | (uint32_t)LCD_PORT4_2ND;
+ GPIO.PFC4 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PIPC4 | (uint32_t)LCD_PORT4_2ND;
+ GPIO.PIPC4 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PMC4 | (uint32_t)LCD_PORT4_2ND;
+ GPIO.PMC4 = (uint16_t)reg_data;
+
+ /* Port 9 */
+ reg_data = (uint32_t)GPIO.PMC9 & (uint32_t)~LCD_PORT9_1ST;
+ GPIO.PMC9 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PMC9;
+ dummy_read = reg_data;
+ /* PFCAE9, PFCE9, PFC9 ... 1st alternative function
+ PIPC9, PMC9
+ b7:b2 : P9_7 ~ P9_2 */
+ reg_data = (uint32_t)GPIO.PFCAE9 & (uint32_t)~LCD_PORT9_1ST;
+ GPIO.PFCAE9 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PFCE9 & (uint32_t)~LCD_PORT9_1ST;
+ GPIO.PFCE9 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PFC9 & (uint32_t)~LCD_PORT9_1ST;
+ GPIO.PFC9 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PIPC9 | (uint32_t)LCD_PORT9_1ST;
+ GPIO.PIPC9 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PMC9 | (uint32_t)LCD_PORT9_1ST;
+ GPIO.PMC9 = (uint16_t)reg_data;
+
+ /* Port 5 */
+ reg_data = (uint32_t)GPIO.PMC5 & (uint32_t)~(LCD_PORT5_7TH|LCD_PORT5_2ND);
+ GPIO.PMC5 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PMC5;
+ dummy_read = reg_data;
+ /* PFCAE5, PFCE5, PFC5 ... 7th alternative function
+ b10:b9 : P5_10 ~ P5_9 */
+ reg_data = (uint32_t)GPIO.PFCAE5 | (uint32_t)LCD_PORT5_7TH;
+ GPIO.PFCAE5 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PFCE5 | (uint32_t)LCD_PORT5_7TH;
+ GPIO.PFCE5 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PFC5 & (uint32_t)~LCD_PORT5_7TH;
+ GPIO.PFC5 = (uint16_t)reg_data;
+ /* PFCAE5, PFCE5, PFC5 ... 2nd alternative function
+ b7:b0 : P5_7 ~ P5_0 */
+ reg_data = (uint32_t)GPIO.PFCAE5 & (uint32_t)~LCD_PORT5_2ND;
+ GPIO.PFCAE5 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PFCE5 & (uint32_t)~LCD_PORT5_2ND;
+ GPIO.PFCE5 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PFC5 | (uint32_t)LCD_PORT5_2ND;
+ GPIO.PFC5 = (uint16_t)reg_data;
+ /* PIPC5, PMC5
+ b10:b9 : P5_10 ~ P5_9
+ b7:b0 : P5_7 ~ P5_0 */
+ reg_data = (uint32_t)GPIO.PIPC5 | (uint32_t)(LCD_PORT5_7TH|LCD_PORT5_2ND);
+ GPIO.PIPC5 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PMC5 | (uint32_t)(LCD_PORT5_7TH|LCD_PORT5_2ND);
+ GPIO.PMC5 = (uint16_t)reg_data;
+
+ /* Port 2 */
+ reg_data = (uint32_t)GPIO.PMC2 & (uint32_t)~(LCD_PORT2_7TH|LCD_PORT2_6TH);
+ GPIO.PMC2 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PMC2;
+ dummy_read = reg_data;
+ /* PFCAE2, PFCE2, PFC2 ... 7th alternative function
+ b15:b12 : P2_15 ~ P2_12 */
+ reg_data = (uint32_t)GPIO.PFCAE2 | (uint32_t)LCD_PORT2_7TH;
+ GPIO.PFCAE2 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PFCE2 | (uint32_t)LCD_PORT2_7TH;
+ GPIO.PFCE2 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PFC2 & (uint32_t)~LCD_PORT2_7TH;
+ GPIO.PFC2 = (uint16_t)reg_data;
+ /* PFCAE2, PFCE2, PFC2 ... 6th alternative function
+ b11:b8 : P2_11 ~ P2_8 */
+ reg_data = (uint32_t)GPIO.PFCAE2 | (uint32_t)LCD_PORT2_6TH;
+ GPIO.PFCAE2 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PFCE2 & (uint32_t)~LCD_PORT2_6TH;
+ GPIO.PFCE2 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PFC2 | (uint32_t)LCD_PORT2_6TH;
+ GPIO.PFC2 = (uint16_t)reg_data;
+ /* PIPC2, PMC2
+ b15:b8 : P2_15 ~ P2_8 */
+ reg_data = (uint32_t)GPIO.PIPC2 | (uint32_t)(LCD_PORT2_7TH|LCD_PORT2_6TH);
+ GPIO.PIPC2 = (uint16_t)reg_data;
+ reg_data = (uint32_t)GPIO.PMC2 | (uint32_t)(LCD_PORT2_7TH|LCD_PORT2_6TH);
+ GPIO.PMC2 = (uint16_t)reg_data;
+} /* End of function GRAPHICS_SetLcdPanel_Ch1() */
+
+/**************************************************************************//**
+ * @brief LCD TCON setup parameter acquisition processing (VDC5 channel 1)
+ * @param[out] outctrl : Address of the area for storing the LCD TCON timing setup data table
+ * @retval None
+******************************************************************************/
+void GRAPHICS_SetLcdTconSettings_Ch1 (const vdc5_lcd_tcon_timing_t * * const outctrl)
+{
+ /* Analog RGB D-sub15 (RGB888), SVGA signal 800x600 */
+ /* TCON timing setting, VS */
+ static const vdc5_lcd_tcon_timing_t lcd_tcon_timing_VS = {
+ (uint16_t)(LCD_CH1_S_VSYNC * FH_1_2_CYCLE), /* Signal pulse start position */
+ (uint16_t)(LCD_CH1_W_VSYNC * FH_1_2_CYCLE), /* Pulse width */
+ VDC5_LCD_TCON_POLMD_NORMAL,
+ VDC5_LCD_TCON_REFSEL_HSYNC,
+ LCD_CH1_POL_VSYNC, /* Polarity inversion control of signal */
+ VDC5_LCD_TCON_PIN_1, /* Output pin for LCD driving signal */
+ LCD_CH1_OUT_EDGE /* Output phase control of signal */
+ };
+ /* TCON timing setting, HS */
+ static const vdc5_lcd_tcon_timing_t lcd_tcon_timing_HS = {
+ (uint16_t)LCD_CH1_S_HSYNC, /* Signal pulse start position */
+ (uint16_t)LCD_CH1_W_HSYNC, /* Pulse width */
+ VDC5_LCD_TCON_POLMD_NORMAL,
+ VDC5_LCD_TCON_REFSEL_HSYNC, /* Signal operating reference select */
+ LCD_CH1_POL_HSYNC, /* Polarity inversion control of signal */
+ VDC5_LCD_TCON_PIN_5, /* Output pin for LCD driving signal */
+ LCD_CH1_OUT_EDGE /* Output phase control of signal */
+ };
+
+ if (outctrl != NULL) {
+ outctrl[VDC5_LCD_TCONSIG_STVA_VS] = &lcd_tcon_timing_VS; /* STVA/VS: Vsync */
+ outctrl[VDC5_LCD_TCONSIG_STVB_VE] = NULL; /* STVB/VE: Not used */
+ outctrl[VDC5_LCD_TCONSIG_STH_SP_HS] = &lcd_tcon_timing_HS; /* STH/SP/HS: Hsync */
+ outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = NULL; /* STB/LP/HE: Not used */
+ outctrl[VDC5_LCD_TCONSIG_CPV_GCK] = NULL; /* CPV/GCK: Not used */
+ outctrl[VDC5_LCD_TCONSIG_POLA] = NULL; /* POLA: Not used */
+ outctrl[VDC5_LCD_TCONSIG_POLB] = NULL; /* POLB: Not used */
+ outctrl[VDC5_LCD_TCONSIG_DE] = NULL; /* DE: Not used */
+ }
+} /* End of function GRAPHICS_SetLcdTconSettings_Ch1() */
+
+#endif /* LCD_VDC5_CH1_PANEL==LCD_CH1_PANEL_ANALOG_RGB */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/common/lcd_panel/lcd_gr_peach_ch0.c Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,99 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file lcd_gr_peach_ch0.c
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief LCD panel for vdc5 channel 0 function
+******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include <string.h>
+
+#include "r_typedefs.h"
+
+#include "r_vdc5.h"
+
+#include "iodefine.h"
+#include "lcd_panel.h"
+
+#if (LCD_VDC5_CH0_PANEL==2)
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+ * @brief LCD panel I/O port setup (VDC5 channel 0)
+ * @param[in] void
+ * @retval None
+******************************************************************************/
+void GRAPHICS_SetLcdPanel_Ch0 (void)
+{
+
+ /* Not Support */
+
+} /* End of function GRAPHICS_SetLcdPanel_Ch0() */
+
+/**************************************************************************//**
+ * @brief LCD TCON setup parameter acquisition processing (VDC5 channel 0)
+ * @param[out] outctrl : Address of the area for storing the LCD TCON timing setup data table
+ * @retval None
+******************************************************************************/
+void GRAPHICS_SetLcdTconSettings_Ch0 (const vdc5_lcd_tcon_timing_t * * const outctrl)
+{
+ /* Not Support */
+
+ if (outctrl != NULL) {
+ outctrl[VDC5_LCD_TCONSIG_STVA_VS] = NULL; /* STVA/VS: Not used */
+ outctrl[VDC5_LCD_TCONSIG_STVB_VE] = NULL; /* STVB/VE: Not used */
+ outctrl[VDC5_LCD_TCONSIG_STH_SP_HS] = NULL; /* STH/SP/HS: Not used */
+ outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = NULL; /* STB/LP/HE: Not used */
+ outctrl[VDC5_LCD_TCONSIG_CPV_GCK] = NULL; /* CPV/GCK: Not used */
+ outctrl[VDC5_LCD_TCONSIG_POLA] = NULL; /* POLA: Not used */
+ outctrl[VDC5_LCD_TCONSIG_POLB] = NULL; /* POLB: Not used */
+ outctrl[VDC5_LCD_TCONSIG_DE] = NULL; /* DE: Not used */
+ }
+} /* End of function GRAPHICS_SetLcdTconSettings_Ch0() */
+
+#endif /* LCD_VDC5_CH0_PANEL==LCD_CH0_PANEL_GR_PEACH */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/common/lcd_settings.c Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,114 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file lcd_settings.c
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief VDC5 driver LCD panel settings sample
+******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include <string.h>
+
+#include "r_typedefs.h"
+
+#include "r_vdc5.h"
+
+#include "iodefine.h"
+#include "lcd_panel.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define LVDSPLL_TST (16u) /* LVDSPLL_TST (LVDS PLL internal parameters) */
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+ * @brief LCD panel I/O port setup
+ * @param[in] channel
+ * @retval None
+******************************************************************************/
+void GRAPHICS_SetLcdPanel (const vdc5_channel_t channel)
+{
+ if (channel == VDC5_CHANNEL_0) {
+ GRAPHICS_SetLcdPanel_Ch0();
+ } else {
+ GRAPHICS_SetLcdPanel_Ch1();
+ }
+} /* End of function GRAPHICS_SetLcdPanel() */
+
+/**************************************************************************//**
+ * @brief LCD TCON setup parameter acquisition processing
+ * @param[in] channel
+ * @param[out] outctrl : Address of the area for storing the LCD TCON timing setup data table
+ * @retval None
+******************************************************************************/
+void GRAPHICS_SetLcdTconSettings (const vdc5_channel_t channel, const vdc5_lcd_tcon_timing_t * * const outctrl)
+{
+ /* LCD TCON timing setting */
+ if (channel == VDC5_CHANNEL_0) {
+ GRAPHICS_SetLcdTconSettings_Ch0(outctrl);
+ } else {
+ GRAPHICS_SetLcdTconSettings_Ch1(outctrl);
+ }
+} /* End of function GRAPHICS_SetLcdTconSettings() */
+
+/**************************************************************************//**
+ * @brief LVDS-related parameter acquisition processing
+ * @param[in] channel
+ * @retval Address of the area containing the LVDS-related parameters
+******************************************************************************/
+vdc5_lvds_t * GRAPHICS_GetLvdsParam (const vdc5_channel_t channel)
+{
+ static vdc5_lvds_t lvds_param;
+ vdc5_lvds_t * p_lvds;
+
+ p_lvds = (vdc5_lvds_t *)&lvds_param;
+
+ if (channel == VDC5_CHANNEL_0) {
+ p_lvds = NULL;
+ } else {
+ p_lvds = NULL;
+ }
+ return p_lvds;
+} /* End of function GRAPHICS_GetLvdsParam() */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/vdc5/include/r_vdc5.h Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,957 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file r_vdc5.h
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief VDC5 driver API definitions
+******************************************************************************/
+
+#ifndef R_VDC5_H
+#define R_VDC5_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_vdc5_user.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define VDC5_GAM_GAIN_ADJ_NUM (32u) /*!< The number of the gamma correction gain coefficient */
+#define VDC5_GAM_START_TH_NUM (31u) /*!< The number of the gamma correction start threshold */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! Error codes of the VDC5 driver */
+typedef enum {
+ VDC5_OK = 0, /*!< Normal termination */
+ VDC5_ERR_PARAM_CHANNEL, /*!< Invalid channel error (parameter error): An illegal channel is specified. */
+ VDC5_ERR_PARAM_LAYER_ID, /*!< Invalid layer ID error (parameter error): An illegal layer ID is specified. */
+ VDC5_ERR_PARAM_NULL, /*!< NULL specification error (parameter error):
+ NULL is specified for a required parameter. */
+ VDC5_ERR_PARAM_BIT_WIDTH, /*!< Bit width error (parameter error):
+ A value exceeding the possible bit width is specified. */
+ VDC5_ERR_PARAM_UNDEFINED, /*!< Undefined parameter error (parameter error):
+ A value that is not defined in the specification is specified. */
+ VDC5_ERR_PARAM_EXCEED_RANGE,/*!< Out-of-value-range error (parameter error):
+ The specified parameter value is beyond the value range defined
+ in the specification. */
+ VDC5_ERR_PARAM_CONDITION, /*!< Unauthorized condition error (parameter error):
+ A parameter is specified under conditions that are not authorized
+ by the specification. */
+ VDC5_ERR_IF_CONDITION, /*!< Interface condition error (interface error):
+ An API function is called under unauthorized conditions. */
+ VDC5_ERR_RESOURCE_CLK, /*!< Clock resource error (resource error): No panel clock is set up. */
+ VDC5_ERR_RESOURCE_VSYNC, /*!< Vsync signal resource error (resource error): No Vsync signal is set up. */
+ VDC5_ERR_RESOURCE_INPUT, /*!< Input signal resource error (resource error): No video image input is set up. */
+ VDC5_ERR_RESOURCE_OUTPUT, /*!< Output resource error (resource error): No display output is set up. */
+ VDC5_ERR_RESOURCE_LVDS_CLK, /*!< LVDS clock resource error (resource error):
+ An attempt is made to use the LVDS clock without setting it up,
+ or the LVDS clock is specified when it is already set up. */
+ VDC5_ERR_RESOURCE_LAYER, /*!< Layer resource error (resource error):
+ The specified layer is under unavailable conditions. */
+ VDC5_ERR_NUM /*!< The number of error codes */
+} vdc5_error_t;
+
+/*! VDC5 channels */
+typedef enum {
+ VDC5_CHANNEL_0 = 0, /*!< Channel 0 */
+ VDC5_CHANNEL_1, /*!< Channel 1 */
+ VDC5_CHANNEL_NUM /*!< The number of channels */
+} vdc5_channel_t;
+
+/*! On/off */
+typedef enum {
+ VDC5_OFF = 0, /*!< Off */
+ VDC5_ON = 1 /*!< On */
+} vdc5_onoff_t;
+/*! Edge of a signal */
+typedef enum {
+ VDC5_EDGE_RISING = 0, /*!< Rising edge */
+ VDC5_EDGE_FALLING = 1 /*!< Falling edge */
+} vdc5_edge_t;
+/*! Polarity of a signal */
+typedef enum {
+ VDC5_SIG_POL_NOT_INVERTED = 0, /*!< Not inverted */
+ VDC5_SIG_POL_INVERTED = 1 /*!< Inverted */
+} vdc5_sig_pol_t;
+
+/*! Scaling type ID */
+typedef enum {
+ VDC5_SC_TYPE_SC0 = 0, /*!< Scaler 0 */
+ VDC5_SC_TYPE_SC1, /*!< Scaler 1 */
+ VDC5_SC_TYPE_OIR, /*!< Output image generator (OIR) */
+ VDC5_SC_TYPE_NUM /*!< The number of scaler types */
+} vdc5_scaling_type_t;
+/*! Graphics type ID */
+typedef enum {
+ VDC5_GR_TYPE_GR0 = 0, /*!< Graphics 0 */
+ VDC5_GR_TYPE_GR1, /*!< Graphics 1 */
+ VDC5_GR_TYPE_GR2, /*!< Graphics 2 */
+ VDC5_GR_TYPE_GR3, /*!< Graphics 3 */
+ VDC5_GR_TYPE_VIN, /*!< VIN synthesizer */
+ VDC5_GR_TYPE_OIR, /*!< Output image generator (OIR) */
+ VDC5_GR_TYPE_NUM /*!< The number of graphics types */
+} vdc5_graphics_type_t;
+/*! Layer ID */
+typedef enum {
+ VDC5_LAYER_ID_ALL = -1, /*!< All layers */
+ VDC5_LAYER_ID_0_WR = (VDC5_SC_TYPE_SC0 + 0), /*!< Write process for layer 0 */
+ VDC5_LAYER_ID_1_WR = (VDC5_SC_TYPE_SC1 + 0), /*!< Write process for layer 1 */
+ VDC5_LAYER_ID_OIR_WR = (VDC5_SC_TYPE_OIR + 0), /*!< Write process for layer OIR */
+ VDC5_LAYER_ID_0_RD = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_GR0), /*!< Read process for layer 0 */
+ VDC5_LAYER_ID_1_RD = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_GR1), /*!< Read process for layer 1 */
+ VDC5_LAYER_ID_2_RD = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_GR2), /*!< Read process for layer 2 */
+ VDC5_LAYER_ID_3_RD = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_GR3), /*!< Read process for layer 3 */
+ VDC5_LAYER_ID_VIN_RD = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_VIN), /*!< VIN synthesizer */
+ VDC5_LAYER_ID_OIR_RD = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_OIR), /*!< Read process for layer OIR */
+ VDC5_LAYER_ID_NUM = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_NUM) /*!< The number of layer IDs */
+} vdc5_layer_id_t;
+/*! The horizontal/vertical timing of the VDC5 signals */
+typedef struct {
+ uint16_t vs; /*!< Vertical signal start position from the reference signal */
+ uint16_t vw; /*!< Vertical signal width (height) */
+ uint16_t hs; /*!< Horizontal signal start position from the reference signal */
+ uint16_t hw; /*!< Horizontal signal width */
+} vdc5_period_rect_t;
+/*! The relative position within the graphics display area */
+typedef struct {
+ uint16_t vs_rel; /*!< Vertical start position */
+ uint16_t vw_rel; /*!< Vertical width (height) */
+ uint16_t hs_rel; /*!< Horizontal start position */
+ uint16_t hw_rel; /*!< Horizontal width */
+} vdc5_pd_disp_rect_t;
+
+/*********************** For R_VDC5_Initialize ***********************/
+/*! Panel clock select */
+typedef enum {
+ VDC5_PANEL_ICKSEL_IMG = 0, /*!< Divided video image clock (VIDEO_X1) */
+ VDC5_PANEL_ICKSEL_IMG_DV, /*!< Divided video image clock (DV_CLK) */
+ VDC5_PANEL_ICKSEL_EXT_0, /*!< Divided external clock (LCD0_EXTCLK) */
+ VDC5_PANEL_ICKSEL_EXT_1, /*!< Divided external clock (LCD1_EXTCLK) */
+ VDC5_PANEL_ICKSEL_PERI, /*!< Divided peripheral clock 1 */
+ VDC5_PANEL_ICKSEL_LVDS, /*!< LVDS PLL clock */
+ VDC5_PANEL_ICKSEL_LVDS_DIV7, /*!< LVDS PLL clock divided by 7 */
+ VDC5_PANEL_ICKSEL_NUM /*!< The number of panel clock select settings */
+} vdc5_panel_clksel_t;
+/*! Clock frequency division ratio */
+typedef enum {
+ VDC5_PANEL_CLKDIV_1_1 = 0, /*!< Division Ratio 1/1 */
+ VDC5_PANEL_CLKDIV_1_2, /*!< Division Ratio 1/2 */
+ VDC5_PANEL_CLKDIV_1_3, /*!< Division Ratio 1/3 */
+ VDC5_PANEL_CLKDIV_1_4, /*!< Division Ratio 1/4 */
+ VDC5_PANEL_CLKDIV_1_5, /*!< Division Ratio 1/5 */
+ VDC5_PANEL_CLKDIV_1_6, /*!< Division Ratio 1/6 */
+ VDC5_PANEL_CLKDIV_1_7, /*!< Division Ratio 1/7 */
+ VDC5_PANEL_CLKDIV_1_8, /*!< Division Ratio 1/8 */
+ VDC5_PANEL_CLKDIV_1_9, /*!< Division Ratio 1/9 */
+ VDC5_PANEL_CLKDIV_1_12, /*!< Division Ratio 1/12 */
+ VDC5_PANEL_CLKDIV_1_16, /*!< Division Ratio 1/16 */
+ VDC5_PANEL_CLKDIV_1_24, /*!< Division Ratio 1/24 */
+ VDC5_PANEL_CLKDIV_1_32, /*!< Division Ratio 1/32 */
+ VDC5_PANEL_CLKDIV_NUM /*!< The number of division ratio settings */
+} vdc5_panel_clk_dcdr_t;
+/*! The clock input to frequency divider 1 */
+typedef enum {
+ VDC5_LVDS_INCLK_SEL_IMG = 0, /*!< Video image clock (VIDEO_X1) */
+ VDC5_LVDS_INCLK_SEL_DV_0, /*!< Video image clock (DV0_CLK) */
+ VDC5_LVDS_INCLK_SEL_DV_1, /*!< Video image clock (DV1_CLK) */
+ VDC5_LVDS_INCLK_SEL_EXT_0, /*!< External clock (LCD0_EXTCLK) */
+ VDC5_LVDS_INCLK_SEL_EXT_1, /*!< External clock (LCD1_EXTCLK) */
+ VDC5_LVDS_INCLK_SEL_PERI, /*!< Peripheral clock 1 */
+ VDC5_LVDS_INCLK_SEL_NUM
+} vdc5_lvds_in_clk_sel_t;
+/*! The frequency dividing value (NIDIV or NODIV) */
+typedef enum {
+ VDC5_LVDS_NDIV_1 = 0, /*!< Div 1 */
+ VDC5_LVDS_NDIV_2, /*!< Div 2 */
+ VDC5_LVDS_NDIV_4, /*!< Div 4 */
+ VDC5_LVDS_NDIV_NUM
+} vdc5_lvds_ndiv_t;
+/*! The frequency dividing value (NOD) for the output frequency */
+typedef enum {
+ VDC5_LVDS_PLL_NOD_1 = 0, /*!< Div 1 */
+ VDC5_LVDS_PLL_NOD_2, /*!< Div 2 */
+ VDC5_LVDS_PLL_NOD_4, /*!< Div 4 */
+ VDC5_LVDS_PLL_NOD_8, /*!< Div 8 */
+ VDC5_LVDS_PLL_NOD_NUM
+} vdc5_lvds_pll_nod_t;
+/*! LVDS parameter */
+typedef struct {
+ vdc5_lvds_in_clk_sel_t lvds_in_clk_sel;/*!< The clock input to frequency divider 1 */
+ vdc5_lvds_ndiv_t lvds_idiv_set; /*!< The frequency dividing value (NIDIV) for frequency divider 1 */
+ uint16_t lvdspll_tst; /*!< Internal parameter setting for LVDS PLL */
+ vdc5_lvds_ndiv_t lvds_odiv_set; /*!< The frequency dividing value (NODIV) for frequency divider 2 */
+ vdc5_channel_t lvds_vdc_sel; /*!< A channel in VDC5 whose data is to be output through the LVDS */
+ uint16_t lvdspll_fd; /*!< The frequency dividing value (NFD) for the feedback frequency */
+ uint16_t lvdspll_rd; /*!< The frequency dividing value (NRD) for the input frequency */
+ vdc5_lvds_pll_nod_t lvdspll_od; /*!< The frequency dividing value (NOD) for the output frequency */
+} vdc5_lvds_t;
+/*! Initialization parameter */
+typedef struct {
+ vdc5_panel_clksel_t panel_icksel; /*!< Panel clock select */
+ vdc5_panel_clk_dcdr_t panel_dcdr; /*!< Clock frequency division ratio */
+ const vdc5_lvds_t * lvds; /*!< LVDS-related parameter */
+} vdc5_init_t;
+
+/*********************** For R_VDC5_VideoInput ***********************/
+/*! Input select */
+typedef enum {
+ VDC5_INPUT_SEL_VDEC = 0, /*!< Video decoder output signals */
+ VDC5_INPUT_SEL_EXT = 1 /*!< Signals supplied via the external input pins */
+} vdc5_input_sel_t;
+/*! Sync signal delay adjustment parameter */
+typedef struct {
+ uint16_t inp_vs_dly_l; /*!< Number of lines for delaying Vsync signal and field differentiation signal */
+ uint16_t inp_fld_dly; /*!< Field differentiation signal delay amount */
+ uint16_t inp_vs_dly; /*!< Vsync signal delay amount */
+ uint16_t inp_hs_dly; /*!< Hsync signal delay amount */
+} vdc5_sync_delay_t;
+/*! External input format select */
+typedef enum {
+ VDC5_EXTIN_FORMAT_RGB888 = 0, /*!< RGB888 */
+ VDC5_EXTIN_FORMAT_RGB666, /*!< RGB666 */
+ VDC5_EXTIN_FORMAT_RGB565, /*!< RGB565 */
+ VDC5_EXTIN_FORMAT_BT656, /*!< BT6556 */
+ VDC5_EXTIN_FORMAT_BT601, /*!< BT6501 */
+ VDC5_EXTIN_FORMAT_YCBCR422, /*!< YCbCr422 */
+ VDC5_EXTIN_FORMAT_YCBCR444, /*!< YCbCr444 */
+ VDC5_EXTIN_FORMAT_NUM
+} vdc5_extin_format_t;
+/*! Reference select for external input BT.656 Hsync signal */
+typedef enum {
+ VDC5_EXTIN_REF_H_EAV = 0, /*!< EAV */
+ VDC5_EXTIN_REF_H_SAV = 1 /*!< SAV */
+} vdc5_extin_ref_hsync_t;
+/*! Number of lines for BT.656 external input */
+typedef enum {
+ VDC5_EXTIN_LINE_525 = 0, /*!< 525 lines */
+ VDC5_EXTIN_LINE_625 = 1 /*!< 625 lines */
+} vdc5_extin_input_line_t;
+/*! Y/Cb/Y/Cr data string start timing */
+typedef enum {
+ VDC5_EXTIN_H_POS_CBYCRY = 0, /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */
+ VDC5_EXTIN_H_POS_YCRYCB, /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */
+ VDC5_EXTIN_H_POS_CRYCBY, /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */
+ VDC5_EXTIN_H_POS_YCBYCR, /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */
+ VDC5_EXTIN_H_POS_NUM
+} vdc5_extin_h_pos_t;
+/*! External input signal parameter */
+typedef struct {
+ vdc5_extin_format_t inp_format; /*!< External input format select */
+ vdc5_edge_t inp_pxd_edge; /*!< Clock edge select for capturing external input video image signals */
+ vdc5_edge_t inp_vs_edge; /*!< Clock edge select for capturing external input Vsync signals */
+ vdc5_edge_t inp_hs_edge; /*!< Clock edge select for capturing external input Hsync signals */
+ vdc5_onoff_t inp_endian_on; /*!< External input bit endian change on/off control */
+ vdc5_onoff_t inp_swap_on; /*!< External input B/R signal swap on/off control */
+ vdc5_sig_pol_t inp_vs_inv; /*!< External input Vsync signal DV_VSYNC inversion control */
+ vdc5_sig_pol_t inp_hs_inv; /*!< External input Hsync signal DV_HSYNC inversion control */
+ vdc5_extin_ref_hsync_t inp_h_edge_sel; /*!< Reference select for external input BT.656 Hsync signal */
+ vdc5_extin_input_line_t inp_f525_625; /*!< Number of lines for BT.656 external input */
+ vdc5_extin_h_pos_t inp_h_pos; /*!< Y/Cb/Y/Cr data string start timing to Hsync reference */
+} vdc5_ext_in_sig_t;
+/*! Video input setup parameter */
+typedef struct {
+ vdc5_input_sel_t inp_sel; /*!< Input select */
+ uint16_t inp_fh50; /*!< Vsync signal 1/2fH phase timing */
+ uint16_t inp_fh25; /*!< Vsync signal 1/4fH phase timing */
+ const vdc5_sync_delay_t * dly; /*!< Sync signal delay adjustment parameter */
+ const vdc5_ext_in_sig_t * ext_sig; /*!< External input signal parameter */
+} vdc5_input_t;
+
+/*********************** For R_VDC5_SyncControl ***********************/
+/*! Horizontal/vertical sync signal output and full-screen enable signal select */
+typedef enum {
+ VDC5_RES_VS_IN_SEL_SC0 = 0, /*!< Sync signal output and full-screen enable signal from scaler 0 */
+ VDC5_RES_VS_IN_SEL_SC1 = 1 /*!< Sync signal output and full-screen enable signal from scaler 1 */
+} vdc5_res_vs_in_sel_t;
+/*! Vsync signal compensation parameter */
+typedef struct {
+ uint16_t res_vmask; /*!< Repeated Vsync signal masking period */
+ uint16_t res_vlack; /*!< Missing-Sync compensating pulse output wait time */
+} vdc5_vsync_cpmpe_t;
+/*! Sync signal control parameter */
+typedef struct {
+ vdc5_onoff_t res_vs_sel; /*!< Vsync signal output select (free-running Vsync on/off control) */
+ vdc5_res_vs_in_sel_t res_vs_in_sel; /*!< Horizontal/vertical sync signal output
+ and full-screen enable signal select */
+ uint16_t res_fv; /*!< Free-running Vsync period setting */
+ uint16_t res_fh; /*!< Hsync period setting */
+ uint16_t res_vsdly; /*!< Vsync signal delay control */
+ vdc5_period_rect_t res_f; /*!< Full-screen enable signal */
+ const vdc5_vsync_cpmpe_t * vsync_cpmpe; /*!< Vsync signal compensation parameter */
+} vdc5_sync_ctrl_t;
+
+/*********************** For R_VDC5_DisplayOutput ***********************/
+/*! POLA/POLB signal generation mode select */
+typedef enum {
+ VDC5_LCD_TCON_POLMD_NORMAL = 0, /*!< Normal mode */
+ VDC5_LCD_TCON_POLMD_1X1REV, /*!< 1x1 reverse mode */
+ VDC5_LCD_TCON_POLMD_1X2REV, /*!< 1x2 reverse mode */
+ VDC5_LCD_TCON_POLMD_2X2REV, /*!< 2x2 reverse mode */
+ VDC5_LCD_TCON_POLMD_NUM
+} vdc5_lcd_tcon_polmode_t;
+/*! Signal operating reference select */
+typedef enum {
+ VDC5_LCD_TCON_REFSEL_HSYNC = 0, /*!< Hsync signal reference */
+ VDC5_LCD_TCON_REFSEL_OFFSET_H = 1 /*!< Offset Hsync signal reference */
+} vdc5_lcd_tcon_refsel_t;
+/*! LCD TCON output pin select */
+typedef enum {
+ VDC5_LCD_TCON_PIN_NON = -1, /*!< Nothing output */
+ VDC5_LCD_TCON_PIN_0, /*!< LCD_TCON0 */
+ VDC5_LCD_TCON_PIN_1, /*!< LCD_TCON1 */
+ VDC5_LCD_TCON_PIN_2, /*!< LCD_TCON2 */
+ VDC5_LCD_TCON_PIN_3, /*!< LCD_TCON3 */
+ VDC5_LCD_TCON_PIN_4, /*!< LCD_TCON4 */
+ VDC5_LCD_TCON_PIN_5, /*!< LCD_TCON5 */
+ VDC5_LCD_TCON_PIN_6, /*!< LCD_TCON6 */
+ VDC5_LCD_TCON_PIN_NUM
+} vdc5_lcd_tcon_pin_t;
+/*! LCD TCON timing signal parameter */
+typedef struct {
+ uint16_t tcon_hsvs; /*!< Signal pulse start position */
+ uint16_t tcon_hwvw; /*!< Pulse width */
+ vdc5_lcd_tcon_polmode_t tcon_md; /*!< POLA/POLB signal generation mode select */
+ vdc5_lcd_tcon_refsel_t tcon_hs_sel; /*!< Signal operating reference select */
+ vdc5_sig_pol_t tcon_inv; /*!< Polarity inversion control of signal */
+ vdc5_lcd_tcon_pin_t tcon_pin; /*!< LCD TCON output pin select */
+ vdc5_edge_t outcnt_edge; /*!< Output phase control of signal */
+} vdc5_lcd_tcon_timing_t;
+/*! Timing signals for driving the LCD panel */
+typedef enum {
+ VDC5_LCD_TCONSIG_STVA_VS = 0, /*!< STVA/VS */
+ VDC5_LCD_TCONSIG_STVB_VE, /*!< STVB/VE */
+ VDC5_LCD_TCONSIG_STH_SP_HS, /*!< STH/SP/HS */
+ VDC5_LCD_TCONSIG_STB_LP_HE, /*!< STB/LP/HE */
+ VDC5_LCD_TCONSIG_CPV_GCK, /*!< CPV/GCK */
+ VDC5_LCD_TCONSIG_POLA, /*!< POLA */
+ VDC5_LCD_TCONSIG_POLB, /*!< POLB */
+ VDC5_LCD_TCONSIG_DE, /*!< DE */
+ VDC5_LCD_TCONSIG_NUM
+} vdc5_lcd_tcon_sigsel_t;
+/*! Output format select */
+typedef enum {
+ VDC5_LCD_OUTFORMAT_RGB888 = 0, /*!< RGB888 */
+ VDC5_LCD_OUTFORMAT_RGB666, /*!< RGB666 */
+ VDC5_LCD_OUTFORMAT_RGB565, /*!< RGB565 */
+ VDC5_LCD_OUTFORMAT_SERIAL_RGB, /*!< Serial RGB */
+ VDC5_LCD_OUTFORMAT_NUM
+} vdc5_lcd_outformat_t;
+/*! Clock frequency control */
+typedef enum {
+ VDC5_LCD_PARALLEL_CLKFRQ_1 = 0, /*!< 100% speed (parallel RGB) */
+ VDC5_LCD_SERIAL_CLKFRQ_3, /*!< Triple speed (serial RGB) */
+ VDC5_LCD_SERIAL_CLKFRQ_4, /*!< Quadruple speed (serial RGB) */
+ VDC5_LCD_SERIAL_CLKFRQ_NUM
+} vdc5_lcd_clkfreqsel_t;
+/*! Scan direction select */
+typedef enum {
+ VDC5_LCD_SERIAL_SCAN_FORWARD = 0, /*!< Forward scan */
+ VDC5_LCD_SERIAL_SCAN_REVERSE = 1 /*!< Reverse scan */
+} vdc5_lcd_scan_t;
+/*! Clock phase adjustment for serial RGB output */
+typedef enum {
+ VDC5_LCD_SERIAL_CLKPHASE_0 = 0, /*!< 0[clk] */
+ VDC5_LCD_SERIAL_CLKPHASE_1, /*!< 1[clk] */
+ VDC5_LCD_SERIAL_CLKPHASE_2, /*!< 2[clk] */
+ VDC5_LCD_SERIAL_CLKPHASE_3, /*!< 3[clk] */
+ VDC5_LCD_SERIAL_CLKPHASE_NUM
+} vdc5_lcd_clkphase_t;
+/*! Display output configuration parameter */
+typedef struct {
+ uint16_t tcon_half; /*!< 1/2fH timing */
+ uint16_t tcon_offset; /*!< Offset Hsync signal timing */
+ const vdc5_lcd_tcon_timing_t * outctrl[VDC5_LCD_TCONSIG_NUM]; /*!< LCD TCON timing signal parameter */
+ vdc5_edge_t outcnt_lcd_edge; /*!< Output phase control of LCD_DATA23
+ to LCD_DATA0 pin */
+ vdc5_onoff_t out_endian_on; /*!< Bit endian change on/off control */
+ vdc5_onoff_t out_swap_on; /*!< B/R signal swap on/off control */
+ vdc5_lcd_outformat_t out_format; /*!< Output format select */
+ vdc5_lcd_clkfreqsel_t out_frq_sel; /*!< Clock frequency control */
+ vdc5_lcd_scan_t out_dir_sel; /*!< Scan direction select */
+ vdc5_lcd_clkphase_t out_phase; /*!< Clock phase adjustment
+ for serial RGB output */
+ uint32_t bg_color; /*!< Background color in 24-bit RGB color format */
+} vdc5_output_t;
+
+/*********************** For R_VDC5_CallbackISR ***********************/
+/*! VDC5 interrupt type */
+typedef enum {
+ VDC5_INT_TYPE_S0_VI_VSYNC = 0, /*!< Vsync signal input to scaler 0 */
+ VDC5_INT_TYPE_S0_LO_VSYNC, /*!< Vsync signal output from scaler 0 */
+ VDC5_INT_TYPE_S0_VSYNCERR, /*!< Missing Vsync signal for scaler 0 */
+ VDC5_INT_TYPE_VLINE, /*!< Specified line signal for panel output in graphics 3 */
+ VDC5_INT_TYPE_S0_VFIELD, /*!< Field end signal for recording function in scaler 0 */
+ VDC5_INT_TYPE_IV1_VBUFERR, /*!< Frame buffer write overflow signal for scaler 0 */
+ VDC5_INT_TYPE_IV3_VBUFERR, /*!< Frame buffer read underflow signal for graphics 0 */
+ VDC5_INT_TYPE_IV5_VBUFERR, /*!< Frame buffer read underflow signal for graphics 2 */
+ VDC5_INT_TYPE_IV6_VBUFERR, /*!< Frame buffer read underflow signal for graphics 3 */
+ VDC5_INT_TYPE_S0_WLINE, /*!< Write specification line signal input to scaling-down control block
+ in scaler 0 */
+ VDC5_INT_TYPE_S1_VI_VSYNC, /*!< Vsync signal input to scaler 1 */
+ VDC5_INT_TYPE_S1_LO_VSYNC, /*!< Vsync signal output from scaler 1 */
+ VDC5_INT_TYPE_S1_VSYNCERR, /*!< Missing Vsync signal for scaler 1 */
+ VDC5_INT_TYPE_S1_VFIELD, /*!< Field end signal for recording function in scaler 1 */
+ VDC5_INT_TYPE_IV2_VBUFERR, /*!< Frame buffer write overflow signal for scaler 1 */
+ VDC5_INT_TYPE_IV4_VBUFERR, /*!< Frame buffer read underflow signal for graphics 1 */
+ VDC5_INT_TYPE_S1_WLINE, /*!< Write specification line signal input to scaling-down control block
+ in scaler 1 */
+ VDC5_INT_TYPE_OIR_VI_VSYNC, /*!< Vsync signal input to output image generator */
+ VDC5_INT_TYPE_OIR_LO_VSYNC, /*!< Vsync signal output from output image generator */
+ VDC5_INT_TYPE_OIR_VLINE, /*!< Specified line signal for panel output in output image generator */
+ VDC5_INT_TYPE_OIR_VFIELD, /*!< Field end signal for recording function in output image generator */
+ VDC5_INT_TYPE_IV7_VBUFERR, /*!< Frame buffer write overflow signal for output image generator */
+ VDC5_INT_TYPE_IV8_VBUFERR, /*!< Frame buffer read underflow signal for graphics (OIR) */
+ VDC5_INT_TYPE_NUM /*!< The number of VDC5 interrupt types */
+} vdc5_int_type_t;
+/*! Interrupt callback setup parameter */
+typedef struct {
+ vdc5_int_type_t type; /*!< VDC5 interrupt type */
+ void (* callback)(vdc5_int_type_t); /*!< Interrupt callback function pointer */
+ uint16_t line_num; /*!< Line interrupt set */
+} vdc5_int_t;
+
+/*********************** For R_VDC5_WriteDataControl ***********************/
+/*! Frame buffer writing mode for image processing */
+typedef enum {
+ VDC5_WR_MD_NORMAL = 0, /*!< Normal */
+ VDC5_WR_MD_MIRROR, /*!< Horizontal mirroring */
+ VDC5_WR_MD_ROT_90DEG, /*!< 90 degree rotation */
+ VDC5_WR_MD_ROT_180DEG, /*!< 180 degree rotation */
+ VDC5_WR_MD_ROT_270DEG, /*!< 270 degree rotation */
+ VDC5_WR_MD_NUM
+} vdc5_wr_md_t;
+/*! Scaling-down and rotation parameter */
+typedef struct {
+ vdc5_period_rect_t res; /*!< Image area to be captured */
+ vdc5_onoff_t res_pfil_sel; /*!< Prefilter mode select for brightness signals (on/off) */
+ uint16_t res_out_vw; /*!< Number of valid lines in vertical direction
+ output by scaling-down control block */
+ uint16_t res_out_hw; /*!< Number of valid horizontal pixels
+ output by scaling-down control block */
+ vdc5_onoff_t adj_sel; /*!< Handling for lack of last-input line (on/off) */
+ vdc5_wr_md_t res_ds_wr_md; /*!< Frame buffer writing mode for image processing */
+} vdc5_scalingdown_rot_t;
+/*! Frame buffer swap setting */
+typedef enum {
+ VDC5_WR_RD_WRSWA_NON = 0, /*!< Not swapped: 1-2-3-4-5-6-7-8 */
+ VDC5_WR_RD_WRSWA_8BIT, /*!< Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */
+ VDC5_WR_RD_WRSWA_16BIT, /*!< Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */
+ VDC5_WR_RD_WRSWA_16_8BIT, /*!< Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */
+ VDC5_WR_RD_WRSWA_32BIT, /*!< Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */
+ VDC5_WR_RD_WRSWA_32_8BIT, /*!< Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */
+ VDC5_WR_RD_WRSWA_32_16BIT, /*!< Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */
+ VDC5_WR_RD_WRSWA_32_16_8BIT, /*!< Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */
+ VDC5_WR_RD_WRSWA_NUM
+} vdc5_wr_rd_swa_t;
+/*! Frame buffer video-signal writing format */
+typedef enum {
+ VDC5_RES_MD_YCBCR422 = 0, /*!< YCbCr422 */
+ VDC5_RES_MD_RGB565, /*!< RGB565 */
+ VDC5_RES_MD_RGB888, /*!< RGB888 */
+ VDC5_RES_MD_YCBCR444, /*!< YCbCr444 */
+ VDC5_RES_MD_NUM
+} vdc5_res_md_t;
+/*! Transfer burst length */
+typedef enum {
+ VDC5_BST_MD_32BYTE = 0, /*!< 32-byte transfer (4 bursts) */
+ VDC5_BST_MD_128BYTE /*!< 128-byte transfer (16 bursts) */
+} vdc5_bst_md_t;
+/*! Field operating mode select */
+typedef enum {
+ VDC5_RES_INTER_PROGRESSIVE = 0, /*!< Progressive */
+ VDC5_RES_INTER_INTERLACE = 1 /*!< Interlace */
+} vdc5_res_inter_t;
+/*! Writing rate */
+typedef enum {
+ VDC5_RES_FS_RATE_PER1 = 0, /* 1/1 an input signal */
+ VDC5_RES_FS_RATE_PER2, /* 1/2 an input signal */
+ VDC5_RES_FS_RATE_PER4, /* 1/4 an input signal */
+ VDC5_RES_FS_RATE_PER8, /* 1/8 an input signal */
+ VDC5_RES_FS_RATE_NUM
+} vdc5_res_fs_rate_t;
+/*! Write field select */
+typedef enum {
+ VDC5_RES_FLD_SEL_TOP = 0, /*!< Top field */
+ VDC5_RES_FLD_SEL_BOTTOM = 1 /*!< Bottom field */
+} vdc5_res_fld_sel_t;
+/*! Data write control parameter */
+typedef struct {
+ vdc5_scalingdown_rot_t scalingdown_rot;/*!< Scaling-down and rotation parameter */
+ vdc5_wr_rd_swa_t res_wrswa; /*!< Swap setting in frame buffer writing */
+ vdc5_res_md_t res_md; /*!< Frame buffer video-signal writing format */
+ vdc5_bst_md_t res_bst_md; /*!< Transfer burst length for frame buffer writing */
+ vdc5_res_inter_t res_inter; /*!< Field operating mode select */
+ vdc5_res_fs_rate_t res_fs_rate; /*!< Writing rate */
+ vdc5_res_fld_sel_t res_fld_sel; /*!< Write field select */
+ vdc5_onoff_t res_dth_on; /*!< Dither correction on/off */
+ void * base; /*!< Frame buffer base address */
+ uint32_t ln_off; /*!< Frame buffer line offset address [byte] */
+ uint32_t flm_num; /*!< Number of frames of buffer to be written to (res_flm_num + 1) */
+ uint32_t flm_off; /*!< Frame buffer frame offset address [byte] */
+ void * btm_base; /*!< Frame buffer base address for bottom */
+} vdc5_write_t;
+
+/*********************** For R_VDC5_ChangeWriteProcess ***********************/
+/*! Data write change parameter */
+typedef struct {
+ vdc5_scalingdown_rot_t scalingdown_rot;/*!< Scaling-down and rotation parameter */
+} vdc5_write_chg_t;
+
+/*********************** For R_VDC5_ReadDataControl ***********************/
+/*! Line offset address direction of the frame buffer */
+typedef enum {
+ VDC5_GR_LN_OFF_DIR_INC = 0, /*!< Increments the address by the line offset address */
+ VDC5_GR_LN_OFF_DIR_DEC /*!< Decrements the address by the line offset address */
+} vdc5_gr_ln_off_dir_t;
+/*! Frame buffer address setting signal */
+typedef enum {
+ VDC5_GR_FLM_SEL_SCALE_DOWN = 0, /*!< Links to scaling-down process */
+ VDC5_GR_FLM_SEL_FLM_NUM, /*!< Selects frame 0 (graphics display) */
+ VDC5_GR_FLM_SEL_DISTORTION, /*!< Links to distortion correction */
+ VDC5_GR_FLM_SEL_POINTER_BUFF, /*!< Links to pointer buffer */
+ VDC5_GR_FLM_SEL_NUM
+} vdc5_gr_flm_sel_t;
+/*! Size of the frame buffer to be read */
+typedef struct {
+ uint16_t in_vw; /*!< Number of lines in a frame */
+ uint16_t in_hw; /*!< Width of the horizontal valid period */
+} vdc5_width_read_fb_t;
+/*! Format of the frame buffer read signal */
+typedef enum {
+ VDC5_GR_FORMAT_RGB565 = 0, /*!< RGB565 */
+ VDC5_GR_FORMAT_RGB888, /*!< RGB888 */
+ VDC5_GR_FORMAT_ARGB1555, /*!< ARGB1555 */
+ VDC5_GR_FORMAT_ARGB4444, /*!< ARGB4444 */
+ VDC5_GR_FORMAT_ARGB8888, /*!< ARGB8888 */
+ VDC5_GR_FORMAT_CLUT8, /*!< CLUT8 */
+ VDC5_GR_FORMAT_CLUT4, /*!< CLUT4 */
+ VDC5_GR_FORMAT_CLUT1, /*!< CLUT1 */
+ VDC5_GR_FORMAT_YCBCR422, /*!< YCbCr422: This setting is prohibited for the graphics 2 and 3 */
+ VDC5_GR_FORMAT_YCBCR444, /*!< YCbCr444: This setting is prohibited for the graphics 2 and 3 */
+ VDC5_GR_FORMAT_RGBA5551, /*!< RGBA5551 */
+ VDC5_GR_FORMAT_RGBA8888, /*!< RGBA8888 */
+ VDC5_GR_FORMAT_NUM /*!< The number of signal formats */
+} vdc5_gr_format_t;
+/*! Swapping of data read from buffer in the YCbCr422 format */
+typedef enum {
+ VDC5_GR_YCCSWAP_CBY0CRY1 = 0,
+ VDC5_GR_YCCSWAP_Y0CBY1CR,
+ VDC5_GR_YCCSWAP_CRY0CBY1,
+ VDC5_GR_YCCSWAP_Y0CRY1CB,
+ VDC5_GR_YCCSWAP_Y1CRY0CB,
+ VDC5_GR_YCCSWAP_CRY1CBY0,
+ VDC5_GR_YCCSWAP_Y1CBY0CR,
+ VDC5_GR_YCCSWAP_CBY1CRY0,
+ VDC5_GR_YCCSWAP_NUM
+} vdc5_gr_ycc_swap_t;
+/*! Data read control parameter */
+typedef struct {
+ vdc5_gr_ln_off_dir_t gr_ln_off_dir; /*!< Line offset address direction of the frame buffer */
+ vdc5_gr_flm_sel_t gr_flm_sel; /*!< Frame buffer address setting signal */
+ vdc5_onoff_t gr_imr_flm_inv; /*!< Frame buffer number for distortion correction */
+ vdc5_bst_md_t gr_bst_md; /*!< Frame buffer burst transfer mode */
+ void * gr_base; /*!< Frame buffer base address */
+ uint32_t gr_ln_off; /*!< Frame buffer line offset address */
+ const vdc5_width_read_fb_t * width_read_fb; /*!< Size of the frame buffer to be read */
+ vdc5_onoff_t adj_sel; /*!< Folding handling (on/off) */
+ vdc5_gr_format_t gr_format; /*!< Format of the frame buffer read signal */
+ vdc5_gr_ycc_swap_t gr_ycc_swap; /*!< Swapping of data read from buffer
+ in the YCbCr422 format */
+ vdc5_wr_rd_swa_t gr_rdswa; /*!< Swap setting in frame buffer reading */
+ vdc5_period_rect_t gr_grc; /*!< Graphics display area */
+} vdc5_read_t;
+
+/******************************* For R_VDC5_ChangeReadProcess *******************************/
+/*! The type of graphics display modes */
+typedef enum {
+ VDC5_DISPSEL_IGNORED = -1, /*!< Ignored */
+ VDC5_DISPSEL_BACK = 0, /*!< Background color display */
+ VDC5_DISPSEL_LOWER = 1, /*!< Lower-layer graphics display */
+ VDC5_DISPSEL_CURRENT = 2, /*!< Current graphics display */
+ VDC5_DISPSEL_BLEND = 3, /*!< Blended display of lower-layer graphics and current graphics */
+ VDC5_DISPSEL_NUM = 4 /*!< The number of graphics display modes */
+} vdc5_gr_disp_sel_t;
+/*! Data read change parameter */
+typedef struct {
+ void * gr_base; /*!< Frame buffer base address */
+ const vdc5_width_read_fb_t * width_read_fb; /*!< Size of the frame buffer to be read */
+ const vdc5_period_rect_t * gr_grc; /*!< Graphics display area */
+ const vdc5_gr_disp_sel_t * gr_disp_sel; /*!< Graphics display mode */
+} vdc5_read_chg_t;
+
+/******************************* For R_VDC5_StartProcess *******************************/
+/*! Data write/read start parameter */
+typedef struct {
+ const vdc5_gr_disp_sel_t * gr_disp_sel; /*!< Graphics display mode */
+} vdc5_start_t;
+
+/******************************* For R_VDC5_VideoNoiseReduction *******************************/
+/*! TAP select */
+typedef enum {
+ VDC5_NR_TAPSEL_1 = 0, /*!< Adjacent pixel */
+ VDC5_NR_TAPSEL_2, /*!< 2 adjacent pixels */
+ VDC5_NR_TAPSEL_3, /*!< 3 adjacent pixels */
+ VDC5_NR_TAPSEL_4, /*!< 4 adjacent pixels */
+ VDC5_NR_TAPSEL_NUM
+} vdc5_nr_tap_t;
+/*! Noise reduction gain adjustment */
+typedef enum {
+ VDC5_NR_GAIN_1_2 = 0, /*!< 1/2 */
+ VDC5_NR_GAIN_1_4, /*!< 1/4 */
+ VDC5_NR_GAIN_1_8, /*!< 1/8 */
+ VDC5_NR_GAIN_1_16, /*!< 1/16 */
+ VDC5_NR_GAIN_NUM
+} vdc5_nr_gain_t;
+/*! Noise reduction parameter */
+typedef struct {
+ vdc5_nr_tap_t nr1d_tap; /*!< TAP select */
+ uint32_t nr1d_th; /*!< Maximum value of coring (absolute value) */
+ vdc5_nr_gain_t nr1d_gain; /*!< Noise reduction gain adjustment */
+} vdc5_nr_param_t;
+/*! Noise reduction setup parameter */
+typedef struct {
+ vdc5_nr_param_t y; /*!< Y/G signal noise reduction parameter */
+ vdc5_nr_param_t cb; /*!< Cb/B signal noise reduction parameter */
+ vdc5_nr_param_t cr; /*!< Cr/R signal noise reduction parameter */
+} vdc5_noise_reduction_t;
+
+/******************************* For R_VDC5_ImageColorMatrix *******************************/
+/*! Color matrix module */
+typedef enum {
+ VDC5_COLORMTX_IMGCNT = 0, /*!< Input Controller (input video signal) */
+ VDC5_COLORMTX_ADJ_0, /*!< Image quality improver 0 (scaler 0 output) */
+ VDC5_COLORMTX_ADJ_1, /*!< Image quality improver 1 (scaler 1 output) */
+ VDC5_COLORMTX_NUM
+} vdc5_colormtx_module_t;
+/*! Operating mode */
+typedef enum {
+ VDC5_COLORMTX_GBR_GBR = 0, /*!< GBR to GBR */
+ VDC5_COLORMTX_GBR_YCBCR, /*!< GBR to YCbCr */
+ VDC5_COLORMTX_YCBCR_GBR, /*!< YCbCr to GBR */
+ VDC5_COLORMTX_YCBCR_YCBCR, /*!< YCbCr to YCbCr */
+ VDC5_COLORMTX_MODE_NUM /*!< The number of operating modes */
+} vdc5_colormtx_mode_t;
+/*! Color matrix offset (DC) adjustment */
+typedef enum {
+ VDC5_COLORMTX_OFFST_YG = 0, /*!< YG */
+ VDC5_COLORMTX_OFFST_B, /*!< B */
+ VDC5_COLORMTX_OFFST_R, /*!< R */
+ VDC5_COLORMTX_OFFST_NUM /*!< The number of the color matrix DC offset values */
+} vdc5_colormtx_offset_t;
+/*! Color matrix signal gain adjustment */
+typedef enum {
+ VDC5_COLORMTX_GAIN_GG = 0, /*!< GG */
+ VDC5_COLORMTX_GAIN_GB, /*!< GB */
+ VDC5_COLORMTX_GAIN_GR, /*!< GR */
+ VDC5_COLORMTX_GAIN_BG, /*!< BG */
+ VDC5_COLORMTX_GAIN_BB, /*!< BB */
+ VDC5_COLORMTX_GAIN_BR, /*!< BR */
+ VDC5_COLORMTX_GAIN_RG, /*!< RG */
+ VDC5_COLORMTX_GAIN_RB, /*!< RB */
+ VDC5_COLORMTX_GAIN_RR, /*!< RR */
+ VDC5_COLORMTX_GAIN_NUM /*!< The number of the color matrix gain values */
+} vdc5_colormtx_gain_t;
+/*! Color matrix setup parameter */
+typedef struct {
+ vdc5_colormtx_module_t module; /*!< Color matrix module */
+ vdc5_colormtx_mode_t mtx_mode; /*!< Operating mode */
+ uint16_t offset[VDC5_COLORMTX_OFFST_NUM];/*!< Offset (DC) adjustment of Y/G, B, and R signal */
+ uint16_t gain[VDC5_COLORMTX_GAIN_NUM]; /*!< GG, GB, GR, BG, BB, BR, RG, RB, and RR signal
+ gain adjustment */
+} vdc5_color_matrix_t;
+
+/******************************* For R_VDC5_ImageEnhancement *******************************/
+/*! Image quality improver ID */
+typedef enum {
+ VDC5_IMG_IMPRV_0 = 0, /*!< Image quality improver 0 */
+ VDC5_IMG_IMPRV_1, /*!< Image quality improver 1 */
+ VDC5_IMG_IMPRV_NUM /*!< The number of image quality improvers */
+} vdc5_imgimprv_id_t;
+
+/*! Sharpness band */
+typedef enum {
+ VDC5_IMGENH_SHARP_H1 = 0, /*!< H1: Adjacent pixel used as reference */
+ VDC5_IMGENH_SHARP_H2, /*!< H2: Second adjacent pixel used as reference */
+ VDC5_IMGENH_SHARP_H3, /*!< H3: Third adjacent pixel used as reference */
+ VDC5_IMGENH_SHARP_NUM /*!< The number of horizontal sharpness bands */
+} vdc5_img_enh_sh_t;
+/*! Sharpness control parameter */
+typedef struct {
+ uint8_t shp_clip_o; /*!< Sharpness correction value clipping (on the overshoot side) */
+ uint8_t shp_clip_u; /*!< Sharpness correction value clipping (on the undershoot side) */
+ uint8_t shp_gain_o; /*!< Sharpness edge amplitude value gain (on the overshoot side) */
+ uint8_t shp_gain_u; /*!< Sharpness edge amplitude value gain (on the undershoot side) */
+ uint8_t shp_core; /*!< Active sharpness range */
+} vdc5_sharpness_ctrl_t;
+/*! Sharpness setup parameter */
+typedef struct {
+ vdc5_onoff_t shp_h2_lpf_sel; /*!< LPF selection for folding prevention
+ before H2 edge detection */
+ vdc5_sharpness_ctrl_t hrz_sharp[VDC5_IMGENH_SHARP_NUM]; /*!< Sharpness control parameter (H1, H2, and H3) */
+} vdc5_enhance_sharp_t;
+/*! LTI band */
+typedef enum {
+ VDC5_IMGENH_LTI1 = 0, /*!< H2: Second adjacent pixel used as reference */
+ VDC5_IMGENH_LTI2, /*!< H4: Fourth adjacent pixel used as reference */
+ VDC5_IMGENH_LTI_NUM /*!< The number of horizontal LTI bands */
+} vdc5_img_enh_lti_t;
+/*! Median filter reference pixel select */
+typedef enum {
+ VDC5_LTI_MDFIL_SEL_ADJ2 = 0, /*!< Second adjacent pixel selected as reference */
+ VDC5_LTI_MDFIL_SEL_ADJ1 /*!< Adjacent pixel selected as reference */
+} vdc5_lti_mdfil_sel_t;
+/*! LTI control parameter */
+typedef struct {
+ uint8_t lti_inc_zero; /*!< Median filter LTI correction threshold */
+ uint8_t lti_gain; /*!< LTI edge amplitude value gain */
+ uint8_t lti_core; /*!< LTI coring (maximum core value of 255) */
+} vdc5_lti_ctrl_t;
+/*! Luminance Transient Improvement setup parameter */
+typedef struct {
+ vdc5_onoff_t lti_h2_lpf_sel; /*!< LPF selection for folding prevention
+ before H2 edge detection */
+ vdc5_lti_mdfil_sel_t lti_h4_median_tap_sel; /*!< Median filter reference pixel select */
+ vdc5_lti_ctrl_t lti[VDC5_IMGENH_LTI_NUM]; /*!< LTI control parameter (H2 and H4) */
+} vdc5_enhance_lti_t;
+
+/******************************* For R_VDC5_ImageBlackStretch *******************************/
+/*! Black stretch setup parameter */
+typedef struct {
+ uint16_t bkstr_st; /*!< Black stretch start point */
+ uint16_t bkstr_d; /*!< Black stretch depth */
+ uint16_t bkstr_t1; /*!< Black stretch time constant (T1) */
+ uint16_t bkstr_t2; /*!< Black stretch time constant (T2) */
+} vdc5_black_t;
+
+/******************************* For R_VDC5_AlphaBlending *******************************/
+/*! Alpha signal of the ARGB1555/ARGB5551 format */
+typedef struct {
+ uint8_t gr_a0; /*!< Alpha signal when alpha is set to '0' */
+ uint8_t gr_a1; /*!< Alpha signal when alpha is set to '1' */
+} vdc5_alpha_argb1555_t;
+/*! Alpha blending in one-pixel units */
+typedef struct {
+ vdc5_onoff_t gr_acalc_md; /*!< Premultiplication processing at alpha blending
+ in one-pixel units (on/off) */
+} vdc5_alpha_pixel_t;
+/*! Alpha blending setup parameter */
+typedef struct {
+ const vdc5_alpha_argb1555_t * alpha_1bit; /*!< Alpha signal of the ARGB1555/ARGB5551 format */
+ const vdc5_alpha_pixel_t * alpha_pixel;/*!< Premultiplication processing at alpha blending in one-pixel */
+} vdc5_alpha_blending_t;
+
+/******************************* For R_VDC5_AlphaBlendingRect *******************************/
+/*! Parameter for alpha blending in a rectangular area */
+typedef struct {
+ int16_t gr_arc_coef; /*!< Alpha coefficient for alpha blending in a rectangular area
+ (-255 to 255) */
+ uint8_t gr_arc_rate; /*!< Frame rate for alpha blending in a rectangular area (gr_arc_rate + 1) */
+ uint8_t gr_arc_def; /*!< Initial alpha value for alpha blending in a rectangular area */
+ vdc5_onoff_t gr_arc_mul; /*!< Multiplication processing with current alpha at alpha blending
+ in a rectangular area (on/off) */
+} vdc5_alpha_rect_t;
+/*! Selection of lower-layer plane in scaler */
+typedef struct {
+ vdc5_onoff_t gr_vin_scl_und_sel; /*!< Selection of lower-layer plane in scaler
+ - VDC5_OFF: Selects graphics 0 as lower-layer graphics
+ and graphics 1 as current graphics
+ - VDC5_ON: Selects graphics 1 as lower-layer graphics
+ and graphics 0 as current graphics */
+} vdc5_scl_und_sel_t;
+/*! Setup parameter for alpha blending in a rectangular area */
+typedef struct {
+ const vdc5_pd_disp_rect_t * gr_arc; /*!< Rectangular area subjected to alpha blending */
+ const vdc5_alpha_rect_t * alpha_rect; /*!< Parameter for alpha blending in a rectangular area */
+ const vdc5_scl_und_sel_t * scl_und_sel;/*!< Selection of lower-layer plane in scaler */
+} vdc5_alpha_blending_rect_t;
+
+/******************************* For R_VDC5_Chromakey *******************************/
+/*! Chroma-key setup parameter */
+typedef struct {
+ uint32_t ck_color; /*!< RGB/CLUT signal for RGB/CLUT-index chroma-key processing */
+ uint32_t rep_color; /*!< Replaced ARGB signal after RGB/CLUT-index chroma-key processing */
+ uint8_t rep_alpha; /*!< Replaced alpha signal after RGB-index chroma-key processing (in 8 bits) */
+} vdc5_chromakey_t;
+
+/******************************* For R_VDC5_CLUT *******************************/
+/*! CLUT setup parameter */
+typedef struct {
+ uint32_t color_num; /*!< The number of colors in CLUT */
+ const uint32_t * clut; /*!< Address of the area storing the CLUT data (in ARGB8888 format) */
+} vdc5_clut_t;
+
+/******************************* For R_VDC5_DisplayCalibration *******************************/
+/*! Correction circuit sequence control */
+typedef enum {
+ VDC5_CALIBR_ROUTE_BCG = 0, /*!< Brightness -> contrast -> gamma correction */
+ VDC5_CALIBR_ROUTE_GBC /*!< Gamma correction -> brightness -> contrast */
+} vdc5_calibr_route_t;
+/*! Brightness (DC) adjustment parameter */
+typedef struct {
+ uint16_t pbrt_g; /*!< Brightness (DC) adjustment of G signal */
+ uint16_t pbrt_b; /*!< Brightness (DC) adjustment of B signal */
+ uint16_t pbrt_r; /*!< Brightness (DC) adjustment of R signal */
+} vdc5_calibr_bright_t;
+/*! Contrast (gain) adjustment parameter */
+typedef struct {
+ uint8_t cont_g; /*!< Contrast (gain) adjustment of G signal */
+ uint8_t cont_b; /*!< Contrast (gain) adjustment of B signal */
+ uint8_t cont_r; /*!< Contrast (gain) adjustment of R signal */
+} vdc5_calibr_contrast_t;
+/*! Panel dither operation mode */
+typedef enum {
+ VDC5_PDTH_MD_TRU = 0, /*!< Truncate */
+ VDC5_PDTH_MD_RDOF, /*!< Round-off */
+ VDC5_PDTH_MD_2X2, /*!< 2 x 2 pattern dither */
+ VDC5_PDTH_MD_RAND, /*!< Random pattern dither */
+ VDC5_PDTH_MD_NUM
+} vdc5_panel_dither_md_t;
+/*! Panel dithering parameter */
+typedef struct {
+ vdc5_panel_dither_md_t pdth_sel; /*!< Panel dither operation mode */
+ uint8_t pdth_pa; /*!< Pattern value (A) of 2x2 pattern dither */
+ uint8_t pdth_pb; /*!< Pattern value (B) of 2x2 pattern dither */
+ uint8_t pdth_pc; /*!< Pattern value (C) of 2x2 pattern dither */
+ uint8_t pdth_pd; /*!< Pattern value (D) of 2x2 pattern dither */
+} vdc5_calibr_dither_t;
+/*! Display calibration parameter */
+typedef struct {
+ vdc5_calibr_route_t route; /*!< Correction circuit sequence control */
+ const vdc5_calibr_bright_t * bright; /*!< Brightness (DC) adjustment parameter */
+ const vdc5_calibr_contrast_t * contrast; /*!< Contrast (gain) adjustment parameter */
+ const vdc5_calibr_dither_t * panel_dither; /*!< Panel dithering parameter */
+} vdc5_disp_calibration_t;
+
+/******************************* For R_VDC5_GammaCorrection *******************************/
+/*! Gamma correction setup parameter */
+typedef struct {
+ const uint16_t * gam_g_gain; /*!< Gain adjustment of area 0 to 31 of G signal */
+ const uint8_t * gam_g_th; /*!< Start threshold of area 1 to 31 of G signal */
+ const uint16_t * gam_b_gain; /*!< Gain adjustment of area 0 to 31 of B signal */
+ const uint8_t * gam_b_th; /*!< Start threshold of area 1 to 31 of B signal */
+ const uint16_t * gam_r_gain; /*!< Gain adjustment of area 0 to 31 of R signal */
+ const uint8_t * gam_r_th; /*!< Start threshold of area 1 to 31 of R signal */
+} vdc5_gamma_correction_t;
+
+
+/******************************************************************************
+Exported global variables
+******************************************************************************/
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+vdc5_error_t R_VDC5_Initialize(
+ const vdc5_channel_t ch,
+ const vdc5_init_t * const param,
+ void (* const init_func)(uint32_t),
+ const uint32_t user_num);
+vdc5_error_t R_VDC5_Terminate(const vdc5_channel_t ch, void (* const quit_func)(uint32_t), const uint32_t user_num);
+vdc5_error_t R_VDC5_VideoInput(const vdc5_channel_t ch, const vdc5_input_t * const param);
+vdc5_error_t R_VDC5_SyncControl(const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param);
+vdc5_error_t R_VDC5_DisplayOutput(const vdc5_channel_t ch, const vdc5_output_t * const param);
+vdc5_error_t R_VDC5_CallbackISR(const vdc5_channel_t ch, const vdc5_int_t * const param);
+vdc5_error_t R_VDC5_WriteDataControl(
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_write_t * const param);
+vdc5_error_t R_VDC5_ChangeWriteProcess(
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_write_chg_t * const param);
+vdc5_error_t R_VDC5_ReadDataControl(
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_read_t * const param);
+vdc5_error_t R_VDC5_ChangeReadProcess(
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_read_chg_t * const param);
+vdc5_error_t R_VDC5_StartProcess(
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_start_t * const param);
+vdc5_error_t R_VDC5_StopProcess(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+vdc5_error_t R_VDC5_ReleaseDataControl(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+vdc5_error_t R_VDC5_VideoNoiseReduction(
+ const vdc5_channel_t ch,
+ const vdc5_onoff_t nr1d_on,
+ const vdc5_noise_reduction_t * const param);
+vdc5_error_t R_VDC5_ImageColorMatrix(const vdc5_channel_t ch, const vdc5_color_matrix_t * const param);
+vdc5_error_t R_VDC5_ImageEnhancement(
+ const vdc5_channel_t ch,
+ const vdc5_imgimprv_id_t imgimprv_id,
+ const vdc5_onoff_t shp_h_on,
+ const vdc5_enhance_sharp_t * const sharp_param,
+ const vdc5_onoff_t lti_h_on,
+ const vdc5_enhance_lti_t * const lti_param,
+ const vdc5_period_rect_t * const enh_area);
+vdc5_error_t R_VDC5_ImageBlackStretch(
+ const vdc5_channel_t ch,
+ const vdc5_imgimprv_id_t imgimprv_id,
+ const vdc5_onoff_t bkstr_on,
+ const vdc5_black_t * const param);
+vdc5_error_t R_VDC5_AlphaBlending(
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_alpha_blending_t * const param);
+vdc5_error_t R_VDC5_AlphaBlendingRect(
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_onoff_t gr_arc_on,
+ const vdc5_alpha_blending_rect_t * const param);
+vdc5_error_t R_VDC5_Chromakey(
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_onoff_t gr_ck_on,
+ const vdc5_chromakey_t * const param);
+vdc5_error_t R_VDC5_CLUT(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_clut_t * const param);
+vdc5_error_t R_VDC5_DisplayCalibration(const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param);
+vdc5_error_t R_VDC5_GammaCorrection(
+ const vdc5_channel_t ch,
+ const vdc5_onoff_t gam_on,
+ const vdc5_gamma_correction_t * const param);
+
+void (*R_VDC5_GetISR(const vdc5_channel_t ch, const vdc5_int_type_t type))(const uint32_t int_sense);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* R_VDC5_H */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/vdc5/include/r_vdc5_user.h Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,103 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file r_vdc5_user.h
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief VDC5 driver user-defined header
+******************************************************************************/
+
+#ifndef R_VDC5_USER_H
+#define R_VDC5_USER_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "iodefine.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/*! Compilation switch to enable parameter check functions<br>
+ If this definition is enabled, the parameter check in each API function will be performed. */
+#define R_VDC5_CHECK_PARAMETERS
+
+
+/*! GBR to YCbCr conversion <br>
+ * Matrix coefficient (typical value) for SMPTE 293M
+ * - Y = 0.299 * R + 0.587 * G + 0.114 * B
+ * - Cb = -0.169 * R - 0.331 * G + 0.500 * B
+ * - Cr = 0.500 * R - 0.419 * G - 0.081 * B
+ * @note
+ * Coefficient values are represented in 11-bit two's complement integer
+ * - DEFINITION = int(COEF * 256 + 0.5)
+ */
+typedef enum {
+ VDC5_COLORCONV_Y_R = (77u),
+ VDC5_COLORCONV_Y_G = (150u),
+ VDC5_COLORCONV_Y_B = (29u),
+ VDC5_COLORCONV_CB_R = (2005u),
+ VDC5_COLORCONV_CB_G = (1963u),
+ VDC5_COLORCONV_CB_B = (128u),
+ VDC5_COLORCONV_CR_R = (128u),
+ VDC5_COLORCONV_CR_G = (1941u),
+ VDC5_COLORCONV_CR_B = (2027u)
+} vdc5_colcnv_rgb_ycbcr_t;
+
+/*! YCbCr to GBR conversion <br>
+ * Matrix coefficient (typical value) for SMPTE 293M
+ * - G = 1.0 * Y - 0.344 * Cb - 0.714 * Cr
+ * - B = 1.0 * Y + 1.772 * Cb + 0.0 * Cr
+ * - R = 1.0 * Y + 0.0 * Cb + 1.402 * Cr
+ * @note
+ * Coefficient values are represented in 11-bit two's complement integer
+ * - DEFINITION = int(COEF * 256 + 0.5)
+ */
+typedef enum {
+ VDC5_COLORCONV_G_Y = (256u),
+ VDC5_COLORCONV_G_CB = (1960u),
+ VDC5_COLORCONV_G_CR = (1865u),
+ VDC5_COLORCONV_B_Y = (256u),
+ VDC5_COLORCONV_B_CB = (454u),
+ VDC5_COLORCONV_B_CR = (0u),
+ VDC5_COLORCONV_R_Y = (256u),
+ VDC5_COLORCONV_R_CB = (0u),
+ VDC5_COLORCONV_R_CR = (359u)
+} vdc5_colcnv_ycbcr_rgb_t;
+
+/*! Color matrix DC offset typical value */
+#define VDC5_COLORCONV_DC_OFFSET (128u)
+/*! Color matrix coefficient value that represents one times */
+#define VDC5_COLORCONV_1TIMES_GAIN (256u)
+
+/*! 1usec wait cycle for LVDS PLL */
+#define VDC5_LVDS_PLL_WAIT_CYCLE (38u)
+/*! 200usec wait counter for LVDS PLL */
+#define VDC5_LVDS_PLL_WAIT_200USEC (13400u)
+
+
+#endif /* R_VDC5_USER_H */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/vdc5/src/r_vdc5.c Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,1224 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file r_vdc5.c
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief VDC5 driver API function
+******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_vdc5.h"
+#include "r_vdc5_user.h"
+#include "r_vdc5_register.h"
+#include "r_vdc5_shared_param.h"
+#include "r_vdc5_check_parameter.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static vdc5_scaling_type_t ConvertRwProcId2SclId(const vdc5_layer_id_t layer_id);
+static vdc5_graphics_type_t ConvertRwProcId2GrId(const vdc5_layer_id_t layer_id);
+
+
+/**************************************************************************//**
+ * @brief VDC5 driver initialization
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Initializes the VDC5 driver's internal variables.
+ * - Calls the user-defined function specified in init_func.
+ * - Sets up and enables the VDC5's panel clock.
+ * - Sets up and enables the LVDS only if LVDS is used.
+ * - Disables all the VDC5 interrupts.
+ * @param[in] ch : Channel
+ * @param[in] param : Initialization parameter
+ * @param[in] init_func : Pointer to a user-defined function
+ * @param[in] user_num : User defined number
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_Initialize (
+ const vdc5_channel_t ch,
+ const vdc5_init_t * const param,
+ void (* const init_func)(uint32_t),
+ const uint32_t user_num)
+{
+ vdc5_error_t ret;
+ vdc5_resource_state_t rsrc_state;
+
+ ret = VDC5_OK;
+#ifdef R_VDC5_CHECK_PARAMETERS
+ ret = VDC5_InitializeCheckPrm(ch, param);
+#endif /* R_VDC5_CHECK_PARAMETERS */
+ if (ret == VDC5_OK) {
+ VDC5_ShrdPrmInit(ch);
+ /* Resource checks */
+ rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_LVDS_CLK);
+ if (rsrc_state != VDC5_RESOURCE_ST_INVALID) {
+ /* The LVDS PLL clock has been already set. */
+ if (param->lvds != NULL) {
+ ret = VDC5_ERR_RESOURCE_LVDS_CLK;
+ }
+ }
+ }
+ if (ret == VDC5_OK) {
+ VDC5_ShrdPrmSetInitParam(ch, param);
+
+ /* Callback function */
+ if (init_func != 0) {
+ init_func(user_num);
+ }
+
+ VDC5_Initialize(ch, param);
+
+ /* Disable all VDC5 interrupts */
+ VDC5_Int_Disable(ch);
+
+ VDC5_ShrdPrmSetResource(ch, VDC5_RESOURCE_PANEL_CLK, VDC5_RESOURCE_ST_VALID);
+ if (param->lvds != NULL) {
+ VDC5_ShrdPrmSetResource(ch, VDC5_RESOURCE_LVDS_CLK, VDC5_RESOURCE_ST_VALID);
+ }
+ }
+ return ret;
+} /* End of function R_VDC5_Initialize() */
+
+/**************************************************************************//**
+ * @brief VDC5 driver termination
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Disables all the VDC5 interrupts.
+ * - Disables the VDC5 panel clock.
+ * - Disables the LVDS if one is used and becomes unnecessary as the result of calling this function.
+ * - Calls the user-defined function specified in quit_func.
+ * @param[in] ch : Channel
+ * @param[in] quit_func : Pointer to a user-defined function
+ * @param[in] user_num : User defined number
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_Terminate (const vdc5_channel_t ch, void (* const quit_func)(uint32_t), const uint32_t user_num)
+{
+ vdc5_error_t ret;
+ vdc5_onoff_t lvds_ref;
+
+ ret = VDC5_OK;
+#ifdef R_VDC5_CHECK_PARAMETERS
+ ret = VDC5_TerminateCheckPrm(ch);
+#endif /* R_VDC5_CHECK_PARAMETERS */
+ if (ret == VDC5_OK) {
+ VDC5_ShrdPrmSetTerminate(ch);
+
+ /* Disable all VDC5 interrupts */
+ VDC5_Int_Disable(ch);
+
+ VDC5_Terminate(ch);
+
+ VDC5_ShrdPrmSetResource(ch, VDC5_RESOURCE_PANEL_CLK, VDC5_RESOURCE_ST_INVALID);
+
+ lvds_ref = VDC5_ShrdPrmGetLvdsClkRef();
+ if (lvds_ref == VDC5_OFF) { /* LVDS PLL clock is not referred. */
+ VDC5_ShrdPrmSetResource(ch, VDC5_RESOURCE_LVDS_CLK, VDC5_RESOURCE_ST_INVALID);
+ }
+
+ /* Callback function */
+ if (quit_func != 0) {
+ quit_func(user_num);
+ }
+ }
+ return ret;
+} /* End of function R_VDC5_Terminate() */
+
+/**************************************************************************//**
+ * @brief Video input setup
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Selects the video input.
+ * - Sets up the phase timing of the input signals.
+ * - Performs delay control on the sync signal for the video inputs.
+ * - Sets up the parameters for the external input video signals only when they are used.
+ * @param[in] ch : Channel
+ * @param[in] param : Video input setup parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_VideoInput (const vdc5_channel_t ch, const vdc5_input_t * const param)
+{
+ vdc5_error_t ret;
+
+ ret = VDC5_OK;
+#ifdef R_VDC5_CHECK_PARAMETERS
+ ret = VDC5_VideoInputCheckPrm(ch, param);
+#endif /* R_VDC5_CHECK_PARAMETERS */
+ if (ret == VDC5_OK) {
+ VDC5_ShrdPrmSetInputParam(ch, param);
+
+ /* Setting VDC5 registers */
+ VDC5_VideoInput(ch, param);
+
+ VDC5_ShrdPrmSetResource(ch, VDC5_RESOURCE_VIDEO_IN, VDC5_RESOURCE_ST_VALID);
+ }
+ return ret;
+} /* End of function R_VDC5_VideoInput() */
+
+/**************************************************************************//**
+ * @brief Sync control setup
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Selects the vertical sync signal.
+ * - Sets up the period of the sync signal.
+ * - Sets up the delay of the vertical sync signal.
+ * - Sets up the full-screen enable signal.
+ * - Sets up the compensation for the vertical sync signal.
+ * @param[in] ch : Channel
+ * @param[in] param : Sync control parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_SyncControl (const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param)
+{
+ vdc5_error_t ret;
+ vdc5_resource_state_t rsrc_state;
+
+ ret = VDC5_OK;
+#ifdef R_VDC5_CHECK_PARAMETERS
+ ret = VDC5_SyncControlCheckPrm(ch, param);
+#endif /* R_VDC5_CHECK_PARAMETERS */
+ if (ret == VDC5_OK) {
+ /* Resource checks */
+ rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_PANEL_CLK);
+ if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+ ret = VDC5_ERR_RESOURCE_CLK;
+ }
+ }
+ if (ret == VDC5_OK) {
+ if (param->res_vs_sel == VDC5_OFF) {
+ /* External input Vsync signal is selected. */
+ if (param->res_vs_in_sel == VDC5_RES_VS_IN_SEL_SC0) {
+ /* Scaler 0 */
+ rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_VIDEO_IN);
+ } else {
+ /* Scaler 1 */
+ rsrc_state = VDC5_ShrdPrmGetResource(
+ ((ch == VDC5_CHANNEL_0) ? VDC5_CHANNEL_1 : VDC5_CHANNEL_0),
+ VDC5_RESOURCE_VIDEO_IN);
+ }
+ if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+ ret = VDC5_ERR_RESOURCE_INPUT;
+ }
+ }
+ }
+ if (ret == VDC5_OK) {
+ VDC5_ShrdPrmSetSyncParam(ch, param);
+
+ /* Setting VDC5 registers */
+ VDC5_SyncControl(ch, param);
+
+ VDC5_ShrdPrmSetResource(ch, VDC5_RESOURCE_VSYNC, VDC5_RESOURCE_ST_VALID);
+ }
+ return ret;
+} /* End of function R_VDC5_SyncControl() */
+
+/**************************************************************************//**
+ * @brief Display output setup
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Sets up the timing signals for driving the LCD panel.
+ * - Sets up the phase, data sequence, and format of the LCD panel output data.
+ * - Sets up the background color.
+ * @param[in] ch : Channel
+ * @param[in] param : Display output configuration parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_DisplayOutput (const vdc5_channel_t ch, const vdc5_output_t * const param)
+{
+ vdc5_error_t ret;
+ vdc5_resource_state_t rsrc_state;
+
+ ret = VDC5_OK;
+#ifdef R_VDC5_CHECK_PARAMETERS
+ ret = VDC5_DisplayOutputCheckPrm(ch, param);
+#endif /* R_VDC5_CHECK_PARAMETERS */
+ if (ret == VDC5_OK) {
+ /* Resource checks */
+ rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_PANEL_CLK);
+ if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+ ret = VDC5_ERR_RESOURCE_CLK;
+ } else {
+ rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_VSYNC);
+ if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+ ret = VDC5_ERR_RESOURCE_VSYNC;
+ }
+ }
+ }
+ if (ret == VDC5_OK) {
+ VDC5_ShrdPrmSetOutputParam(ch, param);
+
+ /* Setting VDC5 registers */
+ VDC5_DisplayOutput(ch, param);
+
+ VDC5_ShrdPrmSetResource(ch, VDC5_RESOURCE_LCD_PANEL, VDC5_RESOURCE_ST_VALID);
+ }
+ return ret;
+} /* End of function R_VDC5_DisplayOutput() */
+
+/**************************************************************************//**
+ * @brief Interrupt callback setup
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.
+ * - Registers the specified interrupt callback function.
+ * - Disables the interrupt when the pointer to the corresponding interrupt callback function is not
+ * specified.
+ * @param[in] ch : Channel
+ * @param[in] param : Interrupt callback setup parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_CallbackISR (const vdc5_channel_t ch, const vdc5_int_t * const param)
+{
+ vdc5_error_t ret;
+ vdc5_resource_state_t rsrc_state;
+
+ ret = VDC5_OK;
+#ifdef R_VDC5_CHECK_PARAMETERS
+ ret = VDC5_CallbackISRCheckPrm(ch, param);
+#endif /* R_VDC5_CHECK_PARAMETERS */
+ if (ret == VDC5_OK) {
+ /* Resource checks */
+ rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_PANEL_CLK);
+ if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+ ret = VDC5_ERR_RESOURCE_CLK;
+ } else {
+ rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_VSYNC);
+ if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+ ret = VDC5_ERR_RESOURCE_VSYNC;
+ }
+ }
+ }
+ if (ret == VDC5_OK) {
+ /* Setting VDC5 registers */
+ VDC5_Int_SetInterrupt(ch, param);
+ }
+ return ret;
+} /* End of function R_VDC5_CallbackISR() */
+
+/**************************************************************************//**
+ * @brief Data write control processing
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Sets up the input image area to be captured.
+ * - Makes input image scale-down/rotation control settings (layers 0 and 1 only).
+ * - Makes frame buffer write control settings.
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * - VDC5_LAYER_ID_0_WR
+ * - VDC5_LAYER_ID_1_WR
+ * - VDC5_LAYER_ID_OIR_WR
+ * @param[in] param : Data write control parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_WriteDataControl (
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_write_t * const param)
+{
+ vdc5_error_t ret;
+ vdc5_scaling_type_t scaling_id;
+ vdc5_resource_state_t rsrc_state;
+
+ scaling_id = ConvertRwProcId2SclId(layer_id);
+
+ ret = VDC5_OK;
+#ifdef R_VDC5_CHECK_PARAMETERS
+ ret = VDC5_WriteDataControlCheckPrm(ch, layer_id, param);
+#endif /* R_VDC5_CHECK_PARAMETERS */
+ if (ret == VDC5_OK) {
+ /* Resource checks */
+ rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, layer_id);
+ if (rsrc_state != VDC5_RESOURCE_ST_INVALID) {
+ /* The specified layer is already used. */
+ ret = VDC5_ERR_RESOURCE_LAYER;
+ } else {
+ if (layer_id == VDC5_LAYER_ID_0_WR) {
+ /* Layer 0 */
+ rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_VIDEO_IN);
+ } else if (layer_id == VDC5_LAYER_ID_1_WR) {
+ /* Layer 1 */
+ rsrc_state = VDC5_ShrdPrmGetResource(
+ ((ch == VDC5_CHANNEL_0) ? VDC5_CHANNEL_1 : VDC5_CHANNEL_0),
+ VDC5_RESOURCE_VIDEO_IN);
+ } else {
+ /* Layer OIR */
+ rsrc_state = VDC5_RESOURCE_ST_VALID;
+ }
+ if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+ ret = VDC5_ERR_RESOURCE_INPUT;
+ }
+ }
+ }
+ if (ret == VDC5_OK) {
+ VDC5_ShrdPrmSetWriteParam(ch, scaling_id, param);
+
+ /* Setting VDC5 registers */
+ VDC5_WriteDataControl(ch, scaling_id, param);
+
+ VDC5_ShrdPrmSetLayerResource(ch, layer_id, VDC5_RESOURCE_ST_VALID);
+ }
+ return ret;
+} /* End of function R_VDC5_WriteDataControl() */
+
+/**************************************************************************//**
+ * @brief Data write change processing
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Changes the input image area to be captured.
+ * - Makes changes with respect to scaling-down/rotation control of the input image (layers 0 and 1 only).
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * - VDC5_LAYER_ID_0_WR
+ * - VDC5_LAYER_ID_1_WR
+ * - VDC5_LAYER_ID_OIR_WR
+ * @param[in] param : Data write change parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ChangeWriteProcess (
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_write_chg_t * const param)
+{
+ vdc5_error_t ret;
+ vdc5_scaling_type_t scaling_id;
+ vdc5_resource_state_t rsrc_state;
+
+ scaling_id = ConvertRwProcId2SclId(layer_id);
+
+ ret = VDC5_OK;
+#ifdef R_VDC5_CHECK_PARAMETERS
+ ret = VDC5_ChangeWriteProcessCheckPrm(ch, layer_id, param);
+#endif /* R_VDC5_CHECK_PARAMETERS */
+ if (ret == VDC5_OK) {
+ /* Resource checks */
+ rsrc_state = VDC5_ShrdPrmGetRwProcEnabled(ch, layer_id);
+ if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+ /* The specified layer is invalid. */
+ ret = VDC5_ERR_RESOURCE_LAYER;
+ }
+ }
+ if (ret == VDC5_OK) {
+ VDC5_ShrdPrmSetChgWriteParam(ch, scaling_id, param);
+
+ /* Setting VDC5 registers */
+ VDC5_ChangeWriteProcess(ch, scaling_id, param);
+ }
+ return ret;
+} /* End of function R_VDC5_ChangeWriteProcess() */
+
+/**************************************************************************//**
+ * @brief Data read control processing
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Sets up the display area for graphics images.
+ * - Makes image scale-up control settings (layers 0 and 1 only).
+ * - Makes frame buffer read control settings.
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * - VDC5_LAYER_ID_0_RD
+ * - VDC5_LAYER_ID_1_RD
+ * - VDC5_LAYER_ID_2_RD
+ * - VDC5_LAYER_ID_3_RD
+ * - VDC5_LAYER_ID_OIR_RD
+ * @param[in] param : Data read control parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ReadDataControl (
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_read_t * const param)
+{
+ vdc5_error_t ret;
+ vdc5_graphics_type_t graphics_id;
+ vdc5_resource_state_t rsrc_state;
+
+ graphics_id = ConvertRwProcId2GrId(layer_id);
+
+ ret = VDC5_OK;
+#ifdef R_VDC5_CHECK_PARAMETERS
+ ret = VDC5_ReadDataControlCheckPrm(ch, layer_id, graphics_id, param);
+#endif /* R_VDC5_CHECK_PARAMETERS */
+ if (ret == VDC5_OK) {
+ /* Resource checks */
+ rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, layer_id);
+ if (rsrc_state != VDC5_RESOURCE_ST_INVALID) {
+ /* The specified layer is already used. */
+ ret = VDC5_ERR_RESOURCE_LAYER;
+ }
+ }
+ if (ret == VDC5_OK) {
+ VDC5_ShrdPrmSetReadParam(ch, graphics_id, param);
+
+ /* Setting VDC5 registers */
+ VDC5_ReadDataControl(ch, graphics_id, param);
+
+ VDC5_ShrdPrmSetLayerResource(ch, layer_id, VDC5_RESOURCE_ST_VALID);
+ }
+ return ret;
+} /* End of function R_VDC5_ReadDataControl() */
+
+/**************************************************************************//**
+ * @brief Data read change processing
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Changes the frame buffer base address.
+ * - Changes the frame buffer read size (image scale-up control) (layers 0 and 1 only).
+ * - Changes the display area for graphics images.
+ * - Changes the graphics display mode.
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * - VDC5_LAYER_ID_0_RD
+ * - VDC5_LAYER_ID_1_RD
+ * - VDC5_LAYER_ID_2_RD
+ * - VDC5_LAYER_ID_3_RD
+ * - VDC5_LAYER_ID_OIR_RD
+ * @param[in] param : Data read change parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ChangeReadProcess (
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_read_chg_t * const param)
+{
+ vdc5_error_t ret;
+ vdc5_graphics_type_t graphics_id;
+ vdc5_resource_state_t rsrc_state;
+
+ graphics_id = ConvertRwProcId2GrId(layer_id);
+
+ ret = VDC5_OK;
+#ifdef R_VDC5_CHECK_PARAMETERS
+ ret = VDC5_ChangeReadProcessCheckPrm(ch, layer_id, param);
+#endif /* R_VDC5_CHECK_PARAMETERS */
+ if (ret == VDC5_OK) {
+ /* Resource checks */
+ rsrc_state = VDC5_ShrdPrmGetRwProcEnabled(ch, layer_id);
+ if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+ /* The specified layer is invalid. */
+ ret = VDC5_ERR_RESOURCE_LAYER;
+ }
+ }
+ if (ret == VDC5_OK) {
+ VDC5_ShrdPrmSetChgReadParam(ch, graphics_id, param);
+
+ /* Setting VDC5 registers */
+ VDC5_ChangeReadProcess(ch, graphics_id, param);
+ }
+ return ret;
+} /* End of function R_VDC5_ChangeReadProcess() */
+
+/**************************************************************************//**
+ * @brief Data write/read start processing
+ *
+ * Description:<br>
+ * This function performs layer start processing. If the layer ID specified in layer_id
+ * is VDC5_LAYER_ID_ALL, the function starts all the layers that are in the stopped state
+ * and also enabled. If the layer ID is not VDC5_LAYER_ID_ALL, the function starts only
+ * the specified layer.<br>
+ * When performing start processing for write, the function starts a write to the frame buffer.
+ * When performing start processing for read, the function starts a read from the frame buffer
+ * and sets the graphics display mode to the specified values for each layer.
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @param[in] param : Data write/read start parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_StartProcess (
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_start_t * const param)
+{
+ vdc5_error_t ret;
+ vdc5_resource_state_t rsrc_state;
+
+ ret = VDC5_OK;
+#ifdef R_VDC5_CHECK_PARAMETERS
+ ret = VDC5_StartProcessCheckPrm(ch, layer_id, param);
+#endif /* R_VDC5_CHECK_PARAMETERS */
+ if (ret == VDC5_OK) {
+ /* Resource checks */
+ if (layer_id != VDC5_LAYER_ID_ALL) {
+ rsrc_state = VDC5_ShrdPrmGetRwProcReady(ch, layer_id);
+ if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+ /* The specified layer is invalid. */
+ ret = VDC5_ERR_RESOURCE_LAYER;
+ }
+ }
+ }
+ if (ret == VDC5_OK) {
+ /* Setting VDC5 registers */
+ VDC5_StartProcess(ch, layer_id, param);
+ }
+ return ret;
+} /* End of function R_VDC5_StartProcess() */
+
+/**************************************************************************//**
+ * @brief Data write/read stop processing
+ *
+ * Description:<br>
+ * This function performs layer stop processing. If the layer ID specified in layer_id is
+ * VDC5_LAYER_ID_ALL, the function stops all the layers that are enabled and running.
+ * If the layer ID is not VDC5_LAYER_ID_ALL, the function stops only the specified layer.<br>
+ * When performing stop processing for write, the function stops the write to the frame buffer.
+ * When performing stop processing for read, the function stops the read from the frame buffer
+ * and resets the graphics display mode to the initial values for each of the layers.
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_StopProcess (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+ vdc5_error_t ret;
+ vdc5_resource_state_t rsrc_state;
+
+ ret = VDC5_OK;
+#ifdef R_VDC5_CHECK_PARAMETERS
+ ret = VDC5_StopProcessCheckPrm(ch, layer_id);
+#endif /* R_VDC5_CHECK_PARAMETERS */
+ if (ret == VDC5_OK) {
+ /* Resource checks */
+ if (layer_id != VDC5_LAYER_ID_ALL) {
+ rsrc_state = VDC5_ShrdPrmGetRwProcEnabled(ch, layer_id);
+ if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+ /* The specified layer is invalid. */
+ ret = VDC5_ERR_RESOURCE_LAYER;
+ }
+ }
+ }
+ if (ret == VDC5_OK) {
+ /* Setting VDC5 registers */
+ VDC5_StopProcess(ch, layer_id);
+ }
+ return ret;
+} /* End of function R_VDC5_StopSurface() */
+
+/**************************************************************************//**
+ * @brief Data write/read control release processing
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Disables the specified layer.
+ * - Initializes the cascaded connection settings (layer 1 read processing only).
+ * - Initializes the VIN synthesizer settings (layer 0 and 1 read processing only).
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ReleaseDataControl (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+ vdc5_error_t ret;
+ vdc5_resource_state_t rsrc_state;
+
+ ret = VDC5_OK;
+#ifdef R_VDC5_CHECK_PARAMETERS
+ ret = VDC5_ReleaseDataControlCheckPrm(ch, layer_id);
+#endif /* R_VDC5_CHECK_PARAMETERS */
+ if (ret == VDC5_OK) {
+ /* Resource checks */
+ if (layer_id != VDC5_LAYER_ID_ALL) {
+ rsrc_state = VDC5_ShrdPrmGetRwProcReady(ch, layer_id);
+ if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+ /* The specified layer is invalid. */
+ ret = VDC5_ERR_RESOURCE_LAYER;
+ }
+ }
+ }
+ if (ret == VDC5_OK) {
+ /* Setting VDC5 registers */
+ VDC5_ReleaseDataControl(ch, layer_id);
+
+ VDC5_ShrdPrmSetLayerResource(ch, layer_id, VDC5_RESOURCE_ST_INVALID);
+ }
+ return ret;
+} /* End of function R_VDC5_ReleaseDataControl() */
+
+/**************************************************************************//**
+ * @brief Noise reduction setup
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Turns on and off noise reduction processing.
+ * - Sets up the noise reduction parameters for the Y/G, Cb/B, and Cr/R signals.
+ * @param[in] ch : Channel
+ * @param[in] nr1d_on : Noise reduction ON/OFF setting
+ * @param[in] param : Noise reduction setup parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_VideoNoiseReduction (
+ const vdc5_channel_t ch,
+ const vdc5_onoff_t nr1d_on,
+ const vdc5_noise_reduction_t * const param)
+{
+ vdc5_error_t ret;
+ vdc5_resource_state_t rsrc_state;
+
+ ret = VDC5_OK;
+#ifdef R_VDC5_CHECK_PARAMETERS
+ ret = VDC5_VideoNoiseReductCheckPrm(ch, param);
+#endif /* R_VDC5_CHECK_PARAMETERS */
+ if (ret == VDC5_OK) {
+ /* Resource checks */
+ rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_VIDEO_IN);
+ if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+ ret = VDC5_ERR_RESOURCE_INPUT;
+ }
+ }
+ if (ret == VDC5_OK) {
+ /* Setting VDC5 registers */
+ VDC5_VideoNoiseReduction(ch, nr1d_on, param);
+ }
+ return ret;
+} /* End of function R_VDC5_VideoNoiseReduction() */
+
+/**************************************************************************//**
+ * @brief Color matrix setup
+ *
+ * Description:<br>
+ * This function sets up the specified color matrix.
+ * @param[in] ch : Channel
+ * @param[in] param : Color matrix setup parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ImageColorMatrix (const vdc5_channel_t ch, const vdc5_color_matrix_t * const param)
+{
+ vdc5_error_t ret;
+ vdc5_resource_state_t rsrc_state;
+
+ ret = VDC5_OK;
+#ifdef R_VDC5_CHECK_PARAMETERS
+ ret = VDC5_ImageColorMatrixCheckPrm(ch, param);
+#endif /* R_VDC5_CHECK_PARAMETERS */
+ if (ret == VDC5_OK) {
+ /* Resource checks */
+ if (param->module == VDC5_COLORMTX_IMGCNT) {
+ rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_0_WR);
+ if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+ rsrc_state = VDC5_ShrdPrmGetLayerResource(
+ ((ch == VDC5_CHANNEL_0) ? VDC5_CHANNEL_1 : VDC5_CHANNEL_0),
+ VDC5_LAYER_ID_1_WR);
+ }
+ } else if (param->module == VDC5_COLORMTX_ADJ_0) {
+ rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_0_RD);
+ } else {
+ rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_1_RD);
+ }
+
+ if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+ ret = VDC5_ERR_RESOURCE_LAYER;
+ }
+ }
+ if (ret == VDC5_OK) {
+ /* Setting VDC5 registers */
+ VDC5_ImageColorMatrix(ch, param);
+ }
+ return ret;
+} /* End of function R_VDC5_ImageColorMatrix() */
+
+/**************************************************************************//**
+ * @brief Image enhancement processing
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Turns on and off sharpness processing.
+ * - Sets up the sharpness parameter.
+ * - Turns on and off LTI processing.
+ * - Sets up the LTI parameter.
+ * - Sets up the enhancer-enabled area to be subjected to sharpness and LTI processing.
+ * @param[in] ch : Channel
+ * @param[in] imgimprv_id : Image quality improver ID
+ * @param[in] shp_h_on : Sharpness ON/OFF setting
+ * @param[in] sharp_param : Sharpness setup parameter
+ * @param[in] lti_h_on : LTI ON/OFF setting
+ * @param[in] lti_param : LTI setup parameter
+ * @param[in] enh_area : Enhancer-enabled area setup parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ImageEnhancement (
+ const vdc5_channel_t ch,
+ const vdc5_imgimprv_id_t imgimprv_id,
+ const vdc5_onoff_t shp_h_on,
+ const vdc5_enhance_sharp_t * const sharp_param,
+ const vdc5_onoff_t lti_h_on,
+ const vdc5_enhance_lti_t * const lti_param,
+ const vdc5_period_rect_t * const enh_area)
+{
+ vdc5_error_t ret;
+ vdc5_resource_state_t rsrc_state;
+ vdc5_color_space_t color_space;
+
+ ret = VDC5_OK;
+#ifdef R_VDC5_CHECK_PARAMETERS
+ ret = VDC5_ImageEnhancementCheckPrm(ch, imgimprv_id, sharp_param, enh_area);
+#endif /* R_VDC5_CHECK_PARAMETERS */
+ if (ret == VDC5_OK) {
+ /* Resource checks */
+ rsrc_state = VDC5_ShrdPrmGetLayerResource(
+ ch,
+ ((imgimprv_id == VDC5_IMG_IMPRV_0) ? VDC5_LAYER_ID_0_RD : VDC5_LAYER_ID_1_RD));
+ if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+ /* The layer is invalid. */
+ ret = VDC5_ERR_RESOURCE_LAYER;
+ } else {
+ /* Condition checks */
+ color_space = VDC5_ShrdPrmGetColorSpaceFbRd(
+ ch,
+ ((imgimprv_id == VDC5_IMG_IMPRV_0) ? VDC5_GR_TYPE_GR0 : VDC5_GR_TYPE_GR1));
+ if (color_space == VDC5_COLOR_SPACE_GBR) {
+ /* The image quality improver does not act on RGB signals. */
+ ret = VDC5_ERR_IF_CONDITION;
+ }
+ }
+ }
+ if (ret == VDC5_OK) {
+ /* Setting VDC5 registers */
+ VDC5_ImageEnhancement(ch, imgimprv_id, shp_h_on, sharp_param, lti_h_on, lti_param, enh_area);
+ }
+ return ret;
+} /* End of function R_VDC5_ImageEnhancement() */
+
+/**************************************************************************//**
+ * @brief Black stretch setup
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Turns on and off black stretch processing.
+ * - Sets up the black stretch parameters.
+ * @param[in] ch : Channel
+ * @param[in] imgimprv_id : Image quality improver ID
+ * @param[in] bkstr_on : Black stretch ON/OFF setting
+ * @param[in] param : Black stretch setup parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ImageBlackStretch (
+ const vdc5_channel_t ch,
+ const vdc5_imgimprv_id_t imgimprv_id,
+ const vdc5_onoff_t bkstr_on,
+ const vdc5_black_t * const param)
+{
+ vdc5_error_t ret;
+ vdc5_resource_state_t rsrc_state;
+ vdc5_color_space_t color_space;
+
+ ret = VDC5_OK;
+#ifdef R_VDC5_CHECK_PARAMETERS
+ ret = VDC5_ImageBlackStretchCheckPrm(ch, imgimprv_id, param);
+#endif /* R_VDC5_CHECK_PARAMETERS */
+ if (ret == VDC5_OK) {
+ /* Resource checks */
+ rsrc_state = VDC5_ShrdPrmGetLayerResource(
+ ch,
+ ((imgimprv_id == VDC5_IMG_IMPRV_0) ? VDC5_LAYER_ID_0_RD : VDC5_LAYER_ID_1_RD));
+ if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+ /* The layer is invalid. */
+ ret = VDC5_ERR_RESOURCE_LAYER;
+ } else {
+ /* Condition checks */
+ color_space = VDC5_ShrdPrmGetColorSpaceFbRd(
+ ch,
+ ((imgimprv_id == VDC5_IMG_IMPRV_0) ? VDC5_GR_TYPE_GR0 : VDC5_GR_TYPE_GR1));
+ if (color_space == VDC5_COLOR_SPACE_GBR) {
+ /* The image quality improver does not act on RGB signals. */
+ ret = VDC5_ERR_IF_CONDITION;
+ }
+ }
+ }
+ if (ret == VDC5_OK) {
+ /* Setting VDC5 registers */
+ VDC5_ImageBlackStretch(ch, imgimprv_id, bkstr_on, param);
+ }
+ return ret;
+} /* End of function R_VDC5_ImageBlackStretch() */
+
+/**************************************************************************//**
+ * @brief Alpha blending setup
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Sets up the alpha value of the ARGB1555/RGBA5551 formats.
+ * - Make settings for premultiplication processing at alpha blending in one-pixel.
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * - VDC5_LAYER_ID_1_RD
+ * - VDC5_LAYER_ID_2_RD
+ * - VDC5_LAYER_ID_3_RD
+ * @param[in] param : Alpha blending setup parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_AlphaBlending (
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_alpha_blending_t * const param)
+{
+ vdc5_error_t ret;
+ vdc5_graphics_type_t graphics_id;
+ vdc5_resource_state_t rsrc_state;
+
+ graphics_id = ConvertRwProcId2GrId(layer_id);
+
+ ret = VDC5_OK;
+#ifdef R_VDC5_CHECK_PARAMETERS
+ ret = VDC5_AlphaBlendingCheckPrm(ch, layer_id, param);
+#endif /* R_VDC5_CHECK_PARAMETERS */
+ if (ret == VDC5_OK) {
+ /* Resource checks */
+ rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, layer_id);
+ if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+ /* The specified layer is invalid. */
+ ret = VDC5_ERR_RESOURCE_LAYER;
+ }
+ }
+ if (ret == VDC5_OK) {
+ /* Setting VDC5 registers */
+ VDC5_AlphaBlending(ch, graphics_id, param);
+ }
+ return ret;
+} /* End of function R_VDC5_AlphaBlending() */
+
+/**************************************************************************//**
+ * @brief Rectangle alpha blending setup
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Turns on and off alpha blending in a rectangular area.
+ * - Sets up the rectangular area subjected to alpha blending.
+ * - Sets up the alpha value for alpha blending in a rectangular area.
+ * - Makes fade-in/-out settings to be applied to rectangle alpha blending.
+ * - Allocates graphics 0 and 1 to the lower-layer/current graphics in the VIN synthesizer.
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * - VDC5_LAYER_ID_1_RD
+ * - VDC5_LAYER_ID_2_RD
+ * - VDC5_LAYER_ID_3_RD
+ * - VDC5_LAYER_ID_VIN_RD
+ * @param[in] gr_arc_on : ON/OFF setting for alpha blending in a rectangular area
+ * @param[in] param : Setup parameter for alpha blending in a rectangular area
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_AlphaBlendingRect (
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_onoff_t gr_arc_on,
+ const vdc5_alpha_blending_rect_t * const param)
+{
+ vdc5_error_t ret;
+ vdc5_graphics_type_t graphics_id;
+ vdc5_color_space_t color_space;
+ vdc5_resource_state_t rsrc_state;
+
+ graphics_id = ConvertRwProcId2GrId(layer_id);
+
+ ret = VDC5_OK;
+#ifdef R_VDC5_CHECK_PARAMETERS
+ ret = VDC5_AlphaBlendingRectCheckPrm(ch, layer_id, param);
+#endif /* R_VDC5_CHECK_PARAMETERS */
+ if (ret == VDC5_OK) {
+ if (layer_id != VDC5_LAYER_ID_VIN_RD) {
+ /* Resource checks */
+ rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, layer_id);
+ if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+ /* The specified layer is invalid. */
+ ret = VDC5_ERR_RESOURCE_LAYER;
+ } else {
+ /* Condition checks */
+ color_space = VDC5_ShrdPrmGetColorSpaceFbRd(ch, graphics_id);
+ if (color_space == VDC5_COLOR_SPACE_YCBCR) {
+ /* Alpha blending cannot be used
+ when the format of the signal read from the frame buffer is YCbCr422 or YCbCr444. */
+ ret = VDC5_ERR_IF_CONDITION;
+ }
+ }
+ }
+ }
+ if (ret == VDC5_OK) {
+ /* Setting VDC5 registers */
+ VDC5_AlphaBlendingRect(ch, graphics_id, gr_arc_on, param);
+ }
+ return ret;
+} /* End of function R_VDC5_AlphaBlendingRect() */
+
+/**************************************************************************//**
+ * @brief Chroma-key setup
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Turns on and off the chroma-key processing.
+ * - Sets up the color signals to be subject to chroma-key processing and
+ * the color signals after replacement.
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * - VDC5_LAYER_ID_0_RD
+ * - VDC5_LAYER_ID_1_RD
+ * - VDC5_LAYER_ID_2_RD
+ * - VDC5_LAYER_ID_3_RD
+ * - VDC5_LAYER_ID_OIR_RD
+ * @param[in] gr_ck_on : Chroma-key ON/OFF setting
+ * @param[in] param : Chroma-key setup parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_Chromakey (
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_onoff_t gr_ck_on,
+ const vdc5_chromakey_t * const param)
+{
+ vdc5_error_t ret;
+ vdc5_graphics_type_t graphics_id;
+ vdc5_color_space_t color_space;
+ vdc5_resource_state_t rsrc_state;
+
+ graphics_id = ConvertRwProcId2GrId(layer_id);
+
+ ret = VDC5_OK;
+#ifdef R_VDC5_CHECK_PARAMETERS
+ ret = VDC5_ChromakeyCheckPrm(ch, layer_id, graphics_id, param);
+#endif /* R_VDC5_CHECK_PARAMETERS */
+ if (ret == VDC5_OK) {
+ /* Resource checks */
+ rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, layer_id);
+ if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+ /* The specified layer is invalid. */
+ ret = VDC5_ERR_RESOURCE_LAYER;
+ } else {
+ /* Condition checks */
+ color_space = VDC5_ShrdPrmGetColorSpaceFbRd(ch, graphics_id);
+ if (color_space == VDC5_COLOR_SPACE_YCBCR) {
+ /* Chroma-key processing cannot be used
+ when the format of the signal read from the frame buffer is YCbCr422 or YCbCr444. */
+ ret = VDC5_ERR_IF_CONDITION;
+ }
+ }
+ }
+ if (ret == VDC5_OK) {
+ /* Setting VDC5 registers */
+ VDC5_Chromakey(ch, graphics_id, gr_ck_on, param);
+ }
+ return ret;
+} /* End of function R_VDC5_Chromakey() */
+
+/**************************************************************************//**
+ * @brief CLUT setup
+ *
+ * Description:<br>
+ * This function sets up CLUT for the specified layer.
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * - VDC5_LAYER_ID_0_RD
+ * - VDC5_LAYER_ID_1_RD
+ * - VDC5_LAYER_ID_2_RD
+ * - VDC5_LAYER_ID_3_RD
+ * - VDC5_LAYER_ID_OIR_RD
+ * @param[in] param : CLUT setup parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_CLUT (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_clut_t * const param)
+{
+ vdc5_error_t ret;
+ vdc5_graphics_type_t graphics_id;
+ vdc5_resource_state_t rsrc_state;
+
+ graphics_id = ConvertRwProcId2GrId(layer_id);
+
+ ret = VDC5_OK;
+#ifdef R_VDC5_CHECK_PARAMETERS
+ ret = VDC5_CLUTCheckPrm(ch, layer_id, graphics_id, param);
+#endif /* R_VDC5_CHECK_PARAMETERS */
+ if (ret == VDC5_OK) {
+ /* Resource checks */
+ rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, layer_id);
+ if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+ /* The specified layer is invalid. */
+ ret = VDC5_ERR_RESOURCE_LAYER;
+ }
+ }
+ if (ret == VDC5_OK) {
+ /* Setting VDC5 registers */
+ VDC5_CLUT(ch, graphics_id, param);
+ }
+ return ret;
+} /* End of function R_VDC5_SetCLUT() */
+
+/**************************************************************************//**
+ * @brief Display calibration processing
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Sets up panel brightness adjustment.
+ * - Sets up contrast adjustment.
+ * - Sets up panel dithering.
+ * - Makes control settings for the correction circuit sequence.
+ * @param[in] ch : Channel
+ * @param[in] param : Display calibration parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_DisplayCalibration (const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param)
+{
+ vdc5_error_t ret;
+ vdc5_resource_state_t rsrc_state;
+
+ ret = VDC5_OK;
+#ifdef R_VDC5_CHECK_PARAMETERS
+ ret = VDC5_DisplayCalibrationCheckPrm(ch, param);
+#endif /* R_VDC5_CHECK_PARAMETERS */
+ if (ret == VDC5_OK) {
+ /* Resource checks */
+ rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_LCD_PANEL);
+ if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+ ret = VDC5_ERR_RESOURCE_OUTPUT;
+ }
+ }
+ if (ret == VDC5_OK) {
+ /* Setting VDC5 registers */
+ VDC5_DisplayCalibration(ch, param);
+ }
+ return ret;
+} /* End of function R_VDC5_DisplayCalibration() */
+
+/**************************************************************************//**
+ * @brief Gamma correction setup
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Turns on and off gamma correction processing.
+ * - Sets up the gamma correction gain adjustment values for the G/B/R signals.
+ * - Sets up the gamma correction start threshold values for the G/B/R signals.
+ * @param[in] ch : Channel
+ * @param[in] gam_on : Gamma correction ON/OFF setting
+ * @param[in] param : Gamma correction setup parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_GammaCorrection (
+ const vdc5_channel_t ch,
+ const vdc5_onoff_t gam_on,
+ const vdc5_gamma_correction_t * const param)
+{
+ vdc5_error_t ret;
+ vdc5_resource_state_t rsrc_state;
+
+ ret = VDC5_OK;
+#ifdef R_VDC5_CHECK_PARAMETERS
+ ret = VDC5_GammaCorrectionCheckPrm(ch, param);
+#endif /* R_VDC5_CHECK_PARAMETERS */
+ if (ret == VDC5_OK) {
+ /* Resource checks */
+ rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_LCD_PANEL);
+ if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+ ret = VDC5_ERR_RESOURCE_OUTPUT;
+ }
+ }
+ if (ret == VDC5_OK) {
+ /* Setting VDC5 registers */
+ VDC5_GammaCorrection(ch, gam_on, param);
+ }
+ return ret;
+} /* End of function R_VDC5_GammaCorrection() */
+
+/******************************************************************************
+Local Functions
+******************************************************************************/
+/**************************************************************************//**
+ * @brief Convert read/write process ID into scaling type ID
+ *
+ * @param[in] layer_id : Layer ID
+ * @retval Scaling type ID
+ *****************************************************************************/
+static vdc5_scaling_type_t ConvertRwProcId2SclId (const vdc5_layer_id_t layer_id)
+{
+ vdc5_scaling_type_t scaling_id;
+
+ switch (layer_id) {
+ case VDC5_LAYER_ID_0_WR: /* Layer 0, write process */
+ scaling_id = VDC5_SC_TYPE_SC0; /* Scaler 0 */
+ break;
+ case VDC5_LAYER_ID_1_WR: /* Layer 1, write process */
+ scaling_id = VDC5_SC_TYPE_SC1; /* Scaler 1 */
+ break;
+ case VDC5_LAYER_ID_OIR_WR: /* Layer OIR, write process */
+ scaling_id = VDC5_SC_TYPE_OIR; /* OIR */
+ break;
+ default: /* Error */
+ scaling_id = VDC5_SC_TYPE_NUM;
+ break;
+ }
+ return scaling_id;
+} /* End of function ConvertRwProcId2SclId() */
+
+/**************************************************************************//**
+ * @brief Convert read/write process ID into graphics type ID
+ *
+ * @param[in] layer_id : Layer ID
+ * @retval Graphics type ID
+ *****************************************************************************/
+static vdc5_graphics_type_t ConvertRwProcId2GrId (const vdc5_layer_id_t layer_id)
+{
+ vdc5_graphics_type_t graphics_id;
+
+ switch (layer_id) {
+ case VDC5_LAYER_ID_0_RD: /* Layer 0, read process */
+ graphics_id = VDC5_GR_TYPE_GR0; /* Graphics 0 */
+ break;
+ case VDC5_LAYER_ID_1_RD: /* Layer 1, read process */
+ graphics_id = VDC5_GR_TYPE_GR1; /* Graphics 1 */
+ break;
+ case VDC5_LAYER_ID_2_RD: /* Layer 2, read process */
+ graphics_id = VDC5_GR_TYPE_GR2; /* Graphics 2 */
+ break;
+ case VDC5_LAYER_ID_3_RD: /* Layer 3, read process */
+ graphics_id = VDC5_GR_TYPE_GR3; /* Graphics 3 */
+ break;
+ case VDC5_LAYER_ID_VIN_RD: /* Layer VIN, read process */
+ graphics_id = VDC5_GR_TYPE_VIN; /* VIN */
+ break;
+ case VDC5_LAYER_ID_OIR_RD: /* Layer OIR, read process */
+ graphics_id = VDC5_GR_TYPE_OIR; /* OIR */
+ break;
+ default: /* Error */
+ graphics_id = VDC5_GR_TYPE_NUM;
+ break;
+ }
+ return graphics_id;
+} /* End of function ConvertRwProcId2GrId() */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/vdc5/src/r_vdc5_check_parameter.c Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,1952 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file r_vdc5_check_parameter.c
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief VDC5 driver parameter check processing
+******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_vdc5.h"
+#include "r_vdc5_user.h"
+#include "r_vdc5_shared_param.h"
+#include "r_vdc5_check_parameter.h"
+
+
+#ifdef R_VDC5_CHECK_PARAMETERS
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* Valid bit range */
+#define VDC5_CPARA_RANGE_0X00000001 (0x00000001u)
+#define VDC5_CPARA_RANGE_0X00000003 (0x00000003u)
+#define VDC5_CPARA_RANGE_0X00000007 (0x00000007u)
+#define VDC5_CPARA_RANGE_0X0000000F (0x0000000Fu)
+#define VDC5_CPARA_RANGE_0X0000001F (0x0000001Fu)
+#define VDC5_CPARA_RANGE_0X0000003F (0x0000003Fu)
+#define VDC5_CPARA_RANGE_0X0000007F (0x0000007Fu)
+#define VDC5_CPARA_RANGE_0X000000FF (0x000000FFu)
+#define VDC5_CPARA_RANGE_0X000003FF (0x000003FFu)
+#define VDC5_CPARA_RANGE_0X000007FF (0x000007FFu)
+#define VDC5_CPARA_RANGE_0X00007FFF (0x00007FFFu)
+#define VDC5_CPARA_RANGE_0X0000FFFF (0x0000FFFFu)
+#define VDC5_CPARA_RANGE_0X007FFFFF (0x007FFFFFu)
+#define VDC5_CPARA_RANGE_0X00FFFFFF (0x00FFFFFFu)
+/* Valid range for signal delay amount */
+#define VDC5_CPARA_INP_FLD_DLY_MAX (254u)
+#define VDC5_CPARA_INP_VS_DLY_MAX (254u)
+#define VDC5_CPARA_INP_HS_DLY_MAX (254u)
+/* Valid range for NFS */
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_56 (56u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_24 (24u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_28 (28u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_31 (31u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_37 (37u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_39 (39u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_46 (46u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_47 (47u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_55 (55u)
+/* Valid range for HS + HW */
+#define VDC5_CPARA_HS_HW_MAX (2015u)
+/* Valid range for HS */
+#define VDC5_CPARA_HS_MIN (16u)
+/* Valid range for VS + VW */
+#define VDC5_CPARA_VS_VW_MAX (2039u)
+/* Valid range for VS */
+#define VDC5_CPARA_VS_MIN (4u)
+/* The max number of CLUT data values */
+#define VDC5_CPARA_CLUT8_NUM (256u)
+#define VDC5_CPARA_CLUT4_NUM (16u)
+#define VDC5_CPARA_CLUT1_NUM (2u)
+/* Valid range for the alpha coefficient */
+#define VDC5_CPARA_GR_ARC_COEF_MIN (-255)
+#define VDC5_CPARA_GR_ARC_COEF_MAX (255)
+/* Valid range for HS of enhancer area */
+#define VDC5_CPARA_ENH_HS_LIMIT (4u)
+/* Valid range for VS of enhancer area */
+#define VDC5_CPARA_ENH_VS_LIMIT (2u)
+
+#define VDC5_BKSTR_T2_PROHIBITED (31u)
+
+#define VDC5_MULTIPLE_4_MASK (0x00000003u)
+#define VDC5_MULTIPLE_32_MASK (0x0000001Fu)
+#define VDC5_MULTIPLE_128_MASK (0x0000007Fu)
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static vdc5_error_t CheckChannel(const vdc5_channel_t ch);
+static vdc5_error_t CheckLayerId(const vdc5_layer_id_t layer_id);
+static vdc5_error_t CheckGraphicsTypeLayerId(const vdc5_layer_id_t layer_id);
+static vdc5_error_t CheckRect(const vdc5_period_rect_t * const rect);
+static vdc5_error_t CheckTcon_Vertical(const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing);
+static vdc5_error_t CheckTcon_Horizontal(const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing);
+static vdc5_error_t CheckTcon_HorizontalPol(const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing);
+static vdc5_error_t CheckTcon_DataEnable(const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing);
+static vdc5_error_t CheckGammaCrct_GainAdjustment(const uint16_t * gam_gain);
+
+
+/**************************************************************************//**
+ * @brief Checks on initialization parameter
+ * @param[in] ch : Channel
+ * @param[in] param : Initialization parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_InitializeCheckPrm (const vdc5_channel_t ch, const vdc5_init_t * const param)
+{
+ vdc5_error_t error;
+ const vdc5_lvds_t * lvds_tmp;
+ vdc5_resource_state_t rsrc_state;
+ vdc5_input_sel_t inp_sel_tmp;
+ vdc5_channel_t lvds_vdc_sel_tmp;
+
+ error = CheckChannel(ch);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+
+ if (param == NULL) {
+ error = VDC5_ERR_PARAM_NULL;
+ goto END;
+ }
+
+ /* Panel clock select */
+ if (param->panel_icksel >= VDC5_PANEL_ICKSEL_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ if ((param->panel_icksel != VDC5_PANEL_ICKSEL_LVDS) && (param->panel_icksel != VDC5_PANEL_ICKSEL_LVDS_DIV7)) {
+ /* Clock frequency division ratio */
+ if (param->panel_dcdr >= VDC5_PANEL_CLKDIV_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ }
+ rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_VIDEO_IN);
+ if (rsrc_state != VDC5_RESOURCE_ST_INVALID) {
+ inp_sel_tmp = VDC5_ShrdPrmGetInputSelect(ch);
+ if (((inp_sel_tmp == VDC5_INPUT_SEL_VDEC) && (param->panel_icksel == VDC5_PANEL_ICKSEL_IMG_DV)) ||
+ ((inp_sel_tmp == VDC5_INPUT_SEL_EXT) && (param->panel_icksel == VDC5_PANEL_ICKSEL_IMG))) {
+ error = VDC5_ERR_PARAM_CONDITION;
+ goto END;
+ }
+ }
+
+ /* LVDS-related parameter */
+ lvds_tmp = param->lvds;
+ if (lvds_tmp == NULL) {
+ rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_LVDS_CLK);
+ if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+ /* The LVDS PLL clock has not been set yet. */
+ if ((param->panel_icksel == VDC5_PANEL_ICKSEL_LVDS) || (param->panel_icksel == VDC5_PANEL_ICKSEL_LVDS_DIV7)) {
+ error = VDC5_ERR_PARAM_NULL;
+ goto END;
+ }
+ } else {
+ if (param->panel_icksel == VDC5_PANEL_ICKSEL_LVDS_DIV7) {
+ lvds_vdc_sel_tmp = VDC5_ShrdPrmGetLvdsCh();
+ if (ch != lvds_vdc_sel_tmp) {
+ /* Channel mismatch error */
+ error = VDC5_ERR_PARAM_CONDITION;
+ goto END;
+ }
+ }
+ }
+ } else {
+ /* The clock input to frequency divider 1 */
+ if (lvds_tmp->lvds_in_clk_sel >= VDC5_LVDS_INCLK_SEL_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ /* The frequency dividing value (NIDIV and NODIV) for frequency divider 1 and 2 */
+ if ((lvds_tmp->lvds_idiv_set >= VDC5_LVDS_NDIV_NUM) || (lvds_tmp->lvds_odiv_set >= VDC5_LVDS_NDIV_NUM)) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ /* Internal parameter setting for LVDS PLL */
+ if (((uint32_t)lvds_tmp->lvdspll_tst & (uint32_t)~VDC5_CPARA_RANGE_0X0000003F) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* A channel in VDC5 whose data is to be output through the LVDS */
+ if (lvds_tmp->lvds_vdc_sel >= VDC5_CHANNEL_NUM) {
+ error = VDC5_ERR_PARAM_CHANNEL;
+ goto END;
+ }
+ if (param->panel_icksel != VDC5_PANEL_ICKSEL_LVDS_DIV7) {
+ /* When using the clock output from the LVDS PLL as the clock for the LVDS output interface,
+ both channel number should match. */
+ if (ch != lvds_tmp->lvds_vdc_sel) {
+ /* Channel mismatch error */
+ error = VDC5_ERR_PARAM_CONDITION;
+ goto END;
+ }
+ }
+ /* The frequency dividing value (NFD) for the feedback frequency */
+ if (((uint32_t)lvds_tmp->lvdspll_fd & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if ((uint32_t)lvds_tmp->lvdspll_fd < (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_56) {
+ if ((uint32_t)lvds_tmp->lvdspll_fd < (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_24) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ if (((uint32_t)lvds_tmp->lvdspll_fd >= (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_28) && ((uint32_t)lvds_tmp->lvdspll_fd <= (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_31)) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ if (((uint32_t)lvds_tmp->lvdspll_fd >= (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_37) && ((uint32_t)lvds_tmp->lvdspll_fd <= (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_39)) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ if (((uint32_t)lvds_tmp->lvdspll_fd == (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_46) ||
+ ((uint32_t)lvds_tmp->lvdspll_fd == (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_47) ||
+ ((uint32_t)lvds_tmp->lvdspll_fd == (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_55)) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ }
+ /* The frequency dividing value (NRD) for the input frequency */
+ if (((uint32_t)lvds_tmp->lvdspll_rd & (uint32_t)~VDC5_CPARA_RANGE_0X0000001F) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* The frequency dividing value (NOD) for the output frequency */
+ if (lvds_tmp->lvdspll_od >= VDC5_LVDS_PLL_NOD_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ }
+END:
+ return error;
+} /* End of function VDC5_InitializeCheckPrm() */
+
+/**************************************************************************//**
+ * @brief Checks on parameters in R_VDC5_Terminate
+ * @param[in] ch : Channel
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_TerminateCheckPrm (const vdc5_channel_t ch)
+{
+ vdc5_error_t error;
+
+ error = CheckChannel(ch);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+END:
+ return error;
+} /* End of function VDC5_TerminateCheckPrm() */
+
+/**************************************************************************//**
+ * @brief Checks on video input setup parameter
+ * @param[in] ch : Channel
+ * @param[in] param : Video input setup parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_VideoInputCheckPrm (const vdc5_channel_t ch, const vdc5_input_t * const param)
+{
+ vdc5_error_t error;
+ const vdc5_sync_delay_t * dly_tmp;
+ const vdc5_ext_in_sig_t * ext_sig_tmp;
+ vdc5_panel_clksel_t panel_clksel;
+ vdc5_resource_state_t rsrc_state;
+
+ error = CheckChannel(ch);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+
+ if (param == NULL) {
+ error = VDC5_ERR_PARAM_NULL;
+ goto END;
+ }
+
+ rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_PANEL_CLK);
+ if (rsrc_state != VDC5_RESOURCE_ST_INVALID) {
+ panel_clksel = VDC5_ShrdPrmGetPanelClkSel(ch);
+ if (param->inp_sel == VDC5_INPUT_SEL_VDEC) {
+ /* Video decoder output signals */
+ if (panel_clksel == VDC5_PANEL_ICKSEL_IMG_DV) {
+ /* Video image clock, DV_CLK */
+ error = VDC5_ERR_PARAM_CONDITION;
+ goto END;
+ }
+ } else {
+ /* Signals supplied via the external input pins */
+ if (panel_clksel == VDC5_PANEL_ICKSEL_IMG) {
+ /* Video image clock, VIDEO_X1 */
+ error = VDC5_ERR_PARAM_CONDITION;
+ goto END;
+ }
+ }
+ }
+
+ /* Vsync signal 1/2fH phase timing */
+ if (((uint32_t)param->inp_fh50 & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* Vsync signal 1/4fH phase timing */
+ if (((uint32_t)param->inp_fh25 & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+
+ /* Sync signal delay adjustment */
+ dly_tmp = param->dly;
+ if (dly_tmp != NULL) {
+ /* Number of lines for delaying Vsync signal and field differentiation signal */
+ if (((uint32_t)dly_tmp->inp_vs_dly_l & (uint32_t)~VDC5_CPARA_RANGE_0X00000007) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* Field differentiation signal delay amount */
+ if (((uint32_t)dly_tmp->inp_fld_dly & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if ((uint32_t)dly_tmp->inp_fld_dly > (uint32_t)VDC5_CPARA_INP_FLD_DLY_MAX) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ /* Vsync signal delay amount */
+ if (((uint32_t)dly_tmp->inp_vs_dly & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if ((uint32_t)dly_tmp->inp_vs_dly > (uint32_t)VDC5_CPARA_INP_VS_DLY_MAX) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ /* Hsync signal delay amount */
+ if (((uint32_t)dly_tmp->inp_hs_dly & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if ((uint32_t)dly_tmp->inp_hs_dly > (uint32_t)VDC5_CPARA_INP_HS_DLY_MAX) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ }
+
+ /* External input signal */
+ ext_sig_tmp = param->ext_sig;
+ if (ext_sig_tmp == NULL) {
+ if (param->inp_sel != VDC5_INPUT_SEL_VDEC) {
+ error = VDC5_ERR_PARAM_NULL;
+ goto END;
+ }
+ } else {
+ /* External input format select */
+ if (ext_sig_tmp->inp_format >= VDC5_EXTIN_FORMAT_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ /* Y/Cb/Y/Cr data string start timing to Hsync reference */
+ if (ext_sig_tmp->inp_h_pos >= VDC5_EXTIN_H_POS_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ if ((ext_sig_tmp->inp_h_pos == VDC5_EXTIN_H_POS_YCRYCB) || (ext_sig_tmp->inp_h_pos == VDC5_EXTIN_H_POS_CRYCBY)) {
+ if (ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_YCBCR422) {
+ error = VDC5_ERR_PARAM_CONDITION;
+ goto END;
+ }
+ }
+ }
+END:
+ return error;
+} /* End of function VDC5_VideoInputCheckPrm() */
+
+/**************************************************************************//**
+ * @brief Checks on sync control parameter
+ * @param[in] ch : Channel
+ * @param[in] param : Sync control parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_SyncControlCheckPrm (const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param)
+{
+ vdc5_error_t error;
+
+ error = CheckChannel(ch);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+
+ if (param == NULL) {
+ error = VDC5_ERR_PARAM_NULL;
+ goto END;
+ }
+
+ if (param->res_vs_sel != VDC5_OFF) {
+ /* Free-running Vsync period setting */
+ if (((uint32_t)param->res_fv & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ }
+ /* Hsync period setting */
+ if (((uint32_t)param->res_fh & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* Vsync signal delay control */
+ if (((uint32_t)param->res_vsdly & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+
+ /* Full-screen enable control */
+ error = CheckRect(¶m->res_f);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+END:
+ return error;
+} /* End of function VDC5_SyncControlCheckPrm() */
+
+/**************************************************************************//**
+ * @brief Checks on display output configuration parameter
+ * @param[in] ch : Channel
+ * @param[in] param : Display output configuration parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_DisplayOutputCheckPrm (const vdc5_channel_t ch, const vdc5_output_t * const param)
+{
+ vdc5_error_t error;
+ uint32_t tcon_sig_index;
+ static vdc5_error_t (* const tcon_function_tbl[VDC5_LCD_TCONSIG_NUM])(
+ const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing) = {
+ &CheckTcon_Vertical, /* STVA/VS */
+ &CheckTcon_Vertical, /* STVB/VE */
+ &CheckTcon_Horizontal, /* STH/HS */
+ &CheckTcon_Horizontal, /* STB/HE */
+ &CheckTcon_Horizontal, /* CPV/GCK */
+ &CheckTcon_HorizontalPol, /* POLA */
+ &CheckTcon_HorizontalPol, /* POLB */
+ &CheckTcon_DataEnable /* DE */
+ };
+
+ error = CheckChannel(ch);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+
+ if (param == NULL) {
+ error = VDC5_ERR_PARAM_NULL;
+ goto END;
+ }
+
+ /* 1/2fH timing */
+ if (((uint32_t)param->tcon_half & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* Offset Hsync signal timing */
+ if (((uint32_t)param->tcon_offset & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+
+ /* LCD TCON timing setting */
+ for (tcon_sig_index = 0; tcon_sig_index < VDC5_LCD_TCONSIG_NUM; tcon_sig_index++) {
+ if (param->outctrl[tcon_sig_index] != NULL) {
+ error = tcon_function_tbl[tcon_sig_index](param->outctrl[tcon_sig_index]);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+ }
+ }
+
+ /* LCD output format select */
+ if (param->out_format >= VDC5_LCD_OUTFORMAT_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ if (param->out_format == VDC5_LCD_OUTFORMAT_SERIAL_RGB) {
+ /* Clock frequency control */
+ if (param->out_frq_sel >= VDC5_LCD_SERIAL_CLKFRQ_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ if (param->out_frq_sel == VDC5_LCD_PARALLEL_CLKFRQ_1) {
+ error = VDC5_ERR_PARAM_CONDITION;
+ goto END;
+ }
+ /* Clock phase adjustment */
+ if (param->out_phase >= VDC5_LCD_SERIAL_CLKPHASE_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ if (param->out_frq_sel == VDC5_LCD_SERIAL_CLKFRQ_3) {
+ if (param->out_phase == VDC5_LCD_SERIAL_CLKPHASE_3) {
+ error = VDC5_ERR_PARAM_CONDITION;
+ goto END;
+ }
+ }
+ }
+ /* Background color in 24-bit RGB color format */
+ if ((param->bg_color & (uint32_t)~VDC5_CPARA_RANGE_0X00FFFFFF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+END:
+ return error;
+} /* End of function VDC5_DisplayOutputCheckPrm() */
+
+/**************************************************************************//**
+ * @brief Checks on interrupt callback setup parameter
+ * @param[in] ch : Channel
+ * @param[in] param : Interrupt callback setup parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_CallbackISRCheckPrm (const vdc5_channel_t ch, const vdc5_int_t * const param)
+{
+ vdc5_error_t error;
+
+ error = CheckChannel(ch);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+
+ if (param == NULL) {
+ error = VDC5_ERR_PARAM_NULL;
+ goto END;
+ }
+
+ /* VDC5 interrupt type */
+ if (param->type >= VDC5_INT_TYPE_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ /* Interrupt callback function pointer */
+ if (param->callback != 0) {
+ if ((param->type == VDC5_INT_TYPE_VLINE) ||
+ (param->type == VDC5_INT_TYPE_S0_WLINE) ||
+ (param->type == VDC5_INT_TYPE_S1_WLINE) ||
+ (param->type == VDC5_INT_TYPE_OIR_VLINE)) {
+ /* Line interrupt set */
+ if (((uint32_t)param->line_num & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ }
+ }
+END:
+ return error;
+} /* End of function VDC5_CallbackISRCheckPrm() */
+
+/**************************************************************************//**
+ * @brief Checks on data write control parameter
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @param[in] param : Data write control parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_WriteDataControlCheckPrm (
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_write_t * const param)
+{
+ vdc5_error_t error;
+ const vdc5_scalingdown_rot_t * scldw_rt_tmp;
+
+ error = CheckChannel(ch);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+ if ((layer_id != VDC5_LAYER_ID_0_WR) && (layer_id != VDC5_LAYER_ID_1_WR) && (layer_id != VDC5_LAYER_ID_OIR_WR)) {
+ error = VDC5_ERR_PARAM_LAYER_ID;
+ goto END;
+ }
+
+ if (param == NULL) {
+ error = VDC5_ERR_PARAM_NULL;
+ goto END;
+ }
+
+ /* Scaling-down and rotation parameter */
+ scldw_rt_tmp = ¶m->scalingdown_rot;
+ /* Image area to be captured */
+ error = CheckRect(&scldw_rt_tmp->res);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+ /* Number of valid lines in vertical direction output by scaling-down control block */
+ if (((uint32_t)scldw_rt_tmp->res_out_vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if (((uint32_t)scldw_rt_tmp->res_out_vw & (uint32_t)VDC5_MULTIPLE_4_MASK) != 0u) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ /* Number of valid horizontal pixels output by scaling-down control block */
+ if (((uint32_t)scldw_rt_tmp->res_out_hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if (((uint32_t)scldw_rt_tmp->res_out_hw & (uint32_t)VDC5_MULTIPLE_4_MASK) != 0u) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ /* Frame buffer writing mode for image processing */
+ if (scldw_rt_tmp->res_ds_wr_md >= VDC5_WR_MD_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+
+ /* Swap setting in frame buffer writing */
+ if (param->res_wrswa >= VDC5_WR_RD_WRSWA_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ /* Frame buffer video-signal writing format */
+ if (param->res_md >= VDC5_RES_MD_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ /* Writing rate */
+ if (param->res_fs_rate >= VDC5_RES_FS_RATE_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ /* Frame buffer base address */
+ if (param->base == NULL) {
+ error = VDC5_ERR_PARAM_NULL;
+ goto END;
+ }
+ /* Frame buffer line offset address [byte] */
+ if ((param->ln_off & (uint32_t)~VDC5_CPARA_RANGE_0X00007FFF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if (param->res_bst_md == VDC5_BST_MD_32BYTE) {
+ /* 32-byte transfer */
+ if ((param->ln_off & (uint32_t)VDC5_MULTIPLE_32_MASK) != 0u) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ } else {
+ /* 128-byte transfer */
+ if ((param->ln_off & (uint32_t)VDC5_MULTIPLE_128_MASK) != 0u) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ }
+ /* Number of frames of buffer to be written to (res_flm_num + 1) */
+ if ((param->flm_num & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* Frame buffer frame offset address [byte] */
+ if (param->flm_num != 0u) {
+ if ((param->flm_off & (uint32_t)~VDC5_CPARA_RANGE_0X007FFFFF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if (param->res_bst_md == VDC5_BST_MD_32BYTE) {
+ /* 32-byte transfer */
+ if ((param->flm_off & (uint32_t)VDC5_MULTIPLE_32_MASK) != 0u) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ } else {
+ /* 128-byte transfer */
+ if ((param->flm_off & (uint32_t)VDC5_MULTIPLE_128_MASK) != 0u) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ }
+ }
+END:
+ return error;
+} /* End of function VDC5_WriteDataControlCheckPrm() */
+
+/**************************************************************************//**
+ * @brief Checks on data write change parameter
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @param[in] param : Data write change parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ChangeWriteProcessCheckPrm (
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_write_chg_t * const param)
+{
+ vdc5_error_t error;
+ const vdc5_scalingdown_rot_t * scldw_rt_tmp;
+
+ error = CheckChannel(ch);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+ if ((layer_id != VDC5_LAYER_ID_0_WR) && (layer_id != VDC5_LAYER_ID_1_WR) && (layer_id != VDC5_LAYER_ID_OIR_WR)) {
+ error = VDC5_ERR_PARAM_LAYER_ID;
+ goto END;
+ }
+
+ if (param == NULL) {
+ error = VDC5_ERR_PARAM_NULL;
+ goto END;
+ }
+
+ /* Scaling-down and rotation parameter */
+ scldw_rt_tmp = ¶m->scalingdown_rot;
+ /* Image area to be captured */
+ error = CheckRect(&scldw_rt_tmp->res);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+ /* Number of valid lines in vertical direction output by scaling-down control block */
+ if (((uint32_t)scldw_rt_tmp->res_out_vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if (((uint32_t)scldw_rt_tmp->res_out_vw & (uint32_t)VDC5_MULTIPLE_4_MASK) != 0u) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ /* Number of valid horizontal pixels output by scaling-down control block */
+ if (((uint32_t)scldw_rt_tmp->res_out_hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if (((uint32_t)scldw_rt_tmp->res_out_hw & (uint32_t)VDC5_MULTIPLE_4_MASK) != 0u) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ /* Frame buffer writing mode */
+ if (scldw_rt_tmp->res_ds_wr_md >= VDC5_WR_MD_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+END:
+ return error;
+} /* End of function VDC5_ChangeWriteProcessCheckPrm() */
+
+/**************************************************************************//**
+ * @brief Checks on data read control parameter
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @param[in] graphics_id : Graphics type ID
+ * @param[in] param : Data read control parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ReadDataControlCheckPrm (
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_read_t * const param)
+{
+ vdc5_error_t error;
+ void * btm_base_tmp;
+ vdc5_resource_state_t rsrc_state;
+
+ error = CheckChannel(ch);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+ error = CheckGraphicsTypeLayerId(layer_id);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+
+ if (param == NULL) {
+ error = VDC5_ERR_PARAM_NULL;
+ goto END;
+ }
+
+ /* Frame buffer address setting signal */
+ if (param->gr_flm_sel >= VDC5_GR_FLM_SEL_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ btm_base_tmp = NULL;
+ rsrc_state = VDC5_RESOURCE_ST_INVALID;
+ switch (graphics_id) {
+ case VDC5_GR_TYPE_GR0:
+ btm_base_tmp = VDC5_ShrdPrmGetFrBuffBtm(ch, VDC5_SC_TYPE_SC0);
+ rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_0_WR);
+ break;
+ case VDC5_GR_TYPE_GR1:
+ if (param->gr_flm_sel == VDC5_GR_FLM_SEL_DISTORTION) {
+ /* IMR-LS2 is implemented in scaler 0 only. */
+ error = VDC5_ERR_PARAM_CONDITION;
+ goto END;
+ }
+ btm_base_tmp = VDC5_ShrdPrmGetFrBuffBtm(ch, VDC5_SC_TYPE_SC1);
+ rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_1_WR);
+ break;
+ /* The following two cases are intentionally combined. */
+ case VDC5_GR_TYPE_GR2:
+ case VDC5_GR_TYPE_GR3:
+ if (param->gr_flm_sel != VDC5_GR_FLM_SEL_FLM_NUM) {
+ error = VDC5_ERR_PARAM_CONDITION;
+ goto END;
+ }
+ break;
+ case VDC5_GR_TYPE_OIR:
+ if (param->gr_flm_sel == VDC5_GR_FLM_SEL_POINTER_BUFF) {
+ error = VDC5_ERR_PARAM_CONDITION;
+ goto END;
+ }
+ if ((ch != VDC5_CHANNEL_0) && (param->gr_flm_sel == VDC5_GR_FLM_SEL_DISTORTION)) {
+ /* IMR-LSD is implemented in channel 0 only. */
+ error = VDC5_ERR_PARAM_CONDITION;
+ goto END;
+ }
+ break;
+ default:
+ /* DO NOTHING */
+ break;
+ }
+ if ((btm_base_tmp != NULL) && (rsrc_state != VDC5_RESOURCE_ST_INVALID)) {
+ /* btm_base_tmp is valid only when rsrc_state is valid. */
+ if (param->gr_flm_sel == VDC5_GR_FLM_SEL_SCALE_DOWN) {
+ error = VDC5_ERR_PARAM_CONDITION;
+ goto END;
+ }
+ }
+ /* Frame buffer base address */
+ if (param->gr_base == NULL) {
+ if (param->gr_flm_sel != VDC5_GR_FLM_SEL_POINTER_BUFF) {
+ error = VDC5_ERR_PARAM_NULL;
+ goto END;
+ }
+ }
+ /* Frame buffer line offset address */
+ if ((param->gr_ln_off & (uint32_t)~VDC5_CPARA_RANGE_0X00007FFF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if (param->gr_bst_md == VDC5_BST_MD_32BYTE) {
+ /* 32-byte transfer */
+ if ((param->gr_ln_off & (uint32_t)VDC5_MULTIPLE_32_MASK) != 0u) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ } else {
+ /* 128-byte transfer */
+ if ((param->gr_ln_off & (uint32_t)VDC5_MULTIPLE_128_MASK) != 0u) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ }
+ if (param->width_read_fb != NULL) {
+ /* Number of lines in a frame */
+ if (((uint32_t)param->width_read_fb->in_vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if ((uint32_t)param->width_read_fb->in_vw == 0u) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ /* Width of the horizontal valid period */
+ if (((uint32_t)param->width_read_fb->in_hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if ((uint32_t)param->width_read_fb->in_hw < (uint32_t)VDC5_CPARA_RANGE_0X00000003) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ }
+ /* Format of the frame buffer read signal */
+ if (param->gr_format >= VDC5_GR_FORMAT_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ if ((param->gr_format == VDC5_GR_FORMAT_YCBCR422) || (param->gr_format == VDC5_GR_FORMAT_YCBCR444)) {
+ /* YCbCr422 and YCbCr444 are supported for the graphics 0 and 1. */
+ if ((graphics_id != VDC5_GR_TYPE_GR0) && (graphics_id != VDC5_GR_TYPE_GR1)) {
+ error = VDC5_ERR_PARAM_CONDITION;
+ goto END;
+ }
+ }
+ if (param->gr_format == VDC5_GR_FORMAT_YCBCR422) {
+ /* Swapping of data read from buffer in the YCbCr422 format */
+ if (param->gr_ycc_swap >= VDC5_GR_YCCSWAP_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ }
+ /* Swap setting in frame buffer reading */
+ if (param->gr_rdswa >= VDC5_WR_RD_WRSWA_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ /* Graphics display area */
+ error = CheckRect(¶m->gr_grc);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+END:
+ return error;
+} /* End of function VDC5_ReadDataControlCheckPrm() */
+
+/**************************************************************************//**
+ * @brief Checks on data read change parameter
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @param[in] param : Data read change parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ChangeReadProcessCheckPrm (
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_read_chg_t * const param)
+{
+ vdc5_error_t error;
+
+ error = CheckChannel(ch);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+ error = CheckGraphicsTypeLayerId(layer_id);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+
+ if (param == NULL) {
+ error = VDC5_ERR_PARAM_NULL;
+ goto END;
+ }
+ /* Width of the image read from frame buffer */
+ if (param->width_read_fb != NULL) {
+ /* Number of lines in a frame */
+ if (((uint32_t)param->width_read_fb->in_vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if ((uint32_t)param->width_read_fb->in_vw == 0u) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ /* Width of the horizontal valid period */
+ if (((uint32_t)param->width_read_fb->in_hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if ((uint32_t)param->width_read_fb->in_hw < (uint32_t)VDC5_CPARA_RANGE_0X00000003) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ }
+ /* Graphics display area */
+ if (param->gr_grc != NULL) {
+ error = CheckRect(param->gr_grc);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+ }
+ /* Graphics display mode */
+ if (param->gr_disp_sel != NULL) {
+ if ((*(param->gr_disp_sel) < VDC5_DISPSEL_IGNORED) || (*(param->gr_disp_sel) >= VDC5_DISPSEL_NUM)) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ }
+END:
+ return error;
+} /* End of function VDC5_ChangeReadProcessCheckPrm() */
+
+/**************************************************************************//**
+ * @brief Checks on data write/read start parameter
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @param[in] param : Data write/read start parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_StartProcessCheckPrm (
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_start_t * const param)
+{
+ vdc5_error_t error;
+ uint32_t graphics_types;
+ const vdc5_gr_disp_sel_t * gr_disp_sel_tmp;
+
+ error = CheckChannel(ch);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+ error = CheckLayerId(layer_id);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+
+ if (param == NULL) {
+ error = VDC5_ERR_PARAM_NULL;
+ goto END;
+ }
+
+ gr_disp_sel_tmp = param->gr_disp_sel;
+ if (gr_disp_sel_tmp == NULL) {
+ error = VDC5_OK;
+ goto END;
+ }
+ /* Graphics display mode */
+ if (layer_id == VDC5_LAYER_ID_ALL) {
+ for (graphics_types = 0; graphics_types < VDC5_GR_TYPE_NUM; graphics_types++) {
+ if ((gr_disp_sel_tmp[graphics_types] < VDC5_DISPSEL_IGNORED) ||
+ (gr_disp_sel_tmp[graphics_types] >= VDC5_DISPSEL_NUM)) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ }
+ } else {
+ if ((*gr_disp_sel_tmp < VDC5_DISPSEL_IGNORED) || (*gr_disp_sel_tmp >= VDC5_DISPSEL_NUM)) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ }
+END:
+ return error;
+} /* End of function VDC5_StartProcessCheckPrm() */
+
+/**************************************************************************//**
+ * @brief Checks on parameters in R_VDC5_StopProcess
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_StopProcessCheckPrm (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+ vdc5_error_t error;
+
+ error = CheckChannel(ch);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+ error = CheckLayerId(layer_id);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+END:
+ return error;
+} /* End of function VDC5_StopProcessCheckPrm() */
+
+/**************************************************************************//**
+ * @brief Checks on parameters in R_VDC5_ReleaseDataControl
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ReleaseDataControlCheckPrm (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+ vdc5_error_t error;
+
+ error = CheckChannel(ch);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+ error = CheckLayerId(layer_id);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+END:
+ return error;
+} /* End of function VDC5_ReleaseDataControlCheckPrm() */
+
+/**************************************************************************//**
+ * @brief Checks on noise reduction setup parameter
+ * @param[in] ch : Channel
+ * @param[in] param : Noise reduction setup parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_VideoNoiseReductCheckPrm (const vdc5_channel_t ch, const vdc5_noise_reduction_t * const param)
+{
+ vdc5_error_t error;
+ const vdc5_nr_param_t * nr_param;
+
+ error = CheckChannel(ch);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+
+ if (param == NULL) {
+ error = VDC5_OK;
+ goto END;
+ }
+
+ /* Y/G signal noise reduction parameter */
+ nr_param = ¶m->y;
+ /* TAP select */
+ if (nr_param->nr1d_tap >= VDC5_NR_TAPSEL_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ /* Maximum value of coring (absolute value) */
+ if ((nr_param->nr1d_th & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* Noise reduction gain adjustment */
+ if (nr_param->nr1d_gain >= VDC5_NR_GAIN_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+
+ /* Cb/B signal noise reduction parameter */
+ nr_param = ¶m->cb;
+ /* TAP select */
+ if (nr_param->nr1d_tap >= VDC5_NR_TAPSEL_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ /* Maximum value of coring (absolute value) */
+ if ((nr_param->nr1d_th & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* Noise reduction gain adjustment */
+ if (nr_param->nr1d_gain >= VDC5_NR_GAIN_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+
+ /* Cr/R signal noise reduction parameter */
+ nr_param = ¶m->cr;
+ /* TAP select */
+ if (nr_param->nr1d_tap >= VDC5_NR_TAPSEL_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ /* Maximum value of coring (absolute value) */
+ if ((nr_param->nr1d_th & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* Noise reduction gain adjustment */
+ if (nr_param->nr1d_gain >= VDC5_NR_GAIN_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+END:
+ return error;
+} /* End of function VDC5_VideoNoiseReductCheckPrm() */
+
+/**************************************************************************//**
+ * @brief Checks on color matrix setup parameter
+ * @param[in] ch : Channel
+ * @param[in] param : Color matrix setup parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ImageColorMatrixCheckPrm (const vdc5_channel_t ch, const vdc5_color_matrix_t * const param)
+{
+ vdc5_error_t error;
+ int32_t colormtx_index;
+
+ error = CheckChannel(ch);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+
+ if (param == NULL) {
+ error = VDC5_ERR_PARAM_NULL;
+ goto END;
+ }
+
+ /* Color matrix module */
+ if (param->module >= VDC5_COLORMTX_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ /* Operating mode */
+ if (param->mtx_mode >= VDC5_COLORMTX_MODE_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ if (param->module != VDC5_COLORMTX_IMGCNT) {
+ if ((param->mtx_mode == VDC5_COLORMTX_GBR_YCBCR) || (param->mtx_mode == VDC5_COLORMTX_YCBCR_YCBCR)) {
+ error = VDC5_ERR_PARAM_CONDITION;
+ goto END;
+ }
+ }
+ /* Offset (DC) adjustment of Y/G, B, and R signal */
+ for (colormtx_index = 0; colormtx_index < VDC5_COLORMTX_OFFST_NUM; colormtx_index++) {
+ if (((uint32_t)param->offset[colormtx_index] & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ }
+ /* GG, GB, GR, BG, BB, BR, RG, RB, and RR signal gain adjustment */
+ for (colormtx_index = 0; colormtx_index < VDC5_COLORMTX_GAIN_NUM; colormtx_index++) {
+ if (((uint32_t)param->gain[colormtx_index] & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ }
+END:
+ return error;
+} /* End of function VDC5_ImageColorMatrixCheckPrm() */
+
+/**************************************************************************//**
+ * @brief Checks on sharpness setup parameter and enhancer-enabled area setup parameter
+ * @param[in] ch : Channel
+ * @param[in] imgimprv_id : Image quality improver ID
+ * @param[in] sharp_param : Sharpness setup parameter
+ * @param[in] enh_area : Enhancer-enabled area setup parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ImageEnhancementCheckPrm (
+ const vdc5_channel_t ch,
+ const vdc5_imgimprv_id_t imgimprv_id,
+ const vdc5_enhance_sharp_t * const sharp_param,
+ const vdc5_period_rect_t * const enh_area)
+{
+ vdc5_error_t error;
+
+ error = CheckChannel(ch);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+
+ /* Image quality improver ID */
+ if (imgimprv_id >= VDC5_IMG_IMPRV_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+
+ /* Sharpness parameter */
+ if (sharp_param != NULL) {
+ /* Sharpness control parameter (H1, H2, and H3) */
+ if (((uint32_t)sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H1].shp_core & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if (((uint32_t)sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H2].shp_core & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if (((uint32_t)sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H3].shp_core & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ }
+ /* Enhancer area */
+ if (enh_area != NULL) {
+ /* Vertical start position */
+ if (((uint32_t)enh_area->vs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if ((uint32_t)enh_area->vs < (uint32_t)VDC5_CPARA_ENH_VS_LIMIT) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ /* Height (vertical width) */
+ if (((uint32_t)enh_area->vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* Horizontal start position */
+ if (((uint32_t)enh_area->hs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if ((uint32_t)enh_area->hs < (uint32_t)VDC5_CPARA_ENH_HS_LIMIT) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ /* Horizontal width */
+ if (((uint32_t)enh_area->hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ }
+END:
+ return error;
+} /* End of function VDC5_ImageEnhancementCheckPrm() */
+
+/**************************************************************************//**
+ * @brief Checks on black stretch setup parameter
+ * @param[in] ch : Channel
+ * @param[in] imgimprv_id : Image quality improver ID
+ * @param[in] param : Black stretch setup parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ImageBlackStretchCheckPrm (
+ const vdc5_channel_t ch,
+ const vdc5_imgimprv_id_t imgimprv_id,
+ const vdc5_black_t * const param)
+{
+ vdc5_error_t error;
+
+ error = CheckChannel(ch);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+
+ /* Image quality improver ID */
+ if (imgimprv_id >= VDC5_IMG_IMPRV_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+
+ if (param != NULL) {
+ /* Black stretch start point */
+ if (((uint32_t)param->bkstr_st & (uint32_t)~VDC5_CPARA_RANGE_0X0000000F) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* Black stretch depth */
+ if (((uint32_t)param->bkstr_d & (uint32_t)~VDC5_CPARA_RANGE_0X0000000F) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* Black stretch time constant (T1) */
+ if (((uint32_t)param->bkstr_t1 & (uint32_t)~VDC5_CPARA_RANGE_0X0000001F) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* Black stretch time constant (T2) */
+ if (((uint32_t)param->bkstr_t2 & (uint32_t)~VDC5_CPARA_RANGE_0X0000001F) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if ((uint32_t)param->bkstr_t2 == VDC5_BKSTR_T2_PROHIBITED) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+
+ }
+END:
+ return error;
+} /* End of function VDC5_ImageBlackStretchCheckPrm() */
+
+/**************************************************************************//**
+ * @brief Checks on alpha blending setup parameter
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @param[in] param : Alpha blending setup parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_AlphaBlendingCheckPrm (
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_alpha_blending_t * const param)
+{
+ vdc5_error_t error;
+
+ error = CheckChannel(ch);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+ if ((layer_id != VDC5_LAYER_ID_1_RD) && (layer_id != VDC5_LAYER_ID_2_RD) && (layer_id != VDC5_LAYER_ID_3_RD)) {
+ error = VDC5_ERR_PARAM_LAYER_ID;
+ goto END;
+ }
+
+ if (param == NULL) {
+ error = VDC5_ERR_PARAM_NULL;
+ goto END;
+ }
+END:
+ return error;
+} /* End of function VDC5_AlphaBlendingCheckPrm() */
+
+/**************************************************************************//**
+ * @brief Checks on setup parameter for alpha blending in a rectangular area
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @param[in] param : Setup parameter for alpha blending in a rectangular area
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_AlphaBlendingRectCheckPrm (
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_alpha_blending_rect_t * const param)
+{
+ vdc5_error_t error;
+
+ error = CheckChannel(ch);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+ if ((layer_id != VDC5_LAYER_ID_1_RD) &&
+ (layer_id != VDC5_LAYER_ID_2_RD) &&
+ (layer_id != VDC5_LAYER_ID_3_RD) &&
+ (layer_id != VDC5_LAYER_ID_VIN_RD)) {
+ error = VDC5_ERR_PARAM_LAYER_ID;
+ goto END;
+ }
+
+ if (param != NULL) {
+ /* Rectangular area subjected to alpha blending */
+ if (param->gr_arc != NULL) {
+ /* Vertical start position */
+ if (((uint32_t)param->gr_arc->vs_rel & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* Height (vertical width) */
+ if (((uint32_t)param->gr_arc->vw_rel & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* Horizontal start position */
+ if (((uint32_t)param->gr_arc->hs_rel & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* Horizontal width */
+ if (((uint32_t)param->gr_arc->hw_rel & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ }
+ /* Alpha Blending in a rectangular area */
+ if (param->alpha_rect != NULL) {
+ /* Frame rate for alpha blending in a rectangular area */
+ if ((param->alpha_rect->gr_arc_coef < (int16_t)VDC5_CPARA_GR_ARC_COEF_MIN) || (param->alpha_rect->gr_arc_coef > (int16_t)VDC5_CPARA_GR_ARC_COEF_MAX)) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ }
+ }
+END:
+ return error;
+} /* End of function VDC5_AlphaBlendingRectCheckPrm() */
+
+/**************************************************************************//**
+ * @brief Checks on chroma-key setup parameter
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @param[in] graphics_id : Graphics type ID
+ * @param[in] param : Chroma-key setup parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ChromakeyCheckPrm (
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_chromakey_t * const param)
+{
+ vdc5_error_t error;
+ vdc5_gr_format_t gr_format_tmp;
+
+ error = CheckChannel(ch);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+ error = CheckGraphicsTypeLayerId(layer_id);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+
+ if (param != NULL) {
+ gr_format_tmp = VDC5_ShrdPrmGetGraphicsFormat(ch, graphics_id);
+ switch (gr_format_tmp) {
+ /* The following four cases are intentionally combined,
+ since the four types of graphics format are represented as 16 bit unsigned integer. */
+ case VDC5_GR_FORMAT_RGB565:
+ case VDC5_GR_FORMAT_ARGB1555:
+ case VDC5_GR_FORMAT_ARGB4444:
+ case VDC5_GR_FORMAT_RGBA5551:
+ if (((param->ck_color & (uint32_t)~VDC5_CPARA_RANGE_0X0000FFFF) != 0u) ||
+ ((param->rep_color & (uint32_t)~VDC5_CPARA_RANGE_0X0000FFFF) != 0u)) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ }
+ break;
+ case VDC5_GR_FORMAT_RGB888:
+ if (((param->ck_color & (uint32_t)~VDC5_CPARA_RANGE_0X00FFFFFF) != 0u) ||
+ ((param->rep_color & (uint32_t)~VDC5_CPARA_RANGE_0X00FFFFFF) != 0u)) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ }
+ break;
+ case VDC5_GR_FORMAT_CLUT8:
+ if ((param->ck_color & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ }
+ break;
+ case VDC5_GR_FORMAT_CLUT4:
+ if ((param->ck_color & (uint32_t)~VDC5_CPARA_RANGE_0X0000000F) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ }
+ break;
+ case VDC5_GR_FORMAT_CLUT1:
+ if ((param->ck_color & (uint32_t)~VDC5_CPARA_RANGE_0X00000001) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ }
+ break;
+ default:
+ /* DO NOTHING */
+ break;
+ }
+ }
+END:
+ return error;
+} /* End of function VDC5_ChromakeyCheckPrm() */
+
+/**************************************************************************//**
+ * @brief Checks on CLUT setup parameter
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @param[in] graphics_id : Graphics type ID
+ * @param[in] param : CLUT setup parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_CLUTCheckPrm (
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_clut_t * const param)
+{
+ vdc5_error_t error;
+ vdc5_gr_format_t gr_format_tmp;
+
+ error = CheckChannel(ch);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+ error = CheckGraphicsTypeLayerId(layer_id);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+
+ if (param == NULL) {
+ error = VDC5_ERR_PARAM_NULL;
+ goto END;
+ }
+
+ /* The number of colors in CLUT */
+ if (param->color_num == 0u) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ gr_format_tmp = VDC5_ShrdPrmGetGraphicsFormat(ch, graphics_id);
+ if (gr_format_tmp == VDC5_GR_FORMAT_CLUT1) {
+ /* CLUT1 */
+ if (param->color_num > (uint32_t)VDC5_CPARA_CLUT1_NUM) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ } else if (gr_format_tmp == VDC5_GR_FORMAT_CLUT4) {
+ /* CLUT4 */
+ if (param->color_num > (uint32_t)VDC5_CPARA_CLUT4_NUM) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ } else {
+ /* CLUT8 */
+ if (param->color_num > (uint32_t)VDC5_CPARA_CLUT8_NUM) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ }
+
+ /* Address of the area storing the CLUT data (in ARGB8888 format) */
+ if (param->clut == NULL) {
+ error = VDC5_ERR_PARAM_NULL;
+ goto END;
+ }
+END:
+ return error;
+} /* End of function VDC5_CLUTCheckPrm() */
+
+/**************************************************************************//**
+ * @brief Checks on display calibration parameter
+ * @param[in] ch : Channel
+ * @param[in] param : Display calibration parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_DisplayCalibrationCheckPrm (const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param)
+{
+ vdc5_error_t error;
+ const vdc5_calibr_bright_t * bright_tmp;
+ const vdc5_calibr_dither_t * panel_dither_tmp;
+
+ error = CheckChannel(ch);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+
+ if (param == NULL) {
+ error = VDC5_ERR_PARAM_NULL;
+ goto END;
+ }
+
+ /* Brightness (DC) adjustment */
+ bright_tmp = param->bright;
+ if (bright_tmp != NULL) {
+ /* Brightness (DC) adjustment of G signal */
+ if (((uint32_t)bright_tmp->pbrt_g & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* Brightness (DC) adjustment of B signal */
+ if (((uint32_t)bright_tmp->pbrt_b & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* Brightness (DC) adjustment of R signal */
+ if (((uint32_t)bright_tmp->pbrt_r & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ }
+ /* Panel dithering */
+ panel_dither_tmp = param->panel_dither;
+ if (panel_dither_tmp != NULL) {
+ /* Panel dither operation mode */
+ if (panel_dither_tmp->pdth_sel >= VDC5_PDTH_MD_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ if (panel_dither_tmp->pdth_sel == VDC5_PDTH_MD_2X2) {
+ /* Pattern value (A)-(D) of 2x2 pattern dither */
+ if (((uint32_t)panel_dither_tmp->pdth_pa & (uint32_t)~VDC5_CPARA_RANGE_0X00000003) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if (((uint32_t)panel_dither_tmp->pdth_pb & (uint32_t)~VDC5_CPARA_RANGE_0X00000003) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if (((uint32_t)panel_dither_tmp->pdth_pc & (uint32_t)~VDC5_CPARA_RANGE_0X00000003) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if (((uint32_t)panel_dither_tmp->pdth_pd & (uint32_t)~VDC5_CPARA_RANGE_0X00000003) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ }
+ }
+END:
+ return error;
+} /* End of function VDC5_DisplayCalibrationCheckPrm() */
+
+/**************************************************************************//**
+ * @brief Checks on gamma correction setup parameter
+ * @param[in] ch : Channel
+ * @param[in] param : Gamma correction setup parameter
+ * @retval Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_GammaCorrectionCheckPrm (const vdc5_channel_t ch, const vdc5_gamma_correction_t * const param)
+{
+ vdc5_error_t error;
+
+ error = CheckChannel(ch);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+
+ if (param != NULL) {
+ /* Gain adjustment of area 0 to 31 of G signal */
+ error = CheckGammaCrct_GainAdjustment(param->gam_g_gain);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+ /* Gain adjustment of area 0 to 31 of B signal */
+ error = CheckGammaCrct_GainAdjustment(param->gam_b_gain);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+ /* Gain adjustment of area 0 to 31 of R signal */
+ error = CheckGammaCrct_GainAdjustment(param->gam_r_gain);
+ if (error != VDC5_OK) {
+ goto END;
+ }
+ }
+END:
+ return error;
+} /* End of function VDC5_GammaCorrectionCheckPrm() */
+
+/******************************************************************************
+Local Functions
+******************************************************************************/
+/**************************************************************************//**
+ * @brief Checks on VDC5 channel
+ * @param[in] ch : Channel
+ * @retval Error code
+******************************************************************************/
+static vdc5_error_t CheckChannel (const vdc5_channel_t ch)
+{
+ vdc5_error_t error;
+
+ error = VDC5_OK;
+
+ if (ch >= VDC5_CHANNEL_NUM) {
+ error = VDC5_ERR_PARAM_CHANNEL;
+ goto END;
+ }
+END:
+ return error;
+} /* End of function CheckChannel() */
+
+/**************************************************************************//**
+ * @brief Checks on layer ID
+ * @param[in] layer_id : Layer ID
+ * @retval Error code
+******************************************************************************/
+static vdc5_error_t CheckLayerId (const vdc5_layer_id_t layer_id)
+{
+ vdc5_error_t error;
+
+ error = VDC5_OK;
+
+ if ((layer_id < VDC5_LAYER_ID_ALL) || (layer_id >= VDC5_LAYER_ID_NUM)) {
+ error = VDC5_ERR_PARAM_LAYER_ID;
+ goto END;
+ }
+ if (layer_id == VDC5_LAYER_ID_VIN_RD) {
+ error = VDC5_ERR_PARAM_LAYER_ID;
+ goto END;
+ }
+END:
+ return error;
+} /* End of function CheckLayerId() */
+
+/**************************************************************************//**
+ * @brief Checks on layer ID related to graphics
+ * @param[in] layer_id : Layer ID
+ * @retval Error code
+******************************************************************************/
+static vdc5_error_t CheckGraphicsTypeLayerId (const vdc5_layer_id_t layer_id)
+{
+ vdc5_error_t error;
+
+ error = VDC5_OK;
+
+ if ((layer_id < VDC5_LAYER_ID_0_RD) || (layer_id > VDC5_LAYER_ID_OIR_RD)) {
+ error = VDC5_ERR_PARAM_LAYER_ID;
+ goto END;
+ }
+ if (layer_id == VDC5_LAYER_ID_VIN_RD) {
+ error = VDC5_ERR_PARAM_LAYER_ID;
+ goto END;
+ }
+END:
+ return error;
+} /* End of function CheckGraphicsTypeLayerId() */
+
+/**************************************************************************//**
+ * @brief Checks on horizontal/vertical timing of the VDC5 signals
+ * @param[in] rect : Horizontal/vertical timing of the VDC5 signals
+ * @retval Error code
+******************************************************************************/
+static vdc5_error_t CheckRect (const vdc5_period_rect_t * const rect)
+{
+ vdc5_error_t error;
+
+ error = VDC5_OK;
+
+ /* Vertical start position */
+ if (((uint32_t)rect->vs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if ((uint32_t)rect->vs < (uint32_t)VDC5_CPARA_VS_MIN) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ /* Height (vertical width) */
+ if (((uint32_t)rect->vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if (((uint32_t)rect->vs + (uint32_t)rect->vw) > (uint32_t)VDC5_CPARA_VS_VW_MAX) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+
+ /* Horizontal start position */
+ if (((uint32_t)rect->hs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if ((uint32_t)rect->hs < (uint32_t)VDC5_CPARA_HS_MIN) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+ /* Horizontal width */
+ if (((uint32_t)rect->hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ if (((uint32_t)rect->hs + (uint32_t)rect->hw) > (uint32_t)VDC5_CPARA_HS_HW_MAX) {
+ error = VDC5_ERR_PARAM_EXCEED_RANGE;
+ goto END;
+ }
+END:
+ return error;
+} /* End of function CheckRect() */
+
+/**************************************************************************//**
+ * @brief Checks on LCD TCON timing signal parameter for horizontal panel driver signal
+ * @param[in] lcd_tcon_timing : LCD TCON timing signal parameter
+ * @retval Error code
+******************************************************************************/
+static vdc5_error_t CheckTcon_Horizontal (const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing)
+{
+ vdc5_error_t error;
+
+ error = VDC5_OK;
+
+ /* Signal pulse start position */
+ if (((uint32_t)lcd_tcon_timing->tcon_hsvs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* Pulse width */
+ if (((uint32_t)lcd_tcon_timing->tcon_hwvw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* LCD TCON output pin select */
+ if ((lcd_tcon_timing->tcon_pin < VDC5_LCD_TCON_PIN_NON) || (lcd_tcon_timing->tcon_pin >= VDC5_LCD_TCON_PIN_NUM)) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+END:
+ return error;
+} /* End of function CheckTcon_Horizontal() */
+
+/**************************************************************************//**
+ * @brief Checks on LCD TCON timing signal parameter for horizontal panel driver signal (POLA/POLB)
+ * @param[in] lcd_tcon_timing : LCD TCON timing signal parameter
+ * @retval Error code
+******************************************************************************/
+static vdc5_error_t CheckTcon_HorizontalPol (const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing)
+{
+ vdc5_error_t error;
+
+ error = VDC5_OK;
+
+ /* Signal pulse start position */
+ if (((uint32_t)lcd_tcon_timing->tcon_hsvs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* Pulse width */
+ if (((uint32_t)lcd_tcon_timing->tcon_hwvw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* POLA/POLB signal generation mode select */
+ if (lcd_tcon_timing->tcon_md >= VDC5_LCD_TCON_POLMD_NUM) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+ /* LCD TCON output pin select */
+ if ((lcd_tcon_timing->tcon_pin < VDC5_LCD_TCON_PIN_NON) || (lcd_tcon_timing->tcon_pin >= VDC5_LCD_TCON_PIN_NUM)) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+END:
+ return error;
+} /* End of function CheckTcon_HorizontalPol() */
+
+/**************************************************************************//**
+ * @brief Checks on LCD TCON timing signal parameter for vertical panel driver signal
+ * @param[in] lcd_tcon_timing : LCD TCON timing signal parameter
+ * @retval Error code
+******************************************************************************/
+static vdc5_error_t CheckTcon_Vertical (const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing)
+{
+ vdc5_error_t error;
+
+ error = VDC5_OK;
+
+ /* Signal pulse start position */
+ if (((uint32_t)lcd_tcon_timing->tcon_hsvs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* Pulse width */
+ if (((uint32_t)lcd_tcon_timing->tcon_hwvw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ /* LCD TCON output pin select */
+ if ((lcd_tcon_timing->tcon_pin < VDC5_LCD_TCON_PIN_NON) || (lcd_tcon_timing->tcon_pin >= VDC5_LCD_TCON_PIN_NUM)) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+END:
+ return error;
+} /* End of function CheckTcon_Vertical() */
+
+/**************************************************************************//**
+ * @brief Checks on LCD TCON timing signal parameter for DE timing signal
+ * @param[in] lcd_tcon_timing : LCD TCON timing signal parameter
+ * @retval Error code
+******************************************************************************/
+static vdc5_error_t CheckTcon_DataEnable (const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing)
+{
+ vdc5_error_t error;
+
+ error = VDC5_OK;
+
+ /* LCD TCON output pin select */
+ if ((lcd_tcon_timing->tcon_pin < VDC5_LCD_TCON_PIN_NON) || (lcd_tcon_timing->tcon_pin >= VDC5_LCD_TCON_PIN_NUM)) {
+ error = VDC5_ERR_PARAM_UNDEFINED;
+ goto END;
+ }
+END:
+ return error;
+} /* End of function CheckTcon_DataEnable() */
+
+/**************************************************************************//**
+ * @brief Checks on gain adjustment of area 0 to 31 of G/B/R signal
+ * @param[in] gam_gain : Gain adjustment of area 0 to 31 of G/B/R signal
+ * @retval Error code
+******************************************************************************/
+static vdc5_error_t CheckGammaCrct_GainAdjustment (const uint16_t * gam_gain)
+{
+ uint32_t gain_index;
+ vdc5_error_t error;
+
+ error = VDC5_OK;
+
+ if (gam_gain != NULL) {
+ for (gain_index = 0; gain_index < VDC5_GAM_GAIN_ADJ_NUM; gain_index++) {
+ if (((uint32_t)*gam_gain & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+ error = VDC5_ERR_PARAM_BIT_WIDTH;
+ goto END;
+ }
+ gam_gain++;
+ }
+ }
+END:
+ return error;
+} /* End of function CheckGammaCrct_GainAdjustment() */
+
+#endif /* R_VDC5_CHECK_PARAMETERS */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/drivers/vdc5/src/r_vdc5_check_parameter.h Fri Jun 26 02:17:53 2015 +0000 @@ -0,0 +1,122 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/**************************************************************************//** +* @file r_vdc5_check_parameter.h +* @version 1.00 +* $Rev: 199 $ +* $Date:: 2014-05-23 16:33:52 +0900#$ +* @brief VDC5 driver parameter check definitions +******************************************************************************/ + +#ifndef R_VDC5_CHECK_PARAMETER_H +#define R_VDC5_CHECK_PARAMETER_H + +/****************************************************************************** +Includes <System Includes> , "Project Includes" +******************************************************************************/ +#include "r_vdc5.h" +#include "r_vdc5_user.h" + + +#ifdef R_VDC5_CHECK_PARAMETERS +/****************************************************************************** +Macro definitions +******************************************************************************/ + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Variable Externs +******************************************************************************/ + +/****************************************************************************** +Functions Prototypes +******************************************************************************/ +vdc5_error_t VDC5_InitializeCheckPrm(const vdc5_channel_t ch, const vdc5_init_t * const param); +vdc5_error_t VDC5_TerminateCheckPrm(const vdc5_channel_t ch); +vdc5_error_t VDC5_VideoInputCheckPrm(const vdc5_channel_t ch, const vdc5_input_t * const param); +vdc5_error_t VDC5_SyncControlCheckPrm(const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param); +vdc5_error_t VDC5_DisplayOutputCheckPrm(const vdc5_channel_t ch, const vdc5_output_t * const param); +vdc5_error_t VDC5_CallbackISRCheckPrm(const vdc5_channel_t ch, const vdc5_int_t * const param); +vdc5_error_t VDC5_WriteDataControlCheckPrm( + const vdc5_channel_t ch, + const vdc5_layer_id_t layer_id, + const vdc5_write_t * const param); +vdc5_error_t VDC5_ChangeWriteProcessCheckPrm( + const vdc5_channel_t ch, + const vdc5_layer_id_t layer_id, + const vdc5_write_chg_t * const param); +vdc5_error_t VDC5_ReadDataControlCheckPrm( + const vdc5_channel_t ch, + const vdc5_layer_id_t layer_id, + const vdc5_graphics_type_t graphics_id, + const vdc5_read_t * const param); +vdc5_error_t VDC5_ChangeReadProcessCheckPrm( + const vdc5_channel_t ch, + const vdc5_layer_id_t layer_id, + const vdc5_read_chg_t * const param); +vdc5_error_t VDC5_StartProcessCheckPrm( + const vdc5_channel_t ch, + const vdc5_layer_id_t layer_id, + const vdc5_start_t * const param); +vdc5_error_t VDC5_StopProcessCheckPrm(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id); +vdc5_error_t VDC5_ReleaseDataControlCheckPrm(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id); +vdc5_error_t VDC5_VideoNoiseReductCheckPrm(const vdc5_channel_t ch, const vdc5_noise_reduction_t * const param); +vdc5_error_t VDC5_ImageColorMatrixCheckPrm(const vdc5_channel_t ch, const vdc5_color_matrix_t * const param); +vdc5_error_t VDC5_ImageEnhancementCheckPrm( + const vdc5_channel_t ch, + const vdc5_imgimprv_id_t imgimprv_id, + const vdc5_enhance_sharp_t * const sharp_param, + const vdc5_period_rect_t * const enh_area); +vdc5_error_t VDC5_ImageBlackStretchCheckPrm( + const vdc5_channel_t ch, + const vdc5_imgimprv_id_t imgimprv_id, + const vdc5_black_t * const param); +vdc5_error_t VDC5_AlphaBlendingCheckPrm( + const vdc5_channel_t ch, + const vdc5_layer_id_t layer_id, + const vdc5_alpha_blending_t * const param); +vdc5_error_t VDC5_AlphaBlendingRectCheckPrm( + const vdc5_channel_t ch, + const vdc5_layer_id_t layer_id, + const vdc5_alpha_blending_rect_t * const param); +vdc5_error_t VDC5_ChromakeyCheckPrm( + const vdc5_channel_t ch, + const vdc5_layer_id_t layer_id, + const vdc5_graphics_type_t graphics_id, + const vdc5_chromakey_t * const param); +vdc5_error_t VDC5_CLUTCheckPrm( + const vdc5_channel_t ch, + const vdc5_layer_id_t layer_id, + const vdc5_graphics_type_t graphics_id, + const vdc5_clut_t * const param); +vdc5_error_t VDC5_DisplayCalibrationCheckPrm(const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param); +vdc5_error_t VDC5_GammaCorrectionCheckPrm(const vdc5_channel_t ch, const vdc5_gamma_correction_t * const param); + + +#endif /* R_VDC5_CHECK_PARAMETERS */ + +#endif /* R_VDC5_CHECK_PARAMETER_H */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/vdc5/src/r_vdc5_interrupt.c Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,1671 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file r_vdc5_interrupt.c
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief VDC5 driver interrupt related processing
+******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_vdc5.h"
+#include "r_vdc5_user.h"
+#include "r_vdc5_register.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define UNUSED_PARAM(param) (void)(param)
+
+#define VDC5_INT_BIT_S0_VI_VSYNC ((uint32_t)0x00000001u)
+#define VDC5_INT_BIT_S0_LO_VSYNC ((uint32_t)0x00000010u)
+#define VDC5_INT_BIT_S0_VSYNCERR ((uint32_t)0x00000100u)
+#define VDC5_INT_BIT_VLINE ((uint32_t)0x00001000u)
+#define VDC5_INT_BIT_S0_VFIELD ((uint32_t)0x00010000u)
+#define VDC5_INT_BIT_IV1_VBUFERR ((uint32_t)0x00100000u)
+#define VDC5_INT_BIT_IV3_VBUFERR ((uint32_t)0x01000000u)
+#define VDC5_INT_BIT_IV5_VBUFERR ((uint32_t)0x10000000u)
+#define VDC5_INT_BIT_IV6_VBUFERR ((uint32_t)0x00000001u)
+#define VDC5_INT_BIT_S0_WLINE ((uint32_t)0x00000010u)
+#define VDC5_INT_BIT_S1_VI_VSYNC ((uint32_t)0x00000100u)
+#define VDC5_INT_BIT_S1_LO_VSYNC ((uint32_t)0x00001000u)
+#define VDC5_INT_BIT_S1_VSYNCERR ((uint32_t)0x00010000u)
+#define VDC5_INT_BIT_S1_VFIELD ((uint32_t)0x00100000u)
+#define VDC5_INT_BIT_IV2_VBUFERR ((uint32_t)0x01000000u)
+#define VDC5_INT_BIT_IV4_VBUFERR ((uint32_t)0x10000000u)
+#define VDC5_INT_BIT_S1_WLINE ((uint32_t)0x00000001u)
+#define VDC5_INT_BIT_OIR_VI_VSYNC ((uint32_t)0x00000010u)
+#define VDC5_INT_BIT_OIR_LO_VSYNC ((uint32_t)0x00000100u)
+#define VDC5_INT_BIT_OIR_VLINE ((uint32_t)0x00001000u)
+#define VDC5_INT_BIT_OIR_VFIELD ((uint32_t)0x00010000u)
+#define VDC5_INT_BIT_IV7_VBUFERR ((uint32_t)0x00100000u)
+#define VDC5_INT_BIT_IV8_VBUFERR ((uint32_t)0x01000000u)
+
+#define VDC5_GR_UPDATE_P_VEN_BIT ((uint32_t)0x00000010u)
+#define VDC5_SCL0_UPDATE_VEN_A_BIT ((uint32_t)0x00000001u)
+
+/* Valid bit range */
+#define VDC5_INT_RANGE_0X000007FF (0x000007FFu)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void VDC5_Ch0_s0_vi_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s0_lo_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s0_vsyncerr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_vline_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s0_vfield_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv1_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv3_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv5_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv6_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s0_wline_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s1_vi_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s1_lo_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s1_vsyncerr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s1_vfield_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv2_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv4_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s1_wline_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_oir_vi_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_oir_lo_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_oir_vline_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_oir_vfield_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv7_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv8_vbuferr_ISR(const uint32_t int_sense);
+
+static void VDC5_Ch1_s0_vi_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s0_lo_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s0_vsyncerr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_vline_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s0_vfield_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv1_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv3_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv5_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv6_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s0_wline_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s1_vi_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s1_lo_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s1_vsyncerr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s1_vfield_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv2_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv4_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s1_wline_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_oir_vi_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_oir_lo_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_oir_vline_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_oir_vfield_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv7_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv8_vbuferr_ISR(const uint32_t int_sense);
+
+/*! List of the callback function pointers */
+static void (*vdc5_int_callback[VDC5_CHANNEL_NUM][VDC5_INT_TYPE_NUM])(vdc5_int_type_t int_type);
+
+
+/**************************************************************************//**
+ * @brief Interrupt service routine acquisition processing
+ *
+ * Description:<br>
+ * This function returns the function pointer to the specified interrupt service routine.
+ * @param[in] ch : Channel
+ * @param[in] type : VDC5 interrupt type
+ * @retval VDC5 Interrupt service routine
+ *****************************************************************************/
+void (*R_VDC5_GetISR (const vdc5_channel_t ch, const vdc5_int_type_t type))(const uint32_t int_sense)
+{
+ static void (* const isr_table[VDC5_CHANNEL_NUM][VDC5_INT_TYPE_NUM])(const uint32_t int_sense) = {
+ {
+ &VDC5_Ch0_s0_vi_vsync_ISR,
+ &VDC5_Ch0_s0_lo_vsync_ISR,
+ &VDC5_Ch0_s0_vsyncerr_ISR,
+ &VDC5_Ch0_vline_ISR,
+ &VDC5_Ch0_s0_vfield_ISR,
+ &VDC5_Ch0_iv1_vbuferr_ISR,
+ &VDC5_Ch0_iv3_vbuferr_ISR,
+ &VDC5_Ch0_iv5_vbuferr_ISR,
+ &VDC5_Ch0_iv6_vbuferr_ISR,
+ &VDC5_Ch0_s0_wline_ISR,
+ &VDC5_Ch0_s1_vi_vsync_ISR,
+ &VDC5_Ch0_s1_lo_vsync_ISR,
+ &VDC5_Ch0_s1_vsyncerr_ISR,
+ &VDC5_Ch0_s1_vfield_ISR,
+ &VDC5_Ch0_iv2_vbuferr_ISR,
+ &VDC5_Ch0_iv4_vbuferr_ISR,
+ &VDC5_Ch0_s1_wline_ISR,
+ &VDC5_Ch0_oir_vi_vsync_ISR,
+ &VDC5_Ch0_oir_lo_vsync_ISR,
+ &VDC5_Ch0_oir_vline_ISR,
+ &VDC5_Ch0_oir_vfield_ISR,
+ &VDC5_Ch0_iv7_vbuferr_ISR,
+ &VDC5_Ch0_iv8_vbuferr_ISR
+ },
+ {
+ &VDC5_Ch1_s0_vi_vsync_ISR,
+ &VDC5_Ch1_s0_lo_vsync_ISR,
+ &VDC5_Ch1_s0_vsyncerr_ISR,
+ &VDC5_Ch1_vline_ISR,
+ &VDC5_Ch1_s0_vfield_ISR,
+ &VDC5_Ch1_iv1_vbuferr_ISR,
+ &VDC5_Ch1_iv3_vbuferr_ISR,
+ &VDC5_Ch1_iv5_vbuferr_ISR,
+ &VDC5_Ch1_iv6_vbuferr_ISR,
+ &VDC5_Ch1_s0_wline_ISR,
+ &VDC5_Ch1_s1_vi_vsync_ISR,
+ &VDC5_Ch1_s1_lo_vsync_ISR,
+ &VDC5_Ch1_s1_vsyncerr_ISR,
+ &VDC5_Ch1_s1_vfield_ISR,
+ &VDC5_Ch1_iv2_vbuferr_ISR,
+ &VDC5_Ch1_iv4_vbuferr_ISR,
+ &VDC5_Ch1_s1_wline_ISR,
+ &VDC5_Ch1_oir_vi_vsync_ISR,
+ &VDC5_Ch1_oir_lo_vsync_ISR,
+ &VDC5_Ch1_oir_vline_ISR,
+ &VDC5_Ch1_oir_vfield_ISR,
+ &VDC5_Ch1_iv7_vbuferr_ISR,
+ &VDC5_Ch1_iv8_vbuferr_ISR
+ }
+ };
+ void (* isr_function)(const uint32_t int_sense);
+
+ isr_function = isr_table[ch][type];
+
+#ifdef R_VDC5_CHECK_PARAMETERS
+ /* Channel and interrupt type */
+ if ((ch >= VDC5_CHANNEL_NUM) || (type >= VDC5_INT_TYPE_NUM)) {
+ isr_function = 0;
+ }
+#endif /* R_VDC5_CHECK_PARAMETERS */
+
+ return isr_function;
+} /* End of function R_VDC5_GetISR() */
+
+/**************************************************************************//**
+ * @brief Disables all VDC5 interrupts
+ * @param[in] ch : Channel
+ * @retval None
+ *****************************************************************************/
+void VDC5_Int_Disable (const vdc5_channel_t ch)
+{
+ const vdc5_regaddr_system_ctrl_t * system_ctrl;
+ int32_t int_type;
+
+ system_ctrl = &vdc5_regaddr_system_ctrl[ch];
+
+ for (int_type = 0; int_type < VDC5_INT_TYPE_NUM; int_type++) {
+ vdc5_int_callback[ch][int_type] = 0;
+ }
+ /* Interrupt output off */
+ *(system_ctrl->syscnt_int4) = 0u;
+ *(system_ctrl->syscnt_int5) = 0u;
+ *(system_ctrl->syscnt_int6) = 0u;
+
+} /* End of function VDC5_Int_Disable() */
+
+/**************************************************************************//**
+ * @brief Enables/disables the specified VDC5 interrupt
+ * @param[in] ch : Channel
+ * @param[in] param : Interrupt callback setup parameter
+ * @retval None
+ *****************************************************************************/
+void VDC5_Int_SetInterrupt (const vdc5_channel_t ch, const vdc5_int_t * const param)
+{
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+ volatile uint32_t * linenum_reg;
+ volatile uint16_t * linenum16_reg;
+ volatile uint32_t * linenum_update_reg;
+ uint32_t mask_bit;
+ uint32_t reg_data;
+ static const uint32_t interrupt_bit_table[VDC5_INT_TYPE_NUM] = {
+ VDC5_INT_BIT_S0_VI_VSYNC,
+ VDC5_INT_BIT_S0_LO_VSYNC,
+ VDC5_INT_BIT_S0_VSYNCERR,
+ VDC5_INT_BIT_VLINE,
+ VDC5_INT_BIT_S0_VFIELD,
+ VDC5_INT_BIT_IV1_VBUFERR,
+ VDC5_INT_BIT_IV3_VBUFERR,
+ VDC5_INT_BIT_IV5_VBUFERR,
+ VDC5_INT_BIT_IV6_VBUFERR,
+ VDC5_INT_BIT_S0_WLINE,
+ VDC5_INT_BIT_S1_VI_VSYNC,
+ VDC5_INT_BIT_S1_LO_VSYNC,
+ VDC5_INT_BIT_S1_VSYNCERR,
+ VDC5_INT_BIT_S1_VFIELD,
+ VDC5_INT_BIT_IV2_VBUFERR,
+ VDC5_INT_BIT_IV4_VBUFERR,
+ VDC5_INT_BIT_S1_WLINE,
+ VDC5_INT_BIT_OIR_VI_VSYNC,
+ VDC5_INT_BIT_OIR_LO_VSYNC,
+ VDC5_INT_BIT_OIR_VLINE,
+ VDC5_INT_BIT_OIR_VFIELD,
+ VDC5_INT_BIT_IV7_VBUFERR,
+ VDC5_INT_BIT_IV8_VBUFERR
+ };
+
+ if (param->type < VDC5_INT_TYPE_IV6_VBUFERR) {
+ /* INT0: VDC5_INT_TYPE_S0_VI_VSYNC ~ INT7: VDC5_INT_TYPE_IV5_VBUFERR */
+ int_clhd_reg = vdc5_regaddr_system_ctrl[ch].syscnt_int1;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[ch].syscnt_int4;
+ } else if (param->type < VDC5_INT_TYPE_S1_WLINE) {
+ /* INT8: VDC5_INT_TYPE_IV6_VBUFERR ~ INT15: VDC5_INT_TYPE_IV4_VBUFERR */
+ int_clhd_reg = vdc5_regaddr_system_ctrl[ch].syscnt_int2;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[ch].syscnt_int5;
+ } else {
+ /* INT16: VDC5_INT_TYPE_S1_WLINE ~ INT22: VDC5_INT_TYPE_IV8_VBUFERR */
+ int_clhd_reg = vdc5_regaddr_system_ctrl[ch].syscnt_int3;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[ch].syscnt_int6;
+ }
+ mask_bit = interrupt_bit_table[param->type];
+
+ /* Interrupt callback function pointer */
+ vdc5_int_callback[ch][param->type] = param->callback;
+
+ if (param->callback != 0) {
+ /* ON */
+ if ((*int_onoff_reg & mask_bit) == 0u) {
+ /* OFF to ON */
+ *int_onoff_reg |= mask_bit;
+ reg_data = *int_onoff_reg;
+ *int_clhd_reg = reg_data;
+ }
+
+ if (param->type == VDC5_INT_TYPE_VLINE) {
+ /* Specified line signal for panel output in graphics 3 */
+ linenum_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR3].gr_clut;
+ linenum_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR3].gr_update;
+ *linenum_reg &= (uint32_t)~VDC5_INT_RANGE_0X000007FF;
+ *linenum_reg |= (uint32_t)param->line_num;
+ *linenum_update_reg |= VDC5_GR_UPDATE_P_VEN_BIT;
+ } else if (param->type == VDC5_INT_TYPE_S0_WLINE) {
+ /* Write specification line signal input to scaling-down control block in scaler 0 */
+ linenum16_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl0_int;
+ linenum_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl0_update;
+ *linenum16_reg = param->line_num;
+ *linenum_update_reg |= VDC5_SCL0_UPDATE_VEN_A_BIT;
+ } else if (param->type == VDC5_INT_TYPE_S1_WLINE) {
+ /* Write specification line signal input to scaling-down control block in scaler 1 */
+ linenum16_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl0_int;
+ linenum_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl0_update;
+ *linenum16_reg = param->line_num;
+ *linenum_update_reg |= VDC5_SCL0_UPDATE_VEN_A_BIT;
+ } else if (param->type == VDC5_INT_TYPE_OIR_VLINE) {
+ /* Specified line signal for panel output in output image generator */
+ linenum_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_OIR].gr_clut;
+ linenum_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_OIR].gr_update;
+ *linenum_reg &= (uint32_t)~VDC5_INT_RANGE_0X000007FF;
+ *linenum_reg |= (uint32_t)param->line_num;
+ *linenum_update_reg |= VDC5_GR_UPDATE_P_VEN_BIT;
+ } else {
+ /* Do nothing */
+ }
+ } else {
+ /* OFF */
+ *int_onoff_reg &= (uint32_t)~mask_bit;
+ reg_data = *int_onoff_reg;
+ *int_clhd_reg = reg_data;
+ }
+
+} /* End of function VDC5_Int_Disable() */
+
+/**************************************************************************//**
+ * @brief VDC5 S0_VI_VSYNC interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch0_s0_vi_vsync_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_S0_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VI_VSYNC) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VI_VSYNC;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VI_VSYNC] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VI_VSYNC](VDC5_INT_TYPE_S0_VI_VSYNC);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch0_s0_vi_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 S0_LO_VSYNC interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch0_s0_lo_vsync_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_S0_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_LO_VSYNC) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_LO_VSYNC;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_LO_VSYNC] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_LO_VSYNC](VDC5_INT_TYPE_S0_LO_VSYNC);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch0_s0_lo_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 S0_VSYNCERR interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch0_s0_vsyncerr_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_S0_VSYNCERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VSYNCERR) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VSYNCERR;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VSYNCERR] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VSYNCERR](VDC5_INT_TYPE_S0_VSYNCERR);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch0_s0_vsyncerr_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 VLINE interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch0_vline_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_VLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_VLINE) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_VLINE;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_VLINE] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_VLINE](VDC5_INT_TYPE_VLINE);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch0_vline_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 S0_VFIELD interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch0_s0_vfield_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_S0_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VFIELD) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VFIELD;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VFIELD] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VFIELD](VDC5_INT_TYPE_S0_VFIELD);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch0_s0_vfield_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 IV1_VBUFERR interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch0_iv1_vbuferr_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_IV1_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV1_VBUFERR) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV1_VBUFERR;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV1_VBUFERR] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV1_VBUFERR](VDC5_INT_TYPE_IV1_VBUFERR);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch0_iv1_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 IV3_VBUFERR interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch0_iv3_vbuferr_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_IV3_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV3_VBUFERR) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV3_VBUFERR;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV3_VBUFERR] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV3_VBUFERR](VDC5_INT_TYPE_IV3_VBUFERR);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch0_iv3_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 IV5_VBUFERR interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch0_iv5_vbuferr_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_IV5_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV5_VBUFERR) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV5_VBUFERR;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV5_VBUFERR] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV5_VBUFERR](VDC5_INT_TYPE_IV5_VBUFERR);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch0_iv5_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 IV6_VBUFERR interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch0_iv6_vbuferr_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_IV6_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV6_VBUFERR) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV6_VBUFERR;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV6_VBUFERR] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV6_VBUFERR](VDC5_INT_TYPE_IV6_VBUFERR);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch0_iv6_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 S0_WLINE interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch0_s0_wline_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_S0_WLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_WLINE) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_WLINE;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_WLINE] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_WLINE](VDC5_INT_TYPE_S0_WLINE);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch0_s0_wline_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 S1_VI_VSYNC interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch0_s1_vi_vsync_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_S1_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VI_VSYNC) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VI_VSYNC;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VI_VSYNC] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VI_VSYNC](VDC5_INT_TYPE_S1_VI_VSYNC);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch0_s1_vi_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 S1_LO_VSYNC interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch0_s1_lo_vsync_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_S1_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_LO_VSYNC) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_LO_VSYNC;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_LO_VSYNC] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_LO_VSYNC](VDC5_INT_TYPE_S1_LO_VSYNC);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch0_s1_lo_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 S1_VSYNCERR interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch0_s1_vsyncerr_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_S1_VSYNCERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VSYNCERR) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VSYNCERR;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VSYNCERR] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VSYNCERR](VDC5_INT_TYPE_S1_VSYNCERR);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch0_s1_vsyncerr_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 S1_VFIELD interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch0_s1_vfield_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_S1_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VFIELD) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VFIELD;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VFIELD] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VFIELD](VDC5_INT_TYPE_S1_VFIELD);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch0_s1_vfield_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 IV2_VBUFERR interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch0_iv2_vbuferr_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_IV2_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV2_VBUFERR) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV2_VBUFERR;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV2_VBUFERR] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV2_VBUFERR](VDC5_INT_TYPE_IV2_VBUFERR);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch0_iv2_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 IV4_VBUFERR interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch0_iv4_vbuferr_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_IV4_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV4_VBUFERR) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV4_VBUFERR;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV4_VBUFERR] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV4_VBUFERR](VDC5_INT_TYPE_IV4_VBUFERR);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch0_iv4_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 S1_WLINE interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch0_s1_wline_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_S1_WLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_WLINE) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_WLINE;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_WLINE] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_WLINE](VDC5_INT_TYPE_S1_WLINE);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch0_s1_wline_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 OIR_VI_VSYNC interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch0_oir_vi_vsync_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_OIR_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VI_VSYNC) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VI_VSYNC;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VI_VSYNC] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VI_VSYNC](VDC5_INT_TYPE_OIR_VI_VSYNC);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch0_oir_vi_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 OIR_LO_VSYNC interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch0_oir_lo_vsync_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_OIR_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_LO_VSYNC) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_LO_VSYNC;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_LO_VSYNC] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_LO_VSYNC](VDC5_INT_TYPE_OIR_LO_VSYNC);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch0_oir_lo_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 OIR_VLINE interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch0_oir_vline_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_OIR_VLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VLINE) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VLINE;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VLINE] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VLINE](VDC5_INT_TYPE_OIR_VLINE);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch0_oir_vline_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 OIR_VFIELD interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch0_oir_vfield_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_OIR_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VFIELD) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VFIELD;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VFIELD] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VFIELD](VDC5_INT_TYPE_OIR_VFIELD);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch0_oir_vfield_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 IV7_VBUFERR interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch0_iv7_vbuferr_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_IV7_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV7_VBUFERR) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV7_VBUFERR;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV7_VBUFERR] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV7_VBUFERR](VDC5_INT_TYPE_IV7_VBUFERR);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch0_iv7_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 IV8_VBUFERR interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch0_iv8_vbuferr_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_IV8_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV8_VBUFERR) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV8_VBUFERR;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV8_VBUFERR] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV8_VBUFERR](VDC5_INT_TYPE_IV8_VBUFERR);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch0_iv8_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 S0_VI_VSYNC interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch1_s0_vi_vsync_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_S0_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VI_VSYNC) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VI_VSYNC;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VI_VSYNC] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VI_VSYNC](VDC5_INT_TYPE_S0_VI_VSYNC);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch1_s0_vi_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 S0_LO_VSYNC interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch1_s0_lo_vsync_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_S0_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_LO_VSYNC) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_LO_VSYNC;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_LO_VSYNC] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_LO_VSYNC](VDC5_INT_TYPE_S0_LO_VSYNC);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch1_s0_lo_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 S0_VSYNCERR interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch1_s0_vsyncerr_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_S0_VSYNCERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VSYNCERR) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VSYNCERR;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VSYNCERR] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VSYNCERR](VDC5_INT_TYPE_S0_VSYNCERR);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch1_s0_vsyncerr_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 VLINE interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch1_vline_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_VLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_VLINE) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_VLINE;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_VLINE] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_VLINE](VDC5_INT_TYPE_VLINE);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch1_vline_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 S0_VFIELD interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch1_s0_vfield_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_S0_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VFIELD) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VFIELD;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VFIELD] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VFIELD](VDC5_INT_TYPE_S0_VFIELD);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch1_s0_vfield_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 IV1_VBUFERR interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch1_iv1_vbuferr_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_IV1_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV1_VBUFERR) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV1_VBUFERR;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV1_VBUFERR] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV1_VBUFERR](VDC5_INT_TYPE_IV1_VBUFERR);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch1_iv1_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 IV3_VBUFERR interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch1_iv3_vbuferr_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_IV3_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV3_VBUFERR) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV3_VBUFERR;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV3_VBUFERR] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV3_VBUFERR](VDC5_INT_TYPE_IV3_VBUFERR);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch1_iv3_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 IV5_VBUFERR interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch1_iv5_vbuferr_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_IV5_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV5_VBUFERR) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV5_VBUFERR;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV5_VBUFERR] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV5_VBUFERR](VDC5_INT_TYPE_IV5_VBUFERR);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch1_iv5_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 IV6_VBUFERR interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch1_iv6_vbuferr_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_IV6_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV6_VBUFERR) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV6_VBUFERR;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV6_VBUFERR] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV6_VBUFERR](VDC5_INT_TYPE_IV6_VBUFERR);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch1_iv6_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 S0_WLINE interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch1_s0_wline_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_S0_WLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_WLINE) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_WLINE;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_WLINE] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_WLINE](VDC5_INT_TYPE_S0_WLINE);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch1_s0_wline_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 S1_VI_VSYNC interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch1_s1_vi_vsync_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_S1_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VI_VSYNC) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VI_VSYNC;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VI_VSYNC] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VI_VSYNC](VDC5_INT_TYPE_S1_VI_VSYNC);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch1_s1_vi_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 S1_LO_VSYNC interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch1_s1_lo_vsync_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_S1_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_LO_VSYNC) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_LO_VSYNC;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_LO_VSYNC] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_LO_VSYNC](VDC5_INT_TYPE_S1_LO_VSYNC);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch1_s1_lo_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 S1_VSYNCERR interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch1_s1_vsyncerr_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_S1_VSYNCERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VSYNCERR) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VSYNCERR;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VSYNCERR] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VSYNCERR](VDC5_INT_TYPE_S1_VSYNCERR);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch1_s1_vsyncerr_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 S1_VFIELD interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch1_s1_vfield_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_S1_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VFIELD) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VFIELD;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VFIELD] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VFIELD](VDC5_INT_TYPE_S1_VFIELD);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch1_s1_vfield_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 IV2_VBUFERR interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch1_iv2_vbuferr_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_IV2_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV2_VBUFERR) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV2_VBUFERR;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV2_VBUFERR] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV2_VBUFERR](VDC5_INT_TYPE_IV2_VBUFERR);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch1_iv2_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 IV4_VBUFERR interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch1_iv4_vbuferr_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_IV4_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV4_VBUFERR) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV4_VBUFERR;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV4_VBUFERR] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV4_VBUFERR](VDC5_INT_TYPE_IV4_VBUFERR);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch1_iv4_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 S1_WLINE interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch1_s1_wline_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_S1_WLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_WLINE) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_WLINE;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_WLINE] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_WLINE](VDC5_INT_TYPE_S1_WLINE);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch1_s1_wline_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 OIR_VI_VSYNC interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch1_oir_vi_vsync_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_OIR_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VI_VSYNC) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VI_VSYNC;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VI_VSYNC] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VI_VSYNC](VDC5_INT_TYPE_OIR_VI_VSYNC);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch1_oir_vi_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 OIR_LO_VSYNC interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch1_oir_lo_vsync_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_OIR_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_LO_VSYNC) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_LO_VSYNC;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_LO_VSYNC] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_LO_VSYNC](VDC5_INT_TYPE_OIR_LO_VSYNC);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch1_oir_lo_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 OIR_VLINE interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch1_oir_vline_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_OIR_VLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VLINE) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VLINE;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VLINE] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VLINE](VDC5_INT_TYPE_OIR_VLINE);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch1_oir_vline_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 OIR_VFIELD interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch1_oir_vfield_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_OIR_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VFIELD) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VFIELD;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VFIELD] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VFIELD](VDC5_INT_TYPE_OIR_VFIELD);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch1_oir_vfield_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 IV7_VBUFERR interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch1_iv7_vbuferr_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_IV7_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV7_VBUFERR) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV7_VBUFERR;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV7_VBUFERR] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV7_VBUFERR](VDC5_INT_TYPE_IV7_VBUFERR);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch1_iv7_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief VDC5 IV8_VBUFERR interrupt service routine
+ * @param[in] int_sense
+ * @retval None
+ *****************************************************************************/
+static void VDC5_Ch1_iv8_vbuferr_ISR (const uint32_t int_sense)
+{
+ uint32_t IntState;
+ volatile uint32_t * int_clhd_reg;
+ volatile uint32_t * int_onoff_reg;
+
+ UNUSED_PARAM(int_sense);
+
+ int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
+ int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
+ IntState = *int_onoff_reg;
+
+ if (((IntState & VDC5_INT_BIT_IV8_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV8_VBUFERR) != 0u)) {
+ /* Clear */
+ *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV8_VBUFERR;
+
+ if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV8_VBUFERR] != 0) {
+ vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV8_VBUFERR](VDC5_INT_TYPE_IV8_VBUFERR);
+ }
+ /* Set */
+ *int_clhd_reg = IntState;
+ }
+} /* End of function VDC5_Ch1_iv8_vbuferr_ISR() */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/vdc5/src/r_vdc5_register.c Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,3784 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file r_vdc5_register.c
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief VDC5 driver register setup processing
+******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_vdc5.h"
+#include "r_vdc5_user.h"
+#include "r_vdc5_register.h"
+#include "r_vdc5_shared_param.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define INITIAL_SCALING_PHASE ((uint32_t)2048u)
+#define SCALING_RATIO_SAME_SIZE (4096u)
+/* Vsync signal delay control for OIR */
+#define OIR_VSYNC_DELAY ((uint32_t)1u)
+
+#define LVDS_LPHYACC_VALUE ((uint32_t)0x0001u)
+
+/* Panel clock frequency division ratio */
+#define VDC5_REG_CLKDIV_1_1 (1u)
+#define VDC5_REG_CLKDIV_1_2 (2u)
+#define VDC5_REG_CLKDIV_1_3 (3u)
+#define VDC5_REG_CLKDIV_1_4 (4u)
+#define VDC5_REG_CLKDIV_1_5 (5u)
+#define VDC5_REG_CLKDIV_1_6 (6u)
+#define VDC5_REG_CLKDIV_1_7 (7u)
+#define VDC5_REG_CLKDIV_1_8 (8u)
+#define VDC5_REG_CLKDIV_1_9 (9u)
+#define VDC5_REG_CLKDIV_1_12 (12u)
+#define VDC5_REG_CLKDIV_1_16 (16u)
+#define VDC5_REG_CLKDIV_1_24 (24u)
+#define VDC5_REG_CLKDIV_1_32 (32u)
+/* Panel clock select */
+#define VDC5_REG_ICKSEL_IMG (0x0000u)
+#define VDC5_REG_ICKSEL_IMG_DV (0x0000u)
+#define VDC5_REG_ICKSEL_EXT_0 (0x1000u)
+#define VDC5_REG_ICKSEL_EXT_1 (0x2000u)
+#define VDC5_REG_ICKSEL_PERI (0x3000u)
+#define VDC5_REG_ICKSEL_LVDS (0x0400u)
+#define VDC5_REG_ICKSEL_LVDS_DIV7 (0x0800u)
+/* Output pin edge select */
+#define VDC5_REG_TCON0_EDGE (0x0040u)
+#define VDC5_REG_TCON1_EDGE (0x0020u)
+#define VDC5_REG_TCON2_EDGE (0x0010u)
+#define VDC5_REG_TCON3_EDGE (0x0008u)
+#define VDC5_REG_TCON4_EDGE (0x0004u)
+#define VDC5_REG_TCON5_EDGE (0x0002u)
+#define VDC5_REG_TCON6_EDGE (0x0001u)
+/* Panel dither output format select */
+#define VDC5_REG_PATH_FORMAT_RGB888 (0x00000000u)
+#define VDC5_REG_PATH_FORMAT_RGB666 (0x00010000u)
+#define VDC5_REG_PATH_FORMAT_RGB565 (0x00020000u)
+#define VDC5_REG_PATH_FORMAT_NON (0x00000000u)
+/* Calculate scaling ratio use value */
+#define VDC5_REG_FLOAT_1_0 (1.0f)
+#define VDC5_REG_FLOAT_0_5 (0.5f)
+/* bits per pixel */
+#define VDC5_REG_BIT_PER_PIXEL_RGB565 (16u)
+#define VDC5_REG_BIT_PER_PIXEL_RGB888 (32u)
+#define VDC5_REG_BIT_PER_PIXEL_ARGB1555 (16u)
+#define VDC5_REG_BIT_PER_PIXEL_ARGB4444 (16u)
+#define VDC5_REG_BIT_PER_PIXEL_ARGB8888 (32u)
+#define VDC5_REG_BIT_PER_PIXEL_CLUT8 (8u)
+#define VDC5_REG_BIT_PER_PIXEL_CLUT4 (4u)
+#define VDC5_REG_BIT_PER_PIXEL_CLUT1 (1u)
+#define VDC5_REG_BIT_PER_PIXEL_YCBCR422 (32u)
+#define VDC5_REG_BIT_PER_PIXEL_YCBCR444 (32u)
+#define VDC5_REG_BIT_PER_PIXEL_RGBA5551 (16u)
+#define VDC5_REG_BIT_PER_PIXEL_RGBA8888 (32u)
+#define VDC5_REG_BIT_PER_PIXEL_VALUE_8 (8u)
+/* Convert the color data from 4 bits value into 8 bits value */
+#define VDC5_REG_EXTENSION_VALUE_17 (17u)
+/* Convert the color data from 5 bits value into 8 bits value */
+#define VDC5_REG_EXTENSION_VALUE_263 (263u)
+#define VDC5_REG_EXTENSION_VALUE_32 (32u)
+/* Convert the color data from 6 bits value into 8 bits value */
+#define VDC5_REG_EXTENSION_VALUE_259 (259u)
+#define VDC5_REG_EXTENSION_VALUE_64 (64u)
+/* Round off */
+#define VDC5_REG_ROUND_OFF_VALUE_1 (1u)
+#define VDC5_REG_ROUND_OFF_VALUE_2 (2u)
+/* Color mask data */
+#define VDC5_REG_ALPHA_8BIT (0xFF000000u)
+#define VDC5_REG_RGB_24BIT_MASK (0x00FFFFFFu)
+#define VDC5_REG_COLOR_8BIT_MASK (0x000000FFu)
+#define VDC5_REG_COLOR_6BIT_MASK (0x0000003Fu)
+#define VDC5_REG_COLOR_5BIT_MASK (0x0000001Fu)
+#define VDC5_REG_COLOR_4BIT_MASK (0x0000000Fu)
+#define VDC5_REG_ARGB8888_GB_MASK (0x00FFFF00u)
+
+/* RGB565 bits mask data */
+#define VDC5_REG_RGB565_R_MASK (0x0000F800u)
+#define VDC5_REG_RGB565_G_MASK (0x000007E0u)
+#define VDC5_REG_RGB565_B_MASK (0x0000001Fu)
+/* ARGB4444 bits mask data */
+#define VDC5_REG_ARGB4444_R_MASK (0x00000F00u)
+#define VDC5_REG_ARGB4444_G_MASK (0x000000F0u)
+#define VDC5_REG_ARGB4444_B_MASK (0x0000000Fu)
+/* ARGB1555 bits mask data */
+#define VDC5_REG_ARGB1555_R_MASK (0x00007C00u)
+#define VDC5_REG_ARGB1555_G_MASK (0x000003E0u)
+#define VDC5_REG_ARGB1555_B_MASK (0x0000001Fu)
+/* RGBA5551 bits mask data */
+#define VDC5_REG_RGBA5551_R_MASK (0x0000F800u)
+#define VDC5_REG_RGBA5551_G_MASK (0x000007C0u)
+#define VDC5_REG_RGBA5551_B_MASK (0x0000003Eu)
+
+/* bit pattern */
+#define VDC5_REG_BIT31 (0x80000000u)
+#define VDC5_REG_BIT29 (0x20000000u)
+#define VDC5_REG_BIT28 (0x10000000u)
+#define VDC5_REG_BIT24 (0x01000000u)
+#define VDC5_REG_BIT20 (0x00100000u)
+#define VDC5_REG_BIT16 (0x00010000u)
+#define VDC5_REG_BIT15 (0x00008000u)
+#define VDC5_REG_BIT14 (0x00004000u)
+#define VDC5_REG_BIT13 (0x00002000u)
+#define VDC5_REG_BIT12 (0x00001000u)
+#define VDC5_REG_BIT8 (0x00000100u)
+#define VDC5_REG_BIT4 (0x00000010u)
+#define VDC5_REG_BIT2 (0x00000004u)
+#define VDC5_REG_BIT1 (0x00000002u)
+#define VDC5_REG_BIT0 (0x00000001u)
+
+/* shift value */
+#define VDC5_REG_SHIFT_28 (28u)
+#define VDC5_REG_SHIFT_24 (24u)
+#define VDC5_REG_SHIFT_20 (20u)
+#define VDC5_REG_SHIFT_16 (16u)
+#define VDC5_REG_SHIFT_13 (13u)
+#define VDC5_REG_SHIFT_12 (12u)
+#define VDC5_REG_SHIFT_11 (11u)
+#define VDC5_REG_SHIFT_10 (10u)
+#define VDC5_REG_SHIFT_8 (8u)
+#define VDC5_REG_SHIFT_6 (6u)
+#define VDC5_REG_SHIFT_5 (5u)
+#define VDC5_REG_SHIFT_4 (4u)
+#define VDC5_REG_SHIFT_2 (2u)
+#define VDC5_REG_SHIFT_1 (1u)
+
+/* register set value */
+#define VDC5_REG_BIT_0XFFFF0000 (0xFFFF0000u) /* scaler_0->scl0_frc2 */
+/* scaler_1->scl0_frc2 */
+/* register mask value */
+#define VDC5_REG_MASK_0XF7FF1C3F (0xF7FF1C3Fu) /* mask img_synthesizer->gr_flm6 */
+#define VDC5_REG_MASK_0X0000D000 (0x0000D000u) /* mask img_synthesizer->gr_ab1 */
+#define VDC5_REG_MASK_0X01FF00FF (0x01FF00FFu) /* mask img_synthesizer->gr_ab6 */
+#define VDC5_REG_MASK_0X0000007F (0x0000007Fu) /* mask output_ctrl->out_clk_phase */
+#define VDC5_REG_MASK_0X11003313 (0x11003313u) /* mask output_ctrl->out_set */
+#define VDC5_REG_MASK_0X00030000 (0x00030000u) /* mask output_ctrl->out_pdtha */
+#define VDC5_REG_MASK_0X0007000D (0x0007000Du) /* mask scaler->scl1_wr1 */
+#define VDC5_REG_MASK_0X00000300 (0x00000300u) /* mask scaler->scl1_wr5 */
+#define VDC5_REG_MASK_0X0703FF02 (0x0703FF02u) /* mask regaddr_lvds->lclkselr */
+#define VDC5_REG_MASK_0X07FF1F30 (0x07FF1F30u) /* mask regaddr_lvds->lpllsetr */
+#define VDC5_REG_MASK_0X00010301 (0x00010301u) /* mask img_synthesizer->gr_flm1 */
+#define VDC5_REG_MASK_0X7FFF03FF (0x7FFF03FFu) /* mask img_synthesizer->gr_flm3 */
+#define VDC5_REG_MASK_0X0000E000 (0x0000E000u) /* mask img_synthesizer->gr_flm6 */
+#define VDC5_REG_MASK_0X00007F33 (0x00007F33u) /* mask input_ctrl->imgcnt_nr_cnt0 */
+#define VDC5_REG_MASK_0X00FF0000 (0x00FF0000u) /* mask img_synthesizer->gr_ab7 */
+#define VDC5_REG_MASK_0X00300000 (0x00300000u) /* mask output_ctrl->out_pdtha */
+#define VDC5_REG_MASK_0X00003333 (0x00003333u) /* mask output_ctrl->out_pdtha */
+#define VDC5_REG_MASK_0X00007111 (0x00007111u) /* mask input_ctrl->inp_sel_cnt */
+#define VDC5_REG_MASK_0X11110113 (0x11110113u) /* mask input_ctrl->inp_ext_sync_cnt */
+#define VDC5_REG_MASK_0X000007FF (0x000007FFu) /* mask img_synthesizer->gr_flm5 */
+#define VDC5_REG_MASK_0X0000FFFF (0x0000FFFFu) /* mask scaler->scl0_ds4 */
+/* caler->scl0_us5 */
+#define VDC5_REG_MASK_0X00000011 (0x00000011u) /* mask scaler->scl0_ds1 */
+/* scaler->scl0_us1 */
+#define VDC5_REG_MASK_0X00000070 (0x00000070u) /* mask scaler->scl1_wr1 */
+#define VDC5_REG_MASK_0X00000080 (0x00000080u) /* mask scaler->scl1_wr1 */
+#define VDC5_REG_MASK_0X00003110 (0x00003110u) /* mask output_ctrl->tcon_tim_pola2 */
+/* output_ctrl->tcon_tim_polb2 */
+#define VDC5_REG_MASK_0X000000FF (0x000000FFu) /* mask scaler_0->scl0_frc5 */
+/* scaler_1->scl0_frc5 */
+#define VDC5_REG_MASK_0X0000003F (0x0000003Fu) /* mask img_synthesizer->gr_flm6 */
+/* img_qlty_imp->adj_enh_shp1 */
+#define VDC5_REG_MASK_0XFF000000 (0xFF000000u) /* mask img_synthesizer->gr_ab10 */
+/* img_synthesizer->gr_ab11 */
+#define VDC5_REG_MASK_0X00000110 (0x00000110u) /* mask output_ctrl->tcon_tim_sth2 */
+/* output_ctrl->tcon_tim_stb2 */
+/* output_ctrl->tcon_tim_cpv2 */
+#define VDC5_REG_MASK_0X00000007 (0x00000007u) /* mask *(output_pin_regaddr[tcon_pin]) */
+/* img_synthesizer->gr_flm2 */
+/* img_synthesizer->gr_flm2 */
+#define VDC5_REG_MASK_0X07FF0000 (0x07FF0000u) /* mask scaler_0->scl0_frc4 */
+/* scaler_1->scl0_frc4 */
+/* img_synthesizer->gr_flm5 */
+/* img_synthesizer->gr_flm6 */
+#define VDC5_REG_MASK_0X0FFF0FFF (0x0FFF0FFFu) /* mask */
+/* scaler->scl0_ds5, scaler->scl0_us6 */
+/* scaler->scl0_ds5, scaler->scl0_us6 */
+/* scaler->scl0_ds5, scaler->scl0_us6 */
+/* scaler->scl0_ds5, scaler->scl0_us6 */
+/* scaler->scl0_ds5, scaler->scl0_us6 */
+#define VDC5_REG_MASK_0X00000003 (0x00000003u) /* mask img_synthesizer->gr_ab1 */
+/* regaddr_lvds->lphyacc */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void SetVideoExternalInput(
+ const vdc5_ext_in_sig_t * const ext_sig_tmp,
+ const vdc5_regaddr_input_ctrl_t * const input_ctrl);
+static void SetInitialConnection(const vdc5_channel_t ch);
+static void SetGrapicsBackgroundColor(const vdc5_channel_t ch);
+static void SetScalerBackgroundColor(
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_color_space_t color_space);
+static void SetLcdTcon_STVA_VS(
+ const vdc5_lcd_tcon_timing_t * const lcd_tcon,
+ const vdc5_regaddr_output_ctrl_t * const output_ctrl);
+static void SetLcdTcon_STVB_VE(
+ const vdc5_lcd_tcon_timing_t * const lcd_tcon,
+ const vdc5_regaddr_output_ctrl_t * const output_ctrl);
+static void SetLcdTcon_STH_HS(
+ const vdc5_lcd_tcon_timing_t * const lcd_tcon,
+ const vdc5_regaddr_output_ctrl_t * const output_ctrl);
+static void SetLcdTcon_STB_HE(
+ const vdc5_lcd_tcon_timing_t * const lcd_tcon,
+ const vdc5_regaddr_output_ctrl_t * const output_ctrl);
+static void SetLcdTcon_CPV_GCK(
+ const vdc5_lcd_tcon_timing_t * const lcd_tcon,
+ const vdc5_regaddr_output_ctrl_t * const output_ctrl);
+static void SetLcdTcon_POLA(
+ const vdc5_lcd_tcon_timing_t * const lcd_tcon,
+ const vdc5_regaddr_output_ctrl_t * const output_ctrl);
+static void SetLcdTcon_POLB(
+ const vdc5_lcd_tcon_timing_t * const lcd_tcon,
+ const vdc5_regaddr_output_ctrl_t * const output_ctrl);
+static void SetLcdTcon_DE(
+ const vdc5_lcd_tcon_timing_t * const lcd_tcon,
+ const vdc5_regaddr_output_ctrl_t * const output_ctrl);
+static void SetScalingDown(
+ const vdc5_scalingdown_rot_t * const scldw_rot,
+ const vdc5_res_inter_t res_inter,
+ const vdc5_regaddr_scaler_t * const scaler);
+static void SetScalingUp(
+ const vdc5_width_read_fb_t * const w_read_fb,
+ const vdc5_period_rect_t * const gr_grc,
+ const vdc5_onoff_t adj_sel,
+ const vdc5_onoff_t ip_conversion,
+ const vdc5_wr_md_t res_ds_wr_md,
+ const vdc5_gr_ln_off_dir_t ln_off_dir,
+ const vdc5_regaddr_scaler_t * const scaler);
+static uint32_t CalcScalingRatio(
+ const uint32_t before_scl,
+ const uint32_t after_scl,
+ const vdc5_onoff_t adj_sel,
+ const vdc5_onoff_t round_up);
+static void SetInputCntrlColorMtx(const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id);
+static vdc5_onoff_t ConfirmGraphicsEnlargement(
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_gr_flm_sel_t gr_flm_sel,
+ const vdc5_width_read_fb_t * const w_read_fb,
+ const vdc5_period_rect_t * const gr_grc);
+static void SetScalerGraphics(
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_width_read_fb_t * const w_read_fb,
+ const vdc5_period_rect_t * const gr_grc,
+ const vdc5_gr_flm_sel_t gr_flm_sel,
+ const vdc5_onoff_t gr_enlarge);
+static uint32_t DisplayStartPixelSetting(const uint32_t gr_base, const vdc5_gr_format_t gr_format);
+static vdc5_onoff_t SetCascade(
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_gr_flm_sel_t gr_flm_sel,
+ const vdc5_onoff_t gr_enlarge);
+static void SetupGraphicsVIN(
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_gr_flm_sel_t gr_flm_sel,
+ const vdc5_onoff_t gr_enlarge);
+static void ChangeGraphicsVIN(
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_gr_flm_sel_t gr_flm_sel,
+ const vdc5_onoff_t gr_enlarge);
+static void SetImgQaImproverColorMtx(
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_color_space_t color_space);
+
+static void SetRwProcAbility_Write_0(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRwProcAbility_Write_1(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRwProcAbility_Write_OIR(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRwProcAbility_Read_0(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRwProcAbility_Read_1(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRwProcAbility_Read_2(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRwProcAbility_Read_3(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRwProcAbility_Read_OIR(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRegUpdateRwEnable(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+
+static void SetGraphicsDisplayMode(
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_gr_disp_sel_t * const gr_disp_sel);
+static void SetColorMatrix(
+ const vdc5_colormtx_mode_t mtx_mode,
+ const uint16_t * const offset,
+ const uint16_t * const gain,
+ const vdc5_regaddr_color_matrix_t * const color_matrix);
+static void SetImageEnhancementSharpness(
+ const vdc5_onoff_t shp_h_on,
+ const vdc5_enhance_sharp_t * const sharp_param,
+ const vdc5_regaddr_img_qlty_imp_t * const img_qlty_imp);
+static void SetImageEnhancementLti(
+ const vdc5_onoff_t lti_h_on,
+ const vdc5_enhance_lti_t * const lti_param,
+ const vdc5_regaddr_img_qlty_imp_t * const img_qlty_imp);
+static void SetAlphaRectArea(
+ const vdc5_pd_disp_rect_t * const pd_disp_rect,
+ const vdc5_regaddr_img_synthesizer_t * const img_synthesizer);
+static void SetUndSel(const vdc5_channel_t ch, const vdc5_onoff_t und_sel);
+static uint32_t ColorConversion(const vdc5_gr_format_t gr_format, const uint32_t input_color);
+static uint32_t ColorConversionFrom4to8(const uint32_t color_value);
+static uint32_t ColorConversionFrom5to8(const uint32_t color_value);
+static uint32_t ColorConversionFrom6to8(const uint32_t color_value);
+static uint32_t ColorConversionIntoAgbr(const uint32_t color_value);
+static void Set_Clut(const vdc5_clut_t * const param, volatile uint32_t * regaddr_clut);
+static void Set_StartThreshold_Gamma(const uint8_t * gam_th, volatile uint32_t * const * const gam_area);
+static void Set_GainAdjustment_Gamma(const uint16_t * gam_gain, volatile uint32_t * const * const gam_lut);
+static void Wait_200_usec(void);
+
+/*! Color matrix offset (DC) adjustment (YG, B, and R) */
+static const uint16_t colormtx_offset_adj[VDC5_COLORMTX_OFFST_NUM] = {
+ (uint16_t)VDC5_COLORCONV_DC_OFFSET, (uint16_t)VDC5_COLORCONV_DC_OFFSET, (uint16_t)VDC5_COLORCONV_DC_OFFSET
+};
+/*! Color matrix signal gain adjustment (GG, GB, GR, BG, BB, BR, RG, RB, and RR) */
+static const uint16_t colormtx_gain_adj[VDC5_COLORMTX_MODE_NUM][VDC5_COLORMTX_GAIN_NUM] = {
+ { /* GBR to GBR */
+ (uint16_t)VDC5_COLORCONV_1TIMES_GAIN, 0, 0,
+ 0, (uint16_t)VDC5_COLORCONV_1TIMES_GAIN, 0,
+ 0, 0, (uint16_t)VDC5_COLORCONV_1TIMES_GAIN
+ },
+ { /* GBR to YCbCr */
+ (uint16_t)VDC5_COLORCONV_Y_G, (uint16_t)VDC5_COLORCONV_Y_B, (uint16_t)VDC5_COLORCONV_Y_R,
+ (uint16_t)VDC5_COLORCONV_CB_G, (uint16_t)VDC5_COLORCONV_CB_B, (uint16_t)VDC5_COLORCONV_CB_R,
+ (uint16_t)VDC5_COLORCONV_CR_G, (uint16_t)VDC5_COLORCONV_CR_B, (uint16_t)VDC5_COLORCONV_CR_R
+ },
+ { /* YCbCr to GBR */
+ (uint16_t)VDC5_COLORCONV_G_Y, (uint16_t)VDC5_COLORCONV_G_CB, (uint16_t)VDC5_COLORCONV_G_CR,
+ (uint16_t)VDC5_COLORCONV_B_Y, (uint16_t)VDC5_COLORCONV_B_CB, (uint16_t)VDC5_COLORCONV_B_CR,
+ (uint16_t)VDC5_COLORCONV_R_Y, (uint16_t)VDC5_COLORCONV_R_CB, (uint16_t)VDC5_COLORCONV_R_CR
+ },
+ { /* YCbCr to YCbCr */
+ (uint16_t)VDC5_COLORCONV_1TIMES_GAIN, 0, 0,
+ 0, (uint16_t)VDC5_COLORCONV_1TIMES_GAIN, 0,
+ 0, 0, (uint16_t)VDC5_COLORCONV_1TIMES_GAIN
+ }
+};
+
+static void (* const rw_proc_function_tbl[VDC5_LAYER_ID_NUM])(const vdc5_channel_t ch, const vdc5_onoff_t ability) = {
+ &SetRwProcAbility_Write_0, /* Write scaler 0 */
+ &SetRwProcAbility_Write_1, /* Write scaler 1 */
+ &SetRwProcAbility_Write_OIR, /* Write OIR */
+ &SetRwProcAbility_Read_0, /* Read graphics 0 */
+ &SetRwProcAbility_Read_1, /* Read graphics 1 */
+ &SetRwProcAbility_Read_2, /* Read graphics 2 */
+ &SetRwProcAbility_Read_3, /* Read graphics 3 */
+ 0, /* Read VIN */
+ &SetRwProcAbility_Read_OIR /* Read OIR */
+};
+
+
+/**************************************************************************//**
+ * @brief Sets registers for initialization
+ * @param[in] ch : Channel
+ * @param[in] param : Initialization parameter
+ * @retval None
+ *****************************************************************************/
+void VDC5_Initialize (const vdc5_channel_t ch, const vdc5_init_t * const param)
+{
+ const vdc5_lvds_t * lvds_tmp;
+ const vdc5_regaddr_lvds_t * regaddr_lvds;
+ volatile uint32_t counter;
+ uint16_t syscnt_panel_clk_tmp;
+ volatile uint16_t * syscnt_panel_clk_reg;
+ volatile uint32_t * inp_sel_cnt_reg;
+ static const uint16_t panel_dcdr_tbl[VDC5_PANEL_CLKDIV_NUM] = {
+ /* Panel clock frequency division ratio */
+ (uint16_t)VDC5_REG_CLKDIV_1_1, (uint16_t)VDC5_REG_CLKDIV_1_2, (uint16_t)VDC5_REG_CLKDIV_1_3, (uint16_t)VDC5_REG_CLKDIV_1_4,
+ (uint16_t)VDC5_REG_CLKDIV_1_5, (uint16_t)VDC5_REG_CLKDIV_1_6, (uint16_t)VDC5_REG_CLKDIV_1_7, (uint16_t)VDC5_REG_CLKDIV_1_8,
+ (uint16_t)VDC5_REG_CLKDIV_1_9, (uint16_t)VDC5_REG_CLKDIV_1_12, (uint16_t)VDC5_REG_CLKDIV_1_16, (uint16_t)VDC5_REG_CLKDIV_1_24,
+ (uint16_t)VDC5_REG_CLKDIV_1_32
+ };
+ static const uint16_t panel_icksel_tbl[VDC5_PANEL_ICKSEL_NUM] = {
+ /* Panel clock select */
+ (uint16_t)VDC5_REG_ICKSEL_IMG, (uint16_t)VDC5_REG_ICKSEL_IMG_DV, (uint16_t)VDC5_REG_ICKSEL_EXT_0, (uint16_t)VDC5_REG_ICKSEL_EXT_1,
+ (uint16_t)VDC5_REG_ICKSEL_PERI, (uint16_t)VDC5_REG_ICKSEL_LVDS, (uint16_t)VDC5_REG_ICKSEL_LVDS_DIV7
+ };
+
+ syscnt_panel_clk_reg = vdc5_regaddr_system_ctrl[ch].syscnt_panel_clk;
+ /* Disable */
+ syscnt_panel_clk_tmp = (uint16_t)((uint32_t)*syscnt_panel_clk_reg & (~VDC5_REG_BIT8));
+ *syscnt_panel_clk_reg = syscnt_panel_clk_tmp;
+
+ /* LVDS */
+ lvds_tmp = param->lvds;
+ if (lvds_tmp != NULL) {
+ regaddr_lvds = &vdc5_regaddr_lvds;
+
+ /* Output from the LVDS PLL is disabled. */
+ *(regaddr_lvds->lclkselr) &= (uint32_t)~VDC5_REG_BIT4;
+ /* Controls power-down for the LVDS PLL: Power-down state */
+ *(regaddr_lvds->lpllsetr) |= (uint32_t)VDC5_REG_BIT0;
+ for (counter = 0; counter < (uint32_t)VDC5_LVDS_PLL_WAIT_CYCLE; counter++) {
+ /* This is a delay (1 usec) while waiting for PLL PD to settle. */
+ }
+
+ /* LPHYACC */
+ *(regaddr_lvds->lphyacc) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+ *(regaddr_lvds->lphyacc) |= LVDS_LPHYACC_VALUE;
+ /* LCLKSELR: LVDS clock select register */
+ *(regaddr_lvds->lclkselr) &= (uint32_t)~VDC5_REG_MASK_0X0703FF02;
+ /* The clock input to frequency divider 1 */
+ *(regaddr_lvds->lclkselr) |= (uint32_t)lvds_tmp->lvds_in_clk_sel << VDC5_REG_SHIFT_24;
+ /* The frequency dividing value (NIDIV) for frequency divider 1 */
+ *(regaddr_lvds->lclkselr) |= (uint32_t)lvds_tmp->lvds_idiv_set << VDC5_REG_SHIFT_16;
+ /* Internal parameter setting for LVDS PLL */
+ *(regaddr_lvds->lclkselr) |= (uint32_t)lvds_tmp->lvdspll_tst << VDC5_REG_SHIFT_10;
+ /* The frequency dividing value (NODIV) for frequency divider 2 */
+ *(regaddr_lvds->lclkselr) |= (uint32_t)lvds_tmp->lvds_odiv_set << VDC5_REG_SHIFT_8;
+ if (lvds_tmp->lvds_vdc_sel != VDC5_CHANNEL_0) {
+ /* A channel in VDC5 whose data is to be output through the LVDS */
+ *(regaddr_lvds->lclkselr) |= (uint32_t)VDC5_REG_BIT1;
+ }
+
+ /* LPLLSETR: LVDS PLL setting register */
+ *(regaddr_lvds->lpllsetr) &= (uint32_t)~VDC5_REG_MASK_0X07FF1F30;
+ /* The frequency dividing value (NFD) for the feedback frequency */
+ *(regaddr_lvds->lpllsetr) |= (uint32_t)lvds_tmp->lvdspll_fd << VDC5_REG_SHIFT_16;
+ /* The frequency dividing value (NRD) for the input frequency */
+ *(regaddr_lvds->lpllsetr) |= (uint32_t)lvds_tmp->lvdspll_rd << VDC5_REG_SHIFT_8;
+ /* The frequency dividing value (NOD) for the output frequency */
+ *(regaddr_lvds->lpllsetr) |= (uint32_t)lvds_tmp->lvdspll_od << VDC5_REG_SHIFT_4;
+
+ for (counter = 0; counter < (uint32_t)VDC5_LVDS_PLL_WAIT_CYCLE; counter++) {
+ /* This is a delay (1 usec) while waiting for PLL PD to settle. */
+ }
+ /* Controls power-down for the LVDS PLL: Normal operation */
+ *(regaddr_lvds->lpllsetr) &= (uint32_t)~VDC5_REG_BIT0;
+
+ /* Wait for 200 usec. */
+ Wait_200_usec();
+
+ /* Output from the LVDS PLL is enabled. */
+ *(regaddr_lvds->lclkselr) |= (uint32_t)VDC5_REG_BIT4;
+ }
+
+ inp_sel_cnt_reg = vdc5_regaddr_input_ctrl[ch].inp_sel_cnt;
+ /* Input select */
+ if (param->panel_icksel == VDC5_PANEL_ICKSEL_IMG_DV) {
+ *inp_sel_cnt_reg |= (uint32_t)VDC5_REG_BIT20;
+ } else {
+ *inp_sel_cnt_reg &= (uint32_t)~VDC5_REG_BIT20;
+ }
+ syscnt_panel_clk_tmp = panel_dcdr_tbl[param->panel_dcdr];
+ syscnt_panel_clk_tmp = (uint16_t)((uint32_t)syscnt_panel_clk_tmp |
+ (uint32_t)panel_icksel_tbl[param->panel_icksel]);
+ *syscnt_panel_clk_reg = syscnt_panel_clk_tmp;
+ /* Enable */
+ syscnt_panel_clk_tmp = (uint16_t)((uint32_t)syscnt_panel_clk_tmp | VDC5_REG_BIT8);
+ *syscnt_panel_clk_reg = syscnt_panel_clk_tmp;
+
+} /* End of function VDC5_Initialize() */
+
+/**************************************************************************//**
+ * @brief Sets registers for termination
+ * @param[in] ch : Channel
+ * @retval None
+******************************************************************************/
+void VDC5_Terminate (const vdc5_channel_t ch)
+{
+ volatile uint16_t * syscnt_panel_clk_reg;
+ uint16_t syscnt_panel_clk_tmp;
+ vdc5_resource_state_t rsrc_state;
+ vdc5_onoff_t lvds_ref;
+ const vdc5_regaddr_lvds_t * regaddr_lvds;
+ volatile uint32_t counter;
+
+ syscnt_panel_clk_reg = vdc5_regaddr_system_ctrl[ch].syscnt_panel_clk;
+ /* Disable */
+ syscnt_panel_clk_tmp = (uint16_t)((uint32_t)*syscnt_panel_clk_reg & (~VDC5_REG_BIT8));
+ *syscnt_panel_clk_reg = syscnt_panel_clk_tmp;
+
+ rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_LVDS_CLK);
+ if (rsrc_state != VDC5_RESOURCE_ST_INVALID) { /* LVDS PLL clock is set. */
+ lvds_ref = VDC5_ShrdPrmGetLvdsClkRef();
+ if (lvds_ref == VDC5_OFF) { /* LVDS PLL clock is not referred. */
+ regaddr_lvds = &vdc5_regaddr_lvds;
+
+ /* Output from the LVDS PLL is disabled. */
+ *(regaddr_lvds->lclkselr) &= (uint32_t)~VDC5_REG_BIT4;
+ /* Controls power-down for the LVDS PLL: Power-down state */
+ *(regaddr_lvds->lpllsetr) |= (uint32_t)VDC5_REG_BIT0;
+ for (counter = 0; counter < (uint32_t)VDC5_LVDS_PLL_WAIT_CYCLE; counter++) {
+ /* This is a delay (1 usec) while waiting for PLL PD to settle. */
+ }
+ }
+ }
+} /* End of function VDC5_Terminate() */
+
+/**************************************************************************//**
+ * @brief Sets registers for video input
+ * @param[in] ch : Channel
+ * @param[in] param : Video input setup parameter
+ * @retval None
+******************************************************************************/
+void VDC5_VideoInput (const vdc5_channel_t ch, const vdc5_input_t * const param)
+{
+ const vdc5_regaddr_input_ctrl_t * input_ctrl;
+ const vdc5_sync_delay_t * dly_tmp;
+ const vdc5_ext_in_sig_t * ext_sig_tmp;
+
+ input_ctrl = &vdc5_regaddr_input_ctrl[ch];
+
+ /* Input select */
+ if (param->inp_sel == VDC5_INPUT_SEL_VDEC) {
+ *(input_ctrl->inp_sel_cnt) &= (uint32_t)~VDC5_REG_BIT20;
+ } else {
+ *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_REG_BIT20;
+ }
+ /* Vsync signal 1/2fH and 1/4fH phase timing */
+ *(input_ctrl->inp_vsync_ph_adj) = (uint32_t)param->inp_fh50 << VDC5_REG_SHIFT_16;
+ *(input_ctrl->inp_vsync_ph_adj) |= (uint32_t)param->inp_fh25;
+
+ /* Sync signal delay adjustment */
+ dly_tmp = param->dly;
+ if (dly_tmp != NULL) {
+ /* Number of lines for delaying Vsync signal and field differentiation signal */
+ *(input_ctrl->inp_dly_adj) = (uint32_t)dly_tmp->inp_vs_dly_l << VDC5_REG_SHIFT_24;
+ /* Field differentiation signal delay amount */
+ *(input_ctrl->inp_dly_adj) |= (uint32_t)dly_tmp->inp_fld_dly << VDC5_REG_SHIFT_16;
+ /* Vsync signal delay amount */
+ *(input_ctrl->inp_dly_adj) |= (uint32_t)dly_tmp->inp_vs_dly << VDC5_REG_SHIFT_8;
+ /* Hsync signal delay amount */
+ *(input_ctrl->inp_dly_adj) |= (uint32_t)dly_tmp->inp_hs_dly;
+ }
+
+ /* Horizontal noise reduction operating mode, Y/Cb/Cr mode */
+ *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)VDC5_REG_BIT20;
+
+ /* External input signal */
+ ext_sig_tmp = param->ext_sig;
+ if (ext_sig_tmp != NULL) {
+ /* Setting external input video signal */
+ SetVideoExternalInput(ext_sig_tmp, input_ctrl);
+
+ /* Horizontal noise reduction operating mode, G/B/R mode */
+ if ((ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_RGB888) ||
+ (ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_RGB666) ||
+ (ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_RGB565)) {
+ *(input_ctrl->imgcnt_nr_cnt0) &= (uint32_t)~VDC5_REG_BIT20;
+ }
+ }
+
+ /* Register update control register (INP_UPDATE)
+ b4 INP_EXT_UPDATE
+ b0 INP_IMG_UPDATE */
+ *(input_ctrl->inp_update) |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+ /* Register update control register (IMGCNT_UPDATE)
+ b0 IMGCNT_VEN */
+ *(input_ctrl->imgcnt_update) |= (uint32_t)VDC5_REG_BIT0;
+} /* End of function VDC5_VideoInput() */
+
+/**************************************************************************//**
+ * @brief Sets registers for sync control
+ * @param[in] ch : Channel
+ * @param[in] param : Sync signal control parameter
+ * @retval None
+******************************************************************************/
+void VDC5_SyncControl (const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param)
+{
+ const vdc5_regaddr_scaler_t * scaler_0;
+ const vdc5_regaddr_scaler_t * scaler_1;
+ const vdc5_regaddr_scaler_t * scaler_oir;
+ uint32_t full_scr;
+
+ scaler_0 = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0];
+ scaler_1 = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1];
+ scaler_oir = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR];
+
+ if (param->vsync_cpmpe != NULL) {
+ /* Frequent Vsync signal masking period */
+ *(scaler_0->scl0_frc1) = (uint32_t)param->vsync_cpmpe->res_vmask << VDC5_REG_SHIFT_16;
+ *(scaler_1->scl0_frc1) = (uint32_t)param->vsync_cpmpe->res_vmask << VDC5_REG_SHIFT_16;
+ /* Missing-Sync compensating pulse output wait time */
+ *(scaler_0->scl0_frc2) = (uint32_t)param->vsync_cpmpe->res_vlack << VDC5_REG_SHIFT_16;
+ *(scaler_1->scl0_frc2) = (uint32_t)param->vsync_cpmpe->res_vlack << VDC5_REG_SHIFT_16;
+ /* Frequent Vsync signal masking and missing Vsync signal compensation */
+ *(scaler_0->scl0_frc1) |= (uint32_t)VDC5_REG_BIT0;
+ *(scaler_1->scl0_frc1) |= (uint32_t)VDC5_REG_BIT0;
+ *(scaler_0->scl0_frc2) |= (uint32_t)VDC5_REG_BIT0;
+ *(scaler_1->scl0_frc2) |= (uint32_t)VDC5_REG_BIT0;
+ } else {
+ /* Frequent Vsync signal masking and missing Vsync signal compensation are disabled, if unnecessary. */
+ *(scaler_0->scl0_frc1) &= (uint32_t)~VDC5_REG_BIT0;
+ *(scaler_1->scl0_frc1) &= (uint32_t)~VDC5_REG_BIT0;
+ *(scaler_0->scl0_frc2) &= (uint32_t)~VDC5_REG_BIT0;
+ *(scaler_0->scl0_frc2) |= (uint32_t)VDC5_REG_BIT_0XFFFF0000;
+ *(scaler_1->scl0_frc2) &= (uint32_t)~VDC5_REG_BIT0;
+ *(scaler_1->scl0_frc2) |= (uint32_t)VDC5_REG_BIT_0XFFFF0000;
+ }
+ /* In OIR, frequent Vsync signal masking and missing Vsync signal compensation are set to off. */
+ *(scaler_oir->scl0_frc1) &= (uint32_t)~VDC5_REG_BIT0;
+ *(scaler_oir->scl0_frc2) &= (uint32_t)~VDC5_REG_BIT0;
+
+ /* Hsync period setting and free-running Vsync period initialization */
+ *(scaler_0->scl0_frc4) = (uint32_t)param->res_fh;
+ *(scaler_1->scl0_frc4) = (uint32_t)param->res_fh;
+ *(scaler_oir->scl0_frc4) = (uint32_t)param->res_fh;
+ /* Vsync signal output select (free-running Vsync on/off control) */
+ if (param->res_vs_sel == VDC5_OFF) {
+ *(scaler_0->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT0;
+ *(scaler_1->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT0;
+ } else {
+ *(scaler_0->scl0_frc3) |= (uint32_t)VDC5_REG_BIT0;
+ *(scaler_1->scl0_frc3) |= (uint32_t)VDC5_REG_BIT0;
+ *(scaler_0->scl0_frc4) &= (uint32_t)~VDC5_REG_MASK_0X07FF0000;
+ *(scaler_0->scl0_frc4) |= (uint32_t)param->res_fv << VDC5_REG_SHIFT_16;
+ *(scaler_1->scl0_frc4) &= (uint32_t)~VDC5_REG_MASK_0X07FF0000;
+ *(scaler_1->scl0_frc4) |= (uint32_t)param->res_fv << VDC5_REG_SHIFT_16;
+ }
+ /* In OIR, external input Vsync signal is selected automatically. */
+ *(scaler_oir->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT0;
+
+ /* Sync signal output and full-screen enable signal select: Scaler 0 */
+ *(scaler_0->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT8;
+ *(scaler_1->scl0_frc3) |= (uint32_t)VDC5_REG_BIT8;
+
+ /* Vsync signal delay control */
+ *(scaler_0->scl0_frc5) &= (uint32_t)~VDC5_REG_MASK_0X000000FF;
+ *(scaler_0->scl0_frc5) |= (uint32_t)param->res_vsdly;
+ *(scaler_1->scl0_frc5) &= (uint32_t)~VDC5_REG_MASK_0X000000FF;
+ *(scaler_1->scl0_frc5) |= (uint32_t)param->res_vsdly;
+ *(scaler_oir->scl0_frc5) &= (uint32_t)~VDC5_REG_MASK_0X000000FF;
+ *(scaler_oir->scl0_frc5) |= OIR_VSYNC_DELAY;
+
+ /* Full-screen enable signal */
+ full_scr = (uint32_t)param->res_f.vs << VDC5_REG_SHIFT_16;
+ full_scr |= (uint32_t)param->res_f.vw;
+
+ *(scaler_0->scl0_frc6) = full_scr;
+ *(scaler_1->scl0_frc6) = full_scr;
+ *(scaler_oir->scl0_frc6) = full_scr;
+
+ full_scr = (uint32_t)param->res_f.hs << VDC5_REG_SHIFT_16;
+ full_scr |= (uint32_t)param->res_f.hw;
+
+ *(scaler_0->scl0_frc7) = full_scr;
+ *(scaler_1->scl0_frc7) = full_scr;
+ *(scaler_oir->scl0_frc7) = full_scr;
+
+ /* Register update control register (SC0_SCL0_UPDATE, SC1_SCL0_UPDATE, OIR_SCL0_UPDATE)
+ b8 SCL0_UPDATE
+ b4 SCL0_VEN_B */
+ *(scaler_0->scl0_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+ *(scaler_1->scl0_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+ *(scaler_oir->scl0_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+
+ SetInitialConnection(ch);
+
+ VDC5_ShrdPrmSetUndSel(ch, VDC5_OFF);
+} /* End of function VDC5_SyncControl() */
+
+/**************************************************************************//**
+ * @brief Sets registers for display output
+ * @param[in] ch : Channel
+ * @param[in] param : Display output configuration parameter
+ * @retval None
+******************************************************************************/
+void VDC5_DisplayOutput (const vdc5_channel_t ch, const vdc5_output_t * const param)
+{
+ const vdc5_regaddr_output_ctrl_t * output_ctrl;
+ volatile uint32_t * output_pin_regaddr[VDC5_LCD_TCON_PIN_NUM];
+ uint32_t tcon_sig_index;
+ const vdc5_lcd_tcon_timing_t * const * lcd_tcon_timing;
+ static void (* const tcon_function_tbl[VDC5_LCD_TCONSIG_NUM])(
+ const vdc5_lcd_tcon_timing_t * const lcd_tcon,
+ const vdc5_regaddr_output_ctrl_t * const output_ctrl) = {
+ &SetLcdTcon_STVA_VS, /* STVA/VS */
+ &SetLcdTcon_STVB_VE, /* STVB/VE */
+ &SetLcdTcon_STH_HS, /* STH_HS */
+ &SetLcdTcon_STB_HE, /* STB_HE */
+ &SetLcdTcon_CPV_GCK, /* CPV_GCK */
+ &SetLcdTcon_POLA, /* POLA */
+ &SetLcdTcon_POLB, /* POLB */
+ &SetLcdTcon_DE /* DE */
+ };
+ const uint32_t output_pin_edge[VDC5_LCD_TCON_PIN_NUM] = {
+ VDC5_REG_TCON0_EDGE, VDC5_REG_TCON1_EDGE, VDC5_REG_TCON2_EDGE, VDC5_REG_TCON3_EDGE,
+ VDC5_REG_TCON4_EDGE, VDC5_REG_TCON5_EDGE, VDC5_REG_TCON6_EDGE
+ };
+ vdc5_lcd_tcon_pin_t tcon_pin_tmp;
+ const vdc5_gr_disp_sel_t gr_disp_sel_tbl[VDC5_GR_TYPE_NUM] = {
+ /* Graphics display mode for initialization */
+ VDC5_DISPSEL_BACK, /* Graphics 0 */
+ VDC5_DISPSEL_LOWER, /* Graphics 1 */
+ VDC5_DISPSEL_LOWER, /* Graphics 2 */
+ VDC5_DISPSEL_LOWER, /* Graphics 3 */
+ VDC5_DISPSEL_IGNORED, /* VIN */
+ VDC5_DISPSEL_BACK /* OIR */
+ };
+ const uint32_t dither_format[VDC5_LCD_OUTFORMAT_NUM] = {
+ /* Panel dither output format select */
+ VDC5_REG_PATH_FORMAT_RGB888, VDC5_REG_PATH_FORMAT_RGB666,
+ VDC5_REG_PATH_FORMAT_RGB565, VDC5_REG_PATH_FORMAT_NON
+ };
+
+ output_ctrl = &vdc5_regaddr_output_ctrl[ch];
+
+ /* 1/2fH timing */
+ *(output_ctrl->tcon_tim) = (uint32_t)param->tcon_half << VDC5_REG_SHIFT_16;
+ /* Offset Hsync signal timing */
+ *(output_ctrl->tcon_tim) |= (uint32_t)param->tcon_offset;
+
+ /* Create output pin register address table */
+ output_pin_regaddr[VDC5_LCD_TCON_PIN_0] = output_ctrl->tcon_tim_stva2;
+ output_pin_regaddr[VDC5_LCD_TCON_PIN_1] = output_ctrl->tcon_tim_stvb2;
+ output_pin_regaddr[VDC5_LCD_TCON_PIN_2] = output_ctrl->tcon_tim_sth2;
+ output_pin_regaddr[VDC5_LCD_TCON_PIN_3] = output_ctrl->tcon_tim_stb2;
+ output_pin_regaddr[VDC5_LCD_TCON_PIN_4] = output_ctrl->tcon_tim_cpv2;
+ output_pin_regaddr[VDC5_LCD_TCON_PIN_5] = output_ctrl->tcon_tim_pola2;
+ output_pin_regaddr[VDC5_LCD_TCON_PIN_6] = output_ctrl->tcon_tim_polb2;
+
+ /* Clear output phase control of LCT_TCON0~6 pin */
+ *(output_ctrl->out_clk_phase) &= (uint32_t)~VDC5_REG_MASK_0X0000007F;
+ /* LCD TCON */
+ lcd_tcon_timing = param->outctrl;
+ for (tcon_sig_index = 0; tcon_sig_index < VDC5_LCD_TCONSIG_NUM; tcon_sig_index++) {
+ if (*lcd_tcon_timing != NULL) {
+ /* Setting LCD TCON */
+ tcon_function_tbl[tcon_sig_index](*lcd_tcon_timing, output_ctrl);
+
+ tcon_pin_tmp = (*lcd_tcon_timing)->tcon_pin;
+ if (tcon_pin_tmp != VDC5_LCD_TCON_PIN_NON) {
+ /* LCD TCON output pin select */
+ *(output_pin_regaddr[tcon_pin_tmp]) &= (uint32_t)~VDC5_REG_MASK_0X00000007;
+ *(output_pin_regaddr[tcon_pin_tmp]) |= tcon_sig_index;
+ /* Output phase control of LCT_TCON pin */
+ if ((*lcd_tcon_timing)->outcnt_edge != VDC5_EDGE_RISING) {
+ *(output_ctrl->out_clk_phase) |= output_pin_edge[tcon_pin_tmp];
+ }
+ }
+ }
+ lcd_tcon_timing++;
+ }
+
+ *(output_ctrl->out_set) &= (uint32_t)~VDC5_REG_MASK_0X11003313;
+ /* Bit endian change ON/OFF control */
+ if (param->out_endian_on != VDC5_OFF) {
+ *(output_ctrl->out_set) |= (uint32_t)VDC5_REG_BIT28;
+ }
+ /* B/R signal swap ON/OFF control */
+ if (param->out_swap_on != VDC5_OFF) {
+ *(output_ctrl->out_set) |= (uint32_t)VDC5_REG_BIT24;
+ }
+ /* Output format select */
+ *(output_ctrl->out_set) |= (uint32_t)param->out_format << VDC5_REG_SHIFT_12;
+
+ /* Panel dither output format select */
+ *(output_ctrl->out_pdtha) &= (uint32_t)~VDC5_REG_MASK_0X00030000;
+ *(output_ctrl->out_pdtha) |= dither_format[param->out_format];
+
+ if (param->out_format == VDC5_LCD_OUTFORMAT_SERIAL_RGB) {
+ /* Clock frequency control */
+ *(output_ctrl->out_set) |= (uint32_t)param->out_frq_sel << VDC5_REG_SHIFT_8;
+ /* Scan direction select */
+ if (param->out_dir_sel != VDC5_LCD_SERIAL_SCAN_FORWARD) {
+ *(output_ctrl->out_set) |= (uint32_t)VDC5_REG_BIT4;
+ }
+ /* Clock phase adjustment */
+ *(output_ctrl->out_set) |= (uint32_t)param->out_phase;
+ } else {
+ /* Clock frequency control */
+ *(output_ctrl->out_set) |= (uint32_t)VDC5_LCD_PARALLEL_CLKFRQ_1 << VDC5_REG_SHIFT_8;
+ }
+
+ /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+ if (param->outcnt_lcd_edge == VDC5_EDGE_RISING) {
+ *(output_ctrl->out_clk_phase) &= (uint32_t)~VDC5_REG_BIT8;
+ } else {
+ *(output_ctrl->out_clk_phase) |= (uint32_t)VDC5_REG_BIT8;
+ }
+
+ /* Set background color */
+ SetGrapicsBackgroundColor(ch);
+ /* Initialize graphics display mode */
+ SetGraphicsDisplayMode(ch, VDC5_LAYER_ID_ALL, gr_disp_sel_tbl);
+
+ /* TCON register update control register (TCON_UPDATE)
+ b0 TCON_VEN */
+ *(output_ctrl->tcon_update) |= (uint32_t)VDC5_REG_BIT0;
+ /* Register update control register (OUT_UPDATE)
+ b0 OUTCNT_VEN */
+ *(output_ctrl->out_update) |= (uint32_t)VDC5_REG_BIT0;
+
+} /* End of function VDC5_DisplayOutput() */
+
+/**************************************************************************//**
+ * @brief Sets registers for data write control processing
+ * @param[in] ch : Channel
+ * @param[in] scaling_id : Scaling type ID
+ * @param[in] param : Data write control parameter
+ * @retval None
+******************************************************************************/
+void VDC5_WriteDataControl (
+ const vdc5_channel_t ch,
+ const vdc5_scaling_type_t scaling_id,
+ const vdc5_write_t * const param)
+{
+ const vdc5_regaddr_scaler_t * scaler;
+ const vdc5_scalingdown_rot_t * scldw_rot;
+
+ scaler = &vdc5_regaddr_scaler[ch][scaling_id];
+ scldw_rot = ¶m->scalingdown_rot;
+
+ /* Image area to be captured */
+ *(scaler->scl0_ds2) = (uint32_t)scldw_rot->res.vs << VDC5_REG_SHIFT_16;
+ *(scaler->scl0_ds2) |= (uint32_t)scldw_rot->res.vw;
+ *(scaler->scl0_ds3) = (uint32_t)scldw_rot->res.hs << VDC5_REG_SHIFT_16;
+ *(scaler->scl0_ds3) |= (uint32_t)scldw_rot->res.hw;
+
+ *(scaler->scl1_wr1) &= (uint32_t)~VDC5_REG_MASK_0X0007000D;
+ /* Swap setting in frame buffer writing */
+ *(scaler->scl1_wr1) |= (uint32_t)param->res_wrswa << VDC5_REG_SHIFT_16;
+ /* Frame buffer video-signal writing format */
+ *(scaler->scl1_wr1) |= (uint32_t)param->res_md << VDC5_REG_SHIFT_2;
+ /* Transfer burst length for frame buffer writing */
+ if (param->res_bst_md != VDC5_BST_MD_32BYTE) {
+ *(scaler->scl1_wr1) |= (uint32_t)VDC5_REG_BIT0;
+ }
+
+ /* Frame buffer base address */
+ *(scaler->scl1_wr2) = (uint32_t)param->base;
+ /* Frame buffer line offset address[byte] */
+ *(scaler->scl1_wr3) = param->ln_off << VDC5_REG_SHIFT_16;
+ /* Number of frames of buffer to be written to (res_flm_num + 1) */
+ *(scaler->scl1_wr3) |= param->flm_num;
+ /* Frame buffer frame offset address [byte] */
+ if (param->flm_num != 0u) {
+ *(scaler->scl1_wr4) = param->flm_off;
+ }
+
+ /* Writing rate */
+ *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_MASK_0X00000300;
+ *(scaler->scl1_wr5) |= (uint32_t)param->res_fs_rate << VDC5_REG_SHIFT_8;
+
+ /* Dither correction on/off */
+ if (param->res_dth_on == VDC5_OFF) {
+ *(scaler->scl1_wr6) &= (uint32_t)~VDC5_REG_BIT4;
+ } else {
+ *(scaler->scl1_wr6) |= (uint32_t)VDC5_REG_BIT4;
+ }
+ /* Bit Reduction */
+ if (param->res_md == VDC5_RES_MD_RGB565) {
+ /* On */
+ *(scaler->scl1_wr6) |= (uint32_t)VDC5_REG_BIT0;
+ } else {
+ /* Off */
+ *(scaler->scl1_wr6) &= (uint32_t)~VDC5_REG_BIT0;
+ }
+
+ if (scaling_id == VDC5_SC_TYPE_OIR) {
+ /* OIR */
+ /* Vertical and horizontal width after scaling-down control block */
+ *(scaler->scl0_ds7) = (uint32_t)scldw_rot->res.vw << VDC5_REG_SHIFT_16;
+ *(scaler->scl0_ds7) |= (uint32_t)scldw_rot->res.hw;
+
+ /* Vertical scaling-down and horizontal scaling-down : OFF */
+ *(scaler->scl0_ds1) &= (uint32_t)~VDC5_REG_MASK_0X00000011;
+
+ /* Field operating mode select is fixed to progressive */
+ *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT12;
+ } else {
+ /* Scaler 0 or 1 */
+ /* Field determination signal delay control */
+ if (param->flm_num == 0u) {
+ /* Frame buffer: One plane */
+ *(scaler->scl0_frc5) &= (uint32_t)~VDC5_REG_BIT8;
+ } else {
+ /* Frame buffer: Two planes or more */
+ *(scaler->scl0_frc5) |= (uint32_t)VDC5_REG_BIT8;
+ }
+
+ /* Horizontal prefilter */
+ if (scldw_rot->res_pfil_sel == VDC5_OFF) {
+ *(scaler->scl0_ds4) &= (uint32_t)~VDC5_REG_BIT29;
+ } else {
+ *(scaler->scl0_ds4) |= (uint32_t)VDC5_REG_BIT29;
+ }
+ /* Number of valid lines in vertical direction output by scaling-down control block */
+ *(scaler->scl0_ds7) = (uint32_t)scldw_rot->res_out_vw << VDC5_REG_SHIFT_16;
+ /* Number of valid horizontal pixels output by scaling-down control block */
+ *(scaler->scl0_ds7) |= (uint32_t)scldw_rot->res_out_hw;
+
+ /* Scaling-down */
+ SetScalingDown(scldw_rot, param->res_inter, scaler);
+
+ /* Frame buffer writing mode for image processing */
+ *(scaler->scl1_wr1) &= (uint32_t)~VDC5_REG_MASK_0X00000070;
+ *(scaler->scl1_wr1) |= (uint32_t)scldw_rot->res_ds_wr_md << VDC5_REG_SHIFT_4;
+
+ /* Field operating mode select */
+ if (param->res_inter == VDC5_RES_INTER_PROGRESSIVE) {
+ /* Progressive */
+ *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT12;
+ } else {
+ /* Interlace */
+ *(scaler->scl1_wr5) |= (uint32_t)VDC5_REG_BIT12;
+ }
+ /* Write field select */
+ if (param->res_fld_sel == VDC5_RES_FLD_SEL_TOP) {
+ /* Top field */
+ *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT4;
+ } else {
+ /* Bottom field */
+ *(scaler->scl1_wr5) |= (uint32_t)VDC5_REG_BIT4;
+ }
+
+ /* Frame buffer for bottom */
+ if (param->btm_base != NULL) {
+ /* SC_RES_TB_ADD_MOD */
+ *(scaler->scl1_wr1) |= (uint32_t)VDC5_REG_MASK_0X00000080;
+
+ /* Frame buffer base address */
+ *(scaler->scl1_wr8) = (uint32_t)param->btm_base;
+ /* Frame buffer line offset address[byte] */
+ *(scaler->scl1_wr9) = param->ln_off << VDC5_REG_SHIFT_16;
+ /* Number of frames of buffer to be written to (defined by res_flm_num + 1) */
+ *(scaler->scl1_wr9) |= param->flm_num;
+ /* Frame buffer frame offset address */
+ if (param->flm_num != 0u) {
+ *(scaler->scl1_wr10) = param->flm_off;
+ }
+ } else {
+ /* SC_RES_TB_ADD_MOD */
+ *(scaler->scl1_wr1) &= (uint32_t)~VDC5_REG_MASK_0X00000080;
+ }
+ }
+
+ /* Register update control register (SC0/SC1/OIR_SCL0_UPDATE)
+ b12 SCL0_VEN_C
+ b4 SCL0_VEN_B
+ b0 SCL0_VEN_A */
+ *(scaler->scl0_update) |= (uint32_t)(VDC5_REG_BIT12 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+ /* Register update control register (SC0/SC1/OIR_SCL1_UPDATE)
+ b16 SCL1_UPDATE_A
+ b4 SCL1_VEN_B
+ b0 SCL1_VEN_A */
+ *(scaler->scl1_update) |= (uint32_t)(VDC5_REG_BIT16 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+
+ if (scaling_id != VDC5_SC_TYPE_OIR) {
+ SetInputCntrlColorMtx(ch, scaling_id);
+ }
+} /* End of function VDC5_WriteDataControl() */
+
+/**************************************************************************//**
+ * @brief Sets registers for data write change processing
+ * @param[in] ch : Channel
+ * @param[in] scaling_id : Scaling type ID
+ * @param[in] param : Data write change parameter
+ * @retval None
+******************************************************************************/
+void VDC5_ChangeWriteProcess (
+ const vdc5_channel_t ch,
+ const vdc5_scaling_type_t scaling_id,
+ const vdc5_write_chg_t * const param)
+{
+ const vdc5_regaddr_scaler_t * scaler;
+ const vdc5_scalingdown_rot_t * scldw_rot;
+ vdc5_res_inter_t res_inter_tmp;
+
+ scaler = &vdc5_regaddr_scaler[ch][scaling_id];
+ scldw_rot = ¶m->scalingdown_rot;
+
+ /* Image area to be captured */
+ *(scaler->scl0_ds2) = (uint32_t)scldw_rot->res.vs << VDC5_REG_SHIFT_16;
+ *(scaler->scl0_ds2) |= (uint32_t)scldw_rot->res.vw;
+ *(scaler->scl0_ds3) = (uint32_t)scldw_rot->res.hs << VDC5_REG_SHIFT_16;
+ *(scaler->scl0_ds3) |= (uint32_t)scldw_rot->res.hw;
+
+ if (scaling_id == VDC5_SC_TYPE_OIR) {
+ /* OIR */
+ /* Vertical and horizontal width after scaling-down control block */
+ *(scaler->scl0_ds7) = (uint32_t)scldw_rot->res.vw << VDC5_REG_SHIFT_16;
+ *(scaler->scl0_ds7) |= (uint32_t)scldw_rot->res.hw;
+ } else {
+ /* Scaler 0 or 1 */
+ /* Horizontal prefilter */
+ if (scldw_rot->res_pfil_sel == VDC5_OFF) {
+ *(scaler->scl0_ds4) &= (uint32_t)~VDC5_REG_BIT29;
+ } else {
+ *(scaler->scl0_ds4) |= (uint32_t)VDC5_REG_BIT29;
+ }
+ /* Number of valid lines in vertical direction output by scaling-down control block */
+ *(scaler->scl0_ds7) = (uint32_t)scldw_rot->res_out_vw << VDC5_REG_SHIFT_16;
+ /* Number of valid horizontal pixels output by scaling-down control block */
+ *(scaler->scl0_ds7) |= (uint32_t)scldw_rot->res_out_hw;
+
+ /* Progressive or interlace */
+ res_inter_tmp = VDC5_ShrdPrmGetInterlace(ch, scaling_id);
+ /* Scaling-down */
+ SetScalingDown(scldw_rot, res_inter_tmp, scaler);
+
+ /* Frame buffer writing mode for image processing */
+ *(scaler->scl1_wr1) &= (uint32_t)~VDC5_REG_MASK_0X00000070;
+ *(scaler->scl1_wr1) |= (uint32_t)scldw_rot->res_ds_wr_md << VDC5_REG_SHIFT_4;
+
+ /* Register update control register (SC0/SC1)
+ b4 SCL1_VEN_B
+ b0 SCL1_VEN_A */
+ *(scaler->scl1_update) |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+ }
+
+ /* Register update control register (SC0/SC1/OIR_SCL0_UPDATE)
+ b12 SCL0_VEN_C
+ b4 SCL0_VEN_B
+ b0 SCL0_VEN_A */
+ *(scaler->scl0_update) |= (uint32_t)(VDC5_REG_BIT12 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+
+} /* End of function VDC5_ChangeWriteProcess() */
+
+/**************************************************************************//**
+ * @brief Sets registers for data read control processing
+ * @param[in] ch : Channel
+ * @param[in] graphics_id : Graphics type ID
+ * @param[in] param : Data read control parameter
+ * @retval None
+******************************************************************************/
+void VDC5_ReadDataControl (
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_read_t * const param)
+{
+ const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+ const vdc5_regaddr_img_qlty_imp_t * img_qlty_imp;
+ vdc5_width_read_fb_t * w_read_fb;
+ vdc5_onoff_t graphics_enlargement;
+ vdc5_color_space_t color_space;
+ vdc5_resource_state_t rsrc_state;
+ uint32_t reg_data;
+
+ w_read_fb = VDC5_ShrdPrmGetFrBuffWidth_Rd(ch, graphics_id);
+
+ graphics_enlargement = ConfirmGraphicsEnlargement(graphics_id, param->gr_flm_sel, w_read_fb, ¶m->gr_grc);
+
+ if ((graphics_id == VDC5_GR_TYPE_GR0) ||
+ (graphics_id == VDC5_GR_TYPE_GR1) ||
+ (graphics_id == VDC5_GR_TYPE_OIR)) {
+ SetScalerGraphics(ch, graphics_id, w_read_fb, ¶m->gr_grc, param->gr_flm_sel, graphics_enlargement);
+ }
+
+ img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+ *(img_synthesizer->gr_flm1) &= (uint32_t)~VDC5_REG_MASK_0X00010301;
+ /* Line offset address direction of the frame buffer */
+ if (param->gr_ln_off_dir != VDC5_GR_LN_OFF_DIR_INC) {
+ *(img_synthesizer->gr_flm1) |= (uint32_t)VDC5_REG_BIT16;
+ }
+ /* Frame buffer address setting signal */
+ *(img_synthesizer->gr_flm1) |= (uint32_t)param->gr_flm_sel << VDC5_REG_SHIFT_8;
+ /* Frame buffer burst transfer mode */
+ if (param->gr_bst_md != VDC5_BST_MD_32BYTE) {
+ *(img_synthesizer->gr_flm1) |= (uint32_t)VDC5_REG_BIT0;
+ }
+ /* Sets the frame buffer number for distortion correction */
+ if (param->gr_flm_sel == VDC5_GR_FLM_SEL_DISTORTION) {
+ if (param->gr_imr_flm_inv == VDC5_OFF) {
+ *(img_synthesizer->gr_flm1) &= (uint32_t)~VDC5_REG_BIT4;
+ } else {
+ *(img_synthesizer->gr_flm1) |= (uint32_t)VDC5_REG_BIT4;
+ }
+ }
+
+ /* Frame buffer base address */
+ *(img_synthesizer->gr_flm2) = (uint32_t)param->gr_base & (uint32_t)~VDC5_REG_MASK_0X00000007;
+
+ /* Frame buffer line offset address[byte] */
+ *(img_synthesizer->gr_flm3) &= (uint32_t)~VDC5_REG_MASK_0X7FFF03FF;
+ *(img_synthesizer->gr_flm3) |= param->gr_ln_off << VDC5_REG_SHIFT_16;
+
+ /* The number of lines when reading the addresses repeatedly */
+ *(img_synthesizer->gr_flm5) = (uint32_t)VDC5_REG_MASK_0X000007FF;
+ /* Number of lines in a frame */
+ *(img_synthesizer->gr_flm5) |= ((uint32_t)w_read_fb->in_vw - 1u) << VDC5_REG_SHIFT_16;
+
+ *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC5_REG_MASK_0XF7FF1C3F;
+ /* Format of the frame buffer read signal */
+ *(img_synthesizer->gr_flm6) |= (uint32_t)param->gr_format << VDC5_REG_SHIFT_28;
+ /* Width of the horizontal valid period */
+ *(img_synthesizer->gr_flm6) |= ((uint32_t)w_read_fb->in_hw - 1u) << VDC5_REG_SHIFT_16;
+ /* Swap setting in frame buffer reading */
+ *(img_synthesizer->gr_flm6) |= (uint32_t)param->gr_rdswa << VDC5_REG_SHIFT_10;
+
+ if ((param->gr_flm_sel == VDC5_GR_FLM_SEL_SCALE_DOWN) || (param->gr_flm_sel == VDC5_GR_FLM_SEL_FLM_NUM)) {
+ /* Sets the amount of data to be skipped through */
+ *(img_synthesizer->gr_flm6) |= DisplayStartPixelSetting((uint32_t)param->gr_base, param->gr_format);
+ }
+
+ /* Graphics display mode */
+ *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+ if ((graphics_id == VDC5_GR_TYPE_GR0) ||
+ (graphics_id == VDC5_GR_TYPE_OIR)) {
+ *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_BACK;
+ } else {
+ *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+ }
+
+ /* Graphics display area */
+ *(img_synthesizer->gr_ab2) = (uint32_t)param->gr_grc.vs << VDC5_REG_SHIFT_16;
+ *(img_synthesizer->gr_ab2) |= (uint32_t)param->gr_grc.vw;
+ *(img_synthesizer->gr_ab3) = (uint32_t)param->gr_grc.hs << VDC5_REG_SHIFT_16;
+ *(img_synthesizer->gr_ab3) |= (uint32_t)param->gr_grc.hw;
+
+ /* Initialize alpha blending in a rectangular area */
+ if ((graphics_id == VDC5_GR_TYPE_GR1) ||
+ (graphics_id == VDC5_GR_TYPE_GR2) ||
+ (graphics_id == VDC5_GR_TYPE_GR3)) {
+ /* Turns off alpha blending in a rectangular area */
+ *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X0000D000;
+ /* The valid image area for alpha blending in a rectangular area */
+ reg_data = *(img_synthesizer->gr_ab2);
+ *(img_synthesizer->gr_ab4) = reg_data;
+ reg_data = *(img_synthesizer->gr_ab3);
+ *(img_synthesizer->gr_ab5) = reg_data;
+ /* Disable fade-in and fade-out */
+ *(img_synthesizer->gr_ab6) &= (uint32_t)~VDC5_REG_MASK_0X01FF00FF;
+ /* Set the initial alpha value to '255' */
+ *(img_synthesizer->gr_ab7) |= (uint32_t)VDC5_REG_MASK_0X00FF0000;
+ }
+ /* Turns off chroma-key processing */
+ *(img_synthesizer->gr_ab7) &= (uint32_t)~VDC5_REG_BIT0;
+
+ if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_OIR)) {
+ /* Alpha value is set to 255. */
+ *(img_synthesizer->gr_ab10) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+ *(img_synthesizer->gr_ab11) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+ }
+ if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_GR1)) {
+ /* Swapping of data read from buffer in the YCbCr422 format */
+ *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC5_REG_MASK_0X0000E000;
+ if (param->gr_format == VDC5_GR_FORMAT_YCBCR422) {
+ *(img_synthesizer->gr_flm6) |= (uint32_t)param->gr_ycc_swap << VDC5_REG_SHIFT_13;
+ /* The interpolation mode for YCC422 to YCbCr444 conversion is fixed to average interpolation */
+ *(img_synthesizer->gr_flm6) |= (uint32_t)VDC5_REG_BIT8;
+ } else {
+ /* If the format of the frame buffer read signal is not YCbCr422,
+ initialize the swapping of data read from buffer in the YCbCr422 format. */
+ *(img_synthesizer->gr_flm6) |= (uint32_t)VDC5_GR_YCCSWAP_CBY0CRY1 << VDC5_REG_SHIFT_13;
+ }
+
+ SetupGraphicsVIN(ch, graphics_id, param->gr_flm_sel, graphics_enlargement);
+
+ color_space = VDC5_ShrdPrmGetColorSpaceFbRd(ch, graphics_id);
+
+ SetScalerBackgroundColor(ch, graphics_id, color_space);
+ SetImgQaImproverColorMtx(ch, graphics_id, color_space);
+
+ if (graphics_id == VDC5_GR_TYPE_GR0) {
+ img_qlty_imp = &vdc5_regaddr_img_qlty_imp[ch][VDC5_IMG_IMPRV_0];
+ } else {
+ img_qlty_imp = &vdc5_regaddr_img_qlty_imp[ch][VDC5_IMG_IMPRV_1];
+ }
+ /* Operating mode */
+ if (color_space == VDC5_COLOR_SPACE_GBR) {
+ *(img_qlty_imp->adj_enh_tim1) &= (uint32_t)~VDC5_REG_BIT4;
+ } else {
+ *(img_qlty_imp->adj_enh_tim1) |= (uint32_t)VDC5_REG_BIT4;
+ }
+ /* Register update control register (ADJx_UPDATE)
+ b0 ADJx_VEN */
+ *(img_qlty_imp->adj_update) |= (uint32_t)VDC5_REG_BIT0;
+ }
+
+ rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_1_RD);
+ if ((graphics_id == VDC5_GR_TYPE_GR0) && (rsrc_state == VDC5_RESOURCE_ST_INVALID)) {
+ /* Graphics 0 is specified when graphics 1 is not used. */
+ SetImgQaImproverColorMtx(ch, VDC5_GR_TYPE_GR1, VDC5_COLOR_SPACE_GBR);
+ }
+ /* Graphics register update control register (GRx_UPDATE)
+ b8 GRx_UPDATE
+ b4 GRx_P_VEN
+ b0 GRx_IBUS_VEN */
+ *(img_synthesizer->gr_update) |= (uint32_t)(VDC5_REG_BIT8 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+
+} /* End of function VDC5_ReadDataControl() */
+
+/**************************************************************************//**
+ * @brief Sets registers for data read change processing
+ * @param[in] ch : Channel
+ * @param[in] graphics_id : Graphics type ID
+ * @param[in] param : Data read change parameter
+ * @retval None
+******************************************************************************/
+void VDC5_ChangeReadProcess (
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_read_chg_t * const param)
+{
+ const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+ vdc5_gr_flm_sel_t gr_flm_sel_tmp;
+ vdc5_period_rect_t * gr_grc_tmp;
+ vdc5_width_read_fb_t * w_read_fb;
+ vdc5_onoff_t graphics_enlargement;
+ vdc5_gr_format_t gr_format_tmp;
+
+ gr_flm_sel_tmp = VDC5_ShrdPrmGetSelFbAddrSig(ch, graphics_id);
+ gr_grc_tmp = VDC5_ShrdPrmGetDisplayArea(ch, graphics_id);
+ w_read_fb = VDC5_ShrdPrmGetFrBuffWidth_Rd(ch, graphics_id);
+
+ graphics_enlargement = ConfirmGraphicsEnlargement(graphics_id, gr_flm_sel_tmp, w_read_fb, gr_grc_tmp);
+
+ if ((graphics_id == VDC5_GR_TYPE_GR0) ||
+ (graphics_id == VDC5_GR_TYPE_GR1) ||
+ (graphics_id == VDC5_GR_TYPE_OIR)) {
+ SetScalerGraphics(ch, graphics_id, w_read_fb, gr_grc_tmp, gr_flm_sel_tmp, graphics_enlargement);
+ }
+
+ img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+ /* Frame buffer base address */
+ if (param->gr_base != NULL) {
+ *(img_synthesizer->gr_flm2) = (uint32_t)param->gr_base & (uint32_t)~VDC5_REG_MASK_0X00000007;
+
+ if ((gr_flm_sel_tmp == VDC5_GR_FLM_SEL_SCALE_DOWN) || (gr_flm_sel_tmp == VDC5_GR_FLM_SEL_FLM_NUM)) {
+ gr_format_tmp = VDC5_ShrdPrmGetGraphicsFormat(ch, graphics_id);
+ /* Sets the amount of data to be skipped through */
+ *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC5_REG_MASK_0X0000003F;
+ *(img_synthesizer->gr_flm6) |= DisplayStartPixelSetting((uint32_t)param->gr_base, gr_format_tmp);
+ }
+ }
+
+ /* Size of the frame buffer to be read */
+ if (param->width_read_fb != NULL) {
+ /* Number of lines in a frame */
+ *(img_synthesizer->gr_flm5) &= (uint32_t)~VDC5_REG_MASK_0X07FF0000;
+ *(img_synthesizer->gr_flm5) |= ((uint32_t)param->width_read_fb->in_vw - 1u) << VDC5_REG_SHIFT_16;
+ /* Width of the horizontal valid period */
+ *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC5_REG_MASK_0X07FF0000;
+ *(img_synthesizer->gr_flm6) |= ((uint32_t)param->width_read_fb->in_hw - 1u) << VDC5_REG_SHIFT_16;
+ }
+
+ /* Graphics display mode */
+ if (param->gr_disp_sel != NULL) {
+ if (*(param->gr_disp_sel) != VDC5_DISPSEL_IGNORED) {
+ *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+ *(img_synthesizer->gr_ab1) |= (uint32_t)*(param->gr_disp_sel);
+ }
+ }
+
+ /* Graphics display area */
+ if (param->gr_grc != NULL) {
+ *(img_synthesizer->gr_ab2) = (uint32_t)param->gr_grc->vs << VDC5_REG_SHIFT_16;
+ *(img_synthesizer->gr_ab2) |= (uint32_t)param->gr_grc->vw;
+ *(img_synthesizer->gr_ab3) = (uint32_t)param->gr_grc->hs << VDC5_REG_SHIFT_16;
+ *(img_synthesizer->gr_ab3) |= (uint32_t)param->gr_grc->hw;
+ }
+
+ /* Graphics register update control register (GRx_UPDATE)
+ b4 GRx_P_VEN
+ b0 GRx_IBUS_VEN */
+ *(img_synthesizer->gr_update) |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+
+ if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_GR1)) {
+ ChangeGraphicsVIN(ch, graphics_id, gr_flm_sel_tmp, graphics_enlargement);
+ }
+} /* End of function VDC5_ChangeReadProcess() */
+
+/**************************************************************************//**
+ * @brief Sets registers for data write/read start processing
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @param[in] param : Data write/read start parameter
+ * @retval None
+******************************************************************************/
+void VDC5_StartProcess (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_start_t * const param)
+{
+ uint32_t layer_id_num;
+ vdc5_resource_state_t resource_state;
+ vdc5_resource_state_t oir_resrc_st_before;
+ vdc5_resource_state_t oir_resrc_st_after;
+ const vdc5_regaddr_scaler_t * scaler;
+
+ if (param->gr_disp_sel != NULL) {
+ /* Set graphics display mode */
+ SetGraphicsDisplayMode(ch, layer_id, param->gr_disp_sel);
+ }
+
+ oir_resrc_st_before = VDC5_ShrdPrmGetOirRwProcEnabled(ch);
+
+ if (layer_id != VDC5_LAYER_ID_ALL) {
+ rw_proc_function_tbl[layer_id](ch, VDC5_ON);
+ } else {
+ for (layer_id_num = 0; layer_id_num < (uint32_t)VDC5_LAYER_ID_NUM; layer_id_num++) {
+ resource_state = VDC5_ShrdPrmGetRwProcReady(ch, (vdc5_layer_id_t)layer_id_num);
+ if (resource_state != VDC5_RESOURCE_ST_INVALID) {
+ rw_proc_function_tbl[layer_id_num](ch, VDC5_ON);
+ }
+ }
+ }
+ SetRegUpdateRwEnable(ch, layer_id);
+
+ oir_resrc_st_after = VDC5_ShrdPrmGetOirRwProcEnabled(ch);
+
+ /* OIR */
+ if ((oir_resrc_st_before == VDC5_RESOURCE_ST_INVALID) &&
+ (oir_resrc_st_after != VDC5_RESOURCE_ST_INVALID)) {
+ scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR];
+ *(scaler->scl0_frc3) |= (uint32_t)VDC5_REG_BIT16;
+ /* Register update control register (OIR_SCL0_UPDATE)
+ b8 SCL0_UPDATE */
+ *(scaler->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
+ }
+} /* End of function VDC5_StartProcess() */
+
+/**************************************************************************//**
+ * @brief Sets registers for data write/read stop processing
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @retval None
+******************************************************************************/
+void VDC5_StopProcess (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+ uint32_t layer_id_num;
+ vdc5_resource_state_t resource_state;
+ vdc5_resource_state_t oir_resrc_st_before;
+ vdc5_resource_state_t oir_resrc_st_after;
+ const vdc5_regaddr_scaler_t * scaler;
+
+ oir_resrc_st_before = VDC5_ShrdPrmGetOirRwProcEnabled(ch);
+
+ if (layer_id != VDC5_LAYER_ID_ALL) {
+ rw_proc_function_tbl[layer_id](ch, VDC5_OFF);
+ } else {
+ for (layer_id_num = 0; layer_id_num < (uint32_t)VDC5_LAYER_ID_NUM; layer_id_num++) {
+ resource_state = VDC5_ShrdPrmGetRwProcEnabled(ch, (vdc5_layer_id_t)layer_id_num);
+ if (resource_state != VDC5_RESOURCE_ST_INVALID) {
+ rw_proc_function_tbl[layer_id_num](ch, VDC5_OFF);
+ }
+ }
+ }
+ SetRegUpdateRwEnable(ch, layer_id);
+
+ oir_resrc_st_after = VDC5_ShrdPrmGetOirRwProcEnabled(ch);
+
+ /* OIR */
+ if ((oir_resrc_st_before != VDC5_RESOURCE_ST_INVALID) &&
+ (oir_resrc_st_after == VDC5_RESOURCE_ST_INVALID)) {
+ scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR];
+ *(scaler->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT16;
+ /* Register update control register (OIR_SCL0_UPDATE)
+ b8 SCL0_UPDATE */
+ *(scaler->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
+ }
+} /* End of function VDC5_StopProcess() */
+
+/**************************************************************************//**
+ * @brief Sets registers for data write/read control release processing
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @retval None
+******************************************************************************/
+void VDC5_ReleaseDataControl (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+ const vdc5_regaddr_scaler_t * scaler;
+ vdc5_resource_state_t resource_state;
+ const vdc5_regaddr_img_synthesizer_t * img_synthesizer_vin;
+
+ resource_state = VDC5_ShrdPrmGetRwProcReady(ch, VDC5_LAYER_ID_1_RD);
+ if ((layer_id == VDC5_LAYER_ID_1_RD) ||
+ ((layer_id == VDC5_LAYER_ID_ALL) && (resource_state!= VDC5_RESOURCE_ST_INVALID))) {
+ SetInitialConnection(ch);
+
+ /* Use Vsync and enable signal output from scaler 0 */
+ scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0];
+ *(scaler->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT8;
+ /* Register update control register (SC0_SCL0_UPDATE)
+ b8 SCL0_UPDATE */
+ *(scaler->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
+
+ scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1];
+ *(scaler->scl0_frc3) |= (uint32_t)VDC5_REG_BIT8;
+ /* Register update control register (SC1_SCL0_UPDATE)
+ b8 SCL0_UPDATE */
+ *(scaler->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
+
+ /* Initialize the color matrix in the image quality improver (scaler 1 output) */
+ SetImgQaImproverColorMtx(ch, VDC5_GR_TYPE_GR1, VDC5_COLOR_SPACE_GBR);
+ }
+
+ resource_state = VDC5_ShrdPrmGetRwProcReady(ch, VDC5_LAYER_ID_0_RD);
+ if ((layer_id == VDC5_LAYER_ID_0_RD) ||
+ ((layer_id == VDC5_LAYER_ID_ALL) && (resource_state!= VDC5_RESOURCE_ST_INVALID))) {
+ img_synthesizer_vin = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_VIN];
+
+ /* Turns off alpha blending in a rectangular area */
+ *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_BIT12;
+ /* Selection of lower-layer plane in scaler, graphics 1 is used as lower-layer graphics. */
+ *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
+ /* Graphics display mode in VIN */
+ *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+ *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+ /* Disable fade-in and fade-out */
+ *(img_synthesizer_vin->gr_ab6) &= (uint32_t)~VDC5_REG_MASK_0X01FF00FF;
+ /* Set the initial alpha value to '255' */
+ *(img_synthesizer_vin->gr_ab7) |= (uint32_t)VDC5_REG_MASK_0X00FF0000;
+
+ /* Graphics register update control register (GR_VIN_UPDATE)
+ b8 GR_VIN_UPDATE
+ b4 GR_VIN_P_VEN */
+ *(img_synthesizer_vin->gr_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+ }
+} /* End of function VDC5_ReleaseDataControl() */
+
+/**************************************************************************//**
+ * @brief Sets registers for noise reduction
+ * @param[in] ch : Channel
+ * @param[in] nr1d_on : Noise reduction ON/OFF setting
+ * @param[in] param : Noise reduction setup parameter
+ * @retval None
+******************************************************************************/
+void VDC5_VideoNoiseReduction (
+ const vdc5_channel_t ch,
+ const vdc5_onoff_t nr1d_on,
+ const vdc5_noise_reduction_t * const param)
+{
+ const vdc5_regaddr_input_ctrl_t * input_ctrl;
+ const vdc5_nr_param_t * nr_param;
+
+ input_ctrl = &vdc5_regaddr_input_ctrl[ch];
+
+ if (param != NULL) {
+ /* Y/G signal noise reduction parameter */
+ nr_param = ¶m->y;
+ *(input_ctrl->imgcnt_nr_cnt0) &= (uint32_t)~VDC5_REG_MASK_0X00007F33;
+ /* Maximum value of coring (absolute value) */
+ *(input_ctrl->imgcnt_nr_cnt0) |= nr_param->nr1d_th << VDC5_REG_SHIFT_8;
+ /* TAP select */
+ *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)nr_param->nr1d_tap << VDC5_REG_SHIFT_4;
+ /* Noise reduction gain adjustment */
+ *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)nr_param->nr1d_gain;
+
+ /* Cb/B signal noise reduction parameter */
+ nr_param = ¶m->cb;
+ /* Maximum value of coring (absolute value) */
+ *(input_ctrl->imgcnt_nr_cnt1) = nr_param->nr1d_th << VDC5_REG_SHIFT_24;
+ /* TAP select */
+ *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_tap << VDC5_REG_SHIFT_20;
+ /* Noise reduction gain adjustment */
+ *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_gain << VDC5_REG_SHIFT_16;
+
+ /* Cr/R signal noise reduction parameter */
+ nr_param = ¶m->cr;
+ /* Maximum value of coring (absolute value) */
+ *(input_ctrl->imgcnt_nr_cnt1) |= nr_param->nr1d_th << VDC5_REG_SHIFT_8;
+ /* TAP select */
+ *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_tap << VDC5_REG_SHIFT_4;
+ /* Noise reduction gain adjustment */
+ *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_gain;
+ }
+
+ if (nr1d_on == VDC5_OFF) {
+ *(input_ctrl->imgcnt_nr_cnt0) &= (uint32_t)~VDC5_REG_BIT16;
+ } else {
+ *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)VDC5_REG_BIT16;
+ }
+
+ /* Register update control register (IMGCNT_UPDATE)
+ b0 IMGCNT_VEN */
+ *(input_ctrl->imgcnt_update) |= (uint32_t)VDC5_REG_BIT0;
+
+} /* End of function VDC5_VideoNoiseReduction() */
+
+/**************************************************************************//**
+ * @brief Sets registers for color matrix
+ * @param[in] ch : Channel
+ * @param[in] param : Color matrix setup parameter
+ * @retval None
+******************************************************************************/
+void VDC5_ImageColorMatrix (const vdc5_channel_t ch, const vdc5_color_matrix_t * const param)
+{
+ SetColorMatrix(param->mtx_mode, param->offset, param->gain, &vdc5_regaddr_color_matrix[ch][param->module]);
+} /* End of function VDC5_ImageColorMatrix() */
+
+/**************************************************************************//**
+ * @brief Sets registers for image enhancement processing
+ * @param[in] ch : Channel
+ * @param[in] imgimprv_id : Image quality improver ID
+ * @param[in] shp_h_on : Sharpness ON/OFF setting
+ * @param[in] sharp_param : Sharpness setup parameter
+ * @param[in] lti_h_on : LTI ON/OFF setting
+ * @param[in] lti_param : LTI setup parameter
+ * @param[in] enh_area : Enhancer-enabled area setup parameter
+ * @retval None
+******************************************************************************/
+void VDC5_ImageEnhancement (
+ const vdc5_channel_t ch,
+ const vdc5_imgimprv_id_t imgimprv_id,
+ const vdc5_onoff_t shp_h_on,
+ const vdc5_enhance_sharp_t * const sharp_param,
+ const vdc5_onoff_t lti_h_on,
+ const vdc5_enhance_lti_t * const lti_param,
+ const vdc5_period_rect_t * const enh_area)
+{
+ const vdc5_regaddr_img_qlty_imp_t * img_qlty_imp;
+
+ img_qlty_imp = &vdc5_regaddr_img_qlty_imp[ch][imgimprv_id];
+
+ /* Sharpness */
+ SetImageEnhancementSharpness(shp_h_on, sharp_param, img_qlty_imp);
+
+ /* LTI */
+ SetImageEnhancementLti(lti_h_on, lti_param, img_qlty_imp);
+
+ /* Enhancer area */
+ if (enh_area != NULL) {
+ *(img_qlty_imp->adj_enh_tim2) = (uint32_t)enh_area->vs << VDC5_REG_SHIFT_16;
+ *(img_qlty_imp->adj_enh_tim2) |= (uint32_t)enh_area->vw;
+ *(img_qlty_imp->adj_enh_tim3) = (uint32_t)enh_area->hs << VDC5_REG_SHIFT_16;
+ *(img_qlty_imp->adj_enh_tim3) |= (uint32_t)enh_area->hw;
+ }
+
+ /* Register update control register (ADJx_UPDATE)
+ b0 ADJx_VEN */
+ *(img_qlty_imp->adj_update) |= (uint32_t)VDC5_REG_BIT0;
+
+} /* End of function VDC5_ImageEnhancement() */
+
+/**************************************************************************//**
+ * @brief Sets registers for black stretch
+ * @param[in] ch : Channel
+ * @param[in] imgimprv_id : Image quality improver ID
+ * @param[in] bkstr_on : Black stretch ON/OFF setting
+ * @param[in] param : Black stretch setup parameter
+ * @retval None
+******************************************************************************/
+void VDC5_ImageBlackStretch (
+ const vdc5_channel_t ch,
+ const vdc5_imgimprv_id_t imgimprv_id,
+ const vdc5_onoff_t bkstr_on,
+ const vdc5_black_t * const param)
+{
+ const vdc5_regaddr_img_qlty_imp_t * img_qlty_imp;
+
+ img_qlty_imp = &vdc5_regaddr_img_qlty_imp[ch][imgimprv_id];
+
+ if (param != NULL) {
+ /* Black stretch start point */
+ *(img_qlty_imp->adj_bkstr_set) = (uint32_t)((uint32_t)param->bkstr_st << VDC5_REG_SHIFT_20);
+ /* Black stretch depth */
+ *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)((uint32_t)param->bkstr_d << VDC5_REG_SHIFT_16);
+ /* Black stretch time constant (T1) */
+ *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)((uint32_t)param->bkstr_t1 << VDC5_REG_SHIFT_8);
+ /* Black stretch time constant (T2) */
+ *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)param->bkstr_t2;
+ }
+
+ if (bkstr_on == VDC5_OFF) {
+ *(img_qlty_imp->adj_bkstr_set) &= (uint32_t)~VDC5_REG_BIT24;
+ } else {
+ *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)VDC5_REG_BIT24;
+ }
+
+ /* Register update control register (ADJx_UPDATE)
+ b0 ADJx_VEN */
+ *(img_qlty_imp->adj_update) |= (uint32_t)VDC5_REG_BIT0;
+
+} /* End of function VDC5_ImageBlackStretch() */
+
+/**************************************************************************//**
+ * @brief Sets registers for alpha blending
+ * @param[in] ch : Channel
+ * @param[in] graphics_id : Graphics type ID
+ * @param[in] param : Alpha blending setup parameter
+ * @retval None
+******************************************************************************/
+void VDC5_AlphaBlending (
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_alpha_blending_t * const param)
+{
+ const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+
+ img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+ /* Alpha signal of the ARGB1555/ARGB5551 format */
+ if (param->alpha_1bit != NULL) {
+ *(img_synthesizer->gr_ab10) &= (uint32_t)~VDC5_REG_MASK_0XFF000000;
+ *(img_synthesizer->gr_ab10) |= (uint32_t)param->alpha_1bit->gr_a0 << VDC5_REG_SHIFT_24;
+ *(img_synthesizer->gr_ab11) &= (uint32_t)~VDC5_REG_MASK_0XFF000000;
+ *(img_synthesizer->gr_ab11) |= (uint32_t)param->alpha_1bit->gr_a1 << VDC5_REG_SHIFT_24;
+ }
+
+ /* Premultiplication processing at alpha blending in one-pixel */
+ if (param->alpha_pixel != NULL) {
+ if (param->alpha_pixel->gr_acalc_md == VDC5_OFF) {
+ *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_BIT14;
+ } else {
+ *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT14;
+ }
+ }
+
+ /* Graphics register update control register (GRx_UPDATE)
+ b4 GRx_P_VEN */
+ *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+
+} /* End of function VDC5_AlphaBlending() */
+
+/**************************************************************************//**
+ * @brief Sets registers for rectangle alpha blending
+ * @param[in] ch : Channel
+ * @param[in] graphics_id : Graphics type ID
+ * @param[in] gr_arc_on : ON/OFF setting for alpha blending in a rectangular area
+ * @param[in] param : Setup parameter for alpha blending in a rectangular area
+ * @retval None
+******************************************************************************/
+void VDC5_AlphaBlendingRect (
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_onoff_t gr_arc_on,
+ const vdc5_alpha_blending_rect_t * const param)
+{
+ const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+ const vdc5_alpha_rect_t * alpha_rect_tmp;
+ uint32_t arc_coef;
+
+ img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+ /* Alpha blending on/off control in a rectangular area */
+ if (gr_arc_on == VDC5_OFF) {
+ *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_BIT12;
+ } else {
+ *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT12;
+ }
+
+ if (param != NULL) {
+ /* Selection of lower-layer plane in scaler */
+ if (param->scl_und_sel != NULL) {
+ SetUndSel(ch, param->scl_und_sel->gr_vin_scl_und_sel);
+ }
+ /* Rectangular area subjected to alpha blending */
+ SetAlphaRectArea(param->gr_arc, img_synthesizer);
+
+ /* Alpha blending in a rectangular area */
+ alpha_rect_tmp = param->alpha_rect;
+ if (alpha_rect_tmp != NULL) {
+ if (graphics_id != VDC5_GR_TYPE_VIN) {
+ /* Multiplication processing with current alpha at alpha blending in a rectangular area (on/off) */
+ if (alpha_rect_tmp->gr_arc_mul == VDC5_OFF) {
+ *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_BIT15;
+ } else {
+ *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT15;
+ }
+ }
+ /* Alpha coefficient for alpha blending in a rectangular area (-255 to 255) */
+ if (alpha_rect_tmp->gr_arc_coef < 0) {
+ arc_coef = (uint32_t)(alpha_rect_tmp->gr_arc_coef * (-1)); /* Conversion into absolute value */
+ /* Subtraction of the alpha coefficient */
+ *(img_synthesizer->gr_ab6) = (uint32_t)VDC5_REG_BIT24;
+ } else {
+ arc_coef = (uint32_t)alpha_rect_tmp->gr_arc_coef;
+ /* Addition of the alpha coefficient */
+ *(img_synthesizer->gr_ab6) = (uint32_t)0x00000000u;
+ }
+ *(img_synthesizer->gr_ab6) |= arc_coef << VDC5_REG_SHIFT_16;
+ /* Frame rate for alpha blending in a rectangular area (gr_arc_rate + 1) */
+ *(img_synthesizer->gr_ab6) |= (uint32_t)alpha_rect_tmp->gr_arc_rate;
+ /* Initial alpha value for alpha blending in a rectangular area */
+ *(img_synthesizer->gr_ab7) &= (uint32_t)~VDC5_REG_MASK_0X00FF0000;
+ *(img_synthesizer->gr_ab7) |= (uint32_t)alpha_rect_tmp->gr_arc_def << VDC5_REG_SHIFT_16;
+ }
+ }
+ /* Graphics register update control register (GRx_UPDATE)
+ b4 GRx_P_VEN */
+ *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+
+} /* End of function VDC5_AlphaBlending() */
+
+/**************************************************************************//**
+ * @brief Sets registers for chroma-key
+ * @param[in] ch : Channel
+ * @param[in] graphics_id : Graphics type ID
+ * @param[in] gr_ck_on : Chroma-key ON/OFF setting
+ * @param[in] param : Chroma-key setup parameter
+ * @retval None
+******************************************************************************/
+void VDC5_Chromakey (
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_onoff_t gr_ck_on,
+ const vdc5_chromakey_t * const param)
+{
+ vdc5_gr_format_t gr_format_tmp;
+ const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+
+ img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+ if (param != NULL) {
+ gr_format_tmp = VDC5_ShrdPrmGetGraphicsFormat(ch, graphics_id);
+ if ((gr_format_tmp == VDC5_GR_FORMAT_CLUT1) ||
+ (gr_format_tmp == VDC5_GR_FORMAT_CLUT4) ||
+ (gr_format_tmp == VDC5_GR_FORMAT_CLUT8)) {
+ *(img_synthesizer->gr_ab8) = (uint32_t)(param->ck_color << VDC5_REG_SHIFT_24);
+ *(img_synthesizer->gr_ab9) = ColorConversionIntoAgbr(param->rep_color & VDC5_REG_RGB_24BIT_MASK);
+ } else {
+ /* Color conversion from gr_format_tmp into RGB888 format */
+ *(img_synthesizer->gr_ab8) = ColorConversion(gr_format_tmp, param->ck_color);
+ *(img_synthesizer->gr_ab9) = ColorConversion(gr_format_tmp, param->rep_color);
+ }
+ if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_OIR)) {
+ /* Alpha value is set to 255. */
+ *(img_synthesizer->gr_ab9) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+ } else {
+ *(img_synthesizer->gr_ab9) |= (uint32_t)param->rep_alpha << VDC5_REG_SHIFT_24;
+ }
+ }
+
+ if (gr_ck_on == VDC5_OFF) {
+ *(img_synthesizer->gr_ab7) &= (uint32_t)~VDC5_REG_BIT0;
+ } else {
+ *(img_synthesizer->gr_ab7) |= (uint32_t)VDC5_REG_BIT0;
+ }
+
+ /* Graphics register update control register (GRx_UPDATE)
+ b4 GRx_P_VEN */
+ *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+
+} /* End of function VDC5_Chromakey() */
+
+/**************************************************************************//**
+ * @brief Sets registers for CLUT
+ * @param[in] ch : Channel
+ * @param[in] graphics_id : Graphics type ID
+ * @param[in] param : CLUT setup parameter
+ * @retval None
+******************************************************************************/
+void VDC5_CLUT (const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id, const vdc5_clut_t * const param)
+{
+ vdc5_gr_format_t gr_format_tmp;
+ const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+
+ img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+ gr_format_tmp = VDC5_ShrdPrmGetGraphicsFormat(ch, graphics_id);
+ if (gr_format_tmp == VDC5_GR_FORMAT_CLUT1) {
+ if (param->color_num == ((uint32_t)1u)) {
+ *(img_synthesizer->gr_ab10) = ColorConversionIntoAgbr(param->clut[0]);
+ if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_OIR)) {
+ /* Alpha value is set to 255. */
+ *(img_synthesizer->gr_ab10) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+ }
+ } else {
+ *(img_synthesizer->gr_ab10) = ColorConversionIntoAgbr(param->clut[0]);
+ *(img_synthesizer->gr_ab11) = ColorConversionIntoAgbr(param->clut[1]);
+ if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_OIR)) {
+ /* Alpha value is set to 255. */
+ *(img_synthesizer->gr_ab10) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+ *(img_synthesizer->gr_ab11) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+ }
+ }
+ } else { /* CLUT4 or CLUT8 */
+ Set_Clut(param, vdc5_regaddr_clut[ch][graphics_id]);
+
+ /* CLUT table control register (GRx_CLUT)
+ b16 GRx_CLT_SEL - CLUT table select signal - XOR, flip signal */
+ *(img_synthesizer->gr_clut) ^= (uint32_t)VDC5_REG_BIT16;
+ }
+ /* Graphics register update control register (GRx_UPDATE)
+ b4 GRx_P_VEN */
+ *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+
+} /* End of function VDC5_CLUT() */
+
+/**************************************************************************//**
+ * @brief Sets registers for display calibration
+ * @param[in] ch : Channel
+ * @param[in] param : Display calibration parameter
+ * @retval None
+******************************************************************************/
+void VDC5_DisplayCalibration (const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param)
+{
+ const vdc5_calibr_bright_t * bright_tmp;
+ const vdc5_calibr_contrast_t * contrast_tmp;
+ const vdc5_calibr_dither_t * panel_dither_tmp;
+ const vdc5_regaddr_output_ctrl_t * output_ctrl;
+
+ output_ctrl = &vdc5_regaddr_output_ctrl[ch];
+
+ /* Correction circuit sequence control */
+ if (param->route == VDC5_CALIBR_ROUTE_BCG) {
+ *(output_ctrl->out_clk_phase) &= (uint32_t)~VDC5_REG_BIT12;
+ } else {
+ *(output_ctrl->out_clk_phase) |= (uint32_t)VDC5_REG_BIT12;
+ }
+
+ /* Brightness (DC) adjustment */
+ bright_tmp = param->bright;
+ if (bright_tmp != NULL) {
+ *(output_ctrl->out_bright1) = (uint32_t)bright_tmp->pbrt_g;
+ *(output_ctrl->out_bright2) = (uint32_t)bright_tmp->pbrt_b << VDC5_REG_SHIFT_16;
+ *(output_ctrl->out_bright2) |= (uint32_t)bright_tmp->pbrt_r;
+ }
+
+ /* Contrast (gain) adjustment */
+ contrast_tmp = param->contrast;
+ if (contrast_tmp != NULL) {
+ *(output_ctrl->out_contrast) = (uint32_t)contrast_tmp->cont_g << VDC5_REG_SHIFT_16;
+ *(output_ctrl->out_contrast) |= (uint32_t)contrast_tmp->cont_b << VDC5_REG_SHIFT_8;
+ *(output_ctrl->out_contrast) |= (uint32_t)contrast_tmp->cont_r;
+ }
+
+ /* Panel dithering */
+ panel_dither_tmp = param->panel_dither;
+ if (panel_dither_tmp != NULL) {
+ *(output_ctrl->out_pdtha) &= (uint32_t)~VDC5_REG_MASK_0X00300000;
+ *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_sel << VDC5_REG_SHIFT_20;
+ if (panel_dither_tmp->pdth_sel == VDC5_PDTH_MD_2X2) {
+ *(output_ctrl->out_pdtha) &= (uint32_t)~VDC5_REG_MASK_0X00003333;
+ *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pa << VDC5_REG_SHIFT_12;
+ *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pb << VDC5_REG_SHIFT_8;
+ *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pc << VDC5_REG_SHIFT_4;
+ *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pd;
+ }
+ }
+
+ /* Register update control register (OUT_UPDATE)
+ b0 OUTCNT_VEN */
+ *(output_ctrl->out_update) |= (uint32_t)VDC5_REG_BIT0;
+
+} /* End of function VDC5_DisplayCalibration() */
+
+/**************************************************************************//**
+ * @brief Sets registers for gamma correction
+ * @param[in] ch : Channel
+ * @param[in] gam_on : Gamma correction ON/OFF setting
+ * @param[in] param : Gamma correction setup parameter
+ * @retval None
+******************************************************************************/
+void VDC5_GammaCorrection (
+ const vdc5_channel_t ch,
+ const vdc5_onoff_t gam_on,
+ const vdc5_gamma_correction_t * const param)
+{
+ const vdc5_regaddr_gamma_t * gamma;
+
+ gamma = &vdc5_regaddr_gamma[ch];
+
+ /* Gamma correction on/off control */
+ *(gamma->gam_sw) = (gam_on == VDC5_OFF) ? 0x0000u : 0x0001u;
+
+ if (param != NULL) {
+ /* Start threshold of area 1 to 31 of G signal */
+ Set_StartThreshold_Gamma(param->gam_g_th, gamma->gam_g_area);
+ /* Gain adjustment of area 0 to 31 of G signal */
+ Set_GainAdjustment_Gamma(param->gam_g_gain, gamma->gam_g_lut);
+ /* Register update control register G (GAM_G_UPDATE)
+ b0 GAM_G_VEN */
+ *(gamma->gam_g_update) |= (uint32_t)VDC5_REG_BIT0;
+
+ /* Start threshold of area 1 to 31 of B signal */
+ Set_StartThreshold_Gamma(param->gam_b_th, gamma->gam_b_area);
+ /* Gain adjustment of area 0 to 31 of B signal */
+ Set_GainAdjustment_Gamma(param->gam_b_gain, gamma->gam_b_lut);
+ /* Register update control register B (GAM_B_UPDATE)
+ b0 GAM_B_VEN */
+ *(gamma->gam_b_update) |= (uint32_t)VDC5_REG_BIT0;
+
+ /* Start threshold of area 1 to 31 of R signal */
+ Set_StartThreshold_Gamma(param->gam_r_th, gamma->gam_r_area);
+ /* Gain adjustment of area 0 to 31 of R signal */
+ Set_GainAdjustment_Gamma(param->gam_r_gain, gamma->gam_r_lut);
+ /* Register update control register R (GAM_R_UPDATE)
+ b0 GAM_R_VEN */
+ *(gamma->gam_r_update) |= (uint32_t)VDC5_REG_BIT0;
+ }
+} /* End of function VDC5_GammaCorrection() */
+
+/******************************************************************************
+Local Functions
+******************************************************************************/
+/**************************************************************************//**
+ * @brief Sets external input video signal
+ * @param[in] ext_sig_tmp : External input signal parameter
+ * @param[in] input_ctrl : Input controller registers
+ * @retval None
+******************************************************************************/
+static void SetVideoExternalInput (
+ const vdc5_ext_in_sig_t * const ext_sig_tmp,
+ const vdc5_regaddr_input_ctrl_t * const input_ctrl)
+{
+ *(input_ctrl->inp_sel_cnt) &= (uint32_t)~VDC5_REG_MASK_0X00007111;
+ /* External input format select */
+ if (ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_YCBCR444) {
+ *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_EXTIN_FORMAT_RGB888 << VDC5_REG_SHIFT_12;
+ } else {
+ *(input_ctrl->inp_sel_cnt) |= (uint32_t)ext_sig_tmp->inp_format << VDC5_REG_SHIFT_12;
+ }
+ /* Clock edge select for capturing external input video image signals */
+ if (ext_sig_tmp->inp_pxd_edge != VDC5_EDGE_RISING) {
+ *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_REG_BIT8;
+ }
+ /* Clock edge select for capturing external input Vsync signals */
+ if (ext_sig_tmp->inp_vs_edge != VDC5_EDGE_RISING) {
+ *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_REG_BIT4;
+ }
+ /* Clock edge select for capturing external input Hsync signals */
+ if (ext_sig_tmp->inp_hs_edge != VDC5_EDGE_RISING) {
+ *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_REG_BIT0;
+ }
+
+ *(input_ctrl->inp_ext_sync_cnt) &= (uint32_t)~VDC5_REG_MASK_0X11110113;
+ /* External input bit endian change on/off control */
+ if (ext_sig_tmp->inp_endian_on != VDC5_OFF) {
+ *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT28;
+ }
+ /* External input B/R signal swap on/off control */
+ if (ext_sig_tmp->inp_swap_on != VDC5_OFF) {
+ *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT24;
+ }
+ /* External input Vsync signal DV_VSYNC inversion control */
+ if (ext_sig_tmp->inp_vs_inv != VDC5_SIG_POL_NOT_INVERTED) {
+ *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT20;
+ }
+ /* External input Hsync signal DV_HSYNC inversion control */
+ if (ext_sig_tmp->inp_hs_inv != VDC5_SIG_POL_NOT_INVERTED) {
+ *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT16;
+ }
+ /* Reference select for external input BT.656 Hsync signal */
+ if (ext_sig_tmp->inp_h_edge_sel != VDC5_EXTIN_REF_H_EAV) {
+ *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT8;
+ }
+ /* Number of lines for BT.656 external input */
+ if (ext_sig_tmp->inp_f525_625 != VDC5_EXTIN_LINE_525) {
+ *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT4;
+ }
+ /* Y/Cb/Y/Cr data string start timing to Hsync reference */
+ *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)ext_sig_tmp->inp_h_pos;
+} /* End of function SetVideoExternalInput() */
+
+/**************************************************************************//**
+ * @brief Initializes cascaded connection
+ * @param[in] ch : Channel
+ * @retval None
+******************************************************************************/
+static void SetInitialConnection (const vdc5_channel_t ch)
+{
+ const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+
+ img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
+
+ /* Cascade ON */
+ *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT28;
+ /* Graphics register update control register (GR1_UPDATE)
+ b8 GR1_UPDATE */
+ *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT8;
+
+ VDC5_ShrdPrmSetCascade(ch, VDC5_ON);
+
+ img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_VIN];
+
+ /* Turns off alpha blending in a rectangular area */
+ *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_BIT12;
+ /* Selection of lower-layer plane in scaler, graphics 1 is used as lower-layer graphics. */
+ *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
+ /* Graphics display mode in VIN */
+ *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+ *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+ /* Disable fade-in and fade-out */
+ *(img_synthesizer->gr_ab6) &= (uint32_t)~VDC5_REG_MASK_0X01FF00FF;
+ /* Set the initial alpha value to '255' */
+ *(img_synthesizer->gr_ab7) |= (uint32_t)VDC5_REG_MASK_0X00FF0000;
+ /* Graphics register update control register (GR_VIN_UPDATE)
+ b8 GR_VIN_UPDATE
+ b4 GR_VIN_P_VEN */
+ *(img_synthesizer->gr_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+
+} /* End of function SetInitialConnection() */
+
+/**************************************************************************//**
+ * @brief Sets background color for graphics
+ * @param[in] ch : Channel
+ * @retval None
+******************************************************************************/
+static void SetGrapicsBackgroundColor (const vdc5_channel_t ch)
+{
+ uint32_t bg_color_tmp;
+ uint32_t bg_color_conv;
+ volatile uint32_t * bg_color_reg;
+ volatile uint32_t * update_reg;
+ vdc5_graphics_type_t gr_type_index;
+
+ /* Background color in 24-bit RGB color format or CrYCb format */
+ bg_color_tmp = VDC5_ShrdPrmGetBgColor(ch, VDC5_COLOR_SPACE_GBR);
+ /* Conversion from RGB into GBR / from CrYCb into YCbCr */
+ bg_color_conv = ColorConversionIntoAgbr(bg_color_tmp);
+ bg_color_conv &= (uint32_t)VDC5_REG_RGB_24BIT_MASK;
+
+ /* GR2, GR3, VIN, OIR */
+ for (gr_type_index = VDC5_GR_TYPE_GR2; gr_type_index < VDC5_GR_TYPE_NUM; gr_type_index++) {
+ /* Background color in GBR format (GRx_BASE) */
+ bg_color_reg = vdc5_regaddr_img_synthesizer[ch][gr_type_index].gr_base;
+ *bg_color_reg = bg_color_conv;
+ /* Graphics register update control register (GRx_UPDATE)
+ b4 GRx_P_VEN */
+ update_reg = vdc5_regaddr_img_synthesizer[ch][gr_type_index].gr_update;
+ *update_reg |= (uint32_t)VDC5_REG_BIT4;
+ }
+ /* For OIR */
+ /* Background color in RGB format (OIR_SCL0_OVR1) */
+ bg_color_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR].scl0_ovr1;
+ *bg_color_reg = bg_color_tmp;
+ /* Register update control register (OIR_SCL0_UPDATE)
+ b4 SCL0_VEN_B */
+ update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR].scl0_update;
+ *update_reg |= (uint32_t)VDC5_REG_BIT4;
+} /* End of function SetGrapicsBackgroundColor() */
+
+/**************************************************************************//**
+ * @brief Sets background color for scaler 0, scaler 1, graphics 0, and graphics 1
+ *
+ * Description:<br>
+ * This function should be called only when graphics 0 or graphics 1 is selected.
+ * @param[in] ch : Channel
+ * @param[in] graphics_id : Graphics type ID
+ * @param[in] color_space : Color space (GBR or YCbCr)
+ * @retval None
+******************************************************************************/
+static void SetScalerBackgroundColor (
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_color_space_t color_space)
+{
+ volatile uint32_t * scl0_update_reg;
+ volatile uint32_t * scl0_ovr1_reg;
+ volatile uint32_t * gr_base_reg;
+ volatile uint32_t * gr_update_reg;
+ uint32_t bg_color_tmp;
+ uint32_t bg_color_conv;
+
+ if (graphics_id == VDC5_GR_TYPE_GR0) {
+ scl0_ovr1_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl0_ovr1;
+ scl0_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl0_update;
+ gr_base_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0].gr_base;
+ gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0].gr_update;
+ } else {
+ /* graphics_id == VDC5_GR_TYPE_GR1 */
+ scl0_ovr1_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl0_ovr1;
+ scl0_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl0_update;
+ gr_base_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1].gr_base;
+ gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1].gr_update;
+ }
+ /* Background color in 24-bit RGB color format or CrYCb format */
+ bg_color_tmp = VDC5_ShrdPrmGetBgColor(ch, color_space);
+ /* Conversion from RGB into GBR / from CrYCb into YCbCr */
+ bg_color_conv = ColorConversionIntoAgbr(bg_color_tmp);
+ bg_color_conv &= (uint32_t)VDC5_REG_RGB_24BIT_MASK;
+
+ /* Background color in RGB format or CrYCb format */
+ *scl0_ovr1_reg = bg_color_tmp;
+ /* Register update control register
+ b4 SCL0_VEN_B */
+ *scl0_update_reg |= (uint32_t)VDC5_REG_BIT4;
+
+ /* Background color in GBR format or YCbCr format */
+ *gr_base_reg = bg_color_conv;
+ /* Graphics register update control register
+ b4 GRx_P_VEN */
+ *gr_update_reg |= (uint32_t)VDC5_REG_BIT4;
+} /* End of function SetScalerBackgroundColor() */
+
+/**************************************************************************//**
+ * @brief Sets LCD TCON - STVA/VS
+ * @param[in] lcd_tcon : LCD TCON timing signal parameter
+ * @param[in] output_ctrl : Output controller registers
+ * @retval None
+******************************************************************************/
+static void SetLcdTcon_STVA_VS (
+ const vdc5_lcd_tcon_timing_t * const lcd_tcon,
+ const vdc5_regaddr_output_ctrl_t * const output_ctrl)
+{
+ /* Signal pulse start position */
+ *(output_ctrl->tcon_tim_stva1) = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+ /* Pulse width */
+ *(output_ctrl->tcon_tim_stva1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+ /* Polarity inversion control of signal */
+ if (lcd_tcon->tcon_inv == VDC5_SIG_POL_NOT_INVERTED) {
+ *(output_ctrl->tcon_tim_stva2) &= (uint32_t)~VDC5_REG_BIT4;
+ } else {
+ *(output_ctrl->tcon_tim_stva2) |= (uint32_t)VDC5_REG_BIT4;
+ }
+} /* End of function SetLcdTcon_STVA_VS() */
+
+/**************************************************************************//**
+ * @brief Sets LCD TCON - STVB/VE
+ * @param[in] lcd_tcon : LCD TCON timing signal parameter
+ * @param[in] output_ctrl : Output controller registers
+ * @retval None
+******************************************************************************/
+static void SetLcdTcon_STVB_VE (
+ const vdc5_lcd_tcon_timing_t * const lcd_tcon,
+ const vdc5_regaddr_output_ctrl_t * const output_ctrl)
+{
+ /* Signal pulse start position */
+ *(output_ctrl->tcon_tim_stvb1) = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+ /* Pulse width */
+ *(output_ctrl->tcon_tim_stvb1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+ /* Polarity inversion control of signal */
+ if (lcd_tcon->tcon_inv == VDC5_SIG_POL_NOT_INVERTED) {
+ *(output_ctrl->tcon_tim_stvb2) &= (uint32_t)~VDC5_REG_BIT4;
+ } else {
+ *(output_ctrl->tcon_tim_stvb2) |= (uint32_t)VDC5_REG_BIT4;
+ }
+} /* End of function SetLcdTcon_STVB_VE() */
+
+/**************************************************************************//**
+ * @brief Sets LCD TCON - STH/HS
+ * @param[in] lcd_tcon : LCD TCON timing signal parameter
+ * @param[in] output_ctrl : Output controller registers
+ * @retval None
+******************************************************************************/
+static void SetLcdTcon_STH_HS (
+ const vdc5_lcd_tcon_timing_t * const lcd_tcon,
+ const vdc5_regaddr_output_ctrl_t * const output_ctrl)
+{
+ /* Signal pulse start position */
+ *(output_ctrl->tcon_tim_sth1) = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+ /* Pulse width */
+ *(output_ctrl->tcon_tim_sth1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+ *(output_ctrl->tcon_tim_sth2) &= (uint32_t)~VDC5_REG_MASK_0X00000110;
+ /* Signal operating reference select */
+ if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC) {
+ *(output_ctrl->tcon_tim_sth2) |= (uint32_t)VDC5_REG_BIT8;
+ }
+ /* Polarity inversion control of signal */
+ if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED) {
+ *(output_ctrl->tcon_tim_sth2) |= (uint32_t)VDC5_REG_BIT4;
+ }
+} /* End of function SetLcdTcon_STH_HS() */
+
+/**************************************************************************//**
+ * @brief Sets LCD TCON - STB/HE
+ * @param[in] lcd_tcon : LCD TCON timing signal parameter
+ * @param[in] output_ctrl : Output controller registers
+ * @retval None
+******************************************************************************/
+static void SetLcdTcon_STB_HE (
+ const vdc5_lcd_tcon_timing_t * const lcd_tcon,
+ const vdc5_regaddr_output_ctrl_t * const output_ctrl)
+{
+ /* Signal pulse start position */
+ *(output_ctrl->tcon_tim_stb1) = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+ /* Pulse width */
+ *(output_ctrl->tcon_tim_stb1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+ *(output_ctrl->tcon_tim_stb2) &= (uint32_t)~VDC5_REG_MASK_0X00000110;
+ /* Signal operating reference select */
+ if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC) {
+ *(output_ctrl->tcon_tim_stb2) |= (uint32_t)VDC5_REG_BIT8;
+ }
+ /* Polarity inversion control of signal */
+ if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED) {
+ *(output_ctrl->tcon_tim_stb2) |= (uint32_t)VDC5_REG_BIT4;
+ }
+} /* End of function SetLcdTcon_STB_HE() */
+
+/**************************************************************************//**
+ * @brief Sets LCD TCON - CPV/GCK
+ * @param[in] lcd_tcon : LCD TCON timing signal parameter
+ * @param[in] output_ctrl : Output controller registers
+ * @retval None
+******************************************************************************/
+static void SetLcdTcon_CPV_GCK (
+ const vdc5_lcd_tcon_timing_t * const lcd_tcon,
+ const vdc5_regaddr_output_ctrl_t * const output_ctrl)
+{
+ /* Signal pulse start position */
+ *(output_ctrl->tcon_tim_cpv1) = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+ /* Pulse width */
+ *(output_ctrl->tcon_tim_cpv1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+ *(output_ctrl->tcon_tim_cpv2) &= (uint32_t)~VDC5_REG_MASK_0X00000110;
+ /* Signal operating reference select */
+ if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC) {
+ *(output_ctrl->tcon_tim_cpv2) |= (uint32_t)VDC5_REG_BIT8;
+ }
+ /* Polarity inversion control of signal */
+ if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED) {
+ *(output_ctrl->tcon_tim_cpv2) |= (uint32_t)VDC5_REG_BIT4;
+ }
+} /* End of function SetLcdTcon_CPV_GCK() */
+
+/**************************************************************************//**
+ * @brief Sets LCD TCON - POLA
+ * @param[in] lcd_tcon : LCD TCON timing signal parameter
+ * @param[in] output_ctrl : Output controller registers
+ * @retval None
+******************************************************************************/
+static void SetLcdTcon_POLA (
+ const vdc5_lcd_tcon_timing_t * const lcd_tcon,
+ const vdc5_regaddr_output_ctrl_t * const output_ctrl)
+{
+ /* Signal pulse start position */
+ *(output_ctrl->tcon_tim_pola1) = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+ /* Pulse width */
+ *(output_ctrl->tcon_tim_pola1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+ *(output_ctrl->tcon_tim_pola2) &= (uint32_t)~VDC5_REG_MASK_0X00003110;
+ /* POLA/POLB signal generation mode select */
+ *(output_ctrl->tcon_tim_pola2) |= (uint32_t)lcd_tcon->tcon_md << VDC5_REG_SHIFT_12;
+ /* Signal operating reference select */
+ if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC) {
+ *(output_ctrl->tcon_tim_pola2) |= (uint32_t)VDC5_REG_BIT8;
+ }
+ /* Polarity inversion control of signal */
+ if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED) {
+ *(output_ctrl->tcon_tim_pola2) |= (uint32_t)VDC5_REG_BIT4;
+ }
+} /* End of function SetLcdTcon_POLA() */
+
+/**************************************************************************//**
+ * @brief Sets LCD TCON - POLB
+ * @param[in] lcd_tcon : LCD TCON timing signal parameter
+ * @param[in] output_ctrl : Output controller registers
+ * @retval None
+******************************************************************************/
+static void SetLcdTcon_POLB (
+ const vdc5_lcd_tcon_timing_t * const lcd_tcon,
+ const vdc5_regaddr_output_ctrl_t * const output_ctrl)
+{
+ /* Signal pulse start position */
+ *(output_ctrl->tcon_tim_polb1) = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+ /* Pulse width */
+ *(output_ctrl->tcon_tim_polb1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+ *(output_ctrl->tcon_tim_polb2) &= (uint32_t)~VDC5_REG_MASK_0X00003110;
+ /* POLA/POLB signal generation mode select */
+ *(output_ctrl->tcon_tim_polb2) |= (uint32_t)lcd_tcon->tcon_md << VDC5_REG_SHIFT_12;
+ /* Signal operating reference select */
+ if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC) {
+ *(output_ctrl->tcon_tim_polb2) |= (uint32_t)VDC5_REG_BIT8;
+ }
+ /* Polarity inversion control of signal */
+ if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED) {
+ *(output_ctrl->tcon_tim_polb2) |= (uint32_t)VDC5_REG_BIT4;
+ }
+} /* End of function SetLcdTcon_POLB() */
+
+/**************************************************************************//**
+ * @brief Sets LCD TCON - DE
+ * @param[in] lcd_tcon : LCD TCON timing signal parameter
+ * @param[in] output_ctrl : Output controller registers
+ * @retval None
+******************************************************************************/
+static void SetLcdTcon_DE (
+ const vdc5_lcd_tcon_timing_t * const lcd_tcon,
+ const vdc5_regaddr_output_ctrl_t * const output_ctrl)
+{
+ /* Polarity inversion control of signal */
+ *(output_ctrl->tcon_tim_de) = (lcd_tcon->tcon_inv == VDC5_SIG_POL_NOT_INVERTED) ? (uint32_t)0u : (uint32_t)1u;
+
+} /* End of function SetLcdTcon_DE() */
+
+/**************************************************************************//**
+ * @brief Sets scaling-down
+ * @param[in] scldw_rot : Scaling-down and rotation parameter
+ * @param[in] res_inter : Field operating mode select
+ * @param[in] scaler : Scaler registers
+ * @retval None
+******************************************************************************/
+static void SetScalingDown (
+ const vdc5_scalingdown_rot_t * const scldw_rot,
+ const vdc5_res_inter_t res_inter,
+ const vdc5_regaddr_scaler_t * const scaler)
+{
+ uint32_t vw_before_scld; /* Vertical width before scaling-down */
+ uint32_t hw_before_scld; /* Horizontal width before scaling-down */
+ uint32_t vw_after_scld; /* Vertical width after scaling-down */
+ uint32_t hw_after_scld; /* Horizontal width after scaling-down */
+ uint32_t scaling_ratio;
+
+ vw_before_scld = (uint32_t)scldw_rot->res.vw;
+ hw_before_scld = (uint32_t)scldw_rot->res.hw;
+
+ vw_after_scld = (uint32_t)scldw_rot->res_out_vw;
+ hw_after_scld = (uint32_t)scldw_rot->res_out_hw;
+
+ /* Vertical scaling-down: ON, vertical scaling-up: OFF */
+ *(scaler->scl0_ds1) |= (uint32_t)VDC5_REG_BIT4;
+ *(scaler->scl0_us1) &= (uint32_t)~VDC5_REG_BIT4;
+ if (vw_before_scld > vw_after_scld) {
+ scaling_ratio = CalcScalingRatio(vw_before_scld, vw_after_scld, scldw_rot->adj_sel, VDC5_OFF);
+
+ *(scaler->scl0_ds6) = scaling_ratio;
+ } else {
+ *(scaler->scl0_ds6) = (uint32_t)SCALING_RATIO_SAME_SIZE;
+ }
+
+ /* Horizontal scaling-down */
+ if (hw_before_scld > hw_after_scld) {
+ /* ON */
+ *(scaler->scl0_ds1) |= (uint32_t)VDC5_REG_BIT0;
+
+ scaling_ratio = CalcScalingRatio(hw_before_scld, hw_after_scld, VDC5_ON, VDC5_ON);
+
+ *(scaler->scl0_ds4) &= (uint32_t)~VDC5_REG_MASK_0X0000FFFF;
+ *(scaler->scl0_ds4) |= scaling_ratio;
+ } else {
+ /* OFF */
+ *(scaler->scl0_ds1) &= (uint32_t)~VDC5_REG_BIT0;
+ }
+
+ /* Initial scaling phase */
+ *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+ *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+ if (res_inter != VDC5_RES_INTER_PROGRESSIVE) {
+ /* Top */
+ *(scaler->scl0_ds5) |= INITIAL_SCALING_PHASE << VDC5_REG_SHIFT_16;
+ }
+
+} /* End of function SetScalingDown() */
+
+/**************************************************************************//**
+ * @brief Sets scaling-up
+ * @param[in] w_read_fb : Size of the frame buffer to be read
+ * @param[in] gr_grc : Graphics display area
+ * @param[in] adj_sel : Folding handling (on/off)
+ * @param[in] ip_conversion : IP conversion on/off
+ * @param[in] res_ds_wr_md : Frame buffer writing mode for image processing
+ * @param[in] ln_off_dir : Line offset address direction of the frame buffer
+ * @param[in] scaler : Scaler registers
+ * @retval None
+******************************************************************************/
+static void SetScalingUp (
+ const vdc5_width_read_fb_t * const w_read_fb,
+ const vdc5_period_rect_t * const gr_grc,
+ const vdc5_onoff_t adj_sel,
+ const vdc5_onoff_t ip_conversion,
+ const vdc5_wr_md_t res_ds_wr_md,
+ const vdc5_gr_ln_off_dir_t ln_off_dir,
+ const vdc5_regaddr_scaler_t * const scaler)
+{
+ uint32_t w_before_scl; /* Width before scaling-up */
+ uint32_t w_after_scl; /* Width after scaling-up */
+ uint32_t scaling_ratio;
+ vdc5_onoff_t vscl_up; /* Vertical scaling-up */
+
+ vscl_up = VDC5_OFF;
+
+ /* Vertical scaling-up */
+ w_before_scl = (uint32_t)w_read_fb->in_vw;
+ w_after_scl = (uint32_t)gr_grc->vw;
+ if (w_before_scl < w_after_scl) {
+ /* Vertical scaling-down: OFF, vertical scaling-up: ON */
+ *(scaler->scl0_ds1) &= (uint32_t)~VDC5_REG_BIT4;
+ *(scaler->scl0_us1) |= (uint32_t)VDC5_REG_BIT4;
+
+ scaling_ratio = CalcScalingRatio(w_before_scl, w_after_scl, adj_sel, VDC5_OFF);
+ *(scaler->scl0_ds6) = scaling_ratio;
+
+ vscl_up = VDC5_ON;
+ } else {
+ /* Vertical scaling-up: OFF */
+ *(scaler->scl0_us1) &= (uint32_t)~VDC5_REG_BIT4;
+ }
+
+ /* Horizontal scaling-up */
+ w_before_scl = (uint32_t)w_read_fb->in_hw;
+ w_after_scl = (uint32_t)gr_grc->hw;
+ if (w_before_scl < w_after_scl) {
+ /* Horizontal scaling-up: ON */
+ *(scaler->scl0_us1) |= (uint32_t)VDC5_REG_BIT0;
+
+ scaling_ratio = CalcScalingRatio(w_before_scl, w_after_scl, adj_sel, VDC5_OFF);
+
+ *(scaler->scl0_us5) &= (uint32_t)~VDC5_REG_MASK_0X0000FFFF;
+ *(scaler->scl0_us5) |= scaling_ratio;
+ } else {
+ /* Horizontal scaling-up: OFF */
+ *(scaler->scl0_us1) &= (uint32_t)~VDC5_REG_BIT0;
+ }
+
+ /* Initial scaling phase */
+ if (ip_conversion == VDC5_OFF) {
+ *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+ *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+ } else {
+ if (vscl_up != VDC5_OFF) {
+ switch (res_ds_wr_md) {
+ case VDC5_WR_MD_ROT_90DEG:
+ *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+ *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+ /* US_HB */
+ *(scaler->scl0_us6) |= INITIAL_SCALING_PHASE;
+ break;
+ case VDC5_WR_MD_ROT_180DEG:
+ if (ln_off_dir == VDC5_GR_LN_OFF_DIR_INC) {
+ *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+ *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+ /* BTM */
+ *(scaler->scl0_ds5) |= INITIAL_SCALING_PHASE;
+ }
+ break;
+ case VDC5_WR_MD_ROT_270DEG:
+ *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+ *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+ /* US_HT */
+ *(scaler->scl0_us6) |= INITIAL_SCALING_PHASE << VDC5_REG_SHIFT_16;
+ break;
+ default: /* Normal or horizontal mirroring */
+ if (ln_off_dir == VDC5_GR_LN_OFF_DIR_DEC) {
+ *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+ *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+ /* BTM */
+ *(scaler->scl0_ds5) |= INITIAL_SCALING_PHASE;
+ }
+ break;
+ }
+ }
+ }
+} /* End of function SetScalingUp() */
+
+/**************************************************************************//**
+ * @brief Calculates scaling ratio
+ *
+ * Description:<br>
+ * In this function, the overflow in calculation is not considered.
+ * before_scl and after_scl are 11bit width, so the overflow does not occur.
+ * @param[in] before_scl : Size before scaling
+ * @param[in] after_scl : Size after scaling
+ * @param[in] adj_sel : Handling for lack of last-input pixel/line, or folding handling
+ * @param[in] round_up : Round-up on/off
+ * @retval Scaling ratio
+******************************************************************************/
+static uint32_t CalcScalingRatio (
+ const uint32_t before_scl,
+ const uint32_t after_scl,
+ const vdc5_onoff_t adj_sel,
+ const vdc5_onoff_t round_up)
+{
+ float32_t ratio;
+ float32_t sigma;
+ int32_t ratio_int;
+ uint32_t scaling_ratio;
+
+ /* When parameter checking is not performed,
+ following checks are necessary to avoid a division by zero exception and a negative number. */
+ if ((after_scl == 0u) || (after_scl == 1u)) {
+ scaling_ratio = (uint32_t)SCALING_RATIO_SAME_SIZE;
+ } else {
+ /* ratio = before_scl * 4096.0 / after_scl */
+ ratio = (float32_t)before_scl * (float32_t)SCALING_RATIO_SAME_SIZE;
+ ratio /= (float32_t)after_scl;
+
+ if (adj_sel != VDC5_OFF) {
+ sigma = ratio * ((float32_t)after_scl - (float32_t)VDC5_REG_FLOAT_1_0);
+ sigma -= ((float32_t)before_scl - (float32_t)VDC5_REG_FLOAT_1_0) * (float32_t)SCALING_RATIO_SAME_SIZE;
+ sigma /= ((float32_t)after_scl - (float32_t)VDC5_REG_FLOAT_1_0);
+ ratio -= sigma;
+ }
+
+ if (round_up == VDC5_OFF) {
+ /* Round off */
+ ratio += (float32_t)VDC5_REG_FLOAT_0_5;
+ ratio_int = (int32_t)ratio;
+ } else {
+ /* Round up */
+ ratio_int = (int32_t)ratio;
+ if ((float32_t)ratio_int < ratio) {
+ ratio_int++;
+ }
+ }
+ scaling_ratio = (uint32_t)ratio_int;
+ }
+ return scaling_ratio;
+} /* End of function CalcScalingRatio() */
+
+/**************************************************************************//**
+ * @brief Sets color matrix in the input controller
+ * @param[in] ch : Channel
+ * @param[in] scaling_id : Scaling type ID
+ * @retval None
+******************************************************************************/
+static void SetInputCntrlColorMtx (const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id)
+{
+ vdc5_channel_t channel;
+ vdc5_color_space_t color_space_input;
+ vdc5_color_space_t color_space_fb;
+ vdc5_colormtx_mode_t mtx_mode_tmp;
+ const uint16_t * offset_tmp;
+ const uint16_t * gain_tmp;
+
+ if (scaling_id == VDC5_SC_TYPE_SC0) {
+ channel = ch;
+ } else {
+ channel = (ch == VDC5_CHANNEL_0) ? VDC5_CHANNEL_1 : VDC5_CHANNEL_0;
+ }
+ color_space_input = VDC5_ShrdPrmGetColorSpace(channel);
+ color_space_fb = VDC5_ShrdPrmGetColorSpaceFbWr(ch, scaling_id);
+ /* Color matrix operating mode */
+ if (color_space_input == VDC5_COLOR_SPACE_GBR) {
+ if (color_space_fb == VDC5_COLOR_SPACE_GBR) {
+ /* GBR to GBR */
+ mtx_mode_tmp = VDC5_COLORMTX_GBR_GBR;
+ } else {
+ /* GBR to YCbCr */
+ mtx_mode_tmp = VDC5_COLORMTX_GBR_YCBCR;
+ }
+ } else {
+ if (color_space_fb == VDC5_COLOR_SPACE_GBR) {
+ /* YCbCr to GBR */
+ mtx_mode_tmp = VDC5_COLORMTX_YCBCR_GBR;
+ } else {
+ /* YCbCr to YCbCr */
+ mtx_mode_tmp = VDC5_COLORMTX_YCBCR_YCBCR;
+ }
+ }
+ /* Color matrix offset (DC) adjustment (YG, B, and R) */
+ offset_tmp = colormtx_offset_adj;
+ /* Color matrix signal gain adjustment (GG, GB, GR, BG, BB, BR, RG, RB, and RR) */
+ gain_tmp = colormtx_gain_adj[mtx_mode_tmp];
+
+ SetColorMatrix(mtx_mode_tmp, offset_tmp, gain_tmp, &vdc5_regaddr_color_matrix[channel][VDC5_COLORMTX_IMGCNT]);
+
+} /* End of function SetInputCntrlColorMtx() */
+
+/**************************************************************************//**
+ * @brief Confirms whether the graphics enlargement will occur or not
+ * @param[in] graphics_id : Graphics type ID
+ * @param[in] gr_flm_sel : Frame buffer address setting signal
+ * @param[in] w_read_fb : Size of the frame buffer to be read
+ * @param[in] gr_grc : Graphics display area
+ * @retval Graphics enlargement on/off
+******************************************************************************/
+static vdc5_onoff_t ConfirmGraphicsEnlargement (
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_gr_flm_sel_t gr_flm_sel,
+ const vdc5_width_read_fb_t * const w_read_fb,
+ const vdc5_period_rect_t * const gr_grc)
+{
+ vdc5_onoff_t graphics_enlargement;
+
+ graphics_enlargement = VDC5_OFF;
+ if (gr_flm_sel == VDC5_GR_FLM_SEL_FLM_NUM) {
+ if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_GR1)) {
+ if (((uint32_t)w_read_fb->in_vw < (uint32_t)gr_grc->vw) ||
+ ((uint32_t)w_read_fb->in_hw < (uint32_t)gr_grc->hw)) {
+ graphics_enlargement = VDC5_ON;
+ }
+ }
+ } else {
+ if (((uint32_t)w_read_fb->in_vw < (uint32_t)gr_grc->vw) || ((uint32_t)w_read_fb->in_hw < (uint32_t)gr_grc->hw)) {
+ graphics_enlargement = VDC5_ON;
+ }
+ }
+ return graphics_enlargement;
+} /* End of function ConfirmGraphicsEnlargement() */
+
+/**************************************************************************//**
+ * @brief Sets scaler for graphics
+ * @param[in] ch : Channel
+ * @param[in] graphics_id : Graphics type ID
+ * @param[in] w_read_fb : Size of the frame buffer to be read
+ * @param[in] gr_grc : Graphics display area
+ * @param[in] gr_flm_sel : Frame buffer address setting signal
+ * @param[in] gr_enlarge : Graphics enlargement on/off
+ * @retval None
+******************************************************************************/
+static void SetScalerGraphics (
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_width_read_fb_t * const w_read_fb,
+ const vdc5_period_rect_t * const gr_grc,
+ const vdc5_gr_flm_sel_t gr_flm_sel,
+ const vdc5_onoff_t gr_enlarge)
+{
+ const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+ const vdc5_regaddr_scaler_t * scaler;
+ vdc5_scaling_type_t scaling_id;
+ vdc5_res_inter_t res_inter_tmp;
+ vdc5_wr_md_t res_ds_wr_md_tmp;
+ vdc5_onoff_t adj_sel_tmp;
+ vdc5_onoff_t ip_conversion;
+ uint32_t reg_data;
+ vdc5_gr_ln_off_dir_t ln_off_dir;
+
+ if (graphics_id == VDC5_GR_TYPE_GR0) {
+ /* Scaler 0 */
+ scaling_id = VDC5_SC_TYPE_SC0;
+ } else if (graphics_id == VDC5_GR_TYPE_GR1) {
+ /* Scaler 1 */
+ scaling_id = VDC5_SC_TYPE_SC1;
+ } else {
+ /* OIR */
+ scaling_id = VDC5_SC_TYPE_OIR;
+ }
+
+ scaler = &vdc5_regaddr_scaler[ch][scaling_id];
+
+ if ((gr_flm_sel == VDC5_GR_FLM_SEL_FLM_NUM) && (gr_enlarge == VDC5_OFF)) {
+ /* Normal graphics display */
+ /* Sync signals from the graphics processing block */
+ *(scaler->scl0_us8) |= (uint32_t)VDC5_REG_BIT4;
+
+ /* Register update control register (SC0_SCL0_UPDATE, SC1_SCL0_UPDATE, OIR_SCL0_UPDATE)
+ b13 SCL0_VEN_D
+ b4 SCL0_VEN_B */
+ *(scaler->scl0_update) |= (uint32_t)(VDC5_REG_BIT13 | VDC5_REG_BIT4);
+ } else {
+ /* Video image or graphics enlargement */
+ if (graphics_id == VDC5_GR_TYPE_OIR) {
+ /* Turn the vertical scaling-up and the horizontal scaling-up off */
+ *(scaler->scl0_us1) &= (uint32_t)~VDC5_REG_MASK_0X00000011;
+ /* Sync signals from the graphics processing block */
+ *(scaler->scl0_us8) |= (uint32_t)VDC5_REG_BIT4;
+ } else {
+ /* Sync signals from the scaling-up control block */
+ *(scaler->scl0_us8) &= (uint32_t)~VDC5_REG_BIT4;
+
+ /* Graphics display area */
+ *(scaler->scl0_us2) = (uint32_t)gr_grc->vs << VDC5_REG_SHIFT_16;
+ *(scaler->scl0_us2) |= (uint32_t)gr_grc->vw;
+ *(scaler->scl0_us3) = (uint32_t)gr_grc->hs << VDC5_REG_SHIFT_16;
+ *(scaler->scl0_us3) |= (uint32_t)gr_grc->hw;
+
+ *(scaler->scl0_us4) = (uint32_t)w_read_fb->in_vw << VDC5_REG_SHIFT_16;
+ *(scaler->scl0_us4) |= (uint32_t)w_read_fb->in_hw;
+
+ res_ds_wr_md_tmp = VDC5_ShrdPrmGetWritingMode(ch, scaling_id);
+ adj_sel_tmp = VDC5_ShrdPrmGetMeasureFolding(ch, graphics_id);
+ ip_conversion = VDC5_OFF;
+ if ((gr_flm_sel == VDC5_GR_FLM_SEL_SCALE_DOWN) || (gr_flm_sel == VDC5_GR_FLM_SEL_POINTER_BUFF)) {
+ res_inter_tmp = VDC5_ShrdPrmGetInterlace(ch, scaling_id);
+ if (res_inter_tmp != VDC5_RES_INTER_PROGRESSIVE) {
+ ip_conversion = VDC5_ON;
+ }
+ }
+
+ ln_off_dir = VDC5_ShrdPrmGetLineOfsAddrDir(ch, graphics_id);
+ /* Scaling-up */
+ SetScalingUp(w_read_fb, gr_grc, adj_sel_tmp, ip_conversion, res_ds_wr_md_tmp, ln_off_dir, scaler);
+ }
+ /* Register update control register (SC0_SCL0_UPDATE, SC1_SCL0_UPDATE, OIR_SCL0_UPDATE)
+ b13 SCL0_VEN_D
+ b8 SCL0_UPDATE
+ b4 SCL0_VEN_B
+ b0 SCL0_VEN_A */
+ *(scaler->scl0_update) |= (uint32_t)(VDC5_REG_BIT13 | VDC5_REG_BIT8 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+ }
+
+ if (gr_flm_sel != VDC5_GR_FLM_SEL_FLM_NUM) {
+ img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+ /* Frame buffer frame offset address */
+ reg_data = *(scaler->scl1_wr4);
+ *(img_synthesizer->gr_flm4) = reg_data;
+
+ /* Graphics register update control register (GRx_UPDATE)
+ b0 GRx_IBUS_VEN */
+ *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT0;
+ }
+} /* End of function SetScalerGraphics() */
+
+/**************************************************************************//**
+ * @brief Gets the amount of data to be skipped through
+ * @param[in] gr_base : Frame buffer base address
+ * @param[in] gr_format : Graphics format
+ * @retval The amount of data to be skipped through
+******************************************************************************/
+static uint32_t DisplayStartPixelSetting (const uint32_t gr_base, const vdc5_gr_format_t gr_format)
+{
+ uint32_t gr_sta_pos;
+ static const uint32_t bits_per_pixel[VDC5_GR_FORMAT_NUM] = {
+ VDC5_REG_BIT_PER_PIXEL_RGB565, /* RGB565 */
+ VDC5_REG_BIT_PER_PIXEL_RGB888, /* RGB888 */
+ VDC5_REG_BIT_PER_PIXEL_ARGB1555, /* ARGB1555 */
+ VDC5_REG_BIT_PER_PIXEL_ARGB4444, /* ARGB4444 */
+ VDC5_REG_BIT_PER_PIXEL_ARGB8888, /* ARGB8888 */
+ VDC5_REG_BIT_PER_PIXEL_CLUT8, /* CLUT8 */
+ VDC5_REG_BIT_PER_PIXEL_CLUT4, /* CLUT4 */
+ VDC5_REG_BIT_PER_PIXEL_CLUT1, /* CLUT1 */
+ VDC5_REG_BIT_PER_PIXEL_YCBCR422, /* YCbCr422: In the YCbCr422 format, 32 bits are used for two pixels. */
+ VDC5_REG_BIT_PER_PIXEL_YCBCR444, /* YCbCr444 */
+ VDC5_REG_BIT_PER_PIXEL_RGBA5551, /* RGBA5551 */
+ VDC5_REG_BIT_PER_PIXEL_RGBA8888 /* RGBA8888 */
+ };
+
+ gr_sta_pos = gr_base & (uint32_t)VDC5_REG_MASK_0X00000007;
+ gr_sta_pos *= (uint32_t)VDC5_REG_BIT_PER_PIXEL_VALUE_8;
+ gr_sta_pos /= bits_per_pixel[gr_format];
+ gr_sta_pos &= (uint32_t)VDC5_REG_MASK_0X0000003F;
+
+ return gr_sta_pos;
+} /* End of function DisplayStartPixelSetting() */
+
+/**************************************************************************//**
+ * @brief Sets cascaded connection
+ * @param[in] ch : Channel
+ * @param[in] graphics_id : Graphics type ID
+ * @param[in] gr_flm_sel : Frame buffer address setting signal
+ * @param[in] gr_enlarge : Graphics enlargement on/off
+ * @retval Cascade ON/OFF
+******************************************************************************/
+static vdc5_onoff_t SetCascade (
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_gr_flm_sel_t gr_flm_sel,
+ const vdc5_onoff_t gr_enlarge)
+{
+ const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+ const vdc5_regaddr_scaler_t * scaler_0;
+ const vdc5_regaddr_scaler_t * scaler_1;
+ vdc5_res_vs_in_sel_t res_vs_in_sel_tmp;
+ vdc5_onoff_t cascade;
+
+ cascade = VDC5_ShrdPrmGetCascade(ch);
+ /* Cascade */
+ if (graphics_id == VDC5_GR_TYPE_GR1) {
+ img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
+ scaler_0 = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0];
+ scaler_1 = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1];
+
+ if ((gr_flm_sel != VDC5_GR_FLM_SEL_FLM_NUM) || (gr_enlarge != VDC5_OFF)) {
+ /* Video image or graphics enlargement */
+ /* Cascade OFF */
+ *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_BIT28;
+
+ cascade = VDC5_OFF;
+ /* Get sync signal output and full-screen enable signal select */
+ res_vs_in_sel_tmp = VDC5_ShrdPrmGetVsInSel(ch);
+ if (res_vs_in_sel_tmp == VDC5_RES_VS_IN_SEL_SC0) {
+ /* Use Vsync and enable signal output from scaler 0 */
+ *(scaler_0->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT8;
+ *(scaler_1->scl0_frc3) |= (uint32_t)VDC5_REG_BIT8;
+ } else {
+ /* Use Vsync and enable signal output from scaler 1 */
+ *(scaler_0->scl0_frc3) |= (uint32_t)VDC5_REG_BIT8;
+ *(scaler_1->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT8;
+ }
+ } else {
+ /* Cascade ON */
+ *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT28;
+
+ cascade = VDC5_ON;
+ /* Use Vsync and enable signal output from scaler 0 */
+ *(scaler_0->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT8;
+ }
+ VDC5_ShrdPrmSetCascade(ch, cascade);
+
+ /* Register update control register (SC0_SCL0_UPDATE)
+ b8 SCL0_UPDATE */
+ *(scaler_0->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
+ /* Register update control register (SC1_SCL0_UPDATE)
+ b8 SCL0_UPDATE */
+ *(scaler_1->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
+ /* Graphics register update control register (GR1_UPDATE)
+ b8 GR1_UPDATE */
+ *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT8;
+ }
+ return cascade;
+} /* End of function SetCascade() */
+
+/**************************************************************************//**
+ * @brief Sets VIN synthesizer
+ * @param[in] ch : Channel
+ * @param[in] graphics_id : Graphics type ID
+ * @param[in] gr_flm_sel : Frame buffer address setting signal
+ * @param[in] gr_enlarge : Graphics enlargement on/off
+ * @retval None
+******************************************************************************/
+static void SetupGraphicsVIN (
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_gr_flm_sel_t gr_flm_sel,
+ const vdc5_onoff_t gr_enlarge)
+{
+ const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+ const vdc5_regaddr_img_synthesizer_t * img_synthesizer_vin;
+ vdc5_onoff_t cascade;
+ vdc5_resource_state_t rsrc_state;
+ vdc5_onoff_t und_sel;
+ uint32_t reg_data;
+
+ /* Cascade */
+ cascade = SetCascade(ch, graphics_id, gr_flm_sel, gr_enlarge);
+
+ /* Display area for VIN */
+ rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_0_RD);
+ if ((cascade == VDC5_OFF) &&
+ ((rsrc_state != VDC5_RESOURCE_ST_INVALID) || (graphics_id == VDC5_GR_TYPE_GR0))) {
+ /* Cascade connection OFF and graphics 0 is used */
+ img_synthesizer_vin = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_VIN];
+
+ und_sel = VDC5_ShrdPrmGetUndSel(ch);
+ if (und_sel == VDC5_OFF) {
+ /* Graphics 1 is allocated to the upper-layer. */
+ *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_BIT2;
+
+ img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
+ } else {
+ /* Graphics 0 is allocated to the upper-layer. */
+ *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
+
+ img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0];
+ }
+ /* Graphics display mode in VIN */
+ *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+ *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_DISPSEL_BLEND;
+ /* Copy the graphics display area in the upper-layer to the VIN display area. */
+ reg_data = *(img_synthesizer->gr_ab2);
+ *(img_synthesizer_vin->gr_ab2) = reg_data;
+ reg_data = *(img_synthesizer->gr_ab3);
+ *(img_synthesizer_vin->gr_ab3) = reg_data;
+ /* The valid image area for alpha blending in a rectangular area */
+ reg_data = *(img_synthesizer_vin->gr_ab2);
+ *(img_synthesizer_vin->gr_ab4) = reg_data;
+ reg_data = *(img_synthesizer_vin->gr_ab3);
+ *(img_synthesizer_vin->gr_ab5) = reg_data;
+
+ /* Graphics register update control register (GR_VIN_UPDATE)
+ b8 GR_VIN_UPDATE
+ b4 GR_VIN_P_VEN */
+ *(img_synthesizer_vin->gr_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+ }
+} /* End of function SetupGraphicsVIN() */
+
+/**************************************************************************//**
+ * @brief Changes VIN synthesizer settings
+ * @param[in] ch : Channel
+ * @param[in] graphics_id : Graphics type ID
+ * @param[in] gr_flm_sel : Frame buffer address setting signal
+ * @param[in] gr_enlarge : Graphics enlargement on/off
+ * @retval None
+******************************************************************************/
+static void ChangeGraphicsVIN (
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_gr_flm_sel_t gr_flm_sel,
+ const vdc5_onoff_t gr_enlarge)
+{
+ const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+ const vdc5_regaddr_img_synthesizer_t * img_synthesizer_vin;
+ vdc5_onoff_t cascade;
+ vdc5_onoff_t cascade_prev;
+ vdc5_resource_state_t rsrc_state;
+ vdc5_onoff_t und_sel;
+ uint32_t reg_data;
+
+ /* Cascade */
+ cascade_prev = VDC5_ShrdPrmGetCascade(ch);
+ cascade = SetCascade(ch, graphics_id, gr_flm_sel, gr_enlarge);
+
+ /* Display area for VIN */
+ rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_0_RD);
+ if (rsrc_state != VDC5_RESOURCE_ST_INVALID) {
+ /* Graphics 0 is used */
+ img_synthesizer_vin = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_VIN];
+ if (cascade == VDC5_OFF) {
+ /* Cascade connection is OFF */
+ und_sel = VDC5_ShrdPrmGetUndSel(ch);
+ if (und_sel == VDC5_OFF) {
+ /* Graphics 1 is allocated to the upper-layer. */
+ *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_BIT2;
+
+ img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
+ } else {
+ /* Graphics 0 is allocated to the upper-layer. */
+ *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
+
+ img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0];
+ }
+ /* Graphics display mode in VIN */
+ *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+ *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_DISPSEL_BLEND;
+ /* Copy the graphics display area in the upper-layer to the VIN display area. */
+ reg_data = *(img_synthesizer->gr_ab2);
+ *(img_synthesizer_vin->gr_ab2) = reg_data;
+ reg_data = *(img_synthesizer->gr_ab3);
+ *(img_synthesizer_vin->gr_ab3) = reg_data;
+ } else {
+ /* Cascade connection is ON */
+ if (cascade_prev == VDC5_OFF) {
+ /* Cascade connection was turned on in this function. */
+ /* Selection of lower-layer plane in scaler is set to 1. */
+ *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
+ /* Graphics display mode in VIN */
+ *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+ *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+ }
+ }
+ /* Graphics register update control register (GR_VIN_UPDATE)
+ b8 GR_VIN_UPDATE
+ b4 GR_VIN_P_VEN */
+ *(img_synthesizer_vin->gr_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+ }
+} /* End of function ChangeGraphicsVIN() */
+
+/**************************************************************************//**
+ * @brief Sets color matrix in the image quality improver
+ * @param[in] ch : Channel
+ * @param[in] graphics_id : Graphics type ID
+ * @param[in] color_space : Color space (GBR or YCbCr)
+ * @retval None
+******************************************************************************/
+static void SetImgQaImproverColorMtx (
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_color_space_t color_space)
+{
+ vdc5_colormtx_module_t module_tmp;
+ vdc5_colormtx_mode_t mtx_mode_tmp;
+ const uint16_t * offset_tmp;
+ const uint16_t * gain_tmp;
+
+ /* Color matrix operating mode */
+ if (color_space == VDC5_COLOR_SPACE_GBR) {
+ mtx_mode_tmp = VDC5_COLORMTX_GBR_GBR;
+ } else {
+ mtx_mode_tmp = VDC5_COLORMTX_YCBCR_GBR;
+ }
+ /* Color matrix module */
+ module_tmp = (graphics_id == VDC5_GR_TYPE_GR0) ? VDC5_COLORMTX_ADJ_0 : VDC5_COLORMTX_ADJ_1;
+ /* Color matrix offset (DC) adjustment (YG, B, and R) */
+ offset_tmp = colormtx_offset_adj;
+ /* Color matrix signal gain adjustment (GG, GB, GR, BG, BB, BR, RG, RB, and RR) */
+ gain_tmp = colormtx_gain_adj[mtx_mode_tmp];
+
+ SetColorMatrix(mtx_mode_tmp, offset_tmp, gain_tmp, &vdc5_regaddr_color_matrix[ch][module_tmp]);
+
+} /* End of function SetImgQaImproverColorMtx() */
+
+/**************************************************************************//**
+ * @brief Activates/deactivates frame buffer writing for scaler 0
+ * @param[in] ch : Channel
+ * @param[in] ability : Ability to enable read/write access to the memory
+ * @retval None
+******************************************************************************/
+static void SetRwProcAbility_Write_0 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+ const vdc5_regaddr_scaler_t * scaler;
+ volatile uint32_t dummy_read;
+ uint32_t reg_data;
+
+ /* SC0/GR0 writing */
+ scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0];
+
+ if (ability == VDC5_OFF) {
+ /* SC0 frame buffer writing is disabled */
+ *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT0;
+
+ VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_0_WR);
+ } else {
+ /* SC0 frame buffer writing is enabled */
+ *(scaler->scl1_wr5) |= (uint32_t)VDC5_REG_BIT0;
+ /* Reset and reset cancellation of the pointer buffer with dummy read */
+ *(scaler->scl1_pbuf_cnt) |= (uint32_t)VDC5_REG_BIT16;
+ reg_data = *(scaler->scl1_pbuf_cnt);
+ dummy_read = reg_data;
+ *(scaler->scl1_pbuf_cnt) &= (uint32_t)~VDC5_REG_BIT16;
+ reg_data = *(scaler->scl1_pbuf_cnt);
+ dummy_read = reg_data;
+
+ VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_0_WR);
+ }
+} /* End of function SetRwProcAbility_Write_0() */
+
+/**************************************************************************//**
+ * @brief Activates/deactivates frame buffer writing for scaler 1
+ * @param[in] ch : Channel
+ * @param[in] ability : Ability to enable read/write access to the memory
+ * @retval None
+******************************************************************************/
+static void SetRwProcAbility_Write_1 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+ const vdc5_regaddr_scaler_t * scaler;
+ volatile uint32_t dummy_read;
+ uint32_t reg_data;
+
+ /* SC1/GR1 writing */
+ scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1];
+
+ if (ability == VDC5_OFF) {
+ /* SC1 frame buffer writing is disabled */
+ *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT0;
+
+ VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_1_WR);
+ } else {
+ /* SC1 frame buffer writing is enabled */
+ *(scaler->scl1_wr5) |= (uint32_t)VDC5_REG_BIT0;
+ /* Reset and reset cancellation of the pointer buffer with dummy read */
+ *(scaler->scl1_pbuf_cnt) |= (uint32_t)VDC5_REG_BIT16;
+ reg_data = *(scaler->scl1_pbuf_cnt);
+ dummy_read = reg_data;
+ *(scaler->scl1_pbuf_cnt) &= (uint32_t)~VDC5_REG_BIT16;
+ reg_data = *(scaler->scl1_pbuf_cnt);
+ dummy_read = reg_data;
+
+ VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_1_WR);
+ }
+} /* End of function SetRwProcAbility_Write_1() */
+
+/**************************************************************************//**
+ * @brief Activates/deactivates frame buffer writing for OIR
+ * @param[in] ch : Channel
+ * @param[in] ability : Ability to enable read/write access to the memory
+ * @retval None
+******************************************************************************/
+static void SetRwProcAbility_Write_OIR (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+ const vdc5_regaddr_scaler_t * scaler;
+
+ /* OIR writing */
+ scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR];
+
+ if (ability == VDC5_OFF) {
+ /* OIR frame buffer writing is disabled */
+ *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT0;
+
+ VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_OIR_WR);
+ } else {
+ /* OIR frame buffer writing is enabled */
+ *(scaler->scl1_wr5) |= (uint32_t)VDC5_REG_BIT0;
+
+ VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_OIR_WR);
+ }
+} /* End of function SetRwProcAbility_Write_OIR() */
+
+/**************************************************************************//**
+ * @brief Activates/deactivates frame buffer reading for graphics 0
+ * @param[in] ch : Channel
+ * @param[in] ability : Ability to enable read/write access to the memory
+ * @retval None
+******************************************************************************/
+static void SetRwProcAbility_Read_0 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+ const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+
+ /* SC0/GR0 reading */
+ img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0];
+
+ if (ability == VDC5_OFF) {
+ /* GR0 frame buffer reading is disabled */
+ *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC5_REG_BIT0;
+ /* Graphics display mode */
+ *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+ *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_BACK;
+
+ VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_0_RD);
+ } else {
+ /* GR0 frame buffer reading is enabled */
+ *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC5_REG_BIT0;
+
+ VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_0_RD);
+ }
+} /* End of function SetRwProcAbility_Read_0() */
+
+/**************************************************************************//**
+ * @brief Activates/deactivates frame buffer reading for graphics 1
+ * @param[in] ch : Channel
+ * @param[in] ability : Ability to enable read/write access to the memory
+ * @retval None
+******************************************************************************/
+static void SetRwProcAbility_Read_1 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+ const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+
+ /* SC1/GR1 reading */
+ img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
+
+ if (ability == VDC5_OFF) {
+ /* GR1 frame buffer reading is disabled */
+ *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC5_REG_BIT0;
+ /* Graphics display mode */
+ *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+ *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+
+ VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_1_RD);
+ } else {
+ /* GR1 frame buffer reading is enabled */
+ *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC5_REG_BIT0;
+
+ VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_1_RD);
+ }
+} /* End of function SetRwProcAbility_Read_1() */
+
+/**************************************************************************//**
+ * @brief Activates/deactivates frame buffer reading for graphics 2
+ * @param[in] ch : Channel
+ * @param[in] ability : Ability to enable read/write access to the memory
+ * @retval None
+******************************************************************************/
+static void SetRwProcAbility_Read_2 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+ const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+
+ /* GR2 reading */
+ img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR2];
+
+ if (ability == VDC5_OFF) {
+ /* GR2 frame buffer reading is disabled */
+ *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC5_REG_BIT0;
+ /* Graphics display mode */
+ *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+ *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+
+ VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_2_RD);
+ } else {
+ /* GR2 frame buffer reading is enabled */
+ *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC5_REG_BIT0;
+
+ VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_2_RD);
+ }
+} /* End of function SetRwProcAbility_Read_2() */
+
+/**************************************************************************//**
+ * @brief Activates/deactivates frame buffer reading for graphics 3
+ * @param[in] ch : Channel
+ * @param[in] ability : Ability to enable read/write access to the memory
+ * @retval None
+******************************************************************************/
+static void SetRwProcAbility_Read_3 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+ const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+
+ /* GR3 reading */
+ img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR3];
+
+ if (ability == VDC5_OFF) {
+ /* GR3 frame buffer reading is disabled */
+ *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC5_REG_BIT0;
+ /* Graphics display mode */
+ *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+ *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+
+ VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_3_RD);
+ } else {
+ /* GR3 frame buffer reading is enabled */
+ *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC5_REG_BIT0;
+
+ VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_3_RD);
+ }
+} /* End of function SetRwProcAbility_Read_3() */
+
+/**************************************************************************//**
+ * @brief Activates/deactivates frame buffer reading for OIR
+ * @param[in] ch : Channel
+ * @param[in] ability : Ability to enable read/write access to the memory
+ * @retval None
+******************************************************************************/
+static void SetRwProcAbility_Read_OIR (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+ const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+
+ /* OIR reading */
+ img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_OIR];
+
+ if (ability == VDC5_OFF) {
+ /* OIR frame buffer reading is disabled */
+ *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC5_REG_BIT0;
+ /* Graphics display mode */
+ *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+ *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_BACK;
+
+ VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_OIR_RD);
+ } else {
+ /* OIR frame buffer reading is enabled */
+ *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC5_REG_BIT0;
+
+ VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_OIR_RD);
+ }
+} /* End of function SetRwProcAbility_Read_OIR() */
+
+/**************************************************************************//**
+ * @brief Sets register update control register to update the frame buffer
+ * read and write enable settings.
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @retval None
+******************************************************************************/
+static void SetRegUpdateRwEnable (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+ volatile uint32_t * scl1_update_reg;
+ volatile uint32_t * gr_update_reg;
+
+ switch (layer_id) {
+ case VDC5_LAYER_ID_0_WR: /* Layer 0, write process */
+ scl1_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl1_update;
+ *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT20 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+ break;
+ case VDC5_LAYER_ID_1_WR: /* Layer 1, write process */
+ scl1_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl1_update;
+ *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT20 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+ break;
+ case VDC5_LAYER_ID_OIR_WR: /* Layer OIR, write process */
+ scl1_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR].scl1_update;
+ *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+ break;
+ case VDC5_LAYER_ID_0_RD: /* Layer 0, read process */
+ gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0].gr_update;
+ *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+ break;
+ case VDC5_LAYER_ID_1_RD: /* Layer 1, read process */
+ gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1].gr_update;
+ *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+ break;
+ case VDC5_LAYER_ID_2_RD: /* Layer 2, read process */
+ gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR2].gr_update;
+ *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+ break;
+ case VDC5_LAYER_ID_3_RD: /* Layer 3, read process */
+ gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR3].gr_update;
+ *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+ break;
+ case VDC5_LAYER_ID_OIR_RD: /* Layer OIR, read process */
+ gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_OIR].gr_update;
+ *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+ break;
+
+ case VDC5_LAYER_ID_ALL: /* All */
+ /* Register update control register (SCx_SCL1_UPDATE)
+ b20 SCL1_UPDATE_B
+ b4 SCL1_VEN_B
+ b0 SCL1_VEN_A */
+ scl1_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl1_update;
+ *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT20 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+ scl1_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl1_update;
+ *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT20 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+ /* Register update control register (OIR_SCL1_UPDATE)
+ b4 SCL1_VEN_B
+ b0 SCL1_VEN_A */
+ scl1_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR].scl1_update;
+ *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+ /* Graphics register update control register (GRx_UPDATE)
+ b4 GRx_P_VEN
+ b0 GRx_IBUS_VEN */
+ gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0].gr_update;
+ *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+ gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1].gr_update;
+ *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+ gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR2].gr_update;
+ *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+ gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR3].gr_update;
+ *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+ gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_OIR].gr_update;
+ *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+ break;
+
+ default:
+ /* DO NOTHING */
+ break;
+ }
+} /* End of function SetRegUpdateRwEnable() */
+
+/**************************************************************************//**
+ * @brief Sets graphics display mode
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @param[in] gr_disp_sel : Graphics display mode
+ * @retval None
+******************************************************************************/
+static void SetGraphicsDisplayMode (
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_gr_disp_sel_t * const gr_disp_sel)
+{
+ uint32_t graphics_id;
+ const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+
+ if (layer_id == VDC5_LAYER_ID_ALL) {
+ for (graphics_id = 0; graphics_id < VDC5_GR_TYPE_NUM; graphics_id++) {
+ if ((graphics_id != VDC5_GR_TYPE_VIN) && (gr_disp_sel[graphics_id] != VDC5_DISPSEL_IGNORED)) {
+ img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+ *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+ *(img_synthesizer->gr_ab1) |= (uint32_t)gr_disp_sel[graphics_id];
+ /* Graphics register update control register (GRx_UPDATE)
+ b4 GRx_P_VEN */
+ *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+ }
+ }
+ } else if ((layer_id >= VDC5_LAYER_ID_0_RD) && (layer_id <= VDC5_LAYER_ID_OIR_RD)) {
+ if (*gr_disp_sel != VDC5_DISPSEL_IGNORED) {
+ graphics_id = (uint32_t)(layer_id - VDC5_SC_TYPE_NUM);
+
+ img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+ *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+ *(img_synthesizer->gr_ab1) |= (uint32_t)*gr_disp_sel;
+ /* Graphics register update control register (GRx_UPDATE)
+ b4 GRx_P_VEN */
+ *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+ }
+ } else {
+ /* Do nothing */
+ }
+} /* End of function SetGraphicsDisplayMode() */
+
+/**************************************************************************//**
+ * @brief Sets color matrix
+ * @param[in] mtx_mode : Operating mode
+ * @param[in] offset : Offset (DC) adjustment of Y/G, B, and R signal
+ * @param[in] gain : GG, GB, GR, BG, BB, BR, RG, RB, and RR signal gain adjustment
+ * @param[in] color_matrix : Color matrix registers
+ * @retval None
+******************************************************************************/
+static void SetColorMatrix (
+ const vdc5_colormtx_mode_t mtx_mode,
+ const uint16_t * const offset,
+ const uint16_t * const gain,
+ const vdc5_regaddr_color_matrix_t * const color_matrix)
+{
+ /* Operating mode */
+ *(color_matrix->mtx_mode) = (uint32_t)mtx_mode;
+
+ /* Offset (DC) adjustment of Y/G, B, and R signal and
+ GG, GB, GR, BG, BB, BR, RG, RB, and RR signal gain adjustment */
+ *(color_matrix->mtx_yg_adj0) = (uint32_t)offset[VDC5_COLORMTX_OFFST_YG] << VDC5_REG_SHIFT_16;
+ *(color_matrix->mtx_yg_adj0) |= (uint32_t)gain[VDC5_COLORMTX_GAIN_GG];
+ *(color_matrix->mtx_yg_adj1) = (uint32_t)gain[VDC5_COLORMTX_GAIN_GB] << VDC5_REG_SHIFT_16;
+ *(color_matrix->mtx_yg_adj1) |= (uint32_t)gain[VDC5_COLORMTX_GAIN_GR];
+ *(color_matrix->mtx_cbb_adj0) = (uint32_t)offset[VDC5_COLORMTX_OFFST_B] << VDC5_REG_SHIFT_16;
+ *(color_matrix->mtx_cbb_adj0) |= (uint32_t)gain[VDC5_COLORMTX_GAIN_BG];
+ *(color_matrix->mtx_cbb_adj1) = (uint32_t)gain[VDC5_COLORMTX_GAIN_BB] << VDC5_REG_SHIFT_16;
+ *(color_matrix->mtx_cbb_adj1) |= (uint32_t)gain[VDC5_COLORMTX_GAIN_BR];
+ *(color_matrix->mtx_crr_adj0) = (uint32_t)offset[VDC5_COLORMTX_OFFST_R] << VDC5_REG_SHIFT_16;
+ *(color_matrix->mtx_crr_adj0) |= (uint32_t)gain[VDC5_COLORMTX_GAIN_RG];
+ *(color_matrix->mtx_crr_adj1) = (uint32_t)gain[VDC5_COLORMTX_GAIN_RB] << VDC5_REG_SHIFT_16;
+ *(color_matrix->mtx_crr_adj1) |= (uint32_t)gain[VDC5_COLORMTX_GAIN_RR];
+
+ /* Register update control register (IMGCNT_UPDATE/ADJx_UPDATE)
+ b0 IMGCNT_VEN/ADJx_VEN */
+ *(color_matrix->mtx_update) |= (uint32_t)VDC5_REG_BIT0;
+
+} /* End of function SetColorMatrix() */
+
+/**************************************************************************//**
+ * @brief Sets sharpness
+ * @param[in] shp_h_on : Sharpness ON/OFF setting
+ * @param[in] sharp_param : Sharpness ON/OFF setting
+ * @param[in] img_qlty_imp : Image quality improver registers
+ * @retval None
+******************************************************************************/
+static void SetImageEnhancementSharpness (
+ const vdc5_onoff_t shp_h_on,
+ const vdc5_enhance_sharp_t * const sharp_param,
+ const vdc5_regaddr_img_qlty_imp_t * const img_qlty_imp)
+{
+ const vdc5_sharpness_ctrl_t * sharpness_ctrl;
+
+ if (sharp_param != NULL) {
+ /* H1, adjacent pixel used as reference */
+ sharpness_ctrl = &sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H1];
+ /* Active sharpness range */
+ *(img_qlty_imp->adj_enh_shp1) &= (uint32_t)~VDC5_REG_MASK_0X0000003F;
+ *(img_qlty_imp->adj_enh_shp1) |= (uint32_t)sharpness_ctrl->shp_core;
+ /* Sharpness correction value clipping and sharpness edge amplitude value gain */
+ *(img_qlty_imp->adj_enh_shp2) = (uint32_t)sharpness_ctrl->shp_clip_o << VDC5_REG_SHIFT_24;
+ *(img_qlty_imp->adj_enh_shp2) |= (uint32_t)sharpness_ctrl->shp_clip_u << VDC5_REG_SHIFT_16;
+ *(img_qlty_imp->adj_enh_shp2) |= (uint32_t)sharpness_ctrl->shp_gain_o << VDC5_REG_SHIFT_8;
+ *(img_qlty_imp->adj_enh_shp2) |= (uint32_t)sharpness_ctrl->shp_gain_u;
+
+ /* H2, second adjacent pixel used as reference */
+ sharpness_ctrl = &sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H2];
+ /* LPF selection for folding prevention before H2 edge detection */
+ if (sharp_param->shp_h2_lpf_sel == VDC5_OFF) {
+ *(img_qlty_imp->adj_enh_shp3) = (uint32_t)0x00000000u;
+ } else {
+ *(img_qlty_imp->adj_enh_shp3) = (uint32_t)VDC5_REG_BIT16;
+ }
+ /* Active sharpness range */
+ *(img_qlty_imp->adj_enh_shp3) |= (uint32_t)sharpness_ctrl->shp_core;
+ /* Sharpness correction value clipping and sharpness edge amplitude value gain */
+ *(img_qlty_imp->adj_enh_shp4) = (uint32_t)sharpness_ctrl->shp_clip_o << VDC5_REG_SHIFT_24;
+ *(img_qlty_imp->adj_enh_shp4) |= (uint32_t)sharpness_ctrl->shp_clip_u << VDC5_REG_SHIFT_16;
+ *(img_qlty_imp->adj_enh_shp4) |= (uint32_t)sharpness_ctrl->shp_gain_o << VDC5_REG_SHIFT_8;
+ *(img_qlty_imp->adj_enh_shp4) |= (uint32_t)sharpness_ctrl->shp_gain_u;
+
+ /* H3, third adjacent pixel used as reference */
+ sharpness_ctrl = &sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H3];
+ /* Active sharpness range */
+ *(img_qlty_imp->adj_enh_shp5) = (uint32_t)sharpness_ctrl->shp_core;
+ /* Sharpness correction value clipping and sharpness edge amplitude value gain */
+ *(img_qlty_imp->adj_enh_shp6) = (uint32_t)sharpness_ctrl->shp_clip_o << VDC5_REG_SHIFT_24;
+ *(img_qlty_imp->adj_enh_shp6) |= (uint32_t)sharpness_ctrl->shp_clip_u << VDC5_REG_SHIFT_16;
+ *(img_qlty_imp->adj_enh_shp6) |= (uint32_t)sharpness_ctrl->shp_gain_o << VDC5_REG_SHIFT_8;
+ *(img_qlty_imp->adj_enh_shp6) |= (uint32_t)sharpness_ctrl->shp_gain_u;
+ }
+
+ if (shp_h_on == VDC5_OFF) {
+ *(img_qlty_imp->adj_enh_shp1) &= (uint32_t)~VDC5_REG_BIT16;
+ } else {
+ *(img_qlty_imp->adj_enh_shp1) |= (uint32_t)VDC5_REG_BIT16;
+ }
+} /* End of function SetImageEnhancementSharpness() */
+
+/**************************************************************************//**
+ * @brief Sets LTI
+ * @param[in] lti_h_on : LTI ON/OFF setting
+ * @param[in] lti_param : LTI setup parameter
+ * @param[in] img_qlty_imp : Image quality improver registers
+ * @retval None
+******************************************************************************/
+static void SetImageEnhancementLti (
+ const vdc5_onoff_t lti_h_on,
+ const vdc5_enhance_lti_t * const lti_param,
+ const vdc5_regaddr_img_qlty_imp_t * const img_qlty_imp)
+{
+ const vdc5_lti_ctrl_t * lti_ctrl;
+
+ if (lti_param != NULL) {
+ /* H2, second adjacent pixel used as reference */
+ lti_ctrl = <i_param->lti[VDC5_IMGENH_LTI1];
+ /* LPF selection for folding prevention before H2 edge detection */
+ if (lti_param->lti_h2_lpf_sel == VDC5_OFF) {
+ *(img_qlty_imp->adj_enh_lti1) = (uint32_t)0x00000000u;
+ } else {
+ *(img_qlty_imp->adj_enh_lti1) = (uint32_t)VDC5_REG_BIT24;
+ }
+ /* Median filter LTI correction threshold */
+ *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)((uint32_t)lti_ctrl->lti_inc_zero << VDC5_REG_SHIFT_16);
+ /* LTI edge amplitude value gain */
+ *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)((uint32_t)lti_ctrl->lti_gain << VDC5_REG_SHIFT_8);
+ /* LTI coring (maximum core value of 255) */
+ *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)lti_ctrl->lti_core;
+
+ /* H4, fourth adjacent pixel used as reference */
+ lti_ctrl = <i_param->lti[VDC5_IMGENH_LTI2];
+ /* Median filter reference pixel select */
+ if (lti_param->lti_h4_median_tap_sel == VDC5_LTI_MDFIL_SEL_ADJ2) {
+ *(img_qlty_imp->adj_enh_lti2) = (uint32_t)0x00000000u;
+ } else {
+ *(img_qlty_imp->adj_enh_lti2) = (uint32_t)VDC5_REG_BIT24;
+ }
+ /* Median filter LTI correction threshold */
+ *(img_qlty_imp->adj_enh_lti2) |= (uint32_t)((uint32_t)lti_ctrl->lti_inc_zero << VDC5_REG_SHIFT_16);
+ /* LTI edge amplitude value gain */
+ *(img_qlty_imp->adj_enh_lti2) |= (uint32_t)((uint32_t)lti_ctrl->lti_gain << VDC5_REG_SHIFT_8);
+ /* LTI coring (maximum core value of 255) */
+ *(img_qlty_imp->adj_enh_lti2) |= (uint32_t)lti_ctrl->lti_core;
+ }
+
+ if (lti_h_on == VDC5_OFF) {
+ *(img_qlty_imp->adj_enh_lti1) &= (uint32_t)~VDC5_REG_BIT31;
+ } else {
+ *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)VDC5_REG_BIT31;
+ }
+} /* End of function SetImageEnhancementLti() */
+
+/**************************************************************************//**
+ * @brief Sets alpha blending area of a rectangle
+ * @param[in] pd_disp_rect : Rectangular area for alpha blending
+ * @param[in] img_synthesizer : Image synthesizer registers
+ * @retval None
+******************************************************************************/
+static void SetAlphaRectArea (
+ const vdc5_pd_disp_rect_t * const pd_disp_rect,
+ const vdc5_regaddr_img_synthesizer_t * const img_synthesizer)
+{
+ uint32_t v_start;
+ uint32_t h_start;
+
+ if (pd_disp_rect != NULL) {
+ v_start = *(img_synthesizer->gr_ab2) >> VDC5_REG_SHIFT_16;
+ h_start = *(img_synthesizer->gr_ab3) >> VDC5_REG_SHIFT_16;
+
+ v_start += (uint32_t)pd_disp_rect->vs_rel;
+ h_start += (uint32_t)pd_disp_rect->hs_rel;
+ /* If the start position exceeds the maximum bit width, the value should be saturated. */
+ if ((v_start & (uint32_t)~VDC5_REG_MASK_0X000007FF) != 0u) {
+ v_start = (uint32_t)VDC5_REG_MASK_0X000007FF;
+ }
+ if ((h_start & (uint32_t)~VDC5_REG_MASK_0X000007FF) != 0u) {
+ h_start = (uint32_t)VDC5_REG_MASK_0X000007FF;
+ }
+
+ *(img_synthesizer->gr_ab4) = (v_start << VDC5_REG_SHIFT_16) | (uint32_t)pd_disp_rect->vw_rel;
+ *(img_synthesizer->gr_ab5) = (h_start << VDC5_REG_SHIFT_16) | (uint32_t)pd_disp_rect->hw_rel;
+ }
+} /* End of function SetAlphaRectArea() */
+
+/**************************************************************************//**
+ * @brief Sets upper-layer and lower-layer plane in scaler
+ * @param[in] ch : Channel
+ * @param[in] und_sel : Selection of lower-layer plane in scaler
+ * @retval None
+ *****************************************************************************/
+static void SetUndSel (const vdc5_channel_t ch, const vdc5_onoff_t und_sel)
+{
+ const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+ const vdc5_regaddr_img_synthesizer_t * img_synthesizer_vin;
+ vdc5_onoff_t current_und_sel;
+ vdc5_onoff_t cascade;
+ vdc5_resource_state_t rsrc_state;
+ uint32_t reg_data;
+
+ current_und_sel = VDC5_ShrdPrmGetUndSel(ch);
+ if (und_sel != current_und_sel) {
+ VDC5_ShrdPrmSetUndSel(ch, und_sel);
+
+ cascade = VDC5_ShrdPrmGetCascade(ch);
+ rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_0_RD);
+ if ((cascade == VDC5_OFF) && (rsrc_state != VDC5_RESOURCE_ST_INVALID)) {
+ /* Cascade connection OFF and graphics 0 is used */
+ img_synthesizer_vin = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_VIN];
+ if (und_sel == VDC5_OFF) {
+ /* Graphics 1 is allocated to the upper-layer. */
+ *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_BIT2;
+
+ img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
+ } else {
+ /* Graphics 0 is allocated to the upper-layer. */
+ *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
+
+ img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0];
+ }
+ /* Copy the graphics display area in the upper-layer to the VIN display area. */
+ reg_data = *(img_synthesizer->gr_ab2);
+ *(img_synthesizer_vin->gr_ab2) = reg_data;
+ reg_data = *(img_synthesizer->gr_ab3);
+ *(img_synthesizer_vin->gr_ab3) = reg_data;
+
+ /* Graphics register update control register (GR_VIN_UPDATE)
+ b8 GR_VIN_UPDATE
+ b4 GR_VIN_P_VEN */
+ *(img_synthesizer_vin->gr_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+ }
+ }
+} /* End of function SetUndSel() */
+
+/**************************************************************************//**
+ * @brief Converts the color format from gr_format format into 24-bit RGB888 format
+ * @param[in] gr_format : Color format
+ * @param[in] input_color : Color data
+ * @retval RGB888 color data
+******************************************************************************/
+static uint32_t ColorConversion (const vdc5_gr_format_t gr_format, const uint32_t input_color)
+{
+ uint32_t red;
+ uint32_t green;
+ uint32_t blue;
+ uint32_t conv_color;
+
+ conv_color = 0;
+ switch (gr_format) {
+ case VDC5_GR_FORMAT_RGB565:
+ red = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_RGB565_R_MASK) >> VDC5_REG_SHIFT_11));
+ green = ColorConversionFrom6to8((uint32_t)((input_color & VDC5_REG_RGB565_G_MASK) >> VDC5_REG_SHIFT_5));
+ blue = ColorConversionFrom5to8((uint32_t)(input_color & VDC5_REG_RGB565_B_MASK));
+ conv_color = (green << VDC5_REG_SHIFT_16) | (blue << VDC5_REG_SHIFT_8) | red;
+ break;
+ case VDC5_GR_FORMAT_RGB888:
+ conv_color = ColorConversionIntoAgbr(input_color);
+ break;
+ case VDC5_GR_FORMAT_ARGB1555:
+ red = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_ARGB1555_R_MASK) >> VDC5_REG_SHIFT_10));
+ green = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_ARGB1555_G_MASK) >> VDC5_REG_SHIFT_5));
+ blue = ColorConversionFrom5to8((uint32_t)(input_color & VDC5_REG_ARGB1555_B_MASK));
+ conv_color = (green << VDC5_REG_SHIFT_16) | (blue << VDC5_REG_SHIFT_8) | red;
+ break;
+ case VDC5_GR_FORMAT_ARGB4444:
+ red = ColorConversionFrom4to8((uint32_t)((input_color & VDC5_REG_ARGB4444_R_MASK) >> VDC5_REG_SHIFT_8));
+ green = ColorConversionFrom4to8((uint32_t)((input_color & VDC5_REG_ARGB4444_G_MASK) >> VDC5_REG_SHIFT_4));
+ blue = ColorConversionFrom4to8((uint32_t)(input_color & VDC5_REG_ARGB4444_B_MASK));
+ conv_color = (green << VDC5_REG_SHIFT_16) | (blue << VDC5_REG_SHIFT_8) | red;
+ break;
+ case VDC5_GR_FORMAT_ARGB8888:
+ conv_color = ColorConversionIntoAgbr((uint32_t)(input_color & VDC5_REG_RGB_24BIT_MASK));
+ break;
+ case VDC5_GR_FORMAT_RGBA5551:
+ red = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_RGBA5551_R_MASK) >> VDC5_REG_SHIFT_11));
+ green = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_RGBA5551_G_MASK) >> VDC5_REG_SHIFT_6));
+ blue = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_RGBA5551_B_MASK) >> VDC5_REG_SHIFT_1));
+ conv_color = (green << VDC5_REG_SHIFT_16) | (blue << VDC5_REG_SHIFT_8) | red;
+ break;
+ case VDC5_GR_FORMAT_RGBA8888:
+ conv_color = ColorConversionIntoAgbr((uint32_t)((input_color >> VDC5_REG_SHIFT_8) & VDC5_REG_RGB_24BIT_MASK));
+ break;
+ default:
+ /* DO NOTHING */
+ break;
+ }
+ return conv_color;
+} /* End of function ColorConversion() */
+
+/**************************************************************************//**
+ * @brief Converts the color data from 4 bits value into 8 bits value
+ * @param[in] color_value : 4-bit color data
+ * @retval 8-bit color data
+******************************************************************************/
+static uint32_t ColorConversionFrom4to8 (const uint32_t color_value)
+{
+ uint32_t color;
+
+ color = color_value & (uint32_t)VDC5_REG_COLOR_4BIT_MASK;
+ color *= (uint32_t)VDC5_REG_EXTENSION_VALUE_17;
+
+ return color;
+} /* End of function ColorConversionFrom4to8() */
+
+/**************************************************************************//**
+ * @brief Converts the color data from 5 bits value into 8 bits value
+ * @param[in] color_value : 5-bit color data
+ * @retval 8-bit color data
+******************************************************************************/
+static uint32_t ColorConversionFrom5to8 (const uint32_t color_value)
+{
+ uint32_t color;
+
+ color = color_value & (uint32_t)VDC5_REG_COLOR_5BIT_MASK;
+ color *= (uint32_t)(VDC5_REG_EXTENSION_VALUE_263 * VDC5_REG_ROUND_OFF_VALUE_2);
+ color /= (uint32_t)VDC5_REG_EXTENSION_VALUE_32;
+ /* Round off */
+ color += (uint32_t)VDC5_REG_ROUND_OFF_VALUE_1;
+ color /= (uint32_t)VDC5_REG_ROUND_OFF_VALUE_2;
+
+ return color;
+} /* End of function ColorConversionFrom5to8() */
+
+/**************************************************************************//**
+ * @brief Converts the color data from 6 bits value into 8 bits value
+ * @param[in] color_value : 6-bit color data
+ * @retval 8-bit color data
+******************************************************************************/
+static uint32_t ColorConversionFrom6to8 (const uint32_t color_value)
+{
+ uint32_t color;
+
+ color = color_value & (uint32_t)VDC5_REG_COLOR_6BIT_MASK;
+ color *= (uint32_t)(VDC5_REG_EXTENSION_VALUE_259 * VDC5_REG_ROUND_OFF_VALUE_2);
+ color /= (uint32_t)VDC5_REG_EXTENSION_VALUE_64;
+ /* Round off */
+ color += (uint32_t)VDC5_REG_ROUND_OFF_VALUE_1;
+ color /= (uint32_t)VDC5_REG_ROUND_OFF_VALUE_2;
+
+ return color;
+} /* End of function ColorConversionFrom6to8() */
+
+/**************************************************************************//**
+ * @brief Converts the color data from ARGB8888 format into AGBR8888 format
+ * @param[in] color_value : ARGB8888 color data
+ * @retval AGBR8888 color data
+******************************************************************************/
+static uint32_t ColorConversionIntoAgbr (const uint32_t color_value)
+{
+ uint32_t color_bgr;
+ uint32_t color_dat;
+
+ /* Green and blue */
+ color_bgr = (uint32_t)(color_value << VDC5_REG_SHIFT_8);
+ color_bgr &= (uint32_t)VDC5_REG_ARGB8888_GB_MASK;
+ /* Alpha */
+ color_dat = (uint32_t)(color_value & VDC5_REG_ALPHA_8BIT);
+ color_bgr |= color_dat;
+ /* Red */
+ color_dat = (uint32_t)((color_value >> VDC5_REG_SHIFT_16) & VDC5_REG_COLOR_8BIT_MASK);
+ color_bgr |= color_dat;
+
+ return color_bgr;
+} /* End of function ColorConversionIntoAgbr() */
+
+/**************************************************************************//**
+ * @brief Sets color lookup table (CLUT)
+ * @param[in] param : CLUT parameter
+ * @param[out] regaddr_clut : CLUT register top address
+ * @retval None
+******************************************************************************/
+static void Set_Clut (const vdc5_clut_t * const param, volatile uint32_t * regaddr_clut)
+{
+ uint32_t data_len;
+ const uint32_t * clut_tmp;
+
+ clut_tmp = param->clut;
+ for (data_len = 0; data_len < param->color_num; data_len++) {
+ *regaddr_clut = *clut_tmp;
+ regaddr_clut++;
+ clut_tmp++;
+ }
+} /* End of function Set_Clut() */
+
+/**************************************************************************//**
+ * @brief Sets start threshold for gamma correction
+ * @param[in] gam_th : Start threshold of area 1 to 31
+ * @param[out] gam_area : Gamma correction registers for start threshold
+ * @retval None
+******************************************************************************/
+static void Set_StartThreshold_Gamma (const uint8_t * gam_th, volatile uint32_t * const * const gam_area)
+{
+ uint32_t reg_index;
+
+ if (gam_th != NULL) {
+ *(gam_area[0]) = (uint32_t)*gam_th << VDC5_REG_SHIFT_16;
+ gam_th++;
+ *(gam_area[0]) |= (uint32_t)*gam_th << VDC5_REG_SHIFT_8;
+ gam_th++;
+ *(gam_area[0]) |= (uint32_t)*gam_th;
+ gam_th++;
+
+ for (reg_index = 1; reg_index < VDC5_GAM_AREA_REG_NUM; reg_index++) {
+ *(gam_area[reg_index]) = (uint32_t)*gam_th << VDC5_REG_SHIFT_24;
+ gam_th++;
+ *(gam_area[reg_index]) |= (uint32_t)*gam_th << VDC5_REG_SHIFT_16;
+ gam_th++;
+ *(gam_area[reg_index]) |= (uint32_t)*gam_th << VDC5_REG_SHIFT_8;
+ gam_th++;
+ *(gam_area[reg_index]) |= (uint32_t)*gam_th;
+ gam_th++;
+ }
+ }
+} /* End of function Set_StartThreshold_Gamma() */
+
+/**************************************************************************//**
+ * @brief Sets gain adjustment for gamma correction
+ * @param[in] gam_gain : Gain adjustment of area 0 to 31
+ * @param[out] gam_lut : Gamma correction registers for gain adjustment
+ * @retval None
+******************************************************************************/
+static void Set_GainAdjustment_Gamma (const uint16_t * gam_gain, volatile uint32_t * const * const gam_lut)
+{
+ uint32_t reg_index;
+
+ if (gam_gain != NULL) {
+ for (reg_index = 0; reg_index < VDC5_GAM_LUT_REG_NUM; reg_index++) {
+ *(gam_lut[reg_index]) = (uint32_t)*gam_gain << VDC5_REG_SHIFT_16;
+ gam_gain++;
+ *(gam_lut[reg_index]) |= (uint32_t)*gam_gain;
+ gam_gain++;
+ }
+ }
+} /* End of function Set_GainAdjustment_Gamma() */
+
+/**************************************************************************//**
+ * @brief Waits for 200 usec
+ * @param[in] void
+ * @retval None
+******************************************************************************/
+static void Wait_200_usec (void)
+{
+ volatile uint32_t counter;
+
+ for (counter = 0; counter < (uint32_t)VDC5_LVDS_PLL_WAIT_200USEC; counter++) {
+ /* Wait for 200 usec. */
+ }
+} /* End of function Wait_200_usec() */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/vdc5/src/r_vdc5_register.h Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,318 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file r_vdc5_register.h
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief VDC5 driver register setup definitions
+******************************************************************************/
+
+#ifndef R_VDC5_REGISTER_H
+#define R_VDC5_REGISTER_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_vdc5.h"
+#include "r_vdc5_user.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define VDC5_GAM_LUT_REG_NUM (16u) /*!< The number of table setting register in gamma correction block */
+#define VDC5_GAM_AREA_REG_NUM (8u) /*!< The number of area setting register in gamma correction block */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! VDC5 input controller register address list */
+typedef struct {
+ volatile uint32_t * inp_update;
+ volatile uint32_t * inp_sel_cnt;
+ volatile uint32_t * inp_ext_sync_cnt;
+ volatile uint32_t * inp_vsync_ph_adj;
+ volatile uint32_t * inp_dly_adj;
+ volatile uint32_t * imgcnt_update;
+ volatile uint32_t * imgcnt_nr_cnt0;
+ volatile uint32_t * imgcnt_nr_cnt1;
+} vdc5_regaddr_input_ctrl_t;
+
+/*! VDC5 scaler register address list */
+typedef struct {
+ volatile uint32_t * scl0_update;
+ volatile uint32_t * scl0_frc1;
+ volatile uint32_t * scl0_frc2;
+ volatile uint32_t * scl0_frc3;
+ volatile uint32_t * scl0_frc4;
+ volatile uint32_t * scl0_frc5;
+ volatile uint32_t * scl0_frc6;
+ volatile uint32_t * scl0_frc7;
+ volatile uint32_t * scl0_frc9;
+ volatile uint16_t * scl0_mon0;
+ volatile uint16_t * scl0_int;
+ volatile uint32_t * scl0_ds1;
+ volatile uint32_t * scl0_ds2;
+ volatile uint32_t * scl0_ds3;
+ volatile uint32_t * scl0_ds4;
+ volatile uint32_t * scl0_ds5;
+ volatile uint32_t * scl0_ds6;
+ volatile uint32_t * scl0_ds7;
+ volatile uint32_t * scl0_us1;
+ volatile uint32_t * scl0_us2;
+ volatile uint32_t * scl0_us3;
+ volatile uint32_t * scl0_us4;
+ volatile uint32_t * scl0_us5;
+ volatile uint32_t * scl0_us6;
+ volatile uint32_t * scl0_us7;
+ volatile uint32_t * scl0_us8;
+ volatile uint32_t * scl0_ovr1;
+ volatile uint32_t * scl1_update;
+ volatile uint32_t * scl1_wr1;
+ volatile uint32_t * scl1_wr2;
+ volatile uint32_t * scl1_wr3;
+ volatile uint32_t * scl1_wr4;
+ volatile uint32_t * scl1_wr5;
+ volatile uint32_t * scl1_wr6;
+ volatile uint32_t * scl1_wr7;
+ volatile uint32_t * scl1_wr8;
+ volatile uint32_t * scl1_wr9;
+ volatile uint32_t * scl1_wr10;
+ volatile uint32_t * scl1_wr11;
+ volatile uint32_t * scl1_mon1;
+ volatile uint32_t * scl1_pbuf0;
+ volatile uint32_t * scl1_pbuf1;
+ volatile uint32_t * scl1_pbuf2;
+ volatile uint32_t * scl1_pbuf3;
+ volatile uint32_t * scl1_pbuf_fld;
+ volatile uint32_t * scl1_pbuf_cnt;
+} vdc5_regaddr_scaler_t;
+
+/*! VDC5 image quality improver register address list */
+typedef struct {
+ volatile uint32_t * adj_update;
+ volatile uint32_t * adj_bkstr_set;
+ volatile uint32_t * adj_enh_tim1;
+ volatile uint32_t * adj_enh_tim2;
+ volatile uint32_t * adj_enh_tim3;
+ volatile uint32_t * adj_enh_shp1;
+ volatile uint32_t * adj_enh_shp2;
+ volatile uint32_t * adj_enh_shp3;
+ volatile uint32_t * adj_enh_shp4;
+ volatile uint32_t * adj_enh_shp5;
+ volatile uint32_t * adj_enh_shp6;
+ volatile uint32_t * adj_enh_lti1;
+ volatile uint32_t * adj_enh_lti2;
+} vdc5_regaddr_img_qlty_imp_t;
+
+/*! VDC5 color matrix register address list */
+typedef struct {
+ volatile uint32_t * mtx_update;
+ volatile uint32_t * mtx_mode;
+ volatile uint32_t * mtx_yg_adj0;
+ volatile uint32_t * mtx_yg_adj1;
+ volatile uint32_t * mtx_cbb_adj0;
+ volatile uint32_t * mtx_cbb_adj1;
+ volatile uint32_t * mtx_crr_adj0;
+ volatile uint32_t * mtx_crr_adj1;
+} vdc5_regaddr_color_matrix_t;
+
+/*! VDC5 image synthesizer register address list */
+typedef struct {
+ volatile uint32_t * gr_update;
+ volatile uint32_t * gr_flm_rd;
+ volatile uint32_t * gr_flm1;
+ volatile uint32_t * gr_flm2;
+ volatile uint32_t * gr_flm3;
+ volatile uint32_t * gr_flm4;
+ volatile uint32_t * gr_flm5;
+ volatile uint32_t * gr_flm6;
+ volatile uint32_t * gr_ab1;
+ volatile uint32_t * gr_ab2;
+ volatile uint32_t * gr_ab3;
+ volatile uint32_t * gr_ab4;
+ volatile uint32_t * gr_ab5;
+ volatile uint32_t * gr_ab6;
+ volatile uint32_t * gr_ab7;
+ volatile uint32_t * gr_ab8;
+ volatile uint32_t * gr_ab9;
+ volatile uint32_t * gr_ab10;
+ volatile uint32_t * gr_ab11;
+ volatile uint32_t * gr_base;
+ volatile uint32_t * gr_clut;
+ volatile uint32_t * gr_mon;
+} vdc5_regaddr_img_synthesizer_t;
+
+/*! VDC5 gamma correction register address list */
+typedef struct {
+ volatile uint32_t * gam_sw;
+ volatile uint32_t * gam_g_update;
+ volatile uint32_t * gam_g_lut[VDC5_GAM_LUT_REG_NUM];
+ volatile uint32_t * gam_g_area[VDC5_GAM_AREA_REG_NUM];
+ volatile uint32_t * gam_b_update;
+ volatile uint32_t * gam_b_lut[VDC5_GAM_LUT_REG_NUM];
+ volatile uint32_t * gam_b_area[VDC5_GAM_AREA_REG_NUM];
+ volatile uint32_t * gam_r_update;
+ volatile uint32_t * gam_r_lut[VDC5_GAM_LUT_REG_NUM];
+ volatile uint32_t * gam_r_area[VDC5_GAM_AREA_REG_NUM];
+} vdc5_regaddr_gamma_t;
+
+/*! VDC5 output controller register address list */
+typedef struct {
+ volatile uint32_t * tcon_update;
+ volatile uint32_t * tcon_tim;
+ volatile uint32_t * tcon_tim_stva1;
+ volatile uint32_t * tcon_tim_stva2;
+ volatile uint32_t * tcon_tim_stvb1;
+ volatile uint32_t * tcon_tim_stvb2;
+ volatile uint32_t * tcon_tim_sth1;
+ volatile uint32_t * tcon_tim_sth2;
+ volatile uint32_t * tcon_tim_stb1;
+ volatile uint32_t * tcon_tim_stb2;
+ volatile uint32_t * tcon_tim_cpv1;
+ volatile uint32_t * tcon_tim_cpv2;
+ volatile uint32_t * tcon_tim_pola1;
+ volatile uint32_t * tcon_tim_pola2;
+ volatile uint32_t * tcon_tim_polb1;
+ volatile uint32_t * tcon_tim_polb2;
+ volatile uint32_t * tcon_tim_de;
+ volatile uint32_t * out_update;
+ volatile uint32_t * out_set;
+ volatile uint32_t * out_bright1;
+ volatile uint32_t * out_bright2;
+ volatile uint32_t * out_contrast;
+ volatile uint32_t * out_pdtha;
+ volatile uint32_t * out_clk_phase;
+} vdc5_regaddr_output_ctrl_t;
+
+/*! VDC5 system controller register address list */
+typedef struct {
+ volatile uint32_t * syscnt_int1;
+ volatile uint32_t * syscnt_int2;
+ volatile uint32_t * syscnt_int3;
+ volatile uint32_t * syscnt_int4;
+ volatile uint32_t * syscnt_int5;
+ volatile uint32_t * syscnt_int6;
+ volatile uint16_t * syscnt_panel_clk;
+ volatile uint16_t * syscnt_clut;
+} vdc5_regaddr_system_ctrl_t;
+
+/*! LVDS register address list */
+typedef struct {
+ volatile uint32_t * lvds_update;
+ volatile uint32_t * lvdsfcl;
+ volatile uint32_t * lclkselr;
+ volatile uint32_t * lpllsetr;
+ volatile uint32_t * lphyacc;
+} vdc5_regaddr_lvds_t;
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+extern const vdc5_regaddr_input_ctrl_t vdc5_regaddr_input_ctrl[VDC5_CHANNEL_NUM];
+extern const vdc5_regaddr_scaler_t vdc5_regaddr_scaler[VDC5_CHANNEL_NUM][VDC5_SC_TYPE_NUM];
+extern const vdc5_regaddr_img_qlty_imp_t vdc5_regaddr_img_qlty_imp[VDC5_CHANNEL_NUM][VDC5_IMG_IMPRV_NUM];
+extern const vdc5_regaddr_color_matrix_t vdc5_regaddr_color_matrix[VDC5_CHANNEL_NUM][VDC5_COLORMTX_NUM];
+extern const vdc5_regaddr_img_synthesizer_t vdc5_regaddr_img_synthesizer[VDC5_CHANNEL_NUM][VDC5_GR_TYPE_NUM];
+extern uint32_t * const vdc5_regaddr_clut[VDC5_CHANNEL_NUM][VDC5_GR_TYPE_NUM];
+extern const vdc5_regaddr_output_ctrl_t vdc5_regaddr_output_ctrl[VDC5_CHANNEL_NUM];
+extern const vdc5_regaddr_gamma_t vdc5_regaddr_gamma[VDC5_CHANNEL_NUM];
+extern const vdc5_regaddr_system_ctrl_t vdc5_regaddr_system_ctrl[VDC5_CHANNEL_NUM];
+extern const vdc5_regaddr_lvds_t vdc5_regaddr_lvds;
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void VDC5_Initialize(const vdc5_channel_t ch, const vdc5_init_t * const param);
+void VDC5_Terminate(const vdc5_channel_t ch);
+void VDC5_VideoInput(const vdc5_channel_t ch, const vdc5_input_t * const param);
+void VDC5_SyncControl(const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param);
+void VDC5_DisplayOutput(const vdc5_channel_t ch, const vdc5_output_t * const param);
+void VDC5_WriteDataControl(
+ const vdc5_channel_t ch,
+ const vdc5_scaling_type_t scaling_id,
+ const vdc5_write_t * const param);
+void VDC5_ChangeWriteProcess(
+ const vdc5_channel_t ch,
+ const vdc5_scaling_type_t scaling_id,
+ const vdc5_write_chg_t * const param);
+void VDC5_ReadDataControl(
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_read_t * const param);
+void VDC5_ChangeReadProcess(
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_read_chg_t * const param);
+void VDC5_StartProcess(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_start_t * const param);
+void VDC5_StopProcess(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+void VDC5_ReleaseDataControl(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+void VDC5_VideoNoiseReduction(
+ const vdc5_channel_t ch,
+ const vdc5_onoff_t nr1d_on,
+ const vdc5_noise_reduction_t * const param);
+void VDC5_ImageColorMatrix(const vdc5_channel_t ch, const vdc5_color_matrix_t * const param);
+void VDC5_ImageEnhancement(
+ const vdc5_channel_t ch,
+ const vdc5_imgimprv_id_t imgimprv_id,
+ const vdc5_onoff_t shp_h_on,
+ const vdc5_enhance_sharp_t * const sharp_param,
+ const vdc5_onoff_t lti_h_on,
+ const vdc5_enhance_lti_t * const lti_param,
+ const vdc5_period_rect_t * const enh_area);
+void VDC5_ImageBlackStretch(
+ const vdc5_channel_t ch,
+ const vdc5_imgimprv_id_t imgimprv_id,
+ const vdc5_onoff_t bkstr_on,
+ const vdc5_black_t * const param);
+void VDC5_AlphaBlending(
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_alpha_blending_t * const param);
+void VDC5_AlphaBlendingRect(
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_onoff_t gr_arc_on,
+ const vdc5_alpha_blending_rect_t * const param);
+void VDC5_Chromakey(
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_onoff_t gr_ck_on,
+ const vdc5_chromakey_t * const param);
+void VDC5_CLUT(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id, const vdc5_clut_t * const param);
+void VDC5_DisplayCalibration(const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param);
+void VDC5_GammaCorrection(
+ const vdc5_channel_t ch,
+ const vdc5_onoff_t gam_on,
+ const vdc5_gamma_correction_t * const param);
+
+void VDC5_Int_Disable(const vdc5_channel_t ch);
+void VDC5_Int_SetInterrupt(const vdc5_channel_t ch, const vdc5_int_t * const param);
+
+
+#endif /* R_VDC5_REGISTER_H */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/vdc5/src/r_vdc5_register_address.c Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,1105 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file r_vdc5_register_address.c
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief VDC5 driver register address table
+******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_vdc5.h"
+#include "r_vdc5_user.h"
+#include "r_vdc5_register.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define VDC5_CH0_GR0_CLUT_TBL (*(uint32_t*)0xFCFF6000u)
+#define VDC5_CH0_GR1_CLUT_TBL (*(uint32_t*)0xFCFF6400u)
+#define VDC5_CH0_GR2_CLUT_TBL (*(uint32_t*)0xFCFF6800u)
+#define VDC5_CH0_GR3_CLUT_TBL (*(uint32_t*)0xFCFF6C00u)
+#define VDC5_CH0_GR_OIR_CLUT_TBL (*(uint32_t*)0xFCFF7000u)
+#define VDC5_CH1_GR0_CLUT_TBL (*(uint32_t*)0xFCFF8000u)
+#define VDC5_CH1_GR1_CLUT_TBL (*(uint32_t*)0xFCFF8400u)
+#define VDC5_CH1_GR2_CLUT_TBL (*(uint32_t*)0xFCFF8800u)
+#define VDC5_CH1_GR3_CLUT_TBL (*(uint32_t*)0xFCFF8C00u)
+#define VDC5_CH1_GR_OIR_CLUT_TBL (*(uint32_t*)0xFCFF9000u)
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+/* VDC5 input controller register address list */
+const vdc5_regaddr_input_ctrl_t vdc5_regaddr_input_ctrl[VDC5_CHANNEL_NUM] = {
+ { /* Channel 0 */
+ &VDC50.INP_UPDATE,
+ &VDC50.INP_SEL_CNT,
+ &VDC50.INP_EXT_SYNC_CNT,
+ &VDC50.INP_VSYNC_PH_ADJ,
+ &VDC50.INP_DLY_ADJ,
+ &VDC50.IMGCNT_UPDATE,
+ &VDC50.IMGCNT_NR_CNT0,
+ &VDC50.IMGCNT_NR_CNT1
+ },
+ { /* Channel 1 */
+ &VDC51.INP_UPDATE,
+ &VDC51.INP_SEL_CNT,
+ &VDC51.INP_EXT_SYNC_CNT,
+ &VDC51.INP_VSYNC_PH_ADJ,
+ &VDC51.INP_DLY_ADJ,
+ &VDC51.IMGCNT_UPDATE,
+ &VDC51.IMGCNT_NR_CNT0,
+ &VDC51.IMGCNT_NR_CNT1
+ }
+};
+
+/* VDC5 scaler register address list */
+const vdc5_regaddr_scaler_t vdc5_regaddr_scaler[VDC5_CHANNEL_NUM][VDC5_SC_TYPE_NUM] = {
+ { /* Channel 0 */
+ { /* SC0 */
+ &VDC50.SC0_SCL0_UPDATE,
+ &VDC50.SC0_SCL0_FRC1,
+ &VDC50.SC0_SCL0_FRC2,
+ &VDC50.SC0_SCL0_FRC3,
+ &VDC50.SC0_SCL0_FRC4,
+ &VDC50.SC0_SCL0_FRC5,
+ &VDC50.SC0_SCL0_FRC6,
+ &VDC50.SC0_SCL0_FRC7,
+ &VDC50.SC0_SCL0_FRC9,
+ &VDC50.SC0_SCL0_MON0,
+ &VDC50.SC0_SCL0_INT,
+ &VDC50.SC0_SCL0_DS1,
+ &VDC50.SC0_SCL0_DS2,
+ &VDC50.SC0_SCL0_DS3,
+ &VDC50.SC0_SCL0_DS4,
+ &VDC50.SC0_SCL0_DS5,
+ &VDC50.SC0_SCL0_DS6,
+ &VDC50.SC0_SCL0_DS7,
+ &VDC50.SC0_SCL0_US1,
+ &VDC50.SC0_SCL0_US2,
+ &VDC50.SC0_SCL0_US3,
+ &VDC50.SC0_SCL0_US4,
+ &VDC50.SC0_SCL0_US5,
+ &VDC50.SC0_SCL0_US6,
+ &VDC50.SC0_SCL0_US7,
+ &VDC50.SC0_SCL0_US8,
+ &VDC50.SC0_SCL0_OVR1,
+ &VDC50.SC0_SCL1_UPDATE,
+ &VDC50.SC0_SCL1_WR1,
+ &VDC50.SC0_SCL1_WR2,
+ &VDC50.SC0_SCL1_WR3,
+ &VDC50.SC0_SCL1_WR4,
+ &VDC50.SC0_SCL1_WR5,
+ &VDC50.SC0_SCL1_WR6,
+ &VDC50.SC0_SCL1_WR7,
+ &VDC50.SC0_SCL1_WR8,
+ &VDC50.SC0_SCL1_WR9,
+ &VDC50.SC0_SCL1_WR10,
+ &VDC50.SC0_SCL1_WR11,
+ &VDC50.SC0_SCL1_MON1,
+ &VDC50.SC0_SCL1_PBUF0,
+ &VDC50.SC0_SCL1_PBUF1,
+ &VDC50.SC0_SCL1_PBUF2,
+ &VDC50.SC0_SCL1_PBUF3,
+ &VDC50.SC0_SCL1_PBUF_FLD,
+ &VDC50.SC0_SCL1_PBUF_CNT
+ },
+ { /* SC1 */
+ &VDC50.SC1_SCL0_UPDATE,
+ &VDC50.SC1_SCL0_FRC1,
+ &VDC50.SC1_SCL0_FRC2,
+ &VDC50.SC1_SCL0_FRC3,
+ &VDC50.SC1_SCL0_FRC4,
+ &VDC50.SC1_SCL0_FRC5,
+ &VDC50.SC1_SCL0_FRC6,
+ &VDC50.SC1_SCL0_FRC7,
+ &VDC50.SC1_SCL0_FRC9,
+ &VDC50.SC1_SCL0_MON0,
+ &VDC50.SC1_SCL0_INT,
+ &VDC50.SC1_SCL0_DS1,
+ &VDC50.SC1_SCL0_DS2,
+ &VDC50.SC1_SCL0_DS3,
+ &VDC50.SC1_SCL0_DS4,
+ &VDC50.SC1_SCL0_DS5,
+ &VDC50.SC1_SCL0_DS6,
+ &VDC50.SC1_SCL0_DS7,
+ &VDC50.SC1_SCL0_US1,
+ &VDC50.SC1_SCL0_US2,
+ &VDC50.SC1_SCL0_US3,
+ &VDC50.SC1_SCL0_US4,
+ &VDC50.SC1_SCL0_US5,
+ &VDC50.SC1_SCL0_US6,
+ &VDC50.SC1_SCL0_US7,
+ &VDC50.SC1_SCL0_US8,
+ &VDC50.SC1_SCL0_OVR1,
+ &VDC50.SC1_SCL1_UPDATE,
+ &VDC50.SC1_SCL1_WR1,
+ &VDC50.SC1_SCL1_WR2,
+ &VDC50.SC1_SCL1_WR3,
+ &VDC50.SC1_SCL1_WR4,
+ &VDC50.SC1_SCL1_WR5,
+ &VDC50.SC1_SCL1_WR6,
+ &VDC50.SC1_SCL1_WR7,
+ &VDC50.SC1_SCL1_WR8,
+ &VDC50.SC1_SCL1_WR9,
+ &VDC50.SC1_SCL1_WR10,
+ &VDC50.SC1_SCL1_WR11,
+ &VDC50.SC1_SCL1_MON1,
+ &VDC50.SC1_SCL1_PBUF0,
+ &VDC50.SC1_SCL1_PBUF1,
+ &VDC50.SC1_SCL1_PBUF2,
+ &VDC50.SC1_SCL1_PBUF3,
+ &VDC50.SC1_SCL1_PBUF_FLD,
+ &VDC50.SC1_SCL1_PBUF_CNT
+ },
+ { /* OIR */
+ &VDC50.OIR_SCL0_UPDATE,
+ &VDC50.OIR_SCL0_FRC1,
+ &VDC50.OIR_SCL0_FRC2,
+ &VDC50.OIR_SCL0_FRC3,
+ &VDC50.OIR_SCL0_FRC4,
+ &VDC50.OIR_SCL0_FRC5,
+ &VDC50.OIR_SCL0_FRC6,
+ &VDC50.OIR_SCL0_FRC7,
+ NULL,
+ NULL,
+ NULL,
+ &VDC50.OIR_SCL0_DS1,
+ &VDC50.OIR_SCL0_DS2,
+ &VDC50.OIR_SCL0_DS3,
+ NULL,
+ NULL,
+ NULL,
+ &VDC50.OIR_SCL0_DS7,
+ &VDC50.OIR_SCL0_US1,
+ &VDC50.OIR_SCL0_US2,
+ &VDC50.OIR_SCL0_US3,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ &VDC50.OIR_SCL0_US8,
+ &VDC50.OIR_SCL0_OVR1,
+ &VDC50.OIR_SCL1_UPDATE,
+ &VDC50.OIR_SCL1_WR1,
+ &VDC50.OIR_SCL1_WR2,
+ &VDC50.OIR_SCL1_WR3,
+ &VDC50.OIR_SCL1_WR4,
+ &VDC50.OIR_SCL1_WR5,
+ &VDC50.OIR_SCL1_WR6,
+ &VDC50.OIR_SCL1_WR7,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL
+ }
+ },
+ { /* Channel 1 */
+ { /* SC0 */
+ &VDC51.SC0_SCL0_UPDATE,
+ &VDC51.SC0_SCL0_FRC1,
+ &VDC51.SC0_SCL0_FRC2,
+ &VDC51.SC0_SCL0_FRC3,
+ &VDC51.SC0_SCL0_FRC4,
+ &VDC51.SC0_SCL0_FRC5,
+ &VDC51.SC0_SCL0_FRC6,
+ &VDC51.SC0_SCL0_FRC7,
+ &VDC51.SC0_SCL0_FRC9,
+ &VDC51.SC0_SCL0_MON0,
+ &VDC51.SC0_SCL0_INT,
+ &VDC51.SC0_SCL0_DS1,
+ &VDC51.SC0_SCL0_DS2,
+ &VDC51.SC0_SCL0_DS3,
+ &VDC51.SC0_SCL0_DS4,
+ &VDC51.SC0_SCL0_DS5,
+ &VDC51.SC0_SCL0_DS6,
+ &VDC51.SC0_SCL0_DS7,
+ &VDC51.SC0_SCL0_US1,
+ &VDC51.SC0_SCL0_US2,
+ &VDC51.SC0_SCL0_US3,
+ &VDC51.SC0_SCL0_US4,
+ &VDC51.SC0_SCL0_US5,
+ &VDC51.SC0_SCL0_US6,
+ &VDC51.SC0_SCL0_US7,
+ &VDC51.SC0_SCL0_US8,
+ &VDC51.SC0_SCL0_OVR1,
+ &VDC51.SC0_SCL1_UPDATE,
+ &VDC51.SC0_SCL1_WR1,
+ &VDC51.SC0_SCL1_WR2,
+ &VDC51.SC0_SCL1_WR3,
+ &VDC51.SC0_SCL1_WR4,
+ &VDC51.SC0_SCL1_WR5,
+ &VDC51.SC0_SCL1_WR6,
+ &VDC51.SC0_SCL1_WR7,
+ &VDC51.SC0_SCL1_WR8,
+ &VDC51.SC0_SCL1_WR9,
+ &VDC51.SC0_SCL1_WR10,
+ &VDC51.SC0_SCL1_WR11,
+ &VDC51.SC0_SCL1_MON1,
+ &VDC51.SC0_SCL1_PBUF0,
+ &VDC51.SC0_SCL1_PBUF1,
+ &VDC51.SC0_SCL1_PBUF2,
+ &VDC51.SC0_SCL1_PBUF3,
+ &VDC51.SC0_SCL1_PBUF_FLD,
+ &VDC51.SC0_SCL1_PBUF_CNT
+ },
+ { /* SC1 */
+ &VDC51.SC1_SCL0_UPDATE,
+ &VDC51.SC1_SCL0_FRC1,
+ &VDC51.SC1_SCL0_FRC2,
+ &VDC51.SC1_SCL0_FRC3,
+ &VDC51.SC1_SCL0_FRC4,
+ &VDC51.SC1_SCL0_FRC5,
+ &VDC51.SC1_SCL0_FRC6,
+ &VDC51.SC1_SCL0_FRC7,
+ &VDC51.SC1_SCL0_FRC9,
+ &VDC51.SC1_SCL0_MON0,
+ &VDC51.SC1_SCL0_INT,
+ &VDC51.SC1_SCL0_DS1,
+ &VDC51.SC1_SCL0_DS2,
+ &VDC51.SC1_SCL0_DS3,
+ &VDC51.SC1_SCL0_DS4,
+ &VDC51.SC1_SCL0_DS5,
+ &VDC51.SC1_SCL0_DS6,
+ &VDC51.SC1_SCL0_DS7,
+ &VDC51.SC1_SCL0_US1,
+ &VDC51.SC1_SCL0_US2,
+ &VDC51.SC1_SCL0_US3,
+ &VDC51.SC1_SCL0_US4,
+ &VDC51.SC1_SCL0_US5,
+ &VDC51.SC1_SCL0_US6,
+ &VDC51.SC1_SCL0_US7,
+ &VDC51.SC1_SCL0_US8,
+ &VDC51.SC1_SCL0_OVR1,
+ &VDC51.SC1_SCL1_UPDATE,
+ &VDC51.SC1_SCL1_WR1,
+ &VDC51.SC1_SCL1_WR2,
+ &VDC51.SC1_SCL1_WR3,
+ &VDC51.SC1_SCL1_WR4,
+ &VDC51.SC1_SCL1_WR5,
+ &VDC51.SC1_SCL1_WR6,
+ &VDC51.SC1_SCL1_WR7,
+ &VDC51.SC1_SCL1_WR8,
+ &VDC51.SC1_SCL1_WR9,
+ &VDC51.SC1_SCL1_WR10,
+ &VDC51.SC1_SCL1_WR11,
+ &VDC51.SC1_SCL1_MON1,
+ &VDC51.SC1_SCL1_PBUF0,
+ &VDC51.SC1_SCL1_PBUF1,
+ &VDC51.SC1_SCL1_PBUF2,
+ &VDC51.SC1_SCL1_PBUF3,
+ &VDC51.SC1_SCL1_PBUF_FLD,
+ &VDC51.SC1_SCL1_PBUF_CNT
+ },
+ { /* OIR */
+ &VDC51.OIR_SCL0_UPDATE,
+ &VDC51.OIR_SCL0_FRC1,
+ &VDC51.OIR_SCL0_FRC2,
+ &VDC51.OIR_SCL0_FRC3,
+ &VDC51.OIR_SCL0_FRC4,
+ &VDC51.OIR_SCL0_FRC5,
+ &VDC51.OIR_SCL0_FRC6,
+ &VDC51.OIR_SCL0_FRC7,
+ NULL,
+ NULL,
+ NULL,
+ &VDC51.OIR_SCL0_DS1,
+ &VDC51.OIR_SCL0_DS2,
+ &VDC51.OIR_SCL0_DS3,
+ NULL,
+ NULL,
+ NULL,
+ &VDC51.OIR_SCL0_DS7,
+ &VDC51.OIR_SCL0_US1,
+ &VDC51.OIR_SCL0_US2,
+ &VDC51.OIR_SCL0_US3,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ &VDC51.OIR_SCL0_US8,
+ &VDC51.OIR_SCL0_OVR1,
+ &VDC51.OIR_SCL1_UPDATE,
+ &VDC51.OIR_SCL1_WR1,
+ &VDC51.OIR_SCL1_WR2,
+ &VDC51.OIR_SCL1_WR3,
+ &VDC51.OIR_SCL1_WR4,
+ &VDC51.OIR_SCL1_WR5,
+ &VDC51.OIR_SCL1_WR6,
+ &VDC51.OIR_SCL1_WR7,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL
+ }
+ }
+};
+
+/* VDC5 image quality improver register address list */
+const vdc5_regaddr_img_qlty_imp_t vdc5_regaddr_img_qlty_imp[VDC5_CHANNEL_NUM][VDC5_IMG_IMPRV_NUM] = {
+ { /* Channel 0 */
+ { /* SC0 */
+ &VDC50.ADJ0_UPDATE,
+ &VDC50.ADJ0_BKSTR_SET,
+ &VDC50.ADJ0_ENH_TIM1,
+ &VDC50.ADJ0_ENH_TIM2,
+ &VDC50.ADJ0_ENH_TIM3,
+ &VDC50.ADJ0_ENH_SHP1,
+ &VDC50.ADJ0_ENH_SHP2,
+ &VDC50.ADJ0_ENH_SHP3,
+ &VDC50.ADJ0_ENH_SHP4,
+ &VDC50.ADJ0_ENH_SHP5,
+ &VDC50.ADJ0_ENH_SHP6,
+ &VDC50.ADJ0_ENH_LTI1,
+ &VDC50.ADJ0_ENH_LTI2
+ },
+ { /* SC1 */
+ &VDC50.ADJ1_UPDATE,
+ &VDC50.ADJ1_BKSTR_SET,
+ &VDC50.ADJ1_ENH_TIM1,
+ &VDC50.ADJ1_ENH_TIM2,
+ &VDC50.ADJ1_ENH_TIM3,
+ &VDC50.ADJ1_ENH_SHP1,
+ &VDC50.ADJ1_ENH_SHP2,
+ &VDC50.ADJ1_ENH_SHP3,
+ &VDC50.ADJ1_ENH_SHP4,
+ &VDC50.ADJ1_ENH_SHP5,
+ &VDC50.ADJ1_ENH_SHP6,
+ &VDC50.ADJ1_ENH_LTI1,
+ &VDC50.ADJ1_ENH_LTI2
+ }
+ },
+ { /* Channel 1 */
+ { /* SC0 */
+ &VDC51.ADJ0_UPDATE,
+ &VDC51.ADJ0_BKSTR_SET,
+ &VDC51.ADJ0_ENH_TIM1,
+ &VDC51.ADJ0_ENH_TIM2,
+ &VDC51.ADJ0_ENH_TIM3,
+ &VDC51.ADJ0_ENH_SHP1,
+ &VDC51.ADJ0_ENH_SHP2,
+ &VDC51.ADJ0_ENH_SHP3,
+ &VDC51.ADJ0_ENH_SHP4,
+ &VDC51.ADJ0_ENH_SHP5,
+ &VDC51.ADJ0_ENH_SHP6,
+ &VDC51.ADJ0_ENH_LTI1,
+ &VDC51.ADJ0_ENH_LTI2
+ },
+ { /* SC1 */
+ &VDC51.ADJ1_UPDATE,
+ &VDC51.ADJ1_BKSTR_SET,
+ &VDC51.ADJ1_ENH_TIM1,
+ &VDC51.ADJ1_ENH_TIM2,
+ &VDC51.ADJ1_ENH_TIM3,
+ &VDC51.ADJ1_ENH_SHP1,
+ &VDC51.ADJ1_ENH_SHP2,
+ &VDC51.ADJ1_ENH_SHP3,
+ &VDC51.ADJ1_ENH_SHP4,
+ &VDC51.ADJ1_ENH_SHP5,
+ &VDC51.ADJ1_ENH_SHP6,
+ &VDC51.ADJ1_ENH_LTI1,
+ &VDC51.ADJ1_ENH_LTI2
+ }
+ }
+};
+
+/* VDC5 color matrix register address list */
+const vdc5_regaddr_color_matrix_t vdc5_regaddr_color_matrix[VDC5_CHANNEL_NUM][VDC5_COLORMTX_NUM] = {
+ { /* Channel 0 */
+ { /* Input Controller */
+ &VDC50.IMGCNT_UPDATE,
+ &VDC50.IMGCNT_MTX_MODE,
+ &VDC50.IMGCNT_MTX_YG_ADJ0,
+ &VDC50.IMGCNT_MTX_YG_ADJ1,
+ &VDC50.IMGCNT_MTX_CBB_ADJ0,
+ &VDC50.IMGCNT_MTX_CBB_ADJ1,
+ &VDC50.IMGCNT_MTX_CRR_ADJ0,
+ &VDC50.IMGCNT_MTX_CRR_ADJ1
+ },
+ { /* Image quality improver 0 */
+ &VDC50.ADJ0_UPDATE,
+ &VDC50.ADJ0_MTX_MODE,
+ &VDC50.ADJ0_MTX_YG_ADJ0,
+ &VDC50.ADJ0_MTX_YG_ADJ1,
+ &VDC50.ADJ0_MTX_CBB_ADJ0,
+ &VDC50.ADJ0_MTX_CBB_ADJ1,
+ &VDC50.ADJ0_MTX_CRR_ADJ0,
+ &VDC50.ADJ0_MTX_CRR_ADJ1
+ },
+ { /* Image quality improver 1 */
+ &VDC50.ADJ1_UPDATE,
+ &VDC50.ADJ1_MTX_MODE,
+ &VDC50.ADJ1_MTX_YG_ADJ0,
+ &VDC50.ADJ1_MTX_YG_ADJ1,
+ &VDC50.ADJ1_MTX_CBB_ADJ0,
+ &VDC50.ADJ1_MTX_CBB_ADJ1,
+ &VDC50.ADJ1_MTX_CRR_ADJ0,
+ &VDC50.ADJ1_MTX_CRR_ADJ1
+ }
+ },
+ { /* Channel 1 */
+ { /* Input Controller */
+ &VDC51.IMGCNT_UPDATE,
+ &VDC51.IMGCNT_MTX_MODE,
+ &VDC51.IMGCNT_MTX_YG_ADJ0,
+ &VDC51.IMGCNT_MTX_YG_ADJ1,
+ &VDC51.IMGCNT_MTX_CBB_ADJ0,
+ &VDC51.IMGCNT_MTX_CBB_ADJ1,
+ &VDC51.IMGCNT_MTX_CRR_ADJ0,
+ &VDC51.IMGCNT_MTX_CRR_ADJ1
+ },
+ { /* Image quality improver 0 */
+ &VDC51.ADJ0_UPDATE,
+ &VDC51.ADJ0_MTX_MODE,
+ &VDC51.ADJ0_MTX_YG_ADJ0,
+ &VDC51.ADJ0_MTX_YG_ADJ1,
+ &VDC51.ADJ0_MTX_CBB_ADJ0,
+ &VDC51.ADJ0_MTX_CBB_ADJ1,
+ &VDC51.ADJ0_MTX_CRR_ADJ0,
+ &VDC51.ADJ0_MTX_CRR_ADJ1
+ },
+ { /* Image quality improver 1 */
+ &VDC51.ADJ1_UPDATE,
+ &VDC51.ADJ1_MTX_MODE,
+ &VDC51.ADJ1_MTX_YG_ADJ0,
+ &VDC51.ADJ1_MTX_YG_ADJ1,
+ &VDC51.ADJ1_MTX_CBB_ADJ0,
+ &VDC51.ADJ1_MTX_CBB_ADJ1,
+ &VDC51.ADJ1_MTX_CRR_ADJ0,
+ &VDC51.ADJ1_MTX_CRR_ADJ1
+ }
+ }
+};
+
+/* VDC5 image synthesizer register address list */
+const vdc5_regaddr_img_synthesizer_t vdc5_regaddr_img_synthesizer[VDC5_CHANNEL_NUM][VDC5_GR_TYPE_NUM] = {
+ { /* Channel 0 */
+ { /* GR0 */
+ &VDC50.GR0_UPDATE,
+ &VDC50.GR0_FLM_RD,
+ &VDC50.GR0_FLM1,
+ &VDC50.GR0_FLM2,
+ &VDC50.GR0_FLM3,
+ &VDC50.GR0_FLM4,
+ &VDC50.GR0_FLM5,
+ &VDC50.GR0_FLM6,
+ &VDC50.GR0_AB1,
+ &VDC50.GR0_AB2,
+ &VDC50.GR0_AB3,
+ NULL,
+ NULL,
+ NULL,
+ &VDC50.GR0_AB7,
+ &VDC50.GR0_AB8,
+ &VDC50.GR0_AB9,
+ &VDC50.GR0_AB10,
+ &VDC50.GR0_AB11,
+ &VDC50.GR0_BASE,
+ &VDC50.GR0_CLUT,
+ NULL
+ },
+ { /* GR1 */
+ &VDC50.GR1_UPDATE,
+ &VDC50.GR1_FLM_RD,
+ &VDC50.GR1_FLM1,
+ &VDC50.GR1_FLM2,
+ &VDC50.GR1_FLM3,
+ &VDC50.GR1_FLM4,
+ &VDC50.GR1_FLM5,
+ &VDC50.GR1_FLM6,
+ &VDC50.GR1_AB1,
+ &VDC50.GR1_AB2,
+ &VDC50.GR1_AB3,
+ &VDC50.GR1_AB4,
+ &VDC50.GR1_AB5,
+ &VDC50.GR1_AB6,
+ &VDC50.GR1_AB7,
+ &VDC50.GR1_AB8,
+ &VDC50.GR1_AB9,
+ &VDC50.GR1_AB10,
+ &VDC50.GR1_AB11,
+ &VDC50.GR1_BASE,
+ &VDC50.GR1_CLUT,
+ &VDC50.GR1_MON
+ },
+ { /* GR2 */
+ &VDC50.GR2_UPDATE,
+ &VDC50.GR2_FLM_RD,
+ &VDC50.GR2_FLM1,
+ &VDC50.GR2_FLM2,
+ &VDC50.GR2_FLM3,
+ &VDC50.GR2_FLM4,
+ &VDC50.GR2_FLM5,
+ &VDC50.GR2_FLM6,
+ &VDC50.GR2_AB1,
+ &VDC50.GR2_AB2,
+ &VDC50.GR2_AB3,
+ &VDC50.GR2_AB4,
+ &VDC50.GR2_AB5,
+ &VDC50.GR2_AB6,
+ &VDC50.GR2_AB7,
+ &VDC50.GR2_AB8,
+ &VDC50.GR2_AB9,
+ &VDC50.GR2_AB10,
+ &VDC50.GR2_AB11,
+ &VDC50.GR2_BASE,
+ &VDC50.GR2_CLUT,
+ &VDC50.GR2_MON
+ },
+ { /* GR3 */
+ &VDC50.GR3_UPDATE,
+ &VDC50.GR3_FLM_RD,
+ &VDC50.GR3_FLM1,
+ &VDC50.GR3_FLM2,
+ &VDC50.GR3_FLM3,
+ &VDC50.GR3_FLM4,
+ &VDC50.GR3_FLM5,
+ &VDC50.GR3_FLM6,
+ &VDC50.GR3_AB1,
+ &VDC50.GR3_AB2,
+ &VDC50.GR3_AB3,
+ &VDC50.GR3_AB4,
+ &VDC50.GR3_AB5,
+ &VDC50.GR3_AB6,
+ &VDC50.GR3_AB7,
+ &VDC50.GR3_AB8,
+ &VDC50.GR3_AB9,
+ &VDC50.GR3_AB10,
+ &VDC50.GR3_AB11,
+ &VDC50.GR3_BASE,
+ &VDC50.GR3_CLUT_INT,
+ &VDC50.GR3_MON
+ },
+ { /* VIN */
+ &VDC50.GR_VIN_UPDATE,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ &VDC50.GR_VIN_AB1,
+ &VDC50.GR_VIN_AB2,
+ &VDC50.GR_VIN_AB3,
+ &VDC50.GR_VIN_AB4,
+ &VDC50.GR_VIN_AB5,
+ &VDC50.GR_VIN_AB6,
+ &VDC50.GR_VIN_AB7,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ &VDC50.GR_VIN_BASE,
+ NULL,
+ &VDC50.GR_VIN_MON
+ },
+ { /* OIR */
+ &VDC50.GR_OIR_UPDATE,
+ &VDC50.GR_OIR_FLM_RD,
+ &VDC50.GR_OIR_FLM1,
+ &VDC50.GR_OIR_FLM2,
+ &VDC50.GR_OIR_FLM3,
+ &VDC50.GR_OIR_FLM4,
+ &VDC50.GR_OIR_FLM5,
+ &VDC50.GR_OIR_FLM6,
+ &VDC50.GR_OIR_AB1,
+ &VDC50.GR_OIR_AB2,
+ &VDC50.GR_OIR_AB3,
+ NULL,
+ NULL,
+ NULL,
+ &VDC50.GR_OIR_AB7,
+ &VDC50.GR_OIR_AB8,
+ &VDC50.GR_OIR_AB9,
+ &VDC50.GR_OIR_AB10,
+ &VDC50.GR_OIR_AB11,
+ &VDC50.GR_OIR_BASE,
+ &VDC50.GR_OIR_CLUT,
+ &VDC50.GR_OIR_MON
+ }
+ },
+ { /* Channel 1 */
+ { /* GR0 */
+ &VDC51.GR0_UPDATE,
+ &VDC51.GR0_FLM_RD,
+ &VDC51.GR0_FLM1,
+ &VDC51.GR0_FLM2,
+ &VDC51.GR0_FLM3,
+ &VDC51.GR0_FLM4,
+ &VDC51.GR0_FLM5,
+ &VDC51.GR0_FLM6,
+ &VDC51.GR0_AB1,
+ &VDC51.GR0_AB2,
+ &VDC51.GR0_AB3,
+ NULL,
+ NULL,
+ NULL,
+ &VDC51.GR0_AB7,
+ &VDC51.GR0_AB8,
+ &VDC51.GR0_AB9,
+ &VDC51.GR0_AB10,
+ &VDC51.GR0_AB11,
+ &VDC51.GR0_BASE,
+ &VDC51.GR0_CLUT,
+ NULL
+ },
+ { /* GR1 */
+ &VDC51.GR1_UPDATE,
+ &VDC51.GR1_FLM_RD,
+ &VDC51.GR1_FLM1,
+ &VDC51.GR1_FLM2,
+ &VDC51.GR1_FLM3,
+ &VDC51.GR1_FLM4,
+ &VDC51.GR1_FLM5,
+ &VDC51.GR1_FLM6,
+ &VDC51.GR1_AB1,
+ &VDC51.GR1_AB2,
+ &VDC51.GR1_AB3,
+ &VDC51.GR1_AB4,
+ &VDC51.GR1_AB5,
+ &VDC51.GR1_AB6,
+ &VDC51.GR1_AB7,
+ &VDC51.GR1_AB8,
+ &VDC51.GR1_AB9,
+ &VDC51.GR1_AB10,
+ &VDC51.GR1_AB11,
+ &VDC51.GR1_BASE,
+ &VDC51.GR1_CLUT,
+ &VDC51.GR1_MON
+ },
+ { /* GR2 */
+ &VDC51.GR2_UPDATE,
+ &VDC51.GR2_FLM_RD,
+ &VDC51.GR2_FLM1,
+ &VDC51.GR2_FLM2,
+ &VDC51.GR2_FLM3,
+ &VDC51.GR2_FLM4,
+ &VDC51.GR2_FLM5,
+ &VDC51.GR2_FLM6,
+ &VDC51.GR2_AB1,
+ &VDC51.GR2_AB2,
+ &VDC51.GR2_AB3,
+ &VDC51.GR2_AB4,
+ &VDC51.GR2_AB5,
+ &VDC51.GR2_AB6,
+ &VDC51.GR2_AB7,
+ &VDC51.GR2_AB8,
+ &VDC51.GR2_AB9,
+ &VDC51.GR2_AB10,
+ &VDC51.GR2_AB11,
+ &VDC51.GR2_BASE,
+ &VDC51.GR2_CLUT,
+ &VDC51.GR2_MON
+ },
+ { /* GR3 */
+ &VDC51.GR3_UPDATE,
+ &VDC51.GR3_FLM_RD,
+ &VDC51.GR3_FLM1,
+ &VDC51.GR3_FLM2,
+ &VDC51.GR3_FLM3,
+ &VDC51.GR3_FLM4,
+ &VDC51.GR3_FLM5,
+ &VDC51.GR3_FLM6,
+ &VDC51.GR3_AB1,
+ &VDC51.GR3_AB2,
+ &VDC51.GR3_AB3,
+ &VDC51.GR3_AB4,
+ &VDC51.GR3_AB5,
+ &VDC51.GR3_AB6,
+ &VDC51.GR3_AB7,
+ &VDC51.GR3_AB8,
+ &VDC51.GR3_AB9,
+ &VDC51.GR3_AB10,
+ &VDC51.GR3_AB11,
+ &VDC51.GR3_BASE,
+ &VDC51.GR3_CLUT_INT,
+ &VDC51.GR3_MON
+ },
+ { /* VIN */
+ &VDC51.GR_VIN_UPDATE,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ &VDC51.GR_VIN_AB1,
+ &VDC51.GR_VIN_AB2,
+ &VDC51.GR_VIN_AB3,
+ &VDC51.GR_VIN_AB4,
+ &VDC51.GR_VIN_AB5,
+ &VDC51.GR_VIN_AB6,
+ &VDC51.GR_VIN_AB7,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ &VDC51.GR_VIN_BASE,
+ NULL,
+ &VDC51.GR_VIN_MON
+ },
+ { /* OIR */
+ &VDC51.GR_OIR_UPDATE,
+ &VDC51.GR_OIR_FLM_RD,
+ &VDC51.GR_OIR_FLM1,
+ &VDC51.GR_OIR_FLM2,
+ &VDC51.GR_OIR_FLM3,
+ &VDC51.GR_OIR_FLM4,
+ &VDC51.GR_OIR_FLM5,
+ &VDC51.GR_OIR_FLM6,
+ &VDC51.GR_OIR_AB1,
+ &VDC51.GR_OIR_AB2,
+ &VDC51.GR_OIR_AB3,
+ NULL,
+ NULL,
+ NULL,
+ &VDC51.GR_OIR_AB7,
+ &VDC51.GR_OIR_AB8,
+ &VDC51.GR_OIR_AB9,
+ &VDC51.GR_OIR_AB10,
+ &VDC51.GR_OIR_AB11,
+ &VDC51.GR_OIR_BASE,
+ &VDC51.GR_OIR_CLUT,
+ &VDC51.GR_OIR_MON
+ }
+ }
+};
+
+/* VDC5 CLUT register address list */
+uint32_t * const vdc5_regaddr_clut[VDC5_CHANNEL_NUM][VDC5_GR_TYPE_NUM] = {
+ { /* Channel 0 */
+ &VDC5_CH0_GR0_CLUT_TBL,
+ &VDC5_CH0_GR1_CLUT_TBL,
+ &VDC5_CH0_GR2_CLUT_TBL,
+ &VDC5_CH0_GR3_CLUT_TBL,
+ NULL,
+ &VDC5_CH0_GR_OIR_CLUT_TBL
+ },
+ { /* Channel 1 */
+ &VDC5_CH1_GR0_CLUT_TBL,
+ &VDC5_CH1_GR1_CLUT_TBL,
+ &VDC5_CH1_GR2_CLUT_TBL,
+ &VDC5_CH1_GR3_CLUT_TBL,
+ NULL,
+ &VDC5_CH1_GR_OIR_CLUT_TBL
+ }
+};
+
+/* VDC5 output controller register address list */
+const vdc5_regaddr_output_ctrl_t vdc5_regaddr_output_ctrl[VDC5_CHANNEL_NUM] = {
+ { /* Channel 0 */
+ &VDC50.TCON_UPDATE,
+ &VDC50.TCON_TIM,
+ &VDC50.TCON_TIM_STVA1,
+ &VDC50.TCON_TIM_STVA2,
+ &VDC50.TCON_TIM_STVB1,
+ &VDC50.TCON_TIM_STVB2,
+ &VDC50.TCON_TIM_STH1,
+ &VDC50.TCON_TIM_STH2,
+ &VDC50.TCON_TIM_STB1,
+ &VDC50.TCON_TIM_STB2,
+ &VDC50.TCON_TIM_CPV1,
+ &VDC50.TCON_TIM_CPV2,
+ &VDC50.TCON_TIM_POLA1,
+ &VDC50.TCON_TIM_POLA2,
+ &VDC50.TCON_TIM_POLB1,
+ &VDC50.TCON_TIM_POLB2,
+ &VDC50.TCON_TIM_DE,
+ &VDC50.OUT_UPDATE,
+ &VDC50.OUT_SET,
+ &VDC50.OUT_BRIGHT1,
+ &VDC50.OUT_BRIGHT2,
+ &VDC50.OUT_CONTRAST,
+ &VDC50.OUT_PDTHA,
+ &VDC50.OUT_CLK_PHASE
+ },
+ { /* Channel 1 */
+ &VDC51.TCON_UPDATE,
+ &VDC51.TCON_TIM,
+ &VDC51.TCON_TIM_STVA1,
+ &VDC51.TCON_TIM_STVA2,
+ &VDC51.TCON_TIM_STVB1,
+ &VDC51.TCON_TIM_STVB2,
+ &VDC51.TCON_TIM_STH1,
+ &VDC51.TCON_TIM_STH2,
+ &VDC51.TCON_TIM_STB1,
+ &VDC51.TCON_TIM_STB2,
+ &VDC51.TCON_TIM_CPV1,
+ &VDC51.TCON_TIM_CPV2,
+ &VDC51.TCON_TIM_POLA1,
+ &VDC51.TCON_TIM_POLA2,
+ &VDC51.TCON_TIM_POLB1,
+ &VDC51.TCON_TIM_POLB2,
+ &VDC51.TCON_TIM_DE,
+ &VDC51.OUT_UPDATE,
+ &VDC51.OUT_SET,
+ &VDC51.OUT_BRIGHT1,
+ &VDC51.OUT_BRIGHT2,
+ &VDC51.OUT_CONTRAST,
+ &VDC51.OUT_PDTHA,
+ &VDC51.OUT_CLK_PHASE
+ }
+};
+
+/* VDC5 gamma correction register address list */
+const vdc5_regaddr_gamma_t vdc5_regaddr_gamma[VDC5_CHANNEL_NUM] = {
+ { /* Channel 0 */
+ &VDC50.GAM_SW,
+ &VDC50.GAM_G_UPDATE,
+ {
+ &VDC50.GAM_G_LUT1,
+ &VDC50.GAM_G_LUT2,
+ &VDC50.GAM_G_LUT3,
+ &VDC50.GAM_G_LUT4,
+ &VDC50.GAM_G_LUT5,
+ &VDC50.GAM_G_LUT6,
+ &VDC50.GAM_G_LUT7,
+ &VDC50.GAM_G_LUT8,
+ &VDC50.GAM_G_LUT9,
+ &VDC50.GAM_G_LUT10,
+ &VDC50.GAM_G_LUT11,
+ &VDC50.GAM_G_LUT12,
+ &VDC50.GAM_G_LUT13,
+ &VDC50.GAM_G_LUT14,
+ &VDC50.GAM_G_LUT15,
+ &VDC50.GAM_G_LUT16
+ },
+ {
+ &VDC50.GAM_G_AREA1,
+ &VDC50.GAM_G_AREA2,
+ &VDC50.GAM_G_AREA3,
+ &VDC50.GAM_G_AREA4,
+ &VDC50.GAM_G_AREA5,
+ &VDC50.GAM_G_AREA6,
+ &VDC50.GAM_G_AREA7,
+ &VDC50.GAM_G_AREA8
+ },
+ &VDC50.GAM_B_UPDATE,
+ {
+ &VDC50.GAM_B_LUT1,
+ &VDC50.GAM_B_LUT2,
+ &VDC50.GAM_B_LUT3,
+ &VDC50.GAM_B_LUT4,
+ &VDC50.GAM_B_LUT5,
+ &VDC50.GAM_B_LUT6,
+ &VDC50.GAM_B_LUT7,
+ &VDC50.GAM_B_LUT8,
+ &VDC50.GAM_B_LUT9,
+ &VDC50.GAM_B_LUT10,
+ &VDC50.GAM_B_LUT11,
+ &VDC50.GAM_B_LUT12,
+ &VDC50.GAM_B_LUT13,
+ &VDC50.GAM_B_LUT14,
+ &VDC50.GAM_B_LUT15,
+ &VDC50.GAM_B_LUT16
+ },
+ {
+ &VDC50.GAM_B_AREA1,
+ &VDC50.GAM_B_AREA2,
+ &VDC50.GAM_B_AREA3,
+ &VDC50.GAM_B_AREA4,
+ &VDC50.GAM_B_AREA5,
+ &VDC50.GAM_B_AREA6,
+ &VDC50.GAM_B_AREA7,
+ &VDC50.GAM_B_AREA8
+ },
+ &VDC50.GAM_R_UPDATE,
+ {
+ &VDC50.GAM_R_LUT1,
+ &VDC50.GAM_R_LUT2,
+ &VDC50.GAM_R_LUT3,
+ &VDC50.GAM_R_LUT4,
+ &VDC50.GAM_R_LUT5,
+ &VDC50.GAM_R_LUT6,
+ &VDC50.GAM_R_LUT7,
+ &VDC50.GAM_R_LUT8,
+ &VDC50.GAM_R_LUT9,
+ &VDC50.GAM_R_LUT10,
+ &VDC50.GAM_R_LUT11,
+ &VDC50.GAM_R_LUT12,
+ &VDC50.GAM_R_LUT13,
+ &VDC50.GAM_R_LUT14,
+ &VDC50.GAM_R_LUT15,
+ &VDC50.GAM_R_LUT16
+ },
+ {
+ &VDC50.GAM_R_AREA1,
+ &VDC50.GAM_R_AREA2,
+ &VDC50.GAM_R_AREA3,
+ &VDC50.GAM_R_AREA4,
+ &VDC50.GAM_R_AREA5,
+ &VDC50.GAM_R_AREA6,
+ &VDC50.GAM_R_AREA7,
+ &VDC50.GAM_R_AREA8
+ }
+ },
+ { /* Channel 1 */
+ &VDC51.GAM_SW,
+ &VDC51.GAM_G_UPDATE,
+ {
+ &VDC51.GAM_G_LUT1,
+ &VDC51.GAM_G_LUT2,
+ &VDC51.GAM_G_LUT3,
+ &VDC51.GAM_G_LUT4,
+ &VDC51.GAM_G_LUT5,
+ &VDC51.GAM_G_LUT6,
+ &VDC51.GAM_G_LUT7,
+ &VDC51.GAM_G_LUT8,
+ &VDC51.GAM_G_LUT9,
+ &VDC51.GAM_G_LUT10,
+ &VDC51.GAM_G_LUT11,
+ &VDC51.GAM_G_LUT12,
+ &VDC51.GAM_G_LUT13,
+ &VDC51.GAM_G_LUT14,
+ &VDC51.GAM_G_LUT15,
+ &VDC51.GAM_G_LUT16
+ },
+ {
+ &VDC51.GAM_G_AREA1,
+ &VDC51.GAM_G_AREA2,
+ &VDC51.GAM_G_AREA3,
+ &VDC51.GAM_G_AREA4,
+ &VDC51.GAM_G_AREA5,
+ &VDC51.GAM_G_AREA6,
+ &VDC51.GAM_G_AREA7,
+ &VDC51.GAM_G_AREA8
+ },
+ &VDC51.GAM_B_UPDATE,
+ {
+ &VDC51.GAM_B_LUT1,
+ &VDC51.GAM_B_LUT2,
+ &VDC51.GAM_B_LUT3,
+ &VDC51.GAM_B_LUT4,
+ &VDC51.GAM_B_LUT5,
+ &VDC51.GAM_B_LUT6,
+ &VDC51.GAM_B_LUT7,
+ &VDC51.GAM_B_LUT8,
+ &VDC51.GAM_B_LUT9,
+ &VDC51.GAM_B_LUT10,
+ &VDC51.GAM_B_LUT11,
+ &VDC51.GAM_B_LUT12,
+ &VDC51.GAM_B_LUT13,
+ &VDC51.GAM_B_LUT14,
+ &VDC51.GAM_B_LUT15,
+ &VDC51.GAM_B_LUT16
+ },
+ {
+ &VDC51.GAM_B_AREA1,
+ &VDC51.GAM_B_AREA2,
+ &VDC51.GAM_B_AREA3,
+ &VDC51.GAM_B_AREA4,
+ &VDC51.GAM_B_AREA5,
+ &VDC51.GAM_B_AREA6,
+ &VDC51.GAM_B_AREA7,
+ &VDC51.GAM_B_AREA8
+ },
+ &VDC51.GAM_R_UPDATE,
+ {
+ &VDC51.GAM_R_LUT1,
+ &VDC51.GAM_R_LUT2,
+ &VDC51.GAM_R_LUT3,
+ &VDC51.GAM_R_LUT4,
+ &VDC51.GAM_R_LUT5,
+ &VDC51.GAM_R_LUT6,
+ &VDC51.GAM_R_LUT7,
+ &VDC51.GAM_R_LUT8,
+ &VDC51.GAM_R_LUT9,
+ &VDC51.GAM_R_LUT10,
+ &VDC51.GAM_R_LUT11,
+ &VDC51.GAM_R_LUT12,
+ &VDC51.GAM_R_LUT13,
+ &VDC51.GAM_R_LUT14,
+ &VDC51.GAM_R_LUT15,
+ &VDC51.GAM_R_LUT16
+ },
+ {
+ &VDC51.GAM_R_AREA1,
+ &VDC51.GAM_R_AREA2,
+ &VDC51.GAM_R_AREA3,
+ &VDC51.GAM_R_AREA4,
+ &VDC51.GAM_R_AREA5,
+ &VDC51.GAM_R_AREA6,
+ &VDC51.GAM_R_AREA7,
+ &VDC51.GAM_R_AREA8
+ }
+ }
+};
+
+/* VDC5 system controller register address list */
+const vdc5_regaddr_system_ctrl_t vdc5_regaddr_system_ctrl[VDC5_CHANNEL_NUM] = {
+ { /* Channel 0 */
+ &VDC50.SYSCNT_INT1,
+ &VDC50.SYSCNT_INT2,
+ &VDC50.SYSCNT_INT3,
+ &VDC50.SYSCNT_INT4,
+ &VDC50.SYSCNT_INT5,
+ &VDC50.SYSCNT_INT6,
+ &VDC50.SYSCNT_PANEL_CLK,
+ &VDC50.SYSCNT_CLUT
+ },
+ { /* Channel 1 */
+ &VDC51.SYSCNT_INT1,
+ &VDC51.SYSCNT_INT2,
+ &VDC51.SYSCNT_INT3,
+ &VDC51.SYSCNT_INT4,
+ &VDC51.SYSCNT_INT5,
+ &VDC51.SYSCNT_INT6,
+ &VDC51.SYSCNT_PANEL_CLK,
+ &VDC51.SYSCNT_CLUT
+ }
+};
+
+/* LVDS register address list */
+const vdc5_regaddr_lvds_t vdc5_regaddr_lvds = {
+ &LVDS.LVDS_UPDATE,
+ &LVDS.LVDSFCL,
+ &LVDS.LCLKSELR,
+ &LVDS.LPLLSETR,
+ &LVDS.LPHYACC
+};
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/vdc5/src/r_vdc5_shared_param.c Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,1029 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file r_vdc5_shared_param.c
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief VDC5 driver shared parameter processing
+******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include <string.h>
+
+#include "r_vdc5.h"
+#include "r_vdc5_user.h"
+#include "r_vdc5_shared_param.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/*! Two to the power of eleven */
+#define TWO_POWER_ELEVEN (2048)
+
+#define VDC5_SPARA_DIV_2 (2)
+#define VDC5_SPARA_DIV_256 (256)
+
+/* Color Conversion Value */
+#define VDC5_SPARA_COLOR_CONV_RANGE (255)
+#define VDC5_SPARA_COLOR_CONV_OFFSET (128)
+
+/* Color mask data */
+#define VDC5_SPARA_COLOR_8BIT_MASK (0x000000FFu)
+
+/* shift value */
+#define VDC5_SPARA_SHIFT_16 (16u)
+#define VDC5_SPARA_SHIFT_8 (8u)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+typedef struct {
+ vdc5_panel_clksel_t panel_icksel; /*!< Panel clock select */
+ vdc5_onoff_t lvds_ref; /*!< Reference to the LVDS PLL clock */
+ vdc5_color_space_t color_sp_in; /*!< Color space of the input video image signal */
+ vdc5_input_sel_t inp_sel; /*!< Input select */
+ vdc5_res_vs_in_sel_t res_vs_in_sel; /*!< Horizontal/vertical sync signal output and
+ full-screen enable signal select */
+ vdc5_onoff_t cascade; /*!< Cascaded connection */
+ vdc5_onoff_t und_sel; /*!< Selection of lower-layer plane in scaler */
+ uint32_t bg_color_rgb; /*!< Background color in 24-bit RGB color format */
+ uint32_t bg_color_crycb; /*!< Background color in 24-bit CrYCb format */
+} vdc5_shared_param_common_t;
+
+typedef struct {
+ vdc5_wr_md_t res_ds_wr_md; /*!< Frame buffer writing mode for image processing */
+ vdc5_res_inter_t res_inter; /*!< Field operating mode select */
+ vdc5_color_space_t color_sp_fb_wr; /*!< Color space of the frame buffer writing format */
+ void * btm_base; /*!< Frame buffer base address for bottom */
+ vdc5_width_read_fb_t width_wr_fb; /*!< Size of the image output by scaling-down control block */
+} vdc5_shared_param_scaling_t;
+
+typedef struct {
+ vdc5_gr_ln_off_dir_t gr_ln_off_dir; /*!< Line offset address direction of the frame buffer */
+ vdc5_gr_flm_sel_t gr_flm_sel; /*!< Frame buffer address setting signal */
+ vdc5_gr_format_t gr_format; /*!< Format of the frame buffer read signal */
+ vdc5_color_space_t color_sp_fb_rd; /*!< Color space of the frame buffer reading format */
+ vdc5_onoff_t adj_sel; /*!< Folding handling (on/off) */
+ vdc5_period_rect_t gr_grc; /*!< Graphics display area */
+ vdc5_width_read_fb_t width_read_fb; /*!< Size of the frame buffer to be read */
+} vdc5_shared_param_graphics_t;
+
+typedef struct {
+ vdc5_resource_state_t rsrc_panel_clock;
+ vdc5_resource_state_t rsrc_video_input;
+ vdc5_resource_state_t rsrc_vsync_signal;
+ vdc5_resource_state_t rsrc_lcd_panel;
+} vdc5_shared_param_resource_t;
+
+/*! Read/write process state */
+typedef enum {
+ VDC5_RW_PROC_STATE_DISABLE = 0,
+ VDC5_RW_PROC_STATE_ENABLE = 1
+} vdc5_rw_proc_state_t;
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static vdc5_resource_state_t * GetResourceStatePointer(const vdc5_channel_t ch, const vdc5_resource_type_t rsrc_type);
+static uint32_t SumProduct(
+ const int32_t red,
+ const int32_t green,
+ const int32_t blue,
+ int32_t coeff_r,
+ int32_t coeff_g,
+ int32_t coeff_b,
+ const int32_t offset);
+
+static vdc5_shared_param_common_t param_common[VDC5_CHANNEL_NUM];
+static vdc5_shared_param_scaling_t param_scaling[VDC5_CHANNEL_NUM][VDC5_SC_TYPE_NUM];
+static vdc5_shared_param_graphics_t param_graphics[VDC5_CHANNEL_NUM][VDC5_GR_TYPE_NUM];
+/*! A channel in VDC5 whose data is to be output through the LVDS */
+static vdc5_channel_t lvds_vdc_sel_ch;
+
+static vdc5_resource_state_t layer_resource[VDC5_CHANNEL_NUM][VDC5_LAYER_ID_NUM];
+static vdc5_rw_proc_state_t rw_proc_state[VDC5_CHANNEL_NUM][VDC5_LAYER_ID_NUM];
+
+static vdc5_onoff_t video_input_flag[VDC5_CHANNEL_NUM] = {VDC5_OFF, VDC5_OFF};
+
+
+/**************************************************************************//**
+ * @brief Initializes variables of the VDC5 driver
+ * @param[in] ch : Channel
+ * @retval None
+ *****************************************************************************/
+void VDC5_ShrdPrmInit (const vdc5_channel_t ch)
+{
+ int32_t layer_id_num;
+ vdc5_shared_param_common_t * shared_param_common;
+ vdc5_shared_param_scaling_t * shared_param_scaling;
+ vdc5_scaling_type_t scaling_id;
+ vdc5_shared_param_graphics_t * shared_param_graphics;
+ vdc5_graphics_type_t graphics_id;
+
+ for (layer_id_num = 0; layer_id_num < VDC5_LAYER_ID_NUM; layer_id_num++) {
+ layer_resource[ch][layer_id_num] = VDC5_RESOURCE_ST_INVALID;
+ rw_proc_state[ch][layer_id_num] = VDC5_RW_PROC_STATE_DISABLE;
+ }
+
+ shared_param_common = ¶m_common[ch];
+
+ shared_param_common->panel_icksel = VDC5_PANEL_ICKSEL_PERI; /* Panel clock select */
+ shared_param_common->lvds_ref = VDC5_OFF; /* Reference to the LVDS PLL clock */
+ shared_param_common->res_vs_in_sel = VDC5_RES_VS_IN_SEL_SC0; /* Horizontal/vertical sync signal output and
+ full-screen enable signal select */
+ shared_param_common->cascade = VDC5_ON; /* Cascaded connection */
+ shared_param_common->und_sel = VDC5_OFF; /* Selection of lower-layer plane in scaler */
+ shared_param_common->bg_color_rgb = (uint32_t)0u; /* Background color in 24-bit RGB color format */
+ shared_param_common->bg_color_crycb = (uint32_t)0u; /* Background color in 24-bit CrYCb format */
+
+ if (video_input_flag[ch] == VDC5_OFF) {
+ shared_param_common->color_sp_in = VDC5_COLOR_SPACE_GBR; /* Color space of the input video image signal */
+ shared_param_common->inp_sel = VDC5_INPUT_SEL_VDEC; /* Input select */
+ }
+
+ for (scaling_id = VDC5_SC_TYPE_SC0; scaling_id < VDC5_SC_TYPE_NUM; scaling_id++) {
+ shared_param_scaling = ¶m_scaling[ch][scaling_id];
+
+ /* Frame buffer writing mode for image processing */
+ shared_param_scaling->res_ds_wr_md = VDC5_WR_MD_NORMAL;
+ shared_param_scaling->res_inter = VDC5_RES_INTER_PROGRESSIVE; /* Field operating mode select */
+ /* Color space of the frame buffer writing format */
+ shared_param_scaling->color_sp_fb_wr = VDC5_COLOR_SPACE_GBR;
+ /* Frame buffer base address for bottom */
+ shared_param_scaling->btm_base = NULL;
+ /* Size of the image output by scaling-down control block */
+ shared_param_scaling->width_wr_fb.in_vw = (uint16_t)0;
+ shared_param_scaling->width_wr_fb.in_hw = (uint16_t)0;
+ }
+
+ for (graphics_id = VDC5_GR_TYPE_GR0; graphics_id < VDC5_GR_TYPE_NUM; graphics_id++) {
+ shared_param_graphics = ¶m_graphics[ch][graphics_id];
+
+ /* Line offset address direction of the frame buffer */
+ shared_param_graphics->gr_ln_off_dir = VDC5_GR_LN_OFF_DIR_INC;
+ /* Frame buffer address setting signal */
+ shared_param_graphics->gr_flm_sel = VDC5_GR_FLM_SEL_FLM_NUM;
+ /* Format of the frame buffer read signal */
+ shared_param_graphics->gr_format = VDC5_GR_FORMAT_RGB565;
+ /* Color space of the frame buffer reading format */
+ shared_param_graphics->color_sp_fb_rd = VDC5_COLOR_SPACE_GBR;
+ /* Folding handling (on/off) */
+ shared_param_graphics->adj_sel = VDC5_OFF;
+ /* Graphics display area */
+ shared_param_graphics->gr_grc.vs = (uint16_t)0;
+ shared_param_graphics->gr_grc.vw = (uint16_t)0;
+ shared_param_graphics->gr_grc.hs = (uint16_t)0;
+ shared_param_graphics->gr_grc.hw = (uint16_t)0;
+ /* Size of the frame buffer to be read */
+ shared_param_graphics->width_read_fb.in_vw = (uint16_t)0;
+ shared_param_graphics->width_read_fb.in_hw = (uint16_t)0;
+ }
+ /* A channel in VDC5 whose data is to be output through the LVDS */
+ lvds_vdc_sel_ch = VDC5_CHANNEL_NUM; /* Initialized with invalid channel */
+} /* End of function VDC5_ShrdPrmInit() */
+
+/**************************************************************************//**
+ * @brief Sets the initialization parameter
+ * @param[in] ch : Channel
+ * @param[in] param : Initialization parameter
+ * @retval None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetInitParam (const vdc5_channel_t ch, const vdc5_init_t * const param)
+{
+ vdc5_shared_param_common_t * shared_param_common;
+
+ shared_param_common = ¶m_common[ch];
+
+ /* Panel clock select */
+ shared_param_common->panel_icksel = param->panel_icksel;
+ /* Reference to the LVDS PLL clock */
+ if ((param->panel_icksel == VDC5_PANEL_ICKSEL_LVDS) || (param->panel_icksel == VDC5_PANEL_ICKSEL_LVDS_DIV7)) {
+ shared_param_common->lvds_ref = VDC5_ON;
+ }
+ if (param->lvds != NULL) {
+ /* A channel in VDC5 whose data is to be output through the LVDS */
+ lvds_vdc_sel_ch = param->lvds->lvds_vdc_sel;
+ }
+} /* End of function VDC5_ShrdPrmSetInitParam() */
+
+/**************************************************************************//**
+ * @brief Sets the termination parameter
+ * @param[in] ch : Channel
+ * @retval None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetTerminate (const vdc5_channel_t ch)
+{
+ vdc5_shared_param_common_t * shared_param_common;
+
+ shared_param_common = ¶m_common[ch];
+
+ /* Reference to the LVDS PLL clock */
+ shared_param_common->lvds_ref = VDC5_OFF;
+} /* End of function VDC5_ShrdPrmSetTerminate() */
+
+/**************************************************************************//**
+ * @brief Sets the video input setup parameter
+ * @param[in] ch : Channel
+ * @param[in] param : Video input setup parameter
+ * @retval None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetInputParam (const vdc5_channel_t ch, const vdc5_input_t * const param)
+{
+ vdc5_shared_param_common_t * shared_param_common;
+
+ video_input_flag[ch] = VDC5_ON;
+
+ shared_param_common = ¶m_common[ch];
+
+ /* Color space */
+ if (param->inp_sel == VDC5_INPUT_SEL_VDEC) {
+ /* Video decoder output signals */
+ shared_param_common->color_sp_in = VDC5_COLOR_SPACE_YCBCR;
+ } else {
+ /* Signals supplied via the external input pins */
+ if ((param->ext_sig->inp_format == VDC5_EXTIN_FORMAT_RGB888) ||
+ (param->ext_sig->inp_format == VDC5_EXTIN_FORMAT_RGB666) ||
+ (param->ext_sig->inp_format == VDC5_EXTIN_FORMAT_RGB565)) {
+ shared_param_common->color_sp_in = VDC5_COLOR_SPACE_GBR;
+ } else {
+ shared_param_common->color_sp_in = VDC5_COLOR_SPACE_YCBCR;
+ }
+ }
+ /* Input select */
+ shared_param_common->inp_sel = param->inp_sel;
+} /* End of function VDC5_ShrdPrmSetInputParam() */
+
+/**************************************************************************//**
+ * @brief Sets the sync control parameter
+ * @param[in] ch : Channel
+ * @param[in] param : Sync control parameter
+ * @retval None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetSyncParam (const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param)
+{
+ vdc5_shared_param_common_t * shared_param_common;
+
+ shared_param_common = ¶m_common[ch];
+
+ shared_param_common->res_vs_in_sel = param->res_vs_in_sel;
+} /* End of function VDC5_ShrdPrmSetSyncParam() */
+
+/**************************************************************************//**
+ * @brief Sets the display output configuration parameter
+ * @param[in] ch : Channel
+ * @param[in] param : Display output configuration parameter
+ * @retval None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetOutputParam (const vdc5_channel_t ch, const vdc5_output_t * const param)
+{
+ vdc5_shared_param_common_t * shared_param_common;
+ int32_t red;
+ int32_t green;
+ int32_t blue;
+ uint32_t y_val;
+ uint32_t cb_val;
+ uint32_t cr_val;
+
+ shared_param_common = ¶m_common[ch];
+
+ /* Background color in 24-bit RGB color format */
+ shared_param_common->bg_color_rgb = param->bg_color;
+
+ red = (int32_t)((param->bg_color >> VDC5_SPARA_SHIFT_16) & (uint32_t)VDC5_SPARA_COLOR_8BIT_MASK);
+ green = (int32_t)((param->bg_color >> VDC5_SPARA_SHIFT_8) & (uint32_t)VDC5_SPARA_COLOR_8BIT_MASK);
+ blue = (int32_t)( param->bg_color & (uint32_t)VDC5_SPARA_COLOR_8BIT_MASK);
+ /* Y */
+ y_val = SumProduct(
+ red,
+ green,
+ blue,
+ (int32_t)VDC5_COLORCONV_Y_R,
+ (int32_t)VDC5_COLORCONV_Y_G,
+ (int32_t)VDC5_COLORCONV_Y_B,
+ 0);
+ /* Cb */
+ cb_val = SumProduct(
+ red,
+ green,
+ blue,
+ (int32_t)VDC5_COLORCONV_CB_R,
+ (int32_t)VDC5_COLORCONV_CB_G,
+ (int32_t)VDC5_COLORCONV_CB_B,
+ (int32_t)VDC5_SPARA_COLOR_CONV_OFFSET);
+ /* Cr */
+ cr_val = SumProduct(
+ red,
+ green,
+ blue,
+ (int32_t)VDC5_COLORCONV_CR_R,
+ (int32_t)VDC5_COLORCONV_CR_G,
+ (int32_t)VDC5_COLORCONV_CR_B,
+ (int32_t)VDC5_SPARA_COLOR_CONV_OFFSET);
+ /* Background color in 24-bit CrYCb format */
+ shared_param_common->bg_color_crycb = (uint32_t)((cr_val << VDC5_SPARA_SHIFT_16) | (y_val << VDC5_SPARA_SHIFT_8) | cb_val);
+} /* End of function VDC5_ShrdPrmSetOutputParam() */
+
+/**************************************************************************//**
+ * @brief Sets the data write control parameter
+ * @param[in] ch : Channel
+ * @param[in] scaling_id : Scaling type ID
+ * @param[in] param : Data write control parameter
+ * @retval None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetWriteParam (
+ const vdc5_channel_t ch,
+ const vdc5_scaling_type_t scaling_id,
+ const vdc5_write_t * const param)
+{
+ vdc5_shared_param_scaling_t * shared_param_scaling;
+
+ shared_param_scaling = ¶m_scaling[ch][scaling_id];
+
+ if (scaling_id == VDC5_SC_TYPE_OIR) {
+ /* Frame buffer writing mode for image processing */
+ shared_param_scaling->res_ds_wr_md = VDC5_WR_MD_NORMAL;
+ /* Field operating mode select */
+ shared_param_scaling->res_inter = VDC5_RES_INTER_PROGRESSIVE;
+ } else {
+ /* Frame buffer writing mode for image processing */
+ shared_param_scaling->res_ds_wr_md = param->scalingdown_rot.res_ds_wr_md;
+ /* Field operating mode select */
+ shared_param_scaling->res_inter = param->res_inter;
+ }
+
+ /* Color space of the frame buffer */
+ if ((param->res_md == VDC5_RES_MD_YCBCR422) || (param->res_md == VDC5_RES_MD_YCBCR444)) {
+ shared_param_scaling->color_sp_fb_wr = VDC5_COLOR_SPACE_YCBCR;
+ } else {
+ shared_param_scaling->color_sp_fb_wr = VDC5_COLOR_SPACE_GBR;
+ }
+
+ /* Frame buffer base address for bottom */
+ shared_param_scaling->btm_base = param->btm_base;
+ /* Size of the image output by scaling-down control block */
+ if (scaling_id == VDC5_SC_TYPE_OIR) {
+ /* OIR */
+ shared_param_scaling->width_wr_fb.in_vw = param->scalingdown_rot.res.vw;
+ shared_param_scaling->width_wr_fb.in_hw = param->scalingdown_rot.res.hw;
+ } else {
+ shared_param_scaling->width_wr_fb.in_vw = param->scalingdown_rot.res_out_vw;
+ shared_param_scaling->width_wr_fb.in_hw = param->scalingdown_rot.res_out_hw;
+ }
+} /* End of function VDC5_ShrdPrmSetWriteParam() */
+
+/**************************************************************************//**
+ * @brief Sets the data write change parameter
+ * @param[in] ch : Channel
+ * @param[in] scaling_id : Scaling type ID
+ * @param[in] param : Data write change parameter
+ * @retval None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetChgWriteParam (
+ const vdc5_channel_t ch,
+ const vdc5_scaling_type_t scaling_id,
+ const vdc5_write_chg_t * const param)
+{
+ vdc5_shared_param_scaling_t * shared_param_scaling;
+
+ shared_param_scaling = ¶m_scaling[ch][scaling_id];
+
+ if (scaling_id != VDC5_SC_TYPE_OIR) {
+ /* Frame buffer writing mode for image processing */
+ shared_param_scaling->res_ds_wr_md = param->scalingdown_rot.res_ds_wr_md;
+ }
+
+ /* Size of the image output by scaling-down control block */
+ if (scaling_id == VDC5_SC_TYPE_OIR) {
+ /* OIR */
+ shared_param_scaling->width_wr_fb.in_vw = param->scalingdown_rot.res.vw;
+ shared_param_scaling->width_wr_fb.in_hw = param->scalingdown_rot.res.hw;
+ } else {
+ shared_param_scaling->width_wr_fb.in_vw = param->scalingdown_rot.res_out_vw;
+ shared_param_scaling->width_wr_fb.in_hw = param->scalingdown_rot.res_out_hw;
+ }
+} /* End of function VDC5_ShrdPrmSetChgWriteParam() */
+
+/**************************************************************************//**
+ * @brief Sets the data read control parameter
+ * @param[in] ch : Channel
+ * @param[in] graphics_id : Graphics type ID
+ * @param[in] param : Data read control parameter
+ * @retval None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetReadParam (
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_read_t * const param)
+{
+ vdc5_shared_param_graphics_t * shared_param_graphics;
+
+ shared_param_graphics = ¶m_graphics[ch][graphics_id];
+
+ /* Line offset address direction of the frame buffer */
+ shared_param_graphics->gr_ln_off_dir = param->gr_ln_off_dir;
+
+ /* Frame buffer address setting signal */
+ shared_param_graphics->gr_flm_sel = param->gr_flm_sel;
+
+ /* Format of the frame buffer read signal */
+ shared_param_graphics->gr_format = param->gr_format;
+
+ /* Color space of the frame buffer */
+ if ((param->gr_format == VDC5_GR_FORMAT_YCBCR422) || (param->gr_format == VDC5_GR_FORMAT_YCBCR444)) {
+ shared_param_graphics->color_sp_fb_rd = VDC5_COLOR_SPACE_YCBCR;
+ } else {
+ shared_param_graphics->color_sp_fb_rd = VDC5_COLOR_SPACE_GBR;
+ }
+
+ /* Folding handling (on/off) */
+ shared_param_graphics->adj_sel = param->adj_sel;
+
+ /* Graphics display area */
+ shared_param_graphics->gr_grc = param->gr_grc;
+ /* Size of the frame buffer to be read */
+ if (param->width_read_fb != NULL) {
+ shared_param_graphics->width_read_fb.in_vw = param->width_read_fb->in_vw;
+ shared_param_graphics->width_read_fb.in_hw = param->width_read_fb->in_hw;
+ } else {
+ /* If not specified, ... */
+ if ((param->gr_flm_sel == VDC5_GR_FLM_SEL_FLM_NUM) || (graphics_id == VDC5_GR_TYPE_OIR)) {
+ /* The size of the frame buffer to be read is assumed that it is the same as
+ the width of the graphics display area. */
+ shared_param_graphics->width_read_fb.in_vw = param->gr_grc.vw;
+ shared_param_graphics->width_read_fb.in_hw = param->gr_grc.hw;
+ } else {
+ /* The size of the image output by scaling-down control block is used for the size of the frame buffer
+ to be read when a frame buffer address setting signal links to the video image signals. */
+ if (graphics_id == VDC5_GR_TYPE_GR0) {
+ /* Scaler 0 */
+ shared_param_graphics->width_read_fb = param_scaling[ch][VDC5_SC_TYPE_SC0].width_wr_fb;
+ } else { /* Scaler 1 */
+ shared_param_graphics->width_read_fb = param_scaling[ch][VDC5_SC_TYPE_SC1].width_wr_fb;
+ }
+ }
+ }
+} /* End of function VDC5_ShrdPrmSetReadParam() */
+
+/**************************************************************************//**
+ * @brief Sets the data read change parameter
+ * @param[in] ch : Channel
+ * @param[in] graphics_id : Graphics type ID
+ * @param[in] param : Data read change parameter
+ * @retval None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetChgReadParam (
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_read_chg_t * const param)
+{
+ vdc5_shared_param_graphics_t * shared_param_graphics;
+
+ shared_param_graphics = ¶m_graphics[ch][graphics_id];
+
+ /* Graphics display area */
+ if (param->gr_grc != NULL) {
+ shared_param_graphics->gr_grc = *(param->gr_grc);
+ }
+
+ /* Size of the frame buffer to be read */
+ if (param->width_read_fb != NULL) {
+ shared_param_graphics->width_read_fb.in_vw = param->width_read_fb->in_vw;
+ shared_param_graphics->width_read_fb.in_hw = param->width_read_fb->in_hw;
+ }
+} /* End of function VDC5_ShrdPrmSetChgReadParam() */
+
+/**************************************************************************//**
+ * @brief Sets the cascaded connection
+ * @param[in] ch : Channel
+ * @param[in] cascade : Cascaded connection
+ * @retval None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetCascade (const vdc5_channel_t ch, const vdc5_onoff_t cascade)
+{
+ param_common[ch].cascade = cascade;
+} /* End of function VDC5_ShrdPrmSetCascade() */
+
+/**************************************************************************//**
+ * @brief Sets the selection of lower-layer plane in scaler
+ * @param[in] ch : Channel
+ * @param[in] und_sel : Selection of lower-layer plane in scaler
+ * @retval None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetUndSel (const vdc5_channel_t ch, const vdc5_onoff_t und_sel)
+{
+ param_common[ch].und_sel = und_sel;
+} /* End of function VDC5_ShrdPrmSetUndSel() */
+
+/**************************************************************************//**
+ * @brief Gets the panel clock select
+ * @param[in] ch : Channel
+ * @retval Panel clock select
+ *****************************************************************************/
+vdc5_panel_clksel_t VDC5_ShrdPrmGetPanelClkSel (const vdc5_channel_t ch)
+{
+ return param_common[ch].panel_icksel;
+} /* End of function VDC5_ShrdPrmGetPanelClkSel() */
+
+/**************************************************************************//**
+ * @brief Gets the reference to the LVDS PLL clock
+ * @param[in] void
+ * @retval Reference to the LVDS PLL clock
+ *****************************************************************************/
+vdc5_onoff_t VDC5_ShrdPrmGetLvdsClkRef (void)
+{
+ vdc5_onoff_t onoff;
+
+ if ((param_common[VDC5_CHANNEL_0].lvds_ref == VDC5_OFF) && (param_common[VDC5_CHANNEL_1].lvds_ref == VDC5_OFF)) {
+ onoff = VDC5_OFF;
+ } else {
+ onoff = VDC5_ON;
+ }
+ return onoff;
+} /* End of function VDC5_ShrdPrmGetLvdsClkRef() */
+
+/**************************************************************************//**
+ * @brief Gets the color space of the input video image signal
+ * @param[in] ch : Channel
+ * @retval Color space of the input video image signal
+ *****************************************************************************/
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpace (const vdc5_channel_t ch)
+{
+ return param_common[ch].color_sp_in;
+} /* End of function VDC5_ShrdPrmGetColorSpace() */
+
+/**************************************************************************//**
+ * @brief Gets the input select
+ * @param[in] ch : Channel
+ * @retval Input select
+ *****************************************************************************/
+vdc5_input_sel_t VDC5_ShrdPrmGetInputSelect (const vdc5_channel_t ch)
+{
+ return param_common[ch].inp_sel;
+} /* End of function VDC5_ShrdPrmGetInputSelect() */
+
+/**************************************************************************//**
+ * @brief Gets the sync signal output and full-screen enable signal select
+ * @param[in] ch : Channel
+ * @retval Horizontal/vertical sync signal output and full-screen enable signal select
+ * - VDC5_RES_VS_IN_SEL_SC0: Sync signal output and full-screen enable signal from scaler 0
+ * - VDC5_RES_VS_IN_SEL_SC1: Sync signal output and full-screen enable signal from scaler 1
+ *****************************************************************************/
+vdc5_res_vs_in_sel_t VDC5_ShrdPrmGetVsInSel (const vdc5_channel_t ch)
+{
+ return param_common[ch].res_vs_in_sel;
+} /* End of function VDC5_ShrdPrmGetVsInSel() */
+
+/**************************************************************************//**
+ * @brief Gets the cascaded connection
+ * @param[in] ch : Channel
+ * @retval Cascaded connection (on/off)
+ *****************************************************************************/
+vdc5_onoff_t VDC5_ShrdPrmGetCascade (const vdc5_channel_t ch)
+{
+ return param_common[ch].cascade;
+} /* End of function VDC5_ShrdPrmGetCascade() */
+
+/**************************************************************************//**
+ * @brief Gets the selection of lower-layer plane in scaler
+ * @param[in] ch : Channel
+ * @retval Selection of lower-layer plane in scaler
+ * - VDC5_OFF: Selects graphics 0 as lower-layer graphics and graphics 1 as current graphics
+ * - VDC5_ON: Selects graphics 1 as lower-layer graphics and graphics 0 as current graphics
+ *****************************************************************************/
+vdc5_onoff_t VDC5_ShrdPrmGetUndSel (const vdc5_channel_t ch)
+{
+ return param_common[ch].und_sel;
+} /* End of function VDC5_ShrdPrmGetUndSel() */
+
+/**************************************************************************//**
+ * @brief Get the background color
+ * @param[in] ch : Channel
+ * @param[in] color_space : Color space
+ * @retval Background color in 24-bit RGB color format or CrYCb format
+ *****************************************************************************/
+uint32_t VDC5_ShrdPrmGetBgColor (const vdc5_channel_t ch, const vdc5_color_space_t color_space)
+{
+ return (color_space == VDC5_COLOR_SPACE_GBR) ? param_common[ch].bg_color_rgb : param_common[ch].bg_color_crycb;
+} /* End of function VDC5_ShrdPrmGetBgColor() */
+
+/**************************************************************************//**
+ * @brief Get the frame buffer writing mode for image processing
+ * @param[in] ch : Channel
+ * @param[in] scaling_id : Scaling type ID
+ * @retval Frame buffer writing mode for image processing
+ *****************************************************************************/
+vdc5_wr_md_t VDC5_ShrdPrmGetWritingMode (const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id)
+{
+ return param_scaling[ch][scaling_id].res_ds_wr_md;
+} /* End of function VDC5_ShrdPrmGetWritingMode() */
+
+/**************************************************************************//**
+ * @brief Gets the field operating mode select
+ * @param[in] ch : Channel
+ * @param[in] scaling_id : Scaling type ID
+ * @retval Field operating mode select
+ *****************************************************************************/
+vdc5_res_inter_t VDC5_ShrdPrmGetInterlace (const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id)
+{
+ return param_scaling[ch][scaling_id].res_inter;
+} /* End of function VDC5_ShrdPrmGetInterlace() */
+
+/**************************************************************************//**
+ * @brief Gets the color space of the frame buffer writing format
+ * @param[in] ch : Channel
+ * @param[in] scaling_id : Scaling type ID
+ * @retval Color space of the frame buffer writing format
+ *****************************************************************************/
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpaceFbWr (const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id)
+{
+ return param_scaling[ch][scaling_id].color_sp_fb_wr;
+} /* End of function VDC5_ShrdPrmGetColorSpaceFbWr() */
+
+/**************************************************************************//**
+ * @brief Gets the frame buffer base address for bottom
+ * @param[in] ch : Channel
+ * @param[in] scaling_id : Scaling type ID
+ * @retval Frame buffer base address for bottom
+ *****************************************************************************/
+void * VDC5_ShrdPrmGetFrBuffBtm (const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id)
+{
+ return param_scaling[ch][scaling_id].btm_base;
+} /* End of function VDC5_ShrdPrmGetFrBuffBtm() */
+
+/**************************************************************************//**
+ * @brief Gets the line offset address direction of the frame buffer
+ * @param[in] ch : Channel
+ * @param[in] graphics_id : Graphics type ID
+ * @retval Line offset address direction of the frame buffer
+ *****************************************************************************/
+vdc5_gr_ln_off_dir_t VDC5_ShrdPrmGetLineOfsAddrDir (const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id)
+{
+ return param_graphics[ch][graphics_id].gr_ln_off_dir;
+} /* End of function VDC5_ShrdPrmGetLineOfsAddrDir() */
+
+/**************************************************************************//**
+ * @brief Gets the frame buffer address setting signal
+ * @param[in] ch : Channel
+ * @param[in] graphics_id : Graphics type ID
+ * @retval Frame buffer address setting signal
+ *****************************************************************************/
+vdc5_gr_flm_sel_t VDC5_ShrdPrmGetSelFbAddrSig (const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id)
+{
+ return param_graphics[ch][graphics_id].gr_flm_sel;
+} /* End of function VDC5_ShrdPrmGetSelFbAddrSig() */
+
+/**************************************************************************//**
+ * @brief Gets the format of the frame buffer read signal
+ * @param[in] ch : Channel
+ * @param[in] graphics_id : Graphics type ID
+ * @retval Format of the frame buffer read signal
+ *****************************************************************************/
+vdc5_gr_format_t VDC5_ShrdPrmGetGraphicsFormat (const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id)
+{
+ return param_graphics[ch][graphics_id].gr_format;
+} /* End of function VDC5_ShrdPrmGetGraphicsFormat() */
+
+/**************************************************************************//**
+ * @brief Gets the color space of the frame buffer reading format
+ * @param[in] ch : Channel
+ * @param[in] graphics_id : Graphics type ID
+ * @retval Color space of the frame buffer reading format
+ *****************************************************************************/
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpaceFbRd (const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id)
+{
+ return param_graphics[ch][graphics_id].color_sp_fb_rd;
+} /* End of function VDC5_ShrdPrmGetColorSpaceFbRd() */
+
+/**************************************************************************//**
+ * @brief Gets the folding handling
+ * @param[in] ch : Channel
+ * @param[in] graphics_id : Graphics type ID
+ * @retval Folding handling (on/off)
+ *****************************************************************************/
+vdc5_onoff_t VDC5_ShrdPrmGetMeasureFolding (const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id)
+{
+ return param_graphics[ch][graphics_id].adj_sel;
+} /* End of function VDC5_ShrdPrmGetMeasureFolding() */
+
+/**************************************************************************//**
+ * @brief Gets the graphics display area
+ * @param[in] ch : Channel
+ * @param[in] graphics_id : Graphics type ID
+ * @retval Graphics display area
+ *****************************************************************************/
+vdc5_period_rect_t * VDC5_ShrdPrmGetDisplayArea (const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id)
+{
+ return ¶m_graphics[ch][graphics_id].gr_grc;
+} /* End of function VDC5_ShrdPrmGetDisplayArea() */
+
+/**************************************************************************//**
+ * @brief Gets the size of the frame buffer to be read
+ * @param[in] ch : Channel
+ * @param[in] graphics_id : Graphics type ID
+ * @retval Size of the frame buffer to be read
+ *****************************************************************************/
+vdc5_width_read_fb_t * VDC5_ShrdPrmGetFrBuffWidth_Rd (
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id)
+{
+ return ¶m_graphics[ch][graphics_id].width_read_fb;
+} /* End of function VDC5_ShrdPrmGetFrBuffWidth_Rd() */
+
+/**************************************************************************//**
+ * @brief Gets the VDC5 channel whose data is to be output through the LVDS
+ * @param[in] void
+ * @retval A channel in VDC5 whose data is to be output through the LVDS
+ *****************************************************************************/
+vdc5_channel_t VDC5_ShrdPrmGetLvdsCh (void)
+{
+ /* This value is valid only when LVDS PLL clock resource (VDC5_RESOURCE_LVDS_CLK) is valid. */
+ return lvds_vdc_sel_ch;
+} /* End of function VDC5_ShrdPrmGetLvdsCh() */
+
+/**************************************************************************//**
+ * @brief Updates the resource state
+ * @param[in] ch : Channel
+ * @param[in] rsrc_type : Resource type
+ * @param[in] rsrc_state : Resource state
+ * @retval None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetResource (
+ const vdc5_channel_t ch,
+ const vdc5_resource_type_t rsrc_type,
+ const vdc5_resource_state_t rsrc_state)
+{
+ vdc5_resource_state_t * resource_state;
+
+ resource_state = GetResourceStatePointer(ch, rsrc_type);
+ if (resource_state != NULL) {
+ *resource_state = rsrc_state;
+ }
+} /* End of function VDC5_ShrdPrmSetResource() */
+
+/**************************************************************************//**
+ * @brief Updates the layer resource state
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @param[in] rsrc_state : Resource state
+ * @retval None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetLayerResource (
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_resource_state_t rsrc_state)
+{
+ uint32_t layer_id_num;
+
+ if (layer_id != VDC5_LAYER_ID_ALL) {
+ layer_resource[ch][layer_id] = rsrc_state;
+ } else {
+ for (layer_id_num = 0; layer_id_num < (uint32_t)VDC5_LAYER_ID_NUM; layer_id_num++) {
+ if (rw_proc_state[ch][layer_id_num] == VDC5_RW_PROC_STATE_DISABLE) {
+ layer_resource[ch][layer_id_num] = rsrc_state;
+ }
+ }
+ }
+} /* End of function VDC5_ShrdPrmSetLayerResource() */
+
+/**************************************************************************//**
+ * @brief Gets the resource state
+ * @param[in] ch : Channel
+ * @param[in] rsrc_type : Resource type
+ * @retval Resource state
+ *****************************************************************************/
+vdc5_resource_state_t VDC5_ShrdPrmGetResource (const vdc5_channel_t ch, const vdc5_resource_type_t rsrc_type)
+{
+ vdc5_resource_state_t * resource_state;
+ vdc5_resource_state_t rsrc_state;
+
+ rsrc_state = VDC5_RESOURCE_ST_INVALID;
+
+ resource_state = GetResourceStatePointer(ch, rsrc_type);
+ if (resource_state != NULL) {
+ rsrc_state = *resource_state;
+ }
+ return rsrc_state;
+} /* End of function VDC5_ShrdPrmGetResource() */
+
+/**************************************************************************//**
+ * @brief Gets the layer resource state
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @retval Layer resource state
+ *****************************************************************************/
+vdc5_resource_state_t VDC5_ShrdPrmGetLayerResource (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+ return layer_resource[ch][layer_id];
+} /* End of function VDC5_ShrdPrmGetLayerResource() */
+
+/**************************************************************************//**
+ * @brief Makes the data write/read processing enabled
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @retval None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetRwProcEnable (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+ if (layer_id != VDC5_LAYER_ID_ALL) {
+ if (layer_resource[ch][layer_id] != VDC5_RESOURCE_ST_INVALID) {
+ rw_proc_state[ch][layer_id] = VDC5_RW_PROC_STATE_ENABLE;
+ }
+ }
+} /* End of function VDC5_ShrdPrmSetRwProcEnable() */
+
+/**************************************************************************//**
+ * @brief Makes the data write/read processing disabled
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @retval None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetRwProcDisable (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+ if (layer_id != VDC5_LAYER_ID_ALL) {
+ if (layer_resource[ch][layer_id] != VDC5_RESOURCE_ST_INVALID) {
+ rw_proc_state[ch][layer_id] = VDC5_RW_PROC_STATE_DISABLE;
+ }
+ }
+} /* End of function VDC5_ShrdPrmSetRwProcDisable() */
+
+/**************************************************************************//**
+ * @brief Gets the state whether the specified layer is ready or not
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @retval Resource state
+ * - VDC5_RESOURCE_ST_VALID: The layer resource state of the specified layer is valid and
+ * the data write/read processing in the layer is disabled.
+ * - VDC5_RESOURCE_ST_INVALID: The specified layer is not ready.
+ *****************************************************************************/
+vdc5_resource_state_t VDC5_ShrdPrmGetRwProcReady (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+ vdc5_resource_state_t state;
+
+ if ((layer_resource[ch][layer_id] != VDC5_RESOURCE_ST_INVALID) &&
+ (rw_proc_state[ch][layer_id] == VDC5_RW_PROC_STATE_DISABLE)) {
+ state = VDC5_RESOURCE_ST_VALID;
+ } else {
+ state = VDC5_RESOURCE_ST_INVALID;
+ }
+ return state;
+} /* End of function VDC5_ShrdPrmGetRwProcReady() */
+
+/**************************************************************************//**
+ * @brief Gets the state whether the specified layer is already run or not
+ * @param[in] ch : Channel
+ * @param[in] layer_id : Layer ID
+ * @retval Resource state
+ * - VDC5_RESOURCE_ST_VALID: The layer resource state of the specified layer is valid and
+ * the data write/read processing in the layer is enabled.
+ * - VDC5_RESOURCE_ST_INVALID: The specified layer is not enabled.
+ *****************************************************************************/
+vdc5_resource_state_t VDC5_ShrdPrmGetRwProcEnabled (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+ vdc5_resource_state_t state;
+
+ if ((layer_resource[ch][layer_id] != VDC5_RESOURCE_ST_INVALID) &&
+ (rw_proc_state[ch][layer_id] != VDC5_RW_PROC_STATE_DISABLE)) {
+ state = VDC5_RESOURCE_ST_VALID;
+ } else {
+ state = VDC5_RESOURCE_ST_INVALID;
+ }
+ return state;
+} /* End of function VDC5_ShrdPrmGetRwProcEnabled() */
+
+/**************************************************************************//**
+ * @brief Gets the state whether the OIR is already run or not
+ * @param[in] ch : Channel
+ * @retval Resource state
+ * - VDC5_RESOURCE_ST_VALID: The layer resource state of the OIR is valid and
+ * the data write/read processing in the OIR is enabled.
+ * - VDC5_RESOURCE_ST_INVALID: The OIR is not enabled.
+ *****************************************************************************/
+vdc5_resource_state_t VDC5_ShrdPrmGetOirRwProcEnabled (const vdc5_channel_t ch)
+{
+ vdc5_resource_state_t state;
+
+ state = VDC5_RESOURCE_ST_INVALID;
+
+ if ((layer_resource[ch][VDC5_LAYER_ID_OIR_WR] != VDC5_RESOURCE_ST_INVALID) &&
+ (rw_proc_state[ch][VDC5_LAYER_ID_OIR_WR] != VDC5_RW_PROC_STATE_DISABLE)) {
+ state = VDC5_RESOURCE_ST_VALID;
+ }
+ if ((layer_resource[ch][VDC5_LAYER_ID_OIR_RD] != VDC5_RESOURCE_ST_INVALID) &&
+ (rw_proc_state[ch][VDC5_LAYER_ID_OIR_RD] != VDC5_RW_PROC_STATE_DISABLE)) {
+ state = VDC5_RESOURCE_ST_VALID;
+ }
+ return state;
+} /* End of function VDC5_ShrdPrmGetOirRwProcEnabled() */
+
+/******************************************************************************
+Local Functions
+******************************************************************************/
+/**************************************************************************//**
+ * @brief Gets the pointer to the resource state
+ * @param[in] ch : Channel
+ * @param[in] rsrc_type : Resource type
+ * @retval Pointer to the resource state
+ *****************************************************************************/
+static vdc5_resource_state_t * GetResourceStatePointer (const vdc5_channel_t ch, const vdc5_resource_type_t rsrc_type)
+{
+ vdc5_resource_state_t * resource_state;
+ static vdc5_shared_param_resource_t param_resource[VDC5_CHANNEL_NUM] = {
+ {VDC5_RESOURCE_ST_INVALID, VDC5_RESOURCE_ST_INVALID, VDC5_RESOURCE_ST_INVALID, VDC5_RESOURCE_ST_INVALID},
+ {VDC5_RESOURCE_ST_INVALID, VDC5_RESOURCE_ST_INVALID, VDC5_RESOURCE_ST_INVALID, VDC5_RESOURCE_ST_INVALID}
+ };
+ static vdc5_resource_state_t lvds_resource = VDC5_RESOURCE_ST_INVALID;
+
+ switch (rsrc_type) {
+ case VDC5_RESOURCE_PANEL_CLK:
+ resource_state = ¶m_resource[ch].rsrc_panel_clock;
+ break;
+ case VDC5_RESOURCE_VIDEO_IN:
+ resource_state = ¶m_resource[ch].rsrc_video_input;
+ break;
+ case VDC5_RESOURCE_VSYNC:
+ resource_state = ¶m_resource[ch].rsrc_vsync_signal;
+ break;
+ case VDC5_RESOURCE_LCD_PANEL:
+ resource_state = ¶m_resource[ch].rsrc_lcd_panel;
+ break;
+ case VDC5_RESOURCE_LVDS_CLK:
+ resource_state = &lvds_resource;
+ break;
+
+ default:
+ resource_state = NULL;
+ break;
+ }
+ return resource_state;
+} /* End of function GetResourceStatePointer() */
+
+/**************************************************************************//**
+ * @brief Product-sum operation
+ * @param[in] red : 8 bits for red
+ * @param[in] green : 8 bits for green
+ * @param[in] blue : 8 bits for blue
+ * @param[in] coeff_r : Coefficient value for Cr/R signal gain adjustment
+ * @param[in] coeff_g : Coefficient value for Y/G signal gain adjustment
+ * @param[in] coeff_b : Coefficient value for Cb/B signal gain adjustment
+ * @param[in] offset : Coefficient value for offset adjustment
+ * @retval Answer
+ *****************************************************************************/
+static uint32_t SumProduct (
+ const int32_t red,
+ const int32_t green,
+ const int32_t blue,
+ int32_t coeff_r,
+ int32_t coeff_g,
+ int32_t coeff_b,
+ const int32_t offset)
+{
+ int32_t color_val;
+
+ /* Coefficient values are represented in 11-bit two's complement integer. */
+ if (coeff_r >= (TWO_POWER_ELEVEN / VDC5_SPARA_DIV_2)) {
+ coeff_r -= (int32_t)TWO_POWER_ELEVEN;
+ }
+ if (coeff_g >= (TWO_POWER_ELEVEN / VDC5_SPARA_DIV_2)) {
+ coeff_g -= (int32_t)TWO_POWER_ELEVEN;
+ }
+ if (coeff_b >= (TWO_POWER_ELEVEN / VDC5_SPARA_DIV_2)) {
+ coeff_b -= (int32_t)TWO_POWER_ELEVEN;
+ }
+
+ color_val = (red * coeff_r) + (green * coeff_g) + (blue * coeff_b);
+ color_val /= (int32_t)VDC5_SPARA_DIV_256;
+ color_val += offset;
+ if (color_val < 0) {
+ color_val = 0;
+ } else if (color_val > (int32_t)VDC5_SPARA_COLOR_CONV_RANGE) {
+ color_val = (int32_t)VDC5_SPARA_COLOR_CONV_RANGE;
+ } else {
+ }
+ return (uint32_t)color_val;
+} /* End of function SumProduct() */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/vdc5/src/r_vdc5_shared_param.h Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,143 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file r_vdc5_shared_param.h
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief VDC5 driver shared parameter definitions
+******************************************************************************/
+
+#ifndef R_VDC5_SHARED_PARAM_H
+#define R_VDC5_SHARED_PARAM_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_vdc5.h"
+#include "r_vdc5_user.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! Color space */
+typedef enum {
+ VDC5_COLOR_SPACE_GBR = 0, /*!< GBR */
+ VDC5_COLOR_SPACE_YCBCR = 1 /*!< YCbCr */
+} vdc5_color_space_t;
+
+/*! Resource state */
+typedef enum {
+ VDC5_RESOURCE_ST_INVALID = 0, /*!< Invalid */
+ VDC5_RESOURCE_ST_VALID = 1 /*!< Valid */
+} vdc5_resource_state_t;
+
+/*! Resource type */
+typedef enum {
+ VDC5_RESOURCE_PANEL_CLK = 0, /*!< Panel clock */
+ VDC5_RESOURCE_VIDEO_IN, /*!< Input video */
+ VDC5_RESOURCE_VSYNC, /*!< Vsync signal */
+ VDC5_RESOURCE_LCD_PANEL, /*!< LCD panel (output video) */
+ VDC5_RESOURCE_LVDS_CLK, /*!< LVDS PLL clock */
+ VDC5_RESOURCE_NUM
+} vdc5_resource_type_t;
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void VDC5_ShrdPrmInit(const vdc5_channel_t ch);
+
+void VDC5_ShrdPrmSetInitParam(const vdc5_channel_t ch, const vdc5_init_t * const param);
+void VDC5_ShrdPrmSetTerminate(const vdc5_channel_t ch);
+void VDC5_ShrdPrmSetInputParam(const vdc5_channel_t ch, const vdc5_input_t * const param);
+void VDC5_ShrdPrmSetSyncParam(const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param);
+void VDC5_ShrdPrmSetOutputParam(const vdc5_channel_t ch, const vdc5_output_t * const param);
+void VDC5_ShrdPrmSetWriteParam(
+ const vdc5_channel_t ch,
+ const vdc5_scaling_type_t scaling_id,
+ const vdc5_write_t * const param);
+void VDC5_ShrdPrmSetChgWriteParam(
+ const vdc5_channel_t ch,
+ const vdc5_scaling_type_t scaling_id,
+ const vdc5_write_chg_t * const param);
+void VDC5_ShrdPrmSetReadParam(
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_read_t * const param);
+void VDC5_ShrdPrmSetChgReadParam(
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id,
+ const vdc5_read_chg_t * const param);
+void VDC5_ShrdPrmSetCascade(const vdc5_channel_t ch, const vdc5_onoff_t cascade);
+void VDC5_ShrdPrmSetUndSel(const vdc5_channel_t ch, const vdc5_onoff_t und_sel);
+
+vdc5_panel_clksel_t VDC5_ShrdPrmGetPanelClkSel(const vdc5_channel_t ch);
+vdc5_onoff_t VDC5_ShrdPrmGetLvdsClkRef(void);
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpace(const vdc5_channel_t ch);
+vdc5_input_sel_t VDC5_ShrdPrmGetInputSelect(const vdc5_channel_t ch);
+vdc5_res_vs_in_sel_t VDC5_ShrdPrmGetVsInSel(const vdc5_channel_t ch);
+vdc5_onoff_t VDC5_ShrdPrmGetCascade(const vdc5_channel_t ch);
+vdc5_onoff_t VDC5_ShrdPrmGetUndSel(const vdc5_channel_t ch);
+uint32_t VDC5_ShrdPrmGetBgColor(const vdc5_channel_t ch, const vdc5_color_space_t color_space);
+vdc5_wr_md_t VDC5_ShrdPrmGetWritingMode(const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id);
+vdc5_res_inter_t VDC5_ShrdPrmGetInterlace(const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id);
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpaceFbWr(const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id);
+void * VDC5_ShrdPrmGetFrBuffBtm(const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id);
+
+vdc5_gr_ln_off_dir_t VDC5_ShrdPrmGetLineOfsAddrDir(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
+vdc5_gr_flm_sel_t VDC5_ShrdPrmGetSelFbAddrSig(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
+vdc5_gr_format_t VDC5_ShrdPrmGetGraphicsFormat(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpaceFbRd(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
+vdc5_onoff_t VDC5_ShrdPrmGetMeasureFolding(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
+vdc5_period_rect_t * VDC5_ShrdPrmGetDisplayArea(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
+vdc5_width_read_fb_t * VDC5_ShrdPrmGetFrBuffWidth_Rd(
+ const vdc5_channel_t ch,
+ const vdc5_graphics_type_t graphics_id);
+vdc5_channel_t VDC5_ShrdPrmGetLvdsCh(void);
+
+void VDC5_ShrdPrmSetResource(
+ const vdc5_channel_t ch,
+ const vdc5_resource_type_t rsrc_type,
+ const vdc5_resource_state_t rsrc_state);
+void VDC5_ShrdPrmSetLayerResource(
+ const vdc5_channel_t ch,
+ const vdc5_layer_id_t layer_id,
+ const vdc5_resource_state_t rsrc_state);
+vdc5_resource_state_t VDC5_ShrdPrmGetResource(const vdc5_channel_t ch, const vdc5_resource_type_t rsrc_type);
+vdc5_resource_state_t VDC5_ShrdPrmGetLayerResource(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+
+void VDC5_ShrdPrmSetRwProcEnable(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+void VDC5_ShrdPrmSetRwProcDisable(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+vdc5_resource_state_t VDC5_ShrdPrmGetRwProcReady(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+vdc5_resource_state_t VDC5_ShrdPrmGetRwProcEnabled(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+vdc5_resource_state_t VDC5_ShrdPrmGetOirRwProcEnabled(const vdc5_channel_t ch);
+
+
+#endif /* R_VDC5_SHARED_PARAM_H */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/vdec/include/r_vdec.h Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,636 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file r_vdec.h
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief VDEC driver API definitions
+******************************************************************************/
+
+#ifndef R_VDEC_H
+#define R_VDEC_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_vdec_user.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/*! The number of chroma filter TAP coefficient values for Y/C separation */
+#define VDEC_CHRFIL_TAPCOEF_NUM (9)
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! Error codes of the VDEC driver */
+typedef enum {
+ VDEC_OK = 0, /*!< Normal termination */
+ VDEC_ERR_CHANNEL, /*!< Invalid channel error */
+ VDEC_ERR_PARAM, /*!< Parameter error */
+ VDEC_ERR_NUM /*!< The number of the error codes */
+} vdec_error_t;
+
+/*! VDEC channel */
+typedef enum {
+ VDEC_CHANNEL_0 = 0, /*!< Channel 0 */
+ VDEC_CHANNEL_1, /*!< Channel 1 */
+ VDEC_CHANNEL_NUM /*!< The number of channels */
+} vdec_channel_t;
+
+/*! On/Off */
+typedef enum {
+ VDEC_OFF = 0, /*!< Off */
+ VDEC_ON = 1 /*!< On */
+} vdec_onoff_t;
+
+/*********************** For R_VDEC_Initialize ***********************/
+/*! Input pin control */
+typedef enum {
+ VDEC_ADC_VINSEL_VIN1 = 0, /*!< VIN1 input */
+ VDEC_ADC_VINSEL_VIN2, /*!< VIN2 input */
+ VDEC_ADC_VINSEL_NUM /*!< The number of input pins */
+} vdec_adc_vinsel_t;
+
+/*********************** For R_VDEC_ActivePeriod ***********************/
+/*! Active image period parameter */
+typedef struct {
+ uint16_t srcleft; /*!< Left end of input video signal capturing area */
+ uint16_t srctop; /*!< Top end of input video signal capturing area */
+ uint16_t srcheight; /*!< Height of input video signal capturing area */
+ uint16_t srcwidth; /*!< Width of input video signal capturing area */
+} vdec_active_period_t;
+
+/*********************** For R_VDEC_SyncSeparation ***********************/
+/*! LPF cutoff frequency before vertical sync separation */
+typedef enum {
+ VDEC_LPF_VSYNC_NONE = 0, /*!< None */
+ VDEC_LPF_VSYNC_0_94, /*!< 0.94 MHz */
+ VDEC_LPF_VSYNC_0_67, /*!< 0.67 MHz */
+ VDEC_LPF_VSYNC_0_54, /*!< 0.54 MHz */
+ VDEC_LPF_VSYNC_0_47, /*!< 0.47 MHz */
+ VDEC_LPF_VSYNC_0_34, /*!< 0.34 MHz */
+ VDEC_LPF_VSYNC_0_27, /*!< 0.27 MHz */
+ VDEC_LPF_VSYNC_0_23, /*!< 0.23 MHz */
+ VDEC_LPF_VSYNC_NUM
+} vdec_lpfvsync_t;
+/*! LPF cutoff frequency before horizontal sync separation */
+typedef enum {
+ VDEC_LPF_HSYNC_NONE = 0, /*!< None */
+ VDEC_LPF_HSYNC_2_15, /*!< 2.15 MHz */
+ VDEC_LPF_HSYNC_1_88, /*!< 1.88 MHz */
+ VDEC_LPF_HSYNC_1_34, /*!< 1.34 MHz */
+ VDEC_LPF_HSYNC_1_07, /*!< 1.07 MHz */
+ VDEC_LPF_HSYNC_0_94, /*!< 0.94 MHz */
+ VDEC_LPF_HSYNC_0_67, /*!< 0.67 MHz */
+ VDEC_LPF_HSYNC_0_54, /*!< 0.54 MHz */
+ VDEC_LPF_HSYNC_NUM
+} vdec_lpfhsync_t;
+/*! Noise reduction LPF parameter */
+typedef struct {
+ vdec_lpfvsync_t lpfvsync; /*!< LPF cutoff frequency before vertical sync separation */
+ vdec_lpfhsync_t lpfhsync; /*!< LPF cutoff frequency before horizontal sync separation */
+} vdec_noise_rd_lpf_t;
+/*! Reference level operation speed control for composite sync separation (for Hsync signal) */
+typedef enum {
+ VDEC_VELOCITY_SHIFT_1 = 0, /*!< x1 */
+ VDEC_VELOCITY_SHIFT_2, /*!< x2 */
+ VDEC_VELOCITY_SHIFT_4, /*!< x4 */
+ VDEC_VELOCITY_SHIFT_8, /*!< x8 */
+ VDEC_VELOCITY_SHIFT_16, /*!< x16 */
+ VDEC_VELOCITY_SHIFT_32, /*!< x32 */
+ VDEC_VELOCITY_SHIFT_64, /*!< x64 */
+ VDEC_VELOCITY_SHIFT_128, /*!< x128 */
+ VDEC_VELOCITY_SHIFT_256, /*!< x256 */
+ VDEC_VELOCITY_SHIFT_NUM
+} vdec_velocityshift_h_t;
+/*! Auto-slice level setting for composite sync separation circuit */
+typedef enum {
+ VDEC_SLICE_MODE_MANULAL = 0, /*!< Manual setting */
+ VDEC_SLICE_MODE_AUTO_25, /*!< 25% of sync depth (Auto) */
+ VDEC_SLICE_MODE_AUTO_50, /*!< 50% of sync depth (Auto) */
+ VDEC_SLICE_MODE_AUTO_75, /*!< 75% of sync depth (Auto) */
+ VDEC_SLICE_MODE_NUM
+} vdec_slicermode_t;
+/*! Clipping level */
+typedef enum {
+ VDEC_CLIP_LV_512 = 0, /*!< 512 */
+ VDEC_CLIP_LV_546, /*!< 546 */
+ VDEC_CLIP_LV_580, /*!< 580 */
+ VDEC_CLIP_LV_614, /*!< 614 */
+ VDEC_CLIP_LV_648, /*!< 648 */
+ VDEC_CLIP_LV_682, /*!< 682 */
+ VDEC_CLIP_LV_716, /*!< 716 */
+ VDEC_CLIP_LV_750, /*!< 750 */
+ VDEC_CLIP_LV_785, /*!< 785 */
+ VDEC_CLIP_LV_819, /*!< 819 */
+ VDEC_CLIP_LV_853, /*!< 853 */
+ VDEC_CLIP_LV_887, /*!< 887 */
+ VDEC_CLIP_LV_921, /*!< 921 */
+ VDEC_CLIP_LV_955, /*!< 955 */
+ VDEC_CLIP_LV_989, /*!< 989 */
+ VDEC_CLIP_LV_1023, /*!< 1023 */
+ VDEC_CLIP_LV_NUM
+} vdec_ssclipsel_t;
+/*! Sync slicer */
+typedef struct {
+ vdec_velocityshift_h_t velocityshift_h; /*!< Reference level operation speed control for
+ composite sync separation (for Hsync signal) */
+ vdec_slicermode_t slicermode_h; /*!< Auto-slice level setting for composite sync separation circuit
+ (for Hsync signal) */
+ vdec_slicermode_t slicermode_v; /*!< Auto-slice level setting for composite sync separation circuit
+ (for Vsync signal) */
+ uint16_t syncmaxduty_h; /*!< Max ratio of horizontal cycle
+ to horizontal sync signal pulse width */
+ uint16_t syncminduty_h; /*!< Min ratio of horizontal cycle
+ to horizontal sync signal pulse width */
+ vdec_ssclipsel_t ssclipsel; /*!< Clipping level */
+ uint16_t csyncslice_h; /*!< Slice level for composite sync signal separation
+ (for Hsync signal) */
+ uint16_t syncmaxduty_v; /*!< Max ratio of horizontal cycle
+ to vertical sync signal pulse width */
+ uint16_t syncminduty_v; /*!< Min ratio of horizontal cycle
+ to horizontal sync signal pulse width */
+ vdec_onoff_t vsyncdelay; /*!< Delays the separated vertical sync signal
+ for 1/4 horizontal cycle */
+ uint16_t vsyncslice; /*!< Threshold for vertical sync separation */
+ uint16_t csyncslice_v; /*!< Slice level for composite sync signal separation
+ (for Vsync signal) */
+} vdec_sync_slicer_t;
+/*! Horizontal AFC VBI period operating mode */
+typedef enum {
+ VDEC_HAFCMD_FIX_PHST = 0, /*!< Loop gain is fixed and phase comparison is stopped
+ during VBI period */
+ VDEC_HAFCMD_FIX_LGRD, /*!< Loop gain is fixed and loop gain is reduced during VBI period */
+ VDEC_HAFCMD_AUTO_PHST, /*!< Loop gain is automatically controlled and
+ phase comparison is stopped during VBI period */
+ VDEC_HAFCMD_AUTO_LGRD, /*!< Loop gain is automatically controlled and loop gain is reduced
+ during VBI period */
+ VDEC_HAFCMD_NUM
+} vdec_hafcmode_t;
+/*! Phase comparator feedback adjust for low sync signal lock stability */
+typedef enum {
+ VDEC_PHDET_DIV_1_1 = 0, /*!< 1/1 */
+ VDEC_PHDET_DIV_1_2, /*!< 1/2 */
+ VDEC_PHDET_DIV_1_4, /*!< 1/4 */
+ VDEC_PHDET_DIV_1_8, /*!< 1/8 */
+ VDEC_PHDET_DIV_1_16, /*!< 1/16 */
+ VDEC_PHDET_DIV_1_32, /*!< 1/32 */
+ VDEC_PHDET_DIV_NUM
+} vdec_phdet_div_t;
+/*! Horizontal AFC parameter */
+typedef struct {
+ uint16_t hafcgain; /*!< Horizontal AFC loop gain */
+ uint16_t hafctyp; /*!< Horizontal AFC center oscillation frequency */
+ uint16_t hafcstart; /*!< Start line of horizontal AFC normal operation
+ (VBI process end line) */
+ vdec_onoff_t nox2hosc; /*!< Disable of horizontal AFC double speed detection */
+ uint16_t hafcmax; /*!< Maximum oscillation frequency of horizontal AFC */
+ uint16_t hafcend; /*!< End line of horizontal AFC normal operation
+ (VBI process start line) */
+ vdec_hafcmode_t hafcmode; /*!< Horizontal AFC VBI period operating mode */
+ uint16_t hafcmin; /*!< Min oscillation frequency of horizontal AFC */
+ vdec_onoff_t phdet_fix; /*!< Forcible or LOWGAIN control */
+ vdec_phdet_div_t phdet_div; /*!< Phase comparator feedback adjust for low sync signal lock stability */
+} vdec_horizontal_afc_t;
+/*! Vertical countdown center oscillation frequency */
+typedef enum {
+ VDEC_VCD_FRQ_AUTO = 0, /*!< Auto-detection */
+ VDEC_VCD_FRQ_50HZ, /*!< 50.00 Hz */
+ VDEC_VCD_FRQ_59_94HZ, /*!< 59.94 Hz */
+ VDEC_VCD_FRQ_60HZ, /*!< 60.00 Hz */
+ VDEC_VCD_FRQ_NUM
+} vdec_vcddefault_t;
+/*! Vertical count-down parameter */
+typedef struct {
+ vdec_onoff_t novcd50_; /*!< Vertical countdown 50-Hz oscillation mode */
+ vdec_onoff_t novcd60_; /*!< Vertical countdown 60-Hz (59.94-Hz) oscillation mode */
+ vdec_vcddefault_t vcddefault; /*!< Vertical countdown center oscillation frequency */
+ uint16_t vcdwindow; /*!< Vertical countdown sync area */
+ uint16_t vcdoffset; /*!< Vertical countdown minimum oscillation frequency */
+} vdec_vcount_down_t;
+/*! AGC/PGA parameter */
+typedef struct {
+ vdec_onoff_t agcmode; /*!< A/D converter AGC ON/OFF control & PGA switch */
+ vdec_onoff_t doreduce; /*!< Manual control of sync signal amplitude detection during VBI period */
+ vdec_onoff_t noreduce_; /*!< Control of sync signal amplitude detection during VBI period */
+ uint16_t agcresponse; /*!< AGC response speed */
+ uint16_t agclevel; /*!< Sync signal reference amplitude */
+ uint16_t agcprecis; /*!< AGC gain adjustment accuracy */
+ uint16_t pga_gain; /*!< PGA gain */
+} vdec_agc_t;
+/*! Peak luminance value to operate peak limiter */
+typedef enum {
+ VDEC_PEAKLV_LIM_OFF =0, /*!< Limiter OFF */
+ VDEC_PEAKLV_1008, /*!< 1008 LSB */
+ VDEC_PEAKLV_992, /*!< 992 LSB */
+ VDEC_PEAKLV_960, /*!< 960 LSB */
+ VDEC_PEAKLV_NUM
+} vdec_peaklevel_t;
+/*! Maximum compression rate of peak limiter */
+typedef enum {
+ VDEC_PEAKRATIO_50 = 0, /*!< Compressed up to 50% */
+ VDEC_PEAKRATIO_25, /*!< Compressed up to 25% */
+ VDEC_PEAKRATIO_12_5, /*!< Compressed up to 12.5% */
+ VDEC_PEAKRATIO_0, /*!< Compressed up to 0% */
+ VDEC_PEAKRATIO_NUM
+} vdec_peakratio_t;
+/*! Peak limiter control parameter */
+typedef struct {
+ vdec_peaklevel_t peaklevel; /*!< Peak luminance value limited by peak limiter (video signal level) */
+ uint16_t peakattack; /*!< Response speed with peak limiter gain decreased */
+ uint16_t peakrelease; /*!< Response speed with peak limiter gain increased */
+ vdec_peakratio_t peakratio; /*!< Maximum compression rate of peak limiter */
+ uint16_t maxpeaksamples; /*!< Allowable number of overflowing pixels */
+} vdec_peak_limiter_t;
+/*! Sync separation parameter */
+typedef struct {
+ vdec_noise_rd_lpf_t * noise_rd_lpf; /*!< Noise reduction LPF parameter */
+ vdec_sync_slicer_t * sync_slicer; /*!< Auto level control sync slicer parameter */
+ vdec_horizontal_afc_t * horizontal_afc; /*!< Horizontal AFC parameter */
+ vdec_vcount_down_t * vcount_down; /*!< Vertical count-down parameter */
+ vdec_agc_t * agc; /*!< AGC/PGA parameter */
+ vdec_peak_limiter_t * peak_limiter; /*!< Peak limiter control parameter */
+} vdec_sync_separation_t;
+
+/*********************** For R_VDEC_YcSeparation ***********************/
+/*! Over-range control parameter */
+typedef struct {
+ uint16_t radj_o_level0; /*!< A/D over-threshold level (between levels 0 and 1) */
+ uint16_t radj_u_level0; /*!< A/D under-threshold level (between levels 2 and 3) */
+ uint16_t radj_o_level1; /*!< A/D over-threshold level (between levels 1 and 2) */
+ uint16_t radj_u_level1; /*!< A/D under-threshold level (between levels 1 and 2) */
+ uint16_t radj_o_level2; /*!< A/D over-threshold level (between levels 2 and 3) */
+ uint16_t radj_u_level2; /*!< A/D under-threshold level (between levels 0 and 1) */
+ vdec_onoff_t ucmp_sw; /*!< Over-range detection enable */
+ vdec_onoff_t dcmp_sw; /*!< Under-range detection enable */
+ vdec_onoff_t hwide_sw; /*!< Horizontal enlargement of over/under-range level */
+} vdec_over_range_t;
+/*! Latter-stage BPF select */
+typedef enum {
+ VDEC_LSTG_BPFSEL_BYPASS = 0, /*!< Bypass */
+ VDEC_LSTG_BPFSEL_17TAP = 1 /*!< 17 TAP */
+} vdec_lstg_bpfsel_t;
+/*! Former-stage BPF select */
+typedef enum {
+ VDEC_FSTG_BPFSEL_17TAP = 0, /*!< 17 TAP */
+ VDEC_FSTG_BPFSEL_9TAP = 1 /*!< 9 TAP */
+} vdec_fstg_bpfsel_t;
+/*! Horizontal filter and horizontal/vertical filter bandwidth switch signal */
+typedef enum {
+ VDEC_HFIL_TAP_SEL_17TAP = 0, /*!< 17 TAP */
+ VDEC_HFIL_TAP_SEL_9TAP = 1 /*!< 9 TAP */
+} vdec_hfil_tap_sel_t;
+/*! Mixing ratio of signals after passing filters */
+typedef enum {
+ VDEC_FILMIX_RATIO_0 = 0, /*!< 0% */
+ VDEC_FILMIX_RATIO_12_5, /*!< 12.5% */
+ VDEC_FILMIX_RATIO_25, /*!< 25% */
+ VDEC_FILMIX_RATIO_37_5, /*!< 37.5% */
+ VDEC_FILMIX_RATIO_50, /*!< 50% */
+ VDEC_FILMIX_RATIO_62_5, /*!< 62.5% */
+ VDEC_FILMIX_RATIO_75, /*!< 75% */
+ VDEC_FILMIX_RATIO_87_5, /*!< 87.5% */
+ VDEC_FILMIX_RATIO_100, /*!< 100% */
+ VDEC_FILMIX_RATIO_NUM
+} vdec_filmix_ratio_t;
+/*! Two-dimensional cascade/TAKE-OFF filter mode select */
+typedef enum {
+ VDEC_2DFIL_MDSEL_BYPASS = 0, /*!< Bypass */
+ VDEC_2DFIL_MDSEL_CASCADE, /*!< Cascade filter */
+ VDEC_2DFIL_MDSEL_TAKEOFF, /*!< TAKE-OFF filter */
+ VDEC_2DFIL_MDSEL_NUM
+} vdec_2dfil_mdsel_t;
+/*! Two-dimensional cascade filter select */
+typedef enum {
+ VDEC_2D_FIL_SEL_BYPASS = 0, /*!< Bypass */
+ VDEC_2D_FIL_SEL_17TAP = 1 /*!< 17 TAP */
+} vdec_2d_fil_sel_t;
+/*! Y/C separation control parameter */
+typedef struct {
+ uint16_t k15; /*!< Two-dimensional Y/C separation filter select coefficient, K15 */
+ uint16_t k13; /*!< Two-dimensional Y/C separation filter select coefficient, K13 */
+ uint16_t k11; /*!< Two-dimensional Y/C separation filter select coefficient, K11 */
+ uint16_t k16; /*!< Two-dimensional Y/C separation filter select coefficient, K16 */
+ uint16_t k14; /*!< Two-dimensional Y/C separation filter select coefficient, K14 */
+ uint16_t k12; /*!< Two-dimensional Y/C separation filter select coefficient, K12 */
+ uint16_t k22a; /*!< Two-dimensional Y/C separation filter select coefficient, K22A */
+ uint16_t k21a; /*!< Two-dimensional Y/C separation filter select coefficient, K21A */
+ uint16_t k22b; /*!< Two-dimensional Y/C separation filter select coefficient, K22B */
+ uint16_t k21b; /*!< Two-dimensional Y/C separation filter select coefficient, K21B */
+ uint16_t k23b; /*!< Two-dimensional Y/C separation filter select coefficient, K23B */
+ uint16_t k23a; /*!< Two-dimensional Y/C separation filter select coefficient, K23A */
+ uint16_t k24; /*!< Two-dimensional Y/C separation filter select coefficient, K24 */
+ vdec_lstg_bpfsel_t hbpf_narrow; /*!< Latter-stage horizontal BPF select */
+ vdec_lstg_bpfsel_t hvbpf_narrow; /*!< Latter-stage horizontal/vertical BPF select */
+ vdec_fstg_bpfsel_t hbpf1_9tap_on; /*!< Former-stage horizontal BPF select */
+ vdec_fstg_bpfsel_t hvbpf1_9tap_on; /*!< Former-stage horizontal/vertical BPF select */
+ vdec_hfil_tap_sel_t hfil_tap_sel; /*!< Horizontal filter and horizontal/vertical filter
+ bandwidth switch signal */
+ vdec_onoff_t det2_on; /*!< Two-dimensional filter mixing select */
+ vdec_filmix_ratio_t hsel_mix_y; /*!< Mixing ratio of signal after passing horizontal filter
+ to signal after passing former-stage horizontal filter */
+ vdec_filmix_ratio_t vsel_mix_y; /*!< Mixing ratio of signal after passing vertical filter
+ to signal after passing former-stage horizontal/vertical filter */
+ vdec_filmix_ratio_t hvsel_mix_y; /*!< Mixing ratio of signal after passing horizontal/vertical filter
+ to signal after passing former-stage horizontal/vertical filter */
+ uint16_t v_y_level; /*!< Vertical luminance detection level for correlation detection filter */
+ vdec_filmix_ratio_t det2_mix_c; /*!< Mixing ratio of C signal after passing horizontal/vertical adaptive filter
+ to signal after passing correlation detection filter */
+ vdec_filmix_ratio_t det2_mix_y; /*!< Mixing ratio of C signal for Y generation after passing
+ horizontal/vertical adaptive filter to signal
+ after passing correlation detection filter */
+ vdec_2dfil_mdsel_t fil2_mode_2d; /*!< Two-dimensional cascade/TAKE-OFF filter mode select */
+ vdec_2d_fil_sel_t fil2_narrow_2d; /*!< Two-dimensional cascade filter select */
+} vdec_yc_sep_ctrl_t;
+/*! Chroma filter TAP coefficient for Y/C separation */
+typedef struct {
+ uint16_t fil2_2d_f[VDEC_CHRFIL_TAPCOEF_NUM]; /*!< Chroma filter TAP coefficient 0 to 8 */
+} vdec_chrfil_tap_t;
+/*! Y/C separation parameter */
+typedef struct {
+ vdec_over_range_t * over_range; /*!< Over-range control parameter */
+ vdec_yc_sep_ctrl_t * yc_sep_ctrl; /*!< Y/C separation control parameter */
+ const vdec_chrfil_tap_t * fil2_2d_wa; /*!< Two-dimensional cascade broadband (3.58/4.43/SECAM-DR)/TAKE-OFF
+ filter TAP coefficient */
+ const vdec_chrfil_tap_t * fil2_2d_wb; /*!< Two-dimensional cascade broadband (SECAM-DB) filter
+ TAP coefficient */
+ const vdec_chrfil_tap_t * fil2_2d_na; /*!< Two-dimensional cascade narrowband (3.58/4.43/SECAM-DR) filter
+ TAP coefficient */
+ const vdec_chrfil_tap_t * fil2_2d_nb; /*!< Two-dimensional cascade narrowband (SECAMDB) filter
+ TAP coefficient */
+} vdec_yc_separation_t;
+
+/*********************** For R_VDEC_ChromaDecoding ***********************/
+/*! Color system */
+typedef enum {
+ VDEC_COL_SYS_NTSC = 0, /*!< NTSC */
+ VDEC_COL_SYS_PAL, /*!< PAL */
+ VDEC_COL_SYS_SECAM, /*!< SECAM */
+ VDEC_COL_SYS_NON, /*!< Not specified/undetectable */
+ VDEC_COL_SYS_NUM /*!< The number of color system settings */
+} vdec_color_sys_t;
+/*! Averaging processing for pre-demodulated line */
+typedef enum {
+ VDEC_DEMOD_MD_NO = 0, /*!< No processing */
+ VDEC_DEMOD_MD_PAL = 2 /*!< For PAL */
+} vdec_demodmode_t;
+/*! Color system detection parameter */
+typedef struct {
+ vdec_color_sys_t defaultsys; /*!< Default color system */
+ vdec_onoff_t nontsc358_; /*!< NTSC-M detection control */
+ vdec_onoff_t nontsc443_; /*!< NTSC-4.43 detection control */
+ vdec_onoff_t nopalm_; /*!< PAL-M detection control */
+ vdec_onoff_t nopaln_; /*!< PAL-N detection control */
+ vdec_onoff_t nopal443_; /*!< PAL-B, G, H, I, D detection control */
+ vdec_onoff_t nosecam_; /*!< SECAM detection control */
+ uint16_t lumadelay; /*!< Luminance signal delay adjustment */
+ vdec_onoff_t chromalpf; /*!< LPF for demodulated chroma */
+ vdec_demodmode_t demodmode; /*!< Averaging processing for pre-demodulated line */
+} vdec_chrmdec_ctrl_t;
+/*! Burst lock PLL lock range */
+typedef enum {
+ VDEC_LOCK_RANGE_400HZ = 0, /*!< +-400 Hz */
+ VDEC_LOCK_RANGE_800HZ, /*!< +-800 Hz */
+ VDEC_LOCK_RANGE_1200HZ, /*!< +-1200 Hz */
+ VDEC_LOCK_RANGE_1600HZ, /*!< +-1600 Hz */
+ VDEC_LOCK_RANGE_NUM
+} vdec_lockrange_t;
+/*! BCO parameter */
+typedef struct {
+ vdec_lockrange_t lockrange; /*!< Burst lock PLL lock range */
+ uint16_t loopgain; /*!< Burst lock PLL loop gain */
+ uint16_t locklimit; /*!< Level for burst lock PLL to re-search free-run frequency */
+ uint16_t bgpcheck; /*!< burst gate pulse position check */
+ uint16_t bgpwidth; /*!< burst gate pulse width */
+ uint16_t bgpstart; /*!< burst gate pulse start position */
+} vdec_burst_lock_t;
+/*! ACC operating mode */
+typedef enum {
+ VDEC_ACC_MD_AUTO = 0, /*!< Auto gain */
+ VDEC_ACC_MD_MANUAL = 1 /*!< Manual gain */
+} vdec_accmode_t;
+/*! Maximum ACC gain */
+typedef enum {
+ VDEC_ACC_MAX_GAIN_6 = 0, /*!< 6 times */
+ VDEC_ACC_MAX_GAIN_8, /*!< 8 times */
+ VDEC_ACC_MAX_GAIN_12, /*!< 12 times */
+ VDEC_ACC_MAX_GAIN_16, /*!< 16 times */
+ VDEC_ACC_MAX_GAIN_NUM
+} vdec_accmaxgain_t;
+/*! Chroma manual gain (sub) */
+typedef enum {
+ VDEC_CHRM_SB_GAIN_1 = 0, /*!< 1 time */
+ VDEC_CHRM_SB_GAIN_2, /*!< 2 times */
+ VDEC_CHRM_SB_GAIN_4, /*!< 4 times */
+ VDEC_CHRM_SB_GAIN_8, /*!< 8 times */
+ VDEC_CHRM_SB_GAIN_NUM
+} vdec_chrm_subgain_t;
+/*! ACC and color killer parameter */
+typedef struct {
+ vdec_accmode_t accmode; /*!< ACC operating mode */
+ vdec_accmaxgain_t accmaxgain; /*!< Maximum ACC Gain */
+ uint16_t acclevel; /*!< ACC reference color burst amplitude */
+ vdec_chrm_subgain_t chromasubgain; /*!< Chroma manual gain (sub) */
+ uint16_t chromamaingain; /*!< Chroma manual gain (main) */
+ uint16_t accresponse; /*!< ACC response speed */
+ uint16_t accprecis; /*!< ACC gain adjustment accuracy */
+ vdec_onoff_t killermode; /*!< Forced color killer mode ON/OFF */
+ uint16_t killerlevel; /*!< Color killer operation start point */
+ uint16_t killeroffset; /*!< Color killer offset */
+} vdec_acc_t;
+/*! TINT correction/R-Y axis correction parameter (only valid for NTSC/PAL) */
+typedef struct {
+ uint16_t tintsub; /*!< Fine adjustment of R-Y demodulation axis */
+ uint16_t tintmain; /*!< Hue adjustment level */
+} vdec_tint_ry_t;
+/*! Chroma decoding parameter */
+typedef struct {
+ vdec_chrmdec_ctrl_t * chrmdec_ctrl; /*!< Color system detection parameter */
+ vdec_burst_lock_t * burst_lock; /*!< BCO parameter */
+ vdec_acc_t * acc; /*!< ACC and color killer parameter */
+ vdec_tint_ry_t * tint_ry; /*!< TINT correction/R-Y axis correction parameter */
+} vdec_chroma_decoding_t;
+
+/*********************** For R_VDEC_DigitalClamp ***********************/
+/*! Clamp level setting mode */
+typedef enum {
+ VDEC_DCPMODE_MANUAL = 0, /*!< Manual clamp level setting */
+ VDEC_DCPMODE_AUTO = 1 /*!< Auto clamp level setting */
+} vdec_dcpmode_t;
+/*! Pedestal clamp parameter */
+typedef struct {
+ vdec_dcpmode_t dcpmode_y; /*!< Clamp level setting mode (Y signal) */
+ uint16_t blanklevel_y; /*!< Clamp offset level (Y signal) */
+ uint16_t dcppos_y; /*!< Digital clamp pulse horizontal start position (Y signal) */
+} vdec_pedestal_clamp_t;
+/*! Center clamp parameter */
+typedef struct {
+ vdec_dcpmode_t dcpmode_c; /*!< Clamp level setting mode (Cb/Cr signal) */
+ uint16_t blanklevel_cb; /*!< Clamp offset level (Cb signal) */
+ uint16_t blanklevel_cr; /*!< Clamp offset level (Cr signal) */
+ uint16_t dcppos_c; /*!< Digital clamp pulse horizontal start position (Cb/Cr signal) */
+} vdec_center_clamp_t;
+/*! Video signal for autocorrelation function */
+typedef enum {
+ VDEC_ACFINPUT_Y = 0, /*!< Y signal */
+ VDEC_ACFINPUT_CB, /*!< Cb signal */
+ VDEC_ACFINPUT_CR, /*!< Cr signal */
+ VDEC_ACFINPUT_NUM
+} vdec_acfinput_t;
+/*! Noise detection parameter */
+typedef struct {
+ vdec_acfinput_t acfinput; /*!< Video signal for autocorrelation function */
+ uint16_t acflagtime; /*!< Delay time for autocorrelation function calculation */
+ uint16_t acffilter; /*!< Smoothing parameter of autocorrelation function data */
+} vdec_noise_det_t;
+/*! Digital clamp parameter */
+typedef struct {
+ vdec_onoff_t dcpcheck; /*!< Digital clamp pulse position check */
+ uint16_t dcpresponse; /*!< Digital clamp response speed */
+ uint16_t dcpstart; /*!< Digital clamp start line */
+ uint16_t dcpend; /*!< Digital clamp end line */
+ uint16_t dcpwidth; /*!< Digital clamp pulse width */
+ vdec_pedestal_clamp_t * pedestal_clamp; /*!< Pedestal clamp parameter */
+ vdec_center_clamp_t * center_clamp; /*!< Center clamp parameter */
+ vdec_noise_det_t * noise_det; /*!< Noise detection parameter */
+} vdec_degital_clamp_t;
+
+/*********************** For R_VDEC_Output ***********************/
+/*! Output adjustment parameter */
+typedef struct {
+ uint16_t y_gain2; /*!< Y signal gain coefficient */
+ uint16_t cb_gain2; /*!< Cb signal gain coefficient */
+ uint16_t cr_gain2; /*!< Cr signal gain coefficient */
+} vdec_output_t;
+
+/*********************** For R_VDEC_Query ***********************/
+/*! Answer */
+typedef enum {
+ VDEC_NO = 0, /*!< No */
+ VDEC_YES = 1 /*!< Yes */
+} vdec_answer_t;
+/*! Lock state */
+typedef enum {
+ VDEC_UNLOCK = 0, /*!< Unlocked */
+ VDEC_LOCK = 1 /*!< Locked */
+} vdec_lock_t;
+/*! Speed detection result */
+typedef enum {
+ VDEC_FHMD_NORMAL = 0, /*!< Normal speed */
+ VDEC_FHMD_MULTIPLIED = 1 /*!< Multiplied speed */
+} vdec_fhmode_t;
+/*! Vertical countdown oscillation mode */
+typedef enum {
+ VDEC_FVMD_50HZ = 0, /*!< 50 Hz */
+ VDEC_FVMD_60HZ = 1 /*!< 60 Hz */
+} vdec_fvmode_t;
+/*! Color sub-carrier frequency detection result */
+typedef enum {
+ VDEC_FSCMD_3_58 = 0, /*!< 3.58 MHz */
+ VDEC_FSCMD_4_43 = 1 /*!< 4.43 MHz */
+} vdec_fscmode_t;
+/*! Sync separation parameters (for query) */
+typedef struct {
+ vdec_lock_t fhlock; /*!< Horizontal AFC lock detection result */
+ vdec_answer_t isnoisy; /*!< Detection result of low S/N signal by sync separation */
+ vdec_fhmode_t fhmode; /*!< Speed detection result */
+ vdec_answer_t nosignal_; /*!< No-signal detection result */
+ vdec_lock_t fvlock; /*!< Vertical countdown lock detection result */
+ vdec_fvmode_t fvmode; /*!< Vertical countdown oscillation mode */
+ vdec_answer_t interlaced; /*!< Interlace detection result */
+ uint16_t fvcount; /*!< Vertical cycle measurement result */
+ uint32_t fhcount; /*!< Horizontal AFC oscillation cycle */
+ vdec_answer_t isreduced; /*!< Sync amplitude detection result during VBI period */
+ uint16_t syncdepth; /*!< Sync pulse amplitude detection result */
+} vdec_q_sync_sep_t;
+/*! AGC parameters (for query) */
+typedef struct {
+ uint16_t highsamples; /*!< Number of pixels which have larger luminance value than peak luminance
+ limited by peak limiter */
+ uint16_t peaksamples; /*!< Number of overflowing pixels */
+ uint16_t agcconverge; /*!< AGC convergence detection result */
+ uint16_t agcgain; /*!< Current AGC gain value */
+} vdec_q_agc_t;
+/*! Chroma decoding parameters (for query) */
+typedef struct {
+ vdec_color_sys_t colorsys; /*!< Color system detection result */
+ vdec_fscmode_t fscmode; /*!< Color sub-carrier frequency detection result */
+ vdec_lock_t fsclock; /*!< Burst lock PLL lock state detection result */
+ vdec_answer_t noburst_; /*!< Color burst detection result */
+ vdec_chrm_subgain_t accsubgain; /*!< Current ACC gain value (sub) */
+ uint16_t accmaingain;/*!< Current ACC gain value (main) */
+ vdec_answer_t issecam; /*!< SECAM detection result */
+ vdec_answer_t ispal; /*!< PAL detection result */
+ vdec_answer_t isntsc; /*!< NTSC detection result */
+ uint16_t locklevel; /*!< Low S/N signal detection result by burst lock PLL */
+} vdec_q_chroma_dec_t;
+/*! Digital clamp parameters (for query) */
+typedef struct {
+ uint16_t clamplevel_cb; /*!< Digital clamp subtraction value (Cb signal) */
+ uint16_t clamplevel_y; /*!< Digital clamp subtraction value (Y signal) */
+ uint16_t clamplevel_cr; /*!< Digital clamp subtraction value (Cr signal) */
+ uint16_t acfstrength; /*!< Noise autocorrelation strength at digital clamp pulse position */
+} vdec_q_digital_clamp_t;
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+vdec_error_t R_VDEC_Initialize(
+ const vdec_channel_t ch,
+ const vdec_adc_vinsel_t vinsel,
+ void (* const init_func)(uint32_t),
+ const uint32_t user_num);
+vdec_error_t R_VDEC_Terminate(const vdec_channel_t ch, void (* const quit_func)(uint32_t), const uint32_t user_num);
+vdec_error_t R_VDEC_ActivePeriod(const vdec_channel_t ch, const vdec_active_period_t * const param);
+vdec_error_t R_VDEC_SyncSeparation(const vdec_channel_t ch, const vdec_sync_separation_t * const param);
+vdec_error_t R_VDEC_YcSeparation(const vdec_channel_t ch, const vdec_yc_separation_t * const param);
+vdec_error_t R_VDEC_ChromaDecoding(const vdec_channel_t ch, const vdec_chroma_decoding_t * const param);
+vdec_error_t R_VDEC_DigitalClamp(const vdec_channel_t ch, const vdec_degital_clamp_t * const param);
+vdec_error_t R_VDEC_Output(const vdec_channel_t ch, const vdec_output_t * const param);
+vdec_error_t R_VDEC_Query(
+ const vdec_channel_t ch,
+ vdec_q_sync_sep_t * const q_sync_sep,
+ vdec_q_agc_t * const q_agc,
+ vdec_q_chroma_dec_t * const q_chroma_dec,
+ vdec_q_digital_clamp_t * const q_digital_clamp);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* R_VDEC_H */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/drivers/vdec/include/r_vdec_user.h Fri Jun 26 02:17:53 2015 +0000 @@ -0,0 +1,49 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/**************************************************************************//** +* @file r_vdec_user.h +* @version 1.00 +* $Rev: 199 $ +* $Date:: 2014-05-23 16:33:52 +0900#$ +* @brief VDEC driver user-defined header +******************************************************************************/ + +#ifndef R_VDEC_USER_H +#define R_VDEC_USER_H + +/****************************************************************************** +Includes <System Includes> , "Project Includes" +******************************************************************************/ +#include "r_typedefs.h" +#include "iodefine.h" + + +/****************************************************************************** +Macro definitions +******************************************************************************/ +/*! Compilation switch to enable parameter check functions<br> + If this definition is enabled, the parameter check in each API function will be performed. */ +#define R_VDEC_CHECK_PARAMETERS + + +#endif /* R_VDEC_USER_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/vdec/src/r_vdec.c Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,345 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file r_vdec.c
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief VDEC driver API function
+******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_vdec.h"
+#include "r_vdec_user.h"
+#include "r_vdec_register.h"
+#include "r_vdec_check_parameter.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+ * @brief VDEC driver initialization
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Calls the user-defined function specified in init_func.
+ * - Sets up the input pins.
+ * @param[in] ch : Channel
+ * @param[in] vinsel : Input pin control
+ * - VDEC_ADC_VINSEL_VIN1
+ * - VDEC_ADC_VINSEL_VIN2
+ * @param[in] init_func : Pointer to a user-defined function
+ * @param[in] user_num : User defined number
+ * @retval Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_Initialize (
+ const vdec_channel_t ch,
+ const vdec_adc_vinsel_t vinsel,
+ void (* const init_func)(uint32_t),
+ const uint32_t user_num)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+#ifdef R_VDEC_CHECK_PARAMETERS
+ if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+ vdec_error = VDEC_ERR_CHANNEL; /* Channel error */
+ }
+ if (vdec_error == VDEC_OK) {
+ vdec_error = VDEC_InitializeCheckParam(vinsel);
+ }
+#endif /* R_VDEC_CHECK_PARAMETERS */
+ if (vdec_error == VDEC_OK) {
+ /* User-defined function */
+ if (init_func != 0) {
+ init_func(user_num);
+ }
+ VDEC_Initialize(ch, vinsel);
+ }
+ return vdec_error;
+} /* End of function R_VDEC_Initialize() */
+
+/**************************************************************************//**
+ * @brief VDEC driver termination
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Calls the user-defined function specified in quit_func.
+ * @param[in] ch : Channel
+ * @param[in] quit_func : Pointer to a user-defined function
+ * @param[in] user_num : User defined number
+ * @retval Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_Terminate (const vdec_channel_t ch, void (* const quit_func)(uint32_t), const uint32_t user_num)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+#ifdef R_VDEC_CHECK_PARAMETERS
+ if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+ vdec_error = VDEC_ERR_CHANNEL; /* Channel error */
+ }
+#endif /* R_VDEC_CHECK_PARAMETERS */
+ if (vdec_error == VDEC_OK) {
+ /* User-defined function */
+ if (quit_func != 0) {
+ quit_func(user_num);
+ }
+ }
+ return vdec_error;
+} /* End of function R_VDEC_Terminate() */
+
+/**************************************************************************//**
+ * @brief Active image period setup
+ *
+ * Description:<br>
+ * This function configures the active image period.
+ * @param[in] ch : Channel
+ * @param[in] param : Active image period parameter
+ * @retval Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_ActivePeriod (const vdec_channel_t ch, const vdec_active_period_t * const param)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+#ifdef R_VDEC_CHECK_PARAMETERS
+ if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+ vdec_error = VDEC_ERR_CHANNEL; /* Channel error */
+ }
+ if (vdec_error == VDEC_OK) {
+ vdec_error = VDEC_ActivePeriodCheckParam(param);
+ }
+#endif /* R_VDEC_CHECK_PARAMETERS */
+ if (vdec_error == VDEC_OK) {
+ VDEC_ActivePeriod(ch, param);
+ }
+ return vdec_error;
+} /* End of function R_VDEC_ActivePeriod() */
+
+/**************************************************************************//**
+ * @brief Sync separation processing
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Configures the noise reduction LPF.
+ * - Configures the auto level control sync slicer.
+ * - Configures the horizontal AFC.
+ * - Configures the vertical count-down.
+ * - Configures the AGC.
+ * - Configures the peak limiter control.
+ * @param[in] ch : Channel
+ * @param[in] param : Sync separation parameter
+ * @retval Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_SyncSeparation (const vdec_channel_t ch, const vdec_sync_separation_t * const param)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+#ifdef R_VDEC_CHECK_PARAMETERS
+ if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+ vdec_error = VDEC_ERR_CHANNEL; /* Channel error */
+ }
+ if (vdec_error == VDEC_OK) {
+ vdec_error = VDEC_SyncSeparationCheckParam(param);
+ }
+#endif /* R_VDEC_CHECK_PARAMETERS */
+ if (vdec_error == VDEC_OK) {
+ VDEC_SyncSeparation(ch, param);
+ }
+ return vdec_error;
+} /* End of function R_VDEC_SyncSeparation() */
+
+/**************************************************************************//**
+ * @brief Y/C separation processing
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Configures the over-range control.
+ * - Configures the Y/C separation control.
+ * - Configures the chroma filter TAP coefficients for Y/C separation.
+ * @param[in] ch : Channel
+ * @param[in] param : Y/C separation parameter
+ * @retval Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_YcSeparation (const vdec_channel_t ch, const vdec_yc_separation_t * const param)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+#ifdef R_VDEC_CHECK_PARAMETERS
+ if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+ vdec_error = VDEC_ERR_CHANNEL; /* Channel error */
+ }
+ if (vdec_error == VDEC_OK) {
+ vdec_error = VDEC_YcSeparationCheckParam(param);
+ }
+#endif /* R_VDEC_CHECK_PARAMETERS */
+ if (vdec_error == VDEC_OK) {
+ VDEC_YcSeparation(ch, param);
+ }
+ return vdec_error;
+} /* End of function R_VDEC_YcSeparation() */
+
+/**************************************************************************//**
+ * @brief Chroma decoding processing
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Configures the color system detection.
+ * - Configures the BCO.
+ * - Configures the ACC/color killer.
+ * - Configures the TINT correction/R-Y axis correction.
+ * @param[in] ch : Channel
+ * @param[in] param : Chroma decoding parameter
+ * @retval Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_ChromaDecoding (const vdec_channel_t ch, const vdec_chroma_decoding_t * const param)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+#ifdef R_VDEC_CHECK_PARAMETERS
+ if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+ vdec_error = VDEC_ERR_CHANNEL; /* Channel error */
+ }
+ if (vdec_error == VDEC_OK) {
+ vdec_error = VDEC_ChromaDecodingCheckParam(param);
+ }
+#endif /* R_VDEC_CHECK_PARAMETERS */
+ if (vdec_error == VDEC_OK) {
+ VDEC_ChromaDecoding(ch, param);
+ }
+ return vdec_error;
+} /* End of function R_VDEC_ChromaDecoding() */
+
+/**************************************************************************//**
+ * @brief Digital clamp processing
+ *
+ * Description:<br>
+ * This function performs the following processing:
+ * - Configures the digital clamp control.
+ * - Configures the center clamp.
+ * - Configures the pedestal clamp.
+ * - Configures the noise detection control.
+ * @param[in] ch : Channel
+ * @param[in] param : Digital clamp parameter
+ * @retval Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_DigitalClamp (const vdec_channel_t ch, const vdec_degital_clamp_t * const param)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+#ifdef R_VDEC_CHECK_PARAMETERS
+ if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+ vdec_error = VDEC_ERR_CHANNEL; /* Channel error */
+ }
+ if (vdec_error == VDEC_OK) {
+ vdec_error = VDEC_DigitalClampCheckParam(param);
+ }
+#endif /* R_VDEC_CHECK_PARAMETERS */
+ if (vdec_error == VDEC_OK) {
+ VDEC_DigitalClamp(ch, param);
+ }
+ return vdec_error;
+} /* End of function R_VDEC_DigitalClamp() */
+
+/**************************************************************************//**
+ * @brief Output adjustment processing
+ *
+ * Description:<br>
+ * This function makes settings for output adjustment.
+ * @param[in] ch : Channel
+ * @param[in] param : Output adjustment parameter
+ * @retval Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_Output (const vdec_channel_t ch, const vdec_output_t * const param)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+#ifdef R_VDEC_CHECK_PARAMETERS
+ if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+ vdec_error = VDEC_ERR_CHANNEL; /* Channel error */
+ }
+ if (vdec_error == VDEC_OK) {
+ vdec_error = VDEC_OutputCheckParam(param);
+ }
+#endif /* R_VDEC_CHECK_PARAMETERS */
+ if (vdec_error == VDEC_OK) {
+ VDEC_Output(ch, param);
+ }
+ return vdec_error;
+} /* End of function R_VDEC_Output() */
+
+/**************************************************************************//**
+ * @brief VDEC information acquisition processing
+ *
+ * Description:<br>
+ * This gets the parameters of the VDEC modules. The parameters that can be obtained are listed below.
+ * - Sync separation parameters
+ * - AGC parameters
+ * - Chroma decoding parameters
+ * - Digital clamp parameters
+ * @param[in] ch : Channel
+ * @param[out] q_sync_sep : Pointer to the place where the sync separation parameters are stored.
+ * @param[out] q_agc : Pointer to the place where the AGC parameters are stored.
+ * @param[out] q_chroma_dec : Pointer to the place where the chroma decoding parameters are stored.
+ * @param[out] q_digital_clamp : Pointer to the place where the digital clamp parameters are stored.
+ * @retval Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_Query (
+ const vdec_channel_t ch,
+ vdec_q_sync_sep_t * const q_sync_sep,
+ vdec_q_agc_t * const q_agc,
+ vdec_q_chroma_dec_t * const q_chroma_dec,
+ vdec_q_digital_clamp_t * const q_digital_clamp)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+#ifdef R_VDEC_CHECK_PARAMETERS
+ if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+ vdec_error = VDEC_ERR_CHANNEL; /* Channel error */
+ }
+#endif /* R_VDEC_CHECK_PARAMETERS */
+ if (vdec_error == VDEC_OK) {
+ VDEC_Query(ch, q_sync_sep, q_agc, q_chroma_dec, q_digital_clamp);
+ }
+ return vdec_error;
+} /* End of function R_VDEC_Query() */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/vdec/src/r_vdec_check_parameter.c Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,983 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file r_vdec_check_parameter.c
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief VDEC driver parameter check processing
+******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_vdec.h"
+#include "r_vdec_user.h"
+#include "r_vdec_check_parameter.h"
+
+
+#ifdef R_VDEC_CHECK_PARAMETERS
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* Valid bit range */
+#define VDEC_CPARA_RANGE_0X00000001 (0x00000001u)
+#define VDEC_CPARA_RANGE_0X00000003 (0x00000003u)
+#define VDEC_CPARA_RANGE_0X00000007 (0x00000007u)
+#define VDEC_CPARA_RANGE_0X0000000F (0x0000000Fu)
+#define VDEC_CPARA_RANGE_0X0000001F (0x0000001Fu)
+#define VDEC_CPARA_RANGE_0X0000003F (0x0000003Fu)
+#define VDEC_CPARA_RANGE_0X0000007F (0x0000007Fu)
+#define VDEC_CPARA_RANGE_0X000000FF (0x000000FFu)
+#define VDEC_CPARA_RANGE_0X000001FF (0x000001FFu)
+#define VDEC_CPARA_RANGE_0X000003FF (0x000003FFu)
+#define VDEC_CPARA_RANGE_0X000007FF (0x000007FFu)
+#define VDEC_CPARA_RANGE_0X00001FFF (0x00001FFFu)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static vdec_error_t NoiseReductionLPFCheckParam(const vdec_noise_rd_lpf_t * const p_noise_rd_lpf);
+static vdec_error_t SyncSlicerCheckParam(const vdec_sync_slicer_t * const p_sync_slicer);
+static vdec_error_t HorizontalAFCCheckParam(const vdec_horizontal_afc_t * const p_horizontal_afc);
+static vdec_error_t VerticalCountdownCheckParam(const vdec_vcount_down_t * const p_vcount_down);
+static vdec_error_t AgcPgaCheckParam(const vdec_agc_t * const p_agc);
+static vdec_error_t PeakLimiterControlCheckParam(const vdec_peak_limiter_t * const p_peak_limiter);
+static vdec_error_t OverRangeControlCheckParam(const vdec_over_range_t * const p_over_range);
+static vdec_error_t YcSeparationControlCheckParam(const vdec_yc_sep_ctrl_t * const p_yc_sep_ctrl);
+static vdec_error_t FilterTAPsCoefficientCheckParam(const vdec_chrfil_tap_t * const fil2_2d);
+static vdec_error_t ChromaDecodingControlCheckParam(const vdec_chrmdec_ctrl_t * const p_chrmdec_ctrl);
+static vdec_error_t BurstLockCheckParam(const vdec_burst_lock_t * const p_burst_lock);
+static vdec_error_t AccColorKillerCheckParam(const vdec_acc_t * const p_acc);
+
+
+/**************************************************************************//**
+ * @brief Checks on input pin control
+ * @param[in] vinsel : Input pin control
+ * @retval Error code
+ *****************************************************************************/
+vdec_error_t VDEC_InitializeCheckParam (const vdec_adc_vinsel_t vinsel)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+
+ if ((vinsel != VDEC_ADC_VINSEL_VIN1) && (vinsel != VDEC_ADC_VINSEL_VIN2)) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+END:
+ return vdec_error;
+} /* End of function VDEC_InitializeCheckParam() */
+
+/**************************************************************************//**
+ * @brief Checks on active image period parameter
+ * @param[in] param : Active image period parameter
+ * @retval Error code
+ *****************************************************************************/
+vdec_error_t VDEC_ActivePeriodCheckParam (const vdec_active_period_t * const param)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+
+ if (param == NULL) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Left end of input video signal capturing area */
+ if (((uint32_t)param->srcleft & (uint32_t)(~VDEC_CPARA_RANGE_0X000001FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Top end of input video signal capturing area */
+ if (((uint32_t)param->srctop & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Height of input video signal capturing area */
+ if (((uint32_t)param->srcheight & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Width of input video signal capturing area */
+ if (((uint32_t)param->srcwidth & (uint32_t)(~VDEC_CPARA_RANGE_0X000007FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+END:
+ return vdec_error;
+} /* End of function VDEC_ActivePeriodCheckParam() */
+
+/**************************************************************************//**
+ * @brief Checks on sync separation parameter
+ * @param[in] param : Sync separation parameter
+ * @retval Error code
+ *****************************************************************************/
+vdec_error_t VDEC_SyncSeparationCheckParam (const vdec_sync_separation_t * const param)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+
+ if (param == NULL) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Noise reduction LPF */
+ vdec_error = NoiseReductionLPFCheckParam(param->noise_rd_lpf);
+ if (vdec_error != VDEC_OK) {
+ goto END;
+ }
+ /* Sync slicer */
+ vdec_error = SyncSlicerCheckParam(param->sync_slicer);
+ if (vdec_error != VDEC_OK) {
+ goto END;
+ }
+ /* Horizontal AFC */
+ vdec_error = HorizontalAFCCheckParam(param->horizontal_afc);
+ if (vdec_error != VDEC_OK) {
+ goto END;
+ }
+ /* Vertical countdown */
+ vdec_error = VerticalCountdownCheckParam(param->vcount_down);
+ if (vdec_error != VDEC_OK) {
+ goto END;
+ }
+ /* AGC / PGA */
+ vdec_error = AgcPgaCheckParam(param->agc);
+ if (vdec_error != VDEC_OK) {
+ goto END;
+ }
+ /* Peak limiter control */
+ vdec_error = PeakLimiterControlCheckParam(param->peak_limiter);
+ if (vdec_error != VDEC_OK) {
+ goto END;
+ }
+END:
+ return vdec_error;
+} /* End of function VDEC_SyncSeparationCheckParam() */
+
+/**************************************************************************//**
+ * @brief Checks on Y/C separation parameter
+ * @param[in] param : Y/C separation parameter
+ * @retval Error code
+ *****************************************************************************/
+vdec_error_t VDEC_YcSeparationCheckParam (const vdec_yc_separation_t * const param)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+
+ if (param == NULL) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Over-range control */
+ vdec_error = OverRangeControlCheckParam(param->over_range);
+ if (vdec_error != VDEC_OK) {
+ goto END;
+ }
+ /* Y/C separation control */
+ vdec_error = YcSeparationControlCheckParam(param->yc_sep_ctrl);
+ if (vdec_error != VDEC_OK) {
+ goto END;
+ }
+ /* Two-dimensional cascade broadband (3.58/4.43/SECAM-DR)/TAKE-OFF filter TAP coefficient */
+ vdec_error = FilterTAPsCoefficientCheckParam(param->fil2_2d_wa);
+ if (vdec_error != VDEC_OK) {
+ goto END;
+ }
+ /* Two-dimensional cascade broadband (SECAM-DB) filter TAP coefficient */
+ vdec_error = FilterTAPsCoefficientCheckParam(param->fil2_2d_wb);
+ if (vdec_error != VDEC_OK) {
+ goto END;
+ }
+ /* Two-dimensional cascade narrowband (3.58/4.43/SECAM-DR) filter TAP coefficient */
+ vdec_error = FilterTAPsCoefficientCheckParam(param->fil2_2d_na);
+ if (vdec_error != VDEC_OK) {
+ goto END;
+ }
+ /* Two-dimensional cascade narrowband (SECAMDB) filter TAP coefficient */
+ vdec_error = FilterTAPsCoefficientCheckParam(param->fil2_2d_nb);
+ if (vdec_error != VDEC_OK) {
+ goto END;
+ }
+END:
+ return vdec_error;
+} /* End of function VDEC_YcSeparationCheckParam() */
+
+/**************************************************************************//**
+ * @brief Checks on chroma decoding parameter
+ * @param[in] param : Chroma decoding parameter
+ * @retval Error code
+ *****************************************************************************/
+vdec_error_t VDEC_ChromaDecodingCheckParam (const vdec_chroma_decoding_t * const param)
+{
+ vdec_tint_ry_t * p_tint_ry;
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+
+ if (param == NULL) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Chroma decoding control */
+ vdec_error = ChromaDecodingControlCheckParam(param->chrmdec_ctrl);
+ if (vdec_error != VDEC_OK) {
+ goto END;
+ }
+ /* Burst lock */
+ vdec_error = BurstLockCheckParam(param->burst_lock);
+ if (vdec_error != VDEC_OK) {
+ goto END;
+ }
+ /* ACC/color killer */
+ vdec_error = AccColorKillerCheckParam(param->acc);
+ if (vdec_error != VDEC_OK) {
+ goto END;
+ }
+ /* TINT/R-Y axis correction (only valid for NTSC/PAL) */
+ p_tint_ry = param->tint_ry;
+ if (p_tint_ry != NULL) {
+ /* Fine adjustment of R-Y demodulation axis and hue adjustment level */
+ if ((((uint32_t)p_tint_ry->tintsub & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) ||
+ (((uint32_t)p_tint_ry->tintmain & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u)) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ }
+END:
+ return vdec_error;
+} /* End of function VDEC_ChromaDecodingCheckParam() */
+
+/**************************************************************************//**
+ * @brief Checks on digital clamp parameter
+ * @param[in] param : Digital clamp parameter
+ * @retval Error code
+ *****************************************************************************/
+vdec_error_t VDEC_DigitalClampCheckParam (const vdec_degital_clamp_t * const param)
+{
+ vdec_pedestal_clamp_t * p_pedestal_clamp;
+ vdec_center_clamp_t * p_center_clamp;
+ vdec_noise_det_t * p_noise_det;
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+
+ if (param == NULL) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Digital clamp response speed */
+ if (((uint32_t)param->dcpresponse & (uint32_t)(~VDEC_CPARA_RANGE_0X00000007)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Digital clamp start line (in 1-line units) */
+ if (((uint32_t)param->dcpstart & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Digital clamp end line (in 1-line units) */
+ if (((uint32_t)param->dcpend & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Digital clamp pulse width */
+ if (((uint32_t)param->dcpwidth & (uint32_t)(~VDEC_CPARA_RANGE_0X0000007F)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+
+ /* Pedestal clamp */
+ p_pedestal_clamp = param->pedestal_clamp;
+ if (p_pedestal_clamp != NULL) {
+ /* Clamp offset level (Y signal) */
+ if (((uint32_t)p_pedestal_clamp->blanklevel_y & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Digital clamp pulse horizontal start position (Y signal) */
+ if (((uint32_t)p_pedestal_clamp->dcppos_y & (uint32_t)(~VDEC_CPARA_RANGE_0X000000FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ }
+ /* Center clamp */
+ p_center_clamp = param->center_clamp;
+ if (p_center_clamp != NULL) {
+ /* Clamp offset level (Cb signal) */
+ if (((uint32_t)p_center_clamp->blanklevel_cb & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Clamp offset level (Cr signal) */
+ if (((uint32_t)p_center_clamp->blanklevel_cr & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Digital clamp pulse horizontal start position (Cb/Cr signal) */
+ if (((uint32_t)p_center_clamp->dcppos_c & (uint32_t)(~VDEC_CPARA_RANGE_0X000000FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ }
+ /* Noise detection */
+ p_noise_det = param->noise_det;
+ if (p_noise_det != NULL) {
+ /* Video signal for autocorrelation function */
+ if (p_noise_det->acfinput >= VDEC_ACFINPUT_NUM) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Delay time for autocorrelation function calculation */
+ if (((uint32_t)p_noise_det->acflagtime & (uint32_t)(~VDEC_CPARA_RANGE_0X0000001F)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Smoothing parameter of autocorrelation function data */
+ if (((uint32_t)p_noise_det->acffilter & (uint32_t)(~VDEC_CPARA_RANGE_0X00000003)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ }
+END:
+ return vdec_error;
+} /* End of function VDEC_DigitalClampCheckParam() */
+
+/**************************************************************************//**
+ * @brief Checks on output adjustment parameter
+ * @param[in] param : Output adjustment parameter
+ * @retval Error code
+ *****************************************************************************/
+vdec_error_t VDEC_OutputCheckParam (const vdec_output_t * const param)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+
+ if (param == NULL) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Y signal gain coefficient */
+ if (((uint32_t)param->y_gain2 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Cb signal gain coefficient */
+ if (((uint32_t)param->cb_gain2 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Cr signal gain coefficient */
+ if (((uint32_t)param->cr_gain2 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+END:
+ return vdec_error;
+} /* End of function VDEC_OutputCheckParam() */
+
+/**************************************************************************//**
+ * @brief Checks on noise reduction LPF parameter
+ * @param[in] p_noise_rd_lpf : Noise reduction LPF parameter
+ * @retval Error code
+ *****************************************************************************/
+static vdec_error_t NoiseReductionLPFCheckParam (const vdec_noise_rd_lpf_t * const p_noise_rd_lpf)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+
+ /* Noise reduction LPF */
+ if (p_noise_rd_lpf != NULL) {
+ /* LPF cutoff frequency before vertical sync separation */
+ if (p_noise_rd_lpf->lpfvsync >= VDEC_LPF_VSYNC_NUM) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* LPF cutoff frequency before horizontal sync separation */
+ if (p_noise_rd_lpf->lpfhsync >= VDEC_LPF_HSYNC_NUM) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ }
+END:
+ return vdec_error;
+} /* End of function NoiseReductionLPFCheckParam() */
+
+/**************************************************************************//**
+ * @brief Checks on auto level control sync slicer parameter
+ * @param[in] p_sync_slicer : Auto level control sync slicer parameter
+ * @retval Error code
+ *****************************************************************************/
+static vdec_error_t SyncSlicerCheckParam (const vdec_sync_slicer_t * const p_sync_slicer)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+
+ /* Sync slicer */
+ if (p_sync_slicer != NULL) {
+ /* Reference level operation speed control for composite sync separation (for Hsync signal) */
+ if (p_sync_slicer->velocityshift_h >= VDEC_VELOCITY_SHIFT_NUM) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Auto-slice level setting for composite sync separator circuit (for Hsync signal) */
+ if (p_sync_slicer->slicermode_h >= VDEC_SLICE_MODE_NUM) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Auto-slice level setting for composite sync separation circuit (for Vsync signal) */
+ if (p_sync_slicer->slicermode_v >= VDEC_SLICE_MODE_NUM) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Max ratio of horizontal cycle to horizontal sync signal pulse width
+ and min ratio of horizontal cycle to horizontal sync signal pulse width (for Hsync signal) */
+ if ((((uint32_t)p_sync_slicer->syncmaxduty_h & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) ||
+ (((uint32_t)p_sync_slicer->syncminduty_h & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u)) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Clipping level */
+ if (p_sync_slicer->ssclipsel >= VDEC_CLIP_LV_NUM) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Slice level for composite sync signal separation (for Hsync signal) */
+ if (((uint32_t)p_sync_slicer->csyncslice_h & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Max ratio of horizontal cycle to horizontal sync signal pulse width
+ and min ratio of horizontal cycle to horizontal sync signal pulse width (for Vsync signal) */
+ if ((((uint32_t)p_sync_slicer->syncmaxduty_v & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) ||
+ (((uint32_t)p_sync_slicer->syncminduty_v & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u)) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Threshold for vertical sync separation */
+ if (((uint32_t)p_sync_slicer->vsyncslice & (uint32_t)(~VDEC_CPARA_RANGE_0X0000001F)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Slice level for composite sync signal separation (for Vsync signal) */
+ if (((uint32_t)p_sync_slicer->csyncslice_v & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ }
+END:
+ return vdec_error;
+} /* End of function SyncSlicerCheckParam() */
+
+/**************************************************************************//**
+ * @brief Checks on horizontal AFC parameter
+ * @param[in] p_horizontal_afc : Horizontal AFC parameter
+ * @retval Error code
+ *****************************************************************************/
+static vdec_error_t HorizontalAFCCheckParam (const vdec_horizontal_afc_t * const p_horizontal_afc)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+
+ /* Horizontal AFC */
+ if (p_horizontal_afc != NULL) {
+ /* Horizontal AFC loop gain */
+ if (((uint32_t)p_horizontal_afc->hafcgain & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Horizontal AFC center oscillation frequency */
+ if (((uint32_t)p_horizontal_afc->hafcgain & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Start line of horizontal AFC normal operation */
+ if (((uint32_t)p_horizontal_afc->hafcstart & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Maximum oscillation frequency of horizontal AFC */
+ if (((uint32_t)p_horizontal_afc->hafcmax & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* End line of horizontal AFC normal operation */
+ if (((uint32_t)p_horizontal_afc->hafcend & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Horizontal AFC VBI period operating mode */
+ if (p_horizontal_afc->hafcmode >= VDEC_HAFCMD_NUM) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Min oscillation frequency of horizontal AFC */
+ if (((uint32_t)p_horizontal_afc->hafcmin & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Phase comparator feedback adjust for low sync signal lock stability */
+ if (p_horizontal_afc->phdet_div >= VDEC_PHDET_DIV_NUM) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ }
+END:
+ return vdec_error;
+} /* End of function HorizontalAFCCheckParam() */
+
+/**************************************************************************//**
+ * @brief Checks on vertical count-down parameter
+ * @param[in] p_vcount_down : Vertical count-down parameter
+ * @retval Error code
+ *****************************************************************************/
+static vdec_error_t VerticalCountdownCheckParam (const vdec_vcount_down_t * const p_vcount_down)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+
+ /* Vertical countdown */
+ if (p_vcount_down != NULL) {
+ /* Vertical countdown center oscillation frequency */
+ if (p_vcount_down->vcddefault >= VDEC_VCD_FRQ_NUM) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Vertical countdown sync area */
+ if (((uint32_t)p_vcount_down->vcdwindow & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Vertical countdown minimum oscillation frequency */
+ if (((uint32_t)p_vcount_down->vcdoffset & (uint32_t)(~VDEC_CPARA_RANGE_0X0000001F)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ }
+END:
+ return vdec_error;
+} /* End of function VerticalCountdownCheckParam() */
+
+/**************************************************************************//**
+ * @brief Checks on AGC/PGA parameter
+ * @param[in] p_agc : AGC/PGA parameter
+ * @retval Error code
+ *****************************************************************************/
+static vdec_error_t AgcPgaCheckParam (const vdec_agc_t * const p_agc)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+
+ /* AGC / PGA */
+ if (p_agc != NULL) {
+ /* AGC response speed */
+ if (((uint32_t)p_agc->agcresponse & (uint32_t)(~VDEC_CPARA_RANGE_0X00000007)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Sync signal reference amplitude */
+ if (((uint32_t)p_agc->agclevel & (uint32_t)(~VDEC_CPARA_RANGE_0X000001FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* AGC gain adjustment accuracy */
+ if (((uint32_t)p_agc->agcprecis & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* PGA gain */
+ if (((uint32_t)p_agc->pga_gain & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ }
+END:
+ return vdec_error;
+} /* End of function AgcPgaCheckParam() */
+
+/**************************************************************************//**
+ * @brief Checks on peak limiter control parameter
+ * @param[in] p_peak_limiter : Peak limiter control parameter
+ * @retval Error code
+ *****************************************************************************/
+static vdec_error_t PeakLimiterControlCheckParam (const vdec_peak_limiter_t * const p_peak_limiter)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+
+ /* Peak limiter control */
+ if (p_peak_limiter != NULL) {
+ /* Peak luminance value to operate peak limiter */
+ if (p_peak_limiter->peaklevel >= VDEC_PEAKLV_NUM) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+
+ /* Response speed with peak limiter gain decreased */
+ if (((uint32_t)p_peak_limiter->peakattack & (uint32_t)(~VDEC_CPARA_RANGE_0X00000003)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Response speed with peak limiter gain increased */
+ if (((uint32_t)p_peak_limiter->peakrelease & (uint32_t)(~VDEC_CPARA_RANGE_0X00000003)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Maximum compression rate of peak limiter */
+ if (p_peak_limiter->peakratio >= VDEC_PEAKRATIO_NUM) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Allowable number of overflowing pixels */
+ if (((uint32_t)p_peak_limiter->maxpeaksamples & (uint32_t)(~VDEC_CPARA_RANGE_0X000000FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ }
+END:
+ return vdec_error;
+} /* End of function PeakLimiterControlCheckParam() */
+
+/**************************************************************************//**
+ * @brief Checks on over-range control parameter
+ * @param[in] p_over_range : Over-range control parameter
+ * @retval Error code
+ *****************************************************************************/
+static vdec_error_t OverRangeControlCheckParam (const vdec_over_range_t * const p_over_range)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+
+ /* Over-range control */
+ if (p_over_range != NULL) {
+ /* A/D over-threshold level (between levels 0 and 1) */
+ if (((uint32_t)p_over_range->radj_o_level0 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* A/D under-threshold level (between levels 2 and 3) */
+ if (((uint32_t)p_over_range->radj_u_level0 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* A/D over-threshold level (between levels 1 and 2) */
+ if (((uint32_t)p_over_range->radj_o_level1 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* A/D under-threshold level (between levels 1 and 2) */
+ if (((uint32_t)p_over_range->radj_u_level1 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* A/D over-threshold level (between levels 2 and 3) */
+ if (((uint32_t)p_over_range->radj_o_level2 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* A/D under-threshold level (between levels 0 and 1) */
+ if (((uint32_t)p_over_range->radj_u_level2 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ }
+END:
+ return vdec_error;
+} /* End of function OverRangeControlCheckParam() */
+
+/**************************************************************************//**
+ * @brief Checks on Y/C separation control parameter
+ * @param[in] p_yc_sep_ctrl : Y/C separation control parameter
+ * @retval Error code
+ *****************************************************************************/
+static vdec_error_t YcSeparationControlCheckParam (const vdec_yc_sep_ctrl_t * const p_yc_sep_ctrl)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+
+ /* Y/C separation control */
+ if (p_yc_sep_ctrl != NULL) {
+ /* Two-dimensional Y/C separation filter select coefficient (K15, K13, and K11) */
+ if ((((uint32_t)p_yc_sep_ctrl->k15 & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) ||
+ (((uint32_t)p_yc_sep_ctrl->k13 & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) ||
+ (((uint32_t)p_yc_sep_ctrl->k11 & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u)) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Two-dimensional Y/C separation filter select coefficient (K16, K14, and K12) */
+ if ((((uint32_t)p_yc_sep_ctrl->k16 & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) ||
+ (((uint32_t)p_yc_sep_ctrl->k14 & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) ||
+ (((uint32_t)p_yc_sep_ctrl->k12 & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u)) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Two-dimensional Y/C separation filter select coefficient (K22A and K21A) */
+ if ((((uint32_t)p_yc_sep_ctrl->k22a & (uint32_t)(~VDEC_CPARA_RANGE_0X000000FF)) != 0u) ||
+ (((uint32_t)p_yc_sep_ctrl->k21a & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u)) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Two-dimensional Y/C separation filter select coefficient (K22B and K21B) */
+ if ((((uint32_t)p_yc_sep_ctrl->k22b & (uint32_t)(~VDEC_CPARA_RANGE_0X000000FF)) != 0u) ||
+ (((uint32_t)p_yc_sep_ctrl->k21b & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u)) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Two-dimensional Y/C separation filter select coefficient (K23B, K23A, and K24) */
+ if ((((uint32_t)p_yc_sep_ctrl->k23b & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) ||
+ (((uint32_t)p_yc_sep_ctrl->k23a & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) ||
+ (((uint32_t)p_yc_sep_ctrl->k24 & (uint32_t)(~VDEC_CPARA_RANGE_0X0000001F)) != 0u)) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Mixing ratio of signal after passing horizontal filter
+ to signal after passing former-stage horizontal filter */
+ if (p_yc_sep_ctrl->hsel_mix_y >= VDEC_FILMIX_RATIO_NUM) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Mixing ratio of signal after passing vertical filter
+ to signal after passing former-stage horizontal/vertical filter */
+ if (p_yc_sep_ctrl->vsel_mix_y >= VDEC_FILMIX_RATIO_NUM) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Mixing ratio of signal after passing horizontal/vertical filter
+ to signal after passing former-stage horizontal/vertical filter */
+ if (p_yc_sep_ctrl->hvsel_mix_y >= VDEC_FILMIX_RATIO_NUM) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Vertical luminance detection level for correlation detection filter */
+ if (((uint32_t)p_yc_sep_ctrl->v_y_level & (uint32_t)(~VDEC_CPARA_RANGE_0X000001FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+
+ /* Mixing ratio of c signal after passing horizontal/vertical adaptive filter
+ to signal after passing correlation detection filter */
+ if (p_yc_sep_ctrl->det2_mix_c >= VDEC_FILMIX_RATIO_NUM) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Mixing ratio of C signal for Y generation after passing
+ horizontal/vertical adaptive filter to signal after passing correlation */
+ if (p_yc_sep_ctrl->det2_mix_y >= VDEC_FILMIX_RATIO_NUM) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Two-dimensional cascade/TAKE-OFF filter mode select */
+ if (p_yc_sep_ctrl->fil2_mode_2d >= VDEC_2DFIL_MDSEL_NUM) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ }
+END:
+ return vdec_error;
+} /* End of function YcSeparationControlCheckParam() */
+
+/**************************************************************************//**
+ * @brief Checks on chroma filter TAP coefficient for Y/C separation
+ * @param[in] fil2_2d : Chroma filter TAP coefficient for Y/C separation
+ * @retval Error code
+ *****************************************************************************/
+static vdec_error_t FilterTAPsCoefficientCheckParam (const vdec_chrfil_tap_t * const fil2_2d)
+{
+ int32_t tap_coef;
+ const uint16_t * taps;
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+
+ if (fil2_2d != NULL) {
+ taps = fil2_2d->fil2_2d_f;
+ for (tap_coef = 0; tap_coef < VDEC_CHRFIL_TAPCOEF_NUM; tap_coef++) {
+ if (((uint32_t)*taps & (uint32_t)(~VDEC_CPARA_RANGE_0X00001FFF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ taps++;
+ }
+ }
+END:
+ return vdec_error;
+} /* End of function FilterTAPsCoefficientCheckParam() */
+
+/**************************************************************************//**
+ * @brief Checks on color system detection parameter
+ * @param[in] p_chrmdec_ctrl : Color system detection parameter
+ * @retval Error code
+ *****************************************************************************/
+static vdec_error_t ChromaDecodingControlCheckParam (const vdec_chrmdec_ctrl_t * const p_chrmdec_ctrl)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+
+ /* Chroma decoding control */
+ if (p_chrmdec_ctrl != NULL) {
+ /* Default color system */
+ if (p_chrmdec_ctrl->defaultsys >= VDEC_COL_SYS_NUM) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Luminance signal delay adjustment */
+ if (((uint32_t)p_chrmdec_ctrl->lumadelay & (uint32_t)(~VDEC_CPARA_RANGE_0X0000001F)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Averaging processing for pre-demodulated line */
+ if ((p_chrmdec_ctrl->demodmode != VDEC_DEMOD_MD_NO) && (p_chrmdec_ctrl->demodmode != VDEC_DEMOD_MD_PAL)) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ }
+END:
+ return vdec_error;
+} /* End of function ChromaDecodingControlCheckParam() */
+
+/**************************************************************************//**
+ * @brief Checks on BCO parameter
+ * @param[in] p_burst_lock : BCO parameter
+ * @retval Error code
+ *****************************************************************************/
+static vdec_error_t BurstLockCheckParam (const vdec_burst_lock_t * const p_burst_lock)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+
+ /* Burst lock */
+ if (p_burst_lock != NULL) {
+ /* Burst lock PLL lock range */
+ if (p_burst_lock->lockrange >= VDEC_LOCK_RANGE_NUM) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Burst lock PLL loop gain */
+ if (((uint32_t)p_burst_lock->loopgain & (uint32_t)(~VDEC_CPARA_RANGE_0X00000003)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Level for burst lock PLL to re-search free-run frequency */
+ if (((uint32_t)p_burst_lock->locklimit & (uint32_t)(~VDEC_CPARA_RANGE_0X00000003)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* burst gate pulse position check */
+ if (((uint32_t)p_burst_lock->bgpcheck & (uint32_t)(~VDEC_CPARA_RANGE_0X00000001)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* burst gate pulse width */
+ if (((uint32_t)p_burst_lock->bgpwidth & (uint32_t)(~VDEC_CPARA_RANGE_0X0000007F)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* burst gate pulse start position */
+ if (((uint32_t)p_burst_lock->bgpstart & (uint32_t)(~VDEC_CPARA_RANGE_0X000000FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ }
+END:
+ return vdec_error;
+} /* End of function BurstLockCheckParam() */
+
+/**************************************************************************//**
+ * @brief Checks on ACC and color killer parameter
+ * @param[in] p_acc : ACC and color killer parameter
+ * @retval Error code
+ *****************************************************************************/
+static vdec_error_t AccColorKillerCheckParam (const vdec_acc_t * const p_acc)
+{
+ vdec_error_t vdec_error;
+
+ vdec_error = VDEC_OK;
+
+ /* ACC/color killer */
+ if (p_acc != NULL) {
+ /* Maximum ACC Gain */
+ if (p_acc->accmaxgain >= VDEC_ACC_MAX_GAIN_NUM) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* ACC reference color burst amplitude */
+ if (((uint32_t)p_acc->acclevel & (uint32_t)(~VDEC_CPARA_RANGE_0X000001FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Chroma manual gain (sub) */
+ if (p_acc->chromasubgain >= VDEC_CHRM_SB_GAIN_NUM) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Chroma manual gain (main) */
+ if (((uint32_t)p_acc->chromamaingain & (uint32_t)(~VDEC_CPARA_RANGE_0X000001FF)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* ACC response speed */
+ if (((uint32_t)p_acc->accresponse & (uint32_t)(~VDEC_CPARA_RANGE_0X00000003)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* ACC gain adjustment accuracy */
+ if (((uint32_t)p_acc->accprecis & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* Color killer operation start point */
+ if (((uint32_t)p_acc->killerlevel & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ /* The offset level to turn off the color killer */
+ if (((uint32_t)p_acc->killeroffset & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) {
+ vdec_error = VDEC_ERR_PARAM;
+ goto END;
+ }
+ }
+END:
+ return vdec_error;
+} /* End of function AccColorKillerCheckParam() */
+
+#endif /* R_VDEC_CHECK_PARAMETERS */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/drivers/vdec/src/r_vdec_check_parameter.h Fri Jun 26 02:17:53 2015 +0000 @@ -0,0 +1,66 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/**************************************************************************//** +* @file r_vdec_check_parameter.h +* @version 1.00 +* $Rev: 199 $ +* $Date:: 2014-05-23 16:33:52 +0900#$ +* @brief VDEC driver parameter check definitions +******************************************************************************/ + +#ifndef R_VDEC_CHECK_PARAMETER_H +#define R_VDEC_CHECK_PARAMETER_H + +/****************************************************************************** +Includes <System Includes> , "Project Includes" +******************************************************************************/ +#include "r_vdec.h" +#include "r_vdec_user.h" + + +#ifdef R_VDEC_CHECK_PARAMETERS +/****************************************************************************** +Macro definitions +******************************************************************************/ + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Variable Externs +******************************************************************************/ + +/****************************************************************************** +Functions Prototypes +******************************************************************************/ +vdec_error_t VDEC_InitializeCheckParam(const vdec_adc_vinsel_t vinsel); +vdec_error_t VDEC_ActivePeriodCheckParam(const vdec_active_period_t * const param); +vdec_error_t VDEC_SyncSeparationCheckParam(const vdec_sync_separation_t * const param); +vdec_error_t VDEC_YcSeparationCheckParam(const vdec_yc_separation_t * const param); +vdec_error_t VDEC_ChromaDecodingCheckParam(const vdec_chroma_decoding_t * const param); +vdec_error_t VDEC_DigitalClampCheckParam(const vdec_degital_clamp_t * const param); +vdec_error_t VDEC_OutputCheckParam(const vdec_output_t * const param); +#endif /* R_VDEC_CHECK_PARAMETERS */ + +#endif /* R_VDEC_CHECK_PARAMETER_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/vdec/src/r_vdec_register.c Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,977 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file r_vdec_register.c
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief VDEC driver register setup processing
+******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_vdec.h"
+#include "r_vdec_user.h"
+#include "r_vdec_register.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* shift value */
+#define VEDC_REG_SHIFT_15 (15u)
+#define VEDC_REG_SHIFT_14 (14u)
+#define VEDC_REG_SHIFT_13 (13u)
+#define VEDC_REG_SHIFT_12 (12u)
+#define VEDC_REG_SHIFT_11 (11u)
+#define VEDC_REG_SHIFT_10 (10u)
+#define VEDC_REG_SHIFT_9 (9u)
+#define VEDC_REG_SHIFT_8 (8u)
+#define VEDC_REG_SHIFT_6 (6u)
+#define VEDC_REG_SHIFT_5 (5u)
+#define VEDC_REG_SHIFT_4 (4u)
+#define VEDC_REG_SHIFT_2 (2u)
+#define VEDC_REG_SHIFT_1 (1u)
+
+/* bit set pattern */
+#define VDEC_REG_SET_0X8000 (0x8000u)
+#define VDEC_REG_SET_0X4000 (0x4000u)
+#define VDEC_REG_SET_0X2000 (0x2000u)
+#define VDEC_REG_SET_0X1000 (0x1000u)
+#define VDEC_REG_SET_0X0800 (0x0800u)
+#define VDEC_REG_SET_0X0100 (0x0100u)
+#define VDEC_REG_SET_0X0080 (0x0080u)
+#define VDEC_REG_SET_0X0020 (0x0020u)
+#define VDEC_REG_SET_0X0010 (0x0010u)
+#define VDEC_REG_SET_0X0008 (0x0008u)
+#define VDEC_REG_SET_0X0004 (0x0004u)
+#define VDEC_REG_SET_0X0002 (0x0002u)
+#define VDEC_REG_SET_0X0001 (0x0001u)
+
+/* bit mask pattern */
+#define VDEC_REG_BIT_MASK_0X8000 (0x8000u)
+#define VDEC_REG_BIT_MASK_0X4000 (0x4000u)
+#define VDEC_REG_BIT_MASK_0X2000 (0x2000u)
+#define VDEC_REG_BIT_MASK_0X1000 (0x1000u)
+#define VDEC_REG_BIT_MASK_0X0800 (0x0800u)
+#define VDEC_REG_BIT_MASK_0X0400 (0x0400u)
+#define VDEC_REG_BIT_MASK_0X0200 (0x0200u)
+#define VDEC_REG_BIT_MASK_0X0100 (0x0100u)
+
+/* register mask value */
+#define VDEC_REG_MASK_0X03FF (0x03FFu) /* mask vdec_reg->syncssr */
+#define VDEC_REG_MASK_0XFF1F (0xFF1Fu) /* mask vdec_reg->ycscr7 */
+#define VDEC_REG_MASK_0XF3FF (0xF3FFu) /* mask vdec_reg->hafccr1 */
+#define VDEC_REG_MASK_0X83FF (0x83FFu) /* mask vdec_reg->dcpcr1 */
+#define VDEC_REG_MASK_0X01FF (0x01FFu) /* mask vdec_reg->ycscr11 */
+#define VDEC_REG_MASK_0X1C00 (0x1C00u) /* mask vdec_reg->dcpcr9 */
+#define VDEC_REG_MASK_0X1F00 (0x1F00u) /* mask vdec_reg->pgacr */
+#define VDEC_REG_MASK_0X3F00 (0x3F00u) /* mask vdec_reg->agccr2 */
+#define VDEC_REG_MASK_0X0007 (0x0007u) /* mask vdec_reg->rgorcr7 */
+#define VDEC_REG_MASK_0XF800 (0xF800u) /* mask vdec_reg->ycscr8 */
+#define VDEC_REG_MASK_0XFC00 (0xFC00u) /* mask vdec_reg->synscr1 */
+#define VDEC_REG_MASK_0X00FF (0x00FFu) /* mask vdec_reg->synscr1 */
+#define VDEC_REG_MASK_0X0003 (0x0003u) /* mask vdec_reg->cromasr1 */
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void NoiseReductionLPF(
+ const vdec_reg_address_t * const vdec_reg,
+ const vdec_noise_rd_lpf_t * const p_noise_rd_lpf);
+static void SyncSlicer(const vdec_reg_address_t * const vdec_reg, const vdec_sync_slicer_t * const p_sync_slicer);
+static void HorizontalAFC(
+ const vdec_reg_address_t * const vdec_reg,
+ const vdec_horizontal_afc_t * const p_horizontal_afc);
+static void VerticalCountdown(
+ const vdec_reg_address_t * const vdec_reg,
+ const vdec_vcount_down_t * const p_vcount_down);
+static void AgcPga(const vdec_reg_address_t * const vdec_reg, const vdec_agc_t * const p_agc);
+static void PeakLimiterControl(
+ const vdec_reg_address_t * const vdec_reg,
+ const vdec_peak_limiter_t * const p_peak_limiter);
+static void OverRangeControl(const vdec_reg_address_t * const vdec_reg, const vdec_over_range_t * const p_over_range);
+static void YcSeparationControl(
+ const vdec_reg_address_t * const vdec_reg,
+ const vdec_yc_sep_ctrl_t * const p_yc_sep_ctrl);
+static void FilterTAPsCoefficient(
+ volatile uint16_t * const * fil_reg_address,
+ const vdec_chrfil_tap_t * const fil2_2d);
+
+
+/**************************************************************************//**
+ * @brief Sets registers for initialization
+ * @param[in] ch : Channel
+ * @param[in] vinsel : Input pin control
+ * @retval None
+ *****************************************************************************/
+void VDEC_Initialize (const vdec_channel_t ch, const vdec_adc_vinsel_t vinsel)
+{
+ const vdec_reg_address_t * vdec_reg;
+ uint16_t reg_data;
+
+ vdec_reg = &vdec_reg_address[ch];
+
+ /* Input pin control */
+ if (vinsel == VDEC_ADC_VINSEL_VIN1) {
+ reg_data = (uint16_t)((uint32_t)*(vdec_reg->adccr2) & (~0x0001u));
+ *(vdec_reg->adccr2) = reg_data;
+ } else {
+ reg_data = (uint16_t)((uint32_t)*(vdec_reg->adccr2) | (0x0001u));
+ *(vdec_reg->adccr2) = reg_data;
+ }
+ return;
+} /* End of function VDEC_Initialize() */
+
+/**************************************************************************//**
+ * @brief Sets registers for active image period
+ * @param[in] ch : Channel
+ * @param[in] param : Active image period parameter
+ * @retval None
+ *****************************************************************************/
+void VDEC_ActivePeriod (const vdec_channel_t ch, const vdec_active_period_t * const param)
+{
+ const vdec_reg_address_t * vdec_reg;
+
+ vdec_reg = &vdec_reg_address[ch];
+
+ /* Left end of input video signal capturing area */
+ *(vdec_reg->tgcr1) = param->srcleft;
+ /* Top end of input video signal capturing area
+ and height of input video signal capturing area */
+ *(vdec_reg->tgcr2) = (uint16_t)(((uint32_t)param->srctop << VEDC_REG_SHIFT_10) | (uint32_t)param->srcheight);
+ /* Width of input video signal capturing area */
+ *(vdec_reg->tgcr3) = param->srcwidth;
+
+ return;
+} /* End of function VDEC_ActivePeriod() */
+
+/**************************************************************************//**
+ * @brief Sets registers for sync separation
+ * @param[in] ch : Channel
+ * @param[in] param : Sync separation parameter
+ * @retval None
+ *****************************************************************************/
+void VDEC_SyncSeparation (const vdec_channel_t ch, const vdec_sync_separation_t * const param)
+{
+ const vdec_reg_address_t * vdec_reg;
+
+ vdec_reg = &vdec_reg_address[ch];
+
+ /* Noise reduction LPF */
+ NoiseReductionLPF(vdec_reg, param->noise_rd_lpf);
+ /* Auto level control sync slicer */
+ SyncSlicer(vdec_reg, param->sync_slicer);
+ /* Horizontal AFC */
+ HorizontalAFC(vdec_reg, param->horizontal_afc);
+ /* Vertical count-down */
+ VerticalCountdown(vdec_reg, param->vcount_down);
+ /* AGC/PGA */
+ AgcPga(vdec_reg, param->agc);
+ /* Peak limiter control */
+ PeakLimiterControl(vdec_reg, param->peak_limiter);
+
+ return;
+} /* End of function VDEC_SyncSeparation() */
+
+/**************************************************************************//**
+ * @brief Sets registers for Y/C separation
+ * @param[in] ch : Channel
+ * @param[in] param : Y/C separation parameter
+ * @retval None
+ *****************************************************************************/
+void VDEC_YcSeparation (const vdec_channel_t ch, const vdec_yc_separation_t * const param)
+{
+ const vdec_reg_address_t * vdec_reg;
+
+ vdec_reg = &vdec_reg_address[ch];
+
+ /* Over-range control */
+ OverRangeControl(vdec_reg, param->over_range);
+ /* Y/C separation control */
+ YcSeparationControl(vdec_reg, param->yc_sep_ctrl);
+
+ /* Two-dimensional cascade broadband (3.58/4.43/SECAM-DR)/TAKE-OFF filter TAP coefficient */
+ FilterTAPsCoefficient(vdec_filter_reg_address[ch].yctwa_f, param->fil2_2d_wa);
+ /* Two-dimensional cascade broadband (SECAM-DB) filter TAP coefficient */
+ FilterTAPsCoefficient(vdec_filter_reg_address[ch].yctwb_f, param->fil2_2d_wb);
+ /* Two-dimensional cascade narrowband (3.58/4.43/SECAM-DR) filter TAP coefficient */
+ FilterTAPsCoefficient(vdec_filter_reg_address[ch].yctna_f, param->fil2_2d_na);
+ /* Two-dimensional cascade narrowband (SECAMDB) filter TAP coefficient */
+ FilterTAPsCoefficient(vdec_filter_reg_address[ch].yctnb_f, param->fil2_2d_nb);
+
+ return;
+} /* End of function VDEC_YcSeparation() */
+
+/**************************************************************************//**
+ * @brief Sets registers for chroma decoding
+ * @param[in] ch : Channel
+ * @param[in] param : Chroma decoding parameter
+ * @retval None
+ *****************************************************************************/
+void VDEC_ChromaDecoding (const vdec_channel_t ch, const vdec_chroma_decoding_t * const param)
+{
+ const vdec_reg_address_t * vdec_reg;
+ vdec_chrmdec_ctrl_t * p_chrmdec_ctrl;
+ vdec_burst_lock_t * p_burst_lock;
+ vdec_acc_t * p_acc;
+ vdec_tint_ry_t * p_tint_ry;
+ uint32_t reg_data;
+
+ vdec_reg = &vdec_reg_address[ch];
+ p_chrmdec_ctrl = param->chrmdec_ctrl;
+ p_burst_lock = param->burst_lock;
+ p_acc = param->acc;
+ p_tint_ry = param->tint_ry;
+
+ /* Color system detection */
+ if (p_chrmdec_ctrl != NULL) {
+ reg_data = (uint32_t)*(vdec_reg->btlcr) & (uint32_t)(~VDEC_REG_MASK_0X00FF);
+ /* Default color system */
+ reg_data |= (uint32_t)p_chrmdec_ctrl->defaultsys << VEDC_REG_SHIFT_6;
+ /* NTSC-M detection control */
+ reg_data |= (p_chrmdec_ctrl->nontsc358_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0020 : (uint32_t)0x0000u;
+ /* NTSC-4.43 detection control */
+ reg_data |= (p_chrmdec_ctrl->nontsc443_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0010 : (uint32_t)0x0000u;
+ /* PAL-M detection control */
+ reg_data |= (p_chrmdec_ctrl->nopalm_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0008 : (uint32_t)0x0000u;
+ /* PAL-N detection control */
+ reg_data |= (p_chrmdec_ctrl->nopaln_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0004 : (uint32_t)0x0000u;
+ /* PAL-B, G, H, I, D detection control */
+ reg_data |= (p_chrmdec_ctrl->nopal443_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0002 : (uint32_t)0x0000u;
+ /* SECAM detection control */
+ reg_data |= (p_chrmdec_ctrl->nosecam_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0001 : (uint32_t)0x0000u;
+
+ *(vdec_reg->btlcr) = (uint16_t)reg_data;
+
+ /* Luminance signal delay adjustment */
+ reg_data = (uint32_t)p_chrmdec_ctrl->lumadelay << VEDC_REG_SHIFT_4;
+ /* LPF for demodulated chroma */
+ reg_data |= (p_chrmdec_ctrl->chromalpf == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0004;
+ /* Averaging processing for pre-demodulated line */
+ reg_data |= (uint32_t)p_chrmdec_ctrl->demodmode;
+
+ *(vdec_reg->ycdcr) = (uint16_t)reg_data;
+ }
+ /* BCO */
+ if (p_burst_lock != NULL) {
+ reg_data = (uint32_t)*(vdec_reg->btlcr) & (uint32_t)(~VDEC_REG_MASK_0XFC00);
+ /* Burst lock PLL lock range */
+ reg_data |= (uint32_t)p_burst_lock->lockrange << VEDC_REG_SHIFT_14;
+ /* Burst lock PLL loop gain */
+ reg_data |= (uint32_t)p_burst_lock->loopgain << VEDC_REG_SHIFT_12;
+ /* Level for burst lock PLL to re-search free-run frequency */
+ reg_data |= (uint32_t)p_burst_lock->locklimit << VEDC_REG_SHIFT_10;
+
+ *(vdec_reg->btlcr) = (uint16_t)reg_data;
+
+ /* burst gate pulse position check */
+ reg_data = (uint32_t)p_burst_lock->bgpcheck << VEDC_REG_SHIFT_15;
+ /* burst gate pulse width */
+ reg_data |= (uint32_t)p_burst_lock->bgpwidth << VEDC_REG_SHIFT_8;
+ /* burst gate pulse start position */
+ reg_data |= (uint32_t)p_burst_lock->bgpstart;
+
+ *(vdec_reg->btgpcr) = (uint16_t)reg_data;
+ }
+ /* ACC and color killer */
+ if (p_acc != NULL) {
+ /* ACC operating mode */
+ reg_data = (p_acc->accmode == VDEC_ACC_MD_AUTO) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0800;
+ /* Maximum ACC Gain */
+ reg_data |= (uint32_t)p_acc->accmaxgain << VEDC_REG_SHIFT_9;
+ /* ACC reference color burst amplitude */
+ reg_data |= (uint32_t)p_acc->acclevel;
+ /* Color killer offset */
+ reg_data |= (uint32_t)p_acc->killeroffset << VEDC_REG_SHIFT_12;
+
+ *(vdec_reg->acccr1) = (uint16_t)reg_data;
+
+ /* Chroma manual gain (sub) */
+ reg_data = (uint32_t)p_acc->chromasubgain << VEDC_REG_SHIFT_9;
+ /* Chroma manual gain (main) */
+ reg_data |= (uint32_t)p_acc->chromamaingain;
+
+ *(vdec_reg->acccr2) = (uint16_t)reg_data;
+
+ /* ACC response speed */
+ reg_data = (uint32_t)p_acc->accresponse << VEDC_REG_SHIFT_14;
+ /* ACC gain adjustment accuracy */
+ reg_data |= (uint32_t)p_acc->accprecis << VEDC_REG_SHIFT_8;
+ /* Forced color killer mode ON/OFF */
+ reg_data |= (p_acc->killermode == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0080;
+ /* Color killer operation start point */
+ reg_data |= (uint32_t)p_acc->killerlevel << VEDC_REG_SHIFT_1;
+
+ *(vdec_reg->acccr3) = (uint16_t)reg_data;
+ }
+ /* TINT correction/R-Y axis correction (only valid for NTSC/PAL) */
+ if (p_tint_ry != NULL) {
+ /* Fine adjustment of R-Y demodulation axis and hue adjustment level */
+ reg_data = (uint32_t)p_tint_ry->tintsub << VEDC_REG_SHIFT_10;
+ reg_data |= (uint32_t)p_tint_ry->tintmain;
+
+ *(vdec_reg->tintcr) = (uint16_t)reg_data;
+ }
+ return;
+} /* End of function VDEC_ChromaDecoding() */
+
+/**************************************************************************//**
+ * @brief Sets registers for digital clamp
+ * @param[in] ch : Channel
+ * @param[in] param : Digital clamp parameter
+ * @retval None
+ *****************************************************************************/
+void VDEC_DigitalClamp (const vdec_channel_t ch, const vdec_degital_clamp_t * const param)
+{
+ const vdec_reg_address_t * vdec_reg;
+ vdec_pedestal_clamp_t * p_pedestal_clamp;
+ vdec_center_clamp_t * p_center_clamp;
+ vdec_noise_det_t * p_noise_det;
+ uint32_t reg_data;
+
+ vdec_reg = &vdec_reg_address[ch];
+ p_pedestal_clamp = param->pedestal_clamp;
+ p_center_clamp = param->center_clamp;
+ p_noise_det = param->noise_det;
+
+ /* Digital clamp pulse position check */
+ reg_data = (uint32_t)*(vdec_reg->dcpcr1);
+ if (param->dcpcheck == VDEC_OFF) {
+ reg_data &= (uint32_t)(~VDEC_REG_SET_0X0800);
+ } else {
+ reg_data |= (uint32_t)VDEC_REG_SET_0X0800;
+ }
+ *(vdec_reg->dcpcr1) = (uint16_t)reg_data;
+
+ /* Digital clamp response speed */
+ *(vdec_reg->dcpcr3) = (uint16_t)((uint32_t)param->dcpresponse << VEDC_REG_SHIFT_12);
+ /* Digital clamp start line */
+ *(vdec_reg->dcpcr4) = (uint16_t)((uint32_t)param->dcpstart << VEDC_REG_SHIFT_10);
+ /* Digital clamp end line */
+ *(vdec_reg->dcpcr5) = (uint16_t)((uint32_t)param->dcpend << VEDC_REG_SHIFT_10);
+ /* Digital clamp pulse width */
+ *(vdec_reg->dcpcr6) = (uint16_t)((uint32_t)param->dcpwidth << VEDC_REG_SHIFT_8);
+
+ /* Pedestal clamp */
+ if (p_pedestal_clamp != NULL) {
+ reg_data = (uint32_t)*(vdec_reg->dcpcr1) & (uint32_t)(~VDEC_REG_MASK_0X83FF);
+ /* Clamp level setting mode (Y signal) */
+ reg_data |= (p_pedestal_clamp->dcpmode_y == VDEC_DCPMODE_MANUAL) ? (uint32_t)0x0000u :
+ (uint32_t)VDEC_REG_SET_0X8000;
+ /* Clamp offset level (Y signal) */
+ reg_data |= (uint32_t)p_pedestal_clamp->blanklevel_y;
+
+ *(vdec_reg->dcpcr1) = (uint16_t)reg_data;
+
+ /* Digital clamp pulse horizontal start position (Y signal) */
+ *(vdec_reg->dcpcr7) = (uint16_t)((uint32_t)p_pedestal_clamp->dcppos_y << VEDC_REG_SHIFT_8);
+ }
+ /* Center clamp */
+ if (p_center_clamp != NULL) {
+ /* Clamp level setting mode (Cb/Cr signal) */
+ reg_data = (p_center_clamp->dcpmode_c == VDEC_DCPMODE_MANUAL) ? (uint32_t)0x0000u :
+ (uint32_t)VDEC_REG_SET_0X8000;
+ /* Clamp offset level (Cb signal) */
+ reg_data |= (uint32_t)p_center_clamp->blanklevel_cb << VEDC_REG_SHIFT_6;
+ /* Clamp offset level (Cr signal) */
+ reg_data |= (uint32_t)p_center_clamp->blanklevel_cr;
+
+ *(vdec_reg->dcpcr2) = (uint16_t)reg_data;
+
+ /* Digital clamp pulse horizontal start position (Cb/Cr signal) */
+ *(vdec_reg->dcpcr8) = (uint16_t)((uint32_t)p_center_clamp->dcppos_c << VEDC_REG_SHIFT_8);
+ }
+ /* Noise detection */
+ if (p_noise_det != NULL) {
+ /* Video signal for autocorrelation function */
+ reg_data = (uint32_t)p_noise_det->acfinput << VEDC_REG_SHIFT_12;
+ /* Delay time for autocorrelation function calculation */
+ reg_data |= (uint32_t)p_noise_det->acflagtime << VEDC_REG_SHIFT_4;
+ /* Smoothing parameter of autocorrelation function data */
+ reg_data |= (uint32_t)p_noise_det->acffilter;
+
+ *(vdec_reg->nsdcr) = (uint16_t)reg_data;
+ }
+ /* Clamp data hold processing (Y, Cb, Cr) OFF */
+ reg_data = (uint32_t)*(vdec_reg->dcpcr9) & (uint32_t)(~VDEC_REG_MASK_0X1C00);
+ *(vdec_reg->dcpcr9) = (uint16_t)reg_data;
+
+ return;
+} /* End of function VDEC_DigitalClamp() */
+
+/**************************************************************************//**
+ * @brief Sets registers for output adjustment
+ * @param[in] ch : Channel
+ * @param[in] param : Output adjustment parameter
+ * @retval None
+ *****************************************************************************/
+void VDEC_Output (const vdec_channel_t ch, const vdec_output_t * const param)
+{
+ const vdec_reg_address_t * vdec_reg;
+
+ vdec_reg = &vdec_reg_address[ch];
+
+ /* Y, Cb and Cr signal gain coefficient */
+ *(vdec_reg->ygaincr) = param->y_gain2;
+ *(vdec_reg->cbgaincr) = param->cb_gain2;
+ *(vdec_reg->crgaincr) = param->cr_gain2;
+
+ return;
+} /* End of function VDEC_Output() */
+
+/**************************************************************************//**
+ * @brief Query VDEC parameters
+ * @param[in] ch : Channel
+ * @param[out] q_sync_sep : Sync separation parameters
+ * @param[out] q_agc : Agc parameters
+ * @param[out] q_chroma_dec : Chroma decoding parameters
+ * @param[out] q_digital_clamp : Digital clamp parameters
+ * @retval None
+ *****************************************************************************/
+void VDEC_Query (
+ const vdec_channel_t ch,
+ vdec_q_sync_sep_t * const q_sync_sep,
+ vdec_q_agc_t * const q_agc,
+ vdec_q_chroma_dec_t * const q_chroma_dec,
+ vdec_q_digital_clamp_t * const q_digital_clamp)
+{
+ const vdec_reg_address_t * vdec_reg;
+ uint32_t reg_value;
+
+ vdec_reg = &vdec_reg_address[ch];
+
+ /* Sync separation */
+ if (q_sync_sep != NULL) {
+ reg_value = (uint32_t)*(vdec_reg->vsyncsr);
+ /* Horizontal AFC lock detection result */
+ q_sync_sep->fhlock = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X4000) == 0u) ? VDEC_UNLOCK : VDEC_LOCK;
+ /* Detection result of low S/N signal by sync separation */
+ q_sync_sep->isnoisy = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X2000) == 0u) ? VDEC_NO : VDEC_YES;
+ /* Speed detection result */
+ q_sync_sep->fhmode = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X1000) == 0u) ? VDEC_FHMD_NORMAL :
+ VDEC_FHMD_MULTIPLIED;
+ /* No-signal detection result */
+ q_sync_sep->nosignal_ = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0800) == 0u) ? VDEC_YES : VDEC_NO;
+ /* Vertical countdown lock detection result */
+ q_sync_sep->fvlock = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0400) == 0u) ? VDEC_UNLOCK : VDEC_LOCK;
+ /* Vertical countdown oscillation mode */
+ q_sync_sep->fvmode = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0200) == 0u) ? VDEC_FVMD_50HZ :
+ VDEC_FVMD_60HZ;
+ /* Interlace detection result */
+ q_sync_sep->interlaced = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0100) == 0u) ? VDEC_NO : VDEC_YES;
+ /* Vertical cycle measurement result */
+ q_sync_sep->fvcount = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X00FF);
+ /* Horizontal AFC oscillation cycle */
+ q_sync_sep->fhcount = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X8000) == 0u) ? 0x0000u : (uint32_t)0x0001u;
+ q_sync_sep->fhcount |= (uint32_t)*(vdec_reg->hsyncsr) << VEDC_REG_SHIFT_1;
+
+ reg_value = (uint32_t)*(vdec_reg->syncssr);
+ /* Sync amplitude detection result during VBI period */
+ q_sync_sep->isreduced = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X1000) == 0u) ? VDEC_NO : VDEC_YES;
+ /* Sync pulse amplitude detection result */
+ q_sync_sep->syncdepth = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X03FF);
+ }
+ /* Agc */
+ if (q_agc != NULL) {
+ reg_value = (uint32_t)*(vdec_reg->agccsr1);
+ /* Number of pixels which have larger luminance value than peak luminance limited by peak limiter */
+ q_agc->highsamples = (uint16_t)(reg_value >> VEDC_REG_SHIFT_8);
+ /* Number of overflowing pixels */
+ q_agc->peaksamples = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X00FF);
+
+ reg_value = (uint32_t)*(vdec_reg->agccsr2);
+ /* AGC convergence detection result */
+ if ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0100) == 0u) {
+ q_agc->agcconverge = (uint16_t)0x0000u;
+ } else {
+ q_agc->agcconverge = (uint16_t)0x0001u;
+ }
+ /* Current AGC gain value */
+ q_agc->agcgain = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X00FF);
+ }
+ /* Chroma decoding */
+ if (q_chroma_dec != NULL) {
+ reg_value = (uint32_t)*(vdec_reg->cromasr1);
+ /* Color system detection result */
+ q_chroma_dec->colorsys = (vdec_color_sys_t)(reg_value >> VEDC_REG_SHIFT_14);
+ /* Color sub-carrier frequency detection result */
+ q_chroma_dec->fscmode = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X2000) == 0u) ? VDEC_FSCMD_3_58 :
+ VDEC_FSCMD_4_43;
+ /* Burst lock PLL lock state detection result */
+ q_chroma_dec->fsclock = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X1000) == 0u) ? VDEC_UNLOCK : VDEC_LOCK;
+ /* Color burst detection result */
+ q_chroma_dec->noburst_ = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0800) == 0u) ? VDEC_YES : VDEC_NO;
+ /* Current ACC gain value (sub) */
+ q_chroma_dec->accsubgain = (vdec_chrm_subgain_t)((reg_value >> VEDC_REG_SHIFT_9) &
+ (uint32_t)VDEC_REG_MASK_0X0003);
+ /* Current ACC gain value (main) */
+ q_chroma_dec->accmaingain = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X01FF);
+
+ reg_value = (uint32_t)*(vdec_reg->cromasr2);
+ /* SECAM detection result */
+ q_chroma_dec->issecam = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X1000) == 0u) ? VDEC_NO : VDEC_YES;
+ /* PAL detection result */
+ q_chroma_dec->ispal = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0800) == 0u) ? VDEC_NO : VDEC_YES;
+ /* NTSC detection result */
+ q_chroma_dec->isntsc = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0400) == 0u) ? VDEC_NO : VDEC_YES;
+ /* Low S/N signal detection result by burst lock PLL */
+ q_chroma_dec->locklevel = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X00FF);
+ }
+ /* Digital clamp */
+ if (q_digital_clamp != NULL) {
+ reg_value = (uint32_t)*(vdec_reg->dcpsr1);
+ /* Digital clamp subtraction value (Cb signal) */
+ q_digital_clamp->clamplevel_cb = (uint16_t)(reg_value >> VEDC_REG_SHIFT_10);
+ /* Digital clamp subtraction value (Y signal) */
+ q_digital_clamp->clamplevel_y = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X03FF);
+
+ /* Digital clamp subtraction value (Cr signal) */
+ q_digital_clamp->clamplevel_cr = (uint16_t)((uint32_t)*(vdec_reg->dcpsr2) >> VEDC_REG_SHIFT_10);
+
+ /* Noise autocorrelation strength at digital clamp pulse position */
+ q_digital_clamp->acfstrength = *(vdec_reg->nsdsr);
+ }
+ return;
+} /* End of function VDEC_Query() */
+
+/**************************************************************************//**
+ * @brief Sets registers for noise reduction LPF
+ * @param[in] vdec_reg : VDEC registers
+ * @param[in] p_noise_rd_lpf : Noise reduction LPF parameter
+ * @retval None
+ *****************************************************************************/
+static void NoiseReductionLPF (
+ const vdec_reg_address_t * const vdec_reg,
+ const vdec_noise_rd_lpf_t * const p_noise_rd_lpf)
+{
+ uint32_t reg_data;
+
+ /* Noise reduction LPF */
+ if (p_noise_rd_lpf != NULL) {
+ reg_data = (uint32_t)*(vdec_reg->synscr1) & (uint32_t)(~VDEC_REG_MASK_0XFC00);
+ /* LPF cutoff frequency before vertical sync separation */
+ reg_data |= (uint32_t)p_noise_rd_lpf->lpfvsync << VEDC_REG_SHIFT_13;
+ /* LPF cutoff frequency before horizontal sync separation */
+ reg_data |= (uint32_t)p_noise_rd_lpf->lpfhsync << VEDC_REG_SHIFT_10;
+
+ *(vdec_reg->synscr1) = (uint16_t)reg_data;
+ }
+ return;
+} /* End of function NoiseReductionLPF() */
+
+/**************************************************************************//**
+ * @brief Sets registers for auto level control sync slicer
+ * @param[in] vdec_reg : VDEC registers
+ * @param[in] p_sync_slicer : Auto level control sync slicer parameter
+ * @retval None
+ *****************************************************************************/
+static void SyncSlicer (const vdec_reg_address_t * const vdec_reg, const vdec_sync_slicer_t * const p_sync_slicer)
+{
+ uint32_t reg_data;
+
+ /* Auto level control sync slicer */
+ if (p_sync_slicer != NULL) {
+ reg_data = (uint32_t)*(vdec_reg->synscr1) & (uint32_t)(~VDEC_REG_MASK_0X00FF);
+ /* Reference level operation speed control for composite sync separation (for Hsync signal) */
+ reg_data |= (uint32_t)p_sync_slicer->velocityshift_h << VEDC_REG_SHIFT_4;
+ /* Auto-slice level setting for composite sync separation circuit (for Hsync signal) */
+ reg_data |= (uint32_t)p_sync_slicer->slicermode_h << VEDC_REG_SHIFT_2;
+ /* Auto-slice level setting for composite sync separation circuit (for Vsync signal) */
+ reg_data |= (uint32_t)p_sync_slicer->slicermode_v;
+
+ *(vdec_reg->synscr1) = (uint16_t)reg_data;
+
+ /* Max ratio of horizontal cycle to horizontal sync signal pulse width
+ and min ratio of horizontal cycle to horizontal sync signal pulse width (for Hsync signal) */
+ reg_data = (uint32_t)p_sync_slicer->syncmaxduty_h << VEDC_REG_SHIFT_6;
+ reg_data |= (uint32_t)p_sync_slicer->syncminduty_h;
+
+ *(vdec_reg->synscr2) = (uint16_t)reg_data;
+
+ /* Clipping level and slice level for composite sync signal separation (for Hsync signal) */
+ reg_data = (uint32_t)p_sync_slicer->ssclipsel << VEDC_REG_SHIFT_10;
+ reg_data |= (uint32_t)p_sync_slicer->csyncslice_h;
+
+ *(vdec_reg->synscr3) = (uint16_t)reg_data;
+
+ /* Max ratio of horizontal cycle to horizontal sync signal pulse width
+ and min ratio of horizontal cycle to horizontal sync signal pulse width (for Vsync signal) */
+ reg_data = (uint32_t)p_sync_slicer->syncmaxduty_v << VEDC_REG_SHIFT_6;
+ reg_data |= (uint32_t)p_sync_slicer->syncminduty_v;
+
+ *(vdec_reg->synscr4) = (uint16_t)reg_data;
+
+ /* Delays the separated vertical sync signal for 1/4 horizontal cycle */
+ reg_data = (p_sync_slicer->vsyncdelay == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X8000;
+ /* Threshold for vertical sync separation */
+ reg_data |= (uint32_t)p_sync_slicer->vsyncslice << VEDC_REG_SHIFT_10;
+ /* Slice level for composite sync signal separation (for Vsync signal) */
+ reg_data |= (uint32_t)p_sync_slicer->csyncslice_v;
+
+ *(vdec_reg->synscr5) = (uint16_t)reg_data;
+ }
+ return;
+} /* End of function SyncSlicer() */
+
+/**************************************************************************//**
+ * @brief Sets registers for horizontal AFC
+ * @param[in] vdec_reg : VDEC registers
+ * @param[in] p_horizontal_afc : Horizontal AFC parameter
+ * @retval None
+ *****************************************************************************/
+static void HorizontalAFC (
+ const vdec_reg_address_t * const vdec_reg,
+ const vdec_horizontal_afc_t * const p_horizontal_afc)
+{
+ uint32_t reg_data;
+
+ /* Horizontal AFC */
+ if (p_horizontal_afc != NULL) {
+ reg_data = (uint32_t)*(vdec_reg->hafccr1) & (uint32_t)(~VDEC_REG_MASK_0XF3FF);
+ /* Horizontal AFC loop gain */
+ reg_data |= (uint32_t)p_horizontal_afc->hafcgain << VEDC_REG_SHIFT_12;
+ /* Horizontal AFC center oscillation frequency */
+ reg_data |= (uint32_t)p_horizontal_afc->hafctyp;
+
+ *(vdec_reg->hafccr1) = (uint16_t)reg_data;
+
+ /* Start line of horizontal AFC normal operation
+ and Horizontal AFC forced double-speed oscillation (DOX2HOSC = 0, auto control) */
+ reg_data = (uint32_t)p_horizontal_afc->hafcstart << VEDC_REG_SHIFT_12;
+ /* Disable of horizontal AFC double speed detection */
+ reg_data |= (p_horizontal_afc->nox2hosc == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0800;
+ /* Maximum oscillation frequency of horizontal AFC */
+ reg_data |= (uint32_t)p_horizontal_afc->hafcmax;
+
+ *(vdec_reg->hafccr2) = (uint16_t)reg_data;
+
+ /* End line of horizontal AFC normal operation */
+ reg_data = (uint32_t)p_horizontal_afc->hafcend << VEDC_REG_SHIFT_12;
+ /* Horizontal AFC VBI period operating mode */
+ reg_data |= (uint32_t)p_horizontal_afc->hafcmode << VEDC_REG_SHIFT_10;
+ /* Min oscillation frequency of horizontal AFC */
+ reg_data |= (uint32_t)p_horizontal_afc->hafcmin;
+
+ *(vdec_reg->hafccr3) = (uint16_t)reg_data;
+
+ /* Forcible or LOWGAIN control */
+ reg_data = (p_horizontal_afc->phdet_fix == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0010;
+ /* Phase comparator feedback adjust for low sync signal lock stability */
+ reg_data |= (uint32_t)p_horizontal_afc->phdet_div;
+
+ *(vdec_reg->afcpfcr) = (uint16_t)reg_data;
+ }
+ return;
+} /* End of function HorizontalAFC() */
+
+/**************************************************************************//**
+ * @brief Sets registers for vertical count-down
+ * @param[in] vdec_reg : VDEC registers
+ * @param[in] p_vcount_down : Vertical count-down parameter
+ * @retval None
+ *****************************************************************************/
+static void VerticalCountdown (
+ const vdec_reg_address_t * const vdec_reg,
+ const vdec_vcount_down_t * const p_vcount_down)
+{
+ uint32_t reg_data;
+
+ /* Vertical count-down */
+ if (p_vcount_down != NULL) {
+ /* Vertical countdown 50-Hz oscillation mode
+ and Vertical countdown free-run oscillation mode (VCDFREERUN = OFF) */
+ reg_data = (p_vcount_down->novcd50_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X4000 : (uint32_t)0x0000u;
+ /* Vertical countdown 60-Hz (59.94-Hz) oscillation mode */
+ reg_data |= (p_vcount_down->novcd60_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X2000 : (uint32_t)0x0000u;
+ /* Vertical countdown center oscillation frequency */
+ reg_data |= (uint32_t)p_vcount_down->vcddefault << VEDC_REG_SHIFT_11;
+ /* Vertical countdown sync area */
+ reg_data |= (uint32_t)p_vcount_down->vcdwindow << VEDC_REG_SHIFT_5;
+ /* Vertical countdown minimum oscillation frequency */
+ reg_data |= (uint32_t)p_vcount_down->vcdoffset;
+
+ *(vdec_reg->vcdwcr1) = (uint16_t)reg_data;
+ }
+ return;
+} /* End of function VerticalCountdown() */
+
+/**************************************************************************//**
+ * @brief Sets registers for AGC/PGA
+ * @param[in] vdec_reg : VDEC registers
+ * @param[in] p_agc : AGC/PGA parameter
+ * @retval None
+ *****************************************************************************/
+static void AgcPga (const vdec_reg_address_t * const vdec_reg, const vdec_agc_t * const p_agc)
+{
+ uint32_t reg_data;
+
+ /* AGC/PGA */
+ if (p_agc != NULL) {
+ /* A/D converter AGC ON/OFF control & PGA switch */
+ if (p_agc->agcmode == VDEC_OFF) {
+ reg_data = (uint32_t)*(vdec_reg->pgacr) | (uint32_t)VDEC_REG_SET_0X2000;
+ *(vdec_reg->pgacr) = (uint16_t)reg_data;
+ *(vdec_reg->adccr1) = (uint16_t)0u;
+ } else {
+ *(vdec_reg->adccr1) = (uint16_t)VDEC_REG_SET_0X0100;
+ reg_data = (uint32_t)*(vdec_reg->pgacr) & (uint32_t)(~VDEC_REG_SET_0X2000);
+ *(vdec_reg->pgacr) = (uint16_t)reg_data;
+ }
+ /* PGA gain */
+ reg_data = (uint32_t)*(vdec_reg->pgacr) & (uint32_t)(~VDEC_REG_MASK_0X1F00);
+ reg_data |= (uint32_t)p_agc->pga_gain << VEDC_REG_SHIFT_8;
+
+ *(vdec_reg->pgacr) = (uint16_t)reg_data;
+
+ /* PGA register update register */
+ *(vdec_reg->pga_update) = (uint16_t)1u;
+
+ /* Manual control of sync signal amplitude detection during VBI period */
+ reg_data = (p_agc->doreduce == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X2000;
+ /* Control of sync signal amplitude detection during VBI period */
+ reg_data |= (p_agc->noreduce_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X1000 : (uint32_t)0x0000u;
+ /* AGC response speed */
+ reg_data |= (uint32_t)p_agc->agcresponse << VEDC_REG_SHIFT_9;
+ /* Sync signal reference amplitude */
+ reg_data |= (uint32_t)p_agc->agclevel;
+
+ *(vdec_reg->agccr1) = (uint16_t)reg_data;
+
+ /* AGC gain adjustment accuracy */
+ reg_data = (uint32_t)*(vdec_reg->agccr2) & (uint32_t)(~VDEC_REG_MASK_0X3F00);
+ reg_data |= (uint32_t)p_agc->agcprecis << VEDC_REG_SHIFT_8;
+
+ *(vdec_reg->agccr2) = (uint16_t)reg_data;
+ }
+ return;
+} /* End of function AgcPga() */
+
+/**************************************************************************//**
+ * @brief Sets registers for peak limiter control
+ * @param[in] vdec_reg : VDEC registers
+ * @param[in] p_peak_limiter : Peak limiter control parameter
+ * @retval None
+ *****************************************************************************/
+static void PeakLimiterControl (
+ const vdec_reg_address_t * const vdec_reg,
+ const vdec_peak_limiter_t * const p_peak_limiter)
+{
+ uint32_t reg_data;
+
+ /* Peak limiter control */
+ if (p_peak_limiter != NULL) {
+ /* Peak luminance value limited by peak limiter */
+ reg_data = (uint32_t)p_peak_limiter->peaklevel << VEDC_REG_SHIFT_14;
+ /* Response speed with peak limiter gain decreased */
+ reg_data |= (uint32_t)p_peak_limiter->peakattack << VEDC_REG_SHIFT_12;
+ /* Response speed with peak limiter gain increased */
+ reg_data |= (uint32_t)p_peak_limiter->peakrelease << VEDC_REG_SHIFT_10;
+ /* Maximum compression rate of peak limiter */
+ reg_data |= (uint32_t)p_peak_limiter->peakratio << VEDC_REG_SHIFT_8;
+ /* Allowable number of overflowing pixels */
+ reg_data |= (uint32_t)p_peak_limiter->maxpeaksamples;
+
+ *(vdec_reg->pklimitcr) = (uint16_t)reg_data;
+ }
+ return;
+} /* End of function PeakLimiterControl() */
+
+/**************************************************************************//**
+ * @brief Sets registers for over-range control
+ * @param[in] vdec_reg : VDEC registers
+ * @param[in] p_over_range : Over-range control parameter
+ * @retval None
+ *****************************************************************************/
+static void OverRangeControl (const vdec_reg_address_t * const vdec_reg, const vdec_over_range_t * const p_over_range)
+{
+ uint32_t reg_data;
+
+ /* Over-range control */
+ if (p_over_range != NULL) {
+ /* A/D over-threshold level (between levels 0 and 1) */
+ *(vdec_reg->rgorcr1) = p_over_range->radj_o_level0;
+ /* A/D under-threshold level (between levels 2 and 3) */
+ *(vdec_reg->rgorcr2) = p_over_range->radj_u_level0;
+ /* A/D over-threshold level (between levels 1 and 2) */
+ *(vdec_reg->rgorcr3) = p_over_range->radj_o_level1;
+ /* A/D under-threshold level (between levels 1 and 2) */
+ *(vdec_reg->rgorcr4) = p_over_range->radj_u_level1;
+ /* A/D over-threshold level (between levels 2 and 3) */
+ *(vdec_reg->rgorcr5) = p_over_range->radj_o_level2;
+ /* A/D under-threshold level (between levels 0 and 1) */
+ *(vdec_reg->rgorcr6) = p_over_range->radj_u_level2;
+
+ reg_data = (uint32_t)*(vdec_reg->rgorcr7) & (uint32_t)(~VDEC_REG_MASK_0X0007);
+ /* Over-range detection enable */
+ reg_data |= (p_over_range->ucmp_sw == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0004;
+ /* Under-range detection enable */
+ reg_data |= (p_over_range->dcmp_sw == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0002;
+ /* Horizontal enlargement of over/under-range level */
+ reg_data |= (p_over_range->hwide_sw == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)0x0001u;
+
+ *(vdec_reg->rgorcr7) = (uint16_t)reg_data;
+ }
+ return;
+} /* End of function OverRangeControl() */
+
+/**************************************************************************//**
+ * @brief Sets registers for Y/C separation control
+ * @param[in] vdec_reg : VDEC registers
+ * @param[in] p_yc_sep_ctrl : Y/C separation control parameter
+ * @retval None
+ *****************************************************************************/
+static void YcSeparationControl (
+ const vdec_reg_address_t * const vdec_reg,
+ const vdec_yc_sep_ctrl_t * const p_yc_sep_ctrl)
+{
+ uint32_t reg_data;
+
+ /* Y/C separation control */
+ if (p_yc_sep_ctrl != NULL) {
+ /* Two-dimensional Y/C separation filter select coefficient (K15, K13, and K11) */
+ reg_data = (uint32_t)p_yc_sep_ctrl->k15 << VEDC_REG_SHIFT_12;
+ reg_data |= (uint32_t)p_yc_sep_ctrl->k13 << VEDC_REG_SHIFT_6;
+ reg_data |= (uint32_t)p_yc_sep_ctrl->k11;
+
+ *(vdec_reg->ycscr3) = (uint16_t)reg_data;
+
+ /* Two-dimensional Y/C separation filter select coefficient (K16, K14, and K12) */
+ reg_data = (uint32_t)p_yc_sep_ctrl->k16 << VEDC_REG_SHIFT_12;
+ reg_data |= (uint32_t)p_yc_sep_ctrl->k14 << VEDC_REG_SHIFT_6;
+ reg_data |= (uint32_t)p_yc_sep_ctrl->k12;
+
+ *(vdec_reg->ycscr4) = (uint16_t)reg_data;
+
+ /* Two-dimensional Y/C separation filter select coefficient (K22A and K21A) */
+ reg_data = (uint32_t)p_yc_sep_ctrl->k22a << VEDC_REG_SHIFT_8;
+ reg_data |= (uint32_t)p_yc_sep_ctrl->k21a;
+
+ *(vdec_reg->ycscr5) = (uint16_t)reg_data;
+
+ /* Two-dimensional Y/C separation filter select coefficient (K22B and K21B) */
+ reg_data = (uint32_t)p_yc_sep_ctrl->k22b << VEDC_REG_SHIFT_8;
+ reg_data |= (uint32_t)p_yc_sep_ctrl->k21b;
+
+ *(vdec_reg->ycscr6) = (uint16_t)reg_data;
+
+ /* Two-dimensional Y/C separation filter select coefficient (K23B, K23A, and K24) */
+ reg_data = (uint32_t)*(vdec_reg->ycscr7) & (uint32_t)(~VDEC_REG_MASK_0XFF1F);
+ reg_data |= (uint32_t)p_yc_sep_ctrl->k23b << VEDC_REG_SHIFT_12;
+ reg_data |= (uint32_t)p_yc_sep_ctrl->k23a << VEDC_REG_SHIFT_8;
+ reg_data |= (uint32_t)p_yc_sep_ctrl->k24;
+
+ *(vdec_reg->ycscr7) = (uint16_t)reg_data;
+
+ reg_data = (uint32_t)*(vdec_reg->ycscr8) & (uint32_t)(~VDEC_REG_MASK_0XF800);
+ /* Latter-stage horizontal BPF select */
+ reg_data |= (p_yc_sep_ctrl->hbpf_narrow == VDEC_LSTG_BPFSEL_BYPASS) ? (uint32_t)0x0000u :
+ (uint32_t)VDEC_REG_SET_0X8000;
+ /* Latter-stage horizontal/vertical BPF select */
+ reg_data |= (p_yc_sep_ctrl->hvbpf_narrow == VDEC_LSTG_BPFSEL_BYPASS) ? (uint32_t)0x0000u :
+ (uint32_t)VDEC_REG_SET_0X4000;
+ /* Former-stage horizontal BPF select */
+ reg_data |= (p_yc_sep_ctrl->hbpf1_9tap_on == VDEC_FSTG_BPFSEL_17TAP) ? (uint32_t)0x0000u :
+ (uint32_t)VDEC_REG_SET_0X2000;
+ /* Former-stage horizontal/vertical BPF select */
+ reg_data |= (p_yc_sep_ctrl->hvbpf1_9tap_on == VDEC_FSTG_BPFSEL_17TAP) ? (uint32_t)0x0000u :
+ (uint32_t)VDEC_REG_SET_0X1000;
+ /* Horizontal filter and horizontal/vertical filter bandwidth switch signal */
+ reg_data |= (p_yc_sep_ctrl->hfil_tap_sel == VDEC_HFIL_TAP_SEL_17TAP) ? (uint32_t)0x0000u :
+ (uint32_t)VDEC_REG_SET_0X0800;
+
+ *(vdec_reg->ycscr8) = (uint16_t)reg_data;
+
+ /* Two-dimensional filter mixing select */
+ reg_data = (p_yc_sep_ctrl->det2_on == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X8000;
+ /* Mixing ratio of signal after passing horizontal filter
+ to signal after passing former-stage horizontal filter */
+ reg_data |= (uint32_t)p_yc_sep_ctrl->hsel_mix_y << VEDC_REG_SHIFT_8;
+ /* Mixing ratio of signal after passing vertical filter
+ to signal after passing former-stage horizontal/vertical filter */
+ reg_data |= (uint32_t)p_yc_sep_ctrl->vsel_mix_y << VEDC_REG_SHIFT_4;
+ /* Mixing ratio of signal after passing horizontal/vertical filter
+ to signal after passing former-stage horizontal/vertical filter */
+ reg_data |= (uint32_t)p_yc_sep_ctrl->hvsel_mix_y;
+
+ *(vdec_reg->ycscr9) = (uint16_t)reg_data;
+
+ /* Vertical luminance detection level for correlation detection filter */
+ reg_data = (uint32_t)*(vdec_reg->ycscr11) & (uint32_t)(~VDEC_REG_MASK_0X01FF);
+ reg_data |= (uint32_t)p_yc_sep_ctrl->v_y_level;
+
+ *(vdec_reg->ycscr11) = (uint16_t)reg_data;
+
+ if (p_yc_sep_ctrl->det2_on == VDEC_OFF) {
+ reg_data = ((uint32_t)VDEC_FILMIX_RATIO_0 << VEDC_REG_SHIFT_12) |
+ ((uint32_t)VDEC_FILMIX_RATIO_0 << VEDC_REG_SHIFT_8);
+ } else {
+ /* Mixing ratio of C signal after passing horizontal/vertical adaptive filter
+ to signal after passing correlation detection filter */
+ reg_data = (uint32_t)p_yc_sep_ctrl->det2_mix_c << VEDC_REG_SHIFT_12;
+ /* Mixing ratio of C signal for Y generation after passing
+ horizontal/vertical adaptive filter to signal after passing correlation */
+ reg_data |= (uint32_t)p_yc_sep_ctrl->det2_mix_y << VEDC_REG_SHIFT_8;
+ }
+ /* Two-dimensional cascade/TAKE-OFF filter mode select */
+ reg_data |= (uint32_t)p_yc_sep_ctrl->fil2_mode_2d << VEDC_REG_SHIFT_2;
+ /* Two-dimensional cascade filter select */
+ reg_data |= (p_yc_sep_ctrl->fil2_narrow_2d == VDEC_2D_FIL_SEL_BYPASS) ? (uint32_t)0x0000u :
+ (uint32_t)0x0001u;
+
+ *(vdec_reg->ycscr12) = (uint16_t)reg_data;
+ }
+ return;
+} /* End of function YcSeparationControl() */
+
+/**************************************************************************//**
+ * @brief Sets registers for chroma filter TAP coefficient
+ * @param[in] fil_reg_address : 2D filter TAP coefficient registers
+ * @param[in] fil2_2d : Chroma filter TAP coefficient for Y/C separation
+ * @retval None
+ *****************************************************************************/
+static void FilterTAPsCoefficient (
+ volatile uint16_t * const * fil_reg_address,
+ const vdec_chrfil_tap_t * const fil2_2d)
+{
+ int32_t tap_coef;
+ volatile uint16_t * fil_reg;
+ const uint16_t * taps;
+
+ if (fil2_2d != NULL) {
+ taps = fil2_2d->fil2_2d_f;
+ for (tap_coef = 0; tap_coef < VDEC_CHRFIL_TAPCOEF_NUM; tap_coef++) {
+ fil_reg = *fil_reg_address;
+ fil_reg_address++;
+ *fil_reg = *taps;
+ taps++;
+ }
+ }
+ return;
+} /* End of function FilterTAPsCoefficient() */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/vdec/src/r_vdec_register.h Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,153 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file r_vdec_register.h
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief VDEC driver register setup definitions
+******************************************************************************/
+
+#ifndef R_VDEC_REGISTER_H
+#define R_VDEC_REGISTER_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_vdec.h"
+#include "r_vdec_user.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! VDEC register address list */
+typedef struct {
+ volatile uint16_t * adccr1;
+ volatile uint16_t * tgcr1;
+ volatile uint16_t * tgcr2;
+ volatile uint16_t * tgcr3;
+ volatile uint16_t * synscr1;
+ volatile uint16_t * synscr2;
+ volatile uint16_t * synscr3;
+ volatile uint16_t * synscr4;
+ volatile uint16_t * synscr5;
+ volatile uint16_t * hafccr1;
+ volatile uint16_t * hafccr2;
+ volatile uint16_t * hafccr3;
+ volatile uint16_t * vcdwcr1;
+ volatile uint16_t * dcpcr1;
+ volatile uint16_t * dcpcr2;
+ volatile uint16_t * dcpcr3;
+ volatile uint16_t * dcpcr4;
+ volatile uint16_t * dcpcr5;
+ volatile uint16_t * dcpcr6;
+ volatile uint16_t * dcpcr7;
+ volatile uint16_t * dcpcr8;
+ volatile uint16_t * nsdcr;
+ volatile uint16_t * btlcr;
+ volatile uint16_t * btgpcr;
+ volatile uint16_t * acccr1;
+ volatile uint16_t * acccr2;
+ volatile uint16_t * acccr3;
+ volatile uint16_t * tintcr;
+ volatile uint16_t * ycdcr;
+ volatile uint16_t * agccr1;
+ volatile uint16_t * agccr2;
+ volatile uint16_t * pklimitcr;
+ volatile uint16_t * rgorcr1;
+ volatile uint16_t * rgorcr2;
+ volatile uint16_t * rgorcr3;
+ volatile uint16_t * rgorcr4;
+ volatile uint16_t * rgorcr5;
+ volatile uint16_t * rgorcr6;
+ volatile uint16_t * rgorcr7;
+ volatile uint16_t * afcpfcr;
+ volatile uint16_t * rupdcr;
+ volatile uint16_t * vsyncsr;
+ volatile uint16_t * hsyncsr;
+ volatile uint16_t * dcpsr1;
+ volatile uint16_t * dcpsr2;
+ volatile uint16_t * nsdsr;
+ volatile uint16_t * cromasr1;
+ volatile uint16_t * cromasr2;
+ volatile uint16_t * syncssr;
+ volatile uint16_t * agccsr1;
+ volatile uint16_t * agccsr2;
+ volatile uint16_t * ycscr3;
+ volatile uint16_t * ycscr4;
+ volatile uint16_t * ycscr5;
+ volatile uint16_t * ycscr6;
+ volatile uint16_t * ycscr7;
+ volatile uint16_t * ycscr8;
+ volatile uint16_t * ycscr9;
+ volatile uint16_t * ycscr11;
+ volatile uint16_t * ycscr12;
+ volatile uint16_t * dcpcr9;
+ volatile uint16_t * ygaincr;
+ volatile uint16_t * cbgaincr;
+ volatile uint16_t * crgaincr;
+ volatile uint16_t * pga_update;
+ volatile uint16_t * pgacr;
+ volatile uint16_t * adccr2;
+} vdec_reg_address_t;
+
+/*! VDEC register address list (for 2D filter tap coefficient) */
+typedef struct {
+ volatile uint16_t * yctwa_f[VDEC_CHRFIL_TAPCOEF_NUM];
+ volatile uint16_t * yctwb_f[VDEC_CHRFIL_TAPCOEF_NUM];
+ volatile uint16_t * yctna_f[VDEC_CHRFIL_TAPCOEF_NUM];
+ volatile uint16_t * yctnb_f[VDEC_CHRFIL_TAPCOEF_NUM];
+} vdec_filter_reg_address_t;
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+extern const vdec_reg_address_t vdec_reg_address[VDEC_CHANNEL_NUM];
+extern const vdec_filter_reg_address_t vdec_filter_reg_address[VDEC_CHANNEL_NUM];
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void VDEC_Initialize(const vdec_channel_t ch, const vdec_adc_vinsel_t vinsel);
+void VDEC_ActivePeriod(const vdec_channel_t ch, const vdec_active_period_t * const param);
+void VDEC_SyncSeparation(const vdec_channel_t ch, const vdec_sync_separation_t * const param);
+void VDEC_YcSeparation(const vdec_channel_t ch, const vdec_yc_separation_t * const param);
+void VDEC_ChromaDecoding(const vdec_channel_t ch, const vdec_chroma_decoding_t * const param);
+void VDEC_DigitalClamp(const vdec_channel_t ch, const vdec_degital_clamp_t * const param);
+void VDEC_Output(const vdec_channel_t ch, const vdec_output_t * const param);
+void VDEC_Query(
+ const vdec_channel_t ch,
+ vdec_q_sync_sep_t * const q_sync_sep,
+ vdec_q_agc_t * const q_agc,
+ vdec_q_chroma_dec_t * const q_chroma_dec,
+ vdec_q_digital_clamp_t * const q_digital_clamp);
+
+
+#endif /* R_VDEC_REGISTER_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/vdec/src/r_vdec_register_address.c Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,287 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file r_vdec_register_address.c
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief VDEC driver register address table
+******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_vdec.h"
+#include "r_vdec_user.h"
+#include "r_vdec_register.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+/* VDEC register address list */
+const vdec_reg_address_t vdec_reg_address[VDEC_CHANNEL_NUM] = {
+ { /* Channel 0 */
+ &DVDEC0.ADCCR1,
+ &DVDEC0.TGCR1,
+ &DVDEC0.TGCR2,
+ &DVDEC0.TGCR3,
+ &DVDEC0.SYNSCR1,
+ &DVDEC0.SYNSCR2,
+ &DVDEC0.SYNSCR3,
+ &DVDEC0.SYNSCR4,
+ &DVDEC0.SYNSCR5,
+ &DVDEC0.HAFCCR1,
+ &DVDEC0.HAFCCR2,
+ &DVDEC0.HAFCCR3,
+ &DVDEC0.VCDWCR1,
+ &DVDEC0.DCPCR1,
+ &DVDEC0.DCPCR2,
+ &DVDEC0.DCPCR3,
+ &DVDEC0.DCPCR4,
+ &DVDEC0.DCPCR5,
+ &DVDEC0.DCPCR6,
+ &DVDEC0.DCPCR7,
+ &DVDEC0.DCPCR8,
+ &DVDEC0.NSDCR,
+ &DVDEC0.BTLCR,
+ &DVDEC0.BTGPCR,
+ &DVDEC0.ACCCR1,
+ &DVDEC0.ACCCR2,
+ &DVDEC0.ACCCR3,
+ &DVDEC0.TINTCR,
+ &DVDEC0.YCDCR,
+ &DVDEC0.AGCCR1,
+ &DVDEC0.AGCCR2,
+ &DVDEC0.PKLIMITCR,
+ &DVDEC0.RGORCR1,
+ &DVDEC0.RGORCR2,
+ &DVDEC0.RGORCR3,
+ &DVDEC0.RGORCR4,
+ &DVDEC0.RGORCR5,
+ &DVDEC0.RGORCR6,
+ &DVDEC0.RGORCR7,
+ &DVDEC0.AFCPFCR,
+ &DVDEC0.RUPDCR,
+ &DVDEC0.VSYNCSR,
+ &DVDEC0.HSYNCSR,
+ &DVDEC0.DCPSR1,
+ &DVDEC0.DCPSR2,
+ &DVDEC0.NSDSR,
+ &DVDEC0.CROMASR1,
+ &DVDEC0.CROMASR2,
+ &DVDEC0.SYNCSSR,
+ &DVDEC0.AGCCSR1,
+ &DVDEC0.AGCCSR2,
+ &DVDEC0.YCSCR3,
+ &DVDEC0.YCSCR4,
+ &DVDEC0.YCSCR5,
+ &DVDEC0.YCSCR6,
+ &DVDEC0.YCSCR7,
+ &DVDEC0.YCSCR8,
+ &DVDEC0.YCSCR9,
+ &DVDEC0.YCSCR11,
+ &DVDEC0.YCSCR12,
+ &DVDEC0.DCPCR9,
+ &DVDEC0.YGAINCR,
+ &DVDEC0.CBGAINCR,
+ &DVDEC0.CRGAINCR,
+ &DVDEC0.PGA_UPDATE,
+ &DVDEC0.PGACR,
+ &DVDEC0.ADCCR2
+ },
+ { /* Channel 1 */
+ &DVDEC1.ADCCR1,
+ &DVDEC1.TGCR1,
+ &DVDEC1.TGCR2,
+ &DVDEC1.TGCR3,
+ &DVDEC1.SYNSCR1,
+ &DVDEC1.SYNSCR2,
+ &DVDEC1.SYNSCR3,
+ &DVDEC1.SYNSCR4,
+ &DVDEC1.SYNSCR5,
+ &DVDEC1.HAFCCR1,
+ &DVDEC1.HAFCCR2,
+ &DVDEC1.HAFCCR3,
+ &DVDEC1.VCDWCR1,
+ &DVDEC1.DCPCR1,
+ &DVDEC1.DCPCR2,
+ &DVDEC1.DCPCR3,
+ &DVDEC1.DCPCR4,
+ &DVDEC1.DCPCR5,
+ &DVDEC1.DCPCR6,
+ &DVDEC1.DCPCR7,
+ &DVDEC1.DCPCR8,
+ &DVDEC1.NSDCR,
+ &DVDEC1.BTLCR,
+ &DVDEC1.BTGPCR,
+ &DVDEC1.ACCCR1,
+ &DVDEC1.ACCCR2,
+ &DVDEC1.ACCCR3,
+ &DVDEC1.TINTCR,
+ &DVDEC1.YCDCR,
+ &DVDEC1.AGCCR1,
+ &DVDEC1.AGCCR2,
+ &DVDEC1.PKLIMITCR,
+ &DVDEC1.RGORCR1,
+ &DVDEC1.RGORCR2,
+ &DVDEC1.RGORCR3,
+ &DVDEC1.RGORCR4,
+ &DVDEC1.RGORCR5,
+ &DVDEC1.RGORCR6,
+ &DVDEC1.RGORCR7,
+ &DVDEC1.AFCPFCR,
+ &DVDEC1.RUPDCR,
+ &DVDEC1.VSYNCSR,
+ &DVDEC1.HSYNCSR,
+ &DVDEC1.DCPSR1,
+ &DVDEC1.DCPSR2,
+ &DVDEC1.NSDSR,
+ &DVDEC1.CROMASR1,
+ &DVDEC1.CROMASR2,
+ &DVDEC1.SYNCSSR,
+ &DVDEC1.AGCCSR1,
+ &DVDEC1.AGCCSR2,
+ &DVDEC1.YCSCR3,
+ &DVDEC1.YCSCR4,
+ &DVDEC1.YCSCR5,
+ &DVDEC1.YCSCR6,
+ &DVDEC1.YCSCR7,
+ &DVDEC1.YCSCR8,
+ &DVDEC1.YCSCR9,
+ &DVDEC1.YCSCR11,
+ &DVDEC1.YCSCR12,
+ &DVDEC1.DCPCR9,
+ &DVDEC1.YGAINCR,
+ &DVDEC1.CBGAINCR,
+ &DVDEC1.CRGAINCR,
+ &DVDEC1.PGA_UPDATE,
+ &DVDEC1.PGACR,
+ &DVDEC1.ADCCR2
+ }
+};
+
+/* VDEC register address list (for 2D filter tap coefficient) */
+const vdec_filter_reg_address_t vdec_filter_reg_address[VDEC_CHANNEL_NUM] = {
+ { /* Channel 0 */
+ {
+ &DVDEC0.YCTWA_F0,
+ &DVDEC0.YCTWA_F1,
+ &DVDEC0.YCTWA_F2,
+ &DVDEC0.YCTWA_F3,
+ &DVDEC0.YCTWA_F4,
+ &DVDEC0.YCTWA_F5,
+ &DVDEC0.YCTWA_F6,
+ &DVDEC0.YCTWA_F7,
+ &DVDEC0.YCTWA_F8
+ },
+ {
+ &DVDEC0.YCTWB_F0,
+ &DVDEC0.YCTWB_F1,
+ &DVDEC0.YCTWB_F2,
+ &DVDEC0.YCTWB_F3,
+ &DVDEC0.YCTWB_F4,
+ &DVDEC0.YCTWB_F5,
+ &DVDEC0.YCTWB_F6,
+ &DVDEC0.YCTWB_F7,
+ &DVDEC0.YCTWB_F8
+ },
+ {
+ &DVDEC0.YCTNA_F0,
+ &DVDEC0.YCTNA_F1,
+ &DVDEC0.YCTNA_F2,
+ &DVDEC0.YCTNA_F3,
+ &DVDEC0.YCTNA_F4,
+ &DVDEC0.YCTNA_F5,
+ &DVDEC0.YCTNA_F6,
+ &DVDEC0.YCTNA_F7,
+ &DVDEC0.YCTNA_F8
+ },
+ {
+ &DVDEC0.YCTNB_F0,
+ &DVDEC0.YCTNB_F1,
+ &DVDEC0.YCTNB_F2,
+ &DVDEC0.YCTNB_F3,
+ &DVDEC0.YCTNB_F4,
+ &DVDEC0.YCTNB_F5,
+ &DVDEC0.YCTNB_F6,
+ &DVDEC0.YCTNB_F7,
+ &DVDEC0.YCTNB_F8
+ }
+ },
+ { /* Channel 1 */
+ {
+ &DVDEC1.YCTWA_F0,
+ &DVDEC1.YCTWA_F1,
+ &DVDEC1.YCTWA_F2,
+ &DVDEC1.YCTWA_F3,
+ &DVDEC1.YCTWA_F4,
+ &DVDEC1.YCTWA_F5,
+ &DVDEC1.YCTWA_F6,
+ &DVDEC1.YCTWA_F7,
+ &DVDEC1.YCTWA_F8
+ },
+ {
+ &DVDEC1.YCTWB_F0,
+ &DVDEC1.YCTWB_F1,
+ &DVDEC1.YCTWB_F2,
+ &DVDEC1.YCTWB_F3,
+ &DVDEC1.YCTWB_F4,
+ &DVDEC1.YCTWB_F5,
+ &DVDEC1.YCTWB_F6,
+ &DVDEC1.YCTWB_F7,
+ &DVDEC1.YCTWB_F8
+ },
+ {
+ &DVDEC1.YCTNA_F0,
+ &DVDEC1.YCTNA_F1,
+ &DVDEC1.YCTNA_F2,
+ &DVDEC1.YCTNA_F3,
+ &DVDEC1.YCTNA_F4,
+ &DVDEC1.YCTNA_F5,
+ &DVDEC1.YCTNA_F6,
+ &DVDEC1.YCTNA_F7,
+ &DVDEC1.YCTNA_F8
+ },
+ {
+ &DVDEC1.YCTNB_F0,
+ &DVDEC1.YCTNB_F1,
+ &DVDEC1.YCTNB_F2,
+ &DVDEC1.YCTNB_F3,
+ &DVDEC1.YCTNB_F4,
+ &DVDEC1.YCTNB_F5,
+ &DVDEC1.YCTNB_F6,
+ &DVDEC1.YCTNB_F7,
+ &DVDEC1.YCTNB_F8
+ }
+ }
+};
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/gr_peach_vdc5.c Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,1192 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file gr_peach_vdc5.c
+* @version
+* $Rev:
+* $Date::
+* @brief VDC5 driver API wrapper function in C interface
+******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include <stdio.h>
+#include <string.h>
+
+#include "r_typedefs.h"
+#include "r_vdc5.h"
+#include "video_decoder.h"
+#include "lvds_pll_calc.h"
+#include "gr_peach_vdc5.h"
+
+#include "mbed_assert.h"
+#include "pinmap.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+//#define DEBUG_USING_GENMAI_BOARD /* debug code */
+#define STP91_BIT (0x02u)
+#define STP90_BIT (0x01u)
+#define STBRQ25_BIT (0x20u)
+#define STBAK25_BIT (0x20u)
+#define STBRQ24_BIT (0x10u)
+#define STBAK24_BIT (0x10u)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+typedef enum {
+ VDC5_CH0,
+ VDC5_CH1,
+} VDC5Name;
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+static const PinMap PinMap_DV_INPUT_PIN[] = {
+ {P8_11 , VDC5_CH0, 8}, /* DV0_CLK */
+ {P10_0 , VDC5_CH0, 1}, /* DV0_CLK */
+ {P1_12 , VDC5_CH0, 2}, /* DV0_VSYNC */
+ {P1_13 , VDC5_CH0, 2}, /* DV0_HSYNC */
+ {P1_1 , VDC5_CH0, 6}, /* DV0_HSYNC */
+ {P1_0 , VDC5_CH0, 6}, /* DV0_VSYNC */
+ {P1_9 , VDC5_CH0, 6}, /* DV0_DATA15 */
+ {P2_15 , VDC5_CH0, 3}, /* DV0_DATA15 */
+ {P4_7 , VDC5_CH0, 7}, /* DV0_DATA15 */
+ {P5_7 , VDC5_CH0, 4}, /* DV0_DATA15 */
+ {P1_8 , VDC5_CH0, 6}, /* DV0_DATA14 */
+ {P2_14 , VDC5_CH0, 3}, /* DV0_DATA14 */
+ {P4_6 , VDC5_CH0, 7}, /* DV0_DATA14 */
+ {P5_6 , VDC5_CH0, 4}, /* DV0_DATA14 */
+ {P1_7 , VDC5_CH0, 6}, /* DV0_DATA13 */
+ {P2_13 , VDC5_CH0, 3}, /* DV0_DATA13 */
+ {P4_5 , VDC5_CH0, 7}, /* DV0_DATA13 */
+ {P5_5 , VDC5_CH0, 4}, /* DV0_DATA13 */
+ {P1_6 , VDC5_CH0, 6}, /* DV0_DATA12 */
+ {P4_4 , VDC5_CH0, 7}, /* DV0_DATA12 */
+ {P5_4 , VDC5_CH0, 4}, /* DV0_DATA12 */
+ {P10_5 , VDC5_CH0, 1}, /* DV0_DATA11 */
+ {P2_10 , VDC5_CH0, 3}, /* DV0_DATA10 */
+ {P10_14, VDC5_CH0, 1}, /* DV0_DATA10 */
+ {P2_9 , VDC5_CH0, 3}, /* DV0_DATA9 */
+ {P10_13, VDC5_CH0, 1}, /* DV0_DATA9 */
+ {P10_12, VDC5_CH0, 1}, /* DV0_DATA8 */
+ {P2_7 , VDC5_CH0, 3}, /* DV0_DATA7 */
+ {P2_6 , VDC5_CH0, 3}, /* DV0_DATA6 */
+ {P2_5 , VDC5_CH0, 3}, /* DV0_DATA5 */
+ {P2_4 , VDC5_CH0, 3}, /* DV0_DATA4 */
+ {P2_3 , VDC5_CH0, 3}, /* DV0_DATA3 */
+ {P2_2 , VDC5_CH0, 3}, /* DV0_DATA2 */
+ {P2_1 , VDC5_CH0, 3}, /* DV0_DATA1 */
+ {P2_0 , VDC5_CH0, 3}, /* DV0_DATA0 */
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_LCD_DISP_PIN[] = {
+ {P2_7 , VDC5_CH0, 8}, /* LCD0_DATA23 */
+ {P10_0 , VDC5_CH0, 5}, /* LCD0_DATA23 */
+ {P2_6 , VDC5_CH0, 8}, /* LCD0_DATA22 */
+ {P2_5 , VDC5_CH0, 8}, /* LCD0_DATA21 */
+ {P2_4 , VDC5_CH0, 8}, /* LCD0_DATA20 */
+ {P2_3 , VDC5_CH0, 8}, /* LCD0_DATA19 */
+ {P2_2 , VDC5_CH0, 8}, /* LCD0_DATA18 */
+ {P2_1 , VDC5_CH0, 8}, /* LCD0_DATA17 */
+ {P2_0 , VDC5_CH0, 8}, /* LCD0_DATA16 */
+ {P4_7 , VDC5_CH0, 1}, /* LCD0_DATA15 */
+ {P4_6 , VDC5_CH0, 1}, /* LCD0_DATA14 */
+ {P4_5 , VDC5_CH0, 1}, /* LCD0_DATA13 */
+ {P4_4 , VDC5_CH0, 1}, /* LCD0_DATA12 */
+ {P10_12, VDC5_CH0, 5}, /* LCD0_DATA11 */
+ {P10_13, VDC5_CH0, 5}, /* LCD0_DATA10 */
+ {P10_14, VDC5_CH0, 5}, /* LCD0_DATA9 */
+ {P4_0 , VDC5_CH0, 1}, /* LCD0_DATA8 */
+ {P10_15, VDC5_CH0, 5}, /* LCD0_DATA8 */
+ {P3_15 , VDC5_CH0, 1}, /* LCD0_DATA7 */
+ {P3_14 , VDC5_CH0, 1}, /* LCD0_DATA6 */
+ {P3_13 , VDC5_CH0, 1}, /* LCD0_DATA5 */
+ {P3_12 , VDC5_CH0, 1}, /* LCD0_DATA4 */
+ {P3_11 , VDC5_CH0, 1}, /* LCD0_DATA3 */
+ {P3_10 , VDC5_CH0, 1}, /* LCD0_DATA2 */
+ {P3_9 , VDC5_CH0, 1}, /* LCD0_DATA1 */
+ {P3_8 , VDC5_CH0, 1}, /* LCD0_DATA0 */
+ {P11_12, VDC5_CH0, 5}, /* LCD0_TCON2 */
+ {P3_2 , VDC5_CH0, 1}, /* LCD0_TCON1 */
+ {P11_13, VDC5_CH0, 5}, /* LCD0_TCON1 */
+ {P11_14, VDC5_CH0, 5}, /* LCD0_TCON0 */
+ {P11_15, VDC5_CH0, 5}, /* LCD0_CLK */
+ {NC , NC , 0}
+};
+#ifdef DEBUG_USING_GENMAI_BOARD
+static const PinMap PinMap_LCD_DISP_GENMAI_PC_MONI_PIN[] = {
+ {P10_0 , VDC5_CH0, 5}, /* LCD0_DATA23 */
+ {P10_1 , VDC5_CH0, 5}, /* LCD0_DATA22 */
+ {P10_2 , VDC5_CH0, 5}, /* LCD0_DATA21 */
+ {P10_3 , VDC5_CH0, 5}, /* LCD0_DATA20 */
+ {P10_4 , VDC5_CH0, 5}, /* LCD0_DATA19 */
+ {P10_5 , VDC5_CH0, 5}, /* LCD0_DATA18 */
+ {P10_7 , VDC5_CH0, 5}, /* LCD0_DATA17 */
+ {P10_8 , VDC5_CH0, 5}, /* LCD0_DATA16 */
+ {P10_9 , VDC5_CH0, 5}, /* LCD0_DATA14 */
+ {P10_10 , VDC5_CH0, 5}, /* LCD0_DATA13 */
+ {P10_11 , VDC5_CH0, 5}, /* LCD0_DATA12 */
+ {P10_12 , VDC5_CH0, 5}, /* LCD0_DATA11 */
+ {P10_13 , VDC5_CH0, 5}, /* LCD0_DATA10 */
+ {P10_14 , VDC5_CH0, 5}, /* LCD0_DATA9 */
+ {P10_15 , VDC5_CH0, 5}, /* LCD0_DATA8 */
+ {P11_0 , VDC5_CH0, 5}, /* LCD0_DATA7 */
+ {P11_1 , VDC5_CH0, 5}, /* LCD0_DATA6 */
+ {P11_2 , VDC5_CH0, 5}, /* LCD0_DATA5 */
+ {P11_3 , VDC5_CH0, 5}, /* LCD0_DATA4 */
+ {P11_4 , VDC5_CH0, 5}, /* LCD0_DATA3 */
+ {P11_5 , VDC5_CH0, 5}, /* LCD0_DATA2 */
+ {P11_6 , VDC5_CH0, 5}, /* LCD0_DATA1 */
+ {P11_7 , VDC5_CH0, 5}, /* LCD0_DATA0 */
+ {P11_13 , VDC5_CH0, 5}, /* LCD0_TCON1 */
+ {P11_14 , VDC5_CH0, 5}, /* LCD0_TCON0 */
+ {P11_15 , VDC5_CH0, 5}, /* LCD0_CLK */
+ {NC , NC , 0}
+};
+#endif /* DEBUG_USING_GENMAI_BOARD */
+
+static const PinMap PinMap_LVDS_DISP_PIN[] = {
+ {P5_7 , VDC5_CH0, 1}, /* TXOUT0M */
+ {P5_6 , VDC5_CH0, 1}, /* TXOUT0P */
+ {P5_5 , VDC5_CH0, 1}, /* TXOUT1M */
+ {P5_4 , VDC5_CH0, 1}, /* TXOUT1P */
+ {P5_3 , VDC5_CH0, 1}, /* TXOUT2M */
+ {P5_2 , VDC5_CH0, 1}, /* TXOUT2P */
+ {P5_1 , VDC5_CH0, 1}, /* TXCLKOUTM */
+ {P5_0 , VDC5_CH0, 1}, /* TXCLKOUTP */
+ {NC , NC , 0}
+};
+
+static const IRQn_Type vdc5_irq_set_tbl[] = {
+ S0_VI_VSYNC0_IRQn,
+ S0_LO_VSYNC0_IRQn,
+ S0_VSYNCERR0_IRQn,
+ GR3_VLINE0_IRQn,
+ S0_VFIELD0_IRQn,
+ IV1_VBUFERR0_IRQn,
+ IV3_VBUFERR0_IRQn,
+ IV5_VBUFERR0_IRQn,
+ IV6_VBUFERR0_IRQn,
+ S0_WLINE0_IRQn,
+ S1_VI_VSYNC0_IRQn,
+ S1_LO_VSYNC0_IRQn,
+ S1_VSYNCERR0_IRQn,
+ S1_VFIELD0_IRQn,
+ IV2_VBUFERR0_IRQn,
+ IV4_VBUFERR0_IRQn,
+ S1_WLINE0_IRQn,
+ OIR_VI_VSYNC0_IRQn,
+ OIR_LO_VSYNC0_IRQn,
+ OIR_VSYNCERR0_IRQn,
+ OIR_VFIELD0_IRQn,
+ IV7_VBUFERR0_IRQn,
+ IV8_VBUFERR0_IRQn
+};
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void init_func (const uint32_t user_num);
+static void DRV_Graphics_Irq_Set(vdc5_int_type_t irq, uint32_t enable);
+
+/**************************************************************************//**
+ * @brief User-defined function within R_VDC5_Initialize
+ * @param[in] user_num : VDC5 channel
+ * @retval None
+******************************************************************************/
+static void init_func (const uint32_t user_num)
+{
+ uint32_t reg_data;
+ volatile uint8_t dummy_read;
+
+ if ((vdc5_channel_t)user_num == VDC5_CHANNEL_0) {
+
+ /* Standby control register 9 (STBCR9)
+ b1 ------0-; MSTP91 : 0 : Video display controller channel 0 & LVDS enable */
+ reg_data = (uint32_t)CPG.STBCR9 & (uint32_t)~STP91_BIT;
+ CPG.STBCR9 = (uint8_t)reg_data;
+ /* In order to reflect the change, a dummy read should be done. */
+ dummy_read = CPG.STBCR9;
+
+ /* Standby Request Register 2 (STBREQ2)
+ b5 --0-----; STBRQ25 : The standby request to VDC5 channel 0 is invalid. */
+ reg_data = (uint32_t)CPG.STBREQ2 & (uint32_t)~STBRQ25_BIT;
+ CPG.STBREQ2 = (uint8_t)reg_data;
+ /* Standby Acknowledge Register 2 (STBACK2)
+ b5 --*-----; STBAK25 : Standby acknowledgement from VDC5 channel 0. */
+ while (((uint32_t)CPG.STBACK2 & (uint32_t)STBAK25_BIT) != 0u) {
+ /* Wait for the STBAK25 to be cleared to 0. */
+ }
+
+ /* Standby control register 9 (STBCR9)
+ b0 -------0; MSTP90 : 0 : Video display controller channel 1 enable */
+ reg_data = (uint32_t)CPG.STBCR9 & (uint32_t)~(STP91_BIT|STP90_BIT);
+ CPG.STBCR9 = (uint8_t)reg_data;
+ /* In order to reflect the change, a dummy read should be done. */
+ dummy_read = CPG.STBCR9;
+
+ /* Standby Request Register 2 (STBREQ2)
+ b4 ---0----; STBRQ24 : The standby request to VDC5 channel 1 is invalid. */
+ reg_data = (uint32_t)CPG.STBREQ2 & (uint32_t)~STBRQ24_BIT;
+ CPG.STBREQ2 = (uint8_t)reg_data;
+ /* Standby Acknowledge Register 2 (STBACK2)
+ b4 ---*----; STBAK24 : Standby acknowledgement from VDC5 channel 1. */
+ while (((uint32_t)CPG.STBACK2 & (uint32_t)STBAK24_BIT) != 0u) {
+ /* Wait for the STBAK24 to be cleared to 0. */
+ }
+ }
+} /* End of function init_func() */
+
+/**************************************************************************//**
+ * @brief Interrupt service routine acquisition processing
+ *
+ * Description:<br>
+ * This function returns the function pointer to the specified interrupt service routine.
+ * @param[in] irq : VDC5 interrupt type
+ * @param[in] enable : VDC5 interrupt enable
+ * @retval None
+******************************************************************************/
+static void DRV_Graphics_Irq_Set(vdc5_int_type_t irq, uint32_t enable)
+{
+ vdc5_channel_t ch = VDC5_CHANNEL_0;
+ IRQn_Type IRQn;
+ IRQHandler handler;
+
+ IRQn = vdc5_irq_set_tbl[irq];
+ handler = R_VDC5_GetISR(ch, irq);
+
+ if (enable) {
+ InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler);
+ GIC_SetPriority(IRQn, 5);
+ GIC_EnableIRQ(IRQn);
+ } else {
+ GIC_DisableIRQ(IRQn);
+ }
+} /* End of function DRV_Graphics_Irq_Set() */
+
+/**************************************************************************//**
+ * @brief Interrupt callback setup
+ * This function performs the following processing:
+ * - Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.
+ * - Registers the specified interrupt callback function.
+ * - Disables the interrupt when the pointer to the corresponding interrupt callback function is not
+ * specified.
+ * @param[in] irq : VDC5 interrupt type
+ * @param[in] num : Interrupt line number
+ * @param[in] * callback : Interrupt callback function pointer
+ * @retval Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Irq_Handler_Set(
+ vdc5_int_type_t irq,
+ uint16_t num,
+ void (* callback)(vdc5_int_type_t) )
+{
+ vdc5_channel_t ch = VDC5_CHANNEL_0;
+ drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+ vdc5_error_t error;
+ vdc5_int_t interrupt;
+
+ if( callback == NULL ) {
+ DRV_Graphics_Irq_Set( irq, 0 );
+ } else {
+ DRV_Graphics_Irq_Set( irq, 1 );
+ }
+
+ /* Interrupt parameter */
+ interrupt.type = irq; /* Interrupt type */
+ interrupt.line_num = num ; /* Line number */
+
+ /* Interrupt parameter */
+ interrupt.callback = callback; /* Callback function pointer */
+ /* Set interrupt service routine */
+ error = R_VDC5_CallbackISR(ch, &interrupt);
+ if (error != VDC5_OK) {
+ drv_error = DRV_GRAPHICS_VDC5_ERR;
+ }
+ return drv_error ;
+} /* End of function DRV_Graphics_Irq_Handler_Set() */
+
+/**************************************************************************//**
+ * @brief LCD output port initialization processing
+ * @param[in] pin : Pin assign for LCD output
+ * @param[in] pin_count : Total number of pin assign
+ * @retval Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Lcd_Port_Init( PinName *pin, uint32_t pin_count )
+{
+ drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+ uint32_t count;
+
+ for( count = 0 ; count < pin_count ; count++ ) {
+#ifndef DEBUG_USING_GENMAI_BOARD
+ pinmap_peripheral(pin[count], PinMap_LCD_DISP_PIN);
+ pinmap_pinout(pin[count], PinMap_LCD_DISP_PIN);
+#else
+ /* debug code */
+ pinmap_peripheral(pin[count], PinMap_LCD_DISP_GENMAI_PC_MONI_PIN);
+ pinmap_pinout(pin[count], PinMap_LCD_DISP_GENMAI_PC_MONI_PIN);
+#endif /* DEBUG_USING_GENMAI_BOARD */
+ }
+ return drv_error;
+} /* End of function DRV_Graphics_Lcd_Port_Init() */
+
+/**************************************************************************//**
+ * @brief LVDS output port initialization processing
+ * @param[in] pin : Pin assign for LVDS output
+ * @param[in] pin_count : Total number of pin assign
+ * @retval Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Lvds_Port_Init( PinName *pin, uint32_t pin_count )
+{
+ drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+ uint32_t count;
+
+ for( count = 0 ; count < pin_count ; count++ ) {
+ pinmap_peripheral(pin[count], PinMap_LVDS_DISP_PIN);
+ pinmap_pinout(pin[count], PinMap_LVDS_DISP_PIN);
+ }
+ return drv_error;
+} /* End of function DRV_Graphics_Lvds_Port_Init() */
+
+/**************************************************************************//**
+ * @brief Digital video inpout port initialization processing
+ * @param[in] pin : Pin assign for digital video input port
+ * @param[in] pin_count : Total number of pin assign
+ * @retval Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Dvinput_Port_Init( PinName *pin, uint32_t pin_count )
+{
+ drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+ uint32_t count;
+
+ for( count = 0 ; count < pin_count ; count++ ) {
+ pinmap_peripheral(pin[count], PinMap_DV_INPUT_PIN);
+ pinmap_pinout(pin[count], PinMap_DV_INPUT_PIN);
+ }
+ return drv_error;
+} /* End of function DRV_Graphics_Dvinput_Port_Init() */
+
+/**************************************************************************//**
+ * @brief Graphics initialization processing
+ * @param[in] drv_lcd_config : LCD configuration
+ * @retval Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Init( drv_lcd_config_t * drv_lcd_config )
+{
+ drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+ vdc5_channel_t ch = VDC5_CHANNEL_0;
+ vdc5_error_t error;
+ vdc5_init_t init;
+ vdc5_lvds_t vdc5_lvds;
+ pll_parameter_t pll_parameter;
+ double InputClock = DEFAULT_INPUT_CLOCK;
+ double OutputClock = DEFAULT_OUTPUT_CLOCK;
+ uint32_t LvdsUsed = LVDS_IF_USE;
+
+ /* Initialization parameter */
+ init.panel_icksel = VDC5_PANEL_ICKSEL_LVDS; /* Panel clock select */
+ init.panel_dcdr = VDC5_PANEL_CLKDIV_1_1; /* Panel clock frequency division ratio */
+
+ if( drv_lcd_config != NULL ) {
+ InputClock = drv_lcd_config->intputClock;
+ OutputClock = drv_lcd_config->outputClock;
+
+ /* LVDS PLL Setting Calculation */
+ if( drv_lcd_config->lcd_type == DRV_LCD_TYPE_LVDS ) {
+ LvdsUsed = LVDS_IF_USE;
+ } else {
+ LvdsUsed = LVDS_IF_NOT_USE;
+ }
+ }
+ lvds_pll_calc( InputClock, OutputClock, LvdsUsed, &pll_parameter );
+
+ vdc5_lvds.lvds_in_clk_sel = VDC5_LVDS_INCLK_SEL_PERI; /* P1 */
+ vdc5_lvds.lvds_idiv_set = (vdc5_lvds_ndiv_t)pll_parameter.nidiv;
+ vdc5_lvds.lvdspll_tst = 16u;
+ vdc5_lvds.lvds_odiv_set = (vdc5_lvds_ndiv_t)pll_parameter.nodiv;
+ vdc5_lvds.lvdspll_tst = 16u;
+ vdc5_lvds.lvds_vdc_sel = ch;
+ vdc5_lvds.lvdspll_fd = pll_parameter.nfd;
+ vdc5_lvds.lvdspll_rd = pll_parameter.nrd;
+ vdc5_lvds.lvdspll_od = (vdc5_lvds_pll_nod_t)pll_parameter.nod;
+ init.lvds = &vdc5_lvds; /* LVDS parameter */
+
+ /* Initialize (Set module clock to VDC5) */
+ error = R_VDC5_Initialize( ch, &init, &init_func, (uint32_t)ch );
+ if (error != VDC5_OK) {
+ drv_error = DRV_GRAPHICS_VDC5_ERR;
+ }
+
+ if ( drv_error == DRV_GRAPHICS_OK ) {
+ vdc5_sync_ctrl_t sync_ctrl;
+
+ /* Sync signal control */
+ sync_ctrl.res_vs_sel = VDC5_ON; /* Vsync signal output select (free-running Vsync on/off control) */
+ /* Sync signal output and full-screen enable signal select */
+ sync_ctrl.res_vs_in_sel = VDC5_RES_VS_IN_SEL_SC0;
+ sync_ctrl.res_fv = drv_lcd_config->v_toatal_period-1; /* Free-running Vsync period setting */
+ sync_ctrl.res_fh = drv_lcd_config->h_toatal_period-1; /* Hsync period setting */
+ sync_ctrl.res_vsdly = (uint16_t)0u; /* Vsync signal delay control */
+ /* Full-screen enable control */
+ sync_ctrl.res_f.vs = (drv_lcd_config->v_back_porch);
+ sync_ctrl.res_f.vw = (drv_lcd_config->v_disp_widht);
+ sync_ctrl.res_f.hs = (drv_lcd_config->h_back_porch);
+ sync_ctrl.res_f.hw = (drv_lcd_config->h_disp_widht);
+ sync_ctrl.vsync_cpmpe = NULL; /* Vsync signal compensation */
+ /* Sync control */
+ error = R_VDC5_SyncControl( ch, &sync_ctrl );
+ if (error != VDC5_OK) {
+ drv_error = DRV_GRAPHICS_VDC5_ERR;
+ }
+ }
+
+ if ( drv_error == DRV_GRAPHICS_OK ) {
+ vdc5_output_t output;
+ vdc5_lcd_tcon_timing_t lcd_tcon_timing_VS;
+ vdc5_lcd_tcon_timing_t lcd_tcon_timing_VE;
+ vdc5_lcd_tcon_timing_t lcd_tcon_timing_HS;
+ vdc5_lcd_tcon_timing_t lcd_tcon_timing_HE;
+ vdc5_lcd_tcon_timing_t lcd_tcon_timing_DE;
+
+ /* Output parameter */
+ output.tcon_half = (drv_lcd_config->h_toatal_period-1)/2; /* TCON reference timing, 1/2fH timing */
+ output.tcon_offset = 0; /* TCON reference timing, offset Hsync signal timing */
+
+ /* LCD TCON timing setting */
+ if( drv_lcd_config->v_sync_port != DRV_LCD_TCON_PIN_NON ) {
+ lcd_tcon_timing_VS.tcon_hsvs = 0u;
+ lcd_tcon_timing_VS.tcon_hwvw = (drv_lcd_config->v_sync_width * 2u);
+ lcd_tcon_timing_VS.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
+ lcd_tcon_timing_VS.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
+ lcd_tcon_timing_VS.tcon_inv = (vdc5_sig_pol_t)drv_lcd_config->v_sync_port_polarity;
+ lcd_tcon_timing_VS.tcon_pin = (vdc5_lcd_tcon_pin_t)drv_lcd_config->v_sync_port;
+ lcd_tcon_timing_VS.outcnt_edge = VDC5_EDGE_FALLING;
+ output.outctrl[VDC5_LCD_TCONSIG_STVA_VS] = &lcd_tcon_timing_VS; /* STVA/VS: Vsync */
+ } else {
+ output.outctrl[VDC5_LCD_TCONSIG_STVA_VS] = NULL; /* STVA/VS: Vsync */
+ }
+
+ if( drv_lcd_config->h_sync_port != DRV_LCD_TCON_PIN_NON ) {
+ lcd_tcon_timing_HS.tcon_hsvs = 0u;
+ lcd_tcon_timing_HS.tcon_hwvw = drv_lcd_config->h_sync_width;
+ lcd_tcon_timing_HS.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
+ lcd_tcon_timing_HS.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
+ lcd_tcon_timing_HS.tcon_inv = (vdc5_sig_pol_t)drv_lcd_config->h_sync_port_polarity;
+ lcd_tcon_timing_HS.tcon_pin = (vdc5_lcd_tcon_pin_t)drv_lcd_config->h_sync_port;
+ lcd_tcon_timing_HS.outcnt_edge = VDC5_EDGE_FALLING;
+ output.outctrl[VDC5_LCD_TCONSIG_STH_SP_HS] = &lcd_tcon_timing_HS; /* STH/SP/HS: Hsync */
+ } else {
+ output.outctrl[VDC5_LCD_TCONSIG_STH_SP_HS] = NULL; /* STH/SP/HS: Hsync */
+ }
+
+ if( drv_lcd_config->de_port != DRV_LCD_TCON_PIN_NON ) {
+ lcd_tcon_timing_VE.tcon_hsvs = (drv_lcd_config->v_back_porch * 2u);
+ lcd_tcon_timing_VE.tcon_hwvw = (drv_lcd_config->v_disp_widht * 2u);
+ lcd_tcon_timing_VE.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
+ lcd_tcon_timing_VE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
+ lcd_tcon_timing_VE.tcon_inv = (vdc5_sig_pol_t)drv_lcd_config->de_port_polarity;
+ lcd_tcon_timing_VE.tcon_pin = VDC5_LCD_TCON_PIN_NON;
+ lcd_tcon_timing_VE.outcnt_edge = VDC5_EDGE_FALLING;
+ output.outctrl[VDC5_LCD_TCONSIG_STVB_VE] = &lcd_tcon_timing_VE; /* STVB/VE: Not used */
+
+ lcd_tcon_timing_HE.tcon_hsvs = drv_lcd_config->h_back_porch;
+ lcd_tcon_timing_HE.tcon_hwvw = drv_lcd_config->h_disp_widht;
+ lcd_tcon_timing_HE.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
+ lcd_tcon_timing_HE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
+ lcd_tcon_timing_HE.tcon_inv = (vdc5_sig_pol_t)drv_lcd_config->de_port_polarity;
+ lcd_tcon_timing_HE.tcon_pin = VDC5_LCD_TCON_PIN_NON;
+ lcd_tcon_timing_HE.outcnt_edge = VDC5_EDGE_FALLING;
+ output.outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = &lcd_tcon_timing_HE; /* STB/LP/HE: Not used */
+
+ lcd_tcon_timing_DE.tcon_hsvs = 0u;
+ lcd_tcon_timing_DE.tcon_hwvw = 0u;
+ lcd_tcon_timing_DE.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
+ lcd_tcon_timing_DE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
+ lcd_tcon_timing_DE.tcon_inv = (vdc5_sig_pol_t)drv_lcd_config->de_port_polarity;
+ lcd_tcon_timing_DE.tcon_pin = (vdc5_lcd_tcon_pin_t)drv_lcd_config->de_port;
+ lcd_tcon_timing_DE.outcnt_edge = VDC5_EDGE_FALLING;
+ output.outctrl[VDC5_LCD_TCONSIG_DE] = &lcd_tcon_timing_DE; /* DE */
+ } else {
+ output.outctrl[VDC5_LCD_TCONSIG_STVB_VE] = NULL; /* STVB/VE: Not used */
+ output.outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = NULL; /* STB/LP/HE: Not used */
+ output.outctrl[VDC5_LCD_TCONSIG_DE] = NULL; /* DE */
+ }
+
+ output.outctrl[VDC5_LCD_TCONSIG_CPV_GCK] = NULL;
+ output.outctrl[VDC5_LCD_TCONSIG_POLA] = NULL;
+ output.outctrl[VDC5_LCD_TCONSIG_POLB] = NULL;
+
+ output.outcnt_lcd_edge = (vdc5_edge_t)drv_lcd_config->lcd_edge; /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+ output.out_endian_on = VDC5_OFF; /* Bit endian change on/off control */
+ output.out_swap_on = VDC5_OFF; /* B/R signal swap on/off control */
+ output.out_format = (vdc5_lcd_outformat_t)drv_lcd_config->lcd_outformat; /* Output format select */
+ output.out_frq_sel = VDC5_LCD_PARALLEL_CLKFRQ_1; /* Clock frequency control */
+ output.out_dir_sel = VDC5_LCD_SERIAL_SCAN_FORWARD; /* Scan direction select */
+ output.out_phase = VDC5_LCD_SERIAL_CLKPHASE_0; /* Clock phase adjustment */
+ output.bg_color = (uint32_t)0x00000000u; /* Background color in 24-bit RGB color format */
+ /* Display output */
+ error = R_VDC5_DisplayOutput( ch, &output );
+ if (error != VDC5_OK) {
+ drv_error = DRV_GRAPHICS_VDC5_ERR;
+ }
+ }
+ return drv_error;
+} /* End of function DRV_Graphics_Init() */
+
+/**************************************************************************//**
+ * @brief Video initialization processing
+ * @param[in] drv_video_ext_in_config : Video configuration
+ * @retval Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Video_init( drv_video_input_sel_t drv_video_input_sel, drv_video_ext_in_config_t * drv_video_ext_in_config )
+{
+ drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+ vdc5_error_t error;
+ vdc5_input_t input;
+ vdc5_ext_in_sig_t ext_in_sig;
+ vdc5_sync_delay_t sync_delay;
+
+ input.inp_sel = (vdc5_input_sel_t)drv_video_input_sel; /* Input select */
+ input.inp_fh50 = (uint16_t)VSYNC_1_2_FH_TIMING; /* Vsync signal 1/2fH phase timing */
+ input.inp_fh25 = (uint16_t)VSYNC_1_4_FH_TIMING; /* Vsync signal 1/4fH phase timing */
+
+ if( drv_video_input_sel == DRV_INPUT_SEL_VDEC ) {
+ input.dly = NULL; /* Sync signal delay adjustment */
+ input.ext_sig = NULL; /* External input signal */
+ } else {
+ ext_in_sig.inp_format = (vdc5_extin_format_t)drv_video_ext_in_config->inp_format;
+ ext_in_sig.inp_pxd_edge = (vdc5_edge_t)drv_video_ext_in_config->inp_pxd_edge;
+ ext_in_sig.inp_vs_edge = (vdc5_edge_t)drv_video_ext_in_config->inp_vs_edge;
+ ext_in_sig.inp_hs_edge = (vdc5_edge_t)drv_video_ext_in_config->inp_hs_edge;
+ ext_in_sig.inp_endian_on = (vdc5_onoff_t)drv_video_ext_in_config->inp_endian_on;
+ ext_in_sig.inp_swap_on = (vdc5_onoff_t)drv_video_ext_in_config->inp_swap_on;
+ ext_in_sig.inp_vs_inv = (vdc5_sig_pol_t)drv_video_ext_in_config->inp_vs_inv;
+ ext_in_sig.inp_hs_inv = (vdc5_sig_pol_t)drv_video_ext_in_config->inp_hs_inv;
+ ext_in_sig.inp_h_edge_sel = (vdc5_extin_ref_hsync_t)drv_video_ext_in_config->inp_hs_edge;
+ ext_in_sig.inp_f525_625 = (vdc5_extin_input_line_t)drv_video_ext_in_config->inp_f525_625;
+ ext_in_sig.inp_h_pos = (vdc5_extin_h_pos_t)drv_video_ext_in_config->inp_h_pos;
+
+ sync_delay.inp_vs_dly_l = 0u;
+ sync_delay.inp_vs_dly = 16u;
+ sync_delay.inp_hs_dly = 16u;
+ sync_delay.inp_fld_dly = 16u;
+
+ input.dly = &sync_delay; /* Sync signal delay adjustment */
+ input.ext_sig = &ext_in_sig; /* External input signal */
+ }
+ /* Video input 0ch */
+ error = R_VDC5_VideoInput( VDC5_CHANNEL_0, &input );
+ if (error != VDC5_OK) {
+ drv_error = DRV_GRAPHICS_VDC5_ERR;
+ }
+
+ if( drv_video_input_sel == DRV_INPUT_SEL_VDEC ) {
+ if ( drv_error == DRV_GRAPHICS_OK ) {
+ /* Video input 1ch */
+ error = R_VDC5_VideoInput( VDC5_CHANNEL_1, &input );
+ if (error != VDC5_OK) {
+ drv_error = DRV_GRAPHICS_VDC5_ERR;
+ }
+ }
+ }
+ return drv_error;
+} /* End of function DRV_Video_Init() */
+
+/**************************************************************************//**
+ * @brief Start the graphics surface read process
+ * @param[in] layer_id : Graphics layer ID
+ * @retval drv_graphics_error_t
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Start ( drv_graphics_layer_t layer_id )
+{
+ drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+ vdc5_channel_t ch = VDC5_CHANNEL_0;
+ vdc5_error_t error;
+ vdc5_start_t start;
+ vdc5_gr_disp_sel_t gr_disp_sel;
+ vdc5_layer_id_t vdc5_layer_id;
+
+ switch( layer_id ) {
+ case DRV_GRAPHICS_LAYER_0:
+ vdc5_layer_id = VDC5_LAYER_ID_0_RD;
+ gr_disp_sel = VDC5_DISPSEL_CURRENT;
+ break;
+ case DRV_GRAPHICS_LAYER_1:
+ vdc5_layer_id = VDC5_LAYER_ID_1_RD;
+ gr_disp_sel = VDC5_DISPSEL_BLEND;
+ break;
+ case DRV_GRAPHICS_LAYER_2:
+ vdc5_layer_id = VDC5_LAYER_ID_2_RD;
+ gr_disp_sel = VDC5_DISPSEL_BLEND;
+ break;
+ case DRV_GRAPHICS_LAYER_3:
+ vdc5_layer_id = VDC5_LAYER_ID_3_RD;
+ gr_disp_sel = VDC5_DISPSEL_BLEND;
+ break;
+ default:
+ drv_error = DRV_GRAPHICS_LAYER_ERR;
+ break;
+ }
+
+ if( drv_error == DRV_GRAPHICS_OK ) {
+ /* Start process */
+ start.gr_disp_sel = &gr_disp_sel;
+ error = R_VDC5_StartProcess( ch, vdc5_layer_id, &start );
+ if (error != VDC5_OK) {
+ drv_error = DRV_GRAPHICS_VDC5_ERR;
+ }
+ }
+ return drv_error;
+} /* End of function DRV_Graphics_Start() */
+
+/**************************************************************************//**
+ * @brief Stop the graphics surface read process
+ * @param[in] layer_id : Graphics layer ID
+ * @retval Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Stop ( drv_graphics_layer_t layer_id )
+{
+ drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+ vdc5_channel_t ch = VDC5_CHANNEL_0;
+ vdc5_error_t error;
+ vdc5_layer_id_t vdc5_layer_id;
+
+ switch( layer_id ) {
+ case DRV_GRAPHICS_LAYER_0:
+ vdc5_layer_id = VDC5_LAYER_ID_0_RD;
+ break;
+ case DRV_GRAPHICS_LAYER_1:
+ vdc5_layer_id = VDC5_LAYER_ID_1_RD;
+ break;
+ case DRV_GRAPHICS_LAYER_2:
+ vdc5_layer_id = VDC5_LAYER_ID_2_RD;
+ break;
+ case DRV_GRAPHICS_LAYER_3:
+ vdc5_layer_id = VDC5_LAYER_ID_3_RD;
+ break;
+ default:
+ drv_error = DRV_GRAPHICS_LAYER_ERR;
+ break;
+ }
+
+ if( drv_error == DRV_GRAPHICS_OK ) {
+ /* Stop process */
+ error = R_VDC5_StopProcess ( ch, vdc5_layer_id );
+ if (error != VDC5_OK) {
+ drv_error = DRV_GRAPHICS_VDC5_ERR;
+ }
+ }
+ return drv_error;
+} /* End of function DRV_Graphics_Stop() */
+
+/**************************************************************************//**
+ * @brief Start the video surface write process
+ * @param[in] video_input_ch : Video input channel
+ * @retval Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Video_Start ( drv_video_input_channel_t video_input_ch )
+{
+ drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+ vdc5_channel_t ch = VDC5_CHANNEL_0;
+ vdc5_error_t error;
+ vdc5_start_t start;
+ vdc5_gr_disp_sel_t gr_disp_sel;
+ vdc5_layer_id_t vdc5_layer_id;
+
+ if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) {
+ vdc5_layer_id = VDC5_LAYER_ID_0_WR;
+ } else if ( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1 ) {
+ vdc5_layer_id = VDC5_LAYER_ID_1_WR;
+ } else {
+ drv_error = DRV_GRAPHICS_LAYER_ERR;
+ }
+
+ if( drv_error == DRV_GRAPHICS_OK ) {
+ /* Start process */
+ gr_disp_sel = VDC5_DISPSEL_CURRENT; /* CURRENT fixed for weave input mode */
+ start.gr_disp_sel = &gr_disp_sel;
+ error = R_VDC5_StartProcess( ch, vdc5_layer_id, &start );
+ if (error != VDC5_OK) {
+ drv_error = DRV_GRAPHICS_VDC5_ERR;
+ }
+ }
+ return drv_error;
+} /* End of function DRV_Video_Start() */
+
+/**************************************************************************//**
+ * @brief Stop the video surface write process
+ * @param[in] video_input_ch : Video input channel
+ * @retval Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Video_Stop ( drv_video_input_channel_t video_input_ch )
+{
+ drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+ vdc5_channel_t ch = VDC5_CHANNEL_0;
+ vdc5_error_t error;
+ vdc5_layer_id_t vdc5_layer_id;
+
+ switch (video_input_ch) {
+ case DRV_VIDEO_INPUT_CHANNEL_0:
+ vdc5_layer_id = VDC5_LAYER_ID_0_WR;
+ break;
+ case DRV_VIDEO_INPUT_CHANNEL_1:
+ vdc5_layer_id = VDC5_LAYER_ID_1_WR;
+ break;
+ default:
+ drv_error = DRV_GRAPHICS_LAYER_ERR;
+ break;
+ }
+
+ if( drv_error == DRV_GRAPHICS_OK ) {
+ /* Stop process */
+ error = R_VDC5_StopProcess ( ch, vdc5_layer_id );
+ if (error != VDC5_OK) {
+ drv_error = DRV_GRAPHICS_VDC5_ERR;
+ }
+ }
+ return drv_error;
+} /* End of function DRV_Video_Stop() */
+
+/**************************************************************************//**
+ * @brief Graphics surface read process setting
+ *
+ * Description:<br>
+ * This function supports the following 4 image format.
+ * YCbCr422, RGB565, RGB888, ARGB8888
+ * @param[in] layer_id : Graphics layer ID
+ * @param[in] framebuff : Base address of the frame buffer
+ * @param[in] fb_stride : Line offset address of the frame buffer
+ * @param[in] gr_format : Format of the frame buffer read signal
+ * @param[in] gr_rect : Graphics display area
+ * @retval Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Read_Setting (
+ drv_graphics_layer_t layer_id,
+ void * framebuff,
+ uint32_t fb_stride,
+ drv_graphics_format_t gr_format,
+ drv_wr_rd_swa_t wr_rd_swa,
+ drv_rect_t * gr_rect )
+{
+ drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+ vdc5_channel_t ch = VDC5_CHANNEL_0;
+ vdc5_error_t error;
+ vdc5_layer_id_t vdc5_layer_id;
+ vdc5_gr_format_t vdc5_gr_format;
+ vdc5_read_t read;
+
+ switch(layer_id) {
+ case DRV_GRAPHICS_LAYER_0:
+ vdc5_layer_id = VDC5_LAYER_ID_0_RD;
+ break;
+ case DRV_GRAPHICS_LAYER_1:
+ vdc5_layer_id = VDC5_LAYER_ID_1_RD;
+ break;
+ case DRV_GRAPHICS_LAYER_2:
+ vdc5_layer_id = VDC5_LAYER_ID_2_RD;
+ break;
+ case DRV_GRAPHICS_LAYER_3:
+ vdc5_layer_id = VDC5_LAYER_ID_3_RD;
+ break;
+ default:
+ drv_error = DRV_GRAPHICS_LAYER_ERR;
+ break;
+ }
+
+ if( drv_error == DRV_GRAPHICS_OK ) {
+ switch( gr_format ) {
+ case DRV_GRAPHICS_FORMAT_YCBCR422:
+ vdc5_gr_format = VDC5_GR_FORMAT_YCBCR422;
+ break;
+ case DRV_GRAPHICS_FORMAT_RGB565:
+ vdc5_gr_format = VDC5_GR_FORMAT_RGB565;
+ break;
+ case DRV_GRAPHICS_FORMAT_RGB888:
+ vdc5_gr_format = VDC5_GR_FORMAT_RGB888;
+ break;
+ case DRV_GRAPHICS_FORMAT_ARGB8888:
+ vdc5_gr_format = VDC5_GR_FORMAT_ARGB8888;
+ break;
+ default:
+ drv_error = DRV_GRAPHICS_FORMAT_ERR;
+ break;
+ }
+ }
+
+ if( drv_error == DRV_GRAPHICS_OK ) {
+ /* Read data parameter */
+ read.gr_ln_off_dir = VDC5_GR_LN_OFF_DIR_INC; /* Line offset address direction of the frame buffer */
+ read.gr_flm_sel = VDC5_GR_FLM_SEL_FLM_NUM; /* Selects a frame buffer address setting signal */
+ read.gr_imr_flm_inv = VDC5_OFF; /* Frame buffer number for distortion correction */
+ read.gr_bst_md = VDC5_BST_MD_32BYTE; /* Frame buffer burst transfer mode */
+ read.gr_base = framebuff; /* Frame buffer base address */
+ read.gr_ln_off = fb_stride; /* Frame buffer line offset address */
+
+ read.width_read_fb = NULL; /* Width of the image read from frame buffer */
+
+ read.adj_sel = VDC5_OFF; /* Measures to decrease the influence
+ by folding pixels/lines (on/off) */
+ read.gr_format = vdc5_gr_format; /* Format of the frame buffer read signal */
+ read.gr_ycc_swap = VDC5_GR_YCCSWAP_CBY0CRY1; /* Controls swapping of data read from buffer
+ in the YCbCr422 format */
+ read.gr_rdswa = (vdc5_wr_rd_swa_t)wr_rd_swa; /* Frame buffer swap setting */
+ /* Display area */
+ read.gr_grc.vs = gr_rect->vs;
+ read.gr_grc.vw = gr_rect->vw;
+ read.gr_grc.hs = gr_rect->hs;
+ read.gr_grc.hw = gr_rect->hw;
+
+ /* Read data control */
+ error = R_VDC5_ReadDataControl( ch, vdc5_layer_id, &read );
+ if (error != VDC5_OK) {
+ drv_error = DRV_GRAPHICS_VDC5_ERR;
+ }
+ }
+ return drv_error;
+} /* End of function DRV_Graphics_Read_Setting() */
+
+/**************************************************************************//**
+ * @brief Graphics surface read buffer change process
+ * @param[in] layer_id : Graphics layer ID
+ * @param[in] framebuff : Base address of the frame buffer
+ * @retval Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Read_Change (
+ drv_graphics_layer_t layer_id,
+ void * framebuff)
+{
+ drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+ vdc5_channel_t ch = VDC5_CHANNEL_0;
+ vdc5_error_t error;
+ vdc5_layer_id_t vdc5_layer_id;
+ vdc5_read_chg_t read_chg;
+
+ switch(layer_id) {
+ case DRV_GRAPHICS_LAYER_0:
+ vdc5_layer_id = VDC5_LAYER_ID_0_RD;
+ break;
+ case DRV_GRAPHICS_LAYER_1:
+ vdc5_layer_id = VDC5_LAYER_ID_1_RD;
+ break;
+ case DRV_GRAPHICS_LAYER_2:
+ vdc5_layer_id = VDC5_LAYER_ID_2_RD;
+ break;
+ case DRV_GRAPHICS_LAYER_3:
+ vdc5_layer_id = VDC5_LAYER_ID_3_RD;
+ break;
+ default:
+ drv_error = DRV_GRAPHICS_LAYER_ERR;
+ break;
+ }
+
+ if( drv_error == DRV_GRAPHICS_OK ) {
+ /* Read data parameter */
+ read_chg.width_read_fb = NULL; /* Width of the image read from frame buffer */
+ read_chg.gr_grc = NULL; /* Display area */
+ read_chg.gr_disp_sel = NULL; /* Graphics display mode */
+ read_chg.gr_base = framebuff; /* Frame buffer base address */
+
+ /* Change read process */
+ error = R_VDC5_ChangeReadProcess( ch, vdc5_layer_id, &read_chg );
+ if (error != VDC5_OK) {
+ drv_error = DRV_GRAPHICS_VDC5_ERR;
+ }
+ }
+ return drv_error;
+} /* End of function DRV_Graphics_Read_Change() */
+
+/**************************************************************************//**
+ * @brief Video surface write process setting
+ *
+ * Description:<br>
+ * This function set the video write process. Input form is weave
+ * (progressive) mode fixed.
+ * This function supports the following 3 image format.
+ * YCbCr422, RGB565, RGB888
+ * @param[in] video_input_ch : Video input channel
+ * @param[in] col_sys : Analog video signal color system
+ * @param[in] adc_vinsel : Video input pin
+ * @param[in] framebuff : Base address of the frame buffer
+ * @param[in] fb_stride [byte] : Line offset address of the frame buffer
+ * @param[in] video_format : Frame buffer video-signal writing format
+ * @param[in] wr_rd_swa : Frame buffer swap setting
+ * @param[in] video_write_size_vw [px]: output height
+ * @param[in] video_write_size_hw [px]: output width
+ * @retval Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Video_Write_Setting (
+ drv_video_input_channel_t video_input_ch,
+ drv_graphics_video_col_sys_t col_sys,
+ void * framebuff,
+ uint32_t fb_stride,
+ drv_video_format_t video_format,
+ drv_wr_rd_swa_t wr_rd_swa,
+ uint16_t video_write_buff_vw,
+ uint16_t video_write_buff_hw )
+{
+ drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+ vdc5_channel_t ch = VDC5_CHANNEL_0;
+ vdc5_error_t error;
+ vdc5_layer_id_t vdc5_layer_id;
+ vdc5_write_t write;
+ vdc5_scalingdown_rot_t * scldw_rot;
+ vdc5_res_md_t res_md;
+ drv_rect_t video_in_rect;
+ uint8_t * framebuffer_t;
+ uint8_t * framebuffer_b;
+
+ if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) {
+ GRAPHICS_VideoDecoderInit( VDEC_ADC_VINSEL_VIN1, VDEC_CHANNEL_0, (graphics_col_sys_t)col_sys );
+ } else if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1 ) {
+ GRAPHICS_VideoDecoderInit( VDEC_ADC_VINSEL_VIN1, VDEC_CHANNEL_1, (graphics_col_sys_t)col_sys );
+ } else {
+ drv_error = DRV_GRAPHICS_CHANNEL_ERR;
+ }
+
+ if( drv_error == DRV_GRAPHICS_OK ) {
+ if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) {
+ vdc5_layer_id = VDC5_LAYER_ID_0_WR;
+ } else if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1 ) {
+ vdc5_layer_id = VDC5_LAYER_ID_1_WR;
+ } else {
+ drv_error = DRV_GRAPHICS_CHANNEL_ERR;
+ }
+ }
+
+ if( drv_error == DRV_GRAPHICS_OK ) {
+ if( video_format == DRV_VIDEO_FORMAT_YCBCR422 ) {
+ res_md = VDC5_RES_MD_YCBCR422;
+ } else if( video_format == DRV_VIDEO_FORMAT_RGB888 ) {
+ res_md = VDC5_RES_MD_RGB888;
+ } else if( video_format == DRV_VIDEO_FORMAT_RGB565 ) {
+ res_md = VDC5_RES_MD_RGB565;
+ } else {
+ drv_error = DRV_GRAPHICS_FORMAT_ERR;
+ }
+ }
+
+ if( col_sys == DRV_COL_SYS_NTSC_358 || col_sys == DVV_COL_SYS_NTSC_443 || col_sys == DRV_COL_SYS_NTSC_443_60 ) {
+ video_in_rect.hs = IMGCAP_SIZE_NTSC_HS * 2;
+ video_in_rect.hw = IMGCAP_SIZE_NTSC_HW * 2;
+ video_in_rect.vs = IMGCAP_SIZE_NTSC_VS;
+ video_in_rect.vw = IMGCAP_SIZE_NTSC_VW;
+ } else {
+ video_in_rect.hs = IMGCAP_SIZE_PAL_HS * 2;
+ video_in_rect.hw = IMGCAP_SIZE_PAL_HW * 2;
+ video_in_rect.vs = IMGCAP_SIZE_PAL_VS;
+ video_in_rect.vw = IMGCAP_SIZE_PAL_VW;
+ }
+
+ if( drv_error == DRV_GRAPHICS_OK ) {
+ if( col_sys == DRV_COL_SYS_NTSC_358 || col_sys == DVV_COL_SYS_NTSC_443 || col_sys == DRV_COL_SYS_NTSC_443_60 ) {
+ if( (video_write_buff_vw / 2u) > video_in_rect.vw ) {
+ drv_error = DRV_GRAPHICS_VIDEO_NTSC_SIZE_ERR;
+ }
+ } else {
+ if( (video_write_buff_vw / 2u) > video_in_rect.vw ) {
+ drv_error = DRV_GRAPHICS_VIDEO_PAL_SIZE_ERR;
+ }
+ }
+ }
+
+ if( drv_error == DRV_GRAPHICS_OK ) {
+ if( video_write_buff_hw > 800 ) {
+ drv_error = DRV_GRAPHICS_PARAM_RANGE_ERR;
+ }
+ }
+
+ if( drv_error == DRV_GRAPHICS_OK ) {
+ /* Scaling-down and rotation parameter */
+ scldw_rot = &write.scalingdown_rot;
+ /* Image area to be captured */
+ scldw_rot->res.vs = (uint16_t)((uint32_t)video_in_rect.vs - 1u);
+ scldw_rot->res.vw = video_in_rect.vw;
+ scldw_rot->res.hs = video_in_rect.hs;
+ scldw_rot->res.hw = video_in_rect.hw;
+
+ /* Write data parameter */
+ framebuffer_t = framebuff;
+ framebuffer_b = &framebuffer_t[fb_stride];
+ scldw_rot->res_pfil_sel = VDC5_ON; /* Prefilter mode select for brightness signals (on/off) */
+ scldw_rot->res_out_vw = video_write_buff_vw / 2u; /* Number of valid lines in vertical direction
+ output by scaling-down control block */
+ scldw_rot->res_out_hw = video_write_buff_hw; /* Number of valid horizontal pixels
+ output by scaling-down control block */
+ scldw_rot->adj_sel = VDC5_ON; /* Measures to decrease the influence
+ by lack of last-input line (on/off) */
+ scldw_rot->res_ds_wr_md = VDC5_WR_MD_NORMAL; /* Frame buffer writing mode */
+ write.res_wrswa = (vdc5_wr_rd_swa_t)wr_rd_swa; /* Frame buffer swap setting */
+ write.res_md = res_md; /* Frame buffer video-signal writing format */
+ write.res_bst_md = VDC5_BST_MD_32BYTE; /* Transfer burst length for frame buffer */
+ write.res_inter = VDC5_RES_INTER_PROGRESSIVE; /* Field operating mode select */
+ write.res_fs_rate = VDC5_RES_FS_RATE_PER1; /* Writing rate */
+ write.res_fld_sel = VDC5_RES_FLD_SEL_TOP; /* Write field select */
+ write.res_dth_on = VDC5_ON; /* Dither correction on/off */
+ write.base = framebuff; /* Frame buffer base address */
+ write.ln_off = fb_stride * 2u; /* Frame buffer line offset address [byte] */
+ write.flm_num = (uint32_t)(1u - 1u); /* Number of frames of buffer (res_flm_num + 1) */
+ /* Frame buffer frame offset address */
+ write.flm_off = fb_stride * 2u * (uint32_t)scldw_rot->res_out_vw;
+ write.btm_base = framebuffer_b; /* Frame buffer base address for bottom */
+
+ /* Write data control */
+ error = R_VDC5_WriteDataControl( ch, vdc5_layer_id, &write );
+ if (error != VDC5_OK) {
+ drv_error = DRV_GRAPHICS_VDC5_ERR;
+ }
+ }
+ return drv_error;
+} /* End of function DRV_Video_Write_Setting() */
+
+/**************************************************************************//**
+ * @brief Video surface write process setting for digital input
+ *
+ * Description:<br>
+ * This function set the video write process for digital input.
+ * This function supports the following 3 image format.
+ * YCbCr422, RGB565, RGB888
+ * @param[in] framebuff : Base address of the frame buffer
+ * @param[in] fb_stride [byte] : Line offset address of the frame buffer
+ * @param[in] video_format : Frame buffer video-signal writing format
+ * @param[in] wr_rd_swa : Frame buffer swap setting
+ * @param[in] video_write_size_vw [px]: output height
+ * @param[in] video_write_size_hw [px]: output width
+ * @param[in] cap_area : Capture area
+ * @retval Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Video_Write_Setting_Digital (
+ void * framebuff,
+ uint32_t fb_stride,
+ drv_video_format_t video_format,
+ drv_wr_rd_swa_t wr_rd_swa,
+ uint16_t video_write_buff_vw,
+ uint16_t video_write_buff_hw,
+ drv_rect_t * cap_area )
+{
+ drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+ vdc5_channel_t ch = VDC5_CHANNEL_0;
+ vdc5_error_t error;
+ vdc5_layer_id_t vdc5_layer_id;
+ vdc5_write_t write;
+ vdc5_scalingdown_rot_t * scldw_rot;
+ vdc5_res_md_t res_md;
+
+ vdc5_layer_id = VDC5_LAYER_ID_0_WR;
+
+ if( drv_error == DRV_GRAPHICS_OK ) {
+ if( video_format == DRV_VIDEO_FORMAT_YCBCR422 ) {
+ res_md = VDC5_RES_MD_YCBCR422;
+ } else if( video_format == DRV_VIDEO_FORMAT_RGB888 ) {
+ res_md = VDC5_RES_MD_RGB888;
+ } else if( video_format == DRV_VIDEO_FORMAT_RGB565 ) {
+ res_md = VDC5_RES_MD_RGB565;
+ } else {
+ drv_error = DRV_GRAPHICS_FORMAT_ERR;
+ }
+ }
+
+ if( drv_error == DRV_GRAPHICS_OK ) {
+ /* Scaling-down and rotation parameter */
+ scldw_rot = &write.scalingdown_rot;
+ /* Image area to be captured */
+ scldw_rot->res.vs = (uint16_t)((uint32_t)cap_area->vs - 1u);
+ scldw_rot->res.vw = cap_area->vw;
+ scldw_rot->res.hs = cap_area->hs;
+ scldw_rot->res.hw = cap_area->hw;
+
+ /* Write data parameter */
+ scldw_rot->res_pfil_sel = VDC5_ON; /* Prefilter mode select for brightness signals (on/off) */
+ scldw_rot->res_out_vw = video_write_buff_vw ; /* Number of valid lines in vertical direction
+ output by scaling-down control block */
+ scldw_rot->res_out_hw = video_write_buff_hw; /* Number of valid horizontal pixels
+ output by scaling-down control block */
+ scldw_rot->adj_sel = VDC5_ON; /* Measures to decrease the influence
+ by lack of last-input line (on/off) */
+ scldw_rot->res_ds_wr_md = VDC5_WR_MD_NORMAL; /* Frame buffer writing mode */
+ write.res_wrswa = (vdc5_wr_rd_swa_t)wr_rd_swa; /* Frame buffer swap setting */
+ write.res_md = res_md; /* Frame buffer video-signal writing format */
+ write.res_bst_md = VDC5_BST_MD_32BYTE; /* Transfer burst length for frame buffer */
+ write.res_inter = VDC5_RES_INTER_PROGRESSIVE; /* Field operating mode select */
+ write.res_fs_rate = VDC5_RES_FS_RATE_PER1; /* Writing rate */
+ write.res_fld_sel = VDC5_RES_FLD_SEL_TOP; /* Write field select */
+ write.res_dth_on = VDC5_ON; /* Dither correction on/off */
+ write.base = framebuff; /* Frame buffer base address */
+ write.ln_off = fb_stride;
+ /* Frame buffer line offset address [byte] */
+ write.flm_num = (uint32_t)(1u - 1u); /* Number of frames of buffer (res_flm_num + 1) */
+ /* Frame buffer frame offset address */
+ write.flm_off = fb_stride * (uint32_t)scldw_rot->res_out_vw;
+ write.btm_base = NULL; /* Frame buffer base address for bottom */
+
+ /* Write data control */
+ error = R_VDC5_WriteDataControl( ch, vdc5_layer_id, &write );
+ if (error != VDC5_OK) {
+ drv_error = DRV_GRAPHICS_VDC5_ERR;
+ }
+ }
+ return drv_error;
+} /* End of function DRV_Video_Write_Setting_Digital() */
+
+/**************************************************************************//**
+ * @brief Video surface write buffer change process
+ * @param[in] video_input_ch : Video input channle
+ * @param[in] framebuff : Base address of the frame buffer
+ * @param[in] fb_stride : Line offset address of the frame buffer
+ * @retval Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Video_Write_Change (
+ drv_video_input_channel_t video_input_ch,
+ void * framebuff,
+ uint32_t fb_stride )
+{
+ drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+ uint8_t * framebuffer_t;
+ uint8_t * framebuffer_b;
+
+ framebuffer_t = (uint8_t *)((uint32_t)framebuff & ~0x1F);
+ framebuffer_b = &framebuffer_t[fb_stride];
+
+ if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) {
+ VDC50.SC0_SCL1_WR2 = (uint32_t)framebuffer_t;
+ VDC50.SC0_SCL1_WR8 = (uint32_t)framebuffer_b;
+ VDC50.SC0_SCL1_UPDATE = 0x10;
+ } else if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1 ) {
+ VDC50.SC1_SCL1_WR2 = (uint32_t)framebuffer_t;
+ VDC50.SC1_SCL1_WR8 = (uint32_t)framebuffer_b;
+ VDC50.SC1_SCL1_UPDATE = 0x10;
+ } else {
+ drv_error = DRV_GRAPHICS_CHANNEL_ERR;
+ }
+ return drv_error;
+} /* End of function DRV_Video_Write_Change() */
+
+/* End of file */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/gr_peach_vdc5.h Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,317 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file gr_peach_vdc5.h
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief Graphics driver wrapper function definitions in C
+******************************************************************************/
+
+#ifndef GR_PEACH_VDC5_H
+#define GR_PEACH_VDC5_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include <stdlib.h>
+
+#include "r_typedefs.h"
+#include "r_vdc5.h"
+#include "pinmap.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+#define VSYNC_1_2_FH_TIMING (858u) /* Vsync signal 1/2fH phase timing */
+#define VSYNC_1_4_FH_TIMING (429u) /* Vsync signal 1/4fH phase timing */
+#define DEFAULT_INPUT_CLOCK (66.67) /* P1 clock VDC5 */
+#define DEFAULT_OUTPUT_CLOCK (66.67) /* LVDS output clock */
+
+#define IMGCAP_SIZE_NTSC_HS (122u)
+#define IMGCAP_SIZE_NTSC_HW (720u)
+#define IMGCAP_SIZE_NTSC_VS (16u)
+#define IMGCAP_SIZE_NTSC_VW (240u)
+
+#define IMGCAP_SIZE_PAL_HS (132u)
+#define IMGCAP_SIZE_PAL_HW (720u)
+#define IMGCAP_SIZE_PAL_VS (19u)
+#define IMGCAP_SIZE_PAL_VW (280u)
+
+typedef void (*vdc5_irq_handler)(uint32_t int_sense);
+
+/* video channel select */
+typedef enum {
+ DRV_VIDEO_INPUT_CHANNEL_0 = 0, /* video input channel 0 */
+ DRV_VIDEO_INPUT_CHANNEL_1 /* video input channel 1 */
+} drv_video_input_channel_t;
+
+/* graphics layer select */
+typedef enum {
+ DRV_GRAPHICS_LAYER_0 = 0, /* graphics layer 0 */
+ DRV_GRAPHICS_LAYER_1, /* graphics layer 1 */
+ DRV_GRAPHICS_LAYER_2, /* graphics layer 2 */
+ DRV_GRAPHICS_LAYER_3 /* graphics layer 3 */
+} drv_graphics_layer_t;
+
+/* error codes */
+typedef enum {
+ DRV_GRAPHICS_OK = 0, /* Normal termination */
+ DRV_GRAPHICS_VDC5_ERR = -1, /* VDC5 error */
+ DRV_GRAPHICS_FORMAT_ERR = -2, /* Not support format */
+ DRV_GRAPHICS_LAYER_ERR = -3, /* Invalid layer ID error */
+ DRV_GRAPHICS_CHANNEL_ERR = -4, /* Invalid channel error */
+ DRV_GRAPHICS_VIDEO_NTSC_SIZE_ERR = -5, /* Video Write */
+ DRV_GRAPHICS_VIDEO_PAL_SIZE_ERR = -6, /* Video Write */
+ DRV_GRAPHICS_PARAM_RANGE_ERR = -7 /* Parameter range error */
+} drv_graphics_error_t;
+
+/* graphics layer format select */
+typedef enum {
+ DRV_GRAPHICS_FORMAT_YCBCR422 = 0, /* YCbCr422 */
+ DRV_GRAPHICS_FORMAT_RGB565, /* RGB565 */
+ DRV_GRAPHICS_FORMAT_RGB888, /* RGB888 */
+ DRV_GRAPHICS_FORMAT_ARGB8888 /* ARGB8888 */
+} drv_graphics_format_t;
+
+/* video writing format select */
+typedef enum {
+ DRV_VIDEO_FORMAT_YCBCR422 = 0, /* YCbCr422 */
+ DRV_VIDEO_FORMAT_RGB565, /* RGB565 */
+ DRV_VIDEO_FORMAT_RGB888 /* RGB888 */
+} drv_video_format_t;
+
+
+/* lcd tcon output pin select */
+typedef enum {
+ DRV_LCD_TCON_PIN_NON = -1, /* Not using output */
+ DRV_LCD_TCON_PIN_0, /* LCD_TCON0 */
+ DRV_LCD_TCON_PIN_1, /* LCD_TCON1 */
+ DRV_LCD_TCON_PIN_2 /* LCD_TCON2 */
+} drv_lcd_tcon_pin_t;
+
+/* lcd output format select */
+typedef enum {
+ DRV_LCD_OUTFORMAT_RGB888 = 0, /* RGB888 or LVDS */
+ DRV_LCD_OUTFORMAT_RGB666, /* RGB666 */
+ DRV_LCD_OUTFORMAT_RGB565 /* RGB565 */
+} drv_lcd_outformat_t;
+
+/* frame buffer swap setting */
+typedef enum {
+ DRV_WR_RD_WRSWA_NON = 0, /* Not swapped: 1-2-3-4-5-6-7-8 */
+ DRV_WR_RD_WRSWA_8BIT, /* Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */
+ DRV_WR_RD_WRSWA_16BIT, /* Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */
+ DRV_WR_RD_WRSWA_16_8BIT, /* Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */
+ DRV_WR_RD_WRSWA_32BIT, /* Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */
+ DRV_WR_RD_WRSWA_32_8BIT, /* Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */
+ DRV_WR_RD_WRSWA_32_16BIT, /* Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */
+ DRV_WR_RD_WRSWA_32_16_8BIT, /* Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */
+} drv_wr_rd_swa_t;
+
+/* edge of a signal */
+typedef enum {
+ DRV_EDGE_RISING = 0, /* Rising edge */
+ DRV_EDGE_FALLING = 1 /* Falling edge */
+} drv_edge_t;
+
+/* lcd type */
+typedef enum {
+ DRV_LCD_TYPE_LVDS = 0, /* LVDS signal control */
+ DRV_LCD_TYPE_PARALLEL_RGB /* RGB parallel signal control */
+} drv_lcd_type_t;
+
+/* Polarity of a signal */
+typedef enum {
+ DRV_SIG_POL_NOT_INVERTED = 0, /* Not inverted */
+ DRV_SIG_POL_INVERTED /* Inverted */
+} drv_sig_pol_t;
+
+/* Video color system */
+typedef enum {
+ DRV_COL_SYS_NTSC_358 = 0, /* NTSC-3.58 */
+ DVV_COL_SYS_NTSC_443 = 1, /* NTSC-4.43 */
+ DRV_COL_SYS_PAL_443 = 2, /* PAL-4.43 */
+ DRV_COL_SYS_PAL_M = 3, /* PAL-M */
+ DRV_COL_SYS_PAL_N = 4, /* PAL-N */
+ DRV_COL_SYS_SECAM = 5, /* SECAM */
+ DRV_COL_SYS_NTSC_443_60 = 6, /* NTSC-4.43 (60Hz) */
+ DRV_COL_SYS_PAL_60 = 7, /* PAL-60 */
+} drv_graphics_video_col_sys_t;
+
+/* External Input select */
+typedef enum {
+ DRV_INPUT_SEL_VDEC = 0, /*!< Video decoder output signals */
+ DRV_INPUT_SEL_EXT = 1 /*!< Signals supplied via the external input pins */
+} drv_video_input_sel_t;
+
+/* External input format select */
+typedef enum {
+ DRV_VIDEO_EXTIN_FORMAT_RGB888 = 0, /*!< RGB888 Not support */
+ DRV_VIDEO_EXTIN_FORMAT_RGB666, /*!< RGB666 */
+ DRV_VIDEO_EXTIN_FORMAT_RGB565, /*!< RGB565 */
+ DRV_VIDEO_EXTIN_FORMAT_BT656, /*!< BT6556 */
+ DRV_VIDEO_EXTIN_FORMAT_BT601, /*!< BT6501 */
+ DRV_VIDEO_EXTIN_FORMAT_YCBCR422, /*!< YCbCr422 */
+ DRV_VIDEO_EXTIN_FORMAT_YCBCR444, /*!< YCbCr444 Not support */
+} drv_video_extin_format_t;
+
+/* On/off */
+typedef enum {
+ DRV_OFF = 0, /*!< Off */
+ DRV_ON = 1 /*!< On */
+} drv_onoff_t;
+
+/* Number of lines for BT.656 external input */
+typedef enum {
+ DRV_EXTIN_LINE_525 = 0, /*!< 525 lines */
+ DRV_EXTIN_LINE_625 = 1 /*!< 625 lines */
+} drv_extin_input_line_t;
+
+/* Y/Cb/Y/Cr data string start timing */
+typedef enum {
+ DRV_EXTIN_H_POS_CBYCRY = 0, /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */
+ DRV_EXTIN_H_POS_YCRYCB, /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */
+ DRV_EXTIN_H_POS_CRYCBY, /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */
+ DRV_EXTIN_H_POS_YCBYCR, /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */
+} drv_extin_h_pos_t;
+
+/* The relative position within the graphics display area */
+typedef struct {
+ uint16_t vs; /* Vertical start pos */
+ uint16_t vw; /* Vertical width (height) */
+ uint16_t hs; /* Horizontal start pos */
+ uint16_t hw; /* Horizontal width */
+} drv_rect_t;
+
+/* lcd configuration */
+typedef struct {
+ drv_lcd_type_t lcd_type; /* LVDS or Pararel RGB */
+ double intputClock; /* P1 clk [MHz] ex. 66.67 */
+ double outputClock; /* LCD clk [MHz] ex. 33.33 */
+
+ drv_lcd_outformat_t lcd_outformat; /* Output format select */
+ drv_edge_t lcd_edge; /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+
+ uint16_t h_toatal_period; /* Free-running Hsync period */
+ uint16_t v_toatal_period; /* Free-running Vsync period */
+ uint16_t h_disp_widht; /* LCD display area size, horizontal width */
+ uint16_t v_disp_widht; /* LCD display area size, vertical width */
+ uint16_t h_back_porch; /* LCD display horizontal back porch period */
+ uint16_t v_back_porch; /* LCD display vertical back porch period */
+
+ drv_lcd_tcon_pin_t h_sync_port; /* TCONn or Not use(-1) */
+ drv_sig_pol_t h_sync_port_polarity; /* Polarity inversion control of signal */
+ uint16_t h_sync_width; /* Hsync width */
+
+ drv_lcd_tcon_pin_t v_sync_port; /* TCONn or Not use(-1) */
+ drv_sig_pol_t v_sync_port_polarity; /* Polarity inversion control of signal */
+ uint16_t v_sync_width; /* Vsync width */
+
+ drv_lcd_tcon_pin_t de_port; /* TCONn or Not use(-1) */
+ drv_sig_pol_t de_port_polarity; /* Polarity inversion control of signal */
+
+} drv_lcd_config_t;
+
+/* Digital video input configuration */
+typedef struct {
+ drv_video_extin_format_t inp_format; /*!< External Input Format Select */
+ drv_edge_t inp_pxd_edge; /*!< Clock Edge Select for Capturing External Input Video Image */
+ drv_edge_t inp_vs_edge; /*!< Clock Edge Select for Capturing External Input Vsync Signal */
+ drv_edge_t inp_hs_edge; /*!< Clock Edge Select for Capturing External Input Hsync Signal */
+ drv_onoff_t inp_endian_on; /*!< External Input B/R Signal Swap On/Off Control */
+ drv_onoff_t inp_swap_on; /*!< External Input Bit Endian Change On/Off Control */
+ drv_sig_pol_t inp_vs_inv; /*!< External Input Vsync Signal DV_VSYNC Inversion Control */
+ drv_sig_pol_t inp_hs_inv; /*!< External Input Hsync Signal DV_HSYNC Inversion Control */
+ drv_extin_input_line_t inp_f525_625; /*!< Number of lines for BT.656 external input */
+ drv_extin_h_pos_t inp_h_pos; /*!< Y/Cb/Y/Cr data string start timing to Hsync reference */
+} drv_video_ext_in_config_t;
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Init( drv_lcd_config_t * drv_lcd_config );
+drv_graphics_error_t DRV_Graphics_Video_init( drv_video_input_sel_t drv_video_input_sel, drv_video_ext_in_config_t * drv_video_ext_in_config );
+
+drv_graphics_error_t DRV_Graphics_Lcd_Port_Init( PinName *pin, uint32_t pin_count );
+drv_graphics_error_t DRV_Graphics_Lvds_Port_Init( PinName *pin, uint32_t pin_count );
+drv_graphics_error_t DRV_Graphics_Dvinput_Port_Init( PinName *pin, uint32_t pin_count );
+
+drv_graphics_error_t DRV_Graphics_Irq_Handler_Set( vdc5_int_type_t irq, uint16_t num, void (* callback)(vdc5_int_type_t) );
+
+drv_graphics_error_t DRV_Graphics_Start ( drv_graphics_layer_t layer_id );
+drv_graphics_error_t DRV_Graphics_Stop ( drv_graphics_layer_t layer_id );
+drv_graphics_error_t DRV_Video_Start ( drv_video_input_channel_t video_input_ch );
+drv_graphics_error_t DRV_Video_Stop ( drv_video_input_channel_t video_input_ch );
+
+drv_graphics_error_t DRV_Graphics_Read_Setting (
+ drv_graphics_layer_t layer_id,
+ void * framebuff,
+ uint32_t fb_stride,
+ drv_graphics_format_t gr_format,
+ drv_wr_rd_swa_t wr_rd_swa,
+ drv_rect_t * gr_rect );
+
+drv_graphics_error_t DRV_Graphics_Read_Change (
+ drv_graphics_layer_t layer_id,
+ void * framebuff);
+
+drv_graphics_error_t DRV_Video_Write_Setting (
+ drv_video_input_channel_t video_input_ch,
+ drv_graphics_video_col_sys_t col_sys,
+ void * framebuff,
+ uint32_t fb_stride,
+ drv_video_format_t video_format,
+ drv_wr_rd_swa_t wr_rd_swa,
+ uint16_t video_write_buff_vw,
+ uint16_t video_write_buff_hw );
+
+drv_graphics_error_t DRV_Video_Write_Setting_Digital (
+ void * framebuff,
+ uint32_t fb_stride,
+ drv_video_format_t video_format,
+ drv_wr_rd_swa_t wr_rd_swa,
+ uint16_t video_write_buff_vw,
+ uint16_t video_write_buff_hw,
+ drv_rect_t * cap_area );
+
+drv_graphics_error_t DRV_Video_Write_Change (
+ drv_video_input_channel_t video_input_ch,
+ void * framebuff,
+ uint32_t fb_stride );
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* GR_PEACH_VDC5_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/inc/lcd_analog_rgb.h Fri Jun 26 02:17:53 2015 +0000 @@ -0,0 +1,134 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/**************************************************************************//** +* @file lcd_analog_rgb.h +* @version 1.00 +* $Rev: 199 $ +* $Date:: 2014-05-23 16:33:52 +0900#$ +* @brief LCD panel definition header +******************************************************************************/ + +#ifndef LCD_ANALOG_RGB_H +#define LCD_ANALOG_RGB_H + +/****************************************************************************** +Includes <System Includes> , "Project Includes" +******************************************************************************/ +#include <stdlib.h> + +#include "r_typedefs.h" + +#include "r_vdc5.h" + + +/****************************************************************************** +Macro definitions +******************************************************************************/ +/* SVGA signal 800x600 + Pixel clock frequency: 40.0 MHz + Refresh rate: 60.3 Hz + Polarity of horizontal sync pulse: Positive + Polarity of vertical sync pulse: Positive +*/ +#define LCD_SVGA_H_VISIBLE_AREA (800u) /* Horizontal visible area [pixel] */ +#define LCD_SVGA_H_FRONT_PORCH (40u) /* Horizontal front porch [pixel] */ +#define LCD_SVGA_H_SYNC_WIDTH (128u) /* Horizontal sync pulse width [pixel] */ +#define LCD_SVGA_H_BACK_PORCH (88u) /* Horizontal back porch [pixel] */ +/* Horizontal total (one line) [pixel] */ +#define LCD_SVGA_H_TOTAL (LCD_SVGA_H_VISIBLE_AREA +\ + LCD_SVGA_H_FRONT_PORCH +\ + LCD_SVGA_H_SYNC_WIDTH +\ + LCD_SVGA_H_BACK_PORCH) +#define LCD_SVGA_H_POLARITY (VDC5_SIG_POL_NOT_INVERTED) /* Polarity of horizontal sync pulse */ + +#define LCD_SVGA_V_VISIBLE_AREA (600u) /* Vertical visible area [line] */ +#define LCD_SVGA_V_FRONT_PORCH (1u) /* Vertical front porch [line] */ +#define LCD_SVGA_V_SYNC_WIDTH (4u) /* Vertical sync pulse width [line] */ +#define LCD_SVGA_V_BACK_PORCH (23u) /* Vertical back porch [line] */ +/* Vertical total (one frame) [line] */ +#define LCD_SVGA_V_TOTAL (LCD_SVGA_V_VISIBLE_AREA +\ + LCD_SVGA_V_FRONT_PORCH +\ + LCD_SVGA_V_SYNC_WIDTH +\ + LCD_SVGA_V_BACK_PORCH) +#define LCD_SVGA_V_POLARITY (VDC5_SIG_POL_NOT_INVERTED) /* Polarity of vertical sync pulse */ + + +/* XGA signal 1024x768 + Pixel clock frequency: 65.0 MHz + Refresh rate: 60.0 Hz + Polarity of horizontal sync pulse: Negative + Polarity of vertical sync pulse: Negative +*/ +#define LCD_XGA_H_VISIBLE_AREA (1024u) /* Horizontal visible area [pixel] */ +#define LCD_XGA_H_FRONT_PORCH (24u) /* Horizontal front porch [pixel] */ +#define LCD_XGA_H_SYNC_WIDTH (136u) /* Horizontal sync pulse width [pixel] */ +#define LCD_XGA_H_BACK_PORCH (160u) /* Horizontal back porch [pixel] */ +/* Horizontal total (one line) [pixel] */ +#define LCD_XGA_H_TOTAL (LCD_XGA_H_VISIBLE_AREA +\ + LCD_XGA_H_FRONT_PORCH +\ + LCD_XGA_H_SYNC_WIDTH +\ + LCD_XGA_H_BACK_PORCH) +#define LCD_XGA_H_POLARITY (VDC5_SIG_POL_INVERTED) /* Polarity of horizontal sync pulse */ + +#define LCD_XGA_V_VISIBLE_AREA (768u) /* Vertical visible area [line] */ +#define LCD_XGA_V_FRONT_PORCH (3u) /* Vertical front porch [line] */ +#define LCD_XGA_V_SYNC_WIDTH (6u) /* Vertical sync pulse width [line] */ +#define LCD_XGA_V_BACK_PORCH (29u) /* Vertical back porch [line] */ +/* Vertical total (one frame) [line] */ +#define LCD_XGA_V_TOTAL (LCD_XGA_V_VISIBLE_AREA +\ + LCD_XGA_V_FRONT_PORCH +\ + LCD_XGA_V_SYNC_WIDTH +\ + LCD_XGA_V_BACK_PORCH) +#define LCD_XGA_V_POLARITY (VDC5_SIG_POL_INVERTED) /* Polarity of vertical sync pulse */ + + +/* VGA signal 640x480 + Pixel clock frequency: 25.175 MHz + Refresh rate: 59.94 Hz + Polarity of horizontal sync pulse: Negative + Polarity of vertical sync pulse: Negative +*/ +#define LCD_VGA_H_VISIBLE_AREA (640u) /* Horizontal visible area [pixel] */ +#define LCD_VGA_H_FRONT_PORCH (16u) /* Horizontal front porch [pixel] */ +#define LCD_VGA_H_SYNC_WIDTH (96u) /* Horizontal sync pulse width [pixel] */ +#define LCD_VGA_H_BACK_PORCH (48u) /* Horizontal back porch [pixel] */ +/* Horizontal total (one line) [pixel] */ +#define LCD_VGA_H_TOTAL (LCD_VGA_H_VISIBLE_AREA +\ + LCD_VGA_H_FRONT_PORCH +\ + LCD_VGA_H_SYNC_WIDTH +\ + LCD_VGA_H_BACK_PORCH) +#define LCD_VGA_H_POLARITY (VDC5_SIG_POL_INVERTED) /* Polarity of horizontal sync pulse */ + +#define LCD_VGA_V_VISIBLE_AREA (480u) /* Vertical visible area [line] */ +#define LCD_VGA_V_FRONT_PORCH (10u) /* Vertical front porch [line] */ +#define LCD_VGA_V_SYNC_WIDTH (2u) /* Vertical sync pulse width [line] */ +#define LCD_VGA_V_BACK_PORCH (33u) /* Vertical back porch [line] */ +/* Vertical total (one frame) [line] */ +#define LCD_VGA_V_TOTAL (LCD_VGA_V_VISIBLE_AREA +\ + LCD_VGA_V_FRONT_PORCH +\ + LCD_VGA_V_SYNC_WIDTH +\ + LCD_VGA_V_BACK_PORCH) +#define LCD_VGA_V_POLARITY (VDC5_SIG_POL_INVERTED) /* Polarity of vertical sync pulse */ + + +#endif /* LCD_ANALOG_RGB_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/inc/lcd_analog_rgb_ch0.h Fri Jun 26 02:17:53 2015 +0000 @@ -0,0 +1,95 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/**************************************************************************//** +* @file lcd_analog_rgb_ch0.h +* @version 1.00 +* $Rev: 199 $ +* $Date:: 2014-05-23 16:33:52 +0900#$ +* @brief LCD panel for vdc5 channel 0 definition header +******************************************************************************/ + +#ifndef LCD_ANALOG_RGB_CH0_H +#define LCD_ANALOG_RGB_CH0_H + +#ifndef LCD_PANEL_H +#error Do not include this file directly! +#else +/****************************************************************************** +Includes <System Includes> , "Project Includes" +******************************************************************************/ +#include <stdlib.h> + +#include "r_typedefs.h" + +#include "r_vdc5.h" + +#include "lcd_analog_rgb.h" + + +/****************************************************************************** +Macro definitions +******************************************************************************/ +/* Option board (part number: RTK7721000B00000BR) + ADV7123 (Video DAC), U8 + Analog RGB D-sub15 (RGB888), J15 */ +#define LCD_CH0_S_HSYNC (0u) /* Hsync start position */ +#define LCD_CH0_W_HSYNC (LCD_SVGA_H_SYNC_WIDTH) /* Hsync width */ +#define LCD_CH0_POL_HSYNC (LCD_SVGA_H_POLARITY) /* Polarity of Hsync pulse */ +/* LCD display area size, horizontal start position */ +#define LCD_CH0_DISP_HS (LCD_SVGA_H_SYNC_WIDTH + LCD_SVGA_H_BACK_PORCH) +#define LCD_CH0_DISP_HW (LCD_SVGA_H_VISIBLE_AREA) /* LCD display area size, horizontal width */ + +/* Vsync start position */ +#define LCD_CH0_S_VSYNC (LCD_SVGA_V_BACK_PORCH + LCD_SVGA_V_VISIBLE_AREA + LCD_SVGA_V_FRONT_PORCH) +#define LCD_CH0_W_VSYNC (LCD_SVGA_V_SYNC_WIDTH) /* Vsync width */ +#define LCD_CH0_POL_VSYNC (LCD_SVGA_V_POLARITY) /* Polarity of Vsync pulse */ +#define LCD_CH0_DISP_VS (LCD_SVGA_V_BACK_PORCH) /* LCD display area size, vertical start position */ +#define LCD_CH0_DISP_VW (LCD_SVGA_V_VISIBLE_AREA) /* LCD display area size, height (vertical width) */ + +#define LCD_CH0_SIG_FV (LCD_SVGA_V_TOTAL - 1u) /* Free-running Vsync period */ +#define LCD_CH0_SIG_FH (LCD_SVGA_H_TOTAL - 1u) /* Hsync period */ +/* Pixel data is latched in the rising edge of pixel clock on ADV7123. + Therefore, pixel data should be output from VDC5 at the falling edge of the clock. */ +#define LCD_CH0_OUT_EDGE VDC5_EDGE_FALLING /* Output phase control of LCD_DATA[23:0] signal */ +#define LCD_CH0_OUT_FORMAT VDC5_LCD_OUTFORMAT_RGB888 /* LCD output format select */ + +#define LCD_CH0_PANEL_CLK VDC5_PANEL_ICKSEL_LVDS /* Panel clock select */ +#define LCD_CH0_PANEL_CLK_DIV VDC5_PANEL_CLKDIV_1_1 /* Panel clock frequency division ratio */ + +#define LCD_CH0_TCON_HALF (LCD_CH0_SIG_FH / 2u) /* TCON reference timing, 1/2fH timing */ +#define LCD_CH0_TCON_OFFSET (0u) /* TCON reference timing, offset Hsync signal timing */ + + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Exported global functions (to be accessed by other files) +******************************************************************************/ +void GRAPHICS_SetLcdPanel_Ch0(void); +void GRAPHICS_SetLcdTconSettings_Ch0(const vdc5_lcd_tcon_timing_t * * const outctrl); + + +#endif /* LCD_PANEL_H not defined */ +#endif /* LCD_ANALOG_RGB_CH0_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/inc/lcd_analog_rgb_ch1.h Fri Jun 26 02:17:53 2015 +0000 @@ -0,0 +1,95 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/**************************************************************************//** +* @file lcd_analog_rgb_ch1.h +* @version 1.00 +* $Rev: 199 $ +* $Date:: 2014-05-23 16:33:52 +0900#$ +* @brief LCD panel for vdc5 channel 1 definition header +******************************************************************************/ + +#ifndef LCD_ANALOG_RGB_CH1_H +#define LCD_ANALOG_RGB_CH1_H + +#ifndef LCD_PANEL_H +#error Do not include this file directly! +#else +/****************************************************************************** +Includes <System Includes> , "Project Includes" +******************************************************************************/ +#include <stdlib.h> + +#include "r_typedefs.h" + +#include "r_vdc5.h" + +#include "lcd_analog_rgb.h" + + +/****************************************************************************** +Macro definitions +******************************************************************************/ +/* Option board (part number: RTK7721000B00000BR) + ADV7123 (Video DAC), U10 + Analog RGB D-sub15 (RGB888), J16 */ +#define LCD_CH1_S_HSYNC (0u) /* Hsync start position */ +#define LCD_CH1_W_HSYNC (LCD_SVGA_H_SYNC_WIDTH) /* Hsync width */ +#define LCD_CH1_POL_HSYNC (LCD_SVGA_H_POLARITY) /* Polarity of Hsync pulse */ +/* LCD display area size, horizontal start position */ +#define LCD_CH1_DISP_HS (LCD_SVGA_H_SYNC_WIDTH + LCD_SVGA_H_BACK_PORCH) +#define LCD_CH1_DISP_HW (LCD_SVGA_H_VISIBLE_AREA) /* LCD display area size, horizontal width */ + +/* Vsync start position */ +#define LCD_CH1_S_VSYNC (LCD_SVGA_V_BACK_PORCH + LCD_SVGA_V_VISIBLE_AREA + LCD_SVGA_V_FRONT_PORCH) +#define LCD_CH1_W_VSYNC (LCD_SVGA_V_SYNC_WIDTH) /* Vsync width */ +#define LCD_CH1_POL_VSYNC (LCD_SVGA_V_POLARITY) /* Polarity of Vsync pulse */ +#define LCD_CH1_DISP_VS (LCD_SVGA_V_BACK_PORCH) /* LCD display area size, vertical start position */ +#define LCD_CH1_DISP_VW (LCD_SVGA_V_VISIBLE_AREA) /* LCD display area size, height (vertical width) */ + +#define LCD_CH1_SIG_FV (LCD_SVGA_V_TOTAL - 1u) /* Free-running Vsync period */ +#define LCD_CH1_SIG_FH (LCD_SVGA_H_TOTAL - 1u) /* Hsync period */ +/* Pixel data is latched in the rising edge of pixel clock on ADV7123. + Therefore, pixel data should be output from VDC5 at the falling edge of the clock. */ +#define LCD_CH1_OUT_EDGE VDC5_EDGE_FALLING /* Output phase control of LCD_DATA[23:0] signal */ +#define LCD_CH1_OUT_FORMAT VDC5_LCD_OUTFORMAT_RGB888 /* LCD output format select */ + +#define LCD_CH1_PANEL_CLK VDC5_PANEL_ICKSEL_LVDS /* Panel clock select */ +#define LCD_CH1_PANEL_CLK_DIV VDC5_PANEL_CLKDIV_1_1 /* Panel clock frequency division ratio */ + +#define LCD_CH1_TCON_HALF (LCD_CH1_SIG_FH / 2u) /* TCON reference timing, 1/2fH timing */ +#define LCD_CH1_TCON_OFFSET (0u) /* TCON reference timing, offset Hsync signal timing */ + + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Exported global functions (to be accessed by other files) +******************************************************************************/ +void GRAPHICS_SetLcdPanel_Ch1(void); +void GRAPHICS_SetLcdTconSettings_Ch1(const vdc5_lcd_tcon_timing_t * * const outctrl); + + +#endif /* LCD_PANEL_H not defined */ +#endif /* LCD_ANALOG_RGB_CH1_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/inc/lcd_gr_peach_ch0.h Fri Jun 26 02:17:53 2015 +0000 @@ -0,0 +1,81 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/**************************************************************************//** +* @file lcd_gr_peach_ch0.h +* @version 1.00 +* $Rev: 199 $ +* $Date:: 2014-05-23 16:33:52 +0900#$ +* @brief LCD panel for vdc5 channel 0 definition header +******************************************************************************/ + +#ifndef LCD_GR_PEACH_CH0_H +#define LCD_GR_PEACH_CH0_H + +#ifndef LCD_PANEL_H +#error Do not include this file directly! +#else +/****************************************************************************** +Includes <System Includes> , "Project Includes" +******************************************************************************/ +#include <stdlib.h> + +#include "r_typedefs.h" + +#include "r_vdc5.h" + + +/****************************************************************************** +Macro definitions +******************************************************************************/ +/* Not support */ +#define LCD_CH0_DISP_HS (128u) /* LCD display area size, horizontal start position */ +#define LCD_CH0_DISP_HW (800u) /* LCD display area size, horizontal width */ +#define LCD_CH0_DISP_VS (10u) /* LCD display area size, vertical start position */ +#define LCD_CH0_DISP_VW (480u) /* LCD display area size, height (vertical width) */ +#define LCD_CH0_SIG_FV (525u - 1u) /* Free-running Vsync period */ +#define LCD_CH0_SIG_FH (1056u - 1u) /* Hsync period */ +/* Pixel data is latched in the falling edge of pixel clock. + Therefore, pixel data should be output from VDC5 at the rising edge of the clock. */ +#define LCD_CH0_OUT_EDGE VDC5_EDGE_RISING /* Output phase control of LCD_DATA[23:0] signal */ +#define LCD_CH0_OUT_FORMAT VDC5_LCD_OUTFORMAT_RGB666 /* LCD output format select */ + +#define LCD_CH0_PANEL_CLK VDC5_PANEL_ICKSEL_PERI /* Panel clock select */ +#define LCD_CH0_PANEL_CLK_DIV VDC5_PANEL_CLKDIV_1_2 /* Panel clock frequency division ratio */ + +#define LCD_CH0_TCON_HALF (LCD_CH0_SIG_FH / 2u) /* TCON reference timing, 1/2fH timing */ +#define LCD_CH0_TCON_OFFSET (0u) /* TCON reference timing, offset Hsync signal timing */ + + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Exported global functions (to be accessed by other files) +******************************************************************************/ +void GRAPHICS_SetLcdPanel_Ch0(void); +void GRAPHICS_SetLcdTconSettings_Ch0(const vdc5_lcd_tcon_timing_t * * const outctrl); + + +#endif /* LCD_PANEL_H not defined */ +#endif /* LCD_GR_PEACH_CH0_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/inc/lcd_panel.h Fri Jun 26 02:17:53 2015 +0000 @@ -0,0 +1,89 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/**************************************************************************//** +* @file lcd_panel.h +* @version 1.00 +* $Rev: 199 $ +* $Date:: 2014-05-23 16:33:52 +0900#$ +* @brief LCD panel definition header +******************************************************************************/ + +#ifndef LCD_PANEL_H +#define LCD_PANEL_H + +/****************************************************************************** +Includes <System Includes> , "Project Includes" +******************************************************************************/ +#include <stdlib.h> + +#include "r_typedefs.h" + +#include "r_vdc5.h" + + +/****************************************************************************** +Macro definitions +******************************************************************************/ +/* LCD panel select (CH0) + 1: Analog RGB D-sub15, SVGA 800x600 debug code for GENMAI Board + 2: Gr-peach, WVGA 800x480 Not support +*/ +#define LCD_CH0_PANEL_ANALOG_RGB (1) /* debug */ +#define LCD_CH0_PANEL_GR_PEACH (2) /* Not support */ +#define LCD_VDC5_CH0_PANEL LCD_CH0_PANEL_GR_PEACH + +/* LCD panel select (CH1) + 1: Analog RGB D-sub15, SVGA 800x600 debug code for GENMAI Board +*/ +#define LCD_CH1_PANEL_ANALOG_RGB (1) /* debug */ +#define LCD_VDC5_CH1_PANEL LCD_CH1_PANEL_ANALOG_RGB + + +#if (LCD_VDC5_CH0_PANEL==1) +#include "lcd_analog_rgb_ch0.h" +#elif (LCD_VDC5_CH0_PANEL==2) +#include "lcd_gr_peach_ch0.h" /* Not support */ +#else +#error Undefined LCD panel! +#endif + +#if (LCD_VDC5_CH1_PANEL==1) +#include "lcd_analog_rgb_ch1.h" +#else +#error Undefined LCD panel! +#endif + + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Exported global functions (to be accessed by other files) +******************************************************************************/ +void GRAPHICS_SetLcdPanel(const vdc5_channel_t channel); +void GRAPHICS_SetLcdTconSettings(const vdc5_channel_t channel, const vdc5_lcd_tcon_timing_t * * const outctrl); +vdc5_lvds_t * GRAPHICS_GetLvdsParam(const vdc5_channel_t channel); + + +#endif /* LCD_PANEL_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/inc/lvds_pll_calc.h Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,70 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file lvds_pll_calc.h
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief Debug function header
+******************************************************************************/
+
+#ifndef LVDS_PLL_CALC_H
+#define LVDS_PLL_CALC_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+typedef struct {
+ double comparison_freq;
+ double output_freq;
+ double nidiv;
+ double nrd;
+ double nfd;
+ double nod;
+ double nodiv;
+} pll_parameter_t;
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+#define LVDS_IF_NOT_USE (0u)
+#define LVDS_IF_USE (1u)
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+extern int32_t lvds_pll_calc(
+ const double InClock,
+ const double OuClock,
+ const uint32_t Lvds,
+ pll_parameter_t * result );
+
+#endif /* LVDS_PLL_CALC_H */
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/inc/video_decoder.h Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,72 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file video_decoder.h
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief Video decoder function header
+******************************************************************************/
+
+#ifndef VIDEO_DECODER_H
+#define VIDEO_DECODER_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include <stdlib.h>
+#include <string.h>
+
+#include "r_vdec.h"
+#include "r_vdec_user.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! Video color system */
+typedef enum {
+ GRPH_COL_SYS_UNKNOWN = -1, /*!< Unknown */
+ GRPH_COL_SYS_NTSC_358 = 0, /*!< NTSC-3.58 */
+ GRPH_COL_SYS_NTSC_443 = 1, /*!< NTSC-4.43 */
+ GRPH_COL_SYS_PAL_443 = 2, /*!< PAL-4.43 */
+ GRPH_COL_SYS_PAL_M = 3, /*!< PAL-M */
+ GRPH_COL_SYS_PAL_N = 4, /*!< PAL-N */
+ GRPH_COL_SYS_SECAM = 5, /*!< SECAM */
+ GRPH_COL_SYS_NTSC_443_60 = 6, /*!< NTSC-4.43 (60Hz) */
+ GRPH_COL_SYS_PAL_60 = 7, /*!< PAL-60 */
+ GRPH_COL_SYS_NUM = 8
+} graphics_col_sys_t;
+
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+vdec_error_t GRAPHICS_VideoDecoderInit (const vdec_adc_vinsel_t adc_vinsel, const vdec_channel_t channel, graphics_col_sys_t col_sys);
+
+
+#endif /* VIDEO_DECODER_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/lvds/lvds_pll_data.c Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,321 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file lvds_pll_data.c
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief lvds pll for vdc5 channel 0 data
+******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include <stdio.h>
+#include <stdlib.h>
+
+
+/******************************************************************************
+Variables
+******************************************************************************/
+const double NIDIV_data[] = {
+ 1.0, 2.0, 4.0,
+ 0.0
+};
+
+const double NRD_data[] = {
+ 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0,
+ 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
+ 17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0,
+ 25.0, 26.0, 27.0, 28.0, 29.0, 30.0, 31.0, 32.0,
+ 0.0
+};
+
+const double NFD_data[] = {
+ 24.0, 25.0, 26.0, 27.0,
+ 32.0, 33.0, 34.0, 35.0, 36.0,
+ 40.0, 41.0, 42.0, 43.0, 44.0, 45.0,
+ 48.0, 49.0, 50.0, 51.0, 52.0, 53.0, 54.0,
+ 56.0, 57.0, 58.0, 59.0, 60.0, 61.0, 62.0, 63.0,
+ 64.0, 65.0, 66.0, 67.0, 68.0, 69.0, 70.0, 71.0,
+ 72.0, 73.0, 74.0, 75.0, 76.0, 77.0, 78.0, 79.0,
+ 80.0, 81.0, 82.0, 83.0, 84.0, 85.0, 86.0, 87.0,
+ 88.0, 89.0, 90.0, 91.0, 92.0, 93.0, 94.0, 95.0,
+ 96.0, 97.0, 98.0, 99.0, 100.0, 101.0, 102.0, 103.0,
+ 104.0, 105.0, 106.0, 107.0, 108.0, 109.0, 110.0, 111.0,
+ 112.0, 113.0, 114.0, 115.0, 116.0, 117.0, 118.0, 119.0,
+ 120.0, 121.0, 122.0, 123.0, 124.0, 125.0, 126.0, 127.0,
+ 128.0, 129.0, 130.0, 131.0, 132.0, 133.0, 134.0, 135.0,
+ 136.0, 137.0, 138.0, 139.0, 140.0, 141.0, 142.0, 143.0,
+ 144.0, 145.0, 146.0, 147.0, 148.0, 149.0, 150.0, 151.0,
+ 152.0, 153.0, 154.0, 155.0, 156.0, 157.0, 158.0, 159.0,
+ 160.0, 161.0, 162.0, 163.0, 164.0, 165.0, 166.0, 167.0,
+ 168.0, 169.0, 170.0, 171.0, 172.0, 173.0, 174.0, 175.0,
+ 176.0, 177.0, 178.0, 179.0, 180.0, 181.0, 182.0, 183.0,
+ 184.0, 185.0, 186.0, 187.0, 188.0, 189.0, 190.0, 191.0,
+ 192.0, 193.0, 194.0, 195.0, 196.0, 197.0, 198.0, 199.0,
+ 200.0, 201.0, 202.0, 203.0, 204.0, 205.0, 206.0, 207.0,
+ 208.0, 209.0, 210.0, 211.0, 212.0, 213.0, 214.0, 215.0,
+ 216.0, 217.0, 218.0, 219.0, 220.0, 221.0, 222.0, 223.0,
+ 224.0, 225.0, 226.0, 227.0, 228.0, 229.0, 230.0, 231.0,
+ 232.0, 233.0, 234.0, 235.0, 236.0, 237.0, 238.0, 239.0,
+ 240.0, 241.0, 242.0, 243.0, 244.0, 245.0, 246.0, 247.0,
+ 248.0, 249.0, 250.0, 251.0, 252.0, 253.0, 254.0, 255.0,
+ 256.0, 257.0, 258.0, 259.0, 260.0, 261.0, 262.0, 263.0,
+ 264.0, 265.0, 266.0, 267.0, 268.0, 269.0, 270.0, 271.0,
+ 272.0, 273.0, 274.0, 275.0, 276.0, 277.0, 278.0, 279.0,
+ 280.0, 281.0, 282.0, 283.0, 284.0, 285.0, 286.0, 287.0,
+ 288.0, 289.0, 290.0, 291.0, 292.0, 293.0, 294.0, 295.0,
+ 296.0, 297.0, 298.0, 299.0, 300.0, 301.0, 302.0, 303.0,
+ 304.0, 305.0, 306.0, 307.0, 308.0, 309.0, 310.0, 311.0,
+ 312.0, 313.0, 314.0, 315.0, 316.0, 317.0, 318.0, 319.0,
+ 320.0, 321.0, 322.0, 323.0, 324.0, 325.0, 326.0, 327.0,
+ 328.0, 329.0, 330.0, 331.0, 332.0, 333.0, 334.0, 335.0,
+ 336.0, 337.0, 338.0, 339.0, 340.0, 341.0, 342.0, 343.0,
+ 344.0, 345.0, 346.0, 347.0, 348.0, 349.0, 350.0, 351.0,
+ 352.0, 353.0, 354.0, 355.0, 356.0, 357.0, 358.0, 359.0,
+ 360.0, 361.0, 362.0, 363.0, 364.0, 365.0, 366.0, 367.0,
+ 368.0, 369.0, 370.0, 371.0, 372.0, 373.0, 374.0, 375.0,
+ 376.0, 377.0, 378.0, 379.0, 380.0, 381.0, 382.0, 383.0,
+ 384.0, 385.0, 386.0, 387.0, 388.0, 389.0, 390.0, 391.0,
+ 392.0, 393.0, 394.0, 395.0, 396.0, 397.0, 398.0, 399.0,
+ 400.0, 401.0, 402.0, 403.0, 404.0, 405.0, 406.0, 407.0,
+ 408.0, 409.0, 410.0, 411.0, 412.0, 413.0, 414.0, 415.0,
+ 416.0, 417.0, 418.0, 419.0, 420.0, 421.0, 422.0, 423.0,
+ 424.0, 425.0, 426.0, 427.0, 428.0, 429.0, 430.0, 431.0,
+ 432.0, 433.0, 434.0, 435.0, 436.0, 437.0, 438.0, 439.0,
+ 440.0, 441.0, 442.0, 443.0, 444.0, 445.0, 446.0, 447.0,
+ 448.0, 449.0, 450.0, 451.0, 452.0, 453.0, 454.0, 455.0,
+ 456.0, 457.0, 458.0, 459.0, 460.0, 461.0, 462.0, 463.0,
+ 464.0, 465.0, 466.0, 467.0, 468.0, 469.0, 470.0, 471.0,
+ 472.0, 473.0, 474.0, 475.0, 476.0, 477.0, 478.0, 479.0,
+ 480.0, 481.0, 482.0, 483.0, 484.0, 485.0, 486.0, 487.0,
+ 488.0, 489.0, 490.0, 491.0, 492.0, 493.0, 494.0, 495.0,
+ 496.0, 497.0, 498.0, 499.0, 500.0, 501.0, 502.0, 503.0,
+ 504.0, 505.0, 506.0, 507.0, 508.0, 509.0, 510.0, 511.0,
+ 512.0, 513.0, 514.0, 515.0, 516.0, 517.0, 518.0, 519.0,
+ 520.0, 521.0, 522.0, 523.0, 524.0, 525.0, 526.0, 527.0,
+ 528.0, 529.0, 530.0, 531.0, 532.0, 533.0, 534.0, 535.0,
+ 536.0, 537.0, 538.0, 539.0, 540.0, 541.0, 542.0, 543.0,
+ 544.0, 545.0, 546.0, 547.0, 548.0, 549.0, 550.0, 551.0,
+ 552.0, 553.0, 554.0, 555.0, 556.0, 557.0, 558.0, 559.0,
+ 560.0, 561.0, 562.0, 563.0, 564.0, 565.0, 566.0, 567.0,
+ 568.0, 569.0, 570.0, 571.0, 572.0, 573.0, 574.0, 575.0,
+ 576.0, 577.0, 578.0, 579.0, 580.0, 581.0, 582.0, 583.0,
+ 584.0, 585.0, 586.0, 587.0, 588.0, 589.0, 590.0, 591.0,
+ 592.0, 593.0, 594.0, 595.0, 596.0, 597.0, 598.0, 599.0,
+ 600.0, 601.0, 602.0, 603.0, 604.0, 605.0, 606.0, 607.0,
+ 608.0, 609.0, 610.0, 611.0, 612.0, 613.0, 614.0, 615.0,
+ 616.0, 617.0, 618.0, 619.0, 620.0, 621.0, 622.0, 623.0,
+ 624.0, 625.0, 626.0, 627.0, 628.0, 629.0, 630.0, 631.0,
+ 632.0, 633.0, 634.0, 635.0, 636.0, 637.0, 638.0, 639.0,
+ 640.0, 641.0, 642.0, 643.0, 644.0, 645.0, 646.0, 647.0,
+ 648.0, 649.0, 650.0, 651.0, 652.0, 653.0, 654.0, 655.0,
+ 656.0, 657.0, 658.0, 659.0, 660.0, 661.0, 662.0, 663.0,
+ 664.0, 665.0, 666.0, 667.0, 668.0, 669.0, 670.0, 671.0,
+ 672.0, 673.0, 674.0, 675.0, 676.0, 677.0, 678.0, 679.0,
+ 680.0, 681.0, 682.0, 683.0, 684.0, 685.0, 686.0, 687.0,
+ 688.0, 689.0, 690.0, 691.0, 692.0, 693.0, 694.0, 695.0,
+ 696.0, 697.0, 698.0, 699.0, 700.0, 701.0, 702.0, 703.0,
+ 704.0, 705.0, 706.0, 707.0, 708.0, 709.0, 710.0, 711.0,
+ 712.0, 713.0, 714.0, 715.0, 716.0, 717.0, 718.0, 719.0,
+ 720.0, 721.0, 722.0, 723.0, 724.0, 725.0, 726.0, 727.0,
+ 728.0, 729.0, 730.0, 731.0, 732.0, 733.0, 734.0, 735.0,
+ 736.0, 737.0, 738.0, 739.0, 740.0, 741.0, 742.0, 743.0,
+ 744.0, 745.0, 746.0, 747.0, 748.0, 749.0, 750.0, 751.0,
+ 752.0, 753.0, 754.0, 755.0, 756.0, 757.0, 758.0, 759.0,
+ 760.0, 761.0, 762.0, 763.0, 764.0, 765.0, 766.0, 767.0,
+ 768.0, 769.0, 770.0, 771.0, 772.0, 773.0, 774.0, 775.0,
+ 776.0, 777.0, 778.0, 779.0, 780.0, 781.0, 782.0, 783.0,
+ 784.0, 785.0, 786.0, 787.0, 788.0, 789.0, 790.0, 791.0,
+ 792.0, 793.0, 794.0, 795.0, 796.0, 797.0, 798.0, 799.0,
+ 800.0, 801.0, 802.0, 803.0, 804.0, 805.0, 806.0, 807.0,
+ 808.0, 809.0, 810.0, 811.0, 812.0, 813.0, 814.0, 815.0,
+ 816.0, 817.0, 818.0, 819.0, 820.0, 821.0, 822.0, 823.0,
+ 824.0, 825.0, 826.0, 827.0, 828.0, 829.0, 830.0, 831.0,
+ 832.0, 833.0, 834.0, 835.0, 836.0, 837.0, 838.0, 839.0,
+ 840.0, 841.0, 842.0, 843.0, 844.0, 845.0, 846.0, 847.0,
+ 848.0, 849.0, 850.0, 851.0, 852.0, 853.0, 854.0, 855.0,
+ 856.0, 857.0, 858.0, 859.0, 860.0, 861.0, 862.0, 863.0,
+ 864.0, 865.0, 866.0, 867.0, 868.0, 869.0, 870.0, 871.0,
+ 872.0, 873.0, 874.0, 875.0, 876.0, 877.0, 878.0, 879.0,
+ 880.0, 881.0, 882.0, 883.0, 884.0, 885.0, 886.0, 887.0,
+ 888.0, 889.0, 890.0, 891.0, 892.0, 893.0, 894.0, 895.0,
+ 896.0, 897.0, 898.0, 899.0, 900.0, 901.0, 902.0, 903.0,
+ 904.0, 905.0, 906.0, 907.0, 908.0, 909.0, 910.0, 911.0,
+ 912.0, 913.0, 914.0, 915.0, 916.0, 917.0, 918.0, 919.0,
+ 920.0, 921.0, 922.0, 923.0, 924.0, 925.0, 926.0, 927.0,
+ 928.0, 929.0, 930.0, 931.0, 932.0, 933.0, 934.0, 935.0,
+ 936.0, 937.0, 938.0, 939.0, 940.0, 941.0, 942.0, 943.0,
+ 944.0, 945.0, 946.0, 947.0, 948.0, 949.0, 950.0, 951.0,
+ 952.0, 953.0, 954.0, 955.0, 956.0, 957.0, 958.0, 959.0,
+ 960.0, 961.0, 962.0, 963.0, 964.0, 965.0, 966.0, 967.0,
+ 968.0, 969.0, 970.0, 971.0, 972.0, 973.0, 974.0, 975.0,
+ 976.0, 977.0, 978.0, 979.0, 980.0, 981.0, 982.0, 983.0,
+ 984.0, 985.0, 986.0, 987.0, 988.0, 989.0, 990.0, 991.0,
+ 992.0, 993.0, 994.0, 995.0, 996.0, 997.0, 998.0, 999.0,
+ 1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0, 1006.0, 1007.0,
+ 1008.0, 1009.0, 1010.0, 1011.0, 1012.0, 1013.0, 1014.0, 1015.0,
+ 1016.0, 1017.0, 1018.0, 1019.0, 1020.0, 1021.0, 1022.0, 1023.0,
+ 1024.0, 1025.0, 1026.0, 1027.0, 1028.0, 1029.0, 1030.0, 1031.0,
+ 1032.0, 1033.0, 1034.0, 1035.0, 1036.0, 1037.0, 1038.0, 1039.0,
+ 1040.0, 1041.0, 1042.0, 1043.0, 1044.0, 1045.0, 1046.0, 1047.0,
+ 1048.0, 1049.0, 1050.0, 1051.0, 1052.0, 1053.0, 1054.0, 1055.0,
+ 1056.0, 1057.0, 1058.0, 1059.0, 1060.0, 1061.0, 1062.0, 1063.0,
+ 1064.0, 1065.0, 1066.0, 1067.0, 1068.0, 1069.0, 1070.0, 1071.0,
+ 1072.0, 1073.0, 1074.0, 1075.0, 1076.0, 1077.0, 1078.0, 1079.0,
+ 1080.0, 1081.0, 1082.0, 1083.0, 1084.0, 1085.0, 1086.0, 1087.0,
+ 1088.0, 1089.0, 1090.0, 1091.0, 1092.0, 1093.0, 1094.0, 1095.0,
+ 1096.0, 1097.0, 1098.0, 1099.0, 1100.0, 1101.0, 1102.0, 1103.0,
+ 1104.0, 1105.0, 1106.0, 1107.0, 1108.0, 1109.0, 1110.0, 1111.0,
+ 1112.0, 1113.0, 1114.0, 1115.0, 1116.0, 1117.0, 1118.0, 1119.0,
+ 1120.0, 1121.0, 1122.0, 1123.0, 1124.0, 1125.0, 1126.0, 1127.0,
+ 1128.0, 1129.0, 1130.0, 1131.0, 1132.0, 1133.0, 1134.0, 1135.0,
+ 1136.0, 1137.0, 1138.0, 1139.0, 1140.0, 1141.0, 1142.0, 1143.0,
+ 1144.0, 1145.0, 1146.0, 1147.0, 1148.0, 1149.0, 1150.0, 1151.0,
+ 1152.0, 1153.0, 1154.0, 1155.0, 1156.0, 1157.0, 1158.0, 1159.0,
+ 1160.0, 1161.0, 1162.0, 1163.0, 1164.0, 1165.0, 1166.0, 1167.0,
+ 1168.0, 1169.0, 1170.0, 1171.0, 1172.0, 1173.0, 1174.0, 1175.0,
+ 1176.0, 1177.0, 1178.0, 1179.0, 1180.0, 1181.0, 1182.0, 1183.0,
+ 1184.0, 1185.0, 1186.0, 1187.0, 1188.0, 1189.0, 1190.0, 1191.0,
+ 1192.0, 1193.0, 1194.0, 1195.0, 1196.0, 1197.0, 1198.0, 1199.0,
+ 1200.0, 1201.0, 1202.0, 1203.0, 1204.0, 1205.0, 1206.0, 1207.0,
+ 1208.0, 1209.0, 1210.0, 1211.0, 1212.0, 1213.0, 1214.0, 1215.0,
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+ 1232.0, 1233.0, 1234.0, 1235.0, 1236.0, 1237.0, 1238.0, 1239.0,
+ 1240.0, 1241.0, 1242.0, 1243.0, 1244.0, 1245.0, 1246.0, 1247.0,
+ 1248.0, 1249.0, 1250.0, 1251.0, 1252.0, 1253.0, 1254.0, 1255.0,
+ 1256.0, 1257.0, 1258.0, 1259.0, 1260.0, 1261.0, 1262.0, 1263.0,
+ 1264.0, 1265.0, 1266.0, 1267.0, 1268.0, 1269.0, 1270.0, 1271.0,
+ 1272.0, 1273.0, 1274.0, 1275.0, 1276.0, 1277.0, 1278.0, 1279.0,
+ 1280.0, 1281.0, 1282.0, 1283.0, 1284.0, 1285.0, 1286.0, 1287.0,
+ 1288.0, 1289.0, 1290.0, 1291.0, 1292.0, 1293.0, 1294.0, 1295.0,
+ 1296.0, 1297.0, 1298.0, 1299.0, 1300.0, 1301.0, 1302.0, 1303.0,
+ 1304.0, 1305.0, 1306.0, 1307.0, 1308.0, 1309.0, 1310.0, 1311.0,
+ 1312.0, 1313.0, 1314.0, 1315.0, 1316.0, 1317.0, 1318.0, 1319.0,
+ 1320.0, 1321.0, 1322.0, 1323.0, 1324.0, 1325.0, 1326.0, 1327.0,
+ 1328.0, 1329.0, 1330.0, 1331.0, 1332.0, 1333.0, 1334.0, 1335.0,
+ 1336.0, 1337.0, 1338.0, 1339.0, 1340.0, 1341.0, 1342.0, 1343.0,
+ 1344.0, 1345.0, 1346.0, 1347.0, 1348.0, 1349.0, 1350.0, 1351.0,
+ 1352.0, 1353.0, 1354.0, 1355.0, 1356.0, 1357.0, 1358.0, 1359.0,
+ 1360.0, 1361.0, 1362.0, 1363.0, 1364.0, 1365.0, 1366.0, 1367.0,
+ 1368.0, 1369.0, 1370.0, 1371.0, 1372.0, 1373.0, 1374.0, 1375.0,
+ 1376.0, 1377.0, 1378.0, 1379.0, 1380.0, 1381.0, 1382.0, 1383.0,
+ 1384.0, 1385.0, 1386.0, 1387.0, 1388.0, 1389.0, 1390.0, 1391.0,
+ 1392.0, 1393.0, 1394.0, 1395.0, 1396.0, 1397.0, 1398.0, 1399.0,
+ 1400.0, 1401.0, 1402.0, 1403.0, 1404.0, 1405.0, 1406.0, 1407.0,
+ 1408.0, 1409.0, 1410.0, 1411.0, 1412.0, 1413.0, 1414.0, 1415.0,
+ 1416.0, 1417.0, 1418.0, 1419.0, 1420.0, 1421.0, 1422.0, 1423.0,
+ 1424.0, 1425.0, 1426.0, 1427.0, 1428.0, 1429.0, 1430.0, 1431.0,
+ 1432.0, 1433.0, 1434.0, 1435.0, 1436.0, 1437.0, 1438.0, 1439.0,
+ 1440.0, 1441.0, 1442.0, 1443.0, 1444.0, 1445.0, 1446.0, 1447.0,
+ 1448.0, 1449.0, 1450.0, 1451.0, 1452.0, 1453.0, 1454.0, 1455.0,
+ 1456.0, 1457.0, 1458.0, 1459.0, 1460.0, 1461.0, 1462.0, 1463.0,
+ 1464.0, 1465.0, 1466.0, 1467.0, 1468.0, 1469.0, 1470.0, 1471.0,
+ 1472.0, 1473.0, 1474.0, 1475.0, 1476.0, 1477.0, 1478.0, 1479.0,
+ 1480.0, 1481.0, 1482.0, 1483.0, 1484.0, 1485.0, 1486.0, 1487.0,
+ 1488.0, 1489.0, 1490.0, 1491.0, 1492.0, 1493.0, 1494.0, 1495.0,
+ 1496.0, 1497.0, 1498.0, 1499.0, 1500.0, 1501.0, 1502.0, 1503.0,
+ 1504.0, 1505.0, 1506.0, 1507.0, 1508.0, 1509.0, 1510.0, 1511.0,
+ 1512.0, 1513.0, 1514.0, 1515.0, 1516.0, 1517.0, 1518.0, 1519.0,
+ 1520.0, 1521.0, 1522.0, 1523.0, 1524.0, 1525.0, 1526.0, 1527.0,
+ 1528.0, 1529.0, 1530.0, 1531.0, 1532.0, 1533.0, 1534.0, 1535.0,
+ 1536.0, 1537.0, 1538.0, 1539.0, 1540.0, 1541.0, 1542.0, 1543.0,
+ 1544.0, 1545.0, 1546.0, 1547.0, 1548.0, 1549.0, 1550.0, 1551.0,
+ 1552.0, 1553.0, 1554.0, 1555.0, 1556.0, 1557.0, 1558.0, 1559.0,
+ 1560.0, 1561.0, 1562.0, 1563.0, 1564.0, 1565.0, 1566.0, 1567.0,
+ 1568.0, 1569.0, 1570.0, 1571.0, 1572.0, 1573.0, 1574.0, 1575.0,
+ 1576.0, 1577.0, 1578.0, 1579.0, 1580.0, 1581.0, 1582.0, 1583.0,
+ 1584.0, 1585.0, 1586.0, 1587.0, 1588.0, 1589.0, 1590.0, 1591.0,
+ 1592.0, 1593.0, 1594.0, 1595.0, 1596.0, 1597.0, 1598.0, 1599.0,
+ 1600.0, 1601.0, 1602.0, 1603.0, 1604.0, 1605.0, 1606.0, 1607.0,
+ 1608.0, 1609.0, 1610.0, 1611.0, 1612.0, 1613.0, 1614.0, 1615.0,
+ 1616.0, 1617.0, 1618.0, 1619.0, 1620.0, 1621.0, 1622.0, 1623.0,
+ 1624.0, 1625.0, 1626.0, 1627.0, 1628.0, 1629.0, 1630.0, 1631.0,
+ 1632.0, 1633.0, 1634.0, 1635.0, 1636.0, 1637.0, 1638.0, 1639.0,
+ 1640.0, 1641.0, 1642.0, 1643.0, 1644.0, 1645.0, 1646.0, 1647.0,
+ 1648.0, 1649.0, 1650.0, 1651.0, 1652.0, 1653.0, 1654.0, 1655.0,
+ 1656.0, 1657.0, 1658.0, 1659.0, 1660.0, 1661.0, 1662.0, 1663.0,
+ 1664.0, 1665.0, 1666.0, 1667.0, 1668.0, 1669.0, 1670.0, 1671.0,
+ 1672.0, 1673.0, 1674.0, 1675.0, 1676.0, 1677.0, 1678.0, 1679.0,
+ 1680.0, 1681.0, 1682.0, 1683.0, 1684.0, 1685.0, 1686.0, 1687.0,
+ 1688.0, 1689.0, 1690.0, 1691.0, 1692.0, 1693.0, 1694.0, 1695.0,
+ 1696.0, 1697.0, 1698.0, 1699.0, 1700.0, 1701.0, 1702.0, 1703.0,
+ 1704.0, 1705.0, 1706.0, 1707.0, 1708.0, 1709.0, 1710.0, 1711.0,
+ 1712.0, 1713.0, 1714.0, 1715.0, 1716.0, 1717.0, 1718.0, 1719.0,
+ 1720.0, 1721.0, 1722.0, 1723.0, 1724.0, 1725.0, 1726.0, 1727.0,
+ 1728.0, 1729.0, 1730.0, 1731.0, 1732.0, 1733.0, 1734.0, 1735.0,
+ 1736.0, 1737.0, 1738.0, 1739.0, 1740.0, 1741.0, 1742.0, 1743.0,
+ 1744.0, 1745.0, 1746.0, 1747.0, 1748.0, 1749.0, 1750.0, 1751.0,
+ 1752.0, 1753.0, 1754.0, 1755.0, 1756.0, 1757.0, 1758.0, 1759.0,
+ 1760.0, 1761.0, 1762.0, 1763.0, 1764.0, 1765.0, 1766.0, 1767.0,
+ 1768.0, 1769.0, 1770.0, 1771.0, 1772.0, 1773.0, 1774.0, 1775.0,
+ 1776.0, 1777.0, 1778.0, 1779.0, 1780.0, 1781.0, 1782.0, 1783.0,
+ 1784.0, 1785.0, 1786.0, 1787.0, 1788.0, 1789.0, 1790.0, 1791.0,
+ 1792.0, 1793.0, 1794.0, 1795.0, 1796.0, 1797.0, 1798.0, 1799.0,
+ 1800.0, 1801.0, 1802.0, 1803.0, 1804.0, 1805.0, 1806.0, 1807.0,
+ 1808.0, 1809.0, 1810.0, 1811.0, 1812.0, 1813.0, 1814.0, 1815.0,
+ 1816.0, 1817.0, 1818.0, 1819.0, 1820.0, 1821.0, 1822.0, 1823.0,
+ 1824.0, 1825.0, 1826.0, 1827.0, 1828.0, 1829.0, 1830.0, 1831.0,
+ 1832.0, 1833.0, 1834.0, 1835.0, 1836.0, 1837.0, 1838.0, 1839.0,
+ 1840.0, 1841.0, 1842.0, 1843.0, 1844.0, 1845.0, 1846.0, 1847.0,
+ 1848.0, 1849.0, 1850.0, 1851.0, 1852.0, 1853.0, 1854.0, 1855.0,
+ 1856.0, 1857.0, 1858.0, 1859.0, 1860.0, 1861.0, 1862.0, 1863.0,
+ 1864.0, 1865.0, 1866.0, 1867.0, 1868.0, 1869.0, 1870.0, 1871.0,
+ 1872.0, 1873.0, 1874.0, 1875.0, 1876.0, 1877.0, 1878.0, 1879.0,
+ 1880.0, 1881.0, 1882.0, 1883.0, 1884.0, 1885.0, 1886.0, 1887.0,
+ 1888.0, 1889.0, 1890.0, 1891.0, 1892.0, 1893.0, 1894.0, 1895.0,
+ 1896.0, 1897.0, 1898.0, 1899.0, 1900.0, 1901.0, 1902.0, 1903.0,
+ 1904.0, 1905.0, 1906.0, 1907.0, 1908.0, 1909.0, 1910.0, 1911.0,
+ 1912.0, 1913.0, 1914.0, 1915.0, 1916.0, 1917.0, 1918.0, 1919.0,
+ 1920.0, 1921.0, 1922.0, 1923.0, 1924.0, 1925.0, 1926.0, 1927.0,
+ 1928.0, 1929.0, 1930.0, 1931.0, 1932.0, 1933.0, 1934.0, 1935.0,
+ 1936.0, 1937.0, 1938.0, 1939.0, 1940.0, 1941.0, 1942.0, 1943.0,
+ 1944.0, 1945.0, 1946.0, 1947.0, 1948.0, 1949.0, 1950.0, 1951.0,
+ 1952.0, 1953.0, 1954.0, 1955.0, 1956.0, 1957.0, 1958.0, 1959.0,
+ 1960.0, 1961.0, 1962.0, 1963.0, 1964.0, 1965.0, 1966.0, 1967.0,
+ 1968.0, 1969.0, 1970.0, 1971.0, 1972.0, 1973.0, 1974.0, 1975.0,
+ 1976.0, 1977.0, 1978.0, 1979.0, 1980.0, 1981.0, 1982.0, 1983.0,
+ 1984.0, 1985.0, 1986.0, 1987.0, 1988.0, 1989.0, 1990.0, 1991.0,
+ 1992.0, 1993.0, 1994.0, 1995.0, 1996.0, 1997.0, 1998.0, 1999.0,
+ 2000.0, 2001.0, 2002.0, 2003.0, 2004.0, 2005.0, 2006.0, 2007.0,
+ 2008.0, 2009.0, 2010.0, 2011.0, 2012.0, 2013.0, 2014.0, 2015.0,
+ 2016.0, 2017.0, 2018.0, 2019.0, 2020.0, 2021.0, 2022.0, 2023.0,
+ 2024.0, 2025.0, 2026.0, 2027.0, 2028.0, 2029.0, 2030.0, 2031.0,
+ 2032.0, 2033.0, 2034.0, 2035.0, 2036.0, 2037.0, 2038.0, 2039.0,
+ 2040.0, 2041.0, 2042.0, 2043.0, 2044.0, 2045.0, 2046.0, 2047.0,
+ 0.0
+};
+
+const double NOD_data[] = {
+ 1.0, 2.0, 4.0, 8.0,
+ 0.0
+};
+
+const double NODIV_data[] = {
+ 1.0, 2.0, 4.0,
+ 0.0
+};
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/lvds/lvds_pll_main.c Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,239 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file lvds_pll_main.c
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief lvds pll setting value
+******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include <stdio.h>
+#include <stdlib.h>
+#include <math.h>
+
+#include "r_typedefs.h"
+#include "lvds_pll_calc.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* FIN: LVDS PLL input frequency */
+#define FIN_MIN (9.0) /*!< The lower limit of the FIN */
+#define FIN_MAX (30.0) /*!< The upper limit of the FIN */
+/* FREF */
+#define FREF_MIN (2.5) /*!< The lower limit of the FREF */
+#define FREF_MAX (30.0) /*!< The upper limit of the FREF */
+/* FVCO: VCO output frequency */
+#define FVCO_MIN (750.0) /*!< The lower limit of the FVCO */
+#define FVCO_MAX (1630.0) /*!< The upper limit of the FVCO */
+/* FOUT: LVDS PLL output frequency */
+#define FOUT_MIN (0.0) /*!< The lower limit of the FOUT */
+#define FOUT_MAX (609.0) /*!< The upper limit of the FOUT */
+
+#define DIVIDER_3 (7.0) /*!< The frequency dividing value for frequency divider 3 */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+extern const double NIDIV_data[];
+extern const double NRD_data[];
+extern const double NFD_data[];
+extern const double NOD_data[];
+extern const double NODIV_data[];
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static double InputClock;
+static double OutputClock;
+static int LvdsUsed;
+
+
+
+/**************************************************************************//**
+ * @brief
+ * @param [in,out]param
+ * @param [in]fout
+ * @retval int
+ *****************************************************************************/
+static int compare_nodiv (pll_parameter_t * param, double fout)
+{
+ int change;
+ const double * nodiv_list;
+ double diff_freq;
+
+ change = 0;
+ nodiv_list = NODIV_data;
+ while (*nodiv_list != 0.0) {
+ diff_freq = fabs(OutputClock - (fout / *nodiv_list));
+ if (param->comparison_freq > diff_freq) {
+ param->comparison_freq = diff_freq;
+ param->output_freq = fout / *nodiv_list;
+ param->nodiv = *nodiv_list;
+ change = 1;
+ }
+ nodiv_list++;
+ }
+ return change;
+}
+
+/**************************************************************************//**
+ * @brief
+ * @param [in,out]param
+ * @param [in]fout
+ * @retval int
+ *****************************************************************************/
+static int compare_div3 (pll_parameter_t * param, double fout)
+{
+ double diff_freq;
+ int change;
+
+ change = 0;
+ diff_freq = fabs(OutputClock - (fout / DIVIDER_3));
+
+ if (param->comparison_freq > diff_freq) {
+ param->comparison_freq = diff_freq;
+ param->output_freq = fout / DIVIDER_3;
+ change = 1;
+ }
+ return change;
+}
+
+/**************************************************************************//**
+ * @brief
+ * @param [out]param
+ * @retval None
+ *****************************************************************************/
+static void SeekValue (pll_parameter_t * param)
+{
+ const double * nidiv_list;
+ const double * nrd_list;
+ const double * nfd_list;
+ const double * nod_list;
+
+ double fin;
+ double fref;
+ double fvco;
+ double fout;
+ int ret;
+
+ nidiv_list = NIDIV_data;
+ while (*nidiv_list != 0.0) {
+ fin = InputClock / *nidiv_list;
+ if ((fin < FIN_MIN) || (FIN_MAX < fin)) {
+ nidiv_list++;
+ continue;
+ }
+ nrd_list = NRD_data;
+ while (*nrd_list != 0.0) {
+ fref = fin / *nrd_list;
+ if ((fref < FREF_MIN) || (FREF_MAX < fref)) {
+ nrd_list++;
+ continue;
+ }
+ nfd_list = NFD_data;
+ while (*nfd_list != 0.0) {
+ fvco = fref * (*nfd_list);
+ if ((fvco < FVCO_MIN) || (FVCO_MAX < fvco)) {
+ nfd_list++;
+ continue;
+ }
+ nod_list = NOD_data;
+ while (*nod_list != 0.0) {
+ fout = fvco / *nod_list;
+ if ((fout < FOUT_MIN) || (FOUT_MAX < fout)) {
+ nod_list++;
+ continue;
+ }
+
+ if (LvdsUsed == 0) {
+ ret = compare_nodiv(param, fout);
+ } else {
+ ret = compare_div3(param, fout);
+ }
+ if (ret != 0) {
+ param->nidiv = *nidiv_list;
+ param->nrd = *nrd_list;
+ param->nfd = *nfd_list;
+ param->nod = *nod_list;
+ }
+ nod_list++;
+ }
+ nfd_list++;
+ }
+ nrd_list++;
+ }
+ nidiv_list++;
+ }
+}
+/**************************************************************************//**
+ * @brief PLL value Calculation function
+ * @param[in] InClock : Input clock frequency [MHz]
+ * @param[in] OuClock : Output clock frequency [MHz]
+ * @param[in] Lvds : The LVDS output interface is used (=1) or not (=0)
+ * @param[out] result : pll_parameter_t
+ * @retval error (-1)
+******************************************************************************/
+int32_t lvds_pll_calc(
+ const double InClock,
+ const double OuClock,
+ const uint32_t Lvds,
+ pll_parameter_t * result )
+{
+ result->comparison_freq = 1000.0;
+ result->output_freq = 0.0;
+ result->nidiv = 0.0;
+ result->nrd = 0.0;
+ result->nfd = 0.0;
+ result->nod = 0.0;
+ result->nodiv = 0.0;
+
+ InputClock = InClock;
+ OutputClock = OuClock;
+ LvdsUsed = Lvds;
+
+ /* Calculation */
+ SeekValue(result);
+
+ result->nidiv = result->nidiv/2;
+ result->nodiv = result->nodiv/2;
+ if( result->nod <= 4 ) {
+ result->nod = result->nod/2;
+ } else if( result->nod == 8 ) {
+ result->nod = 3;
+ } else {
+ }
+ result->nrd -=1; /* nrd-1 */
+ return 0;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/video_decoder/video_decoder.c Fri Jun 26 02:17:53 2015 +0000
@@ -0,0 +1,987 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file video_decoder.c
+* @version 1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief Video decoder function
+******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include <stdlib.h>
+#include <string.h>
+
+#include "r_typedefs.h"
+#include "iodefine.h"
+
+#include "r_vdec.h"
+#include "r_vdec_user.h"
+
+#include "video_decoder.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define STBCR7_BIT7 (0x80u)
+#define STBCR7_BIT6 (0x40u)
+
+/*! Video decoder recommended value */
+#define SRCLEFT_NTSC_3_58 ((uint16_t)256u)
+#define SRCLEFT_NTSC_4_43 ((uint16_t)256u)
+#define SRCLEFT_PAL_4_43 ((uint16_t)256u)
+#define SRCLEFT_PAL_M ((uint16_t)256u)
+#define SRCLEFT_PAL_N ((uint16_t)256u)
+#define SRCLEFT_SECAM ((uint16_t)256u)
+#define SRCLEFT_NTSC_443_60 ((uint16_t)256u)
+#define SRCLEFT_PAL_60 ((uint16_t)256u)
+
+#define SRCTOP_NTSC_3_58 ((uint16_t)16u)
+#define SRCTOP_NTSC_4_43 ((uint16_t)19u)
+#define SRCTOP_PAL_4_43 ((uint16_t)19u)
+#define SRCTOP_PAL_M ((uint16_t)16u)
+#define SRCTOP_PAL_N ((uint16_t)19u)
+#define SRCTOP_SECAM ((uint16_t)19u)
+#define SRCTOP_NTSC_443_60 ((uint16_t)16u)
+#define SRCTOP_PAL_60 ((uint16_t)16u)
+
+#define SRCHEIGHT_NTSC_3_58 ((uint16_t)241u)
+#define SRCHEIGHT_NTSC_4_43 ((uint16_t)288u)
+#define SRCHEIGHT_PAL_4_43 ((uint16_t)288u)
+#define SRCHEIGHT_PAL_M ((uint16_t)241u)
+#define SRCHEIGHT_PAL_N ((uint16_t)288u)
+#define SRCHEIGHT_SECAM ((uint16_t)288u)
+#define SRCHEIGHT_NTSC_443_60 ((uint16_t)241u)
+#define SRCHEIGHT_PAL_60 ((uint16_t)241u)
+
+#define SRCWIDTH_NTSC_3_58 ((uint16_t)1428u)
+#define SRCWIDTH_NTSC_4_43 ((uint16_t)1412u)
+#define SRCWIDTH_PAL_4_43 ((uint16_t)1412u)
+#define SRCWIDTH_PAL_M ((uint16_t)1428u)
+#define SRCWIDTH_PAL_N ((uint16_t)1412u)
+#define SRCWIDTH_SECAM ((uint16_t)1412u)
+#define SRCWIDTH_NTSC_443_60 ((uint16_t)1428u)
+#define SRCWIDTH_PAL_60 ((uint16_t)1428u)
+
+#define HAFCTYP_NTSC_3_58 ((uint16_t)692u)
+#define HAFCTYP_NTSC_4_43 ((uint16_t)704u)
+#define HAFCTYP_PAL_4_43 ((uint16_t)704u)
+#define HAFCTYP_PAL_M ((uint16_t)692u)
+#define HAFCTYP_PAL_N ((uint16_t)704u)
+#define HAFCTYP_SECAM ((uint16_t)704u)
+#define HAFCTYP_NTSC_443_60 ((uint16_t)692u)
+#define HAFCTYP_PAL_60 ((uint16_t)692u)
+
+#define HAFCMAX_NTSC_3_58 ((uint16_t)792u)
+#define HAFCMAX_NTSC_4_43 ((uint16_t)785u)
+#define HAFCMAX_PAL_4_43 ((uint16_t)785u)
+#define HAFCMAX_PAL_M ((uint16_t)792u)
+#define HAFCMAX_PAL_N ((uint16_t)785u)
+#define HAFCMAX_SECAM ((uint16_t)785u)
+#define HAFCMAX_NTSC_443_60 ((uint16_t)792u)
+#define HAFCMAX_PAL_60 ((uint16_t)792u)
+
+#define HAFCMIN_NTSC_3_58 ((uint16_t)592u)
+#define HAFCMIN_NTSC_4_43 ((uint16_t)630u)
+#define HAFCMIN_PAL_4_43 ((uint16_t)630u)
+#define HAFCMIN_PAL_M ((uint16_t)592u)
+#define HAFCMIN_PAL_N ((uint16_t)630u)
+#define HAFCMIN_SECAM ((uint16_t)630u)
+#define HAFCMIN_NTSC_443_60 ((uint16_t)592u)
+#define HAFCMIN_PAL_60 ((uint16_t)592u)
+
+#define VCDWINDOW_NTSC_3_58 ((uint16_t)30u)
+#define VCDWINDOW_NTSC_4_43 ((uint16_t)30u)
+#define VCDWINDOW_PAL_4_43 ((uint16_t)30u)
+#define VCDWINDOW_PAL_M ((uint16_t)30u)
+#define VCDWINDOW_PAL_N ((uint16_t)30u)
+#define VCDWINDOW_SECAM ((uint16_t)30u)
+#define VCDWINDOW_NTSC_443_60 ((uint16_t)30u)
+#define VCDWINDOW_PAL_60 ((uint16_t)30u)
+
+#define VCDOFFSET_NTSC_3_58 ((uint16_t)15u)
+#define VCDOFFSET_NTSC_4_43 ((uint16_t)15u)
+#define VCDOFFSET_PAL_4_43 ((uint16_t)15u)
+#define VCDOFFSET_PAL_M ((uint16_t)15u)
+#define VCDOFFSET_PAL_N ((uint16_t)15u)
+#define VCDOFFSET_SECAM ((uint16_t)15u)
+#define VCDOFFSET_NTSC_443_60 ((uint16_t)15u)
+#define VCDOFFSET_PAL_60 ((uint16_t)15u)
+
+#define ACCLEVEL_NTSC_3_58 ((uint16_t)220u)
+#define ACCLEVEL_NTSC_4_43 ((uint16_t)220u)
+#define ACCLEVEL_PAL_4_43 ((uint16_t)220u)
+#define ACCLEVEL_PAL_M ((uint16_t)230u)
+#define ACCLEVEL_PAL_N ((uint16_t)230u)
+#define ACCLEVEL_SECAM ((uint16_t)220u)
+#define ACCLEVEL_NTSC_443_60 ((uint16_t)220u)
+#define ACCLEVEL_PAL_60 ((uint16_t)230u)
+
+#define AGCLEVEL_NTSC_3_58 ((uint16_t)230u)
+#define AGCLEVEL_NTSC_4_43 ((uint16_t)230u)
+#define AGCLEVEL_PAL_4_43 ((uint16_t)242u)
+#define AGCLEVEL_PAL_M ((uint16_t)242u)
+#define AGCLEVEL_PAL_N ((uint16_t)242u)
+#define AGCLEVEL_SECAM ((uint16_t)242u)
+#define AGCLEVEL_NTSC_443_60 ((uint16_t)230u)
+#define AGCLEVEL_PAL_60 ((uint16_t)242u)
+
+#define K15_NTSC_3_58 ((uint16_t)2u)
+#define K15_NTSC_4_43 ((uint16_t)2u)
+#define K15_PAL_4_43 ((uint16_t)2u)
+#define K15_PAL_M ((uint16_t)2u)
+#define K15_PAL_N ((uint16_t)2u)
+#define K15_SECAM ((uint16_t)2u)
+#define K15_NTSC_443_60 ((uint16_t)2u)
+#define K15_PAL_60 ((uint16_t)2u)
+
+#define K13_NTSC_3_58 ((uint16_t)8u)
+#define K13_NTSC_4_43 ((uint16_t)8u)
+#define K13_PAL_4_43 ((uint16_t)8u)
+#define K13_PAL_M ((uint16_t)8u)
+#define K13_PAL_N ((uint16_t)8u)
+#define K13_SECAM ((uint16_t)8u)
+#define K13_NTSC_443_60 ((uint16_t)8u)
+#define K13_PAL_60 ((uint16_t)8u)
+
+#define K11_NTSC_3_58 ((uint16_t)4u)
+#define K11_NTSC_4_43 ((uint16_t)4u)
+#define K11_PAL_4_43 ((uint16_t)3u)
+#define K11_PAL_M ((uint16_t)3u)
+#define K11_PAL_N ((uint16_t)3u)
+#define K11_SECAM ((uint16_t)4u)
+#define K11_NTSC_443_60 ((uint16_t)4u)
+#define K11_PAL_60 ((uint16_t)3u)
+
+#define K16_NTSC_3_58 ((uint16_t)3u)
+#define K16_NTSC_4_43 ((uint16_t)3u)
+#define K16_PAL_4_43 ((uint16_t)4u)
+#define K16_PAL_M ((uint16_t)4u)
+#define K16_PAL_N ((uint16_t)4u)
+#define K16_SECAM ((uint16_t)3u)
+#define K16_NTSC_443_60 ((uint16_t)3u)
+#define K16_PAL_60 ((uint16_t)4u)
+
+#define K14_NTSC_3_58 ((uint16_t)16u)
+#define K14_NTSC_4_43 ((uint16_t)16u)
+#define K14_PAL_4_43 ((uint16_t)63u)
+#define K14_PAL_M ((uint16_t)63u)
+#define K14_PAL_N ((uint16_t)63u)
+#define K14_SECAM ((uint16_t)16u)
+#define K14_NTSC_443_60 ((uint16_t)16u)
+#define K14_PAL_60 ((uint16_t)63u)
+
+#define K12_NTSC_3_58 ((uint16_t)8u)
+#define K12_NTSC_4_43 ((uint16_t)8u)
+#define K12_PAL_4_43 ((uint16_t)2u)
+#define K12_PAL_M ((uint16_t)2u)
+#define K12_PAL_N ((uint16_t)2u)
+#define K12_SECAM ((uint16_t)1u)
+#define K12_NTSC_443_60 ((uint16_t)8u)
+#define K12_PAL_60 ((uint16_t)2u)
+
+#define K22A_NTSC_3_58 ((uint16_t)32u)
+#define K22A_NTSC_4_43 ((uint16_t)32u)
+#define K22A_PAL_4_43 ((uint16_t)32u)
+#define K22A_PAL_M ((uint16_t)32u)
+#define K22A_PAL_N ((uint16_t)32u)
+#define K22A_SECAM ((uint16_t)32u)
+#define K22A_NTSC_443_60 ((uint16_t)32u)
+#define K22A_PAL_60 ((uint16_t)32u)
+
+#define K21A_NTSC_3_58 ((uint16_t)6u)
+#define K21A_NTSC_4_43 ((uint16_t)6u)
+#define K21A_PAL_4_43 ((uint16_t)10u)
+#define K21A_PAL_M ((uint16_t)10u)
+#define K21A_PAL_N ((uint16_t)10u)
+#define K21A_SECAM ((uint16_t)10u)
+#define K21A_NTSC_443_60 ((uint16_t)6u)
+#define K21A_PAL_60 ((uint16_t)10u)
+
+#define K22B_NTSC_3_58 ((uint16_t)8u)
+#define K22B_NTSC_4_43 ((uint16_t)8u)
+#define K22B_PAL_4_43 ((uint16_t)15u)
+#define K22B_PAL_M ((uint16_t)15u)
+#define K22B_PAL_N ((uint16_t)15u)
+#define K22B_SECAM ((uint16_t)15u)
+#define K22B_NTSC_443_60 ((uint16_t)8u)
+#define K22B_PAL_60 ((uint16_t)15u)
+
+#define K21B_NTSC_3_58 ((uint16_t)6u)
+#define K21B_NTSC_4_43 ((uint16_t)6u)
+#define K21B_PAL_4_43 ((uint16_t)10u)
+#define K21B_PAL_M ((uint16_t)10u)
+#define K21B_PAL_N ((uint16_t)10u)
+#define K21B_SECAM ((uint16_t)6u)
+#define K21B_NTSC_443_60 ((uint16_t)6u)
+#define K21B_PAL_60 ((uint16_t)10u)
+
+#define K23B_NTSC_3_58 ((uint16_t)6u)
+#define K23B_NTSC_4_43 ((uint16_t)6u)
+#define K23B_PAL_4_43 ((uint16_t)3u)
+#define K23B_PAL_M ((uint16_t)3u)
+#define K23B_PAL_N ((uint16_t)3u)
+#define K23B_SECAM ((uint16_t)3u)
+#define K23B_NTSC_443_60 ((uint16_t)6u)
+#define K23B_PAL_60 ((uint16_t)3u)
+
+#define K23A_NTSC_3_58 ((uint16_t)3u)
+#define K23A_NTSC_4_43 ((uint16_t)3u)
+#define K23A_PAL_4_43 ((uint16_t)3u)
+#define K23A_PAL_M ((uint16_t)3u)
+#define K23A_PAL_N ((uint16_t)3u)
+#define K23A_SECAM ((uint16_t)3u)
+#define K23A_NTSC_443_60 ((uint16_t)3u)
+#define K23A_PAL_60 ((uint16_t)3u)
+
+#define K24_NTSC_3_58 ((uint16_t)5u)
+#define K24_NTSC_4_43 ((uint16_t)5u)
+#define K24_PAL_4_43 ((uint16_t)8u)
+#define K24_PAL_M ((uint16_t)8u)
+#define K24_PAL_N ((uint16_t)8u)
+#define K24_SECAM ((uint16_t)8u)
+#define K24_NTSC_443_60 ((uint16_t)5u)
+#define K24_PAL_60 ((uint16_t)8u)
+
+/* SyncSep */
+#define SYNCMAXDUTY_H_VALUE ((uint16_t)15u)
+#define SYNCMINDUTY_H_VALUE ((uint16_t)10u)
+#define CSYNCSLICE_H_VALUE ((uint16_t)146u)
+#define SYNCMAXDUTY_V_VALUE ((uint16_t)15u)
+#define SYNCMINDUTY_V_VALUE ((uint16_t)9u)
+#define VSYNCSLICE_VALUE ((uint16_t)10u)
+#define CSYNCSLICE_V_VALUE ((uint16_t)146u)
+#define HAFCGAIN_VALUE ((uint16_t)12u)
+#define HAFCSTART_VALUE ((uint16_t)0u)
+#define HAFCEND_VALUE ((uint16_t)8u)
+#define AGCRESPONSE_VALUE ((uint16_t)4u)
+#define AGCPRECIS_VALUE ((uint16_t)10u)
+#define PGA_GAIN_VALUE ((uint16_t)0u)
+#define PEAKATTACK_VALUE ((uint16_t)2u)
+#define PEAKRELEASE_VALUE ((uint16_t)3u)
+#define MAXPEAKSAMPLES_VALUE ((uint16_t)20u)
+
+/* YcSep */
+#define RADJ_O_LEVEL0_VALUE ((uint16_t)928u)
+#define RADJ_U_LEVEL0_VALUE ((uint16_t)32u)
+#define RADJ_O_LEVEL1_VALUE ((uint16_t)960u)
+#define RADJ_U_LEVEL1_VALUE ((uint16_t)48u)
+#define RADJ_O_LEVEL2_VALUE ((uint16_t)992u)
+#define RADJ_U_LEVEL2_VALUE ((uint16_t)64u)
+#define V_Y_LEVEL_VALUE ((uint16_t)0u)
+
+/* ChromaDec */
+#define LUMADELAY_VALUE ((uint16_t)0u)
+#define LOOPGAIN_VALUE ((uint16_t)3u)
+#define LOCKLIMIT_VALUE ((uint16_t)1u)
+#define BGPCHECK_VALUE ((uint16_t)0u)
+#define BGPWIDTH_VALUE ((uint16_t)54u)
+#define BGPSTART_VALUE ((uint16_t)110u)
+#define CHROMAMAINGAIN_VALUE ((uint16_t)210u)
+#define ACCRESPONSE_VALUE ((uint16_t)1u)
+#define ACCPRECIS_VALUE ((uint16_t)8u)
+#define KILLERLEVEL_VALUE ((uint16_t)4u)
+#define KILLEROFFSET_VALUE ((uint16_t)5u)
+
+/* DigitalClamp */
+#define BLANKLEVEL_Y_VALUE ((uint16_t)984u)
+#define DCPPOS_Y_VALUE ((uint16_t)162u)
+#define BLANKLEVEL_CB_VALUE ((uint16_t)0u)
+#define BLANKLEVEL_CR_VALUE ((uint16_t)0u)
+#define DCPPOS_C_VALUE ((uint16_t)54u)
+#define ACFLAGTIME_VALUE ((uint16_t)0u)
+#define ACFFILTER_VALUE ((uint16_t)3u)
+#define DCPRESPONSE_VALUE ((uint16_t)0u)
+#define DCPSTART_VALUE ((uint16_t)16u)
+#define DCPEND_VALUE ((uint16_t)16u)
+#define DCPWIDTH_VALUE ((uint16_t)27u)
+
+/* Output */
+#define Y_GAIN2_VALUE ((uint16_t)816u)
+#define CB_GAIN2_VALUE ((uint16_t)663u)
+#define CR_GAIN2_VALUE ((uint16_t)663u)
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! Video decoder recommended value */
+typedef struct {
+ /* Capturing position setting */
+ uint16_t srcleft;
+ uint16_t srctop;
+ uint16_t srcheight;
+ uint16_t srcwidth;
+ /* Horizontal AFC setting */
+ uint16_t hafctyp;
+ uint16_t hafcmax;
+ uint16_t hafcmin;
+ /* Vertical countdown setting */
+ vdec_onoff_t novcd50_;
+ vdec_onoff_t novcd60_;
+ vdec_vcddefault_t vcddefault;
+ uint16_t vcdwindow;
+ uint16_t vcdoffset;
+ /* BCO setting */
+ vdec_color_sys_t defaultsys;
+ vdec_onoff_t nontsc358_;
+ vdec_onoff_t nontsc443_;
+ vdec_onoff_t nopalm_;
+ vdec_onoff_t nopaln_;
+ vdec_onoff_t nopal443_;
+ vdec_onoff_t nosecam_;
+ /* ACC level setting */
+ uint16_t acclevel;
+ /* AGC level setting */
+ uint16_t agclevel;
+ /* Y/C separation setting */
+ uint16_t k15;
+ uint16_t k13;
+ uint16_t k11;
+ uint16_t k16;
+ uint16_t k14;
+ uint16_t k12;
+ uint16_t k22A;
+ uint16_t k21A;
+ uint16_t k22B;
+ uint16_t k21B;
+ uint16_t k23B;
+ uint16_t k23A;
+ uint16_t k24;
+ vdec_onoff_t det2_on;
+ vdec_filmix_ratio_t hsel_mix_y;
+ vdec_filmix_ratio_t vsel_mix_y;
+ vdec_filmix_ratio_t hvsel_mix_y;
+ vdec_filmix_ratio_t det2_mix_c;
+ vdec_filmix_ratio_t det2_mix_y;
+ vdec_2dfil_mdsel_t fil2_mode_2d;
+ vdec_2d_fil_sel_t fil2_narrow_2d;
+} video_recmd_val_t;
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void Input(const graphics_col_sys_t color_system, const vdec_channel_t channel);
+static void SyncSep(const graphics_col_sys_t color_system, const vdec_channel_t channel);
+static void YcSep(const graphics_col_sys_t color_system, const vdec_channel_t channel);
+static void ChromaDec(const graphics_col_sys_t color_system, const vdec_channel_t channel);
+static void DigitalClamp(const vdec_channel_t channel);
+static void Output(const vdec_channel_t channel);
+
+static void init_func(const uint32_t user_num);
+
+static const video_recmd_val_t RecommendedValue[GRPH_COL_SYS_NUM] = {
+ { /* NTSC-3.58 */
+ /* Capturing position setting */
+ SRCLEFT_NTSC_3_58, SRCTOP_NTSC_3_58, SRCHEIGHT_NTSC_3_58, SRCWIDTH_NTSC_3_58,
+ /* Horizontal AFC setting */
+ HAFCTYP_NTSC_3_58, HAFCMAX_NTSC_3_58, HAFCMIN_NTSC_3_58,
+ /* Vertical countdown setting */
+ VDEC_OFF, VDEC_ON, VDEC_VCD_FRQ_59_94HZ, VCDWINDOW_NTSC_3_58, VCDOFFSET_NTSC_3_58,
+ /* BCO setting */
+ VDEC_COL_SYS_NTSC, VDEC_ON, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF,
+ /* ACC level setting */
+ ACCLEVEL_NTSC_3_58,
+ /* AGC level setting */
+ AGCLEVEL_NTSC_3_58,
+ /* Y/C separation setting */
+ K15_NTSC_3_58, K13_NTSC_3_58, K11_NTSC_3_58, K16_NTSC_3_58, K14_NTSC_3_58, K12_NTSC_3_58,
+ K22A_NTSC_3_58, K21A_NTSC_3_58, K22B_NTSC_3_58, K21B_NTSC_3_58, K23B_NTSC_3_58, K23A_NTSC_3_58, K24_NTSC_3_58,
+ VDEC_ON, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_0,
+ VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_25, VDEC_2DFIL_MDSEL_CASCADE, VDEC_2D_FIL_SEL_17TAP
+ },
+ { /* NTSC-4.43 */
+ /* Capturing position setting */
+ SRCLEFT_NTSC_4_43, SRCTOP_NTSC_4_43, SRCHEIGHT_NTSC_4_43, SRCWIDTH_NTSC_4_43,
+ /* Horizontal AFC setting */
+ HAFCTYP_NTSC_4_43, HAFCMAX_NTSC_4_43, HAFCMIN_NTSC_4_43,
+ /* Vertical countdown setting */
+ VDEC_ON, VDEC_OFF, VDEC_VCD_FRQ_50HZ, VCDWINDOW_NTSC_4_43, VCDOFFSET_NTSC_4_43,
+ /* BCO setting */
+ VDEC_COL_SYS_NTSC, VDEC_OFF, VDEC_ON, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF,
+ /* ACC level setting */
+ ACCLEVEL_NTSC_4_43,
+ /* AGC level setting */
+ AGCLEVEL_NTSC_4_43,
+ /* Y/C separation setting */
+ K15_NTSC_4_43, K13_NTSC_4_43, K11_NTSC_4_43, K16_NTSC_4_43, K14_NTSC_4_43, K12_NTSC_4_43,
+ K22A_NTSC_4_43, K21A_NTSC_4_43, K22B_NTSC_4_43, K21B_NTSC_4_43, K23B_NTSC_4_43, K23A_NTSC_4_43, K24_NTSC_4_43,
+ VDEC_ON, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_0,
+ VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_25, VDEC_2DFIL_MDSEL_CASCADE, VDEC_2D_FIL_SEL_17TAP
+ },
+ { /* PAL-4.43 */
+ /* Capturing position setting */
+ SRCLEFT_PAL_4_43, SRCTOP_PAL_4_43, SRCHEIGHT_PAL_4_43, SRCWIDTH_PAL_4_43,
+ /* Horizontal AFC setting */
+ HAFCTYP_PAL_4_43, HAFCMAX_PAL_4_43, HAFCMIN_PAL_4_43,
+ /* Vertical countdown setting */
+ VDEC_ON, VDEC_OFF, VDEC_VCD_FRQ_50HZ, VCDWINDOW_PAL_4_43, VCDOFFSET_PAL_4_43,
+ /* BCO setting */
+ VDEC_COL_SYS_PAL, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_ON, VDEC_OFF,
+ /* ACC level setting */
+ ACCLEVEL_PAL_4_43,
+ /* AGC level setting */
+ AGCLEVEL_PAL_4_43,
+ /* Y/C separation setting */
+ K15_PAL_4_43, K13_PAL_4_43, K11_PAL_4_43, K16_PAL_4_43, K14_PAL_4_43, K12_PAL_4_43,
+ K22A_PAL_4_43, K21A_PAL_4_43, K22B_PAL_4_43, K21B_PAL_4_43, K23B_PAL_4_43, K23A_PAL_4_43, K24_PAL_4_43,
+ VDEC_OFF, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0,
+ VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_2DFIL_MDSEL_BYPASS, VDEC_2D_FIL_SEL_17TAP
+ },
+ { /* PAL-M */
+ /* Capturing position setting */
+ SRCLEFT_PAL_M, SRCTOP_PAL_M, SRCHEIGHT_PAL_M, SRCWIDTH_PAL_M,
+ /* Horizontal AFC setting */
+ HAFCTYP_PAL_M, HAFCMAX_PAL_M, HAFCMIN_PAL_M,
+ /* Vertical countdown setting */
+ VDEC_OFF, VDEC_ON, VDEC_VCD_FRQ_59_94HZ, VCDWINDOW_PAL_M, VCDOFFSET_PAL_M,
+ /* BCO setting */
+ VDEC_COL_SYS_PAL, VDEC_OFF, VDEC_OFF, VDEC_ON, VDEC_OFF, VDEC_OFF, VDEC_OFF,
+ /* ACC level setting */
+ ACCLEVEL_PAL_M,
+ /* AGC level setting */
+ AGCLEVEL_PAL_M,
+ /* Y/C separation setting */
+ K15_PAL_M, K13_PAL_M, K11_PAL_M, K16_PAL_M, K14_PAL_M, K12_PAL_M,
+ K22A_PAL_M, K21A_PAL_M, K22B_PAL_M, K21B_PAL_M, K23B_PAL_M, K23A_PAL_M, K24_PAL_M,
+ VDEC_OFF, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0,
+ VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_2DFIL_MDSEL_BYPASS, VDEC_2D_FIL_SEL_17TAP
+ },
+ { /* PAL-N */
+ /* Capturing position setting */
+ SRCLEFT_PAL_N, SRCTOP_PAL_N, SRCHEIGHT_PAL_N, SRCWIDTH_PAL_N,
+ /* Horizontal AFC setting */
+ HAFCTYP_PAL_N, HAFCMAX_PAL_N, HAFCMIN_PAL_N,
+ /* Vertical countdown setting */
+ VDEC_ON, VDEC_OFF, VDEC_VCD_FRQ_50HZ, VCDWINDOW_PAL_N, VCDOFFSET_PAL_N,
+ /* BCO setting */
+ VDEC_COL_SYS_PAL, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_ON, VDEC_OFF, VDEC_OFF,
+ /* ACC level setting */
+ ACCLEVEL_PAL_N,
+ /* AGC level setting */
+ AGCLEVEL_PAL_N,
+ /* Y/C separation setting */
+ K15_PAL_N, K13_PAL_N, K11_PAL_N, K16_PAL_N, K14_PAL_N, K12_PAL_N,
+ K22A_PAL_N, K21A_PAL_N, K22B_PAL_N, K21B_PAL_N, K23B_PAL_N, K23A_PAL_N, K24_PAL_N,
+ VDEC_OFF, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0,
+ VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_2DFIL_MDSEL_BYPASS, VDEC_2D_FIL_SEL_17TAP
+ },
+ { /* SECAM */
+ /* Capturing position setting */
+ SRCLEFT_SECAM, SRCTOP_SECAM, SRCHEIGHT_SECAM, SRCWIDTH_SECAM,
+ /* Horizontal AFC setting */
+ HAFCTYP_SECAM, HAFCMAX_SECAM, HAFCMIN_SECAM,
+ /* Vertical countdown setting */
+ VDEC_ON, VDEC_OFF, VDEC_VCD_FRQ_50HZ, VCDWINDOW_SECAM, VCDOFFSET_SECAM,
+ /* BCO setting */
+ VDEC_COL_SYS_SECAM, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_ON,
+ /* ACC level setting */
+ ACCLEVEL_SECAM,
+ /* AGC level setting */
+ AGCLEVEL_SECAM,
+ /* Y/C separation setting */
+ K15_SECAM, K13_SECAM, K11_SECAM, K16_SECAM, K14_SECAM, K12_SECAM,
+ K22A_SECAM, K21A_SECAM, K22B_SECAM, K21B_SECAM, K23B_SECAM, K23A_SECAM, K24_SECAM,
+ VDEC_ON, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_0,
+ VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_2DFIL_MDSEL_CASCADE, VDEC_2D_FIL_SEL_17TAP
+ },
+ { /* NTSC-4.43 (60Hz) */
+ /* Capturing position setting */
+ SRCLEFT_NTSC_443_60, SRCTOP_NTSC_443_60, SRCHEIGHT_NTSC_443_60, SRCWIDTH_NTSC_443_60,
+ /* Horizontal AFC setting */
+ HAFCTYP_NTSC_443_60, HAFCMAX_NTSC_443_60, HAFCMIN_NTSC_443_60,
+ /* Vertical countdown setting */
+ VDEC_OFF, VDEC_ON, VDEC_VCD_FRQ_59_94HZ, VCDWINDOW_NTSC_443_60, VCDOFFSET_NTSC_443_60,
+ /* BCO setting */
+ VDEC_COL_SYS_NTSC, VDEC_OFF, VDEC_ON, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF,
+ /* ACC level setting */
+ ACCLEVEL_NTSC_443_60,
+ /* AGC level setting */
+ AGCLEVEL_NTSC_443_60,
+ /* Y/C separation setting */
+ K15_NTSC_443_60, K13_NTSC_443_60, K11_NTSC_443_60, K16_NTSC_443_60, K14_NTSC_443_60, K12_NTSC_443_60,
+ K22A_NTSC_443_60, K21A_NTSC_443_60, K22B_NTSC_443_60, K21B_NTSC_443_60, K23B_NTSC_443_60, K23A_NTSC_443_60,
+ K24_NTSC_443_60,
+ VDEC_ON, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_0,
+ VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_25, VDEC_2DFIL_MDSEL_CASCADE, VDEC_2D_FIL_SEL_17TAP
+ },
+ { /* PAL-60 */
+ /* Capturing position setting */
+ SRCLEFT_PAL_60, SRCTOP_PAL_60, SRCHEIGHT_PAL_60, SRCWIDTH_PAL_60,
+ /* Horizontal AFC setting */
+ HAFCTYP_PAL_60, HAFCMAX_PAL_60, HAFCMIN_PAL_60,
+ /* Vertical countdown setting */
+ VDEC_OFF, VDEC_ON, VDEC_VCD_FRQ_59_94HZ, VCDWINDOW_PAL_60, VCDOFFSET_PAL_60,
+ /* BCO setting */
+ VDEC_COL_SYS_PAL, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_ON, VDEC_OFF,
+ /* ACC level setting */
+ ACCLEVEL_PAL_60,
+ /* AGC level setting */
+ AGCLEVEL_PAL_60,
+ /* Y/C separation setting */
+ K15_PAL_60, K13_PAL_60, K11_PAL_60, K16_PAL_60, K14_PAL_60, K12_PAL_60,
+ K22A_PAL_60, K21A_PAL_60, K22B_PAL_60, K21B_PAL_60, K23B_PAL_60, K23A_PAL_60, K24_PAL_60,
+ VDEC_OFF, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0,
+ VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_2DFIL_MDSEL_BYPASS, VDEC_2D_FIL_SEL_17TAP
+ }
+};
+/* Two-Dimensional Cascade Broadband and Narrowband (3.58/4.43) Filter TAP Coefficient */
+static const vdec_chrfil_tap_t wana_ntsc = {
+ {
+ (uint16_t)24u, (uint16_t)44u, (uint16_t)20u, (uint16_t)(0x1000u | 52u), (uint16_t)(0x1000u | 128u),
+ (uint16_t)(0x1000u | 128u), (uint16_t)(0x1000u | 12u), (uint16_t)132u, (uint16_t)200u
+ }
+};
+/* Two-Dimensional Cascade Broadband (SECAM-DR) Filter TAP Coefficient */
+static const vdec_chrfil_tap_t wa_secam = {
+ {
+ (uint16_t)(0x1000u | 20u), (uint16_t)24u, (uint16_t)64u, (uint16_t)40u, (uint16_t)(0x1000u | 76u),
+ (uint16_t)(0x1000u | 164u), (uint16_t)(0x1000u | 84u), (uint16_t)108u, (uint16_t)216u
+ }
+};
+/* Two-Dimensional Cascade Broadband (SECAM-DB) Filter TAP Coefficient */
+static const vdec_chrfil_tap_t wb_secam = {
+ {
+ (uint16_t)(0x1000u | 12u), (uint16_t)40u, (uint16_t)60u, (uint16_t)12u, (uint16_t)(0x1000u | 104u),
+ (uint16_t)(0x1000u | 156u), (uint16_t)(0x1000u | 64u), (uint16_t)120u, (uint16_t)208u
+ }
+};
+/* Two-Dimensional Cascade Narrowband (SECAM-DR) Filter TAP Coefficient */
+static const vdec_chrfil_tap_t na_secam = {
+ {
+ (uint16_t)(0x1000u | 1008u), (uint16_t)1976u, (uint16_t)(0x1000u | 2024u), (uint16_t)444u, (uint16_t)1868u,
+ (uint16_t)(0x1000u | 2864u), (uint16_t)1352u, (uint16_t)1376u, (uint16_t)(0x1000u | 2240u)
+ }
+};
+/* Two-Dimensional Cascade Narrowband (SECAM-DB) Filter TAP Coefficient */
+static const vdec_chrfil_tap_t nb_secam = {
+ {
+ (uint16_t)(0x1000u | 1080u), (uint16_t)2800u, (uint16_t)(0x1000u | 3308u), (uint16_t)1628u, (uint16_t)1444u,
+ (uint16_t)(0x1000u | 3308u), (uint16_t)2140u, (uint16_t)376u, (uint16_t)(0x1000u | 1384u)
+ }
+};
+
+
+/**************************************************************************//**
+ * @brief Video decoder initialization
+ * @param [in]adc_vinsel : Input pin control
+ * @param [in]channel : Channel
+ * @retval Detected color system
+ *****************************************************************************/
+vdec_error_t GRAPHICS_VideoDecoderInit (const vdec_adc_vinsel_t adc_vinsel, const vdec_channel_t channel, graphics_col_sys_t col_sys)
+{
+ vdec_error_t error = VDEC_OK;
+
+ /* Video Decoder Driver Initialization */
+ error = R_VDEC_Initialize(channel, adc_vinsel, &init_func, (uint32_t)channel);
+ if (error == VDEC_OK) {
+ if (col_sys != GRPH_COL_SYS_UNKNOWN) {
+ /* Input */
+ Input(col_sys, channel);
+ /* Sync separation */
+ SyncSep(col_sys, channel);
+ /* Y/C separation */
+ YcSep(col_sys, channel);
+ /* Chroma decoding */
+ ChromaDec(col_sys, channel);
+ /* Digital clamp */
+ DigitalClamp(channel);
+ /* Output */
+ Output(channel);
+ } else {
+ error = VDEC_ERR_PARAM;
+ }
+ }
+ return error;
+} /* End of function GRAPHICS_VideoDecoderInit() */
+
+
+/**************************************************************************//**
+ * @brief User-defined function
+ * @param [in]user_num
+ * @retval None
+ *****************************************************************************/
+static void init_func (const uint32_t user_num)
+{
+ uint32_t reg_data;
+ volatile uint8_t dummy_read;
+
+ reg_data = (uint32_t)CPG.STBCR7;
+ if ((vdec_channel_t)user_num == VDEC_CHANNEL_0) {
+ /* Standby control register 7 (STBCR7)
+ b7 0-------; MSTP77 : 0 : Video decoder channel 0 enable */
+ reg_data &= (uint32_t)~STBCR7_BIT7;
+ } else {
+ /* Standby control register 7 (STBCR7)
+ b6 -0------; MSTP76 : 0 : Video decoder channel 1 enable */
+ reg_data &= (uint32_t)~STBCR7_BIT6;
+ }
+ CPG.STBCR7 = (uint8_t)reg_data;
+ /* In order to reflect the change, a dummy read should be done. */
+ dummy_read = CPG.STBCR7;
+} /* End of function init_func() */
+
+/**************************************************************************//**
+ * @brief Video decoder input setup
+ * @param [in]color_system : Color system
+ * @param [in]channel : Channel
+ * @retval None
+ *****************************************************************************/
+static void Input (const graphics_col_sys_t color_system, const vdec_channel_t channel)
+{
+ vdec_error_t error;
+ vdec_active_period_t param;
+ const video_recmd_val_t * RecommendValTbl;
+
+ RecommendValTbl = &RecommendedValue[color_system];
+
+ param.srcleft = RecommendValTbl->srcleft; /* Left end of input video signal capturing area */
+ param.srctop = RecommendValTbl->srctop; /* Top end of input video signal capturing area */
+ param.srcheight = RecommendValTbl->srcheight; /* Height of input video signal capturing area */
+ param.srcwidth = RecommendValTbl->srcwidth; /* Width of input video signal capturing area */
+ /* Video decoder driver input */
+ error = R_VDEC_ActivePeriod(channel, ¶m);
+ if (error != VDEC_OK) {
+ }
+} /* End of function Input() */
+
+/**************************************************************************//**
+ * @brief Video decoder sync separation setup
+ * @param [in]color_system : Color system
+ * @param [in]channel : Channel
+ * @retval None
+ *****************************************************************************/
+static void SyncSep (const graphics_col_sys_t color_system, const vdec_channel_t channel)
+{
+ vdec_error_t error;
+ vdec_sync_separation_t param;
+ vdec_noise_rd_lpf_t noise_rd_lpf_tmp;
+ vdec_sync_slicer_t sync_slicer_tmp;
+ vdec_horizontal_afc_t horizontal_afc_tmp;
+ vdec_vcount_down_t vcount_down_tmp;
+ vdec_agc_t agc_tmp;
+ vdec_peak_limiter_t peak_limiter_tmp;
+ const video_recmd_val_t * RecommendValTbl;
+
+ RecommendValTbl = &RecommendedValue[color_system];
+
+ /* Noise reduction LPF */
+ noise_rd_lpf_tmp.lpfvsync = VDEC_LPF_VSYNC_0_54; /* LPF cutoff frequency before vertical sync separation */
+ noise_rd_lpf_tmp.lpfhsync = VDEC_LPF_HSYNC_0_94; /* LPF cutoff frequency before horizontal sync separation */
+ /* Sync slicer */
+ sync_slicer_tmp.velocityshift_h = VDEC_VELOCITY_SHIFT_4; /* Reference level operation speed control for
+ composite sync separation (for Hsync signal) */
+ sync_slicer_tmp.slicermode_h = VDEC_SLICE_MODE_AUTO_50; /* Auto-slice level setting for composite sync
+ separator circuit (for Hsync signal) */
+ sync_slicer_tmp.slicermode_v = VDEC_SLICE_MODE_AUTO_50; /* Auto-slice level setting for composite sync
+ separation circuit (for Vsync signal) */
+ sync_slicer_tmp.syncmaxduty_h = SYNCMAXDUTY_H_VALUE; /* Max ratio of horizontal cycle to horizontal sync
+ signal pulse width (for Hsync signal) */
+ sync_slicer_tmp.syncminduty_h = SYNCMINDUTY_H_VALUE; /* Min ratio of horizontal cycle to horizontal sync
+ signal pulse width (for Hsync signal) */
+ sync_slicer_tmp.ssclipsel = VDEC_CLIP_LV_1023; /* Clipping level */
+ sync_slicer_tmp.csyncslice_h = CSYNCSLICE_H_VALUE; /* Slice level for composite sync
+ signal separation (for Hsync signal) */
+ sync_slicer_tmp.syncmaxduty_v = SYNCMAXDUTY_V_VALUE; /* Max ratio of horizontal cycle to horizontal sync
+ signal pulse width (for Vsync signal) */
+ sync_slicer_tmp.syncminduty_v = SYNCMINDUTY_V_VALUE; /* Min ratio of horizontal cycle to horizontal sync
+ signal pulse width (for Vsync signal) */
+ sync_slicer_tmp.vsyncdelay = VDEC_OFF; /* Delays the separated vertical sync signal for
+ 1/4 horizontal cycle */
+ sync_slicer_tmp.vsyncslice = VSYNCSLICE_VALUE; /* Threshold for vertical sync separation */
+ sync_slicer_tmp.csyncslice_v = CSYNCSLICE_V_VALUE; /* Slice level for composite sync
+ signal separation (for Vsync signal) */
+ /* Horizontal AFC */
+ horizontal_afc_tmp.hafcgain = HAFCGAIN_VALUE; /* Horizontal AFC loop gain */
+ horizontal_afc_tmp.hafctyp = RecommendValTbl->hafctyp; /* Horizontal AFC center oscillation frequency */
+ horizontal_afc_tmp.hafcstart = HAFCSTART_VALUE; /* Start line of horizontal AFC normal operation */
+ horizontal_afc_tmp.nox2hosc = VDEC_ON; /* Disable of horizontal AFC double speed detection */
+ horizontal_afc_tmp.hafcmax = RecommendValTbl->hafcmax; /* Maximum oscillation frequency of horizontal AFC */
+ horizontal_afc_tmp.hafcend = HAFCEND_VALUE; /* End line of horizontal AFC normal operation */
+ horizontal_afc_tmp.hafcmode = VDEC_HAFCMD_AUTO_PHST; /* Horizontal AFC VBI period operating mode */
+ horizontal_afc_tmp.hafcmin = RecommendValTbl->hafcmin; /* Min oscillation frequency of horizontal AFC */
+ horizontal_afc_tmp.phdet_fix = VDEC_OFF; /* Forcible or LOWGAIN control */
+ horizontal_afc_tmp.phdet_div = VDEC_PHDET_DIV_1_32; /* Phase comparator feedback adjust for
+ low sync signal lock stability */
+ /* Vertical countdown */
+ vcount_down_tmp.novcd50_ = RecommendValTbl->novcd50_; /* Vertical countdown 50-Hz oscillation mode */
+ vcount_down_tmp.novcd60_ = RecommendValTbl->novcd60_; /* Vertical countdown 60-Hz (59.94-Hz)
+ oscillation mode */
+ vcount_down_tmp.vcddefault = RecommendValTbl->vcddefault; /* Vertical countdown center oscillation frequency */
+ vcount_down_tmp.vcdwindow = RecommendValTbl->vcdwindow; /* Vertical countdown sync area */
+ vcount_down_tmp.vcdoffset = RecommendValTbl->vcdoffset; /* Vertical countdown minimum oscillation frequency */
+ /* AGC / PGA */
+ agc_tmp.agcmode = VDEC_ON; /* A/D converter AGC ON/OFF control & PGA gain select */
+ agc_tmp.doreduce = VDEC_OFF; /* Manual control of sync signal amplitude detection
+ during VBI period */
+ agc_tmp.noreduce_ = VDEC_ON; /* Control of sync signal amplitude detection during VBI period */
+ agc_tmp.agcresponse = AGCRESPONSE_VALUE; /* AGC response speed */
+ agc_tmp.agclevel = RecommendValTbl->agclevel;/* Sync signal reference amplitude */
+ agc_tmp.agcprecis = AGCPRECIS_VALUE; /* AGC gain adjustment accuracy */
+ agc_tmp.pga_gain = PGA_GAIN_VALUE; /* PGA gain */
+ /* Peak limiter control */
+ peak_limiter_tmp.peaklevel = VDEC_PEAKLV_992; /* Peak luminance value to operate peak limiter */
+ peak_limiter_tmp.peakattack = PEAKATTACK_VALUE; /* Response speed with peak limiter gain decreased */
+ peak_limiter_tmp.peakrelease = PEAKRELEASE_VALUE; /* Response speed with peak limiter gain increased */
+ peak_limiter_tmp.peakratio = VDEC_PEAKRATIO_50; /* Maximum compression rate of peak limiter */
+ peak_limiter_tmp.maxpeaksamples = MAXPEAKSAMPLES_VALUE; /* Allowable number of overflowing pixels */
+
+ param.noise_rd_lpf = &noise_rd_lpf_tmp; /* Noise reduction LPF */
+ param.sync_slicer = &sync_slicer_tmp; /* Sync slicer */
+ param.horizontal_afc = &horizontal_afc_tmp; /* Horizontal AFC */
+ param.vcount_down = &vcount_down_tmp; /* Vertical countdown */
+ param.agc = &agc_tmp; /* AGC / PGA */
+ param.peak_limiter = &peak_limiter_tmp; /* Peak limiter control */
+ /* Video decoder driver sync separation */
+ error = R_VDEC_SyncSeparation(channel, ¶m);
+ if (error != VDEC_OK) {
+ }
+} /* End of function SyncSep() */
+
+/**************************************************************************//**
+ * @brief Video decoder Y/C separation setup
+ * @param [in]color_system : Color system
+ * @param [in]channel : Channel
+ * @retval None
+ *****************************************************************************/
+static void YcSep (const graphics_col_sys_t color_system, const vdec_channel_t channel)
+{
+ vdec_error_t error;
+ vdec_yc_separation_t param;
+ vdec_over_range_t over_range_tmp;
+ vdec_yc_sep_ctrl_t yc_sep_ctrl_tmp;
+ const video_recmd_val_t * RecommendValTbl;
+
+ RecommendValTbl = &RecommendedValue[color_system];
+
+ /* Over-range control */
+ over_range_tmp.radj_o_level0 = RADJ_O_LEVEL0_VALUE; /* A/D over-threshold level (between levels 0 and 1) */
+ over_range_tmp.radj_u_level0 = RADJ_U_LEVEL0_VALUE; /* A/D under-threshold level (between levels 2 and 3) */
+ over_range_tmp.radj_o_level1 = RADJ_O_LEVEL1_VALUE; /* A/D over-threshold level (between levels 1 and 2) */
+ over_range_tmp.radj_u_level1 = RADJ_U_LEVEL1_VALUE; /* A/D under-threshold level (between levels 1 and 2) */
+ over_range_tmp.radj_o_level2 = RADJ_O_LEVEL2_VALUE; /* A/D over-threshold level (between levels 2 and 3) */
+ over_range_tmp.radj_u_level2 = RADJ_U_LEVEL2_VALUE; /* A/D under-threshold level (between levels 0 and 1) */
+ over_range_tmp.ucmp_sw = VDEC_ON; /* Over-range detection */
+ over_range_tmp.dcmp_sw = VDEC_ON; /* Under-range detection */
+ over_range_tmp.hwide_sw = VDEC_ON; /* Horizontal enlargement of over/under-range level */
+ /* Y/C separation control */
+ /* Two-dimensional Y/C separation filter select coefficient */
+ yc_sep_ctrl_tmp.k15 = RecommendValTbl->k15; /* K15 */
+ yc_sep_ctrl_tmp.k13 = RecommendValTbl->k13; /* K13 */
+ yc_sep_ctrl_tmp.k11 = RecommendValTbl->k11; /* K11 */
+ yc_sep_ctrl_tmp.k16 = RecommendValTbl->k16; /* K16 */
+ yc_sep_ctrl_tmp.k14 = RecommendValTbl->k14; /* K14 */
+ yc_sep_ctrl_tmp.k12 = RecommendValTbl->k12; /* K12 */
+ yc_sep_ctrl_tmp.k22a = RecommendValTbl->k22A; /* K22A */
+ yc_sep_ctrl_tmp.k21a = RecommendValTbl->k21A; /* K21A */
+ yc_sep_ctrl_tmp.k22b = RecommendValTbl->k22B; /* K22B */
+ yc_sep_ctrl_tmp.k21b = RecommendValTbl->k21B; /* K21B */
+ yc_sep_ctrl_tmp.k23b = RecommendValTbl->k23B; /* K23B */
+ yc_sep_ctrl_tmp.k23a = RecommendValTbl->k23A; /* K23A */
+ yc_sep_ctrl_tmp.k24 = RecommendValTbl->k24; /* K24 */
+ yc_sep_ctrl_tmp.hbpf_narrow = VDEC_LSTG_BPFSEL_BYPASS; /* Latter-stage horizontal BPF select */
+ yc_sep_ctrl_tmp.hvbpf_narrow = VDEC_LSTG_BPFSEL_BYPASS; /* Latter-stage horizontal/vertical BPF select */
+ yc_sep_ctrl_tmp.hbpf1_9tap_on = VDEC_FSTG_BPFSEL_17TAP; /* Former-stage horizontal BPF select */
+ yc_sep_ctrl_tmp.hvbpf1_9tap_on = VDEC_FSTG_BPFSEL_17TAP; /* Former-stage horizontal/vertical BPF select */
+ yc_sep_ctrl_tmp.hfil_tap_sel = VDEC_HFIL_TAP_SEL_17TAP; /* Horizontal filter and horizontal/vertical filter
+ bandwidth switch signal */
+ yc_sep_ctrl_tmp.det2_on = RecommendValTbl->det2_on; /* Two-dimensional filter mixing select */
+ yc_sep_ctrl_tmp.hsel_mix_y = RecommendValTbl->hsel_mix_y; /* Mixing ratio of signal after passing
+ horizontal filter to signal after passing
+ former-stage horizontal filter */
+ yc_sep_ctrl_tmp.vsel_mix_y = RecommendValTbl->vsel_mix_y; /* Mixing ratio of signal after passing
+ vertical filter to signal after passing
+ former-stage horizontal/vertical filter */
+ yc_sep_ctrl_tmp.hvsel_mix_y = RecommendValTbl->hvsel_mix_y; /* Mixing ratio of signal after passing
+ horizontal/vertical filter to signal
+ after passing former-stage
+ horizontal/vertical filter */
+ yc_sep_ctrl_tmp.v_y_level = V_Y_LEVEL_VALUE; /* Vertical luminance detection level
+ for correlation detection filter */
+ yc_sep_ctrl_tmp.det2_mix_c = RecommendValTbl->det2_mix_c; /* Mixing ratio of c signal after passing
+ horizontal/vertical adaptive filter
+ to signal after passing correlation detection
+ filter */
+ yc_sep_ctrl_tmp.det2_mix_y = RecommendValTbl->det2_mix_y; /* Mixing ratio of c signal for y generation after
+ passing horizontal/vertical adaptive filter to
+ signal after passing correlation */
+ yc_sep_ctrl_tmp.fil2_mode_2d = RecommendValTbl->fil2_mode_2d;/* Two-dimensional cascade/TAKE-OFF
+ filter mode select */
+ yc_sep_ctrl_tmp.fil2_narrow_2d = RecommendValTbl->fil2_narrow_2d; /* Two-dimensional cascade filter select */
+
+ param.over_range = &over_range_tmp; /* Over-range control */
+ param.yc_sep_ctrl = &yc_sep_ctrl_tmp; /* Y/C separation control */
+ param.fil2_2d_wa = NULL; /* Two-dimensional cascade broadband
+ (3.58/4.43/SECAM-DR)/TAKE-OFF filter TAP coefficient */
+ param.fil2_2d_wb = NULL; /* Two-dimensional cascade broadband (SECAM-DB) filter TAP coefficient */
+ param.fil2_2d_na = NULL; /* Two-dimensional cascade narrowband
+ (3.58/4.43/SECAM-DR) filter TAP coefficient */
+ param.fil2_2d_nb = NULL; /* Two-dimensional cascade narrowband (SECAMDB) filter TAP coefficient */
+ if ((color_system == GRPH_COL_SYS_NTSC_358) ||
+ (color_system == GRPH_COL_SYS_NTSC_443) ||
+ (color_system == GRPH_COL_SYS_NTSC_443_60)) {
+ param.fil2_2d_wa = &wana_ntsc;
+ param.fil2_2d_na = &wana_ntsc;
+ } else if (color_system == GRPH_COL_SYS_SECAM) {
+ param.fil2_2d_wa = &wa_secam;
+ param.fil2_2d_wb = &wb_secam;
+ param.fil2_2d_na = &na_secam;
+ param.fil2_2d_nb = &nb_secam;
+ } else {
+ /* Do nothing */
+ }
+ /* Video decoder driver y/c separation */
+ error = R_VDEC_YcSeparation(channel, ¶m);
+ if (error != VDEC_OK) {
+ }
+} /* End of function YcSep() */
+
+/**************************************************************************//**
+ * @brief Video decoder chroma decoding setup
+ * @param [in]color_system : Color system
+ * @param [in]channel : Channel
+ * @retval None
+ *****************************************************************************/
+static void ChromaDec (const graphics_col_sys_t color_system, const vdec_channel_t channel)
+{
+ vdec_error_t error;
+ vdec_chroma_decoding_t param;
+ vdec_chrmdec_ctrl_t chrmdec_ctrl_tmp;
+ vdec_burst_lock_t burst_lock_tmp;
+ vdec_acc_t acc_tmp;
+ const video_recmd_val_t * RecommendValTbl;
+
+ RecommendValTbl = &RecommendedValue[color_system];
+
+ /* Chroma decoding control */
+ chrmdec_ctrl_tmp.defaultsys = RecommendValTbl->defaultsys; /* Default color system */
+ chrmdec_ctrl_tmp.nontsc358_ = RecommendValTbl->nontsc358_; /* NTSC-M detection control */
+ chrmdec_ctrl_tmp.nontsc443_ = RecommendValTbl->nontsc443_; /* NTSC-4.43 detection control */
+ chrmdec_ctrl_tmp.nopalm_ = RecommendValTbl->nopalm_; /* PAL-M detection control */
+ chrmdec_ctrl_tmp.nopaln_ = RecommendValTbl->nopaln_; /* PAL-N detection control */
+ chrmdec_ctrl_tmp.nopal443_ = RecommendValTbl->nopal443_; /* PAL-B, G, H, I, D detection control */
+ chrmdec_ctrl_tmp.nosecam_ = RecommendValTbl->nosecam_; /* SECAM detection control */
+ chrmdec_ctrl_tmp.lumadelay = LUMADELAY_VALUE; /* Luminance signal delay adjustment */
+ chrmdec_ctrl_tmp.chromalpf = VDEC_OFF; /* LPF for demodulated chroma */
+ chrmdec_ctrl_tmp.demodmode = VDEC_DEMOD_MD_PAL; /* Averaging processing for pre-demodulated line */
+ /* Burst lock */
+ burst_lock_tmp.lockrange = VDEC_LOCK_RANGE_800HZ;/* Burst lock PLL lock range */
+ burst_lock_tmp.loopgain = LOOPGAIN_VALUE; /* Burst lock PLL loop gain */
+ burst_lock_tmp.locklimit = LOCKLIMIT_VALUE; /* Level for burst lock PLL to re-search free-run frequency */
+ burst_lock_tmp.bgpcheck = BGPCHECK_VALUE; /* burst gate pulse position check */
+ burst_lock_tmp.bgpwidth = BGPWIDTH_VALUE; /* burst gate pulse width */
+ burst_lock_tmp.bgpstart = BGPSTART_VALUE; /* burst gate pulse start position */
+ /* ACC / color killer */
+ acc_tmp.accmode = VDEC_ACC_MD_AUTO; /* ACC operating mode */
+ acc_tmp.accmaxgain = VDEC_ACC_MAX_GAIN_6; /* Maximum ACC Gain */
+ acc_tmp.acclevel = RecommendValTbl->acclevel;/* ACC reference color burst amplitude */
+ acc_tmp.chromasubgain = VDEC_CHRM_SB_GAIN_1; /* Chroma manual gain (sub) */
+ acc_tmp.chromamaingain = CHROMAMAINGAIN_VALUE; /* Chroma manual gain (main) */
+ acc_tmp.accresponse = ACCRESPONSE_VALUE; /* ACC response speed */
+ acc_tmp.accprecis = ACCPRECIS_VALUE; /* ACC gain adjustment accuracy */
+ acc_tmp.killermode = VDEC_OFF; /* Forced color killer mode ON/OFF */
+ acc_tmp.killerlevel = KILLERLEVEL_VALUE; /* Color killer operation start point */
+ acc_tmp.killeroffset = KILLEROFFSET_VALUE; /* The offset level to turn off the color killer */
+
+ param.chrmdec_ctrl = &chrmdec_ctrl_tmp; /* Chroma decoding control */
+ param.burst_lock = &burst_lock_tmp; /* Burst lock */
+ param.acc = &acc_tmp; /* ACC/color killer */
+ param.tint_ry = NULL; /* TINT/R-Y axis correction (only valid for NTSC/PAL) */
+ /* Video decoder driver chroma decoding */
+ error = R_VDEC_ChromaDecoding(channel, ¶m);
+ if (error != VDEC_OK) {
+ }
+} /* End of function ChromaDec() */
+
+/**************************************************************************//**
+ * @brief Video decoder digital clamp setup
+ * @param [in]channel : Channel
+ * @retval None
+ *****************************************************************************/
+static void DigitalClamp (const vdec_channel_t channel)
+{
+ vdec_error_t error;
+ vdec_degital_clamp_t param;
+ vdec_pedestal_clamp_t pedestal_clamp_tmp;
+ vdec_center_clamp_t center_clamp_tmp;
+ vdec_noise_det_t noise_det_tmp;
+
+ /* Pedestal clamp */
+ pedestal_clamp_tmp.dcpmode_y = VDEC_DCPMODE_AUTO; /* Clamp level setting mode */
+ pedestal_clamp_tmp.blanklevel_y = BLANKLEVEL_Y_VALUE; /* Clamp offset level (Y signal) */
+ pedestal_clamp_tmp.dcppos_y = DCPPOS_Y_VALUE; /* Digital clamp pulse horizontal start position (Y signal) */
+ /* Center clamp */
+ center_clamp_tmp.dcpmode_c = VDEC_DCPMODE_MANUAL; /* Clamp level setting mode */
+ center_clamp_tmp.blanklevel_cb = BLANKLEVEL_CB_VALUE; /* Clamp offset level (Cb signal) */
+ center_clamp_tmp.blanklevel_cr = BLANKLEVEL_CR_VALUE; /* Clamp offset level (Cr signal) */
+ center_clamp_tmp.dcppos_c = DCPPOS_C_VALUE; /* Digital clamp pulse
+ horizontal start position (Cb/Cr signal) */
+ /* Noise detection */
+ noise_det_tmp.acfinput = VDEC_ACFINPUT_Y; /* Video signal for autocorrelation function */
+ noise_det_tmp.acflagtime = ACFLAGTIME_VALUE; /* Delay time for autocorrelation function calculation */
+ noise_det_tmp.acffilter = ACFFILTER_VALUE; /* Smoothing parameter of autocorrelation function data */
+
+ param.dcpcheck = VDEC_OFF; /* Digital clamp pulse position check */
+ param.dcpresponse = DCPRESPONSE_VALUE; /* Digital clamp response speed */
+ param.dcpstart = DCPSTART_VALUE; /* Digital clamp start line (in 1-line units) */
+ param.dcpend = DCPEND_VALUE; /* Digital clamp end line (in 1-line units) */
+ param.dcpwidth = DCPWIDTH_VALUE; /* Digital clamp pulse width */
+ param.pedestal_clamp = &pedestal_clamp_tmp; /* Pedestal clamp */
+ param.center_clamp = ¢er_clamp_tmp; /* Center clamp */
+ param.noise_det = &noise_det_tmp; /* Noise detection */
+ /* Video decoder driver digital clamp */
+ error = R_VDEC_DigitalClamp(channel, ¶m);
+ if (error != VDEC_OK) {
+ }
+} /* End of function DigitalClamp() */
+
+/**************************************************************************//**
+ * @brief Video decoder output adjustment setup
+ * @param [in]channel : Channel
+ * @retval None
+ *****************************************************************************/
+static void Output (const vdec_channel_t channel)
+{
+ vdec_error_t error;
+ vdec_output_t param;
+
+ param.y_gain2 = Y_GAIN2_VALUE; /* Y signal gain coefficient */
+ param.cb_gain2 = CB_GAIN2_VALUE; /* Cb signal gain coefficient */
+ param.cr_gain2 = CR_GAIN2_VALUE; /* Cr signal gain coefficient */
+ /* Video decoder driver output */
+ error = R_VDEC_Output(channel, ¶m);
+ if (error != VDEC_OK) {
+ }
+} /* End of function Output() */