gr_peach_vdc5.h

00001 /*******************************************************************************
00002 * DISCLAIMER
00003 * This software is supplied by Renesas Electronics Corporation and is only
00004 * intended for use with Renesas products. No other uses are authorized. This
00005 * software is owned by Renesas Electronics Corporation and is protected under
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00007 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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00009 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
00010 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
00011 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
00012 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
00013 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
00014 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
00015 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
00016 * Renesas reserves the right, without notice, to make changes to this software
00017 * and to discontinue the availability of this software. By using this software,
00018 * you agree to the additional terms and conditions found by accessing the
00019 * following link:
00020 * http://www.renesas.com/disclaimer
00021 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
00022 *******************************************************************************/
00023 /**************************************************************************//**
00024 * @file         gr_peach_vdc5.h
00025 * @version      1.00
00026 * $Rev: 199 $
00027 * $Date:: 2014-05-23 16:33:52 +0900#$
00028 * @brief        Graphics driver wrapper function definitions in C
00029 ******************************************************************************/
00030 
00031 #ifndef GR_PEACH_VDC5_H
00032 #define GR_PEACH_VDC5_H
00033 
00034 /******************************************************************************
00035 Includes   <System Includes> , "Project Includes"
00036 ******************************************************************************/
00037 #include    <stdlib.h>
00038 
00039 #include    "r_typedefs.h"
00040 #include    "r_vdc5.h"
00041 #include    "pinmap.h"
00042 
00043 #ifdef  __cplusplus
00044 extern  "C"
00045 {
00046 #endif  /* __cplusplus */
00047 
00048 /******************************************************************************
00049 Macro definitions
00050 ******************************************************************************/
00051 
00052 #define VSYNC_1_2_FH_TIMING    (858u)   /* Vsync signal 1/2fH phase timing */
00053 #define VSYNC_1_4_FH_TIMING    (429u)   /* Vsync signal 1/4fH phase timing */
00054 #define DEFAULT_INPUT_CLOCK    (66.67)  /* P1 clock VDC5 */
00055 #define DEFAULT_OUTPUT_CLOCK   (66.67)  /* LVDS output clock */
00056 
00057 #define     IMGCAP_SIZE_NTSC_HS         (122u)
00058 #define     IMGCAP_SIZE_NTSC_HW         (720u)
00059 #define     IMGCAP_SIZE_NTSC_VS         (16u)
00060 #define     IMGCAP_SIZE_NTSC_VW         (240u)
00061 
00062 #define     IMGCAP_SIZE_PAL_HS          (132u)
00063 #define     IMGCAP_SIZE_PAL_HW          (720u)
00064 #define     IMGCAP_SIZE_PAL_VS          (19u)
00065 #define     IMGCAP_SIZE_PAL_VW          (280u)
00066 
00067 typedef void (*vdc5_irq_handler)(uint32_t int_sense);
00068 
00069 /* video channel select */
00070 typedef enum {
00071     DRV_VIDEO_INPUT_CHANNEL_0 = 0,      /* video input channel 0    */
00072     DRV_VIDEO_INPUT_CHANNEL_1           /* video input channel 1    */
00073 } drv_video_input_channel_t;
00074 
00075 /* input pin control */
00076 typedef enum {
00077     DRV_VIDEO_ADC_VINSEL_VIN1 = 0,      /* VIN1 input               */
00078     DRV_VIDEO_ADC_VINSEL_VIN2           /* VIN2 input               */
00079 } drv_video_adc_vinsel_t;
00080 
00081 /* graphics layer select */
00082 typedef enum {
00083     DRV_GRAPHICS_LAYER_0 = 0,           /* graphics layer 0         */
00084     DRV_GRAPHICS_LAYER_1,               /* graphics layer 1         */
00085     DRV_GRAPHICS_LAYER_2,               /* graphics layer 2         */
00086     DRV_GRAPHICS_LAYER_3                /* graphics layer 3         */
00087 } drv_graphics_layer_t;
00088 
00089 /* error codes */
00090 typedef enum {
00091     DRV_GRAPHICS_OK = 0,                /* Normal termination       */
00092     DRV_GRAPHICS_VDC5_ERR = -1,         /* VDC5 error               */
00093     DRV_GRAPHICS_FORMAT_ERR = -2,       /* Not support format       */
00094     DRV_GRAPHICS_LAYER_ERR = -3,        /* Invalid layer ID error   */
00095     DRV_GRAPHICS_CHANNEL_ERR = -4,      /* Invalid channel error    */
00096     DRV_GRAPHICS_VIDEO_NTSC_SIZE_ERR = -5, /* Video Write           */
00097     DRV_GRAPHICS_VIDEO_PAL_SIZE_ERR = -6,  /* Video Write           */
00098     DRV_GRAPHICS_PARAM_RANGE_ERR = -7   /* Parameter range error    */
00099 } drv_graphics_error_t;
00100 
00101 /* graphics layer format select */
00102 typedef enum {
00103     DRV_GRAPHICS_FORMAT_YCBCR422 = 0,   /* YCbCr422                 */
00104     DRV_GRAPHICS_FORMAT_RGB565,         /* RGB565                   */
00105     DRV_GRAPHICS_FORMAT_RGB888,         /* RGB888                   */
00106     DRV_GRAPHICS_FORMAT_ARGB8888,       /* ARGB8888                 */
00107     DRV_GRAPHICS_FORMAT_ARGB4444        /* ARGB4444                 */
00108 } drv_graphics_format_t;
00109 
00110 /* video writing format select */
00111 typedef enum {
00112     DRV_VIDEO_FORMAT_YCBCR422 = 0,      /* YCbCr422                 */
00113     DRV_VIDEO_FORMAT_RGB565,            /* RGB565                   */
00114     DRV_VIDEO_FORMAT_RGB888             /* RGB888                   */
00115 } drv_video_format_t;
00116 
00117 
00118 /* lcd tcon output pin select */
00119 typedef enum {
00120     DRV_LCD_TCON_PIN_NON = -1,          /* Not using output         */
00121     DRV_LCD_TCON_PIN_0,                 /* LCD_TCON0                */
00122     DRV_LCD_TCON_PIN_1,                 /* LCD_TCON1                */
00123     DRV_LCD_TCON_PIN_2                  /* LCD_TCON2                */
00124 } drv_lcd_tcon_pin_t;
00125 
00126 /* lcd output format select */
00127 typedef enum {
00128     DRV_LCD_OUTFORMAT_RGB888 = 0,       /* RGB888 or LVDS           */
00129     DRV_LCD_OUTFORMAT_RGB666,           /* RGB666                   */
00130     DRV_LCD_OUTFORMAT_RGB565            /* RGB565                   */
00131 } drv_lcd_outformat_t;
00132 
00133 /* frame buffer swap setting */
00134 typedef enum {
00135     DRV_WR_RD_WRSWA_NON = 0,           /* Not swapped: 1-2-3-4-5-6-7-8 */
00136     DRV_WR_RD_WRSWA_8BIT,              /* Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */
00137     DRV_WR_RD_WRSWA_16BIT,             /* Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */
00138     DRV_WR_RD_WRSWA_16_8BIT,           /* Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */
00139     DRV_WR_RD_WRSWA_32BIT,             /* Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */
00140     DRV_WR_RD_WRSWA_32_8BIT,           /* Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */
00141     DRV_WR_RD_WRSWA_32_16BIT,          /* Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */
00142     DRV_WR_RD_WRSWA_32_16_8BIT,        /* Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */
00143 } drv_wr_rd_swa_t;
00144 
00145 /* edge of a signal */
00146 typedef enum {
00147     DRV_EDGE_RISING    = 0,             /* Rising edge              */
00148     DRV_EDGE_FALLING   = 1              /* Falling edge             */
00149 } drv_edge_t;
00150 
00151 /* lcd type */
00152 typedef enum {
00153     DRV_LCD_TYPE_LVDS = 0,              /* LVDS signal control      */
00154     DRV_LCD_TYPE_PARALLEL_RGB           /* RGB parallel signal control */
00155 } drv_lcd_type_t;
00156 
00157 /* Polarity of a signal */
00158 typedef enum {
00159     DRV_SIG_POL_NOT_INVERTED = 0,       /* Not inverted             */
00160     DRV_SIG_POL_INVERTED                /* Inverted                 */
00161 } drv_sig_pol_t;
00162 
00163 /* Video color system */
00164 typedef enum {
00165     DRV_COL_SYS_NTSC_358       = 0,        /* NTSC-3.58 */
00166     DVV_COL_SYS_NTSC_443       = 1,        /* NTSC-4.43 */
00167     DRV_COL_SYS_PAL_443        = 2,        /* PAL-4.43 */
00168     DRV_COL_SYS_PAL_M          = 3,        /* PAL-M */
00169     DRV_COL_SYS_PAL_N          = 4,        /* PAL-N */
00170     DRV_COL_SYS_SECAM          = 5,        /* SECAM */
00171     DRV_COL_SYS_NTSC_443_60    = 6,        /* NTSC-4.43 (60Hz) */
00172     DRV_COL_SYS_PAL_60         = 7,        /* PAL-60 */
00173 } drv_graphics_video_col_sys_t;
00174 
00175 /* External Input select */
00176 typedef enum {
00177     DRV_INPUT_SEL_VDEC      = 0,            /*!< Video decoder output signals */
00178     DRV_INPUT_SEL_EXT       = 1             /*!< Signals supplied via the external input pins */
00179 } drv_video_input_sel_t ;
00180 
00181 /* External input format select  */
00182 typedef enum {
00183     DRV_VIDEO_EXTIN_FORMAT_RGB888  = 0,   /*!< RGB888 Not support */
00184     DRV_VIDEO_EXTIN_FORMAT_RGB666 ,       /*!< RGB666 */
00185     DRV_VIDEO_EXTIN_FORMAT_RGB565 ,       /*!< RGB565 */
00186     DRV_VIDEO_EXTIN_FORMAT_BT656 ,        /*!< BT6556 */
00187     DRV_VIDEO_EXTIN_FORMAT_BT601 ,        /*!< BT6501 */
00188     DRV_VIDEO_EXTIN_FORMAT_YCBCR422 ,     /*!< YCbCr422 */
00189     DRV_VIDEO_EXTIN_FORMAT_YCBCR444 ,     /*!< YCbCr444 Not support */
00190 } drv_video_extin_format_t ;
00191 
00192 /* On/off */
00193 typedef enum {
00194     DRV_OFF     = 0,                      /*!< Off */
00195     DRV_ON      = 1                       /*!< On */
00196 } drv_onoff_t ;
00197 
00198 /* Number of lines for BT.656 external input  */
00199 typedef enum {
00200     DRV_EXTIN_LINE_525      = 0,    /*!< 525 lines */
00201     DRV_EXTIN_LINE_625      = 1     /*!< 625 lines */
00202 } drv_extin_input_line_t ;
00203 
00204 /* Y/Cb/Y/Cr data string start timing */
00205 typedef enum {
00206     DRV_EXTIN_H_POS_CBYCRY  = 0,    /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */
00207     DRV_EXTIN_H_POS_YCRYCB ,        /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */
00208     DRV_EXTIN_H_POS_CRYCBY ,        /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */
00209     DRV_EXTIN_H_POS_YCBYCR ,        /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */
00210 } drv_extin_h_pos_t ;
00211 
00212 /* The relative position within the graphics display area */
00213 typedef struct {
00214     uint16_t   vs;                  /* Vertical start pos       */
00215     uint16_t   vw;                  /* Vertical width (height)  */
00216     uint16_t   hs;                  /* Horizontal start pos     */
00217     uint16_t   hw;                  /* Horizontal width         */
00218 } drv_rect_t;
00219 
00220 /* lcd configuration  */
00221 typedef struct {
00222     drv_lcd_type_t      lcd_type;               /* LVDS or Pararel RGB                      */
00223     double              intputClock;            /* P1  clk [MHz] ex. 66.67                  */
00224     double              outputClock;            /* LCD clk [MHz] ex. 33.33                  */
00225 
00226     drv_lcd_outformat_t lcd_outformat;          /* Output format select */
00227     drv_edge_t          lcd_edge;               /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
00228 
00229     uint16_t            h_toatal_period;        /* Free-running Hsync period                */
00230     uint16_t            v_toatal_period;        /* Free-running Vsync period                */
00231     uint16_t            h_disp_widht;           /* LCD display area size, horizontal width  */
00232     uint16_t            v_disp_widht;           /* LCD display area size, vertical width    */
00233     uint16_t            h_back_porch;           /* LCD display horizontal back porch period */
00234     uint16_t            v_back_porch;           /* LCD display vertical back porch period   */
00235 
00236     drv_lcd_tcon_pin_t  h_sync_port;            /* TCONn or Not use(-1)                     */
00237     drv_sig_pol_t       h_sync_port_polarity;   /* Polarity inversion control of signal     */
00238     uint16_t            h_sync_width;           /* Hsync width                              */
00239 
00240     drv_lcd_tcon_pin_t  v_sync_port;            /* TCONn or Not use(-1)                     */
00241     drv_sig_pol_t       v_sync_port_polarity;   /* Polarity inversion control of signal     */
00242     uint16_t            v_sync_width;           /* Vsync width  */
00243 
00244     drv_lcd_tcon_pin_t  de_port;                /* TCONn or Not use(-1)                     */
00245     drv_sig_pol_t       de_port_polarity;       /* Polarity inversion control of signal     */
00246 
00247 } drv_lcd_config_t;
00248 
00249 /* Digital video input configuration  */
00250 typedef struct {
00251     drv_video_extin_format_t      inp_format;    /*!< External Input Format Select                                */
00252     drv_edge_t                   inp_pxd_edge;  /*!< Clock Edge Select for Capturing External Input Video Image  */
00253     drv_edge_t                   inp_vs_edge;   /*!< Clock Edge Select for Capturing External Input Vsync Signal */
00254     drv_edge_t                   inp_hs_edge;   /*!< Clock Edge Select for Capturing External Input Hsync Signal */
00255     drv_onoff_t                   inp_endian_on; /*!< External Input B/R Signal Swap On/Off Control               */
00256     drv_onoff_t                   inp_swap_on;   /*!< External Input Bit Endian Change On/Off Control             */
00257     drv_sig_pol_t                inp_vs_inv;    /*!< External Input Vsync Signal DV_VSYNC Inversion Control      */
00258     drv_sig_pol_t                inp_hs_inv;    /*!< External Input Hsync Signal DV_HSYNC Inversion Control      */
00259     drv_extin_input_line_t        inp_f525_625;  /*!< Number of lines for BT.656 external input */
00260     drv_extin_h_pos_t             inp_h_pos;     /*!< Y/Cb/Y/Cr data string start timing to Hsync reference */
00261 } drv_video_ext_in_config_t;
00262 
00263 /******************************************************************************
00264 Typedef definitions
00265 ******************************************************************************/
00266 
00267 /******************************************************************************
00268 Exported global functions (to be accessed by other files)
00269 ******************************************************************************/
00270 drv_graphics_error_t DRV_Graphics_Init( drv_lcd_config_t * drv_lcd_config );
00271 drv_graphics_error_t DRV_Graphics_Video_init( drv_video_input_sel_t  drv_video_input_sel, drv_video_ext_in_config_t * drv_video_ext_in_config );
00272 
00273 drv_graphics_error_t DRV_Graphics_Lcd_Port_Init( PinName *pin, uint32_t pin_count );
00274 drv_graphics_error_t DRV_Graphics_Lvds_Port_Init( PinName *pin, uint32_t pin_count );
00275 drv_graphics_error_t DRV_Graphics_Dvinput_Port_Init( PinName *pin, uint32_t pin_count );
00276 
00277 drv_graphics_error_t DRV_Graphics_Irq_Handler_Set( vdc5_int_type_t  irq, uint16_t num, void (* callback)(vdc5_int_type_t )  );
00278 
00279 drv_graphics_error_t DRV_Graphics_Start ( drv_graphics_layer_t layer_id );
00280 drv_graphics_error_t DRV_Graphics_Stop ( drv_graphics_layer_t layer_id );
00281 drv_graphics_error_t DRV_Video_Start ( drv_video_input_channel_t video_input_ch );
00282 drv_graphics_error_t DRV_Video_Stop ( drv_video_input_channel_t video_input_ch );
00283 
00284 drv_graphics_error_t DRV_Graphics_Read_Setting (
00285     drv_graphics_layer_t    layer_id,
00286     void                  * framebuff,
00287     uint32_t                fb_stride,
00288     drv_graphics_format_t   gr_format,
00289     drv_wr_rd_swa_t         wr_rd_swa,
00290     drv_rect_t            * gr_rect );
00291 
00292 drv_graphics_error_t DRV_Graphics_Read_Change (
00293     drv_graphics_layer_t    layer_id,
00294     void                 *  framebuff);
00295 
00296 drv_graphics_error_t DRV_Video_Write_Setting (
00297     drv_video_input_channel_t       video_input_ch,
00298     drv_graphics_video_col_sys_t    col_sys,
00299     void                          * framebuff,
00300     uint32_t                        fb_stride,
00301     drv_video_format_t              video_format,
00302     drv_wr_rd_swa_t                 wr_rd_swa,
00303     uint16_t                        video_write_buff_vw,
00304     uint16_t                        video_write_buff_hw,
00305     drv_video_adc_vinsel_t          video_adc_vinsel );
00306 
00307 drv_graphics_error_t DRV_Video_Write_Setting_Digital (
00308     void                          * framebuff,
00309     uint32_t                        fb_stride,
00310     drv_video_format_t              video_format,
00311     drv_wr_rd_swa_t                 wr_rd_swa,
00312     uint16_t                        video_write_buff_vw,
00313     uint16_t                        video_write_buff_hw,
00314     drv_rect_t                    * cap_area );
00315 
00316 drv_graphics_error_t DRV_Video_Write_Change (
00317     drv_video_input_channel_t    video_input_ch,
00318     void                       * framebuff,
00319     uint32_t                     fb_stride );
00320 
00321 #ifdef  __cplusplus
00322 }
00323 #endif  /* __cplusplus */
00324 
00325 #endif  /* GR_PEACH_VDC5_H */