Video library for GR-PEACH
Dependents: Trace_Program2 GR-PEACH_Camera_in_barcode GR-PEACH_LCD_sample GR-PEACH_LCD_4_3inch_sample ... more
Video library for GR-PEACH.
Hello World!
Import programGR-PEACH_Camera_in
Camera in sample for GR-PEACH. This sample works on GR-LYCHEE besides GR-PEACH.
API
Import library
Interface
See the Pinout page for more details
gr_peach_vdc5.h@4:aeefe5171463, 2016-06-30 (annotated)
- Committer:
- dkato
- Date:
- Thu Jun 30 11:00:37 2016 +0000
- Revision:
- 4:aeefe5171463
- Parent:
- 2:3149baf7925b
Add ARGB4444 to graphics layer read format.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
dkato | 0:853f5b7408a7 | 1 | /******************************************************************************* |
dkato | 0:853f5b7408a7 | 2 | * DISCLAIMER |
dkato | 0:853f5b7408a7 | 3 | * This software is supplied by Renesas Electronics Corporation and is only |
dkato | 0:853f5b7408a7 | 4 | * intended for use with Renesas products. No other uses are authorized. This |
dkato | 0:853f5b7408a7 | 5 | * software is owned by Renesas Electronics Corporation and is protected under |
dkato | 0:853f5b7408a7 | 6 | * all applicable laws, including copyright laws. |
dkato | 0:853f5b7408a7 | 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING |
dkato | 0:853f5b7408a7 | 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT |
dkato | 0:853f5b7408a7 | 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE |
dkato | 0:853f5b7408a7 | 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. |
dkato | 0:853f5b7408a7 | 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS |
dkato | 0:853f5b7408a7 | 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE |
dkato | 0:853f5b7408a7 | 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR |
dkato | 0:853f5b7408a7 | 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE |
dkato | 0:853f5b7408a7 | 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
dkato | 0:853f5b7408a7 | 16 | * Renesas reserves the right, without notice, to make changes to this software |
dkato | 0:853f5b7408a7 | 17 | * and to discontinue the availability of this software. By using this software, |
dkato | 0:853f5b7408a7 | 18 | * you agree to the additional terms and conditions found by accessing the |
dkato | 0:853f5b7408a7 | 19 | * following link: |
dkato | 0:853f5b7408a7 | 20 | * http://www.renesas.com/disclaimer |
dkato | 0:853f5b7408a7 | 21 | * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved. |
dkato | 0:853f5b7408a7 | 22 | *******************************************************************************/ |
dkato | 0:853f5b7408a7 | 23 | /**************************************************************************//** |
dkato | 0:853f5b7408a7 | 24 | * @file gr_peach_vdc5.h |
dkato | 0:853f5b7408a7 | 25 | * @version 1.00 |
dkato | 0:853f5b7408a7 | 26 | * $Rev: 199 $ |
dkato | 0:853f5b7408a7 | 27 | * $Date:: 2014-05-23 16:33:52 +0900#$ |
dkato | 0:853f5b7408a7 | 28 | * @brief Graphics driver wrapper function definitions in C |
dkato | 0:853f5b7408a7 | 29 | ******************************************************************************/ |
dkato | 0:853f5b7408a7 | 30 | |
dkato | 0:853f5b7408a7 | 31 | #ifndef GR_PEACH_VDC5_H |
dkato | 0:853f5b7408a7 | 32 | #define GR_PEACH_VDC5_H |
dkato | 0:853f5b7408a7 | 33 | |
dkato | 0:853f5b7408a7 | 34 | /****************************************************************************** |
dkato | 0:853f5b7408a7 | 35 | Includes <System Includes> , "Project Includes" |
dkato | 0:853f5b7408a7 | 36 | ******************************************************************************/ |
dkato | 0:853f5b7408a7 | 37 | #include <stdlib.h> |
dkato | 0:853f5b7408a7 | 38 | |
dkato | 0:853f5b7408a7 | 39 | #include "r_typedefs.h" |
dkato | 0:853f5b7408a7 | 40 | #include "r_vdc5.h" |
dkato | 0:853f5b7408a7 | 41 | #include "pinmap.h" |
dkato | 0:853f5b7408a7 | 42 | |
dkato | 0:853f5b7408a7 | 43 | #ifdef __cplusplus |
dkato | 0:853f5b7408a7 | 44 | extern "C" |
dkato | 0:853f5b7408a7 | 45 | { |
dkato | 0:853f5b7408a7 | 46 | #endif /* __cplusplus */ |
dkato | 0:853f5b7408a7 | 47 | |
dkato | 0:853f5b7408a7 | 48 | /****************************************************************************** |
dkato | 0:853f5b7408a7 | 49 | Macro definitions |
dkato | 0:853f5b7408a7 | 50 | ******************************************************************************/ |
dkato | 0:853f5b7408a7 | 51 | |
dkato | 0:853f5b7408a7 | 52 | #define VSYNC_1_2_FH_TIMING (858u) /* Vsync signal 1/2fH phase timing */ |
dkato | 0:853f5b7408a7 | 53 | #define VSYNC_1_4_FH_TIMING (429u) /* Vsync signal 1/4fH phase timing */ |
dkato | 0:853f5b7408a7 | 54 | #define DEFAULT_INPUT_CLOCK (66.67) /* P1 clock VDC5 */ |
dkato | 0:853f5b7408a7 | 55 | #define DEFAULT_OUTPUT_CLOCK (66.67) /* LVDS output clock */ |
dkato | 0:853f5b7408a7 | 56 | |
dkato | 0:853f5b7408a7 | 57 | #define IMGCAP_SIZE_NTSC_HS (122u) |
dkato | 0:853f5b7408a7 | 58 | #define IMGCAP_SIZE_NTSC_HW (720u) |
dkato | 0:853f5b7408a7 | 59 | #define IMGCAP_SIZE_NTSC_VS (16u) |
dkato | 0:853f5b7408a7 | 60 | #define IMGCAP_SIZE_NTSC_VW (240u) |
dkato | 0:853f5b7408a7 | 61 | |
dkato | 0:853f5b7408a7 | 62 | #define IMGCAP_SIZE_PAL_HS (132u) |
dkato | 0:853f5b7408a7 | 63 | #define IMGCAP_SIZE_PAL_HW (720u) |
dkato | 0:853f5b7408a7 | 64 | #define IMGCAP_SIZE_PAL_VS (19u) |
dkato | 0:853f5b7408a7 | 65 | #define IMGCAP_SIZE_PAL_VW (280u) |
dkato | 0:853f5b7408a7 | 66 | |
dkato | 0:853f5b7408a7 | 67 | typedef void (*vdc5_irq_handler)(uint32_t int_sense); |
dkato | 0:853f5b7408a7 | 68 | |
dkato | 0:853f5b7408a7 | 69 | /* video channel select */ |
dkato | 0:853f5b7408a7 | 70 | typedef enum { |
dkato | 0:853f5b7408a7 | 71 | DRV_VIDEO_INPUT_CHANNEL_0 = 0, /* video input channel 0 */ |
dkato | 0:853f5b7408a7 | 72 | DRV_VIDEO_INPUT_CHANNEL_1 /* video input channel 1 */ |
dkato | 0:853f5b7408a7 | 73 | } drv_video_input_channel_t; |
dkato | 0:853f5b7408a7 | 74 | |
dkato | 2:3149baf7925b | 75 | /* input pin control */ |
dkato | 2:3149baf7925b | 76 | typedef enum { |
dkato | 2:3149baf7925b | 77 | DRV_VIDEO_ADC_VINSEL_VIN1 = 0, /* VIN1 input */ |
dkato | 2:3149baf7925b | 78 | DRV_VIDEO_ADC_VINSEL_VIN2 /* VIN2 input */ |
dkato | 2:3149baf7925b | 79 | } drv_video_adc_vinsel_t; |
dkato | 2:3149baf7925b | 80 | |
dkato | 0:853f5b7408a7 | 81 | /* graphics layer select */ |
dkato | 0:853f5b7408a7 | 82 | typedef enum { |
dkato | 0:853f5b7408a7 | 83 | DRV_GRAPHICS_LAYER_0 = 0, /* graphics layer 0 */ |
dkato | 0:853f5b7408a7 | 84 | DRV_GRAPHICS_LAYER_1, /* graphics layer 1 */ |
dkato | 0:853f5b7408a7 | 85 | DRV_GRAPHICS_LAYER_2, /* graphics layer 2 */ |
dkato | 0:853f5b7408a7 | 86 | DRV_GRAPHICS_LAYER_3 /* graphics layer 3 */ |
dkato | 0:853f5b7408a7 | 87 | } drv_graphics_layer_t; |
dkato | 0:853f5b7408a7 | 88 | |
dkato | 0:853f5b7408a7 | 89 | /* error codes */ |
dkato | 0:853f5b7408a7 | 90 | typedef enum { |
dkato | 0:853f5b7408a7 | 91 | DRV_GRAPHICS_OK = 0, /* Normal termination */ |
dkato | 0:853f5b7408a7 | 92 | DRV_GRAPHICS_VDC5_ERR = -1, /* VDC5 error */ |
dkato | 0:853f5b7408a7 | 93 | DRV_GRAPHICS_FORMAT_ERR = -2, /* Not support format */ |
dkato | 0:853f5b7408a7 | 94 | DRV_GRAPHICS_LAYER_ERR = -3, /* Invalid layer ID error */ |
dkato | 0:853f5b7408a7 | 95 | DRV_GRAPHICS_CHANNEL_ERR = -4, /* Invalid channel error */ |
dkato | 0:853f5b7408a7 | 96 | DRV_GRAPHICS_VIDEO_NTSC_SIZE_ERR = -5, /* Video Write */ |
dkato | 0:853f5b7408a7 | 97 | DRV_GRAPHICS_VIDEO_PAL_SIZE_ERR = -6, /* Video Write */ |
dkato | 0:853f5b7408a7 | 98 | DRV_GRAPHICS_PARAM_RANGE_ERR = -7 /* Parameter range error */ |
dkato | 0:853f5b7408a7 | 99 | } drv_graphics_error_t; |
dkato | 0:853f5b7408a7 | 100 | |
dkato | 0:853f5b7408a7 | 101 | /* graphics layer format select */ |
dkato | 0:853f5b7408a7 | 102 | typedef enum { |
dkato | 0:853f5b7408a7 | 103 | DRV_GRAPHICS_FORMAT_YCBCR422 = 0, /* YCbCr422 */ |
dkato | 0:853f5b7408a7 | 104 | DRV_GRAPHICS_FORMAT_RGB565, /* RGB565 */ |
dkato | 0:853f5b7408a7 | 105 | DRV_GRAPHICS_FORMAT_RGB888, /* RGB888 */ |
dkato | 4:aeefe5171463 | 106 | DRV_GRAPHICS_FORMAT_ARGB8888, /* ARGB8888 */ |
dkato | 4:aeefe5171463 | 107 | DRV_GRAPHICS_FORMAT_ARGB4444 /* ARGB4444 */ |
dkato | 0:853f5b7408a7 | 108 | } drv_graphics_format_t; |
dkato | 0:853f5b7408a7 | 109 | |
dkato | 0:853f5b7408a7 | 110 | /* video writing format select */ |
dkato | 0:853f5b7408a7 | 111 | typedef enum { |
dkato | 0:853f5b7408a7 | 112 | DRV_VIDEO_FORMAT_YCBCR422 = 0, /* YCbCr422 */ |
dkato | 0:853f5b7408a7 | 113 | DRV_VIDEO_FORMAT_RGB565, /* RGB565 */ |
dkato | 0:853f5b7408a7 | 114 | DRV_VIDEO_FORMAT_RGB888 /* RGB888 */ |
dkato | 0:853f5b7408a7 | 115 | } drv_video_format_t; |
dkato | 0:853f5b7408a7 | 116 | |
dkato | 0:853f5b7408a7 | 117 | |
dkato | 0:853f5b7408a7 | 118 | /* lcd tcon output pin select */ |
dkato | 0:853f5b7408a7 | 119 | typedef enum { |
dkato | 0:853f5b7408a7 | 120 | DRV_LCD_TCON_PIN_NON = -1, /* Not using output */ |
dkato | 0:853f5b7408a7 | 121 | DRV_LCD_TCON_PIN_0, /* LCD_TCON0 */ |
dkato | 0:853f5b7408a7 | 122 | DRV_LCD_TCON_PIN_1, /* LCD_TCON1 */ |
dkato | 0:853f5b7408a7 | 123 | DRV_LCD_TCON_PIN_2 /* LCD_TCON2 */ |
dkato | 0:853f5b7408a7 | 124 | } drv_lcd_tcon_pin_t; |
dkato | 0:853f5b7408a7 | 125 | |
dkato | 0:853f5b7408a7 | 126 | /* lcd output format select */ |
dkato | 0:853f5b7408a7 | 127 | typedef enum { |
dkato | 0:853f5b7408a7 | 128 | DRV_LCD_OUTFORMAT_RGB888 = 0, /* RGB888 or LVDS */ |
dkato | 0:853f5b7408a7 | 129 | DRV_LCD_OUTFORMAT_RGB666, /* RGB666 */ |
dkato | 0:853f5b7408a7 | 130 | DRV_LCD_OUTFORMAT_RGB565 /* RGB565 */ |
dkato | 0:853f5b7408a7 | 131 | } drv_lcd_outformat_t; |
dkato | 0:853f5b7408a7 | 132 | |
dkato | 0:853f5b7408a7 | 133 | /* frame buffer swap setting */ |
dkato | 0:853f5b7408a7 | 134 | typedef enum { |
dkato | 0:853f5b7408a7 | 135 | DRV_WR_RD_WRSWA_NON = 0, /* Not swapped: 1-2-3-4-5-6-7-8 */ |
dkato | 0:853f5b7408a7 | 136 | DRV_WR_RD_WRSWA_8BIT, /* Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */ |
dkato | 0:853f5b7408a7 | 137 | DRV_WR_RD_WRSWA_16BIT, /* Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */ |
dkato | 0:853f5b7408a7 | 138 | DRV_WR_RD_WRSWA_16_8BIT, /* Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */ |
dkato | 0:853f5b7408a7 | 139 | DRV_WR_RD_WRSWA_32BIT, /* Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */ |
dkato | 0:853f5b7408a7 | 140 | DRV_WR_RD_WRSWA_32_8BIT, /* Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */ |
dkato | 0:853f5b7408a7 | 141 | DRV_WR_RD_WRSWA_32_16BIT, /* Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */ |
dkato | 0:853f5b7408a7 | 142 | DRV_WR_RD_WRSWA_32_16_8BIT, /* Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */ |
dkato | 0:853f5b7408a7 | 143 | } drv_wr_rd_swa_t; |
dkato | 0:853f5b7408a7 | 144 | |
dkato | 0:853f5b7408a7 | 145 | /* edge of a signal */ |
dkato | 0:853f5b7408a7 | 146 | typedef enum { |
dkato | 0:853f5b7408a7 | 147 | DRV_EDGE_RISING = 0, /* Rising edge */ |
dkato | 0:853f5b7408a7 | 148 | DRV_EDGE_FALLING = 1 /* Falling edge */ |
dkato | 0:853f5b7408a7 | 149 | } drv_edge_t; |
dkato | 0:853f5b7408a7 | 150 | |
dkato | 0:853f5b7408a7 | 151 | /* lcd type */ |
dkato | 0:853f5b7408a7 | 152 | typedef enum { |
dkato | 0:853f5b7408a7 | 153 | DRV_LCD_TYPE_LVDS = 0, /* LVDS signal control */ |
dkato | 0:853f5b7408a7 | 154 | DRV_LCD_TYPE_PARALLEL_RGB /* RGB parallel signal control */ |
dkato | 0:853f5b7408a7 | 155 | } drv_lcd_type_t; |
dkato | 0:853f5b7408a7 | 156 | |
dkato | 0:853f5b7408a7 | 157 | /* Polarity of a signal */ |
dkato | 0:853f5b7408a7 | 158 | typedef enum { |
dkato | 0:853f5b7408a7 | 159 | DRV_SIG_POL_NOT_INVERTED = 0, /* Not inverted */ |
dkato | 0:853f5b7408a7 | 160 | DRV_SIG_POL_INVERTED /* Inverted */ |
dkato | 0:853f5b7408a7 | 161 | } drv_sig_pol_t; |
dkato | 0:853f5b7408a7 | 162 | |
dkato | 0:853f5b7408a7 | 163 | /* Video color system */ |
dkato | 0:853f5b7408a7 | 164 | typedef enum { |
dkato | 0:853f5b7408a7 | 165 | DRV_COL_SYS_NTSC_358 = 0, /* NTSC-3.58 */ |
dkato | 0:853f5b7408a7 | 166 | DVV_COL_SYS_NTSC_443 = 1, /* NTSC-4.43 */ |
dkato | 0:853f5b7408a7 | 167 | DRV_COL_SYS_PAL_443 = 2, /* PAL-4.43 */ |
dkato | 0:853f5b7408a7 | 168 | DRV_COL_SYS_PAL_M = 3, /* PAL-M */ |
dkato | 0:853f5b7408a7 | 169 | DRV_COL_SYS_PAL_N = 4, /* PAL-N */ |
dkato | 0:853f5b7408a7 | 170 | DRV_COL_SYS_SECAM = 5, /* SECAM */ |
dkato | 0:853f5b7408a7 | 171 | DRV_COL_SYS_NTSC_443_60 = 6, /* NTSC-4.43 (60Hz) */ |
dkato | 0:853f5b7408a7 | 172 | DRV_COL_SYS_PAL_60 = 7, /* PAL-60 */ |
dkato | 0:853f5b7408a7 | 173 | } drv_graphics_video_col_sys_t; |
dkato | 0:853f5b7408a7 | 174 | |
dkato | 0:853f5b7408a7 | 175 | /* External Input select */ |
dkato | 0:853f5b7408a7 | 176 | typedef enum { |
dkato | 0:853f5b7408a7 | 177 | DRV_INPUT_SEL_VDEC = 0, /*!< Video decoder output signals */ |
dkato | 0:853f5b7408a7 | 178 | DRV_INPUT_SEL_EXT = 1 /*!< Signals supplied via the external input pins */ |
dkato | 0:853f5b7408a7 | 179 | } drv_video_input_sel_t; |
dkato | 0:853f5b7408a7 | 180 | |
dkato | 0:853f5b7408a7 | 181 | /* External input format select */ |
dkato | 0:853f5b7408a7 | 182 | typedef enum { |
dkato | 0:853f5b7408a7 | 183 | DRV_VIDEO_EXTIN_FORMAT_RGB888 = 0, /*!< RGB888 Not support */ |
dkato | 0:853f5b7408a7 | 184 | DRV_VIDEO_EXTIN_FORMAT_RGB666, /*!< RGB666 */ |
dkato | 0:853f5b7408a7 | 185 | DRV_VIDEO_EXTIN_FORMAT_RGB565, /*!< RGB565 */ |
dkato | 0:853f5b7408a7 | 186 | DRV_VIDEO_EXTIN_FORMAT_BT656, /*!< BT6556 */ |
dkato | 0:853f5b7408a7 | 187 | DRV_VIDEO_EXTIN_FORMAT_BT601, /*!< BT6501 */ |
dkato | 0:853f5b7408a7 | 188 | DRV_VIDEO_EXTIN_FORMAT_YCBCR422, /*!< YCbCr422 */ |
dkato | 0:853f5b7408a7 | 189 | DRV_VIDEO_EXTIN_FORMAT_YCBCR444, /*!< YCbCr444 Not support */ |
dkato | 0:853f5b7408a7 | 190 | } drv_video_extin_format_t; |
dkato | 0:853f5b7408a7 | 191 | |
dkato | 0:853f5b7408a7 | 192 | /* On/off */ |
dkato | 0:853f5b7408a7 | 193 | typedef enum { |
dkato | 0:853f5b7408a7 | 194 | DRV_OFF = 0, /*!< Off */ |
dkato | 0:853f5b7408a7 | 195 | DRV_ON = 1 /*!< On */ |
dkato | 0:853f5b7408a7 | 196 | } drv_onoff_t; |
dkato | 0:853f5b7408a7 | 197 | |
dkato | 0:853f5b7408a7 | 198 | /* Number of lines for BT.656 external input */ |
dkato | 0:853f5b7408a7 | 199 | typedef enum { |
dkato | 0:853f5b7408a7 | 200 | DRV_EXTIN_LINE_525 = 0, /*!< 525 lines */ |
dkato | 0:853f5b7408a7 | 201 | DRV_EXTIN_LINE_625 = 1 /*!< 625 lines */ |
dkato | 0:853f5b7408a7 | 202 | } drv_extin_input_line_t; |
dkato | 0:853f5b7408a7 | 203 | |
dkato | 0:853f5b7408a7 | 204 | /* Y/Cb/Y/Cr data string start timing */ |
dkato | 0:853f5b7408a7 | 205 | typedef enum { |
dkato | 0:853f5b7408a7 | 206 | DRV_EXTIN_H_POS_CBYCRY = 0, /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */ |
dkato | 0:853f5b7408a7 | 207 | DRV_EXTIN_H_POS_YCRYCB, /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */ |
dkato | 0:853f5b7408a7 | 208 | DRV_EXTIN_H_POS_CRYCBY, /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */ |
dkato | 0:853f5b7408a7 | 209 | DRV_EXTIN_H_POS_YCBYCR, /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */ |
dkato | 0:853f5b7408a7 | 210 | } drv_extin_h_pos_t; |
dkato | 0:853f5b7408a7 | 211 | |
dkato | 0:853f5b7408a7 | 212 | /* The relative position within the graphics display area */ |
dkato | 0:853f5b7408a7 | 213 | typedef struct { |
dkato | 0:853f5b7408a7 | 214 | uint16_t vs; /* Vertical start pos */ |
dkato | 0:853f5b7408a7 | 215 | uint16_t vw; /* Vertical width (height) */ |
dkato | 0:853f5b7408a7 | 216 | uint16_t hs; /* Horizontal start pos */ |
dkato | 0:853f5b7408a7 | 217 | uint16_t hw; /* Horizontal width */ |
dkato | 0:853f5b7408a7 | 218 | } drv_rect_t; |
dkato | 0:853f5b7408a7 | 219 | |
dkato | 0:853f5b7408a7 | 220 | /* lcd configuration */ |
dkato | 0:853f5b7408a7 | 221 | typedef struct { |
dkato | 0:853f5b7408a7 | 222 | drv_lcd_type_t lcd_type; /* LVDS or Pararel RGB */ |
dkato | 0:853f5b7408a7 | 223 | double intputClock; /* P1 clk [MHz] ex. 66.67 */ |
dkato | 0:853f5b7408a7 | 224 | double outputClock; /* LCD clk [MHz] ex. 33.33 */ |
dkato | 0:853f5b7408a7 | 225 | |
dkato | 0:853f5b7408a7 | 226 | drv_lcd_outformat_t lcd_outformat; /* Output format select */ |
dkato | 0:853f5b7408a7 | 227 | drv_edge_t lcd_edge; /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */ |
dkato | 0:853f5b7408a7 | 228 | |
dkato | 0:853f5b7408a7 | 229 | uint16_t h_toatal_period; /* Free-running Hsync period */ |
dkato | 0:853f5b7408a7 | 230 | uint16_t v_toatal_period; /* Free-running Vsync period */ |
dkato | 0:853f5b7408a7 | 231 | uint16_t h_disp_widht; /* LCD display area size, horizontal width */ |
dkato | 0:853f5b7408a7 | 232 | uint16_t v_disp_widht; /* LCD display area size, vertical width */ |
dkato | 0:853f5b7408a7 | 233 | uint16_t h_back_porch; /* LCD display horizontal back porch period */ |
dkato | 0:853f5b7408a7 | 234 | uint16_t v_back_porch; /* LCD display vertical back porch period */ |
dkato | 0:853f5b7408a7 | 235 | |
dkato | 0:853f5b7408a7 | 236 | drv_lcd_tcon_pin_t h_sync_port; /* TCONn or Not use(-1) */ |
dkato | 0:853f5b7408a7 | 237 | drv_sig_pol_t h_sync_port_polarity; /* Polarity inversion control of signal */ |
dkato | 0:853f5b7408a7 | 238 | uint16_t h_sync_width; /* Hsync width */ |
dkato | 0:853f5b7408a7 | 239 | |
dkato | 0:853f5b7408a7 | 240 | drv_lcd_tcon_pin_t v_sync_port; /* TCONn or Not use(-1) */ |
dkato | 0:853f5b7408a7 | 241 | drv_sig_pol_t v_sync_port_polarity; /* Polarity inversion control of signal */ |
dkato | 0:853f5b7408a7 | 242 | uint16_t v_sync_width; /* Vsync width */ |
dkato | 0:853f5b7408a7 | 243 | |
dkato | 0:853f5b7408a7 | 244 | drv_lcd_tcon_pin_t de_port; /* TCONn or Not use(-1) */ |
dkato | 0:853f5b7408a7 | 245 | drv_sig_pol_t de_port_polarity; /* Polarity inversion control of signal */ |
dkato | 0:853f5b7408a7 | 246 | |
dkato | 0:853f5b7408a7 | 247 | } drv_lcd_config_t; |
dkato | 0:853f5b7408a7 | 248 | |
dkato | 0:853f5b7408a7 | 249 | /* Digital video input configuration */ |
dkato | 0:853f5b7408a7 | 250 | typedef struct { |
dkato | 0:853f5b7408a7 | 251 | drv_video_extin_format_t inp_format; /*!< External Input Format Select */ |
dkato | 0:853f5b7408a7 | 252 | drv_edge_t inp_pxd_edge; /*!< Clock Edge Select for Capturing External Input Video Image */ |
dkato | 0:853f5b7408a7 | 253 | drv_edge_t inp_vs_edge; /*!< Clock Edge Select for Capturing External Input Vsync Signal */ |
dkato | 0:853f5b7408a7 | 254 | drv_edge_t inp_hs_edge; /*!< Clock Edge Select for Capturing External Input Hsync Signal */ |
dkato | 0:853f5b7408a7 | 255 | drv_onoff_t inp_endian_on; /*!< External Input B/R Signal Swap On/Off Control */ |
dkato | 0:853f5b7408a7 | 256 | drv_onoff_t inp_swap_on; /*!< External Input Bit Endian Change On/Off Control */ |
dkato | 0:853f5b7408a7 | 257 | drv_sig_pol_t inp_vs_inv; /*!< External Input Vsync Signal DV_VSYNC Inversion Control */ |
dkato | 0:853f5b7408a7 | 258 | drv_sig_pol_t inp_hs_inv; /*!< External Input Hsync Signal DV_HSYNC Inversion Control */ |
dkato | 0:853f5b7408a7 | 259 | drv_extin_input_line_t inp_f525_625; /*!< Number of lines for BT.656 external input */ |
dkato | 0:853f5b7408a7 | 260 | drv_extin_h_pos_t inp_h_pos; /*!< Y/Cb/Y/Cr data string start timing to Hsync reference */ |
dkato | 0:853f5b7408a7 | 261 | } drv_video_ext_in_config_t; |
dkato | 0:853f5b7408a7 | 262 | |
dkato | 0:853f5b7408a7 | 263 | /****************************************************************************** |
dkato | 0:853f5b7408a7 | 264 | Typedef definitions |
dkato | 0:853f5b7408a7 | 265 | ******************************************************************************/ |
dkato | 0:853f5b7408a7 | 266 | |
dkato | 0:853f5b7408a7 | 267 | /****************************************************************************** |
dkato | 0:853f5b7408a7 | 268 | Exported global functions (to be accessed by other files) |
dkato | 0:853f5b7408a7 | 269 | ******************************************************************************/ |
dkato | 0:853f5b7408a7 | 270 | drv_graphics_error_t DRV_Graphics_Init( drv_lcd_config_t * drv_lcd_config ); |
dkato | 0:853f5b7408a7 | 271 | drv_graphics_error_t DRV_Graphics_Video_init( drv_video_input_sel_t drv_video_input_sel, drv_video_ext_in_config_t * drv_video_ext_in_config ); |
dkato | 0:853f5b7408a7 | 272 | |
dkato | 0:853f5b7408a7 | 273 | drv_graphics_error_t DRV_Graphics_Lcd_Port_Init( PinName *pin, uint32_t pin_count ); |
dkato | 0:853f5b7408a7 | 274 | drv_graphics_error_t DRV_Graphics_Lvds_Port_Init( PinName *pin, uint32_t pin_count ); |
dkato | 0:853f5b7408a7 | 275 | drv_graphics_error_t DRV_Graphics_Dvinput_Port_Init( PinName *pin, uint32_t pin_count ); |
dkato | 0:853f5b7408a7 | 276 | |
dkato | 0:853f5b7408a7 | 277 | drv_graphics_error_t DRV_Graphics_Irq_Handler_Set( vdc5_int_type_t irq, uint16_t num, void (* callback)(vdc5_int_type_t) ); |
dkato | 0:853f5b7408a7 | 278 | |
dkato | 0:853f5b7408a7 | 279 | drv_graphics_error_t DRV_Graphics_Start ( drv_graphics_layer_t layer_id ); |
dkato | 0:853f5b7408a7 | 280 | drv_graphics_error_t DRV_Graphics_Stop ( drv_graphics_layer_t layer_id ); |
dkato | 0:853f5b7408a7 | 281 | drv_graphics_error_t DRV_Video_Start ( drv_video_input_channel_t video_input_ch ); |
dkato | 0:853f5b7408a7 | 282 | drv_graphics_error_t DRV_Video_Stop ( drv_video_input_channel_t video_input_ch ); |
dkato | 0:853f5b7408a7 | 283 | |
dkato | 0:853f5b7408a7 | 284 | drv_graphics_error_t DRV_Graphics_Read_Setting ( |
dkato | 0:853f5b7408a7 | 285 | drv_graphics_layer_t layer_id, |
dkato | 0:853f5b7408a7 | 286 | void * framebuff, |
dkato | 0:853f5b7408a7 | 287 | uint32_t fb_stride, |
dkato | 0:853f5b7408a7 | 288 | drv_graphics_format_t gr_format, |
dkato | 0:853f5b7408a7 | 289 | drv_wr_rd_swa_t wr_rd_swa, |
dkato | 0:853f5b7408a7 | 290 | drv_rect_t * gr_rect ); |
dkato | 0:853f5b7408a7 | 291 | |
dkato | 0:853f5b7408a7 | 292 | drv_graphics_error_t DRV_Graphics_Read_Change ( |
dkato | 0:853f5b7408a7 | 293 | drv_graphics_layer_t layer_id, |
dkato | 0:853f5b7408a7 | 294 | void * framebuff); |
dkato | 0:853f5b7408a7 | 295 | |
dkato | 0:853f5b7408a7 | 296 | drv_graphics_error_t DRV_Video_Write_Setting ( |
dkato | 0:853f5b7408a7 | 297 | drv_video_input_channel_t video_input_ch, |
dkato | 0:853f5b7408a7 | 298 | drv_graphics_video_col_sys_t col_sys, |
dkato | 0:853f5b7408a7 | 299 | void * framebuff, |
dkato | 0:853f5b7408a7 | 300 | uint32_t fb_stride, |
dkato | 0:853f5b7408a7 | 301 | drv_video_format_t video_format, |
dkato | 0:853f5b7408a7 | 302 | drv_wr_rd_swa_t wr_rd_swa, |
dkato | 0:853f5b7408a7 | 303 | uint16_t video_write_buff_vw, |
dkato | 2:3149baf7925b | 304 | uint16_t video_write_buff_hw, |
dkato | 2:3149baf7925b | 305 | drv_video_adc_vinsel_t video_adc_vinsel ); |
dkato | 0:853f5b7408a7 | 306 | |
dkato | 0:853f5b7408a7 | 307 | drv_graphics_error_t DRV_Video_Write_Setting_Digital ( |
dkato | 0:853f5b7408a7 | 308 | void * framebuff, |
dkato | 0:853f5b7408a7 | 309 | uint32_t fb_stride, |
dkato | 0:853f5b7408a7 | 310 | drv_video_format_t video_format, |
dkato | 0:853f5b7408a7 | 311 | drv_wr_rd_swa_t wr_rd_swa, |
dkato | 0:853f5b7408a7 | 312 | uint16_t video_write_buff_vw, |
dkato | 0:853f5b7408a7 | 313 | uint16_t video_write_buff_hw, |
dkato | 0:853f5b7408a7 | 314 | drv_rect_t * cap_area ); |
dkato | 0:853f5b7408a7 | 315 | |
dkato | 0:853f5b7408a7 | 316 | drv_graphics_error_t DRV_Video_Write_Change ( |
dkato | 0:853f5b7408a7 | 317 | drv_video_input_channel_t video_input_ch, |
dkato | 0:853f5b7408a7 | 318 | void * framebuff, |
dkato | 0:853f5b7408a7 | 319 | uint32_t fb_stride ); |
dkato | 0:853f5b7408a7 | 320 | |
dkato | 0:853f5b7408a7 | 321 | #ifdef __cplusplus |
dkato | 0:853f5b7408a7 | 322 | } |
dkato | 0:853f5b7408a7 | 323 | #endif /* __cplusplus */ |
dkato | 0:853f5b7408a7 | 324 | |
dkato | 0:853f5b7408a7 | 325 | #endif /* GR_PEACH_VDC5_H */ |