Renesas / GR-PEACH_video

Video library for GR-PEACH

Dependents:   Trace_Program2 GR-PEACH_Camera_in_barcode GR-PEACH_LCD_sample GR-PEACH_LCD_4_3inch_sample ... more

Video ｌibrary for GR-PEACH.

Hello World!

Import programGR-PEACH_Camera_in

Camera in sample for GR-PEACH. This sample works on GR-LYCHEE besides GR-PEACH.

Last commit 28 Dec 2018 by Renesas

API

Import library
GR-PEACH_video - DisplayBase Class Reference

Data Structures

struct lcd_config_t
LCD configuration. More...
struct rect_t
The relative position within the graphics display area. More...
struct video_ext_in_config_t
Digital Video Input configuration. More...

Public Types

enum video_input_channel_t { VIDEO_INPUT_CHANNEL_0 = 0, VIDEO_INPUT_CHANNEL_1 }

Video input channel select.

More...
enum graphics_layer_t { GRAPHICS_LAYER_0 = 0, GRAPHICS_LAYER_1 , GRAPHICS_LAYER_2 , GRAPHICS_LAYER_3 }

Graphics layer select.

More...
enum graphics_error_t {
GRAPHICS_OK = 0, GRAPHICS_VDC5_ERR = -1, GRAPHICS_FORMA_ERR = -2, GRAPHICS_LAYER_ERR = -3,
GRAPHICS_CHANNLE_ERR = -4, GRAPHICS_VIDEO_NTSC_SIZE_ERR = -5, GRAPHICS_VIDEO_PAL_SIZE_ERR = -6, GRAPHICS_PARAM_RANGE_ERR = -7
}

Error codes.

More...
enum graphics_format_t { GRAPHICS_FORMAT_YCBCR422 = 0, GRAPHICS_FORMAT_RGB565 , GRAPHICS_FORMAT_RGB888 , GRAPHICS_FORMAT_ARGB8888 }

Graphics layer read format selects.

More...
enum video_format_t { VIDEO_FORMAT_YCBCR422 = 0, VIDEO_FORMAT_RGB565 , VIDEO_FORMAT_RGB888 }

Video writing format selects.

More...
enum wr_rd_swa_t {
WR_RD_WRSWA_NON = 0, WR_RD_WRSWA_8BIT , WR_RD_WRSWA_16BIT , WR_RD_WRSWA_16_8BIT ,
WR_RD_WRSWA_32BIT , WR_RD_WRSWA_32_8BIT , WR_RD_WRSWA_32_16BIT , WR_RD_WRSWA_32_16_8BIT
}

Frame buffer swap setting.

More...
enum lcd_tcon_pin_t { LCD_TCON_PIN_NON = -1, LCD_TCON_PIN_0 , LCD_TCON_PIN_1 , LCD_TCON_PIN_2 }

LCD tcon output pin selects.

More...
enum lcd_outformat_t { LCD_OUTFORMAT_RGB888 = 0, LCD_OUTFORMAT_RGB666 , LCD_OUTFORMAT_RGB565 }

LCD output format selects.

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enum edge_t { EDGE_RISING = 0, EDGE_FALLING = 1 }

Edge of a signal.

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enum lcd_type_t { LCD_TYPE_LVDS = 0, LCD_TYPE_PARALLEL_RGB }

LCD type.

More...
enum sig_pol_t { SIG_POL_NOT_INVERTED = 0, SIG_POL_INVERTED }

Polarity of a signal.

More...
enum int_type_t {
INT_TYPE_S0_VI_VSYNC = 0, INT_TYPE_S0_LO_VSYNC , INT_TYPE_S0_VSYNCERR , INT_TYPE_VLINE ,
INT_TYPE_S0_VFIELD , INT_TYPE_IV1_VBUFERR , INT_TYPE_IV3_VBUFERR , INT_TYPE_IV5_VBUFERR ,
INT_TYPE_IV6_VBUFERR , INT_TYPE_S0_WLINE , INT_TYPE_S1_VI_VSYNC , INT_TYPE_S1_LO_VSYNC ,
INT_TYPE_S1_VSYNCERR , INT_TYPE_S1_VFIELD , INT_TYPE_IV2_VBUFERR , INT_TYPE_IV4_VBUFERR ,
INT_TYPE_S1_WLINE , INT_TYPE_OIR_VI_VSYNC , INT_TYPE_OIR_LO_VSYNC , INT_TYPE_OIR_VLINE ,
INT_TYPE_OIR_VFIELD , INT_TYPE_IV7_VBUFERR , INT_TYPE_IV8_VBUFERR , INT_TYPE_NUM
}

Interrupt type.

More...
enum graphics_video_col_sys_t {
COL_SYS_NTSC_358 = 0, COL_SYS_NTSC_443 = 1, COL_SYS_PAL_443 = 2, COL_SYS_PAL_M = 3,
COL_SYS_PAL_N = 4, COL_SYS_SECAM = 5, COL_SYS_NTSC_443_60 = 6, COL_SYS_PAL_60 = 7
}

Video color system.

More...
enum video_input_sel_t { INPUT_SEL_VDEC = 0, INPUT_SEL_EXT = 1 }

External Input select.

More...
enum video_extin_format_t {
VIDEO_EXTIN_FORMAT_RGB888 = 0, VIDEO_EXTIN_FORMAT_RGB666 , VIDEO_EXTIN_FORMAT_RGB565 , VIDEO_EXTIN_FORMAT_BT656 ,
VIDEO_EXTIN_FORMAT_BT601 , VIDEO_EXTIN_FORMAT_YCBCR422 , VIDEO_EXTIN_FORMAT_YCBCR444
}

External input format select.

More...
enum onoff_t { OFF = 0, ON = 1 }

On/off.

More...
enum extin_input_line_t { EXTIN_LINE_525 = 0, EXTIN_LINE_625 = 1 }

Number of lines for BT.656 external input.

More...
enum extin_h_pos_t { EXTIN_H_POS_CBYCRY = 0, EXTIN_H_POS_YCRYCB , EXTIN_H_POS_CRYCBY , EXTIN_H_POS_YCBYCR }

Y/Cb/Y/Cr data string start timing.

More...

Public Member Functions

DisplayBase (void)
Constructor method of display base object.
graphics_error_t Graphics_init ( lcd_config_t *lcd_config)
Graphics initialization processing
If not using display, set NULL in parameter.
graphics_error_t Graphics_Video_init ( video_input_sel_t video_input_sel, video_ext_in_config_t *video_ext_in_config)
Graphics Video initialization processing
If setting INPUT_SEL_VDEC in video_input_sel parameter, set NULL in video_ext_in_config parameter.
graphics_error_t Graphics_Lcd_Port_Init (PinName *pin, unsigned int pin_count)
LCD output port initialization processing.
graphics_error_t Graphics_Lvds_Port_Init (PinName *pin, unsigned int pin_count)
LVDS output port initialization processing.
graphics_error_t Graphics_Dvinput_Port_Init (PinName *pin, unsigned int pin_count)
Digital video input port initialization processing.
graphics_error_t Graphics_Irq_Handler_Set ( int_type_t Graphics_Irq_Handler_Set, unsigned short num, void(*callback)( int_type_t ))
Interrupt callback setup This function performs the following processing:

  • Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.

graphics_error_t Graphics_Start ( graphics_layer_t layer_id)
Start the graphics surface read process.
graphics_error_t Graphics_Stop ( graphics_layer_t layer_id)
Stop the graphics surface read process.
graphics_error_t Video_Start ( video_input_channel_t video_input_channel)
Start the video surface write process.
graphics_error_t Video_Stop ( video_input_channel_t video_input_channel)
Stop the video surface write process.
graphics_error_t Graphics_Read_Setting ( graphics_layer_t layer_id, void *framebuff, unsigned int fb_stride, graphics_format_t gr_format, wr_rd_swa_t wr_rd_swa, rect_t *gr_rect)
Graphics surface read process setting.
graphics_error_t Graphics_Read_Change ( graphics_layer_t layer_id, void *framebuff)
Graphics surface read buffer change process.
graphics_error_t Video_Write_Setting ( video_input_channel_t video_input_channel, graphics_video_col_sys_t col_sys, void *framebuff, unsigned int fb_stride, video_format_t video_format, wr_rd_swa_t wr_rd_swa, unsigned short video_write_buff_vw, unsigned short video_write_buff_hw)
Video surface write process setting.
graphics_error_t Video_Write_Change ( video_input_channel_t video_input_channel, void *framebuff, uint32_t fb_stride)
Video surface write buffer change process.

Interface

See the Pinout page for more details

DisplayBace.h@4:aeefe5171463, 2016-06-30 (annotated)

Committer:
dkato
Date:
Thu Jun 30 11:00:37 2016 +0000
Revision:
4:aeefe5171463
Parent:
3:e0e475089616 
Add ARGB4444 to graphics layer read format.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:853f5b7408a7 1 /*******************************************************************************
dkato 0:853f5b7408a7 2 * DISCLAIMER
dkato 0:853f5b7408a7 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:853f5b7408a7 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:853f5b7408a7 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:853f5b7408a7 6 * all applicable laws, including copyright laws.
dkato 0:853f5b7408a7 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:853f5b7408a7 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:853f5b7408a7 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:853f5b7408a7 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:853f5b7408a7 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:853f5b7408a7 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:853f5b7408a7 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:853f5b7408a7 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:853f5b7408a7 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:853f5b7408a7 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:853f5b7408a7 17 * and to discontinue the availability of this software. By using this software,
dkato 0:853f5b7408a7 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:853f5b7408a7 19 * following link:
dkato 0:853f5b7408a7 20 * http://www.renesas.com/disclaimer
dkato 0:853f5b7408a7 21 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
dkato 0:853f5b7408a7 22 *******************************************************************************/
dkato 0:853f5b7408a7 23 /**************************************************************************//**
dkato 0:853f5b7408a7 24 * @file DisplayBase.h
dkato 0:853f5b7408a7 25 * @brief Display driver wrapper class for GR-PEACH
dkato 0:853f5b7408a7 26 ******************************************************************************/
dkato 0:853f5b7408a7 27
dkato 0:853f5b7408a7 28 #ifndef MBED_DISPLAYBASE_H
dkato 0:853f5b7408a7 29 #define MBED_DISPLAYBASE_H
dkato 0:853f5b7408a7 30
dkato 0:853f5b7408a7 31 #include "pinmap.h"
dkato 0:853f5b7408a7 32
dkato 0:853f5b7408a7 33 /*! @class DisplayBase
dkato 0:853f5b7408a7 34 * @brief Display driver wrapper class for GR-PEACH
dkato 0:853f5b7408a7 35 */
dkato 0:853f5b7408a7 36 class DisplayBase
dkato 0:853f5b7408a7 37 {
dkato 0:853f5b7408a7 38
dkato 0:853f5b7408a7 39 public:
dkato 0:853f5b7408a7 40 /*! @enum video_input_channel_t
dkato 0:853f5b7408a7 41 @brief Video input channel select
dkato 0:853f5b7408a7 42 */
dkato 0:853f5b7408a7 43 typedef enum {
dkato 0:853f5b7408a7 44 VIDEO_INPUT_CHANNEL_0 = 0, /*!< Video input channel 0 */
dkato 0:853f5b7408a7 45 VIDEO_INPUT_CHANNEL_1 /*!< Video input channel 1 */
dkato 0:853f5b7408a7 46 } video_input_channel_t;
dkato 0:853f5b7408a7 47
dkato 2:3149baf7925b 48 /*! @enum video_adc_vinsel_t
dkato 2:3149baf7925b 49 @brief Input pin control
dkato 2:3149baf7925b 50 */
dkato 2:3149baf7925b 51 typedef enum {
dkato 2:3149baf7925b 52 VIDEO_ADC_VINSEL_VIN1 = 0, /*!< VIN1 input */
dkato 2:3149baf7925b 53 VIDEO_ADC_VINSEL_VIN2 /*!< VIN2 input */
dkato 2:3149baf7925b 54 } video_adc_vinsel_t;
dkato 2:3149baf7925b 55
dkato 0:853f5b7408a7 56 /*! @enum graphics_layer_t
dkato 0:853f5b7408a7 57 @brief Graphics layer select
dkato 0:853f5b7408a7 58 */
dkato 0:853f5b7408a7 59 typedef enum {
dkato 0:853f5b7408a7 60 GRAPHICS_LAYER_0 = 0, /*!< Graphics layer 0 */
dkato 0:853f5b7408a7 61 GRAPHICS_LAYER_1, /*!< Graphics layer 1 */
dkato 0:853f5b7408a7 62 GRAPHICS_LAYER_2, /*!< Graphics layer 2 */
dkato 0:853f5b7408a7 63 GRAPHICS_LAYER_3 /*!< Graphics layer 3 */
dkato 0:853f5b7408a7 64 } graphics_layer_t;
dkato 0:853f5b7408a7 65
dkato 0:853f5b7408a7 66 /*! @enum graphics_error_t
dkato 0:853f5b7408a7 67 @brief Error codes
dkato 0:853f5b7408a7 68 */
dkato 0:853f5b7408a7 69 typedef enum {
dkato 0:853f5b7408a7 70 GRAPHICS_OK = 0, /*!< Normal termination */
dkato 0:853f5b7408a7 71 GRAPHICS_VDC5_ERR = -1, /*!< VDC5 driver error */
dkato 0:853f5b7408a7 72 GRAPHICS_FORMA_ERR = -2, /*!< Not support format */
dkato 0:853f5b7408a7 73 GRAPHICS_LAYER_ERR = -3, /*!< Invalid layer ID error */
dkato 0:853f5b7408a7 74 GRAPHICS_CHANNLE_ERR = -4, /*!< Invalid channel error */
dkato 0:853f5b7408a7 75 GRAPHICS_VIDEO_NTSC_SIZE_ERR = -5, /*!< Video write size(vw) error */
dkato 0:853f5b7408a7 76 GRAPHICS_VIDEO_PAL_SIZE_ERR = -6, /*!< Video Write size(vw) error */
dkato 0:853f5b7408a7 77 GRAPHICS_PARAM_RANGE_ERR = -7 /*!< Parameter range error */
dkato 0:853f5b7408a7 78 } graphics_error_t;
dkato 0:853f5b7408a7 79
dkato 0:853f5b7408a7 80 /*! @enum graphics_format_t
dkato 0:853f5b7408a7 81 @brief Graphics layer read format selects
dkato 0:853f5b7408a7 82 */
dkato 0:853f5b7408a7 83 typedef enum {
dkato 0:853f5b7408a7 84 GRAPHICS_FORMAT_YCBCR422 = 0, /*!< YCbCr422 (2byte / px) */
dkato 0:853f5b7408a7 85 GRAPHICS_FORMAT_RGB565, /*!< RGB565 (2byte / px) */
dkato 0:853f5b7408a7 86 GRAPHICS_FORMAT_RGB888, /*!< RGB888 (4byte / px) */
dkato 4:aeefe5171463 87 GRAPHICS_FORMAT_ARGB8888, /*!< ARGB8888 (4byte / px) */
dkato 4:aeefe5171463 88 GRAPHICS_FORMAT_ARGB4444 /*!< ARGB4444 (2byte / px) */
dkato 0:853f5b7408a7 89 } graphics_format_t;
dkato 0:853f5b7408a7 90
dkato 0:853f5b7408a7 91 /*! @enum video_format_t
dkato 0:853f5b7408a7 92 @brief Video writing format selects
dkato 0:853f5b7408a7 93 */
dkato 0:853f5b7408a7 94 typedef enum {
dkato 0:853f5b7408a7 95 VIDEO_FORMAT_YCBCR422 = 0, /*!< YCbCr422 (2byte / px) */
dkato 0:853f5b7408a7 96 VIDEO_FORMAT_RGB565, /*!< RGB565 (2byte / px) */
dkato 0:853f5b7408a7 97 VIDEO_FORMAT_RGB888 /*!< RGB888 (4byte / px) */
dkato 0:853f5b7408a7 98 } video_format_t;
dkato 0:853f5b7408a7 99
dkato 0:853f5b7408a7 100 /*! @enum wr_rd_swa_t
dkato 0:853f5b7408a7 101 @brief Frame buffer swap setting
dkato 0:853f5b7408a7 102 */
dkato 0:853f5b7408a7 103 typedef enum {
dkato 0:853f5b7408a7 104 WR_RD_WRSWA_NON = 0, /*!< Not swapped: 1-2-3-4-5-6-7-8 */
dkato 0:853f5b7408a7 105 WR_RD_WRSWA_8BIT, /*!< Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */
dkato 0:853f5b7408a7 106 WR_RD_WRSWA_16BIT, /*!< Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */
dkato 0:853f5b7408a7 107 WR_RD_WRSWA_16_8BIT, /*!< Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */
dkato 0:853f5b7408a7 108 WR_RD_WRSWA_32BIT, /*!< Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */
dkato 0:853f5b7408a7 109 WR_RD_WRSWA_32_8BIT, /*!< Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */
dkato 0:853f5b7408a7 110 WR_RD_WRSWA_32_16BIT, /*!< Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */
dkato 0:853f5b7408a7 111 WR_RD_WRSWA_32_16_8BIT, /*!< Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */
dkato 0:853f5b7408a7 112 } wr_rd_swa_t;
dkato 0:853f5b7408a7 113
dkato 0:853f5b7408a7 114 /*! @enum lcd_tcon_pin_t
dkato 0:853f5b7408a7 115 @brief LCD tcon output pin selects
dkato 0:853f5b7408a7 116 */
dkato 0:853f5b7408a7 117 typedef enum {
dkato 0:853f5b7408a7 118 LCD_TCON_PIN_NON = -1, /*!< Not using output */
dkato 0:853f5b7408a7 119 LCD_TCON_PIN_0, /*!< LCD_TCON0 */
dkato 0:853f5b7408a7 120 LCD_TCON_PIN_1, /*!< LCD_TCON1 */
dkato 2:3149baf7925b 121 LCD_TCON_PIN_2, /*!< LCD_TCON2 */
dkato 3:e0e475089616 122 LCD_TCON_PIN_3, /*!< LCD_TCON3 */
dkato 3:e0e475089616 123 LCD_TCON_PIN_4, /*!< LCD_TCON4 */
dkato 0:853f5b7408a7 124 } lcd_tcon_pin_t;
dkato 0:853f5b7408a7 125
dkato 0:853f5b7408a7 126 /*! @enum lcd_outformat_t
dkato 0:853f5b7408a7 127 @brief LCD output format selects
dkato 0:853f5b7408a7 128 */
dkato 0:853f5b7408a7 129 typedef enum {
dkato 0:853f5b7408a7 130 LCD_OUTFORMAT_RGB888 = 0, /*!< RGB888 or LVDS */
dkato 0:853f5b7408a7 131 LCD_OUTFORMAT_RGB666, /*!< RGB666 */
dkato 0:853f5b7408a7 132 LCD_OUTFORMAT_RGB565 /*!< RGB565 */
dkato 0:853f5b7408a7 133 } lcd_outformat_t;
dkato 0:853f5b7408a7 134
dkato 0:853f5b7408a7 135 /*! @enum edge_t
dkato 0:853f5b7408a7 136 @brief Edge of a signal
dkato 0:853f5b7408a7 137 */
dkato 0:853f5b7408a7 138 typedef enum {
dkato 0:853f5b7408a7 139 EDGE_RISING = 0, /*!< Rising edge */
dkato 0:853f5b7408a7 140 EDGE_FALLING = 1 /*!< Falling edge */
dkato 0:853f5b7408a7 141 } edge_t;
dkato 0:853f5b7408a7 142
dkato 0:853f5b7408a7 143 /*! @enum lcd_type_t
dkato 0:853f5b7408a7 144 @brief LCD type
dkato 0:853f5b7408a7 145 */
dkato 0:853f5b7408a7 146 typedef enum {
dkato 0:853f5b7408a7 147 LCD_TYPE_LVDS = 0, /*!< LVDS control */
dkato 0:853f5b7408a7 148 LCD_TYPE_PARALLEL_RGB /*!< RGB parallel signal control */
dkato 0:853f5b7408a7 149 } lcd_type_t;
dkato 0:853f5b7408a7 150
dkato 0:853f5b7408a7 151 /*! @enum sig_pol_t
dkato 0:853f5b7408a7 152 @brief Polarity of a signal
dkato 0:853f5b7408a7 153 */
dkato 0:853f5b7408a7 154 typedef enum {
dkato 0:853f5b7408a7 155 SIG_POL_NOT_INVERTED = 0, /*!< Not inverted */
dkato 0:853f5b7408a7 156 SIG_POL_INVERTED /*!< Inverted */
dkato 0:853f5b7408a7 157 } sig_pol_t;
dkato 0:853f5b7408a7 158
dkato 0:853f5b7408a7 159 /*! @enum int_type_t
dkato 0:853f5b7408a7 160 @brief Interrupt type
dkato 0:853f5b7408a7 161 */
dkato 0:853f5b7408a7 162 typedef enum {
dkato 0:853f5b7408a7 163 INT_TYPE_S0_VI_VSYNC = 0, /*!< Vsync signal input to scaler 0 */
dkato 0:853f5b7408a7 164 INT_TYPE_S0_LO_VSYNC, /*!< Vsync signal output from scaler 0 */
dkato 0:853f5b7408a7 165 INT_TYPE_S0_VSYNCERR, /*!< Missing Vsync signal for scaler 0 */
dkato 0:853f5b7408a7 166 INT_TYPE_VLINE, /*!< Specified line signal for panel output in graphics 3 */
dkato 0:853f5b7408a7 167 INT_TYPE_S0_VFIELD, /*!< Field end signal for recording function in scaler 0 */
dkato 0:853f5b7408a7 168 INT_TYPE_IV1_VBUFERR, /*!< Frame buffer write overflow signal for scaler 0 */
dkato 0:853f5b7408a7 169 INT_TYPE_IV3_VBUFERR, /*!< Frame buffer read underflow signal for graphics 0 */
dkato 0:853f5b7408a7 170 INT_TYPE_IV5_VBUFERR, /*!< Frame buffer read underflow signal for graphics 2 */
dkato 0:853f5b7408a7 171 INT_TYPE_IV6_VBUFERR, /*!< Frame buffer read underflow signal for graphics 3 */
dkato 0:853f5b7408a7 172 INT_TYPE_S0_WLINE, /*!< Write specification line signal input to scaling-down control block in scaler 0 */
dkato 0:853f5b7408a7 173 INT_TYPE_S1_VI_VSYNC, /*!< Vsync signal input to scaler 1 */
dkato 0:853f5b7408a7 174 INT_TYPE_S1_LO_VSYNC, /*!< Vsync signal output from scaler 1 */
dkato 0:853f5b7408a7 175 INT_TYPE_S1_VSYNCERR, /*!< Missing Vsync signal for scaler 1 */
dkato 0:853f5b7408a7 176 INT_TYPE_S1_VFIELD, /*!< Field end signal for recording function in scaler 1 */
dkato 0:853f5b7408a7 177 INT_TYPE_IV2_VBUFERR, /*!< Frame buffer write overflow signal for scaler 1 */
dkato 0:853f5b7408a7 178 INT_TYPE_IV4_VBUFERR, /*!< Frame buffer read underflow signal for graphics 1 */
dkato 0:853f5b7408a7 179 INT_TYPE_S1_WLINE, /*!< Write specification line signal input to scaling-down control block in scaler 1 */
dkato 0:853f5b7408a7 180 INT_TYPE_OIR_VI_VSYNC, /*!< Vsync signal input to output image generator */
dkato 0:853f5b7408a7 181 INT_TYPE_OIR_LO_VSYNC, /*!< Vsync signal output from output image generator */
dkato 0:853f5b7408a7 182 INT_TYPE_OIR_VLINE, /*!< Specified line signal for panel output in output image generator */
dkato 0:853f5b7408a7 183 INT_TYPE_OIR_VFIELD, /*!< Field end signal for recording function in output image generator */
dkato 0:853f5b7408a7 184 INT_TYPE_IV7_VBUFERR, /*!< Frame buffer write overflow signal for output image generator */
dkato 0:853f5b7408a7 185 INT_TYPE_IV8_VBUFERR, /*!< Frame buffer read underflow signal for graphics (OIR) */
dkato 0:853f5b7408a7 186 INT_TYPE_NUM /*!< The number of VDC5 interrupt types */
dkato 0:853f5b7408a7 187 } int_type_t;
dkato 0:853f5b7408a7 188
dkato 0:853f5b7408a7 189 /*! @enum graphics_video_col_sys_t
dkato 0:853f5b7408a7 190 @brief Video color system
dkato 0:853f5b7408a7 191 */
dkato 0:853f5b7408a7 192 typedef enum {
dkato 0:853f5b7408a7 193 COL_SYS_NTSC_358 = 0, /*!< NTSC-3.58 */
dkato 0:853f5b7408a7 194 COL_SYS_NTSC_443 = 1, /*!< NTSC-4.43 */
dkato 0:853f5b7408a7 195 COL_SYS_PAL_443 = 2, /*!< PAL-4.43 */
dkato 0:853f5b7408a7 196 COL_SYS_PAL_M = 3, /*!< PAL-M */
dkato 0:853f5b7408a7 197 COL_SYS_PAL_N = 4, /*!< PAL-N */
dkato 0:853f5b7408a7 198 COL_SYS_SECAM = 5, /*!< SECAM */
dkato 0:853f5b7408a7 199 COL_SYS_NTSC_443_60 = 6, /*!< NTSC-4.43 (60Hz) */
dkato 0:853f5b7408a7 200 COL_SYS_PAL_60 = 7, /*!< PAL-60 */
dkato 0:853f5b7408a7 201 } graphics_video_col_sys_t;
dkato 0:853f5b7408a7 202
dkato 0:853f5b7408a7 203 /*! @enum video_input_sel_t
dkato 0:853f5b7408a7 204 @brief External Input select
dkato 0:853f5b7408a7 205 */
dkato 0:853f5b7408a7 206 typedef enum {
dkato 0:853f5b7408a7 207 INPUT_SEL_VDEC = 0, /*!< Video decoder output signals */
dkato 0:853f5b7408a7 208 INPUT_SEL_EXT = 1 /*!< Signals supplied via the external input pins */
dkato 0:853f5b7408a7 209 } video_input_sel_t;
dkato 0:853f5b7408a7 210
dkato 0:853f5b7408a7 211 /*! @enum video_extin_format_t
dkato 0:853f5b7408a7 212 @brief External input format select
dkato 0:853f5b7408a7 213 */
dkato 0:853f5b7408a7 214 typedef enum {
dkato 0:853f5b7408a7 215 VIDEO_EXTIN_FORMAT_RGB888 = 0, /*!< RGB888 Not support */
dkato 0:853f5b7408a7 216 VIDEO_EXTIN_FORMAT_RGB666, /*!< RGB666 */
dkato 0:853f5b7408a7 217 VIDEO_EXTIN_FORMAT_RGB565, /*!< RGB565 */
dkato 0:853f5b7408a7 218 VIDEO_EXTIN_FORMAT_BT656, /*!< BT6556 */
dkato 0:853f5b7408a7 219 VIDEO_EXTIN_FORMAT_BT601, /*!< BT6501 */
dkato 0:853f5b7408a7 220 VIDEO_EXTIN_FORMAT_YCBCR422, /*!< YCbCr422 */
dkato 0:853f5b7408a7 221 VIDEO_EXTIN_FORMAT_YCBCR444, /*!< YCbCr444 Not support */
dkato 0:853f5b7408a7 222 } video_extin_format_t;
dkato 0:853f5b7408a7 223
dkato 0:853f5b7408a7 224 /*! @enum onoff_t
dkato 0:853f5b7408a7 225 @brief On/off
dkato 0:853f5b7408a7 226 */
dkato 0:853f5b7408a7 227 typedef enum {
dkato 0:853f5b7408a7 228 OFF = 0, /*!< Off */
dkato 0:853f5b7408a7 229 ON = 1 /*!< On */
dkato 0:853f5b7408a7 230 } onoff_t;
dkato 0:853f5b7408a7 231
dkato 0:853f5b7408a7 232 /*! @enum extin_input_line_t
dkato 0:853f5b7408a7 233 @brief Number of lines for BT.656 external input
dkato 0:853f5b7408a7 234 */
dkato 0:853f5b7408a7 235 typedef enum {
dkato 0:853f5b7408a7 236 EXTIN_LINE_525 = 0, /*!< 525 lines */
dkato 0:853f5b7408a7 237 EXTIN_LINE_625 = 1 /*!< 625 lines */
dkato 0:853f5b7408a7 238 } extin_input_line_t;
dkato 0:853f5b7408a7 239
dkato 0:853f5b7408a7 240 /*! @enum extin_h_pos_t
dkato 0:853f5b7408a7 241 @brief Y/Cb/Y/Cr data string start timing
dkato 0:853f5b7408a7 242 */
dkato 0:853f5b7408a7 243 typedef enum {
dkato 0:853f5b7408a7 244 EXTIN_H_POS_CBYCRY = 0, /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */
dkato 0:853f5b7408a7 245 EXTIN_H_POS_YCRYCB, /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */
dkato 0:853f5b7408a7 246 EXTIN_H_POS_CRYCBY, /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */
dkato 0:853f5b7408a7 247 EXTIN_H_POS_YCBYCR, /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */
dkato 0:853f5b7408a7 248 EXTIN_H_POS_NUM
dkato 0:853f5b7408a7 249 } extin_h_pos_t;
dkato 0:853f5b7408a7 250
dkato 0:853f5b7408a7 251 /*! @struct rect_t
dkato 0:853f5b7408a7 252 @brief The relative position within the graphics display area
dkato 0:853f5b7408a7 253 */
dkato 0:853f5b7408a7 254 typedef struct {
dkato 0:853f5b7408a7 255 unsigned short vs; /*!< Vertical start pos */
dkato 0:853f5b7408a7 256 unsigned short vw; /*!< Vertical width (height) */
dkato 0:853f5b7408a7 257 unsigned short hs; /*!< Horizontal start pos */
dkato 0:853f5b7408a7 258 unsigned short hw; /*!< Horizontal width */
dkato 0:853f5b7408a7 259 } rect_t;
dkato 0:853f5b7408a7 260
dkato 0:853f5b7408a7 261 /*! @struct lcd_config_t
dkato 0:853f5b7408a7 262 @brief LCD configuration
dkato 0:853f5b7408a7 263 */
dkato 0:853f5b7408a7 264 typedef struct {
dkato 0:853f5b7408a7 265 lcd_type_t lcd_type; /*!< LVDS or Pararel RGB */
dkato 0:853f5b7408a7 266 double intputClock; /*!< P1 clk [MHz] ex. 66.67f */
dkato 0:853f5b7408a7 267 double outputClock; /*!< LCD clk [MHz] ex. 33.33f */
dkato 0:853f5b7408a7 268
dkato 0:853f5b7408a7 269 lcd_outformat_t lcd_outformat; /*!< Output format select */
dkato 0:853f5b7408a7 270 edge_t lcd_edge; /*!< Output phase control of LCD_DATA23 to LCD_DATA0 pin */
dkato 0:853f5b7408a7 271
dkato 0:853f5b7408a7 272 unsigned short h_toatal_period; /*!< Free-running Hsync period */
dkato 0:853f5b7408a7 273 unsigned short v_toatal_period; /*!< Free-running Vsync period */
dkato 0:853f5b7408a7 274 unsigned short h_disp_widht; /*!< LCD display area size, horizontal width */
dkato 0:853f5b7408a7 275 unsigned short v_disp_widht; /*!< LCD display area size, vertical width */
dkato 0:853f5b7408a7 276 unsigned short h_back_porch; /*!< LCD display horizontal back porch period */
dkato 0:853f5b7408a7 277 unsigned short v_back_porch; /*!< LCD display vertical back porch period */
dkato 0:853f5b7408a7 278
dkato 0:853f5b7408a7 279 lcd_tcon_pin_t h_sync_port; /*!< TCONn or Not use(-1) */
dkato 0:853f5b7408a7 280 sig_pol_t h_sync_port_polarity; /*!< Polarity inversion control of signal */
dkato 0:853f5b7408a7 281 unsigned short h_sync_width; /*!< Hsync width */
dkato 0:853f5b7408a7 282
dkato 0:853f5b7408a7 283 lcd_tcon_pin_t v_sync_port; /*!< TCONn or Not use(-1) */
dkato 0:853f5b7408a7 284 sig_pol_t v_sync_port_polarity; /*!< Polarity inversion control of signal */
dkato 0:853f5b7408a7 285 unsigned short v_sync_width; /*!< Vsync width */
dkato 0:853f5b7408a7 286
dkato 0:853f5b7408a7 287 lcd_tcon_pin_t de_port; /*!< TCONn or Not use(-1) */
dkato 0:853f5b7408a7 288 sig_pol_t de_port_polarity; /*!< Polarity inversion control of signal */
dkato 0:853f5b7408a7 289 } lcd_config_t;
dkato 0:853f5b7408a7 290
dkato 0:853f5b7408a7 291 /*! @struct video_ext_in_config_t
dkato 0:853f5b7408a7 292 @brief Digital Video Input configuration
dkato 0:853f5b7408a7 293 */
dkato 0:853f5b7408a7 294 typedef struct {
dkato 0:853f5b7408a7 295 video_extin_format_t inp_format; /*!< External Input Format Select */
dkato 0:853f5b7408a7 296 edge_t inp_pxd_edge; /*!< Clock Edge Select for Capturing External Input Video Image */
dkato 0:853f5b7408a7 297 edge_t inp_vs_edge; /*!< Clock Edge Select for Capturing External Input Vsync Signal */
dkato 0:853f5b7408a7 298 edge_t inp_hs_edge; /*!< Clock Edge Select for Capturing External Input Hsync Signal */
dkato 0:853f5b7408a7 299 onoff_t inp_endian_on; /*!< External Input B/R Signal Swap On/Off Control */
dkato 0:853f5b7408a7 300 onoff_t inp_swap_on; /*!< External Input Bit Endian Change On/Off Control */
dkato 0:853f5b7408a7 301 sig_pol_t inp_vs_inv; /*!< External Input Vsync Signal DV_VSYNC Inversion Control */
dkato 0:853f5b7408a7 302 sig_pol_t inp_hs_inv; /*!< External Input Hsync Signal DV_HSYNC Inversion Control */
dkato 0:853f5b7408a7 303 extin_input_line_t inp_f525_625; /*!< Number of lines for BT.656 external input */
dkato 0:853f5b7408a7 304 extin_h_pos_t inp_h_pos; /*!< Y/Cb/Y/Cr data string start timing to Hsync reference */
dkato 0:853f5b7408a7 305 unsigned short cap_vs_pos; /*!< Capture start position from Vsync */
dkato 0:853f5b7408a7 306 unsigned short cap_hs_pos; /*!< Capture start position form Hsync */
dkato 0:853f5b7408a7 307 unsigned short cap_width; /*!< Capture width */
dkato 0:853f5b7408a7 308 unsigned short cap_height; /*!< Capture height should be a multiple of 4.*/
dkato 0:853f5b7408a7 309 } video_ext_in_config_t;
dkato 0:853f5b7408a7 310
dkato 0:853f5b7408a7 311 /** Constructor method of display base object
dkato 0:853f5b7408a7 312 */
dkato 0:853f5b7408a7 313 DisplayBase( void );
dkato 0:853f5b7408a7 314
dkato 0:853f5b7408a7 315 /** Graphics initialization processing<br>
dkato 0:853f5b7408a7 316 * If not using display, set NULL in parameter.
dkato 0:853f5b7408a7 317 * @param[in] lcd_config : LCD configuration
dkato 0:853f5b7408a7 318 * @retval Error code
dkato 0:853f5b7408a7 319 */
dkato 0:853f5b7408a7 320 graphics_error_t Graphics_init( lcd_config_t * lcd_config );
dkato 0:853f5b7408a7 321
dkato 0:853f5b7408a7 322 /** Graphics Video initialization processing<br>
dkato 0:853f5b7408a7 323 * If setting INPUT_SEL_VDEC in video_input_sel parameter, set NULL in video_ext_in_config parameter.
dkato 0:853f5b7408a7 324 * @param[in] video_input_sel : Input select
dkato 0:853f5b7408a7 325 * @param[in] video_ext_in_config : Video configuration
dkato 0:853f5b7408a7 326 * @retval error code
dkato 0:853f5b7408a7 327 */
dkato 0:853f5b7408a7 328 graphics_error_t Graphics_Video_init( video_input_sel_t video_input_sel, video_ext_in_config_t * video_ext_in_config );
dkato 0:853f5b7408a7 329
dkato 0:853f5b7408a7 330 /** LCD output port initialization processing
dkato 0:853f5b7408a7 331 * @param[in] pin : Pin assign for LCD output
dkato 0:853f5b7408a7 332 * @param[in] pin_count : Total number of pin assign
dkato 0:853f5b7408a7 333 * @retval Error code
dkato 0:853f5b7408a7 334 */
dkato 0:853f5b7408a7 335 graphics_error_t Graphics_Lcd_Port_Init( PinName *pin, unsigned int pin_count );
dkato 0:853f5b7408a7 336
dkato 0:853f5b7408a7 337 /** LVDS output port initialization processing
dkato 0:853f5b7408a7 338 * @param[in] pin : Pin assign for LVDS output
dkato 0:853f5b7408a7 339 * @param[in] pin_count : Total number of pin assign
dkato 0:853f5b7408a7 340 * @retval Error code
dkato 0:853f5b7408a7 341 */
dkato 0:853f5b7408a7 342 graphics_error_t Graphics_Lvds_Port_Init( PinName *pin, unsigned int pin_count );
dkato 0:853f5b7408a7 343
dkato 0:853f5b7408a7 344 /** Digital video input port initialization processing
dkato 0:853f5b7408a7 345 * @param[in] pin : Pin assign for digital video input port
dkato 0:853f5b7408a7 346 * @param[in] pin_count : Total number of pin assign
dkato 0:853f5b7408a7 347 * @retval Error code
dkato 0:853f5b7408a7 348 */
dkato 0:853f5b7408a7 349 graphics_error_t Graphics_Dvinput_Port_Init( PinName *pin, unsigned int pin_count );
dkato 0:853f5b7408a7 350
dkato 0:853f5b7408a7 351 /** Interrupt callback setup
dkato 0:853f5b7408a7 352 * This function performs the following processing:
dkato 0:853f5b7408a7 353 * - Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.<br>
dkato 0:853f5b7408a7 354 * - Registers the specified interrupt callback function.<br>
dkato 0:853f5b7408a7 355 * - Disables the interrupt when the pointer to the corresponding interrupt callback function is not specified.<br>
dkato 0:853f5b7408a7 356 * @param[in] Graphics_Irq_Handler_Set : VDC5 interrupt type
dkato 0:853f5b7408a7 357 * @param[in] num : Interrupt line number
dkato 0:853f5b7408a7 358 * @param[in] callback : Interrupt callback function pointer
dkato 0:853f5b7408a7 359 * @retval Error code
dkato 0:853f5b7408a7 360 */
dkato 0:853f5b7408a7 361 graphics_error_t Graphics_Irq_Handler_Set( int_type_t Graphics_Irq_Handler_Set, unsigned short num, void (* callback)(int_type_t) );
dkato 0:853f5b7408a7 362
dkato 0:853f5b7408a7 363 /** Start the graphics surface read process
dkato 0:853f5b7408a7 364 * @param[in] layer_id : Graphics layer ID <br />
dkato 0:853f5b7408a7 365 * - GRAPHICS_LAYER_0 : Layer 0
dkato 0:853f5b7408a7 366 * - GRAPHICS_LAYER_1 : Layer 1
dkato 0:853f5b7408a7 367 * - GRAPHICS_LAYER_2 : Layer 2
dkato 0:853f5b7408a7 368 * - GRAPHICS_LAYER_3 : Layer 3
dkato 0:853f5b7408a7 369 * @retval Error code
dkato 0:853f5b7408a7 370 */
dkato 0:853f5b7408a7 371 graphics_error_t Graphics_Start( graphics_layer_t layer_id );
dkato 0:853f5b7408a7 372
dkato 0:853f5b7408a7 373 /** Stop the graphics surface read process
dkato 0:853f5b7408a7 374 * @param[in] layer_id : Graphics layer ID <br />
dkato 0:853f5b7408a7 375 * - GRAPHICS_LAYER_0 : Layer 0
dkato 0:853f5b7408a7 376 * - GRAPHICS_LAYER_1 : Layer 1
dkato 0:853f5b7408a7 377 * - GRAPHICS_LAYER_2 : Layer 2
dkato 0:853f5b7408a7 378 * - GRAPHICS_LAYER_3 : Layer 3
dkato 0:853f5b7408a7 379 * @retval Error code
dkato 0:853f5b7408a7 380 */
dkato 0:853f5b7408a7 381 graphics_error_t Graphics_Stop( graphics_layer_t layer_id );
dkato 0:853f5b7408a7 382
dkato 0:853f5b7408a7 383 /** Start the video surface write process
dkato 0:853f5b7408a7 384 * @param[in] video_input_channel : Video input channel <br />
dkato 0:853f5b7408a7 385 * - VIDEO_INPUT_CHANNEL_0 : Video channel 0
dkato 0:853f5b7408a7 386 * - VIDEO_INPUT_CHANNEL_1 : Video channel 1
dkato 0:853f5b7408a7 387 * @retval Error code
dkato 0:853f5b7408a7 388 */
dkato 0:853f5b7408a7 389 graphics_error_t Video_Start ( video_input_channel_t video_input_channel );
dkato 0:853f5b7408a7 390
dkato 0:853f5b7408a7 391 /** Stop the video surface write process
dkato 0:853f5b7408a7 392 * @param[in] video_input_channel : Video input channel <br />
dkato 0:853f5b7408a7 393 * - VIDEO_INPUT_CHANNEL_0 : Video channel 0
dkato 0:853f5b7408a7 394 * - VIDEO_INPUT_CHANNEL_1 : Video channel 1
dkato 0:853f5b7408a7 395 * @retval Error code
dkato 0:853f5b7408a7 396 */
dkato 0:853f5b7408a7 397 graphics_error_t Video_Stop ( video_input_channel_t video_input_channel );
dkato 0:853f5b7408a7 398
dkato 0:853f5b7408a7 399 /** Graphics surface read process setting
dkato 0:853f5b7408a7 400 * @param[in] layer_id : Graphics layer ID <br />
dkato 0:853f5b7408a7 401 * - GRAPHICS_LAYER_0 : Layer 0
dkato 0:853f5b7408a7 402 * - GRAPHICS_LAYER_1 : Layer 1
dkato 0:853f5b7408a7 403 * - GRAPHICS_LAYER_2 : Layer 2
dkato 0:853f5b7408a7 404 * - GRAPHICS_LAYER_3 : Layer 3
dkato 0:853f5b7408a7 405 * @param[in] framebuff : Base address of the frame buffer(Not set NULL)
dkato 0:853f5b7408a7 406 * @param[in] fb_stride : Line offset address of the frame buffer[byte] <br />
dkato 0:853f5b7408a7 407 * Frame buffer stride should be set to a multiple of 32 or 128
dkato 0:853f5b7408a7 408 * in accordance with the frame buffer burst transfer mode.
dkato 0:853f5b7408a7 409 * @param[in] gr_format : Format of the frame buffer read signal <br />
dkato 0:853f5b7408a7 410 * - VIDEO_FORMAT_YCBCR422 : YCBCR422 (2byte/px)
dkato 0:853f5b7408a7 411 * - VIDEO_FORMAT_RGB565 : RGB565 (2byte/px)
dkato 0:853f5b7408a7 412 * - VIDEO_FORMAT_RGB888 : RGB888 (4byte/px)
dkato 0:853f5b7408a7 413 * - VIDEO_FORMAT_ARGB8888 : ARGB8888 (4byte/px)
dkato 0:853f5b7408a7 414 * @param[in] wr_rd_swa : frame buffer swap setting <br />
dkato 0:853f5b7408a7 415 * - WR_RD_WRSWA_NON : Not swapped: 1-2-3-4-5-6-7-8
dkato 0:853f5b7408a7 416 * - WR_RD_WRSWA_8BIT : Swapped in 8-bit units: 2-1-4-3-6-5-8-7
dkato 0:853f5b7408a7 417 * - WR_RD_WRSWA_16BIT : Swapped in 16-bit units: 3-4-1-2-7-8-5-6
dkato 0:853f5b7408a7 418 * - WR_RD_WRSWA_16_8BIT : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5
dkato 0:853f5b7408a7 419 * - WR_RD_WRSWA_32BIT : Swapped in 32-bit units: 5-6-7-8-1-2-3-4
dkato 0:853f5b7408a7 420 * - WR_RD_WRSWA_32_8BIT : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3
dkato 0:853f5b7408a7 421 * - WR_RD_WRSWA_32_16BIT : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2
dkato 0:853f5b7408a7 422 * - WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1
dkato 0:853f5b7408a7 423 * @param[in] gr_rect : Graphics display area
dkato 0:853f5b7408a7 424 * @retval Error code
dkato 0:853f5b7408a7 425 */
dkato 0:853f5b7408a7 426 graphics_error_t Graphics_Read_Setting (
dkato 0:853f5b7408a7 427 graphics_layer_t layer_id,
dkato 0:853f5b7408a7 428 void * framebuff,
dkato 0:853f5b7408a7 429 unsigned int fb_stride,
dkato 0:853f5b7408a7 430 graphics_format_t gr_format,
dkato 0:853f5b7408a7 431 wr_rd_swa_t wr_rd_swa,
dkato 0:853f5b7408a7 432 rect_t * gr_rect );
dkato 0:853f5b7408a7 433
dkato 0:853f5b7408a7 434 /** Graphics surface read buffer change process
dkato 0:853f5b7408a7 435 * @param[in] layer_id : Graphics layer ID <br />
dkato 0:853f5b7408a7 436 * - GRAPHICS_LAYER_0 : Layer 0
dkato 0:853f5b7408a7 437 * - GRAPHICS_LAYER_1 : Layer 1
dkato 0:853f5b7408a7 438 * - GRAPHICS_LAYER_2 : Layer 2
dkato 0:853f5b7408a7 439 * - GRAPHICS_LAYER_3 : Layer 3
dkato 0:853f5b7408a7 440 * @param[in] framebuff : Base address of the frame buffer(Not set NULL)
dkato 0:853f5b7408a7 441 * @retval Error code
dkato 0:853f5b7408a7 442 */
dkato 0:853f5b7408a7 443 graphics_error_t Graphics_Read_Change (
dkato 0:853f5b7408a7 444 graphics_layer_t layer_id,
dkato 0:853f5b7408a7 445 void * framebuff);
dkato 0:853f5b7408a7 446
dkato 0:853f5b7408a7 447 /** Video surface write process setting
dkato 0:853f5b7408a7 448 * @param[in] video_input_channel : Video input channel <br />
dkato 0:853f5b7408a7 449 * If using digital input, this parameter is not referenced. <br />
dkato 0:853f5b7408a7 450 * - VIDEO_INPUT_CHANNEL_0 : Video channel 0
dkato 0:853f5b7408a7 451 * - VIDEO_INPUT_CHANNEL_1 : Video channel 1
dkato 0:853f5b7408a7 452 * @param[in] col_sys : Analog video signal color system <br />
dkato 0:853f5b7408a7 453 * If using digital input, this parameter is not referenced. <br />
dkato 0:853f5b7408a7 454 * - COL_SYS_NTSC_358 : NTSC-3.58
dkato 0:853f5b7408a7 455 * - COL_SYS_NTSC_443 : NTSC-4.43
dkato 0:853f5b7408a7 456 * - COL_SYS_PAL_443 : PAL-4.43
dkato 0:853f5b7408a7 457 * - COL_SYS_PAL_M : PAL-M
dkato 0:853f5b7408a7 458 * - COL_SYS_PAL_N : PAL-N
dkato 0:853f5b7408a7 459 * - COL_SYS_SECAM : SECAM
dkato 0:853f5b7408a7 460 * - COL_SYS_NTSC_443_60 : NTSC-4.43 (60Hz)
dkato 0:853f5b7408a7 461 * - COL_SYS_PAL_60 : PAL-60
dkato 0:853f5b7408a7 462 * @param[in] framebuff : Base address of the frame buffer(Not set NULL)
dkato 0:853f5b7408a7 463 * @param[in] fb_stride : Line offset address of the frame buffer[byte] <br />
dkato 0:853f5b7408a7 464 * Frame buffer stride should be set to a multiple of 32 or 128
dkato 0:853f5b7408a7 465 * in accordance with the frame buffer burst transfer mode.
dkato 0:853f5b7408a7 466 * @param[in] video_format : Frame buffer video-signal writing format <br />
dkato 0:853f5b7408a7 467 * - VIDEO_FORMAT_YCBCR422 : YCBCR422 (2byte/px)
dkato 0:853f5b7408a7 468 * - VIDEO_FORMAT_RGB565 : RGB565 (2byte/px)
dkato 0:853f5b7408a7 469 * - VIDEO_FORMAT_RGB888 : RGB888 (4byte/px)
dkato 0:853f5b7408a7 470 * @param[in] wr_rd_swa : frame buffer swap setting <br />
dkato 0:853f5b7408a7 471 * - WR_RD_WRSWA_NON : Not swapped: 1-2-3-4-5-6-7-8
dkato 0:853f5b7408a7 472 * - WR_RD_WRSWA_8BIT : Swapped in 8-bit units: 2-1-4-3-6-5-8-7
dkato 0:853f5b7408a7 473 * - WR_RD_WRSWA_16BIT : Swapped in 16-bit units: 3-4-1-2-7-8-5-6
dkato 0:853f5b7408a7 474 * - WR_RD_WRSWA_16_8BIT : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5
dkato 0:853f5b7408a7 475 * - WR_RD_WRSWA_32BIT : Swapped in 32-bit units: 5-6-7-8-1-2-3-4
dkato 0:853f5b7408a7 476 * - WR_RD_WRSWA_32_8BIT : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3
dkato 0:853f5b7408a7 477 * - WR_RD_WRSWA_32_16BIT : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2
dkato 0:853f5b7408a7 478 * - WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1
dkato 0:853f5b7408a7 479 * @param[in] video_write_buff_vw : Output height[px] <br />
dkato 0:853f5b7408a7 480 * - NTSC format : Max height is 480[px]
dkato 0:853f5b7408a7 481 * - PAL format : Max height is 520[px]
dkato 0:853f5b7408a7 482 * @param[in] video_write_buff_hw : Output width[px] <br />
dkato 0:853f5b7408a7 483 * - Max width : 800[px]
dkato 2:3149baf7925b 484 * @param[in] video_adc_vinsel : Input pin control <br />
dkato 2:3149baf7925b 485 * - VIDEO_ADC_VINSEL_VIN1 : VIN1 input
dkato 2:3149baf7925b 486 * - VIDEO_ADC_VINSEL_VIN2 : VIN2 input
dkato 0:853f5b7408a7 487 * @retval Error code
dkato 0:853f5b7408a7 488 */
dkato 0:853f5b7408a7 489 graphics_error_t Video_Write_Setting (
dkato 0:853f5b7408a7 490 video_input_channel_t video_input_channel,
dkato 0:853f5b7408a7 491 graphics_video_col_sys_t col_sys,
dkato 0:853f5b7408a7 492 void * framebuff,
dkato 0:853f5b7408a7 493 unsigned int fb_stride,
dkato 0:853f5b7408a7 494 video_format_t video_format,
dkato 0:853f5b7408a7 495 wr_rd_swa_t wr_rd_swa,
dkato 0:853f5b7408a7 496 unsigned short video_write_buff_vw,
dkato 2:3149baf7925b 497 unsigned short video_write_buff_hw,
dkato 2:3149baf7925b 498 video_adc_vinsel_t video_adc_vinsel = VIDEO_ADC_VINSEL_VIN1 );
dkato 0:853f5b7408a7 499
dkato 0:853f5b7408a7 500 /** Video surface write buffer change process
dkato 0:853f5b7408a7 501 * @param[in] video_input_channel : Video input channel <br />
dkato 0:853f5b7408a7 502 * - VIDEO_INPUT_CHANNEL_0 : Video channel 0
dkato 0:853f5b7408a7 503 * - VIDEO_INPUT_CHANNEL_1 : Video channel 1
dkato 0:853f5b7408a7 504 * @param[in] framebuff : Base address of the frame buffer(Not set NULL)
dkato 0:853f5b7408a7 505 * @param[in] fb_stride : Line offset address of the frame buffer <br />
dkato 0:853f5b7408a7 506 * Frame buffer stride should be set to a multiple of 32 or 128
dkato 0:853f5b7408a7 507 * in accordance with the frame buffer burst transfer mode.
dkato 0:853f5b7408a7 508 * @retval Error code
dkato 0:853f5b7408a7 509 */
dkato 0:853f5b7408a7 510 graphics_error_t Video_Write_Change (
dkato 0:853f5b7408a7 511 video_input_channel_t video_input_channel,
dkato 0:853f5b7408a7 512 void * framebuff,
dkato 0:853f5b7408a7 513 uint32_t fb_stride );
dkato 0:853f5b7408a7 514
dkato 0:853f5b7408a7 515 protected:
dkato 0:853f5b7408a7 516 lcd_config_t _lcd_config;
dkato 0:853f5b7408a7 517 video_input_sel_t _video_input_sel;
dkato 0:853f5b7408a7 518 video_ext_in_config_t _video_ext_in_config;
dkato 0:853f5b7408a7 519 };
dkato 0:853f5b7408a7 520
dkato 0:853f5b7408a7 521
dkato 0:853f5b7408a7 522 #endif /* MBED_DISPLAYBASE_H */