GR-PEACH_video - Video library for GR-PEACH

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Renesas / GR-PEACH_video

Video library for GR-PEACH

Dependents: Trace_Program2 GR-PEACH_Camera_in_barcode GR-PEACH_LCD_sample GR-PEACH_LCD_4_3inch_sample ... more

Video ｌibrary for GR-PEACH.

Hello World!

Import program GR-PEACH_Camera_in

Camera in sample for GR-PEACH. This sample works on GR-LYCHEE besides GR-PEACH.

API

Import library
GR-PEACH_video - DisplayBase Class Reference

Data Structures
struct	lcd_config_t
	LCD configuration. More...
struct	rect_t
	The relative position within the graphics display area. More...
struct	video_ext_in_config_t
	Digital Video Input configuration. More...
Public Types
enum	video_input_channel_t { VIDEO_INPUT_CHANNEL_0 = 0, VIDEO_INPUT_CHANNEL_1 }
	Video input channel select. More...
enum	graphics_layer_t { GRAPHICS_LAYER_0 = 0, GRAPHICS_LAYER_1 , GRAPHICS_LAYER_2 , GRAPHICS_LAYER_3 }
	Graphics layer select. More...
enum	graphics_error_t { GRAPHICS_OK = 0, GRAPHICS_VDC5_ERR = -1, GRAPHICS_FORMA_ERR = -2, GRAPHICS_LAYER_ERR = -3, GRAPHICS_CHANNLE_ERR = -4, GRAPHICS_VIDEO_NTSC_SIZE_ERR = -5, GRAPHICS_VIDEO_PAL_SIZE_ERR = -6, GRAPHICS_PARAM_RANGE_ERR = -7 }
	Error codes. More...
enum	graphics_format_t { GRAPHICS_FORMAT_YCBCR422 = 0, GRAPHICS_FORMAT_RGB565 , GRAPHICS_FORMAT_RGB888 , GRAPHICS_FORMAT_ARGB8888 }
	Graphics layer read format selects. More...
enum	video_format_t { VIDEO_FORMAT_YCBCR422 = 0, VIDEO_FORMAT_RGB565 , VIDEO_FORMAT_RGB888 }
	Video writing format selects. More...
enum	wr_rd_swa_t { WR_RD_WRSWA_NON = 0, WR_RD_WRSWA_8BIT , WR_RD_WRSWA_16BIT , WR_RD_WRSWA_16_8BIT , WR_RD_WRSWA_32BIT , WR_RD_WRSWA_32_8BIT , WR_RD_WRSWA_32_16BIT , WR_RD_WRSWA_32_16_8BIT }
	Frame buffer swap setting. More...
enum	lcd_tcon_pin_t { LCD_TCON_PIN_NON = -1, LCD_TCON_PIN_0 , LCD_TCON_PIN_1 , LCD_TCON_PIN_2 }
	LCD tcon output pin selects. More...
enum	lcd_outformat_t { LCD_OUTFORMAT_RGB888 = 0, LCD_OUTFORMAT_RGB666 , LCD_OUTFORMAT_RGB565 }
	LCD output format selects. More...
enum	edge_t { EDGE_RISING = 0, EDGE_FALLING = 1 }
	Edge of a signal. More...
enum	lcd_type_t { LCD_TYPE_LVDS = 0, LCD_TYPE_PARALLEL_RGB }
	LCD type. More...
enum	sig_pol_t { SIG_POL_NOT_INVERTED = 0, SIG_POL_INVERTED }
	Polarity of a signal. More...
enum	int_type_t { INT_TYPE_S0_VI_VSYNC = 0, INT_TYPE_S0_LO_VSYNC , INT_TYPE_S0_VSYNCERR , INT_TYPE_VLINE , INT_TYPE_S0_VFIELD , INT_TYPE_IV1_VBUFERR , INT_TYPE_IV3_VBUFERR , INT_TYPE_IV5_VBUFERR , INT_TYPE_IV6_VBUFERR , INT_TYPE_S0_WLINE , INT_TYPE_S1_VI_VSYNC , INT_TYPE_S1_LO_VSYNC , INT_TYPE_S1_VSYNCERR , INT_TYPE_S1_VFIELD , INT_TYPE_IV2_VBUFERR , INT_TYPE_IV4_VBUFERR , INT_TYPE_S1_WLINE , INT_TYPE_OIR_VI_VSYNC , INT_TYPE_OIR_LO_VSYNC , INT_TYPE_OIR_VLINE , INT_TYPE_OIR_VFIELD , INT_TYPE_IV7_VBUFERR , INT_TYPE_IV8_VBUFERR , INT_TYPE_NUM }
	Interrupt type. More...
enum	graphics_video_col_sys_t { COL_SYS_NTSC_358 = 0, COL_SYS_NTSC_443 = 1, COL_SYS_PAL_443 = 2, COL_SYS_PAL_M = 3, COL_SYS_PAL_N = 4, COL_SYS_SECAM = 5, COL_SYS_NTSC_443_60 = 6, COL_SYS_PAL_60 = 7 }
	Video color system. More...
enum	video_input_sel_t { INPUT_SEL_VDEC = 0, INPUT_SEL_EXT = 1 }
	External Input select. More...
enum	video_extin_format_t { VIDEO_EXTIN_FORMAT_RGB888 = 0, VIDEO_EXTIN_FORMAT_RGB666 , VIDEO_EXTIN_FORMAT_RGB565 , VIDEO_EXTIN_FORMAT_BT656 , VIDEO_EXTIN_FORMAT_BT601 , VIDEO_EXTIN_FORMAT_YCBCR422 , VIDEO_EXTIN_FORMAT_YCBCR444 }
	External input format select. More...
enum	onoff_t { OFF = 0, ON = 1 }
	On/off. More...
enum	extin_input_line_t { EXTIN_LINE_525 = 0, EXTIN_LINE_625 = 1 }
	Number of lines for BT.656 external input. More...
enum	extin_h_pos_t { EXTIN_H_POS_CBYCRY = 0, EXTIN_H_POS_YCRYCB , EXTIN_H_POS_CRYCBY , EXTIN_H_POS_YCBYCR }
	Y/Cb/Y/Cr data string start timing. More...
Public Member Functions
	DisplayBase (void)
	Constructor method of display base object.
graphics_error_t	Graphics_init ( lcd_config_t *lcd_config)
	Graphics initialization processing If not using display, set NULL in parameter.
graphics_error_t	Graphics_Video_init ( video_input_sel_t video_input_sel, video_ext_in_config_t *video_ext_in_config)
	Graphics Video initialization processing If setting INPUT_SEL_VDEC in video_input_sel parameter, set NULL in video_ext_in_config parameter.
graphics_error_t	Graphics_Lcd_Port_Init (PinName *pin, unsigned int pin_count)
	LCD output port initialization processing.
graphics_error_t	Graphics_Lvds_Port_Init (PinName *pin, unsigned int pin_count)
	LVDS output port initialization processing.
graphics_error_t	Graphics_Dvinput_Port_Init (PinName *pin, unsigned int pin_count)
	Digital video input port initialization processing.
graphics_error_t	Graphics_Irq_Handler_Set ( int_type_t Graphics_Irq_Handler_Set, unsigned short num, void(*callback)( int_type_t ))
	Interrupt callback setup This function performs the following processing: Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.
graphics_error_t	Graphics_Start ( graphics_layer_t layer_id)
	Start the graphics surface read process.
graphics_error_t	Graphics_Stop ( graphics_layer_t layer_id)
	Stop the graphics surface read process.
graphics_error_t	Video_Start ( video_input_channel_t video_input_channel)
	Start the video surface write process.
graphics_error_t	Video_Stop ( video_input_channel_t video_input_channel)
	Stop the video surface write process.
graphics_error_t	Graphics_Read_Setting ( graphics_layer_t layer_id, void framebuff, unsigned int fb_stride, graphics_format_t gr_format, wr_rd_swa_t wr_rd_swa, rect_t gr_rect)
	Graphics surface read process setting.
graphics_error_t	Graphics_Read_Change ( graphics_layer_t layer_id, void *framebuff)
	Graphics surface read buffer change process.
graphics_error_t	Video_Write_Setting ( video_input_channel_t video_input_channel, graphics_video_col_sys_t col_sys, void *framebuff, unsigned int fb_stride, video_format_t video_format, wr_rd_swa_t wr_rd_swa, unsigned short video_write_buff_vw, unsigned short video_write_buff_hw)
	Video surface write process setting.
graphics_error_t	Video_Write_Change ( video_input_channel_t video_input_channel, void *framebuff, uint32_t fb_stride)
	Video surface write buffer change process.

Interface

See the Pinout page for more details

gr_peach_vdc5.c@4:aeefe5171463, 2016-06-30 (annotated)

Committer:: dkato
Date:: Thu Jun 30 11:00:37 2016 +0000
Revision:: 4:aeefe5171463
Parent:: 3:e0e475089616

Add ARGB4444 to graphics layer read format.

Who changed what in which revision?

User	Revision	Line number	New contents of line
dkato	0:853f5b7408a7	1	/*******************************************************************************
dkato	0:853f5b7408a7	2	* DISCLAIMER
dkato	0:853f5b7408a7	3	* This software is supplied by Renesas Electronics Corporation and is only
dkato	0:853f5b7408a7	4	* intended for use with Renesas products. No other uses are authorized. This
dkato	0:853f5b7408a7	5	* software is owned by Renesas Electronics Corporation and is protected under
dkato	0:853f5b7408a7	6	* all applicable laws, including copyright laws.
dkato	0:853f5b7408a7	7	* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato	0:853f5b7408a7	8	* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato	0:853f5b7408a7	9	* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato	0:853f5b7408a7	10	* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato	0:853f5b7408a7	11	* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato	0:853f5b7408a7	12	* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato	0:853f5b7408a7	13	* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato	0:853f5b7408a7	14	* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato	0:853f5b7408a7	15	* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato	0:853f5b7408a7	16	* Renesas reserves the right, without notice, to make changes to this software
dkato	0:853f5b7408a7	17	* and to discontinue the availability of this software. By using this software,
dkato	0:853f5b7408a7	18	* you agree to the additional terms and conditions found by accessing the
dkato	0:853f5b7408a7	19	* following link:
dkato	0:853f5b7408a7	20	* http://www.renesas.com/disclaimer
dkato	0:853f5b7408a7	21	* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
dkato	0:853f5b7408a7	22	*******************************************************************************/
dkato	0:853f5b7408a7	23	/************************************************************************//
dkato	0:853f5b7408a7	24	* @file gr_peach_vdc5.c
dkato	0:853f5b7408a7	25	* @version
dkato	0:853f5b7408a7	26	* $Rev:
dkato	0:853f5b7408a7	27	* $Date::
dkato	0:853f5b7408a7	28	* @brief VDC5 driver API wrapper function in C interface
dkato	0:853f5b7408a7	29	******************************************************************************/
dkato	0:853f5b7408a7	30
dkato	0:853f5b7408a7	31	/******************************************************************************
dkato	0:853f5b7408a7	32	Includes <System Includes> , "Project Includes"
dkato	0:853f5b7408a7	33	******************************************************************************/
dkato	0:853f5b7408a7	34	#include <stdio.h>
dkato	0:853f5b7408a7	35	#include <string.h>
dkato	0:853f5b7408a7	36
dkato	0:853f5b7408a7	37	#include "r_typedefs.h"
dkato	0:853f5b7408a7	38	#include "r_vdc5.h"
dkato	0:853f5b7408a7	39	#include "video_decoder.h"
dkato	0:853f5b7408a7	40	#include "lvds_pll_calc.h"
dkato	0:853f5b7408a7	41	#include "gr_peach_vdc5.h"
dkato	0:853f5b7408a7	42
dkato	0:853f5b7408a7	43	#include "mbed_assert.h"
dkato	0:853f5b7408a7	44	#include "pinmap.h"
dkato	0:853f5b7408a7	45
dkato	0:853f5b7408a7	46	/******************************************************************************
dkato	0:853f5b7408a7	47	Macro definitions
dkato	0:853f5b7408a7	48	******************************************************************************/
dkato	0:853f5b7408a7	49	#define STP91_BIT (0x02u)
dkato	0:853f5b7408a7	50	#define STP90_BIT (0x01u)
dkato	0:853f5b7408a7	51	#define STBRQ25_BIT (0x20u)
dkato	0:853f5b7408a7	52	#define STBAK25_BIT (0x20u)
dkato	0:853f5b7408a7	53	#define STBRQ24_BIT (0x10u)
dkato	0:853f5b7408a7	54	#define STBAK24_BIT (0x10u)
dkato	0:853f5b7408a7	55
dkato	0:853f5b7408a7	56	/******************************************************************************
dkato	0:853f5b7408a7	57	Typedef definitions
dkato	0:853f5b7408a7	58	******************************************************************************/
dkato	0:853f5b7408a7	59	typedef enum {
dkato	0:853f5b7408a7	60	VDC5_CH0,
dkato	0:853f5b7408a7	61	VDC5_CH1,
dkato	0:853f5b7408a7	62	} VDC5Name;
dkato	0:853f5b7408a7	63
dkato	0:853f5b7408a7	64	/******************************************************************************
dkato	0:853f5b7408a7	65	Imported global variables and functions (from other files)
dkato	0:853f5b7408a7	66	******************************************************************************/
dkato	0:853f5b7408a7	67
dkato	0:853f5b7408a7	68	/******************************************************************************
dkato	0:853f5b7408a7	69	Exported global variables (to be accessed by other files)
dkato	0:853f5b7408a7	70	******************************************************************************/
dkato	0:853f5b7408a7	71	static const PinMap PinMap_DV_INPUT_PIN[] = {
dkato	0:853f5b7408a7	72	{P8_11 , VDC5_CH0, 8}, /* DV0_CLK */
dkato	0:853f5b7408a7	73	{P10_0 , VDC5_CH0, 1}, /* DV0_CLK */
dkato	0:853f5b7408a7	74	{P1_12 , VDC5_CH0, 2}, /* DV0_VSYNC */
dkato	0:853f5b7408a7	75	{P1_13 , VDC5_CH0, 2}, /* DV0_HSYNC */
dkato	0:853f5b7408a7	76	{P1_1 , VDC5_CH0, 6}, /* DV0_HSYNC */
dkato	0:853f5b7408a7	77	{P1_0 , VDC5_CH0, 6}, /* DV0_VSYNC */
dkato	0:853f5b7408a7	78	{P1_9 , VDC5_CH0, 6}, /* DV0_DATA15 */
dkato	0:853f5b7408a7	79	{P2_15 , VDC5_CH0, 3}, /* DV0_DATA15 */
dkato	0:853f5b7408a7	80	{P4_7 , VDC5_CH0, 7}, /* DV0_DATA15 */
dkato	0:853f5b7408a7	81	{P5_7 , VDC5_CH0, 4}, /* DV0_DATA15 */
dkato	0:853f5b7408a7	82	{P1_8 , VDC5_CH0, 6}, /* DV0_DATA14 */
dkato	0:853f5b7408a7	83	{P2_14 , VDC5_CH0, 3}, /* DV0_DATA14 */
dkato	0:853f5b7408a7	84	{P4_6 , VDC5_CH0, 7}, /* DV0_DATA14 */
dkato	0:853f5b7408a7	85	{P5_6 , VDC5_CH0, 4}, /* DV0_DATA14 */
dkato	0:853f5b7408a7	86	{P1_7 , VDC5_CH0, 6}, /* DV0_DATA13 */
dkato	0:853f5b7408a7	87	{P2_13 , VDC5_CH0, 3}, /* DV0_DATA13 */
dkato	0:853f5b7408a7	88	{P4_5 , VDC5_CH0, 7}, /* DV0_DATA13 */
dkato	0:853f5b7408a7	89	{P5_5 , VDC5_CH0, 4}, /* DV0_DATA13 */
dkato	0:853f5b7408a7	90	{P1_6 , VDC5_CH0, 6}, /* DV0_DATA12 */
dkato	0:853f5b7408a7	91	{P4_4 , VDC5_CH0, 7}, /* DV0_DATA12 */
dkato	0:853f5b7408a7	92	{P5_4 , VDC5_CH0, 4}, /* DV0_DATA12 */
dkato	0:853f5b7408a7	93	{P10_5 , VDC5_CH0, 1}, /* DV0_DATA11 */
dkato	0:853f5b7408a7	94	{P2_10 , VDC5_CH0, 3}, /* DV0_DATA10 */
dkato	0:853f5b7408a7	95	{P10_14, VDC5_CH0, 1}, /* DV0_DATA10 */
dkato	0:853f5b7408a7	96	{P2_9 , VDC5_CH0, 3}, /* DV0_DATA9 */
dkato	0:853f5b7408a7	97	{P10_13, VDC5_CH0, 1}, /* DV0_DATA9 */
dkato	0:853f5b7408a7	98	{P10_12, VDC5_CH0, 1}, /* DV0_DATA8 */
dkato	0:853f5b7408a7	99	{P2_7 , VDC5_CH0, 3}, /* DV0_DATA7 */
dkato	0:853f5b7408a7	100	{P2_6 , VDC5_CH0, 3}, /* DV0_DATA6 */
dkato	0:853f5b7408a7	101	{P2_5 , VDC5_CH0, 3}, /* DV0_DATA5 */
dkato	0:853f5b7408a7	102	{P2_4 , VDC5_CH0, 3}, /* DV0_DATA4 */
dkato	0:853f5b7408a7	103	{P2_3 , VDC5_CH0, 3}, /* DV0_DATA3 */
dkato	0:853f5b7408a7	104	{P2_2 , VDC5_CH0, 3}, /* DV0_DATA2 */
dkato	0:853f5b7408a7	105	{P2_1 , VDC5_CH0, 3}, /* DV0_DATA1 */
dkato	0:853f5b7408a7	106	{P2_0 , VDC5_CH0, 3}, /* DV0_DATA0 */
dkato	0:853f5b7408a7	107	{NC , NC , 0}
dkato	0:853f5b7408a7	108	};
dkato	0:853f5b7408a7	109
dkato	0:853f5b7408a7	110	static const PinMap PinMap_LCD_DISP_PIN[] = {
dkato	0:853f5b7408a7	111	{P2_7 , VDC5_CH0, 8}, /* LCD0_DATA23 */
dkato	3:e0e475089616	112	{P5_7 , VDC5_CH0, 3}, /* LCD0_DATA23 */
dkato	0:853f5b7408a7	113	{P10_0 , VDC5_CH0, 5}, /* LCD0_DATA23 */
dkato	0:853f5b7408a7	114	{P2_6 , VDC5_CH0, 8}, /* LCD0_DATA22 */
dkato	3:e0e475089616	115	{P5_6 , VDC5_CH0, 3}, /* LCD0_DATA22 */
dkato	3:e0e475089616	116	{P10_1 , VDC5_CH0, 5}, /* LCD0_DATA22 */
dkato	0:853f5b7408a7	117	{P2_5 , VDC5_CH0, 8}, /* LCD0_DATA21 */
dkato	3:e0e475089616	118	{P5_5 , VDC5_CH0, 3}, /* LCD0_DATA21 */
dkato	3:e0e475089616	119	{P10_2 , VDC5_CH0, 5}, /* LCD0_DATA21 */
dkato	0:853f5b7408a7	120	{P2_4 , VDC5_CH0, 8}, /* LCD0_DATA20 */
dkato	3:e0e475089616	121	{P5_4 , VDC5_CH0, 3}, /* LCD0_DATA20 */
dkato	3:e0e475089616	122	{P10_3 , VDC5_CH0, 5}, /* LCD0_DATA20 */
dkato	0:853f5b7408a7	123	{P2_3 , VDC5_CH0, 8}, /* LCD0_DATA19 */
dkato	3:e0e475089616	124	{P5_3 , VDC5_CH0, 3}, /* LCD0_DATA19 */
dkato	3:e0e475089616	125	{P10_4 , VDC5_CH0, 5}, /* LCD0_DATA19 */
dkato	0:853f5b7408a7	126	{P2_2 , VDC5_CH0, 8}, /* LCD0_DATA18 */
dkato	3:e0e475089616	127	{P5_2 , VDC5_CH0, 3}, /* LCD0_DATA18 */
dkato	3:e0e475089616	128	{P10_5 , VDC5_CH0, 5}, /* LCD0_DATA18 */
dkato	0:853f5b7408a7	129	{P2_1 , VDC5_CH0, 8}, /* LCD0_DATA17 */
dkato	3:e0e475089616	130	{P5_1 , VDC5_CH0, 3}, /* LCD0_DATA17 */
dkato	3:e0e475089616	131	{P10_7 , VDC5_CH0, 5}, /* LCD0_DATA17 */
dkato	0:853f5b7408a7	132	{P2_0 , VDC5_CH0, 8}, /* LCD0_DATA16 */
dkato	3:e0e475089616	133	{P5_0 , VDC5_CH0, 3}, /* LCD0_DATA16 */
dkato	3:e0e475089616	134	{P10_6 , VDC5_CH0, 5}, /* LCD0_DATA16 */
dkato	0:853f5b7408a7	135	{P4_7 , VDC5_CH0, 1}, /* LCD0_DATA15 */
dkato	3:e0e475089616	136	{P10_8 , VDC5_CH0, 5}, /* LCD0_DATA15 */
dkato	0:853f5b7408a7	137	{P4_6 , VDC5_CH0, 1}, /* LCD0_DATA14 */
dkato	3:e0e475089616	138	{P10_9 , VDC5_CH0, 5}, /* LCD0_DATA14 */
dkato	0:853f5b7408a7	139	{P4_5 , VDC5_CH0, 1}, /* LCD0_DATA13 */
dkato	3:e0e475089616	140	{P10_10, VDC5_CH0, 5}, /* LCD0_DATA13 */
dkato	0:853f5b7408a7	141	{P4_4 , VDC5_CH0, 1}, /* LCD0_DATA12 */
dkato	3:e0e475089616	142	{P10_11, VDC5_CH0, 5}, /* LCD0_DATA12 */
dkato	0:853f5b7408a7	143	{P10_12, VDC5_CH0, 5}, /* LCD0_DATA11 */
dkato	0:853f5b7408a7	144	{P10_13, VDC5_CH0, 5}, /* LCD0_DATA10 */
dkato	0:853f5b7408a7	145	{P10_14, VDC5_CH0, 5}, /* LCD0_DATA9 */
dkato	0:853f5b7408a7	146	{P4_0 , VDC5_CH0, 1}, /* LCD0_DATA8 */
dkato	0:853f5b7408a7	147	{P10_15, VDC5_CH0, 5}, /* LCD0_DATA8 */
dkato	0:853f5b7408a7	148	{P3_15 , VDC5_CH0, 1}, /* LCD0_DATA7 */
dkato	3:e0e475089616	149	{P11_0 , VDC5_CH0, 5}, /* LCD0_DATA7 */
dkato	0:853f5b7408a7	150	{P3_14 , VDC5_CH0, 1}, /* LCD0_DATA6 */
dkato	3:e0e475089616	151	{P11_1 , VDC5_CH0, 5}, /* LCD0_DATA6 */
dkato	0:853f5b7408a7	152	{P3_13 , VDC5_CH0, 1}, /* LCD0_DATA5 */
dkato	3:e0e475089616	153	{P11_2 , VDC5_CH0, 5}, /* LCD0_DATA5 */
dkato	0:853f5b7408a7	154	{P3_12 , VDC5_CH0, 1}, /* LCD0_DATA4 */
dkato	3:e0e475089616	155	{P11_3 , VDC5_CH0, 5}, /* LCD0_DATA4 */
dkato	0:853f5b7408a7	156	{P3_11 , VDC5_CH0, 1}, /* LCD0_DATA3 */
dkato	3:e0e475089616	157	{P11_4 , VDC5_CH0, 5}, /* LCD0_DATA3 */
dkato	0:853f5b7408a7	158	{P3_10 , VDC5_CH0, 1}, /* LCD0_DATA2 */
dkato	3:e0e475089616	159	{P11_5 , VDC5_CH0, 5}, /* LCD0_DATA2 */
dkato	0:853f5b7408a7	160	{P3_9 , VDC5_CH0, 1}, /* LCD0_DATA1 */
dkato	3:e0e475089616	161	{P11_6 , VDC5_CH0, 5}, /* LCD0_DATA1 */
dkato	0:853f5b7408a7	162	{P3_8 , VDC5_CH0, 1}, /* LCD0_DATA0 */
dkato	3:e0e475089616	163	{P11_7 , VDC5_CH0, 5}, /* LCD0_DATA0 */
dkato	3:e0e475089616	164	{P11_10, VDC5_CH0, 5}, /* LCD0_TCON4 */
dkato	3:e0e475089616	165	{P11_11, VDC5_CH0, 5}, /* LCD0_TCON3 */
dkato	0:853f5b7408a7	166	{P11_12, VDC5_CH0, 5}, /* LCD0_TCON2 */
dkato	0:853f5b7408a7	167	{P3_2 , VDC5_CH0, 1}, /* LCD0_TCON1 */
dkato	0:853f5b7408a7	168	{P11_13, VDC5_CH0, 5}, /* LCD0_TCON1 */
dkato	0:853f5b7408a7	169	{P11_14, VDC5_CH0, 5}, /* LCD0_TCON0 */
dkato	0:853f5b7408a7	170	{P11_15, VDC5_CH0, 5}, /* LCD0_CLK */
dkato	0:853f5b7408a7	171	{NC , NC , 0}
dkato	0:853f5b7408a7	172	};
dkato	0:853f5b7408a7	173
dkato	0:853f5b7408a7	174	static const PinMap PinMap_LVDS_DISP_PIN[] = {
dkato	0:853f5b7408a7	175	{P5_7 , VDC5_CH0, 1}, /* TXOUT0M */
dkato	0:853f5b7408a7	176	{P5_6 , VDC5_CH0, 1}, /* TXOUT0P */
dkato	0:853f5b7408a7	177	{P5_5 , VDC5_CH0, 1}, /* TXOUT1M */
dkato	0:853f5b7408a7	178	{P5_4 , VDC5_CH0, 1}, /* TXOUT1P */
dkato	0:853f5b7408a7	179	{P5_3 , VDC5_CH0, 1}, /* TXOUT2M */
dkato	0:853f5b7408a7	180	{P5_2 , VDC5_CH0, 1}, /* TXOUT2P */
dkato	0:853f5b7408a7	181	{P5_1 , VDC5_CH0, 1}, /* TXCLKOUTM */
dkato	0:853f5b7408a7	182	{P5_0 , VDC5_CH0, 1}, /* TXCLKOUTP */
dkato	0:853f5b7408a7	183	{NC , NC , 0}
dkato	0:853f5b7408a7	184	};
dkato	0:853f5b7408a7	185
dkato	0:853f5b7408a7	186	static const IRQn_Type vdc5_irq_set_tbl[] = {
dkato	0:853f5b7408a7	187	S0_VI_VSYNC0_IRQn,
dkato	0:853f5b7408a7	188	S0_LO_VSYNC0_IRQn,
dkato	0:853f5b7408a7	189	S0_VSYNCERR0_IRQn,
dkato	0:853f5b7408a7	190	GR3_VLINE0_IRQn,
dkato	0:853f5b7408a7	191	S0_VFIELD0_IRQn,
dkato	0:853f5b7408a7	192	IV1_VBUFERR0_IRQn,
dkato	0:853f5b7408a7	193	IV3_VBUFERR0_IRQn,
dkato	0:853f5b7408a7	194	IV5_VBUFERR0_IRQn,
dkato	0:853f5b7408a7	195	IV6_VBUFERR0_IRQn,
dkato	0:853f5b7408a7	196	S0_WLINE0_IRQn,
dkato	0:853f5b7408a7	197	S1_VI_VSYNC0_IRQn,
dkato	0:853f5b7408a7	198	S1_LO_VSYNC0_IRQn,
dkato	0:853f5b7408a7	199	S1_VSYNCERR0_IRQn,
dkato	0:853f5b7408a7	200	S1_VFIELD0_IRQn,
dkato	0:853f5b7408a7	201	IV2_VBUFERR0_IRQn,
dkato	0:853f5b7408a7	202	IV4_VBUFERR0_IRQn,
dkato	0:853f5b7408a7	203	S1_WLINE0_IRQn,
dkato	0:853f5b7408a7	204	OIR_VI_VSYNC0_IRQn,
dkato	0:853f5b7408a7	205	OIR_LO_VSYNC0_IRQn,
dkato	0:853f5b7408a7	206	OIR_VSYNCERR0_IRQn,
dkato	0:853f5b7408a7	207	OIR_VFIELD0_IRQn,
dkato	0:853f5b7408a7	208	IV7_VBUFERR0_IRQn,
dkato	0:853f5b7408a7	209	IV8_VBUFERR0_IRQn
dkato	0:853f5b7408a7	210	};
dkato	0:853f5b7408a7	211
dkato	0:853f5b7408a7	212	/******************************************************************************
dkato	0:853f5b7408a7	213	Private global variables and functions
dkato	0:853f5b7408a7	214	******************************************************************************/
dkato	0:853f5b7408a7	215	static void init_func (const uint32_t user_num);
dkato	0:853f5b7408a7	216	static void DRV_Graphics_Irq_Set(vdc5_int_type_t irq, uint32_t enable);
dkato	0:853f5b7408a7	217
dkato	0:853f5b7408a7	218	/************************************************************************//
dkato	0:853f5b7408a7	219	* @brief User-defined function within R_VDC5_Initialize
dkato	0:853f5b7408a7	220	* @param[in] user_num : VDC5 channel
dkato	0:853f5b7408a7	221	* @retval None
dkato	0:853f5b7408a7	222	******************************************************************************/
dkato	0:853f5b7408a7	223	static void init_func (const uint32_t user_num)
dkato	0:853f5b7408a7	224	{
dkato	0:853f5b7408a7	225	uint32_t reg_data;
dkato	0:853f5b7408a7	226	volatile uint8_t dummy_read;
dkato	0:853f5b7408a7	227
dkato	0:853f5b7408a7	228	if ((vdc5_channel_t)user_num == VDC5_CHANNEL_0) {
dkato	0:853f5b7408a7	229
dkato	0:853f5b7408a7	230	/* Standby control register 9 (STBCR9)
dkato	0:853f5b7408a7	231	b1 ------0-; MSTP91 : 0 : Video display controller channel 0 & LVDS enable */
dkato	0:853f5b7408a7	232	reg_data = (uint32_t)CPG.STBCR9 & (uint32_t)~STP91_BIT;
dkato	0:853f5b7408a7	233	CPG.STBCR9 = (uint8_t)reg_data;
dkato	0:853f5b7408a7	234	/* In order to reflect the change, a dummy read should be done. */
dkato	0:853f5b7408a7	235	dummy_read = CPG.STBCR9;
dkato	0:853f5b7408a7	236
dkato	0:853f5b7408a7	237	/* Standby Request Register 2 (STBREQ2)
dkato	0:853f5b7408a7	238	b5 --0-----; STBRQ25 : The standby request to VDC5 channel 0 is invalid. */
dkato	0:853f5b7408a7	239	reg_data = (uint32_t)CPG.STBREQ2 & (uint32_t)~STBRQ25_BIT;
dkato	0:853f5b7408a7	240	CPG.STBREQ2 = (uint8_t)reg_data;
dkato	0:853f5b7408a7	241	/* Standby Acknowledge Register 2 (STBACK2)
dkato	0:853f5b7408a7	242	b5 -------; STBAK25 : Standby acknowledgement from VDC5 channel 0. /
dkato	0:853f5b7408a7	243	while (((uint32_t)CPG.STBACK2 & (uint32_t)STBAK25_BIT) != 0u) {
dkato	0:853f5b7408a7	244	/* Wait for the STBAK25 to be cleared to 0. */
dkato	0:853f5b7408a7	245	}
dkato	0:853f5b7408a7	246
dkato	0:853f5b7408a7	247	/* Standby control register 9 (STBCR9)
dkato	0:853f5b7408a7	248	b0 -------0; MSTP90 : 0 : Video display controller channel 1 enable */
dkato	0:853f5b7408a7	249	reg_data = (uint32_t)CPG.STBCR9 & (uint32_t)~(STP91_BIT\|STP90_BIT);
dkato	0:853f5b7408a7	250	CPG.STBCR9 = (uint8_t)reg_data;
dkato	0:853f5b7408a7	251	/* In order to reflect the change, a dummy read should be done. */
dkato	0:853f5b7408a7	252	dummy_read = CPG.STBCR9;
dkato	0:853f5b7408a7	253
dkato	0:853f5b7408a7	254	/* Standby Request Register 2 (STBREQ2)
dkato	0:853f5b7408a7	255	b4 ---0----; STBRQ24 : The standby request to VDC5 channel 1 is invalid. */
dkato	0:853f5b7408a7	256	reg_data = (uint32_t)CPG.STBREQ2 & (uint32_t)~STBRQ24_BIT;
dkato	0:853f5b7408a7	257	CPG.STBREQ2 = (uint8_t)reg_data;
dkato	0:853f5b7408a7	258	/* Standby Acknowledge Register 2 (STBACK2)
dkato	0:853f5b7408a7	259	b4 -------; STBAK24 : Standby acknowledgement from VDC5 channel 1. /
dkato	0:853f5b7408a7	260	while (((uint32_t)CPG.STBACK2 & (uint32_t)STBAK24_BIT) != 0u) {
dkato	0:853f5b7408a7	261	/* Wait for the STBAK24 to be cleared to 0. */
dkato	0:853f5b7408a7	262	}
dkato	0:853f5b7408a7	263	}
dkato	0:853f5b7408a7	264	} /* End of function init_func() */
dkato	0:853f5b7408a7	265
dkato	0:853f5b7408a7	266	/************************************************************************//
dkato	0:853f5b7408a7	267	* @brief Interrupt service routine acquisition processing
dkato	0:853f5b7408a7	268	*
dkato	0:853f5b7408a7	269	* Description:<br>
dkato	0:853f5b7408a7	270	* This function returns the function pointer to the specified interrupt service routine.
dkato	0:853f5b7408a7	271	* @param[in] irq : VDC5 interrupt type
dkato	0:853f5b7408a7	272	* @param[in] enable : VDC5 interrupt enable
dkato	0:853f5b7408a7	273	* @retval None
dkato	0:853f5b7408a7	274	******************************************************************************/
dkato	0:853f5b7408a7	275	static void DRV_Graphics_Irq_Set(vdc5_int_type_t irq, uint32_t enable)
dkato	0:853f5b7408a7	276	{
dkato	0:853f5b7408a7	277	vdc5_channel_t ch = VDC5_CHANNEL_0;
dkato	0:853f5b7408a7	278	IRQn_Type IRQn;
dkato	0:853f5b7408a7	279	IRQHandler handler;
dkato	0:853f5b7408a7	280
dkato	0:853f5b7408a7	281	IRQn = vdc5_irq_set_tbl[irq];
dkato	0:853f5b7408a7	282	handler = R_VDC5_GetISR(ch, irq);
dkato	0:853f5b7408a7	283
dkato	0:853f5b7408a7	284	if (enable) {
dkato	0:853f5b7408a7	285	InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler);
dkato	0:853f5b7408a7	286	GIC_SetPriority(IRQn, 5);
dkato	0:853f5b7408a7	287	GIC_EnableIRQ(IRQn);
dkato	0:853f5b7408a7	288	} else {
dkato	0:853f5b7408a7	289	GIC_DisableIRQ(IRQn);
dkato	0:853f5b7408a7	290	}
dkato	0:853f5b7408a7	291	} /* End of function DRV_Graphics_Irq_Set() */
dkato	0:853f5b7408a7	292
dkato	0:853f5b7408a7	293	/************************************************************************//
dkato	0:853f5b7408a7	294	* @brief Interrupt callback setup
dkato	0:853f5b7408a7	295	* This function performs the following processing:
dkato	0:853f5b7408a7	296	* - Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.
dkato	0:853f5b7408a7	297	* - Registers the specified interrupt callback function.
dkato	0:853f5b7408a7	298	* - Disables the interrupt when the pointer to the corresponding interrupt callback function is not
dkato	0:853f5b7408a7	299	* specified.
dkato	0:853f5b7408a7	300	* @param[in] irq : VDC5 interrupt type
dkato	0:853f5b7408a7	301	* @param[in] num : Interrupt line number
dkato	0:853f5b7408a7	302	* @param[in] * callback : Interrupt callback function pointer
dkato	0:853f5b7408a7	303	* @retval Error code
dkato	0:853f5b7408a7	304	******************************************************************************/
dkato	0:853f5b7408a7	305	drv_graphics_error_t DRV_Graphics_Irq_Handler_Set(
dkato	0:853f5b7408a7	306	vdc5_int_type_t irq,
dkato	0:853f5b7408a7	307	uint16_t num,
dkato	0:853f5b7408a7	308	void (* callback)(vdc5_int_type_t) )
dkato	0:853f5b7408a7	309	{
dkato	0:853f5b7408a7	310	vdc5_channel_t ch = VDC5_CHANNEL_0;
dkato	0:853f5b7408a7	311	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
dkato	0:853f5b7408a7	312	vdc5_error_t error;
dkato	0:853f5b7408a7	313	vdc5_int_t interrupt;
dkato	0:853f5b7408a7	314
dkato	0:853f5b7408a7	315	if( callback == NULL ) {
dkato	0:853f5b7408a7	316	DRV_Graphics_Irq_Set( irq, 0 );
dkato	0:853f5b7408a7	317	} else {
dkato	0:853f5b7408a7	318	DRV_Graphics_Irq_Set( irq, 1 );
dkato	0:853f5b7408a7	319	}
dkato	0:853f5b7408a7	320
dkato	0:853f5b7408a7	321	/* Interrupt parameter */
dkato	0:853f5b7408a7	322	interrupt.type = irq; /* Interrupt type */
dkato	0:853f5b7408a7	323	interrupt.line_num = num ; /* Line number */
dkato	0:853f5b7408a7	324
dkato	0:853f5b7408a7	325	/* Interrupt parameter */
dkato	0:853f5b7408a7	326	interrupt.callback = callback; /* Callback function pointer */
dkato	0:853f5b7408a7	327	/* Set interrupt service routine */
dkato	0:853f5b7408a7	328	error = R_VDC5_CallbackISR(ch, &interrupt);
dkato	0:853f5b7408a7	329	if (error != VDC5_OK) {
dkato	0:853f5b7408a7	330	drv_error = DRV_GRAPHICS_VDC5_ERR;
dkato	0:853f5b7408a7	331	}
dkato	0:853f5b7408a7	332	return drv_error ;
dkato	0:853f5b7408a7	333	} /* End of function DRV_Graphics_Irq_Handler_Set() */
dkato	0:853f5b7408a7	334
dkato	0:853f5b7408a7	335	/************************************************************************//
dkato	0:853f5b7408a7	336	* @brief LCD output port initialization processing
dkato	0:853f5b7408a7	337	* @param[in] pin : Pin assign for LCD output
dkato	0:853f5b7408a7	338	* @param[in] pin_count : Total number of pin assign
dkato	0:853f5b7408a7	339	* @retval Error code
dkato	0:853f5b7408a7	340	******************************************************************************/
dkato	0:853f5b7408a7	341	drv_graphics_error_t DRV_Graphics_Lcd_Port_Init( PinName *pin, uint32_t pin_count )
dkato	0:853f5b7408a7	342	{
dkato	0:853f5b7408a7	343	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
dkato	0:853f5b7408a7	344	uint32_t count;
dkato	0:853f5b7408a7	345
dkato	0:853f5b7408a7	346	for( count = 0 ; count < pin_count ; count++ ) {
dkato	0:853f5b7408a7	347	pinmap_peripheral(pin[count], PinMap_LCD_DISP_PIN);
dkato	0:853f5b7408a7	348	pinmap_pinout(pin[count], PinMap_LCD_DISP_PIN);
dkato	0:853f5b7408a7	349	}
dkato	0:853f5b7408a7	350	return drv_error;
dkato	0:853f5b7408a7	351	} /* End of function DRV_Graphics_Lcd_Port_Init() */
dkato	0:853f5b7408a7	352
dkato	0:853f5b7408a7	353	/************************************************************************//
dkato	0:853f5b7408a7	354	* @brief LVDS output port initialization processing
dkato	0:853f5b7408a7	355	* @param[in] pin : Pin assign for LVDS output
dkato	0:853f5b7408a7	356	* @param[in] pin_count : Total number of pin assign
dkato	0:853f5b7408a7	357	* @retval Error code
dkato	0:853f5b7408a7	358	******************************************************************************/
dkato	0:853f5b7408a7	359	drv_graphics_error_t DRV_Graphics_Lvds_Port_Init( PinName *pin, uint32_t pin_count )
dkato	0:853f5b7408a7	360	{
dkato	0:853f5b7408a7	361	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
dkato	0:853f5b7408a7	362	uint32_t count;
dkato	0:853f5b7408a7	363
dkato	0:853f5b7408a7	364	for( count = 0 ; count < pin_count ; count++ ) {
dkato	0:853f5b7408a7	365	pinmap_peripheral(pin[count], PinMap_LVDS_DISP_PIN);
dkato	0:853f5b7408a7	366	pinmap_pinout(pin[count], PinMap_LVDS_DISP_PIN);
dkato	0:853f5b7408a7	367	}
dkato	0:853f5b7408a7	368	return drv_error;
dkato	0:853f5b7408a7	369	} /* End of function DRV_Graphics_Lvds_Port_Init() */
dkato	0:853f5b7408a7	370
dkato	0:853f5b7408a7	371	/************************************************************************//
dkato	0:853f5b7408a7	372	* @brief Digital video inpout port initialization processing
dkato	0:853f5b7408a7	373	* @param[in] pin : Pin assign for digital video input port
dkato	0:853f5b7408a7	374	* @param[in] pin_count : Total number of pin assign
dkato	0:853f5b7408a7	375	* @retval Error code
dkato	0:853f5b7408a7	376	******************************************************************************/
dkato	0:853f5b7408a7	377	drv_graphics_error_t DRV_Graphics_Dvinput_Port_Init( PinName *pin, uint32_t pin_count )
dkato	0:853f5b7408a7	378	{
dkato	0:853f5b7408a7	379	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
dkato	0:853f5b7408a7	380	uint32_t count;
dkato	0:853f5b7408a7	381
dkato	0:853f5b7408a7	382	for( count = 0 ; count < pin_count ; count++ ) {
dkato	0:853f5b7408a7	383	pinmap_peripheral(pin[count], PinMap_DV_INPUT_PIN);
dkato	0:853f5b7408a7	384	pinmap_pinout(pin[count], PinMap_DV_INPUT_PIN);
dkato	0:853f5b7408a7	385	}
dkato	0:853f5b7408a7	386	return drv_error;
dkato	0:853f5b7408a7	387	} /* End of function DRV_Graphics_Dvinput_Port_Init() */
dkato	0:853f5b7408a7	388
dkato	0:853f5b7408a7	389	/************************************************************************//
dkato	0:853f5b7408a7	390	* @brief Graphics initialization processing
dkato	0:853f5b7408a7	391	* @param[in] drv_lcd_config : LCD configuration
dkato	0:853f5b7408a7	392	* @retval Error code
dkato	0:853f5b7408a7	393	******************************************************************************/
dkato	0:853f5b7408a7	394	drv_graphics_error_t DRV_Graphics_Init( drv_lcd_config_t * drv_lcd_config )
dkato	0:853f5b7408a7	395	{
dkato	0:853f5b7408a7	396	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
dkato	0:853f5b7408a7	397	vdc5_channel_t ch = VDC5_CHANNEL_0;
dkato	0:853f5b7408a7	398	vdc5_error_t error;
dkato	0:853f5b7408a7	399	vdc5_init_t init;
dkato	0:853f5b7408a7	400	vdc5_lvds_t vdc5_lvds;
dkato	0:853f5b7408a7	401	pll_parameter_t pll_parameter;
dkato	0:853f5b7408a7	402	double InputClock = DEFAULT_INPUT_CLOCK;
dkato	0:853f5b7408a7	403	double OutputClock = DEFAULT_OUTPUT_CLOCK;
dkato	0:853f5b7408a7	404	uint32_t LvdsUsed = LVDS_IF_USE;
dkato	0:853f5b7408a7	405
dkato	0:853f5b7408a7	406	/* Initialization parameter */
dkato	0:853f5b7408a7	407	init.panel_icksel = VDC5_PANEL_ICKSEL_LVDS; /* Panel clock select */
dkato	0:853f5b7408a7	408	init.panel_dcdr = VDC5_PANEL_CLKDIV_1_1; /* Panel clock frequency division ratio */
dkato	0:853f5b7408a7	409
dkato	0:853f5b7408a7	410	if( drv_lcd_config != NULL ) {
dkato	0:853f5b7408a7	411	InputClock = drv_lcd_config->intputClock;
dkato	0:853f5b7408a7	412	OutputClock = drv_lcd_config->outputClock;
dkato	0:853f5b7408a7	413
dkato	0:853f5b7408a7	414	/* LVDS PLL Setting Calculation */
dkato	0:853f5b7408a7	415	if( drv_lcd_config->lcd_type == DRV_LCD_TYPE_LVDS ) {
dkato	0:853f5b7408a7	416	LvdsUsed = LVDS_IF_USE;
dkato	1:fe90cfd5fe25	417	init.panel_icksel = VDC5_PANEL_ICKSEL_LVDS_DIV7; /* Panel clock select */
dkato	0:853f5b7408a7	418	} else {
dkato	0:853f5b7408a7	419	LvdsUsed = LVDS_IF_NOT_USE;
dkato	0:853f5b7408a7	420	}
dkato	0:853f5b7408a7	421	}
dkato	0:853f5b7408a7	422	lvds_pll_calc( InputClock, OutputClock, LvdsUsed, &pll_parameter );
dkato	0:853f5b7408a7	423
dkato	0:853f5b7408a7	424	vdc5_lvds.lvds_in_clk_sel = VDC5_LVDS_INCLK_SEL_PERI; /* P1 */
dkato	0:853f5b7408a7	425	vdc5_lvds.lvds_idiv_set = (vdc5_lvds_ndiv_t)pll_parameter.nidiv;
dkato	0:853f5b7408a7	426	vdc5_lvds.lvdspll_tst = 16u;
dkato	0:853f5b7408a7	427	vdc5_lvds.lvds_odiv_set = (vdc5_lvds_ndiv_t)pll_parameter.nodiv;
dkato	0:853f5b7408a7	428	vdc5_lvds.lvdspll_tst = 16u;
dkato	0:853f5b7408a7	429	vdc5_lvds.lvds_vdc_sel = ch;
dkato	0:853f5b7408a7	430	vdc5_lvds.lvdspll_fd = pll_parameter.nfd;
dkato	0:853f5b7408a7	431	vdc5_lvds.lvdspll_rd = pll_parameter.nrd;
dkato	0:853f5b7408a7	432	vdc5_lvds.lvdspll_od = (vdc5_lvds_pll_nod_t)pll_parameter.nod;
dkato	0:853f5b7408a7	433	init.lvds = &vdc5_lvds; /* LVDS parameter */
dkato	0:853f5b7408a7	434
dkato	0:853f5b7408a7	435	/* Initialize (Set module clock to VDC5) */
dkato	0:853f5b7408a7	436	error = R_VDC5_Initialize( ch, &init, &init_func, (uint32_t)ch );
dkato	0:853f5b7408a7	437	if (error != VDC5_OK) {
dkato	0:853f5b7408a7	438	drv_error = DRV_GRAPHICS_VDC5_ERR;
dkato	0:853f5b7408a7	439	}
dkato	0:853f5b7408a7	440
dkato	0:853f5b7408a7	441	if ( drv_error == DRV_GRAPHICS_OK ) {
dkato	0:853f5b7408a7	442	vdc5_sync_ctrl_t sync_ctrl;
dkato	0:853f5b7408a7	443
dkato	0:853f5b7408a7	444	/* Sync signal control */
dkato	0:853f5b7408a7	445	sync_ctrl.res_vs_sel = VDC5_ON; /* Vsync signal output select (free-running Vsync on/off control) */
dkato	0:853f5b7408a7	446	/* Sync signal output and full-screen enable signal select */
dkato	0:853f5b7408a7	447	sync_ctrl.res_vs_in_sel = VDC5_RES_VS_IN_SEL_SC0;
dkato	0:853f5b7408a7	448	sync_ctrl.res_fv = drv_lcd_config->v_toatal_period-1; /* Free-running Vsync period setting */
dkato	0:853f5b7408a7	449	sync_ctrl.res_fh = drv_lcd_config->h_toatal_period-1; /* Hsync period setting */
dkato	0:853f5b7408a7	450	sync_ctrl.res_vsdly = (uint16_t)0u; /* Vsync signal delay control */
dkato	0:853f5b7408a7	451	/* Full-screen enable control */
dkato	0:853f5b7408a7	452	sync_ctrl.res_f.vs = (drv_lcd_config->v_back_porch);
dkato	0:853f5b7408a7	453	sync_ctrl.res_f.vw = (drv_lcd_config->v_disp_widht);
dkato	0:853f5b7408a7	454	sync_ctrl.res_f.hs = (drv_lcd_config->h_back_porch);
dkato	0:853f5b7408a7	455	sync_ctrl.res_f.hw = (drv_lcd_config->h_disp_widht);
dkato	0:853f5b7408a7	456	sync_ctrl.vsync_cpmpe = NULL; /* Vsync signal compensation */
dkato	0:853f5b7408a7	457	/* Sync control */
dkato	0:853f5b7408a7	458	error = R_VDC5_SyncControl( ch, &sync_ctrl );
dkato	0:853f5b7408a7	459	if (error != VDC5_OK) {
dkato	0:853f5b7408a7	460	drv_error = DRV_GRAPHICS_VDC5_ERR;
dkato	0:853f5b7408a7	461	}
dkato	0:853f5b7408a7	462	}
dkato	0:853f5b7408a7	463
dkato	0:853f5b7408a7	464	if ( drv_error == DRV_GRAPHICS_OK ) {
dkato	0:853f5b7408a7	465	vdc5_output_t output;
dkato	0:853f5b7408a7	466	vdc5_lcd_tcon_timing_t lcd_tcon_timing_VS;
dkato	0:853f5b7408a7	467	vdc5_lcd_tcon_timing_t lcd_tcon_timing_VE;
dkato	0:853f5b7408a7	468	vdc5_lcd_tcon_timing_t lcd_tcon_timing_HS;
dkato	0:853f5b7408a7	469	vdc5_lcd_tcon_timing_t lcd_tcon_timing_HE;
dkato	0:853f5b7408a7	470	vdc5_lcd_tcon_timing_t lcd_tcon_timing_DE;
dkato	0:853f5b7408a7	471
dkato	0:853f5b7408a7	472	/* Output parameter */
dkato	0:853f5b7408a7	473	output.tcon_half = (drv_lcd_config->h_toatal_period-1)/2; /* TCON reference timing, 1/2fH timing */
dkato	0:853f5b7408a7	474	output.tcon_offset = 0; /* TCON reference timing, offset Hsync signal timing */
dkato	0:853f5b7408a7	475
dkato	0:853f5b7408a7	476	/* LCD TCON timing setting */
dkato	0:853f5b7408a7	477	if( drv_lcd_config->v_sync_port != DRV_LCD_TCON_PIN_NON ) {
dkato	0:853f5b7408a7	478	lcd_tcon_timing_VS.tcon_hsvs = 0u;
dkato	0:853f5b7408a7	479	lcd_tcon_timing_VS.tcon_hwvw = (drv_lcd_config->v_sync_width * 2u);
dkato	0:853f5b7408a7	480	lcd_tcon_timing_VS.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
dkato	0:853f5b7408a7	481	lcd_tcon_timing_VS.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
dkato	0:853f5b7408a7	482	lcd_tcon_timing_VS.tcon_inv = (vdc5_sig_pol_t)drv_lcd_config->v_sync_port_polarity;
dkato	0:853f5b7408a7	483	lcd_tcon_timing_VS.tcon_pin = (vdc5_lcd_tcon_pin_t)drv_lcd_config->v_sync_port;
dkato	0:853f5b7408a7	484	lcd_tcon_timing_VS.outcnt_edge = VDC5_EDGE_FALLING;
dkato	0:853f5b7408a7	485	output.outctrl[VDC5_LCD_TCONSIG_STVA_VS] = &lcd_tcon_timing_VS; /* STVA/VS: Vsync */
dkato	0:853f5b7408a7	486	} else {
dkato	0:853f5b7408a7	487	output.outctrl[VDC5_LCD_TCONSIG_STVA_VS] = NULL; /* STVA/VS: Vsync */
dkato	0:853f5b7408a7	488	}
dkato	0:853f5b7408a7	489
dkato	0:853f5b7408a7	490	if( drv_lcd_config->h_sync_port != DRV_LCD_TCON_PIN_NON ) {
dkato	0:853f5b7408a7	491	lcd_tcon_timing_HS.tcon_hsvs = 0u;
dkato	0:853f5b7408a7	492	lcd_tcon_timing_HS.tcon_hwvw = drv_lcd_config->h_sync_width;
dkato	0:853f5b7408a7	493	lcd_tcon_timing_HS.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
dkato	0:853f5b7408a7	494	lcd_tcon_timing_HS.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
dkato	0:853f5b7408a7	495	lcd_tcon_timing_HS.tcon_inv = (vdc5_sig_pol_t)drv_lcd_config->h_sync_port_polarity;
dkato	0:853f5b7408a7	496	lcd_tcon_timing_HS.tcon_pin = (vdc5_lcd_tcon_pin_t)drv_lcd_config->h_sync_port;
dkato	0:853f5b7408a7	497	lcd_tcon_timing_HS.outcnt_edge = VDC5_EDGE_FALLING;
dkato	0:853f5b7408a7	498	output.outctrl[VDC5_LCD_TCONSIG_STH_SP_HS] = &lcd_tcon_timing_HS; /* STH/SP/HS: Hsync */
dkato	0:853f5b7408a7	499	} else {
dkato	0:853f5b7408a7	500	output.outctrl[VDC5_LCD_TCONSIG_STH_SP_HS] = NULL; /* STH/SP/HS: Hsync */
dkato	0:853f5b7408a7	501	}
dkato	0:853f5b7408a7	502
dkato	0:853f5b7408a7	503	if( drv_lcd_config->de_port != DRV_LCD_TCON_PIN_NON ) {
dkato	0:853f5b7408a7	504	lcd_tcon_timing_VE.tcon_hsvs = (drv_lcd_config->v_back_porch * 2u);
dkato	0:853f5b7408a7	505	lcd_tcon_timing_VE.tcon_hwvw = (drv_lcd_config->v_disp_widht * 2u);
dkato	0:853f5b7408a7	506	lcd_tcon_timing_VE.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
dkato	0:853f5b7408a7	507	lcd_tcon_timing_VE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
dkato	0:853f5b7408a7	508	lcd_tcon_timing_VE.tcon_inv = (vdc5_sig_pol_t)drv_lcd_config->de_port_polarity;
dkato	0:853f5b7408a7	509	lcd_tcon_timing_VE.tcon_pin = VDC5_LCD_TCON_PIN_NON;
dkato	0:853f5b7408a7	510	lcd_tcon_timing_VE.outcnt_edge = VDC5_EDGE_FALLING;
dkato	0:853f5b7408a7	511	output.outctrl[VDC5_LCD_TCONSIG_STVB_VE] = &lcd_tcon_timing_VE; /* STVB/VE: Not used */
dkato	0:853f5b7408a7	512
dkato	0:853f5b7408a7	513	lcd_tcon_timing_HE.tcon_hsvs = drv_lcd_config->h_back_porch;
dkato	0:853f5b7408a7	514	lcd_tcon_timing_HE.tcon_hwvw = drv_lcd_config->h_disp_widht;
dkato	0:853f5b7408a7	515	lcd_tcon_timing_HE.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
dkato	0:853f5b7408a7	516	lcd_tcon_timing_HE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
dkato	0:853f5b7408a7	517	lcd_tcon_timing_HE.tcon_inv = (vdc5_sig_pol_t)drv_lcd_config->de_port_polarity;
dkato	0:853f5b7408a7	518	lcd_tcon_timing_HE.tcon_pin = VDC5_LCD_TCON_PIN_NON;
dkato	0:853f5b7408a7	519	lcd_tcon_timing_HE.outcnt_edge = VDC5_EDGE_FALLING;
dkato	0:853f5b7408a7	520	output.outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = &lcd_tcon_timing_HE; /* STB/LP/HE: Not used */
dkato	0:853f5b7408a7	521
dkato	0:853f5b7408a7	522	lcd_tcon_timing_DE.tcon_hsvs = 0u;
dkato	0:853f5b7408a7	523	lcd_tcon_timing_DE.tcon_hwvw = 0u;
dkato	0:853f5b7408a7	524	lcd_tcon_timing_DE.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
dkato	0:853f5b7408a7	525	lcd_tcon_timing_DE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
dkato	0:853f5b7408a7	526	lcd_tcon_timing_DE.tcon_inv = (vdc5_sig_pol_t)drv_lcd_config->de_port_polarity;
dkato	0:853f5b7408a7	527	lcd_tcon_timing_DE.tcon_pin = (vdc5_lcd_tcon_pin_t)drv_lcd_config->de_port;
dkato	0:853f5b7408a7	528	lcd_tcon_timing_DE.outcnt_edge = VDC5_EDGE_FALLING;
dkato	0:853f5b7408a7	529	output.outctrl[VDC5_LCD_TCONSIG_DE] = &lcd_tcon_timing_DE; /* DE */
dkato	0:853f5b7408a7	530	} else {
dkato	0:853f5b7408a7	531	output.outctrl[VDC5_LCD_TCONSIG_STVB_VE] = NULL; /* STVB/VE: Not used */
dkato	0:853f5b7408a7	532	output.outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = NULL; /* STB/LP/HE: Not used */
dkato	0:853f5b7408a7	533	output.outctrl[VDC5_LCD_TCONSIG_DE] = NULL; /* DE */
dkato	0:853f5b7408a7	534	}
dkato	0:853f5b7408a7	535
dkato	0:853f5b7408a7	536	output.outctrl[VDC5_LCD_TCONSIG_CPV_GCK] = NULL;
dkato	0:853f5b7408a7	537	output.outctrl[VDC5_LCD_TCONSIG_POLA] = NULL;
dkato	0:853f5b7408a7	538	output.outctrl[VDC5_LCD_TCONSIG_POLB] = NULL;
dkato	0:853f5b7408a7	539
dkato	0:853f5b7408a7	540	output.outcnt_lcd_edge = (vdc5_edge_t)drv_lcd_config->lcd_edge; /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
dkato	0:853f5b7408a7	541	output.out_endian_on = VDC5_OFF; /* Bit endian change on/off control */
dkato	0:853f5b7408a7	542	output.out_swap_on = VDC5_OFF; /* B/R signal swap on/off control */
dkato	0:853f5b7408a7	543	output.out_format = (vdc5_lcd_outformat_t)drv_lcd_config->lcd_outformat; /* Output format select */
dkato	0:853f5b7408a7	544	output.out_frq_sel = VDC5_LCD_PARALLEL_CLKFRQ_1; /* Clock frequency control */
dkato	0:853f5b7408a7	545	output.out_dir_sel = VDC5_LCD_SERIAL_SCAN_FORWARD; /* Scan direction select */
dkato	0:853f5b7408a7	546	output.out_phase = VDC5_LCD_SERIAL_CLKPHASE_0; /* Clock phase adjustment */
dkato	0:853f5b7408a7	547	output.bg_color = (uint32_t)0x00000000u; /* Background color in 24-bit RGB color format */
dkato	0:853f5b7408a7	548	/* Display output */
dkato	0:853f5b7408a7	549	error = R_VDC5_DisplayOutput( ch, &output );
dkato	0:853f5b7408a7	550	if (error != VDC5_OK) {
dkato	0:853f5b7408a7	551	drv_error = DRV_GRAPHICS_VDC5_ERR;
dkato	0:853f5b7408a7	552	}
dkato	0:853f5b7408a7	553	}
dkato	0:853f5b7408a7	554	return drv_error;
dkato	0:853f5b7408a7	555	} /* End of function DRV_Graphics_Init() */
dkato	0:853f5b7408a7	556
dkato	0:853f5b7408a7	557	/************************************************************************//
dkato	0:853f5b7408a7	558	* @brief Video initialization processing
dkato	0:853f5b7408a7	559	* @param[in] drv_video_ext_in_config : Video configuration
dkato	0:853f5b7408a7	560	* @retval Error code
dkato	0:853f5b7408a7	561	******************************************************************************/
dkato	0:853f5b7408a7	562	drv_graphics_error_t DRV_Graphics_Video_init( drv_video_input_sel_t drv_video_input_sel, drv_video_ext_in_config_t * drv_video_ext_in_config )
dkato	0:853f5b7408a7	563	{
dkato	0:853f5b7408a7	564	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
dkato	0:853f5b7408a7	565	vdc5_error_t error;
dkato	0:853f5b7408a7	566	vdc5_input_t input;
dkato	0:853f5b7408a7	567	vdc5_ext_in_sig_t ext_in_sig;
dkato	0:853f5b7408a7	568	vdc5_sync_delay_t sync_delay;
dkato	0:853f5b7408a7	569
dkato	0:853f5b7408a7	570	input.inp_sel = (vdc5_input_sel_t)drv_video_input_sel; /* Input select */
dkato	0:853f5b7408a7	571	input.inp_fh50 = (uint16_t)VSYNC_1_2_FH_TIMING; /* Vsync signal 1/2fH phase timing */
dkato	0:853f5b7408a7	572	input.inp_fh25 = (uint16_t)VSYNC_1_4_FH_TIMING; /* Vsync signal 1/4fH phase timing */
dkato	0:853f5b7408a7	573
dkato	0:853f5b7408a7	574	if( drv_video_input_sel == DRV_INPUT_SEL_VDEC ) {
dkato	0:853f5b7408a7	575	input.dly = NULL; /* Sync signal delay adjustment */
dkato	0:853f5b7408a7	576	input.ext_sig = NULL; /* External input signal */
dkato	0:853f5b7408a7	577	} else {
dkato	0:853f5b7408a7	578	ext_in_sig.inp_format = (vdc5_extin_format_t)drv_video_ext_in_config->inp_format;
dkato	0:853f5b7408a7	579	ext_in_sig.inp_pxd_edge = (vdc5_edge_t)drv_video_ext_in_config->inp_pxd_edge;
dkato	0:853f5b7408a7	580	ext_in_sig.inp_vs_edge = (vdc5_edge_t)drv_video_ext_in_config->inp_vs_edge;
dkato	0:853f5b7408a7	581	ext_in_sig.inp_hs_edge = (vdc5_edge_t)drv_video_ext_in_config->inp_hs_edge;
dkato	0:853f5b7408a7	582	ext_in_sig.inp_endian_on = (vdc5_onoff_t)drv_video_ext_in_config->inp_endian_on;
dkato	0:853f5b7408a7	583	ext_in_sig.inp_swap_on = (vdc5_onoff_t)drv_video_ext_in_config->inp_swap_on;
dkato	0:853f5b7408a7	584	ext_in_sig.inp_vs_inv = (vdc5_sig_pol_t)drv_video_ext_in_config->inp_vs_inv;
dkato	0:853f5b7408a7	585	ext_in_sig.inp_hs_inv = (vdc5_sig_pol_t)drv_video_ext_in_config->inp_hs_inv;
dkato	0:853f5b7408a7	586	ext_in_sig.inp_h_edge_sel = (vdc5_extin_ref_hsync_t)drv_video_ext_in_config->inp_hs_edge;
dkato	0:853f5b7408a7	587	ext_in_sig.inp_f525_625 = (vdc5_extin_input_line_t)drv_video_ext_in_config->inp_f525_625;
dkato	0:853f5b7408a7	588	ext_in_sig.inp_h_pos = (vdc5_extin_h_pos_t)drv_video_ext_in_config->inp_h_pos;
dkato	0:853f5b7408a7	589
dkato	0:853f5b7408a7	590	sync_delay.inp_vs_dly_l = 0u;
dkato	0:853f5b7408a7	591	sync_delay.inp_vs_dly = 16u;
dkato	0:853f5b7408a7	592	sync_delay.inp_hs_dly = 16u;
dkato	0:853f5b7408a7	593	sync_delay.inp_fld_dly = 16u;
dkato	0:853f5b7408a7	594
dkato	0:853f5b7408a7	595	input.dly = &sync_delay; /* Sync signal delay adjustment */
dkato	0:853f5b7408a7	596	input.ext_sig = &ext_in_sig; /* External input signal */
dkato	0:853f5b7408a7	597	}
dkato	0:853f5b7408a7	598	/* Video input 0ch */
dkato	0:853f5b7408a7	599	error = R_VDC5_VideoInput( VDC5_CHANNEL_0, &input );
dkato	0:853f5b7408a7	600	if (error != VDC5_OK) {
dkato	0:853f5b7408a7	601	drv_error = DRV_GRAPHICS_VDC5_ERR;
dkato	0:853f5b7408a7	602	}
dkato	0:853f5b7408a7	603
dkato	0:853f5b7408a7	604	if( drv_video_input_sel == DRV_INPUT_SEL_VDEC ) {
dkato	0:853f5b7408a7	605	if ( drv_error == DRV_GRAPHICS_OK ) {
dkato	0:853f5b7408a7	606	/* Video input 1ch */
dkato	0:853f5b7408a7	607	error = R_VDC5_VideoInput( VDC5_CHANNEL_1, &input );
dkato	0:853f5b7408a7	608	if (error != VDC5_OK) {
dkato	0:853f5b7408a7	609	drv_error = DRV_GRAPHICS_VDC5_ERR;
dkato	0:853f5b7408a7	610	}
dkato	0:853f5b7408a7	611	}
dkato	0:853f5b7408a7	612	}
dkato	0:853f5b7408a7	613	return drv_error;
dkato	0:853f5b7408a7	614	} /* End of function DRV_Video_Init() */
dkato	0:853f5b7408a7	615
dkato	0:853f5b7408a7	616	/************************************************************************//
dkato	0:853f5b7408a7	617	* @brief Start the graphics surface read process
dkato	0:853f5b7408a7	618	* @param[in] layer_id : Graphics layer ID
dkato	0:853f5b7408a7	619	* @retval drv_graphics_error_t
dkato	0:853f5b7408a7	620	******************************************************************************/
dkato	0:853f5b7408a7	621	drv_graphics_error_t DRV_Graphics_Start ( drv_graphics_layer_t layer_id )
dkato	0:853f5b7408a7	622	{
dkato	0:853f5b7408a7	623	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
dkato	0:853f5b7408a7	624	vdc5_channel_t ch = VDC5_CHANNEL_0;
dkato	0:853f5b7408a7	625	vdc5_error_t error;
dkato	0:853f5b7408a7	626	vdc5_start_t start;
dkato	0:853f5b7408a7	627	vdc5_gr_disp_sel_t gr_disp_sel;
dkato	0:853f5b7408a7	628	vdc5_layer_id_t vdc5_layer_id;
dkato	0:853f5b7408a7	629
dkato	0:853f5b7408a7	630	switch( layer_id ) {
dkato	0:853f5b7408a7	631	case DRV_GRAPHICS_LAYER_0:
dkato	0:853f5b7408a7	632	vdc5_layer_id = VDC5_LAYER_ID_0_RD;
dkato	0:853f5b7408a7	633	gr_disp_sel = VDC5_DISPSEL_CURRENT;
dkato	0:853f5b7408a7	634	break;
dkato	0:853f5b7408a7	635	case DRV_GRAPHICS_LAYER_1:
dkato	0:853f5b7408a7	636	vdc5_layer_id = VDC5_LAYER_ID_1_RD;
dkato	0:853f5b7408a7	637	gr_disp_sel = VDC5_DISPSEL_BLEND;
dkato	0:853f5b7408a7	638	break;
dkato	0:853f5b7408a7	639	case DRV_GRAPHICS_LAYER_2:
dkato	0:853f5b7408a7	640	vdc5_layer_id = VDC5_LAYER_ID_2_RD;
dkato	0:853f5b7408a7	641	gr_disp_sel = VDC5_DISPSEL_BLEND;
dkato	0:853f5b7408a7	642	break;
dkato	0:853f5b7408a7	643	case DRV_GRAPHICS_LAYER_3:
dkato	0:853f5b7408a7	644	vdc5_layer_id = VDC5_LAYER_ID_3_RD;
dkato	0:853f5b7408a7	645	gr_disp_sel = VDC5_DISPSEL_BLEND;
dkato	0:853f5b7408a7	646	break;
dkato	0:853f5b7408a7	647	default:
dkato	0:853f5b7408a7	648	drv_error = DRV_GRAPHICS_LAYER_ERR;
dkato	0:853f5b7408a7	649	break;
dkato	0:853f5b7408a7	650	}
dkato	0:853f5b7408a7	651
dkato	0:853f5b7408a7	652	if( drv_error == DRV_GRAPHICS_OK ) {
dkato	0:853f5b7408a7	653	/* Start process */
dkato	0:853f5b7408a7	654	start.gr_disp_sel = &gr_disp_sel;
dkato	0:853f5b7408a7	655	error = R_VDC5_StartProcess( ch, vdc5_layer_id, &start );
dkato	0:853f5b7408a7	656	if (error != VDC5_OK) {
dkato	0:853f5b7408a7	657	drv_error = DRV_GRAPHICS_VDC5_ERR;
dkato	0:853f5b7408a7	658	}
dkato	0:853f5b7408a7	659	}
dkato	0:853f5b7408a7	660	return drv_error;
dkato	0:853f5b7408a7	661	} /* End of function DRV_Graphics_Start() */
dkato	0:853f5b7408a7	662
dkato	0:853f5b7408a7	663	/************************************************************************//
dkato	0:853f5b7408a7	664	* @brief Stop the graphics surface read process
dkato	0:853f5b7408a7	665	* @param[in] layer_id : Graphics layer ID
dkato	0:853f5b7408a7	666	* @retval Error code
dkato	0:853f5b7408a7	667	******************************************************************************/
dkato	0:853f5b7408a7	668	drv_graphics_error_t DRV_Graphics_Stop ( drv_graphics_layer_t layer_id )
dkato	0:853f5b7408a7	669	{
dkato	0:853f5b7408a7	670	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
dkato	0:853f5b7408a7	671	vdc5_channel_t ch = VDC5_CHANNEL_0;
dkato	0:853f5b7408a7	672	vdc5_error_t error;
dkato	0:853f5b7408a7	673	vdc5_layer_id_t vdc5_layer_id;
dkato	0:853f5b7408a7	674
dkato	0:853f5b7408a7	675	switch( layer_id ) {
dkato	0:853f5b7408a7	676	case DRV_GRAPHICS_LAYER_0:
dkato	0:853f5b7408a7	677	vdc5_layer_id = VDC5_LAYER_ID_0_RD;
dkato	0:853f5b7408a7	678	break;
dkato	0:853f5b7408a7	679	case DRV_GRAPHICS_LAYER_1:
dkato	0:853f5b7408a7	680	vdc5_layer_id = VDC5_LAYER_ID_1_RD;
dkato	0:853f5b7408a7	681	break;
dkato	0:853f5b7408a7	682	case DRV_GRAPHICS_LAYER_2:
dkato	0:853f5b7408a7	683	vdc5_layer_id = VDC5_LAYER_ID_2_RD;
dkato	0:853f5b7408a7	684	break;
dkato	0:853f5b7408a7	685	case DRV_GRAPHICS_LAYER_3:
dkato	0:853f5b7408a7	686	vdc5_layer_id = VDC5_LAYER_ID_3_RD;
dkato	0:853f5b7408a7	687	break;
dkato	0:853f5b7408a7	688	default:
dkato	0:853f5b7408a7	689	drv_error = DRV_GRAPHICS_LAYER_ERR;
dkato	0:853f5b7408a7	690	break;
dkato	0:853f5b7408a7	691	}
dkato	0:853f5b7408a7	692
dkato	0:853f5b7408a7	693	if( drv_error == DRV_GRAPHICS_OK ) {
dkato	0:853f5b7408a7	694	/* Stop process */
dkato	0:853f5b7408a7	695	error = R_VDC5_StopProcess ( ch, vdc5_layer_id );
dkato	0:853f5b7408a7	696	if (error != VDC5_OK) {
dkato	0:853f5b7408a7	697	drv_error = DRV_GRAPHICS_VDC5_ERR;
dkato	0:853f5b7408a7	698	}
dkato	0:853f5b7408a7	699	}
dkato	0:853f5b7408a7	700	return drv_error;
dkato	0:853f5b7408a7	701	} /* End of function DRV_Graphics_Stop() */
dkato	0:853f5b7408a7	702
dkato	0:853f5b7408a7	703	/************************************************************************//
dkato	0:853f5b7408a7	704	* @brief Start the video surface write process
dkato	0:853f5b7408a7	705	* @param[in] video_input_ch : Video input channel
dkato	0:853f5b7408a7	706	* @retval Error code
dkato	0:853f5b7408a7	707	******************************************************************************/
dkato	0:853f5b7408a7	708	drv_graphics_error_t DRV_Video_Start ( drv_video_input_channel_t video_input_ch )
dkato	0:853f5b7408a7	709	{
dkato	0:853f5b7408a7	710	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
dkato	0:853f5b7408a7	711	vdc5_channel_t ch = VDC5_CHANNEL_0;
dkato	0:853f5b7408a7	712	vdc5_error_t error;
dkato	0:853f5b7408a7	713	vdc5_start_t start;
dkato	0:853f5b7408a7	714	vdc5_gr_disp_sel_t gr_disp_sel;
dkato	0:853f5b7408a7	715	vdc5_layer_id_t vdc5_layer_id;
dkato	0:853f5b7408a7	716
dkato	0:853f5b7408a7	717	if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) {
dkato	0:853f5b7408a7	718	vdc5_layer_id = VDC5_LAYER_ID_0_WR;
dkato	0:853f5b7408a7	719	} else if ( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1 ) {
dkato	0:853f5b7408a7	720	vdc5_layer_id = VDC5_LAYER_ID_1_WR;
dkato	0:853f5b7408a7	721	} else {
dkato	0:853f5b7408a7	722	drv_error = DRV_GRAPHICS_LAYER_ERR;
dkato	0:853f5b7408a7	723	}
dkato	0:853f5b7408a7	724
dkato	0:853f5b7408a7	725	if( drv_error == DRV_GRAPHICS_OK ) {
dkato	0:853f5b7408a7	726	/* Start process */
dkato	0:853f5b7408a7	727	gr_disp_sel = VDC5_DISPSEL_CURRENT; /* CURRENT fixed for weave input mode */
dkato	0:853f5b7408a7	728	start.gr_disp_sel = &gr_disp_sel;
dkato	0:853f5b7408a7	729	error = R_VDC5_StartProcess( ch, vdc5_layer_id, &start );
dkato	0:853f5b7408a7	730	if (error != VDC5_OK) {
dkato	0:853f5b7408a7	731	drv_error = DRV_GRAPHICS_VDC5_ERR;
dkato	0:853f5b7408a7	732	}
dkato	0:853f5b7408a7	733	}
dkato	0:853f5b7408a7	734	return drv_error;
dkato	0:853f5b7408a7	735	} /* End of function DRV_Video_Start() */
dkato	0:853f5b7408a7	736
dkato	0:853f5b7408a7	737	/************************************************************************//
dkato	0:853f5b7408a7	738	* @brief Stop the video surface write process
dkato	0:853f5b7408a7	739	* @param[in] video_input_ch : Video input channel
dkato	0:853f5b7408a7	740	* @retval Error code
dkato	0:853f5b7408a7	741	******************************************************************************/
dkato	0:853f5b7408a7	742	drv_graphics_error_t DRV_Video_Stop ( drv_video_input_channel_t video_input_ch )
dkato	0:853f5b7408a7	743	{
dkato	0:853f5b7408a7	744	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
dkato	0:853f5b7408a7	745	vdc5_channel_t ch = VDC5_CHANNEL_0;
dkato	0:853f5b7408a7	746	vdc5_error_t error;
dkato	0:853f5b7408a7	747	vdc5_layer_id_t vdc5_layer_id;
dkato	0:853f5b7408a7	748
dkato	0:853f5b7408a7	749	switch (video_input_ch) {
dkato	0:853f5b7408a7	750	case DRV_VIDEO_INPUT_CHANNEL_0:
dkato	0:853f5b7408a7	751	vdc5_layer_id = VDC5_LAYER_ID_0_WR;
dkato	0:853f5b7408a7	752	break;
dkato	0:853f5b7408a7	753	case DRV_VIDEO_INPUT_CHANNEL_1:
dkato	0:853f5b7408a7	754	vdc5_layer_id = VDC5_LAYER_ID_1_WR;
dkato	0:853f5b7408a7	755	break;
dkato	0:853f5b7408a7	756	default:
dkato	0:853f5b7408a7	757	drv_error = DRV_GRAPHICS_LAYER_ERR;
dkato	0:853f5b7408a7	758	break;
dkato	0:853f5b7408a7	759	}
dkato	0:853f5b7408a7	760
dkato	0:853f5b7408a7	761	if( drv_error == DRV_GRAPHICS_OK ) {
dkato	0:853f5b7408a7	762	/* Stop process */
dkato	0:853f5b7408a7	763	error = R_VDC5_StopProcess ( ch, vdc5_layer_id );
dkato	0:853f5b7408a7	764	if (error != VDC5_OK) {
dkato	0:853f5b7408a7	765	drv_error = DRV_GRAPHICS_VDC5_ERR;
dkato	0:853f5b7408a7	766	}
dkato	0:853f5b7408a7	767	}
dkato	0:853f5b7408a7	768	return drv_error;
dkato	0:853f5b7408a7	769	} /* End of function DRV_Video_Stop() */
dkato	0:853f5b7408a7	770
dkato	0:853f5b7408a7	771	/************************************************************************//
dkato	0:853f5b7408a7	772	* @brief Graphics surface read process setting
dkato	0:853f5b7408a7	773	*
dkato	0:853f5b7408a7	774	* Description:<br>
dkato	0:853f5b7408a7	775	* This function supports the following 4 image format.
dkato	0:853f5b7408a7	776	* YCbCr422, RGB565, RGB888, ARGB8888
dkato	0:853f5b7408a7	777	* @param[in] layer_id : Graphics layer ID
dkato	0:853f5b7408a7	778	* @param[in] framebuff : Base address of the frame buffer
dkato	0:853f5b7408a7	779	* @param[in] fb_stride : Line offset address of the frame buffer
dkato	0:853f5b7408a7	780	* @param[in] gr_format : Format of the frame buffer read signal
dkato	0:853f5b7408a7	781	* @param[in] gr_rect : Graphics display area
dkato	0:853f5b7408a7	782	* @retval Error code
dkato	0:853f5b7408a7	783	******************************************************************************/
dkato	0:853f5b7408a7	784	drv_graphics_error_t DRV_Graphics_Read_Setting (
dkato	0:853f5b7408a7	785	drv_graphics_layer_t layer_id,
dkato	0:853f5b7408a7	786	void * framebuff,
dkato	0:853f5b7408a7	787	uint32_t fb_stride,
dkato	0:853f5b7408a7	788	drv_graphics_format_t gr_format,
dkato	0:853f5b7408a7	789	drv_wr_rd_swa_t wr_rd_swa,
dkato	0:853f5b7408a7	790	drv_rect_t * gr_rect )
dkato	0:853f5b7408a7	791	{
dkato	0:853f5b7408a7	792	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
dkato	0:853f5b7408a7	793	vdc5_channel_t ch = VDC5_CHANNEL_0;
dkato	0:853f5b7408a7	794	vdc5_error_t error;
dkato	0:853f5b7408a7	795	vdc5_layer_id_t vdc5_layer_id;
dkato	0:853f5b7408a7	796	vdc5_gr_format_t vdc5_gr_format;
dkato	0:853f5b7408a7	797	vdc5_read_t read;
dkato	0:853f5b7408a7	798
dkato	0:853f5b7408a7	799	switch(layer_id) {
dkato	0:853f5b7408a7	800	case DRV_GRAPHICS_LAYER_0:
dkato	0:853f5b7408a7	801	vdc5_layer_id = VDC5_LAYER_ID_0_RD;
dkato	0:853f5b7408a7	802	break;
dkato	0:853f5b7408a7	803	case DRV_GRAPHICS_LAYER_1:
dkato	0:853f5b7408a7	804	vdc5_layer_id = VDC5_LAYER_ID_1_RD;
dkato	0:853f5b7408a7	805	break;
dkato	0:853f5b7408a7	806	case DRV_GRAPHICS_LAYER_2:
dkato	0:853f5b7408a7	807	vdc5_layer_id = VDC5_LAYER_ID_2_RD;
dkato	0:853f5b7408a7	808	break;
dkato	0:853f5b7408a7	809	case DRV_GRAPHICS_LAYER_3:
dkato	0:853f5b7408a7	810	vdc5_layer_id = VDC5_LAYER_ID_3_RD;
dkato	0:853f5b7408a7	811	break;
dkato	0:853f5b7408a7	812	default:
dkato	0:853f5b7408a7	813	drv_error = DRV_GRAPHICS_LAYER_ERR;
dkato	0:853f5b7408a7	814	break;
dkato	0:853f5b7408a7	815	}
dkato	0:853f5b7408a7	816
dkato	0:853f5b7408a7	817	if( drv_error == DRV_GRAPHICS_OK ) {
dkato	0:853f5b7408a7	818	switch( gr_format ) {
dkato	0:853f5b7408a7	819	case DRV_GRAPHICS_FORMAT_YCBCR422:
dkato	0:853f5b7408a7	820	vdc5_gr_format = VDC5_GR_FORMAT_YCBCR422;
dkato	0:853f5b7408a7	821	break;
dkato	0:853f5b7408a7	822	case DRV_GRAPHICS_FORMAT_RGB565:
dkato	0:853f5b7408a7	823	vdc5_gr_format = VDC5_GR_FORMAT_RGB565;
dkato	0:853f5b7408a7	824	break;
dkato	0:853f5b7408a7	825	case DRV_GRAPHICS_FORMAT_RGB888:
dkato	0:853f5b7408a7	826	vdc5_gr_format = VDC5_GR_FORMAT_RGB888;
dkato	0:853f5b7408a7	827	break;
dkato	0:853f5b7408a7	828	case DRV_GRAPHICS_FORMAT_ARGB8888:
dkato	0:853f5b7408a7	829	vdc5_gr_format = VDC5_GR_FORMAT_ARGB8888;
dkato	0:853f5b7408a7	830	break;
dkato	4:aeefe5171463	831	case DRV_GRAPHICS_FORMAT_ARGB4444:
dkato	4:aeefe5171463	832	vdc5_gr_format = VDC5_GR_FORMAT_ARGB4444;
dkato	4:aeefe5171463	833	break;
dkato	0:853f5b7408a7	834	default:
dkato	0:853f5b7408a7	835	drv_error = DRV_GRAPHICS_FORMAT_ERR;
dkato	0:853f5b7408a7	836	break;
dkato	0:853f5b7408a7	837	}
dkato	0:853f5b7408a7	838	}
dkato	0:853f5b7408a7	839
dkato	0:853f5b7408a7	840	if( drv_error == DRV_GRAPHICS_OK ) {
dkato	0:853f5b7408a7	841	/* Read data parameter */
dkato	0:853f5b7408a7	842	read.gr_ln_off_dir = VDC5_GR_LN_OFF_DIR_INC; /* Line offset address direction of the frame buffer */
dkato	0:853f5b7408a7	843	read.gr_flm_sel = VDC5_GR_FLM_SEL_FLM_NUM; /* Selects a frame buffer address setting signal */
dkato	0:853f5b7408a7	844	read.gr_imr_flm_inv = VDC5_OFF; /* Frame buffer number for distortion correction */
dkato	0:853f5b7408a7	845	read.gr_bst_md = VDC5_BST_MD_32BYTE; /* Frame buffer burst transfer mode */
dkato	0:853f5b7408a7	846	read.gr_base = framebuff; /* Frame buffer base address */
dkato	0:853f5b7408a7	847	read.gr_ln_off = fb_stride; /* Frame buffer line offset address */
dkato	0:853f5b7408a7	848
dkato	0:853f5b7408a7	849	read.width_read_fb = NULL; /* Width of the image read from frame buffer */
dkato	0:853f5b7408a7	850
dkato	0:853f5b7408a7	851	read.adj_sel = VDC5_OFF; /* Measures to decrease the influence
dkato	0:853f5b7408a7	852	by folding pixels/lines (on/off) */
dkato	0:853f5b7408a7	853	read.gr_format = vdc5_gr_format; /* Format of the frame buffer read signal */
dkato	0:853f5b7408a7	854	read.gr_ycc_swap = VDC5_GR_YCCSWAP_CBY0CRY1; /* Controls swapping of data read from buffer
dkato	0:853f5b7408a7	855	in the YCbCr422 format */
dkato	0:853f5b7408a7	856	read.gr_rdswa = (vdc5_wr_rd_swa_t)wr_rd_swa; /* Frame buffer swap setting */
dkato	0:853f5b7408a7	857	/* Display area */
dkato	0:853f5b7408a7	858	read.gr_grc.vs = gr_rect->vs;
dkato	0:853f5b7408a7	859	read.gr_grc.vw = gr_rect->vw;
dkato	0:853f5b7408a7	860	read.gr_grc.hs = gr_rect->hs;
dkato	0:853f5b7408a7	861	read.gr_grc.hw = gr_rect->hw;
dkato	0:853f5b7408a7	862
dkato	0:853f5b7408a7	863	/* Read data control */
dkato	0:853f5b7408a7	864	error = R_VDC5_ReadDataControl( ch, vdc5_layer_id, &read );
dkato	0:853f5b7408a7	865	if (error != VDC5_OK) {
dkato	0:853f5b7408a7	866	drv_error = DRV_GRAPHICS_VDC5_ERR;
dkato	0:853f5b7408a7	867	}
dkato	0:853f5b7408a7	868	}
dkato	0:853f5b7408a7	869	return drv_error;
dkato	0:853f5b7408a7	870	} /* End of function DRV_Graphics_Read_Setting() */
dkato	0:853f5b7408a7	871
dkato	0:853f5b7408a7	872	/************************************************************************//
dkato	0:853f5b7408a7	873	* @brief Graphics surface read buffer change process
dkato	0:853f5b7408a7	874	* @param[in] layer_id : Graphics layer ID
dkato	0:853f5b7408a7	875	* @param[in] framebuff : Base address of the frame buffer
dkato	0:853f5b7408a7	876	* @retval Error code
dkato	0:853f5b7408a7	877	******************************************************************************/
dkato	0:853f5b7408a7	878	drv_graphics_error_t DRV_Graphics_Read_Change (
dkato	0:853f5b7408a7	879	drv_graphics_layer_t layer_id,
dkato	0:853f5b7408a7	880	void * framebuff)
dkato	0:853f5b7408a7	881	{
dkato	0:853f5b7408a7	882	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
dkato	0:853f5b7408a7	883	vdc5_channel_t ch = VDC5_CHANNEL_0;
dkato	0:853f5b7408a7	884	vdc5_error_t error;
dkato	0:853f5b7408a7	885	vdc5_layer_id_t vdc5_layer_id;
dkato	0:853f5b7408a7	886	vdc5_read_chg_t read_chg;
dkato	0:853f5b7408a7	887
dkato	0:853f5b7408a7	888	switch(layer_id) {
dkato	0:853f5b7408a7	889	case DRV_GRAPHICS_LAYER_0:
dkato	0:853f5b7408a7	890	vdc5_layer_id = VDC5_LAYER_ID_0_RD;
dkato	0:853f5b7408a7	891	break;
dkato	0:853f5b7408a7	892	case DRV_GRAPHICS_LAYER_1:
dkato	0:853f5b7408a7	893	vdc5_layer_id = VDC5_LAYER_ID_1_RD;
dkato	0:853f5b7408a7	894	break;
dkato	0:853f5b7408a7	895	case DRV_GRAPHICS_LAYER_2:
dkato	0:853f5b7408a7	896	vdc5_layer_id = VDC5_LAYER_ID_2_RD;
dkato	0:853f5b7408a7	897	break;
dkato	0:853f5b7408a7	898	case DRV_GRAPHICS_LAYER_3:
dkato	0:853f5b7408a7	899	vdc5_layer_id = VDC5_LAYER_ID_3_RD;
dkato	0:853f5b7408a7	900	break;
dkato	0:853f5b7408a7	901	default:
dkato	0:853f5b7408a7	902	drv_error = DRV_GRAPHICS_LAYER_ERR;
dkato	0:853f5b7408a7	903	break;
dkato	0:853f5b7408a7	904	}
dkato	0:853f5b7408a7	905
dkato	0:853f5b7408a7	906	if( drv_error == DRV_GRAPHICS_OK ) {
dkato	0:853f5b7408a7	907	/* Read data parameter */
dkato	0:853f5b7408a7	908	read_chg.width_read_fb = NULL; /* Width of the image read from frame buffer */
dkato	0:853f5b7408a7	909	read_chg.gr_grc = NULL; /* Display area */
dkato	0:853f5b7408a7	910	read_chg.gr_disp_sel = NULL; /* Graphics display mode */
dkato	0:853f5b7408a7	911	read_chg.gr_base = framebuff; /* Frame buffer base address */
dkato	0:853f5b7408a7	912
dkato	0:853f5b7408a7	913	/* Change read process */
dkato	0:853f5b7408a7	914	error = R_VDC5_ChangeReadProcess( ch, vdc5_layer_id, &read_chg );
dkato	0:853f5b7408a7	915	if (error != VDC5_OK) {
dkato	0:853f5b7408a7	916	drv_error = DRV_GRAPHICS_VDC5_ERR;
dkato	0:853f5b7408a7	917	}
dkato	0:853f5b7408a7	918	}
dkato	0:853f5b7408a7	919	return drv_error;
dkato	0:853f5b7408a7	920	} /* End of function DRV_Graphics_Read_Change() */
dkato	0:853f5b7408a7	921
dkato	0:853f5b7408a7	922	/************************************************************************//
dkato	0:853f5b7408a7	923	* @brief Video surface write process setting
dkato	0:853f5b7408a7	924	*
dkato	0:853f5b7408a7	925	* Description:<br>
dkato	0:853f5b7408a7	926	* This function set the video write process. Input form is weave
dkato	0:853f5b7408a7	927	* (progressive) mode fixed.
dkato	0:853f5b7408a7	928	* This function supports the following 3 image format.
dkato	0:853f5b7408a7	929	* YCbCr422, RGB565, RGB888
dkato	0:853f5b7408a7	930	* @param[in] video_input_ch : Video input channel
dkato	0:853f5b7408a7	931	* @param[in] col_sys : Analog video signal color system
dkato	0:853f5b7408a7	932	* @param[in] adc_vinsel : Video input pin
dkato	0:853f5b7408a7	933	* @param[in] framebuff : Base address of the frame buffer
dkato	0:853f5b7408a7	934	* @param[in] fb_stride [byte] : Line offset address of the frame buffer
dkato	0:853f5b7408a7	935	* @param[in] video_format : Frame buffer video-signal writing format
dkato	0:853f5b7408a7	936	* @param[in] wr_rd_swa : Frame buffer swap setting
dkato	0:853f5b7408a7	937	* @param[in] video_write_size_vw [px]: output height
dkato	0:853f5b7408a7	938	* @param[in] video_write_size_hw [px]: output width
dkato	2:3149baf7925b	939	* @param[in] video_adc_vinsel : Input pin control
dkato	0:853f5b7408a7	940	* @retval Error code
dkato	0:853f5b7408a7	941	******************************************************************************/
dkato	0:853f5b7408a7	942	drv_graphics_error_t DRV_Video_Write_Setting (
dkato	0:853f5b7408a7	943	drv_video_input_channel_t video_input_ch,
dkato	0:853f5b7408a7	944	drv_graphics_video_col_sys_t col_sys,
dkato	0:853f5b7408a7	945	void * framebuff,
dkato	0:853f5b7408a7	946	uint32_t fb_stride,
dkato	0:853f5b7408a7	947	drv_video_format_t video_format,
dkato	0:853f5b7408a7	948	drv_wr_rd_swa_t wr_rd_swa,
dkato	0:853f5b7408a7	949	uint16_t video_write_buff_vw,
dkato	2:3149baf7925b	950	uint16_t video_write_buff_hw,
dkato	2:3149baf7925b	951	drv_video_adc_vinsel_t video_adc_vinsel )
dkato	0:853f5b7408a7	952	{
dkato	0:853f5b7408a7	953	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
dkato	0:853f5b7408a7	954	vdc5_channel_t ch = VDC5_CHANNEL_0;
dkato	0:853f5b7408a7	955	vdc5_error_t error;
dkato	0:853f5b7408a7	956	vdc5_layer_id_t vdc5_layer_id;
dkato	0:853f5b7408a7	957	vdc5_write_t write;
dkato	0:853f5b7408a7	958	vdc5_scalingdown_rot_t * scldw_rot;
dkato	0:853f5b7408a7	959	vdc5_res_md_t res_md;
dkato	0:853f5b7408a7	960	drv_rect_t video_in_rect;
dkato	0:853f5b7408a7	961	uint8_t * framebuffer_t;
dkato	0:853f5b7408a7	962	uint8_t * framebuffer_b;
dkato	0:853f5b7408a7	963
dkato	0:853f5b7408a7	964	if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) {
dkato	2:3149baf7925b	965	GRAPHICS_VideoDecoderInit( (vdec_adc_vinsel_t)video_adc_vinsel, VDEC_CHANNEL_0, (graphics_col_sys_t)col_sys );
dkato	0:853f5b7408a7	966	} else if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1 ) {
dkato	2:3149baf7925b	967	GRAPHICS_VideoDecoderInit( (vdec_adc_vinsel_t)video_adc_vinsel, VDEC_CHANNEL_1, (graphics_col_sys_t)col_sys );
dkato	0:853f5b7408a7	968	} else {
dkato	0:853f5b7408a7	969	drv_error = DRV_GRAPHICS_CHANNEL_ERR;
dkato	0:853f5b7408a7	970	}
dkato	0:853f5b7408a7	971
dkato	0:853f5b7408a7	972	if( drv_error == DRV_GRAPHICS_OK ) {
dkato	0:853f5b7408a7	973	if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) {
dkato	0:853f5b7408a7	974	vdc5_layer_id = VDC5_LAYER_ID_0_WR;
dkato	0:853f5b7408a7	975	} else if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1 ) {
dkato	0:853f5b7408a7	976	vdc5_layer_id = VDC5_LAYER_ID_1_WR;
dkato	0:853f5b7408a7	977	} else {
dkato	0:853f5b7408a7	978	drv_error = DRV_GRAPHICS_CHANNEL_ERR;
dkato	0:853f5b7408a7	979	}
dkato	0:853f5b7408a7	980	}
dkato	0:853f5b7408a7	981
dkato	0:853f5b7408a7	982	if( drv_error == DRV_GRAPHICS_OK ) {
dkato	0:853f5b7408a7	983	if( video_format == DRV_VIDEO_FORMAT_YCBCR422 ) {
dkato	0:853f5b7408a7	984	res_md = VDC5_RES_MD_YCBCR422;
dkato	0:853f5b7408a7	985	} else if( video_format == DRV_VIDEO_FORMAT_RGB888 ) {
dkato	0:853f5b7408a7	986	res_md = VDC5_RES_MD_RGB888;
dkato	0:853f5b7408a7	987	} else if( video_format == DRV_VIDEO_FORMAT_RGB565 ) {
dkato	0:853f5b7408a7	988	res_md = VDC5_RES_MD_RGB565;
dkato	0:853f5b7408a7	989	} else {
dkato	0:853f5b7408a7	990	drv_error = DRV_GRAPHICS_FORMAT_ERR;
dkato	0:853f5b7408a7	991	}
dkato	0:853f5b7408a7	992	}
dkato	0:853f5b7408a7	993
dkato	0:853f5b7408a7	994	if( col_sys == DRV_COL_SYS_NTSC_358 \|\| col_sys == DVV_COL_SYS_NTSC_443 \|\| col_sys == DRV_COL_SYS_NTSC_443_60 ) {
dkato	0:853f5b7408a7	995	video_in_rect.hs = IMGCAP_SIZE_NTSC_HS * 2;
dkato	0:853f5b7408a7	996	video_in_rect.hw = IMGCAP_SIZE_NTSC_HW * 2;
dkato	0:853f5b7408a7	997	video_in_rect.vs = IMGCAP_SIZE_NTSC_VS;
dkato	0:853f5b7408a7	998	video_in_rect.vw = IMGCAP_SIZE_NTSC_VW;
dkato	0:853f5b7408a7	999	} else {
dkato	0:853f5b7408a7	1000	video_in_rect.hs = IMGCAP_SIZE_PAL_HS * 2;
dkato	0:853f5b7408a7	1001	video_in_rect.hw = IMGCAP_SIZE_PAL_HW * 2;
dkato	0:853f5b7408a7	1002	video_in_rect.vs = IMGCAP_SIZE_PAL_VS;
dkato	0:853f5b7408a7	1003	video_in_rect.vw = IMGCAP_SIZE_PAL_VW;
dkato	0:853f5b7408a7	1004	}
dkato	0:853f5b7408a7	1005
dkato	0:853f5b7408a7	1006	if( drv_error == DRV_GRAPHICS_OK ) {
dkato	0:853f5b7408a7	1007	if( col_sys == DRV_COL_SYS_NTSC_358 \|\| col_sys == DVV_COL_SYS_NTSC_443 \|\| col_sys == DRV_COL_SYS_NTSC_443_60 ) {
dkato	0:853f5b7408a7	1008	if( (video_write_buff_vw / 2u) > video_in_rect.vw ) {
dkato	0:853f5b7408a7	1009	drv_error = DRV_GRAPHICS_VIDEO_NTSC_SIZE_ERR;
dkato	0:853f5b7408a7	1010	}
dkato	0:853f5b7408a7	1011	} else {
dkato	0:853f5b7408a7	1012	if( (video_write_buff_vw / 2u) > video_in_rect.vw ) {
dkato	0:853f5b7408a7	1013	drv_error = DRV_GRAPHICS_VIDEO_PAL_SIZE_ERR;
dkato	0:853f5b7408a7	1014	}
dkato	0:853f5b7408a7	1015	}
dkato	0:853f5b7408a7	1016	}
dkato	0:853f5b7408a7	1017
dkato	0:853f5b7408a7	1018	if( drv_error == DRV_GRAPHICS_OK ) {
dkato	0:853f5b7408a7	1019	if( video_write_buff_hw > 800 ) {
dkato	0:853f5b7408a7	1020	drv_error = DRV_GRAPHICS_PARAM_RANGE_ERR;
dkato	0:853f5b7408a7	1021	}
dkato	0:853f5b7408a7	1022	}
dkato	0:853f5b7408a7	1023
dkato	0:853f5b7408a7	1024	if( drv_error == DRV_GRAPHICS_OK ) {
dkato	0:853f5b7408a7	1025	/* Scaling-down and rotation parameter */
dkato	0:853f5b7408a7	1026	scldw_rot = &write.scalingdown_rot;
dkato	0:853f5b7408a7	1027	/* Image area to be captured */
dkato	0:853f5b7408a7	1028	scldw_rot->res.vs = (uint16_t)((uint32_t)video_in_rect.vs - 1u);
dkato	0:853f5b7408a7	1029	scldw_rot->res.vw = video_in_rect.vw;
dkato	0:853f5b7408a7	1030	scldw_rot->res.hs = video_in_rect.hs;
dkato	0:853f5b7408a7	1031	scldw_rot->res.hw = video_in_rect.hw;
dkato	0:853f5b7408a7	1032
dkato	0:853f5b7408a7	1033	/* Write data parameter */
dkato	0:853f5b7408a7	1034	framebuffer_t = framebuff;
dkato	0:853f5b7408a7	1035	framebuffer_b = &framebuffer_t[fb_stride];
dkato	0:853f5b7408a7	1036	scldw_rot->res_pfil_sel = VDC5_ON; /* Prefilter mode select for brightness signals (on/off) */
dkato	0:853f5b7408a7	1037	scldw_rot->res_out_vw = video_write_buff_vw / 2u; /* Number of valid lines in vertical direction
dkato	0:853f5b7408a7	1038	output by scaling-down control block */
dkato	0:853f5b7408a7	1039	scldw_rot->res_out_hw = video_write_buff_hw; /* Number of valid horizontal pixels
dkato	0:853f5b7408a7	1040	output by scaling-down control block */
dkato	0:853f5b7408a7	1041	scldw_rot->adj_sel = VDC5_ON; /* Measures to decrease the influence
dkato	0:853f5b7408a7	1042	by lack of last-input line (on/off) */
dkato	0:853f5b7408a7	1043	scldw_rot->res_ds_wr_md = VDC5_WR_MD_NORMAL; /* Frame buffer writing mode */
dkato	0:853f5b7408a7	1044	write.res_wrswa = (vdc5_wr_rd_swa_t)wr_rd_swa; /* Frame buffer swap setting */
dkato	0:853f5b7408a7	1045	write.res_md = res_md; /* Frame buffer video-signal writing format */
dkato	0:853f5b7408a7	1046	write.res_bst_md = VDC5_BST_MD_32BYTE; /* Transfer burst length for frame buffer */
dkato	0:853f5b7408a7	1047	write.res_inter = VDC5_RES_INTER_PROGRESSIVE; /* Field operating mode select */
dkato	0:853f5b7408a7	1048	write.res_fs_rate = VDC5_RES_FS_RATE_PER1; /* Writing rate */
dkato	0:853f5b7408a7	1049	write.res_fld_sel = VDC5_RES_FLD_SEL_TOP; /* Write field select */
dkato	0:853f5b7408a7	1050	write.res_dth_on = VDC5_ON; /* Dither correction on/off */
dkato	0:853f5b7408a7	1051	write.base = framebuff; /* Frame buffer base address */
dkato	0:853f5b7408a7	1052	write.ln_off = fb_stride * 2u; /* Frame buffer line offset address [byte] */
dkato	0:853f5b7408a7	1053	write.flm_num = (uint32_t)(1u - 1u); /* Number of frames of buffer (res_flm_num + 1) */
dkato	0:853f5b7408a7	1054	/* Frame buffer frame offset address */
dkato	0:853f5b7408a7	1055	write.flm_off = fb_stride * 2u * (uint32_t)scldw_rot->res_out_vw;
dkato	0:853f5b7408a7	1056	write.btm_base = framebuffer_b; /* Frame buffer base address for bottom */
dkato	0:853f5b7408a7	1057
dkato	0:853f5b7408a7	1058	/* Write data control */
dkato	0:853f5b7408a7	1059	error = R_VDC5_WriteDataControl( ch, vdc5_layer_id, &write );
dkato	0:853f5b7408a7	1060	if (error != VDC5_OK) {
dkato	0:853f5b7408a7	1061	drv_error = DRV_GRAPHICS_VDC5_ERR;
dkato	0:853f5b7408a7	1062	}
dkato	0:853f5b7408a7	1063	}
dkato	0:853f5b7408a7	1064	return drv_error;
dkato	0:853f5b7408a7	1065	} /* End of function DRV_Video_Write_Setting() */
dkato	0:853f5b7408a7	1066
dkato	0:853f5b7408a7	1067	/************************************************************************//
dkato	0:853f5b7408a7	1068	* @brief Video surface write process setting for digital input
dkato	0:853f5b7408a7	1069	*
dkato	0:853f5b7408a7	1070	* Description:<br>
dkato	0:853f5b7408a7	1071	* This function set the video write process for digital input.
dkato	0:853f5b7408a7	1072	* This function supports the following 3 image format.
dkato	0:853f5b7408a7	1073	* YCbCr422, RGB565, RGB888
dkato	0:853f5b7408a7	1074	* @param[in] framebuff : Base address of the frame buffer
dkato	0:853f5b7408a7	1075	* @param[in] fb_stride [byte] : Line offset address of the frame buffer
dkato	0:853f5b7408a7	1076	* @param[in] video_format : Frame buffer video-signal writing format
dkato	0:853f5b7408a7	1077	* @param[in] wr_rd_swa : Frame buffer swap setting
dkato	0:853f5b7408a7	1078	* @param[in] video_write_size_vw [px]: output height
dkato	0:853f5b7408a7	1079	* @param[in] video_write_size_hw [px]: output width
dkato	0:853f5b7408a7	1080	* @param[in] cap_area : Capture area
dkato	0:853f5b7408a7	1081	* @retval Error code
dkato	0:853f5b7408a7	1082	******************************************************************************/
dkato	0:853f5b7408a7	1083	drv_graphics_error_t DRV_Video_Write_Setting_Digital (
dkato	0:853f5b7408a7	1084	void * framebuff,
dkato	0:853f5b7408a7	1085	uint32_t fb_stride,
dkato	0:853f5b7408a7	1086	drv_video_format_t video_format,
dkato	0:853f5b7408a7	1087	drv_wr_rd_swa_t wr_rd_swa,
dkato	0:853f5b7408a7	1088	uint16_t video_write_buff_vw,
dkato	0:853f5b7408a7	1089	uint16_t video_write_buff_hw,
dkato	0:853f5b7408a7	1090	drv_rect_t * cap_area )
dkato	0:853f5b7408a7	1091	{
dkato	0:853f5b7408a7	1092	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
dkato	0:853f5b7408a7	1093	vdc5_channel_t ch = VDC5_CHANNEL_0;
dkato	0:853f5b7408a7	1094	vdc5_error_t error;
dkato	0:853f5b7408a7	1095	vdc5_layer_id_t vdc5_layer_id;
dkato	0:853f5b7408a7	1096	vdc5_write_t write;
dkato	0:853f5b7408a7	1097	vdc5_scalingdown_rot_t * scldw_rot;
dkato	0:853f5b7408a7	1098	vdc5_res_md_t res_md;
dkato	0:853f5b7408a7	1099
dkato	0:853f5b7408a7	1100	vdc5_layer_id = VDC5_LAYER_ID_0_WR;
dkato	0:853f5b7408a7	1101
dkato	0:853f5b7408a7	1102	if( drv_error == DRV_GRAPHICS_OK ) {
dkato	0:853f5b7408a7	1103	if( video_format == DRV_VIDEO_FORMAT_YCBCR422 ) {
dkato	0:853f5b7408a7	1104	res_md = VDC5_RES_MD_YCBCR422;
dkato	0:853f5b7408a7	1105	} else if( video_format == DRV_VIDEO_FORMAT_RGB888 ) {
dkato	0:853f5b7408a7	1106	res_md = VDC5_RES_MD_RGB888;
dkato	0:853f5b7408a7	1107	} else if( video_format == DRV_VIDEO_FORMAT_RGB565 ) {
dkato	0:853f5b7408a7	1108	res_md = VDC5_RES_MD_RGB565;
dkato	0:853f5b7408a7	1109	} else {
dkato	0:853f5b7408a7	1110	drv_error = DRV_GRAPHICS_FORMAT_ERR;
dkato	0:853f5b7408a7	1111	}
dkato	0:853f5b7408a7	1112	}
dkato	0:853f5b7408a7	1113
dkato	0:853f5b7408a7	1114	if( drv_error == DRV_GRAPHICS_OK ) {
dkato	0:853f5b7408a7	1115	/* Scaling-down and rotation parameter */
dkato	0:853f5b7408a7	1116	scldw_rot = &write.scalingdown_rot;
dkato	0:853f5b7408a7	1117	/* Image area to be captured */
dkato	0:853f5b7408a7	1118	scldw_rot->res.vs = (uint16_t)((uint32_t)cap_area->vs - 1u);
dkato	0:853f5b7408a7	1119	scldw_rot->res.vw = cap_area->vw;
dkato	0:853f5b7408a7	1120	scldw_rot->res.hs = cap_area->hs;
dkato	0:853f5b7408a7	1121	scldw_rot->res.hw = cap_area->hw;
dkato	0:853f5b7408a7	1122
dkato	0:853f5b7408a7	1123	/* Write data parameter */
dkato	0:853f5b7408a7	1124	scldw_rot->res_pfil_sel = VDC5_ON; /* Prefilter mode select for brightness signals (on/off) */
dkato	0:853f5b7408a7	1125	scldw_rot->res_out_vw = video_write_buff_vw ; /* Number of valid lines in vertical direction
dkato	0:853f5b7408a7	1126	output by scaling-down control block */
dkato	0:853f5b7408a7	1127	scldw_rot->res_out_hw = video_write_buff_hw; /* Number of valid horizontal pixels
dkato	0:853f5b7408a7	1128	output by scaling-down control block */
dkato	0:853f5b7408a7	1129	scldw_rot->adj_sel = VDC5_ON; /* Measures to decrease the influence
dkato	0:853f5b7408a7	1130	by lack of last-input line (on/off) */
dkato	0:853f5b7408a7	1131	scldw_rot->res_ds_wr_md = VDC5_WR_MD_NORMAL; /* Frame buffer writing mode */
dkato	0:853f5b7408a7	1132	write.res_wrswa = (vdc5_wr_rd_swa_t)wr_rd_swa; /* Frame buffer swap setting */
dkato	0:853f5b7408a7	1133	write.res_md = res_md; /* Frame buffer video-signal writing format */
dkato	0:853f5b7408a7	1134	write.res_bst_md = VDC5_BST_MD_32BYTE; /* Transfer burst length for frame buffer */
dkato	0:853f5b7408a7	1135	write.res_inter = VDC5_RES_INTER_PROGRESSIVE; /* Field operating mode select */
dkato	0:853f5b7408a7	1136	write.res_fs_rate = VDC5_RES_FS_RATE_PER1; /* Writing rate */
dkato	0:853f5b7408a7	1137	write.res_fld_sel = VDC5_RES_FLD_SEL_TOP; /* Write field select */
dkato	0:853f5b7408a7	1138	write.res_dth_on = VDC5_ON; /* Dither correction on/off */
dkato	0:853f5b7408a7	1139	write.base = framebuff; /* Frame buffer base address */
dkato	0:853f5b7408a7	1140	write.ln_off = fb_stride;
dkato	0:853f5b7408a7	1141	/* Frame buffer line offset address [byte] */
dkato	0:853f5b7408a7	1142	write.flm_num = (uint32_t)(1u - 1u); /* Number of frames of buffer (res_flm_num + 1) */
dkato	0:853f5b7408a7	1143	/* Frame buffer frame offset address */
dkato	0:853f5b7408a7	1144	write.flm_off = fb_stride * (uint32_t)scldw_rot->res_out_vw;
dkato	0:853f5b7408a7	1145	write.btm_base = NULL; /* Frame buffer base address for bottom */
dkato	0:853f5b7408a7	1146
dkato	0:853f5b7408a7	1147	/* Write data control */
dkato	0:853f5b7408a7	1148	error = R_VDC5_WriteDataControl( ch, vdc5_layer_id, &write );
dkato	0:853f5b7408a7	1149	if (error != VDC5_OK) {
dkato	0:853f5b7408a7	1150	drv_error = DRV_GRAPHICS_VDC5_ERR;
dkato	0:853f5b7408a7	1151	}
dkato	0:853f5b7408a7	1152	}
dkato	0:853f5b7408a7	1153	return drv_error;
dkato	0:853f5b7408a7	1154	} /* End of function DRV_Video_Write_Setting_Digital() */
dkato	0:853f5b7408a7	1155
dkato	0:853f5b7408a7	1156	/************************************************************************//
dkato	0:853f5b7408a7	1157	* @brief Video surface write buffer change process
dkato	0:853f5b7408a7	1158	* @param[in] video_input_ch : Video input channle
dkato	0:853f5b7408a7	1159	* @param[in] framebuff : Base address of the frame buffer
dkato	0:853f5b7408a7	1160	* @param[in] fb_stride : Line offset address of the frame buffer
dkato	0:853f5b7408a7	1161	* @retval Error code
dkato	0:853f5b7408a7	1162	******************************************************************************/
dkato	0:853f5b7408a7	1163	drv_graphics_error_t DRV_Video_Write_Change (
dkato	0:853f5b7408a7	1164	drv_video_input_channel_t video_input_ch,
dkato	0:853f5b7408a7	1165	void * framebuff,
dkato	0:853f5b7408a7	1166	uint32_t fb_stride )
dkato	0:853f5b7408a7	1167	{
dkato	0:853f5b7408a7	1168	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
dkato	0:853f5b7408a7	1169	uint8_t * framebuffer_t;
dkato	0:853f5b7408a7	1170	uint8_t * framebuffer_b;
dkato	0:853f5b7408a7	1171
dkato	0:853f5b7408a7	1172	framebuffer_t = (uint8_t *)((uint32_t)framebuff & ~0x1F);
dkato	0:853f5b7408a7	1173	framebuffer_b = &framebuffer_t[fb_stride];
dkato	0:853f5b7408a7	1174
dkato	0:853f5b7408a7	1175	if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) {
dkato	0:853f5b7408a7	1176	VDC50.SC0_SCL1_WR2 = (uint32_t)framebuffer_t;
dkato	0:853f5b7408a7	1177	VDC50.SC0_SCL1_WR8 = (uint32_t)framebuffer_b;
dkato	0:853f5b7408a7	1178	VDC50.SC0_SCL1_UPDATE = 0x10;
dkato	0:853f5b7408a7	1179	} else if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1 ) {
dkato	0:853f5b7408a7	1180	VDC50.SC1_SCL1_WR2 = (uint32_t)framebuffer_t;
dkato	0:853f5b7408a7	1181	VDC50.SC1_SCL1_WR8 = (uint32_t)framebuffer_b;
dkato	0:853f5b7408a7	1182	VDC50.SC1_SCL1_UPDATE = 0x10;
dkato	0:853f5b7408a7	1183	} else {
dkato	0:853f5b7408a7	1184	drv_error = DRV_GRAPHICS_CHANNEL_ERR;
dkato	0:853f5b7408a7	1185	}
dkato	0:853f5b7408a7	1186	return drv_error;
dkato	0:853f5b7408a7	1187	} /* End of function DRV_Video_Write_Change() */
dkato	0:853f5b7408a7	1188
dkato	0:853f5b7408a7	1189	/* End of file */

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Type:	Library
Created:	26 Jun 2015
Imports:	137
Forks:	1
Commits:	5
Dependents:	44
Dependencies:	0
Followers:	63

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Import programGR-PEACH_Camera_in

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Import libraryGR-PEACH_video - DisplayBase Class Reference

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gr_peach_vdc5.c@4:aeefe5171463, 2016-06-30 (annotated)

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Import program GR-PEACH_Camera_in

Import library
GR-PEACH_video - DisplayBase Class Reference