Renesas / GR-PEACH_video

Video library for GR-PEACH

Dependents:   Trace_Program2 GR-PEACH_Camera_in_barcode GR-PEACH_LCD_sample GR-PEACH_LCD_4_3inch_sample ... more

Video ｌibrary for GR-PEACH.

Hello World!

Import programGR-PEACH_Camera_in

Camera in sample for GR-PEACH. This sample works on GR-LYCHEE besides GR-PEACH.

Last commit 28 Dec 2018 by Renesas

API

Import library
GR-PEACH_video - DisplayBase Class Reference

Data Structures

struct lcd_config_t
LCD configuration. More...
struct rect_t
The relative position within the graphics display area. More...
struct video_ext_in_config_t
Digital Video Input configuration. More...

Public Types

enum video_input_channel_t { VIDEO_INPUT_CHANNEL_0 = 0, VIDEO_INPUT_CHANNEL_1 }

Video input channel select.

More...
enum graphics_layer_t { GRAPHICS_LAYER_0 = 0, GRAPHICS_LAYER_1 , GRAPHICS_LAYER_2 , GRAPHICS_LAYER_3 }

Graphics layer select.

More...
enum graphics_error_t {
GRAPHICS_OK = 0, GRAPHICS_VDC5_ERR = -1, GRAPHICS_FORMA_ERR = -2, GRAPHICS_LAYER_ERR = -3,
GRAPHICS_CHANNLE_ERR = -4, GRAPHICS_VIDEO_NTSC_SIZE_ERR = -5, GRAPHICS_VIDEO_PAL_SIZE_ERR = -6, GRAPHICS_PARAM_RANGE_ERR = -7
}

Error codes.

More...
enum graphics_format_t { GRAPHICS_FORMAT_YCBCR422 = 0, GRAPHICS_FORMAT_RGB565 , GRAPHICS_FORMAT_RGB888 , GRAPHICS_FORMAT_ARGB8888 }

Graphics layer read format selects.

More...
enum video_format_t { VIDEO_FORMAT_YCBCR422 = 0, VIDEO_FORMAT_RGB565 , VIDEO_FORMAT_RGB888 }

Video writing format selects.

More...
enum wr_rd_swa_t {
WR_RD_WRSWA_NON = 0, WR_RD_WRSWA_8BIT , WR_RD_WRSWA_16BIT , WR_RD_WRSWA_16_8BIT ,
WR_RD_WRSWA_32BIT , WR_RD_WRSWA_32_8BIT , WR_RD_WRSWA_32_16BIT , WR_RD_WRSWA_32_16_8BIT
}

Frame buffer swap setting.

More...
enum lcd_tcon_pin_t { LCD_TCON_PIN_NON = -1, LCD_TCON_PIN_0 , LCD_TCON_PIN_1 , LCD_TCON_PIN_2 }

LCD tcon output pin selects.

More...
enum lcd_outformat_t { LCD_OUTFORMAT_RGB888 = 0, LCD_OUTFORMAT_RGB666 , LCD_OUTFORMAT_RGB565 }

LCD output format selects.

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enum edge_t { EDGE_RISING = 0, EDGE_FALLING = 1 }

Edge of a signal.

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enum lcd_type_t { LCD_TYPE_LVDS = 0, LCD_TYPE_PARALLEL_RGB }

LCD type.

More...
enum sig_pol_t { SIG_POL_NOT_INVERTED = 0, SIG_POL_INVERTED }

Polarity of a signal.

More...
enum int_type_t {
INT_TYPE_S0_VI_VSYNC = 0, INT_TYPE_S0_LO_VSYNC , INT_TYPE_S0_VSYNCERR , INT_TYPE_VLINE ,
INT_TYPE_S0_VFIELD , INT_TYPE_IV1_VBUFERR , INT_TYPE_IV3_VBUFERR , INT_TYPE_IV5_VBUFERR ,
INT_TYPE_IV6_VBUFERR , INT_TYPE_S0_WLINE , INT_TYPE_S1_VI_VSYNC , INT_TYPE_S1_LO_VSYNC ,
INT_TYPE_S1_VSYNCERR , INT_TYPE_S1_VFIELD , INT_TYPE_IV2_VBUFERR , INT_TYPE_IV4_VBUFERR ,
INT_TYPE_S1_WLINE , INT_TYPE_OIR_VI_VSYNC , INT_TYPE_OIR_LO_VSYNC , INT_TYPE_OIR_VLINE ,
INT_TYPE_OIR_VFIELD , INT_TYPE_IV7_VBUFERR , INT_TYPE_IV8_VBUFERR , INT_TYPE_NUM
}

Interrupt type.

More...
enum graphics_video_col_sys_t {
COL_SYS_NTSC_358 = 0, COL_SYS_NTSC_443 = 1, COL_SYS_PAL_443 = 2, COL_SYS_PAL_M = 3,
COL_SYS_PAL_N = 4, COL_SYS_SECAM = 5, COL_SYS_NTSC_443_60 = 6, COL_SYS_PAL_60 = 7
}

Video color system.

More...
enum video_input_sel_t { INPUT_SEL_VDEC = 0, INPUT_SEL_EXT = 1 }

External Input select.

More...
enum video_extin_format_t {
VIDEO_EXTIN_FORMAT_RGB888 = 0, VIDEO_EXTIN_FORMAT_RGB666 , VIDEO_EXTIN_FORMAT_RGB565 , VIDEO_EXTIN_FORMAT_BT656 ,
VIDEO_EXTIN_FORMAT_BT601 , VIDEO_EXTIN_FORMAT_YCBCR422 , VIDEO_EXTIN_FORMAT_YCBCR444
}

External input format select.

More...
enum onoff_t { OFF = 0, ON = 1 }

On/off.

More...
enum extin_input_line_t { EXTIN_LINE_525 = 0, EXTIN_LINE_625 = 1 }

Number of lines for BT.656 external input.

More...
enum extin_h_pos_t { EXTIN_H_POS_CBYCRY = 0, EXTIN_H_POS_YCRYCB , EXTIN_H_POS_CRYCBY , EXTIN_H_POS_YCBYCR }

Y/Cb/Y/Cr data string start timing.

More...

Public Member Functions

DisplayBase (void)
Constructor method of display base object.
graphics_error_t Graphics_init ( lcd_config_t *lcd_config)
Graphics initialization processing
If not using display, set NULL in parameter.
graphics_error_t Graphics_Video_init ( video_input_sel_t video_input_sel, video_ext_in_config_t *video_ext_in_config)
Graphics Video initialization processing
If setting INPUT_SEL_VDEC in video_input_sel parameter, set NULL in video_ext_in_config parameter.
graphics_error_t Graphics_Lcd_Port_Init (PinName *pin, unsigned int pin_count)
LCD output port initialization processing.
graphics_error_t Graphics_Lvds_Port_Init (PinName *pin, unsigned int pin_count)
LVDS output port initialization processing.
graphics_error_t Graphics_Dvinput_Port_Init (PinName *pin, unsigned int pin_count)
Digital video input port initialization processing.
graphics_error_t Graphics_Irq_Handler_Set ( int_type_t Graphics_Irq_Handler_Set, unsigned short num, void(*callback)( int_type_t ))
Interrupt callback setup This function performs the following processing:

  • Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.

graphics_error_t Graphics_Start ( graphics_layer_t layer_id)
Start the graphics surface read process.
graphics_error_t Graphics_Stop ( graphics_layer_t layer_id)
Stop the graphics surface read process.
graphics_error_t Video_Start ( video_input_channel_t video_input_channel)
Start the video surface write process.
graphics_error_t Video_Stop ( video_input_channel_t video_input_channel)
Stop the video surface write process.
graphics_error_t Graphics_Read_Setting ( graphics_layer_t layer_id, void *framebuff, unsigned int fb_stride, graphics_format_t gr_format, wr_rd_swa_t wr_rd_swa, rect_t *gr_rect)
Graphics surface read process setting.
graphics_error_t Graphics_Read_Change ( graphics_layer_t layer_id, void *framebuff)
Graphics surface read buffer change process.
graphics_error_t Video_Write_Setting ( video_input_channel_t video_input_channel, graphics_video_col_sys_t col_sys, void *framebuff, unsigned int fb_stride, video_format_t video_format, wr_rd_swa_t wr_rd_swa, unsigned short video_write_buff_vw, unsigned short video_write_buff_hw)
Video surface write process setting.
graphics_error_t Video_Write_Change ( video_input_channel_t video_input_channel, void *framebuff, uint32_t fb_stride)
Video surface write buffer change process.

Interface

See the Pinout page for more details

drivers/vdc5/src/r_vdc5_register.h@4:aeefe5171463, 2016-06-30 (annotated)

Committer:
dkato
Date:
Thu Jun 30 11:00:37 2016 +0000
Revision:
4:aeefe5171463
Parent:
0:853f5b7408a7 
Add ARGB4444 to graphics layer read format.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:853f5b7408a7 1 /*******************************************************************************
dkato 0:853f5b7408a7 2 * DISCLAIMER
dkato 0:853f5b7408a7 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:853f5b7408a7 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:853f5b7408a7 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:853f5b7408a7 6 * all applicable laws, including copyright laws.
dkato 0:853f5b7408a7 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:853f5b7408a7 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:853f5b7408a7 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:853f5b7408a7 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:853f5b7408a7 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:853f5b7408a7 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:853f5b7408a7 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:853f5b7408a7 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:853f5b7408a7 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:853f5b7408a7 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:853f5b7408a7 17 * and to discontinue the availability of this software. By using this software,
dkato 0:853f5b7408a7 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:853f5b7408a7 19 * following link:
dkato 0:853f5b7408a7 20 * http://www.renesas.com/disclaimer
dkato 0:853f5b7408a7 21 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
dkato 0:853f5b7408a7 22 *******************************************************************************/
dkato 0:853f5b7408a7 23 /**************************************************************************//**
dkato 0:853f5b7408a7 24 * @file r_vdc5_register.h
dkato 0:853f5b7408a7 25 * @version 1.00
dkato 0:853f5b7408a7 26 * $Rev: 199 $
dkato 0:853f5b7408a7 27 * $Date:: 2014-05-23 16:33:52 +0900#$
dkato 0:853f5b7408a7 28 * @brief VDC5 driver register setup definitions
dkato 0:853f5b7408a7 29 ******************************************************************************/
dkato 0:853f5b7408a7 30
dkato 0:853f5b7408a7 31 #ifndef R_VDC5_REGISTER_H
dkato 0:853f5b7408a7 32 #define R_VDC5_REGISTER_H
dkato 0:853f5b7408a7 33
dkato 0:853f5b7408a7 34 /******************************************************************************
dkato 0:853f5b7408a7 35 Includes <System Includes> , "Project Includes"
dkato 0:853f5b7408a7 36 ******************************************************************************/
dkato 0:853f5b7408a7 37 #include "r_vdc5.h"
dkato 0:853f5b7408a7 38 #include "r_vdc5_user.h"
dkato 0:853f5b7408a7 39
dkato 0:853f5b7408a7 40
dkato 0:853f5b7408a7 41 /******************************************************************************
dkato 0:853f5b7408a7 42 Macro definitions
dkato 0:853f5b7408a7 43 ******************************************************************************/
dkato 0:853f5b7408a7 44 #define VDC5_GAM_LUT_REG_NUM (16u) /*!< The number of table setting register in gamma correction block */
dkato 0:853f5b7408a7 45 #define VDC5_GAM_AREA_REG_NUM (8u) /*!< The number of area setting register in gamma correction block */
dkato 0:853f5b7408a7 46
dkato 0:853f5b7408a7 47
dkato 0:853f5b7408a7 48 /******************************************************************************
dkato 0:853f5b7408a7 49 Typedef definitions
dkato 0:853f5b7408a7 50 ******************************************************************************/
dkato 0:853f5b7408a7 51 /*! VDC5 input controller register address list */
dkato 0:853f5b7408a7 52 typedef struct {
dkato 0:853f5b7408a7 53 volatile uint32_t * inp_update;
dkato 0:853f5b7408a7 54 volatile uint32_t * inp_sel_cnt;
dkato 0:853f5b7408a7 55 volatile uint32_t * inp_ext_sync_cnt;
dkato 0:853f5b7408a7 56 volatile uint32_t * inp_vsync_ph_adj;
dkato 0:853f5b7408a7 57 volatile uint32_t * inp_dly_adj;
dkato 0:853f5b7408a7 58 volatile uint32_t * imgcnt_update;
dkato 0:853f5b7408a7 59 volatile uint32_t * imgcnt_nr_cnt0;
dkato 0:853f5b7408a7 60 volatile uint32_t * imgcnt_nr_cnt1;
dkato 0:853f5b7408a7 61 } vdc5_regaddr_input_ctrl_t;
dkato 0:853f5b7408a7 62
dkato 0:853f5b7408a7 63 /*! VDC5 scaler register address list */
dkato 0:853f5b7408a7 64 typedef struct {
dkato 0:853f5b7408a7 65 volatile uint32_t * scl0_update;
dkato 0:853f5b7408a7 66 volatile uint32_t * scl0_frc1;
dkato 0:853f5b7408a7 67 volatile uint32_t * scl0_frc2;
dkato 0:853f5b7408a7 68 volatile uint32_t * scl0_frc3;
dkato 0:853f5b7408a7 69 volatile uint32_t * scl0_frc4;
dkato 0:853f5b7408a7 70 volatile uint32_t * scl0_frc5;
dkato 0:853f5b7408a7 71 volatile uint32_t * scl0_frc6;
dkato 0:853f5b7408a7 72 volatile uint32_t * scl0_frc7;
dkato 0:853f5b7408a7 73 volatile uint32_t * scl0_frc9;
dkato 0:853f5b7408a7 74 volatile uint16_t * scl0_mon0;
dkato 0:853f5b7408a7 75 volatile uint16_t * scl0_int;
dkato 0:853f5b7408a7 76 volatile uint32_t * scl0_ds1;
dkato 0:853f5b7408a7 77 volatile uint32_t * scl0_ds2;
dkato 0:853f5b7408a7 78 volatile uint32_t * scl0_ds3;
dkato 0:853f5b7408a7 79 volatile uint32_t * scl0_ds4;
dkato 0:853f5b7408a7 80 volatile uint32_t * scl0_ds5;
dkato 0:853f5b7408a7 81 volatile uint32_t * scl0_ds6;
dkato 0:853f5b7408a7 82 volatile uint32_t * scl0_ds7;
dkato 0:853f5b7408a7 83 volatile uint32_t * scl0_us1;
dkato 0:853f5b7408a7 84 volatile uint32_t * scl0_us2;
dkato 0:853f5b7408a7 85 volatile uint32_t * scl0_us3;
dkato 0:853f5b7408a7 86 volatile uint32_t * scl0_us4;
dkato 0:853f5b7408a7 87 volatile uint32_t * scl0_us5;
dkato 0:853f5b7408a7 88 volatile uint32_t * scl0_us6;
dkato 0:853f5b7408a7 89 volatile uint32_t * scl0_us7;
dkato 0:853f5b7408a7 90 volatile uint32_t * scl0_us8;
dkato 0:853f5b7408a7 91 volatile uint32_t * scl0_ovr1;
dkato 0:853f5b7408a7 92 volatile uint32_t * scl1_update;
dkato 0:853f5b7408a7 93 volatile uint32_t * scl1_wr1;
dkato 0:853f5b7408a7 94 volatile uint32_t * scl1_wr2;
dkato 0:853f5b7408a7 95 volatile uint32_t * scl1_wr3;
dkato 0:853f5b7408a7 96 volatile uint32_t * scl1_wr4;
dkato 0:853f5b7408a7 97 volatile uint32_t * scl1_wr5;
dkato 0:853f5b7408a7 98 volatile uint32_t * scl1_wr6;
dkato 0:853f5b7408a7 99 volatile uint32_t * scl1_wr7;
dkato 0:853f5b7408a7 100 volatile uint32_t * scl1_wr8;
dkato 0:853f5b7408a7 101 volatile uint32_t * scl1_wr9;
dkato 0:853f5b7408a7 102 volatile uint32_t * scl1_wr10;
dkato 0:853f5b7408a7 103 volatile uint32_t * scl1_wr11;
dkato 0:853f5b7408a7 104 volatile uint32_t * scl1_mon1;
dkato 0:853f5b7408a7 105 volatile uint32_t * scl1_pbuf0;
dkato 0:853f5b7408a7 106 volatile uint32_t * scl1_pbuf1;
dkato 0:853f5b7408a7 107 volatile uint32_t * scl1_pbuf2;
dkato 0:853f5b7408a7 108 volatile uint32_t * scl1_pbuf3;
dkato 0:853f5b7408a7 109 volatile uint32_t * scl1_pbuf_fld;
dkato 0:853f5b7408a7 110 volatile uint32_t * scl1_pbuf_cnt;
dkato 0:853f5b7408a7 111 } vdc5_regaddr_scaler_t;
dkato 0:853f5b7408a7 112
dkato 0:853f5b7408a7 113 /*! VDC5 image quality improver register address list */
dkato 0:853f5b7408a7 114 typedef struct {
dkato 0:853f5b7408a7 115 volatile uint32_t * adj_update;
dkato 0:853f5b7408a7 116 volatile uint32_t * adj_bkstr_set;
dkato 0:853f5b7408a7 117 volatile uint32_t * adj_enh_tim1;
dkato 0:853f5b7408a7 118 volatile uint32_t * adj_enh_tim2;
dkato 0:853f5b7408a7 119 volatile uint32_t * adj_enh_tim3;
dkato 0:853f5b7408a7 120 volatile uint32_t * adj_enh_shp1;
dkato 0:853f5b7408a7 121 volatile uint32_t * adj_enh_shp2;
dkato 0:853f5b7408a7 122 volatile uint32_t * adj_enh_shp3;
dkato 0:853f5b7408a7 123 volatile uint32_t * adj_enh_shp4;
dkato 0:853f5b7408a7 124 volatile uint32_t * adj_enh_shp5;
dkato 0:853f5b7408a7 125 volatile uint32_t * adj_enh_shp6;
dkato 0:853f5b7408a7 126 volatile uint32_t * adj_enh_lti1;
dkato 0:853f5b7408a7 127 volatile uint32_t * adj_enh_lti2;
dkato 0:853f5b7408a7 128 } vdc5_regaddr_img_qlty_imp_t;
dkato 0:853f5b7408a7 129
dkato 0:853f5b7408a7 130 /*! VDC5 color matrix register address list */
dkato 0:853f5b7408a7 131 typedef struct {
dkato 0:853f5b7408a7 132 volatile uint32_t * mtx_update;
dkato 0:853f5b7408a7 133 volatile uint32_t * mtx_mode;
dkato 0:853f5b7408a7 134 volatile uint32_t * mtx_yg_adj0;
dkato 0:853f5b7408a7 135 volatile uint32_t * mtx_yg_adj1;
dkato 0:853f5b7408a7 136 volatile uint32_t * mtx_cbb_adj0;
dkato 0:853f5b7408a7 137 volatile uint32_t * mtx_cbb_adj1;
dkato 0:853f5b7408a7 138 volatile uint32_t * mtx_crr_adj0;
dkato 0:853f5b7408a7 139 volatile uint32_t * mtx_crr_adj1;
dkato 0:853f5b7408a7 140 } vdc5_regaddr_color_matrix_t;
dkato 0:853f5b7408a7 141
dkato 0:853f5b7408a7 142 /*! VDC5 image synthesizer register address list */
dkato 0:853f5b7408a7 143 typedef struct {
dkato 0:853f5b7408a7 144 volatile uint32_t * gr_update;
dkato 0:853f5b7408a7 145 volatile uint32_t * gr_flm_rd;
dkato 0:853f5b7408a7 146 volatile uint32_t * gr_flm1;
dkato 0:853f5b7408a7 147 volatile uint32_t * gr_flm2;
dkato 0:853f5b7408a7 148 volatile uint32_t * gr_flm3;
dkato 0:853f5b7408a7 149 volatile uint32_t * gr_flm4;
dkato 0:853f5b7408a7 150 volatile uint32_t * gr_flm5;
dkato 0:853f5b7408a7 151 volatile uint32_t * gr_flm6;
dkato 0:853f5b7408a7 152 volatile uint32_t * gr_ab1;
dkato 0:853f5b7408a7 153 volatile uint32_t * gr_ab2;
dkato 0:853f5b7408a7 154 volatile uint32_t * gr_ab3;
dkato 0:853f5b7408a7 155 volatile uint32_t * gr_ab4;
dkato 0:853f5b7408a7 156 volatile uint32_t * gr_ab5;
dkato 0:853f5b7408a7 157 volatile uint32_t * gr_ab6;
dkato 0:853f5b7408a7 158 volatile uint32_t * gr_ab7;
dkato 0:853f5b7408a7 159 volatile uint32_t * gr_ab8;
dkato 0:853f5b7408a7 160 volatile uint32_t * gr_ab9;
dkato 0:853f5b7408a7 161 volatile uint32_t * gr_ab10;
dkato 0:853f5b7408a7 162 volatile uint32_t * gr_ab11;
dkato 0:853f5b7408a7 163 volatile uint32_t * gr_base;
dkato 0:853f5b7408a7 164 volatile uint32_t * gr_clut;
dkato 0:853f5b7408a7 165 volatile uint32_t * gr_mon;
dkato 0:853f5b7408a7 166 } vdc5_regaddr_img_synthesizer_t;
dkato 0:853f5b7408a7 167
dkato 0:853f5b7408a7 168 /*! VDC5 gamma correction register address list */
dkato 0:853f5b7408a7 169 typedef struct {
dkato 0:853f5b7408a7 170 volatile uint32_t * gam_sw;
dkato 0:853f5b7408a7 171 volatile uint32_t * gam_g_update;
dkato 0:853f5b7408a7 172 volatile uint32_t * gam_g_lut[VDC5_GAM_LUT_REG_NUM];
dkato 0:853f5b7408a7 173 volatile uint32_t * gam_g_area[VDC5_GAM_AREA_REG_NUM];
dkato 0:853f5b7408a7 174 volatile uint32_t * gam_b_update;
dkato 0:853f5b7408a7 175 volatile uint32_t * gam_b_lut[VDC5_GAM_LUT_REG_NUM];
dkato 0:853f5b7408a7 176 volatile uint32_t * gam_b_area[VDC5_GAM_AREA_REG_NUM];
dkato 0:853f5b7408a7 177 volatile uint32_t * gam_r_update;
dkato 0:853f5b7408a7 178 volatile uint32_t * gam_r_lut[VDC5_GAM_LUT_REG_NUM];
dkato 0:853f5b7408a7 179 volatile uint32_t * gam_r_area[VDC5_GAM_AREA_REG_NUM];
dkato 0:853f5b7408a7 180 } vdc5_regaddr_gamma_t;
dkato 0:853f5b7408a7 181
dkato 0:853f5b7408a7 182 /*! VDC5 output controller register address list */
dkato 0:853f5b7408a7 183 typedef struct {
dkato 0:853f5b7408a7 184 volatile uint32_t * tcon_update;
dkato 0:853f5b7408a7 185 volatile uint32_t * tcon_tim;
dkato 0:853f5b7408a7 186 volatile uint32_t * tcon_tim_stva1;
dkato 0:853f5b7408a7 187 volatile uint32_t * tcon_tim_stva2;
dkato 0:853f5b7408a7 188 volatile uint32_t * tcon_tim_stvb1;
dkato 0:853f5b7408a7 189 volatile uint32_t * tcon_tim_stvb2;
dkato 0:853f5b7408a7 190 volatile uint32_t * tcon_tim_sth1;
dkato 0:853f5b7408a7 191 volatile uint32_t * tcon_tim_sth2;
dkato 0:853f5b7408a7 192 volatile uint32_t * tcon_tim_stb1;
dkato 0:853f5b7408a7 193 volatile uint32_t * tcon_tim_stb2;
dkato 0:853f5b7408a7 194 volatile uint32_t * tcon_tim_cpv1;
dkato 0:853f5b7408a7 195 volatile uint32_t * tcon_tim_cpv2;
dkato 0:853f5b7408a7 196 volatile uint32_t * tcon_tim_pola1;
dkato 0:853f5b7408a7 197 volatile uint32_t * tcon_tim_pola2;
dkato 0:853f5b7408a7 198 volatile uint32_t * tcon_tim_polb1;
dkato 0:853f5b7408a7 199 volatile uint32_t * tcon_tim_polb2;
dkato 0:853f5b7408a7 200 volatile uint32_t * tcon_tim_de;
dkato 0:853f5b7408a7 201 volatile uint32_t * out_update;
dkato 0:853f5b7408a7 202 volatile uint32_t * out_set;
dkato 0:853f5b7408a7 203 volatile uint32_t * out_bright1;
dkato 0:853f5b7408a7 204 volatile uint32_t * out_bright2;
dkato 0:853f5b7408a7 205 volatile uint32_t * out_contrast;
dkato 0:853f5b7408a7 206 volatile uint32_t * out_pdtha;
dkato 0:853f5b7408a7 207 volatile uint32_t * out_clk_phase;
dkato 0:853f5b7408a7 208 } vdc5_regaddr_output_ctrl_t;
dkato 0:853f5b7408a7 209
dkato 0:853f5b7408a7 210 /*! VDC5 system controller register address list */
dkato 0:853f5b7408a7 211 typedef struct {
dkato 0:853f5b7408a7 212 volatile uint32_t * syscnt_int1;
dkato 0:853f5b7408a7 213 volatile uint32_t * syscnt_int2;
dkato 0:853f5b7408a7 214 volatile uint32_t * syscnt_int3;
dkato 0:853f5b7408a7 215 volatile uint32_t * syscnt_int4;
dkato 0:853f5b7408a7 216 volatile uint32_t * syscnt_int5;
dkato 0:853f5b7408a7 217 volatile uint32_t * syscnt_int6;
dkato 0:853f5b7408a7 218 volatile uint16_t * syscnt_panel_clk;
dkato 0:853f5b7408a7 219 volatile uint16_t * syscnt_clut;
dkato 0:853f5b7408a7 220 } vdc5_regaddr_system_ctrl_t;
dkato 0:853f5b7408a7 221
dkato 0:853f5b7408a7 222 /*! LVDS register address list */
dkato 0:853f5b7408a7 223 typedef struct {
dkato 0:853f5b7408a7 224 volatile uint32_t * lvds_update;
dkato 0:853f5b7408a7 225 volatile uint32_t * lvdsfcl;
dkato 0:853f5b7408a7 226 volatile uint32_t * lclkselr;
dkato 0:853f5b7408a7 227 volatile uint32_t * lpllsetr;
dkato 0:853f5b7408a7 228 volatile uint32_t * lphyacc;
dkato 0:853f5b7408a7 229 } vdc5_regaddr_lvds_t;
dkato 0:853f5b7408a7 230
dkato 0:853f5b7408a7 231
dkato 0:853f5b7408a7 232 /******************************************************************************
dkato 0:853f5b7408a7 233 Variable Externs
dkato 0:853f5b7408a7 234 ******************************************************************************/
dkato 0:853f5b7408a7 235 extern const vdc5_regaddr_input_ctrl_t vdc5_regaddr_input_ctrl[VDC5_CHANNEL_NUM];
dkato 0:853f5b7408a7 236 extern const vdc5_regaddr_scaler_t vdc5_regaddr_scaler[VDC5_CHANNEL_NUM][VDC5_SC_TYPE_NUM];
dkato 0:853f5b7408a7 237 extern const vdc5_regaddr_img_qlty_imp_t vdc5_regaddr_img_qlty_imp[VDC5_CHANNEL_NUM][VDC5_IMG_IMPRV_NUM];
dkato 0:853f5b7408a7 238 extern const vdc5_regaddr_color_matrix_t vdc5_regaddr_color_matrix[VDC5_CHANNEL_NUM][VDC5_COLORMTX_NUM];
dkato 0:853f5b7408a7 239 extern const vdc5_regaddr_img_synthesizer_t vdc5_regaddr_img_synthesizer[VDC5_CHANNEL_NUM][VDC5_GR_TYPE_NUM];
dkato 0:853f5b7408a7 240 extern uint32_t * const vdc5_regaddr_clut[VDC5_CHANNEL_NUM][VDC5_GR_TYPE_NUM];
dkato 0:853f5b7408a7 241 extern const vdc5_regaddr_output_ctrl_t vdc5_regaddr_output_ctrl[VDC5_CHANNEL_NUM];
dkato 0:853f5b7408a7 242 extern const vdc5_regaddr_gamma_t vdc5_regaddr_gamma[VDC5_CHANNEL_NUM];
dkato 0:853f5b7408a7 243 extern const vdc5_regaddr_system_ctrl_t vdc5_regaddr_system_ctrl[VDC5_CHANNEL_NUM];
dkato 0:853f5b7408a7 244 extern const vdc5_regaddr_lvds_t vdc5_regaddr_lvds;
dkato 0:853f5b7408a7 245
dkato 0:853f5b7408a7 246
dkato 0:853f5b7408a7 247 /******************************************************************************
dkato 0:853f5b7408a7 248 Functions Prototypes
dkato 0:853f5b7408a7 249 ******************************************************************************/
dkato 0:853f5b7408a7 250 void VDC5_Initialize(const vdc5_channel_t ch, const vdc5_init_t * const param);
dkato 0:853f5b7408a7 251 void VDC5_Terminate(const vdc5_channel_t ch);
dkato 0:853f5b7408a7 252 void VDC5_VideoInput(const vdc5_channel_t ch, const vdc5_input_t * const param);
dkato 0:853f5b7408a7 253 void VDC5_SyncControl(const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param);
dkato 0:853f5b7408a7 254 void VDC5_DisplayOutput(const vdc5_channel_t ch, const vdc5_output_t * const param);
dkato 0:853f5b7408a7 255 void VDC5_WriteDataControl(
dkato 0:853f5b7408a7 256 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 257 const vdc5_scaling_type_t scaling_id,
dkato 0:853f5b7408a7 258 const vdc5_write_t * const param);
dkato 0:853f5b7408a7 259 void VDC5_ChangeWriteProcess(
dkato 0:853f5b7408a7 260 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 261 const vdc5_scaling_type_t scaling_id,
dkato 0:853f5b7408a7 262 const vdc5_write_chg_t * const param);
dkato 0:853f5b7408a7 263 void VDC5_ReadDataControl(
dkato 0:853f5b7408a7 264 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 265 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 266 const vdc5_read_t * const param);
dkato 0:853f5b7408a7 267 void VDC5_ChangeReadProcess(
dkato 0:853f5b7408a7 268 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 269 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 270 const vdc5_read_chg_t * const param);
dkato 0:853f5b7408a7 271 void VDC5_StartProcess(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_start_t * const param);
dkato 0:853f5b7408a7 272 void VDC5_StopProcess(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
dkato 0:853f5b7408a7 273 void VDC5_ReleaseDataControl(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
dkato 0:853f5b7408a7 274 void VDC5_VideoNoiseReduction(
dkato 0:853f5b7408a7 275 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 276 const vdc5_onoff_t nr1d_on,
dkato 0:853f5b7408a7 277 const vdc5_noise_reduction_t * const param);
dkato 0:853f5b7408a7 278 void VDC5_ImageColorMatrix(const vdc5_channel_t ch, const vdc5_color_matrix_t * const param);
dkato 0:853f5b7408a7 279 void VDC5_ImageEnhancement(
dkato 0:853f5b7408a7 280 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 281 const vdc5_imgimprv_id_t imgimprv_id,
dkato 0:853f5b7408a7 282 const vdc5_onoff_t shp_h_on,
dkato 0:853f5b7408a7 283 const vdc5_enhance_sharp_t * const sharp_param,
dkato 0:853f5b7408a7 284 const vdc5_onoff_t lti_h_on,
dkato 0:853f5b7408a7 285 const vdc5_enhance_lti_t * const lti_param,
dkato 0:853f5b7408a7 286 const vdc5_period_rect_t * const enh_area);
dkato 0:853f5b7408a7 287 void VDC5_ImageBlackStretch(
dkato 0:853f5b7408a7 288 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 289 const vdc5_imgimprv_id_t imgimprv_id,
dkato 0:853f5b7408a7 290 const vdc5_onoff_t bkstr_on,
dkato 0:853f5b7408a7 291 const vdc5_black_t * const param);
dkato 0:853f5b7408a7 292 void VDC5_AlphaBlending(
dkato 0:853f5b7408a7 293 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 294 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 295 const vdc5_alpha_blending_t * const param);
dkato 0:853f5b7408a7 296 void VDC5_AlphaBlendingRect(
dkato 0:853f5b7408a7 297 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 298 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 299 const vdc5_onoff_t gr_arc_on,
dkato 0:853f5b7408a7 300 const vdc5_alpha_blending_rect_t * const param);
dkato 0:853f5b7408a7 301 void VDC5_Chromakey(
dkato 0:853f5b7408a7 302 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 303 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 304 const vdc5_onoff_t gr_ck_on,
dkato 0:853f5b7408a7 305 const vdc5_chromakey_t * const param);
dkato 0:853f5b7408a7 306 void VDC5_CLUT(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id, const vdc5_clut_t * const param);
dkato 0:853f5b7408a7 307 void VDC5_DisplayCalibration(const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param);
dkato 0:853f5b7408a7 308 void VDC5_GammaCorrection(
dkato 0:853f5b7408a7 309 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 310 const vdc5_onoff_t gam_on,
dkato 0:853f5b7408a7 311 const vdc5_gamma_correction_t * const param);
dkato 0:853f5b7408a7 312
dkato 0:853f5b7408a7 313 void VDC5_Int_Disable(const vdc5_channel_t ch);
dkato 0:853f5b7408a7 314 void VDC5_Int_SetInterrupt(const vdc5_channel_t ch, const vdc5_int_t * const param);
dkato 0:853f5b7408a7 315
dkato 0:853f5b7408a7 316
dkato 0:853f5b7408a7 317 #endif /* R_VDC5_REGISTER_H */
dkato 0:853f5b7408a7 318