RT2_P3 / Mbed 2 deprecated nucf446-cuboid-balance_strong

cuboid strong

Dependencies:   mbed

EncoderCounter.cpp@2:38d9d1c3c85f, 2018-03-01 (annotated)

Committer:
altb
Date:
Thu Mar 01 10:33:19 2018 +0000
Revision:
2:38d9d1c3c85f
Parent:
0:15be70d21d7c 
Cuboid with lift up and down

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rtlabor 0:15be70d21d7c 1 /*
rtlabor 0:15be70d21d7c 2 * EncoderCounter.cpp
rtlabor 0:15be70d21d7c 3 * Copyright (c) 2017, ZHAW
rtlabor 0:15be70d21d7c 4 * All rights reserved.
rtlabor 0:15be70d21d7c 5 */
rtlabor 0:15be70d21d7c 6
rtlabor 0:15be70d21d7c 7 #include "EncoderCounter.h"
rtlabor 0:15be70d21d7c 8
rtlabor 0:15be70d21d7c 9 using namespace std;
rtlabor 0:15be70d21d7c 10
rtlabor 0:15be70d21d7c 11 /**
rtlabor 0:15be70d21d7c 12 * Creates and initializes the driver to read the quadrature
rtlabor 0:15be70d21d7c 13 * encoder counter of the STM32 microcontroller.
rtlabor 0:15be70d21d7c 14 * @param a the input pin for the channel A.
rtlabor 0:15be70d21d7c 15 * @param b the input pin for the channel B.
rtlabor 0:15be70d21d7c 16 */
rtlabor 0:15be70d21d7c 17 EncoderCounter::EncoderCounter(PinName a, PinName b) {
rtlabor 0:15be70d21d7c 18
rtlabor 0:15be70d21d7c 19 // check pins
rtlabor 0:15be70d21d7c 20
rtlabor 0:15be70d21d7c 21 if ((a == PA_6) && (b == PC_7)) {
rtlabor 0:15be70d21d7c 22
rtlabor 0:15be70d21d7c 23 // pinmap OK for TIM3 CH1 and CH2
rtlabor 0:15be70d21d7c 24
rtlabor 0:15be70d21d7c 25 TIM = TIM3;
rtlabor 0:15be70d21d7c 26
rtlabor 0:15be70d21d7c 27 // configure reset and clock control registers
rtlabor 0:15be70d21d7c 28
rtlabor 0:15be70d21d7c 29 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN; // manually enable port C (port A enabled by mbed library)
rtlabor 0:15be70d21d7c 30
rtlabor 0:15be70d21d7c 31 // configure general purpose I/O registers
rtlabor 0:15be70d21d7c 32
rtlabor 0:15be70d21d7c 33 GPIOA->MODER &= ~GPIO_MODER_MODER6; // reset port A6
rtlabor 0:15be70d21d7c 34 GPIOA->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port A6
rtlabor 0:15be70d21d7c 35 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port A6
rtlabor 0:15be70d21d7c 36 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
rtlabor 0:15be70d21d7c 37 GPIOA->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port A6
rtlabor 0:15be70d21d7c 38 GPIOA->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port A6
rtlabor 0:15be70d21d7c 39
rtlabor 0:15be70d21d7c 40 GPIOC->MODER &= ~GPIO_MODER_MODER7; // reset port C7
rtlabor 0:15be70d21d7c 41 GPIOC->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port C7
rtlabor 0:15be70d21d7c 42 GPIOC->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port C7
rtlabor 0:15be70d21d7c 43 GPIOC->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
rtlabor 0:15be70d21d7c 44 GPIOC->AFR[0] &= ~0xF0000000; // reset alternate function of port C7
rtlabor 0:15be70d21d7c 45 GPIOC->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port C7
rtlabor 0:15be70d21d7c 46
rtlabor 0:15be70d21d7c 47 // configure reset and clock control registers
rtlabor 0:15be70d21d7c 48
rtlabor 0:15be70d21d7c 49 RCC->APB1RSTR |= RCC_APB1RSTR_TIM3RST; //reset TIM3 controller
rtlabor 0:15be70d21d7c 50 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM3RST;
rtlabor 0:15be70d21d7c 51
rtlabor 0:15be70d21d7c 52 RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; // TIM3 clock enable
rtlabor 0:15be70d21d7c 53
rtlabor 0:15be70d21d7c 54 } else if ((a == PB_6) && (b == PB_7)) {
rtlabor 0:15be70d21d7c 55
rtlabor 0:15be70d21d7c 56 // pinmap OK for TIM4 CH1 and CH2
rtlabor 0:15be70d21d7c 57
rtlabor 0:15be70d21d7c 58 TIM = TIM4;
rtlabor 0:15be70d21d7c 59
rtlabor 0:15be70d21d7c 60 // configure reset and clock control registers
rtlabor 0:15be70d21d7c 61
rtlabor 0:15be70d21d7c 62 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; // manually enable port B (port A enabled by mbed library)
rtlabor 0:15be70d21d7c 63
rtlabor 0:15be70d21d7c 64 // configure general purpose I/O registers
rtlabor 0:15be70d21d7c 65
rtlabor 0:15be70d21d7c 66 GPIOB->MODER &= ~GPIO_MODER_MODER6; // reset port B6
rtlabor 0:15be70d21d7c 67 GPIOB->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port B6
rtlabor 0:15be70d21d7c 68 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port B6
rtlabor 0:15be70d21d7c 69 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
rtlabor 0:15be70d21d7c 70 GPIOB->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port B6
rtlabor 0:15be70d21d7c 71 GPIOB->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port B6
rtlabor 0:15be70d21d7c 72
rtlabor 0:15be70d21d7c 73 GPIOB->MODER &= ~GPIO_MODER_MODER7; // reset port B7
rtlabor 0:15be70d21d7c 74 GPIOB->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port B7
rtlabor 0:15be70d21d7c 75 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port B7
rtlabor 0:15be70d21d7c 76 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
rtlabor 0:15be70d21d7c 77 GPIOB->AFR[0] &= ~0xF0000000; // reset alternate function of port B7
rtlabor 0:15be70d21d7c 78 GPIOB->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port B7
rtlabor 0:15be70d21d7c 79
rtlabor 0:15be70d21d7c 80 // configure reset and clock control registers
rtlabor 0:15be70d21d7c 81
rtlabor 0:15be70d21d7c 82 RCC->APB1RSTR |= RCC_APB1RSTR_TIM4RST; //reset TIM4 controller
rtlabor 0:15be70d21d7c 83 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM4RST;
rtlabor 0:15be70d21d7c 84
rtlabor 0:15be70d21d7c 85 RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; // TIM4 clock enable
rtlabor 0:15be70d21d7c 86
rtlabor 0:15be70d21d7c 87 } else {
rtlabor 0:15be70d21d7c 88
rtlabor 0:15be70d21d7c 89 printf("pinmap not found for peripheral\n");
rtlabor 0:15be70d21d7c 90 }
rtlabor 0:15be70d21d7c 91
rtlabor 0:15be70d21d7c 92 // configure general purpose timer 3 or 4
rtlabor 0:15be70d21d7c 93
rtlabor 0:15be70d21d7c 94 TIM->CR1 = 0x0000; // counter disable
rtlabor 0:15be70d21d7c 95 TIM->CR2 = 0x0000; // reset master mode selection
rtlabor 0:15be70d21d7c 96 TIM->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0; // counting on both TI1 & TI2 edges
rtlabor 0:15be70d21d7c 97 TIM->CCMR1 = TIM_CCMR1_CC2S_0 | TIM_CCMR1_CC1S_0;
rtlabor 0:15be70d21d7c 98 TIM->CCMR2 = 0x0000; // reset capture mode register 2
rtlabor 0:15be70d21d7c 99 TIM->CCER = TIM_CCER_CC2E | TIM_CCER_CC1E;
rtlabor 0:15be70d21d7c 100 TIM->CNT = 0x0000; // reset counter value
rtlabor 0:15be70d21d7c 101 TIM->ARR = 0xFFFF; // auto reload register
rtlabor 0:15be70d21d7c 102 TIM->CR1 = TIM_CR1_CEN; // counter enable
rtlabor 0:15be70d21d7c 103 }
rtlabor 0:15be70d21d7c 104
rtlabor 0:15be70d21d7c 105 EncoderCounter::~EncoderCounter() {}
rtlabor 0:15be70d21d7c 106
rtlabor 0:15be70d21d7c 107 /**
rtlabor 0:15be70d21d7c 108 * Resets the counter value to zero.
rtlabor 0:15be70d21d7c 109 */
rtlabor 0:15be70d21d7c 110 void EncoderCounter::reset() {
rtlabor 0:15be70d21d7c 111
rtlabor 0:15be70d21d7c 112 TIM->CNT = 0x0000;
rtlabor 0:15be70d21d7c 113 }
rtlabor 0:15be70d21d7c 114
rtlabor 0:15be70d21d7c 115 /**
rtlabor 0:15be70d21d7c 116 * Resets the counter value to a given offset value.
rtlabor 0:15be70d21d7c 117 * @param offset the offset value to reset the counter to.
rtlabor 0:15be70d21d7c 118 */
rtlabor 0:15be70d21d7c 119 void EncoderCounter::reset(short offset) {
rtlabor 0:15be70d21d7c 120
rtlabor 0:15be70d21d7c 121 TIM->CNT = -offset;
rtlabor 0:15be70d21d7c 122 }
rtlabor 0:15be70d21d7c 123
rtlabor 0:15be70d21d7c 124 /**
rtlabor 0:15be70d21d7c 125 * Reads the quadrature encoder counter value.
rtlabor 0:15be70d21d7c 126 * @return the quadrature encoder counter as a signed 16-bit integer value.
rtlabor 0:15be70d21d7c 127 */
rtlabor 0:15be70d21d7c 128 short EncoderCounter::read() {
rtlabor 0:15be70d21d7c 129
rtlabor 0:15be70d21d7c 130 return (short)(-TIM->CNT);
rtlabor 0:15be70d21d7c 131 }
rtlabor 0:15be70d21d7c 132
rtlabor 0:15be70d21d7c 133 /**
rtlabor 0:15be70d21d7c 134 * The empty operator is a shorthand notation of the <code>read()</code> method.
rtlabor 0:15be70d21d7c 135 */
rtlabor 0:15be70d21d7c 136 EncoderCounter::operator short() {
rtlabor 0:15be70d21d7c 137
rtlabor 0:15be70d21d7c 138 return read();
rtlabor 0:15be70d21d7c 139 }