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targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma_ex.h@0:9b334a45a8ff, 2015-10-01 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Oct 01 15:25:22 2015 +0300
- Revision:
- 0:9b334a45a8ff
- Child:
- 144:ef7eb2e8f9f7
Initial commit on mbed-dev
Replaces mbed-src (now inactive)
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /** |
| bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 3 | * @file stm32f0xx_hal_dma_ex.h |
| bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
| bogdanm | 0:9b334a45a8ff | 5 | * @version V1.3.0 |
| bogdanm | 0:9b334a45a8ff | 6 | * @date 26-June-2015 |
| bogdanm | 0:9b334a45a8ff | 7 | * @brief Header file of DMA HAL Extension module. |
| bogdanm | 0:9b334a45a8ff | 8 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 9 | * @attention |
| bogdanm | 0:9b334a45a8ff | 10 | * |
| bogdanm | 0:9b334a45a8ff | 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| bogdanm | 0:9b334a45a8ff | 12 | * |
| bogdanm | 0:9b334a45a8ff | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 0:9b334a45a8ff | 14 | * are permitted provided that the following conditions are met: |
| bogdanm | 0:9b334a45a8ff | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 16 | * this list of conditions and the following disclaimer. |
| bogdanm | 0:9b334a45a8ff | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 18 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 0:9b334a45a8ff | 19 | * and/or other materials provided with the distribution. |
| bogdanm | 0:9b334a45a8ff | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 0:9b334a45a8ff | 21 | * may be used to endorse or promote products derived from this software |
| bogdanm | 0:9b334a45a8ff | 22 | * without specific prior written permission. |
| bogdanm | 0:9b334a45a8ff | 23 | * |
| bogdanm | 0:9b334a45a8ff | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 0:9b334a45a8ff | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 0:9b334a45a8ff | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 0:9b334a45a8ff | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 0:9b334a45a8ff | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 0:9b334a45a8ff | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 0:9b334a45a8ff | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 0:9b334a45a8ff | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 0:9b334a45a8ff | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 0:9b334a45a8ff | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 0:9b334a45a8ff | 34 | * |
| bogdanm | 0:9b334a45a8ff | 35 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 36 | */ |
| bogdanm | 0:9b334a45a8ff | 37 | |
| bogdanm | 0:9b334a45a8ff | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 39 | #ifndef __STM32F0xx_HAL_DMA_EX_H |
| bogdanm | 0:9b334a45a8ff | 40 | #define __STM32F0xx_HAL_DMA_EX_H |
| bogdanm | 0:9b334a45a8ff | 41 | |
| bogdanm | 0:9b334a45a8ff | 42 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 43 | extern "C" { |
| bogdanm | 0:9b334a45a8ff | 44 | #endif |
| bogdanm | 0:9b334a45a8ff | 45 | |
| bogdanm | 0:9b334a45a8ff | 46 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 47 | #include "stm32f0xx_hal_def.h" |
| bogdanm | 0:9b334a45a8ff | 48 | |
| bogdanm | 0:9b334a45a8ff | 49 | /** @addtogroup STM32F0xx_HAL_Driver |
| bogdanm | 0:9b334a45a8ff | 50 | * @{ |
| bogdanm | 0:9b334a45a8ff | 51 | */ |
| bogdanm | 0:9b334a45a8ff | 52 | |
| bogdanm | 0:9b334a45a8ff | 53 | /** @defgroup DMAEx DMAEx |
| bogdanm | 0:9b334a45a8ff | 54 | * @brief DMA HAL module driver |
| bogdanm | 0:9b334a45a8ff | 55 | * @{ |
| bogdanm | 0:9b334a45a8ff | 56 | */ |
| bogdanm | 0:9b334a45a8ff | 57 | |
| bogdanm | 0:9b334a45a8ff | 58 | /* Exported types ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 59 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 60 | #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
| bogdanm | 0:9b334a45a8ff | 61 | /** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants |
| bogdanm | 0:9b334a45a8ff | 62 | * @{ |
| bogdanm | 0:9b334a45a8ff | 63 | */ |
| bogdanm | 0:9b334a45a8ff | 64 | #define DMA1_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
| bogdanm | 0:9b334a45a8ff | 65 | #define DMA1_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
| bogdanm | 0:9b334a45a8ff | 66 | #define DMA1_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
| bogdanm | 0:9b334a45a8ff | 67 | #define DMA1_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
| bogdanm | 0:9b334a45a8ff | 68 | #define DMA1_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
| bogdanm | 0:9b334a45a8ff | 69 | #if !defined(STM32F030xC) |
| bogdanm | 0:9b334a45a8ff | 70 | #define DMA1_CHANNEL6_RMP 0x50000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
| bogdanm | 0:9b334a45a8ff | 71 | #define DMA1_CHANNEL7_RMP 0x60000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
| bogdanm | 0:9b334a45a8ff | 72 | #define DMA2_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
| bogdanm | 0:9b334a45a8ff | 73 | #define DMA2_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
| bogdanm | 0:9b334a45a8ff | 74 | #define DMA2_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
| bogdanm | 0:9b334a45a8ff | 75 | #define DMA2_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
| bogdanm | 0:9b334a45a8ff | 76 | #define DMA2_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
| bogdanm | 0:9b334a45a8ff | 77 | #endif /* !defined(STM32F030xC) */ |
| bogdanm | 0:9b334a45a8ff | 78 | |
| bogdanm | 0:9b334a45a8ff | 79 | /****************** DMA1 remap bit field definition********************/ |
| bogdanm | 0:9b334a45a8ff | 80 | /* DMA1 - Channel 1 */ |
| bogdanm | 0:9b334a45a8ff | 81 | #define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ |
| bogdanm | 0:9b334a45a8ff | 82 | #define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/ |
| bogdanm | 0:9b334a45a8ff | 83 | #define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */ |
| bogdanm | 0:9b334a45a8ff | 84 | #define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */ |
| bogdanm | 0:9b334a45a8ff | 85 | #define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */ |
| bogdanm | 0:9b334a45a8ff | 86 | #define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */ |
| bogdanm | 0:9b334a45a8ff | 87 | #define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */ |
| bogdanm | 0:9b334a45a8ff | 88 | #define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */ |
| bogdanm | 0:9b334a45a8ff | 89 | #define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */ |
| bogdanm | 0:9b334a45a8ff | 90 | #define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */ |
| bogdanm | 0:9b334a45a8ff | 91 | #if !defined(STM32F030xC) |
| bogdanm | 0:9b334a45a8ff | 92 | #define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */ |
| bogdanm | 0:9b334a45a8ff | 93 | #define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */ |
| bogdanm | 0:9b334a45a8ff | 94 | #endif /* !defined(STM32F030xC) */ |
| bogdanm | 0:9b334a45a8ff | 95 | |
| bogdanm | 0:9b334a45a8ff | 96 | /* DMA1 - Channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 97 | #define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ |
| bogdanm | 0:9b334a45a8ff | 98 | #define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 99 | #define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 100 | #define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_SPI1_RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 101 | #define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 102 | #define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 103 | #define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 104 | #define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 105 | #define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 106 | #define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 107 | #define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 108 | #define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 109 | #define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 110 | #if !defined(STM32F030xC) |
| bogdanm | 0:9b334a45a8ff | 111 | #define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 112 | #define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 113 | #endif /* !defined(STM32F030xC) */ |
| bogdanm | 0:9b334a45a8ff | 114 | |
| bogdanm | 0:9b334a45a8ff | 115 | /* DMA1 - Channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 116 | #define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ |
| bogdanm | 0:9b334a45a8ff | 117 | #define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 118 | #if !defined(STM32F030xC) |
| bogdanm | 0:9b334a45a8ff | 119 | #define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 120 | #endif /* !defined(STM32F030xC) */ |
| bogdanm | 0:9b334a45a8ff | 121 | #define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 122 | #define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 123 | #define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 124 | #if !defined(STM32F030xC) |
| bogdanm | 0:9b334a45a8ff | 125 | #define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 126 | #endif /* !defined(STM32F030xC) */ |
| bogdanm | 0:9b334a45a8ff | 127 | #define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 128 | #define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 129 | #define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 130 | #define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 131 | #define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 132 | #define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 133 | #define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 134 | #define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 135 | #if !defined(STM32F030xC) |
| bogdanm | 0:9b334a45a8ff | 136 | #define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 137 | #define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 138 | #endif /* !defined(STM32F030xC) */ |
| bogdanm | 0:9b334a45a8ff | 139 | |
| bogdanm | 0:9b334a45a8ff | 140 | /* DMA1 - Channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 141 | #define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ |
| bogdanm | 0:9b334a45a8ff | 142 | #define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 143 | #if !defined(STM32F030xC) |
| bogdanm | 0:9b334a45a8ff | 144 | #define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 145 | #endif /* !defined(STM32F030xC) */ |
| bogdanm | 0:9b334a45a8ff | 146 | #define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 147 | #define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 148 | #if !defined(STM32F030xC) |
| bogdanm | 0:9b334a45a8ff | 149 | #define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 150 | #endif /* !defined(STM32F030xC) */ |
| bogdanm | 0:9b334a45a8ff | 151 | #define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 152 | #define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 153 | #define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 154 | #define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 155 | #define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 156 | #define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 157 | #define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 158 | #define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 159 | #define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 160 | #define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 161 | #if !defined(STM32F030xC) |
| bogdanm | 0:9b334a45a8ff | 162 | #define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 163 | #define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 164 | #endif /* !defined(STM32F030xC) */ |
| bogdanm | 0:9b334a45a8ff | 165 | |
| bogdanm | 0:9b334a45a8ff | 166 | /* DMA1 - Channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 167 | #define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ |
| bogdanm | 0:9b334a45a8ff | 168 | #define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 169 | #define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 170 | #define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 171 | #define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 172 | #define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 173 | #define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 174 | #define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 175 | #define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 176 | #define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 177 | #if !defined(STM32F030xC) |
| bogdanm | 0:9b334a45a8ff | 178 | #define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 179 | #define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 180 | #endif /* !defined(STM32F030xC) */ |
| bogdanm | 0:9b334a45a8ff | 181 | |
| bogdanm | 0:9b334a45a8ff | 182 | #if !defined(STM32F030xC) |
| bogdanm | 0:9b334a45a8ff | 183 | /* DMA1 - Channel 6 */ |
| bogdanm | 0:9b334a45a8ff | 184 | #define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ |
| bogdanm | 0:9b334a45a8ff | 185 | #define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */ |
| bogdanm | 0:9b334a45a8ff | 186 | #define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */ |
| bogdanm | 0:9b334a45a8ff | 187 | #define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */ |
| bogdanm | 0:9b334a45a8ff | 188 | #define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */ |
| bogdanm | 0:9b334a45a8ff | 189 | #define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */ |
| bogdanm | 0:9b334a45a8ff | 190 | #define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */ |
| bogdanm | 0:9b334a45a8ff | 191 | #define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */ |
| bogdanm | 0:9b334a45a8ff | 192 | #define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */ |
| bogdanm | 0:9b334a45a8ff | 193 | #define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */ |
| bogdanm | 0:9b334a45a8ff | 194 | #define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */ |
| bogdanm | 0:9b334a45a8ff | 195 | #define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */ |
| bogdanm | 0:9b334a45a8ff | 196 | #define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */ |
| bogdanm | 0:9b334a45a8ff | 197 | #define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */ |
| bogdanm | 0:9b334a45a8ff | 198 | #define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */ |
| bogdanm | 0:9b334a45a8ff | 199 | #define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */ |
| bogdanm | 0:9b334a45a8ff | 200 | #define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */ |
| bogdanm | 0:9b334a45a8ff | 201 | #define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */ |
| bogdanm | 0:9b334a45a8ff | 202 | /* DMA1 - Channel 7 */ |
| bogdanm | 0:9b334a45a8ff | 203 | #define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ |
| bogdanm | 0:9b334a45a8ff | 204 | #define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */ |
| bogdanm | 0:9b334a45a8ff | 205 | #define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */ |
| bogdanm | 0:9b334a45a8ff | 206 | #define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */ |
| bogdanm | 0:9b334a45a8ff | 207 | #define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */ |
| bogdanm | 0:9b334a45a8ff | 208 | #define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */ |
| bogdanm | 0:9b334a45a8ff | 209 | #define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */ |
| bogdanm | 0:9b334a45a8ff | 210 | #define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */ |
| bogdanm | 0:9b334a45a8ff | 211 | #define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */ |
| bogdanm | 0:9b334a45a8ff | 212 | #define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */ |
| bogdanm | 0:9b334a45a8ff | 213 | #define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */ |
| bogdanm | 0:9b334a45a8ff | 214 | #define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */ |
| bogdanm | 0:9b334a45a8ff | 215 | #define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */ |
| bogdanm | 0:9b334a45a8ff | 216 | #define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */ |
| bogdanm | 0:9b334a45a8ff | 217 | #define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */ |
| bogdanm | 0:9b334a45a8ff | 218 | |
| bogdanm | 0:9b334a45a8ff | 219 | /****************** DMA2 remap bit field definition********************/ |
| bogdanm | 0:9b334a45a8ff | 220 | /* DMA2 - Channel 1 */ |
| bogdanm | 0:9b334a45a8ff | 221 | #define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ |
| bogdanm | 0:9b334a45a8ff | 222 | #define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */ |
| bogdanm | 0:9b334a45a8ff | 223 | #define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */ |
| bogdanm | 0:9b334a45a8ff | 224 | #define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */ |
| bogdanm | 0:9b334a45a8ff | 225 | #define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */ |
| bogdanm | 0:9b334a45a8ff | 226 | #define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */ |
| bogdanm | 0:9b334a45a8ff | 227 | #define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */ |
| bogdanm | 0:9b334a45a8ff | 228 | #define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */ |
| bogdanm | 0:9b334a45a8ff | 229 | #define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */ |
| bogdanm | 0:9b334a45a8ff | 230 | #define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */ |
| bogdanm | 0:9b334a45a8ff | 231 | /* DMA2 - Channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 232 | #define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ |
| bogdanm | 0:9b334a45a8ff | 233 | #define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 234 | #define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 235 | #define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 236 | #define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 237 | #define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 238 | #define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 239 | #define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 240 | #define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 241 | #define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 242 | /* DMA2 - Channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 243 | #define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ |
| bogdanm | 0:9b334a45a8ff | 244 | #define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 245 | #define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 246 | #define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 247 | #define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 248 | #define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 249 | #define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 250 | #define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 251 | #define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 252 | #define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 253 | #define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 254 | #define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 255 | /* DMA2 - Channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 256 | #define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ |
| bogdanm | 0:9b334a45a8ff | 257 | #define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 258 | #define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 259 | #define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 260 | #define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 261 | #define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 262 | #define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 263 | #define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 264 | #define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 265 | #define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 266 | #define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 267 | #define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 268 | /* DMA2 - Channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 269 | #define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ |
| bogdanm | 0:9b334a45a8ff | 270 | #define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 271 | #define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 272 | #define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 273 | #define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 274 | #define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 275 | #define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 276 | #define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 277 | #define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 278 | #define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 279 | #endif /* !defined(STM32F030xC) */ |
| bogdanm | 0:9b334a45a8ff | 280 | |
| bogdanm | 0:9b334a45a8ff | 281 | #if defined(STM32F091xC) || defined(STM32F098xx) |
| bogdanm | 0:9b334a45a8ff | 282 | #define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\ |
| bogdanm | 0:9b334a45a8ff | 283 | ((REQUEST) == HAL_DMA1_CH1_ADC) ||\ |
| bogdanm | 0:9b334a45a8ff | 284 | ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\ |
| bogdanm | 0:9b334a45a8ff | 285 | ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\ |
| bogdanm | 0:9b334a45a8ff | 286 | ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 287 | ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 288 | ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 289 | ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 290 | ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 291 | ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 292 | ((REQUEST) == HAL_DMA1_CH1_USART7_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 293 | ((REQUEST) == HAL_DMA1_CH1_USART8_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 294 | ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\ |
| bogdanm | 0:9b334a45a8ff | 295 | ((REQUEST) == HAL_DMA1_CH2_ADC) ||\ |
| bogdanm | 0:9b334a45a8ff | 296 | ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 297 | ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 298 | ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\ |
| bogdanm | 0:9b334a45a8ff | 299 | ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 300 | ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\ |
| bogdanm | 0:9b334a45a8ff | 301 | ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\ |
| bogdanm | 0:9b334a45a8ff | 302 | ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 303 | ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 304 | ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 305 | ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 306 | ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 307 | ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 308 | ((REQUEST) == HAL_DMA1_CH2_USART7_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 309 | ((REQUEST) == HAL_DMA1_CH2_USART8_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 310 | ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\ |
| bogdanm | 0:9b334a45a8ff | 311 | ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\ |
| bogdanm | 0:9b334a45a8ff | 312 | ((REQUEST) == HAL_DMA1_CH3_DAC_CH1) ||\ |
| bogdanm | 0:9b334a45a8ff | 313 | ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 314 | ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 315 | ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\ |
| bogdanm | 0:9b334a45a8ff | 316 | ((REQUEST) == HAL_DMA1_CH3_TIM2_CH2) ||\ |
| bogdanm | 0:9b334a45a8ff | 317 | ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\ |
| bogdanm | 0:9b334a45a8ff | 318 | ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\ |
| bogdanm | 0:9b334a45a8ff | 319 | ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 320 | ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 321 | ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 322 | ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 323 | ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 324 | ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 325 | ((REQUEST) == HAL_DMA1_CH3_USART7_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 326 | ((REQUEST) == HAL_DMA1_CH3_USART8_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 327 | ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\ |
| bogdanm | 0:9b334a45a8ff | 328 | ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\ |
| bogdanm | 0:9b334a45a8ff | 329 | ((REQUEST) == HAL_DMA1_CH4_DAC_CH2) ||\ |
| bogdanm | 0:9b334a45a8ff | 330 | ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 331 | ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 332 | ((REQUEST) == HAL_DMA1_CH4_TIM2_CH4) ||\ |
| bogdanm | 0:9b334a45a8ff | 333 | ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\ |
| bogdanm | 0:9b334a45a8ff | 334 | ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\ |
| bogdanm | 0:9b334a45a8ff | 335 | ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\ |
| bogdanm | 0:9b334a45a8ff | 336 | ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\ |
| bogdanm | 0:9b334a45a8ff | 337 | ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 338 | ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 339 | ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 340 | ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 341 | ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 342 | ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 343 | ((REQUEST) == HAL_DMA1_CH4_USART7_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 344 | ((REQUEST) == HAL_DMA1_CH4_USART8_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 345 | ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\ |
| bogdanm | 0:9b334a45a8ff | 346 | ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 347 | ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 348 | ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\ |
| bogdanm | 0:9b334a45a8ff | 349 | ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 350 | ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 351 | ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 352 | ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 353 | ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 354 | ((REQUEST) == HAL_DMA1_CH5_USART6_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 355 | ((REQUEST) == HAL_DMA1_CH5_USART7_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 356 | ((REQUEST) == HAL_DMA1_CH5_USART8_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 357 | ((REQUEST) == HAL_DMA1_CH6_DEFAULT) ||\ |
| bogdanm | 0:9b334a45a8ff | 358 | ((REQUEST) == HAL_DMA1_CH6_I2C1_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 359 | ((REQUEST) == HAL_DMA1_CH6_SPI2_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 360 | ((REQUEST) == HAL_DMA1_CH6_TIM1_CH1) ||\ |
| bogdanm | 0:9b334a45a8ff | 361 | ((REQUEST) == HAL_DMA1_CH6_TIM1_CH2) ||\ |
| bogdanm | 0:9b334a45a8ff | 362 | ((REQUEST) == HAL_DMA1_CH6_TIM1_CH3) ||\ |
| bogdanm | 0:9b334a45a8ff | 363 | ((REQUEST) == HAL_DMA1_CH6_TIM3_CH1) ||\ |
| bogdanm | 0:9b334a45a8ff | 364 | ((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) ||\ |
| bogdanm | 0:9b334a45a8ff | 365 | ((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) ||\ |
| bogdanm | 0:9b334a45a8ff | 366 | ((REQUEST) == HAL_DMA1_CH6_TIM16_UP) ||\ |
| bogdanm | 0:9b334a45a8ff | 367 | ((REQUEST) == HAL_DMA1_CH6_USART1_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 368 | ((REQUEST) == HAL_DMA1_CH6_USART2_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 369 | ((REQUEST) == HAL_DMA1_CH6_USART3_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 370 | ((REQUEST) == HAL_DMA1_CH6_USART4_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 371 | ((REQUEST) == HAL_DMA1_CH6_USART5_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 372 | ((REQUEST) == HAL_DMA1_CH6_USART6_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 373 | ((REQUEST) == HAL_DMA1_CH6_USART7_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 374 | ((REQUEST) == HAL_DMA1_CH6_USART8_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 375 | ((REQUEST) == HAL_DMA1_CH7_DEFAULT) ||\ |
| bogdanm | 0:9b334a45a8ff | 376 | ((REQUEST) == HAL_DMA1_CH7_I2C1_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 377 | ((REQUEST) == HAL_DMA1_CH7_SPI2_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 378 | ((REQUEST) == HAL_DMA1_CH7_TIM2_CH2) ||\ |
| bogdanm | 0:9b334a45a8ff | 379 | ((REQUEST) == HAL_DMA1_CH7_TIM2_CH4) ||\ |
| bogdanm | 0:9b334a45a8ff | 380 | ((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) ||\ |
| bogdanm | 0:9b334a45a8ff | 381 | ((REQUEST) == HAL_DMA1_CH7_TIM17_UP) ||\ |
| bogdanm | 0:9b334a45a8ff | 382 | ((REQUEST) == HAL_DMA1_CH7_USART1_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 383 | ((REQUEST) == HAL_DMA1_CH7_USART2_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 384 | ((REQUEST) == HAL_DMA1_CH7_USART3_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 385 | ((REQUEST) == HAL_DMA1_CH7_USART4_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 386 | ((REQUEST) == HAL_DMA1_CH7_USART5_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 387 | ((REQUEST) == HAL_DMA1_CH7_USART6_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 388 | ((REQUEST) == HAL_DMA1_CH7_USART7_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 389 | ((REQUEST) == HAL_DMA1_CH7_USART8_TX)) |
| bogdanm | 0:9b334a45a8ff | 390 | |
| bogdanm | 0:9b334a45a8ff | 391 | #define IS_HAL_DMA2_REMAP(REQUEST) (((REQUEST) == HAL_DMA2_CH1_DEFAULT) ||\ |
| bogdanm | 0:9b334a45a8ff | 392 | ((REQUEST) == HAL_DMA2_CH1_I2C2_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 393 | ((REQUEST) == HAL_DMA2_CH1_USART1_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 394 | ((REQUEST) == HAL_DMA2_CH1_USART2_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 395 | ((REQUEST) == HAL_DMA2_CH1_USART3_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 396 | ((REQUEST) == HAL_DMA2_CH1_USART4_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 397 | ((REQUEST) == HAL_DMA2_CH1_USART5_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 398 | ((REQUEST) == HAL_DMA2_CH1_USART6_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 399 | ((REQUEST) == HAL_DMA2_CH1_USART7_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 400 | ((REQUEST) == HAL_DMA2_CH1_USART8_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 401 | ((REQUEST) == HAL_DMA2_CH2_DEFAULT) ||\ |
| bogdanm | 0:9b334a45a8ff | 402 | ((REQUEST) == HAL_DMA2_CH2_I2C2_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 403 | ((REQUEST) == HAL_DMA2_CH2_USART1_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 404 | ((REQUEST) == HAL_DMA2_CH2_USART2_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 405 | ((REQUEST) == HAL_DMA2_CH2_USART3_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 406 | ((REQUEST) == HAL_DMA2_CH2_USART4_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 407 | ((REQUEST) == HAL_DMA2_CH2_USART5_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 408 | ((REQUEST) == HAL_DMA2_CH2_USART6_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 409 | ((REQUEST) == HAL_DMA2_CH2_USART7_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 410 | ((REQUEST) == HAL_DMA2_CH2_USART8_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 411 | ((REQUEST) == HAL_DMA2_CH3_DEFAULT) ||\ |
| bogdanm | 0:9b334a45a8ff | 412 | ((REQUEST) == HAL_DMA2_CH3_TIM6_UP) ||\ |
| bogdanm | 0:9b334a45a8ff | 413 | ((REQUEST) == HAL_DMA2_CH3_DAC_CH1) ||\ |
| bogdanm | 0:9b334a45a8ff | 414 | ((REQUEST) == HAL_DMA2_CH3_SPI1_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 415 | ((REQUEST) == HAL_DMA2_CH3_USART1_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 416 | ((REQUEST) == HAL_DMA2_CH3_USART2_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 417 | ((REQUEST) == HAL_DMA2_CH3_USART3_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 418 | ((REQUEST) == HAL_DMA2_CH3_USART4_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 419 | ((REQUEST) == HAL_DMA2_CH3_USART5_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 420 | ((REQUEST) == HAL_DMA2_CH3_USART6_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 421 | ((REQUEST) == HAL_DMA2_CH3_USART7_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 422 | ((REQUEST) == HAL_DMA2_CH3_USART8_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 423 | ((REQUEST) == HAL_DMA2_CH4_DEFAULT) ||\ |
| bogdanm | 0:9b334a45a8ff | 424 | ((REQUEST) == HAL_DMA2_CH4_TIM7_UP) ||\ |
| bogdanm | 0:9b334a45a8ff | 425 | ((REQUEST) == HAL_DMA2_CH4_DAC_CH2) ||\ |
| bogdanm | 0:9b334a45a8ff | 426 | ((REQUEST) == HAL_DMA2_CH4_SPI1_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 427 | ((REQUEST) == HAL_DMA2_CH4_USART1_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 428 | ((REQUEST) == HAL_DMA2_CH4_USART2_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 429 | ((REQUEST) == HAL_DMA2_CH4_USART3_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 430 | ((REQUEST) == HAL_DMA2_CH4_USART4_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 431 | ((REQUEST) == HAL_DMA2_CH4_USART5_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 432 | ((REQUEST) == HAL_DMA2_CH4_USART6_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 433 | ((REQUEST) == HAL_DMA2_CH4_USART7_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 434 | ((REQUEST) == HAL_DMA2_CH4_USART8_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 435 | ((REQUEST) == HAL_DMA2_CH5_DEFAULT) ||\ |
| bogdanm | 0:9b334a45a8ff | 436 | ((REQUEST) == HAL_DMA2_CH5_ADC) ||\ |
| bogdanm | 0:9b334a45a8ff | 437 | ((REQUEST) == HAL_DMA2_CH5_USART1_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 438 | ((REQUEST) == HAL_DMA2_CH5_USART2_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 439 | ((REQUEST) == HAL_DMA2_CH5_USART3_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 440 | ((REQUEST) == HAL_DMA2_CH5_USART4_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 441 | ((REQUEST) == HAL_DMA2_CH5_USART5_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 442 | ((REQUEST) == HAL_DMA2_CH5_USART6_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 443 | ((REQUEST) == HAL_DMA2_CH5_USART7_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 444 | ((REQUEST) == HAL_DMA2_CH5_USART8_TX )) |
| bogdanm | 0:9b334a45a8ff | 445 | #endif /* STM32F091xC || STM32F098xx */ |
| bogdanm | 0:9b334a45a8ff | 446 | |
| bogdanm | 0:9b334a45a8ff | 447 | #if defined(STM32F030xC) |
| bogdanm | 0:9b334a45a8ff | 448 | #define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\ |
| bogdanm | 0:9b334a45a8ff | 449 | ((REQUEST) == HAL_DMA1_CH1_ADC) ||\ |
| bogdanm | 0:9b334a45a8ff | 450 | ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\ |
| bogdanm | 0:9b334a45a8ff | 451 | ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\ |
| bogdanm | 0:9b334a45a8ff | 452 | ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 453 | ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 454 | ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 455 | ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 456 | ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 457 | ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 458 | ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\ |
| bogdanm | 0:9b334a45a8ff | 459 | ((REQUEST) == HAL_DMA1_CH2_ADC) ||\ |
| bogdanm | 0:9b334a45a8ff | 460 | ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 461 | ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 462 | ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\ |
| bogdanm | 0:9b334a45a8ff | 463 | ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 464 | ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\ |
| bogdanm | 0:9b334a45a8ff | 465 | ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\ |
| bogdanm | 0:9b334a45a8ff | 466 | ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 467 | ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 468 | ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 469 | ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 470 | ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 471 | ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 472 | ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\ |
| bogdanm | 0:9b334a45a8ff | 473 | ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\ |
| bogdanm | 0:9b334a45a8ff | 474 | ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 475 | ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 476 | ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\ |
| bogdanm | 0:9b334a45a8ff | 477 | ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\ |
| bogdanm | 0:9b334a45a8ff | 478 | ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\ |
| bogdanm | 0:9b334a45a8ff | 479 | ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 480 | ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 481 | ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 482 | ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 483 | ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 484 | ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 485 | ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\ |
| bogdanm | 0:9b334a45a8ff | 486 | ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\ |
| bogdanm | 0:9b334a45a8ff | 487 | ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 488 | ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 489 | ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\ |
| bogdanm | 0:9b334a45a8ff | 490 | ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\ |
| bogdanm | 0:9b334a45a8ff | 491 | ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\ |
| bogdanm | 0:9b334a45a8ff | 492 | ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\ |
| bogdanm | 0:9b334a45a8ff | 493 | ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 494 | ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 495 | ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 496 | ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 497 | ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 498 | ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 499 | ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\ |
| bogdanm | 0:9b334a45a8ff | 500 | ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 501 | ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\ |
| bogdanm | 0:9b334a45a8ff | 502 | ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\ |
| bogdanm | 0:9b334a45a8ff | 503 | ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 504 | ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 505 | ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 506 | ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 507 | ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\ |
| bogdanm | 0:9b334a45a8ff | 508 | ((REQUEST) == HAL_DMA1_CH5_USART6_RX)) |
| bogdanm | 0:9b334a45a8ff | 509 | #endif /* STM32F030xC */ |
| bogdanm | 0:9b334a45a8ff | 510 | |
| bogdanm | 0:9b334a45a8ff | 511 | /** |
| bogdanm | 0:9b334a45a8ff | 512 | * @} |
| bogdanm | 0:9b334a45a8ff | 513 | */ |
| bogdanm | 0:9b334a45a8ff | 514 | #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ |
| bogdanm | 0:9b334a45a8ff | 515 | |
| bogdanm | 0:9b334a45a8ff | 516 | /* Exported macros -----------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 517 | |
| bogdanm | 0:9b334a45a8ff | 518 | /** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros |
| bogdanm | 0:9b334a45a8ff | 519 | * @{ |
| bogdanm | 0:9b334a45a8ff | 520 | */ |
| bogdanm | 0:9b334a45a8ff | 521 | /* Interrupt & Flag management */ |
| bogdanm | 0:9b334a45a8ff | 522 | |
| bogdanm | 0:9b334a45a8ff | 523 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
| bogdanm | 0:9b334a45a8ff | 524 | /** |
| bogdanm | 0:9b334a45a8ff | 525 | * @brief Returns the current DMA Channel transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 526 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 527 | * @retval The specified transfer complete flag index. |
| bogdanm | 0:9b334a45a8ff | 528 | */ |
| bogdanm | 0:9b334a45a8ff | 529 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
| bogdanm | 0:9b334a45a8ff | 530 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ |
| bogdanm | 0:9b334a45a8ff | 531 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ |
| bogdanm | 0:9b334a45a8ff | 532 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ |
| bogdanm | 0:9b334a45a8ff | 533 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ |
| bogdanm | 0:9b334a45a8ff | 534 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ |
| bogdanm | 0:9b334a45a8ff | 535 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ |
| bogdanm | 0:9b334a45a8ff | 536 | DMA_FLAG_TC7) |
| bogdanm | 0:9b334a45a8ff | 537 | |
| bogdanm | 0:9b334a45a8ff | 538 | /** |
| bogdanm | 0:9b334a45a8ff | 539 | * @brief Returns the current DMA Channel half transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 540 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 541 | * @retval The specified half transfer complete flag index. |
| bogdanm | 0:9b334a45a8ff | 542 | */ |
| bogdanm | 0:9b334a45a8ff | 543 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
| bogdanm | 0:9b334a45a8ff | 544 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ |
| bogdanm | 0:9b334a45a8ff | 545 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ |
| bogdanm | 0:9b334a45a8ff | 546 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ |
| bogdanm | 0:9b334a45a8ff | 547 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ |
| bogdanm | 0:9b334a45a8ff | 548 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ |
| bogdanm | 0:9b334a45a8ff | 549 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ |
| bogdanm | 0:9b334a45a8ff | 550 | DMA_FLAG_HT7) |
| bogdanm | 0:9b334a45a8ff | 551 | |
| bogdanm | 0:9b334a45a8ff | 552 | /** |
| bogdanm | 0:9b334a45a8ff | 553 | * @brief Returns the current DMA Channel transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 554 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 555 | * @retval The specified transfer error flag index. |
| bogdanm | 0:9b334a45a8ff | 556 | */ |
| bogdanm | 0:9b334a45a8ff | 557 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
| bogdanm | 0:9b334a45a8ff | 558 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ |
| bogdanm | 0:9b334a45a8ff | 559 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ |
| bogdanm | 0:9b334a45a8ff | 560 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ |
| bogdanm | 0:9b334a45a8ff | 561 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ |
| bogdanm | 0:9b334a45a8ff | 562 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ |
| bogdanm | 0:9b334a45a8ff | 563 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ |
| bogdanm | 0:9b334a45a8ff | 564 | DMA_FLAG_TE7) |
| bogdanm | 0:9b334a45a8ff | 565 | |
| bogdanm | 0:9b334a45a8ff | 566 | /** |
| bogdanm | 0:9b334a45a8ff | 567 | * @brief Get the DMA Channel pending flags. |
| bogdanm | 0:9b334a45a8ff | 568 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 569 | * @param __FLAG__: Get the specified flag. |
| bogdanm | 0:9b334a45a8ff | 570 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 571 | * @arg DMA_FLAG_TCx: Transfer complete flag |
| bogdanm | 0:9b334a45a8ff | 572 | * @arg DMA_FLAG_HTx: Half transfer complete flag |
| bogdanm | 0:9b334a45a8ff | 573 | * @arg DMA_FLAG_TEx: Transfer error flag |
| bogdanm | 0:9b334a45a8ff | 574 | * Where x can be 1_7 to select the DMA Channel flag. |
| bogdanm | 0:9b334a45a8ff | 575 | * @retval The state of FLAG (SET or RESET). |
| bogdanm | 0:9b334a45a8ff | 576 | */ |
| bogdanm | 0:9b334a45a8ff | 577 | |
| bogdanm | 0:9b334a45a8ff | 578 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) |
| bogdanm | 0:9b334a45a8ff | 579 | |
| bogdanm | 0:9b334a45a8ff | 580 | /** |
| bogdanm | 0:9b334a45a8ff | 581 | * @brief Clears the DMA Channel pending flags. |
| bogdanm | 0:9b334a45a8ff | 582 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 583 | * @param __FLAG__: specifies the flag to clear. |
| bogdanm | 0:9b334a45a8ff | 584 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 585 | * @arg DMA_FLAG_TCx: Transfer complete flag |
| bogdanm | 0:9b334a45a8ff | 586 | * @arg DMA_FLAG_HTx: Half transfer complete flag |
| bogdanm | 0:9b334a45a8ff | 587 | * @arg DMA_FLAG_TEx: Transfer error flag |
| bogdanm | 0:9b334a45a8ff | 588 | * Where x can be 1_7 to select the DMA Channel flag. |
| bogdanm | 0:9b334a45a8ff | 589 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 590 | */ |
| bogdanm | 0:9b334a45a8ff | 591 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) |
| bogdanm | 0:9b334a45a8ff | 592 | |
| bogdanm | 0:9b334a45a8ff | 593 | #elif defined(STM32F091xC) || defined(STM32F098xx) |
| bogdanm | 0:9b334a45a8ff | 594 | /** |
| bogdanm | 0:9b334a45a8ff | 595 | * @brief Returns the current DMA Channel transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 596 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 597 | * @retval The specified transfer complete flag index. |
| bogdanm | 0:9b334a45a8ff | 598 | */ |
| bogdanm | 0:9b334a45a8ff | 599 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
| bogdanm | 0:9b334a45a8ff | 600 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ |
| bogdanm | 0:9b334a45a8ff | 601 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ |
| bogdanm | 0:9b334a45a8ff | 602 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ |
| bogdanm | 0:9b334a45a8ff | 603 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ |
| bogdanm | 0:9b334a45a8ff | 604 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ |
| bogdanm | 0:9b334a45a8ff | 605 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ |
| bogdanm | 0:9b334a45a8ff | 606 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ |
| bogdanm | 0:9b334a45a8ff | 607 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ |
| bogdanm | 0:9b334a45a8ff | 608 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ |
| bogdanm | 0:9b334a45a8ff | 609 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ |
| bogdanm | 0:9b334a45a8ff | 610 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ |
| bogdanm | 0:9b334a45a8ff | 611 | DMA_FLAG_TC5) |
| bogdanm | 0:9b334a45a8ff | 612 | |
| bogdanm | 0:9b334a45a8ff | 613 | /** |
| bogdanm | 0:9b334a45a8ff | 614 | * @brief Returns the current DMA Channel half transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 615 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 616 | * @retval The specified half transfer complete flag index. |
| bogdanm | 0:9b334a45a8ff | 617 | */ |
| bogdanm | 0:9b334a45a8ff | 618 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
| bogdanm | 0:9b334a45a8ff | 619 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ |
| bogdanm | 0:9b334a45a8ff | 620 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ |
| bogdanm | 0:9b334a45a8ff | 621 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ |
| bogdanm | 0:9b334a45a8ff | 622 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ |
| bogdanm | 0:9b334a45a8ff | 623 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ |
| bogdanm | 0:9b334a45a8ff | 624 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ |
| bogdanm | 0:9b334a45a8ff | 625 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ |
| bogdanm | 0:9b334a45a8ff | 626 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ |
| bogdanm | 0:9b334a45a8ff | 627 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ |
| bogdanm | 0:9b334a45a8ff | 628 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ |
| bogdanm | 0:9b334a45a8ff | 629 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ |
| bogdanm | 0:9b334a45a8ff | 630 | DMA_FLAG_HT5) |
| bogdanm | 0:9b334a45a8ff | 631 | |
| bogdanm | 0:9b334a45a8ff | 632 | /** |
| bogdanm | 0:9b334a45a8ff | 633 | * @brief Returns the current DMA Channel transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 634 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 635 | * @retval The specified transfer error flag index. |
| bogdanm | 0:9b334a45a8ff | 636 | */ |
| bogdanm | 0:9b334a45a8ff | 637 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
| bogdanm | 0:9b334a45a8ff | 638 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ |
| bogdanm | 0:9b334a45a8ff | 639 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ |
| bogdanm | 0:9b334a45a8ff | 640 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ |
| bogdanm | 0:9b334a45a8ff | 641 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ |
| bogdanm | 0:9b334a45a8ff | 642 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ |
| bogdanm | 0:9b334a45a8ff | 643 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ |
| bogdanm | 0:9b334a45a8ff | 644 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ |
| bogdanm | 0:9b334a45a8ff | 645 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ |
| bogdanm | 0:9b334a45a8ff | 646 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ |
| bogdanm | 0:9b334a45a8ff | 647 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ |
| bogdanm | 0:9b334a45a8ff | 648 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ |
| bogdanm | 0:9b334a45a8ff | 649 | DMA_FLAG_TE5) |
| bogdanm | 0:9b334a45a8ff | 650 | |
| bogdanm | 0:9b334a45a8ff | 651 | /** |
| bogdanm | 0:9b334a45a8ff | 652 | * @brief Get the DMA Channel pending flags. |
| bogdanm | 0:9b334a45a8ff | 653 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 654 | * @param __FLAG__: Get the specified flag. |
| bogdanm | 0:9b334a45a8ff | 655 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 656 | * @arg DMA_FLAG_TCx: Transfer complete flag |
| bogdanm | 0:9b334a45a8ff | 657 | * @arg DMA_FLAG_HTx: Half transfer complete flag |
| bogdanm | 0:9b334a45a8ff | 658 | * @arg DMA_FLAG_TEx: Transfer error flag |
| bogdanm | 0:9b334a45a8ff | 659 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. |
| bogdanm | 0:9b334a45a8ff | 660 | * @retval The state of FLAG (SET or RESET). |
| bogdanm | 0:9b334a45a8ff | 661 | */ |
| bogdanm | 0:9b334a45a8ff | 662 | |
| bogdanm | 0:9b334a45a8ff | 663 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ |
| bogdanm | 0:9b334a45a8ff | 664 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\ |
| bogdanm | 0:9b334a45a8ff | 665 | (DMA1->ISR & (__FLAG__))) |
| bogdanm | 0:9b334a45a8ff | 666 | |
| bogdanm | 0:9b334a45a8ff | 667 | /** |
| bogdanm | 0:9b334a45a8ff | 668 | * @brief Clears the DMA Channel pending flags. |
| bogdanm | 0:9b334a45a8ff | 669 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 670 | * @param __FLAG__: specifies the flag to clear. |
| bogdanm | 0:9b334a45a8ff | 671 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 672 | * @arg DMA_FLAG_TCx: Transfer complete flag |
| bogdanm | 0:9b334a45a8ff | 673 | * @arg DMA_FLAG_HTx: Half transfer complete flag |
| bogdanm | 0:9b334a45a8ff | 674 | * @arg DMA_FLAG_TEx: Transfer error flag |
| bogdanm | 0:9b334a45a8ff | 675 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. |
| bogdanm | 0:9b334a45a8ff | 676 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 677 | */ |
| bogdanm | 0:9b334a45a8ff | 678 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
| bogdanm | 0:9b334a45a8ff | 679 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\ |
| bogdanm | 0:9b334a45a8ff | 680 | (DMA1->IFCR = (__FLAG__))) |
| bogdanm | 0:9b334a45a8ff | 681 | |
| bogdanm | 0:9b334a45a8ff | 682 | #else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */ |
| bogdanm | 0:9b334a45a8ff | 683 | /** |
| bogdanm | 0:9b334a45a8ff | 684 | * @brief Returns the current DMA Channel transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 685 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 686 | * @retval The specified transfer complete flag index. |
| bogdanm | 0:9b334a45a8ff | 687 | */ |
| bogdanm | 0:9b334a45a8ff | 688 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
| bogdanm | 0:9b334a45a8ff | 689 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ |
| bogdanm | 0:9b334a45a8ff | 690 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ |
| bogdanm | 0:9b334a45a8ff | 691 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ |
| bogdanm | 0:9b334a45a8ff | 692 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ |
| bogdanm | 0:9b334a45a8ff | 693 | DMA_FLAG_TC5) |
| bogdanm | 0:9b334a45a8ff | 694 | |
| bogdanm | 0:9b334a45a8ff | 695 | /** |
| bogdanm | 0:9b334a45a8ff | 696 | * @brief Returns the current DMA Channel half transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 697 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 698 | * @retval The specified half transfer complete flag index. |
| bogdanm | 0:9b334a45a8ff | 699 | */ |
| bogdanm | 0:9b334a45a8ff | 700 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
| bogdanm | 0:9b334a45a8ff | 701 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ |
| bogdanm | 0:9b334a45a8ff | 702 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ |
| bogdanm | 0:9b334a45a8ff | 703 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ |
| bogdanm | 0:9b334a45a8ff | 704 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ |
| bogdanm | 0:9b334a45a8ff | 705 | DMA_FLAG_HT5) |
| bogdanm | 0:9b334a45a8ff | 706 | |
| bogdanm | 0:9b334a45a8ff | 707 | /** |
| bogdanm | 0:9b334a45a8ff | 708 | * @brief Returns the current DMA Channel transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 709 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 710 | * @retval The specified transfer error flag index. |
| bogdanm | 0:9b334a45a8ff | 711 | */ |
| bogdanm | 0:9b334a45a8ff | 712 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
| bogdanm | 0:9b334a45a8ff | 713 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ |
| bogdanm | 0:9b334a45a8ff | 714 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ |
| bogdanm | 0:9b334a45a8ff | 715 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ |
| bogdanm | 0:9b334a45a8ff | 716 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ |
| bogdanm | 0:9b334a45a8ff | 717 | DMA_FLAG_TE5) |
| bogdanm | 0:9b334a45a8ff | 718 | |
| bogdanm | 0:9b334a45a8ff | 719 | /** |
| bogdanm | 0:9b334a45a8ff | 720 | * @brief Get the DMA Channel pending flags. |
| bogdanm | 0:9b334a45a8ff | 721 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 722 | * @param __FLAG__: Get the specified flag. |
| bogdanm | 0:9b334a45a8ff | 723 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 724 | * @arg DMA_FLAG_TCx: Transfer complete flag |
| bogdanm | 0:9b334a45a8ff | 725 | * @arg DMA_FLAG_HTx: Half transfer complete flag |
| bogdanm | 0:9b334a45a8ff | 726 | * @arg DMA_FLAG_TEx: Transfer error flag |
| bogdanm | 0:9b334a45a8ff | 727 | * Where x can be 1_5 to select the DMA Channel flag. |
| bogdanm | 0:9b334a45a8ff | 728 | * @retval The state of FLAG (SET or RESET). |
| bogdanm | 0:9b334a45a8ff | 729 | */ |
| bogdanm | 0:9b334a45a8ff | 730 | |
| bogdanm | 0:9b334a45a8ff | 731 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) |
| bogdanm | 0:9b334a45a8ff | 732 | |
| bogdanm | 0:9b334a45a8ff | 733 | /** |
| bogdanm | 0:9b334a45a8ff | 734 | * @brief Clears the DMA Channel pending flags. |
| bogdanm | 0:9b334a45a8ff | 735 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 736 | * @param __FLAG__: specifies the flag to clear. |
| bogdanm | 0:9b334a45a8ff | 737 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 738 | * @arg DMA_FLAG_TCx: Transfer complete flag |
| bogdanm | 0:9b334a45a8ff | 739 | * @arg DMA_FLAG_HTx: Half transfer complete flag |
| bogdanm | 0:9b334a45a8ff | 740 | * @arg DMA_FLAG_TEx: Transfer error flag |
| bogdanm | 0:9b334a45a8ff | 741 | * Where x can be 1_5 to select the DMA Channel flag. |
| bogdanm | 0:9b334a45a8ff | 742 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 743 | */ |
| bogdanm | 0:9b334a45a8ff | 744 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) |
| bogdanm | 0:9b334a45a8ff | 745 | |
| bogdanm | 0:9b334a45a8ff | 746 | #endif |
| bogdanm | 0:9b334a45a8ff | 747 | |
| bogdanm | 0:9b334a45a8ff | 748 | |
| bogdanm | 0:9b334a45a8ff | 749 | #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
| bogdanm | 0:9b334a45a8ff | 750 | #define __HAL_DMA1_REMAP(__REQUEST__) \ |
| bogdanm | 0:9b334a45a8ff | 751 | do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__)); \ |
| bogdanm | 0:9b334a45a8ff | 752 | DMA1->CSELR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \ |
| bogdanm | 0:9b334a45a8ff | 753 | DMA1->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \ |
| bogdanm | 0:9b334a45a8ff | 754 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 755 | |
| bogdanm | 0:9b334a45a8ff | 756 | #if defined(STM32F091xC) || defined(STM32F098xx) |
| bogdanm | 0:9b334a45a8ff | 757 | #define __HAL_DMA2_REMAP(__REQUEST__) \ |
| bogdanm | 0:9b334a45a8ff | 758 | do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__)); \ |
| bogdanm | 0:9b334a45a8ff | 759 | DMA2->CSELR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \ |
| bogdanm | 0:9b334a45a8ff | 760 | DMA2->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \ |
| bogdanm | 0:9b334a45a8ff | 761 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 762 | #endif /* STM32F091xC || STM32F098xx */ |
| bogdanm | 0:9b334a45a8ff | 763 | |
| bogdanm | 0:9b334a45a8ff | 764 | #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ |
| bogdanm | 0:9b334a45a8ff | 765 | |
| bogdanm | 0:9b334a45a8ff | 766 | /** |
| bogdanm | 0:9b334a45a8ff | 767 | * @} |
| bogdanm | 0:9b334a45a8ff | 768 | */ |
| bogdanm | 0:9b334a45a8ff | 769 | |
| bogdanm | 0:9b334a45a8ff | 770 | /** |
| bogdanm | 0:9b334a45a8ff | 771 | * @} |
| bogdanm | 0:9b334a45a8ff | 772 | */ |
| bogdanm | 0:9b334a45a8ff | 773 | |
| bogdanm | 0:9b334a45a8ff | 774 | /** |
| bogdanm | 0:9b334a45a8ff | 775 | * @} |
| bogdanm | 0:9b334a45a8ff | 776 | */ |
| bogdanm | 0:9b334a45a8ff | 777 | |
| bogdanm | 0:9b334a45a8ff | 778 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 779 | } |
| bogdanm | 0:9b334a45a8ff | 780 | #endif |
| bogdanm | 0:9b334a45a8ff | 781 | |
| bogdanm | 0:9b334a45a8ff | 782 | #endif /* __STM32F0xx_HAL_DMA_EX_H */ |
| bogdanm | 0:9b334a45a8ff | 783 | |
| bogdanm | 0:9b334a45a8ff | 784 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |