registerArrays.h

00001 const uint8_t initialize[][2] = {
00002     { 0x7F, 0x00 }, // switch to bank0, not allowed to perform SPIWriteRead
00003     { 0x05, 0xA8 }, // sleep mode disabled
00004     { 0x09, 0x5A }, // disable write protect
00005     { 0x51, 0x06 }, // set LD current source to 6
00006     { 0x0D, 0x1F }, // CPI resolution setting for X-direction
00007     { 0x0E, 0x1F }, // CPI resolution setting for Y-direction
00008     { 0x07, 0x00 },
00009     { 0x1B, 0x42 },
00010     { 0x2E, 0x40 },
00011     { 0x32, 0x40 },
00012     { 0x33, 0x02 },
00013     { 0x34, 0x00 },
00014     { 0x36, 0xE0 },
00015     { 0x38, 0xA0 },
00016     { 0x39, 0x01 },
00017     { 0x3E, 0x14 },
00018     { 0x44, 0x02 },
00019     { 0x4A, 0xE0 },
00020     { 0x4F, 0x02 },
00021     { 0x52, 0x0D }, // Turn off internal VDDA
00022     { 0x57, 0x03 },
00023     { 0x59, 0x03 },
00024     { 0x5B, 0x03 },
00025     { 0x5C, 0xFF },
00026     
00027     { 0x7F, 0x01 }, // switch to bank1, not allowed to perform SPIWriteRead
00028     { 0x00, 0x25 },
00029     { 0x07, 0x78 },
00030     { 0x20, 0x00 },
00031     { 0x21, 0x40 },
00032     { 0x23, 0x00 },
00033     { 0x2F, 0x64 },
00034     { 0x37, 0x30 },
00035     { 0x3B, 0x64 },
00036     { 0x43, 0x0A },
00037     { 0x59, 0x01 },
00038     { 0x5A, 0x01 },
00039     { 0x5C, 0x04 },
00040     { 0x5E, 0x04 },
00041     
00042     { 0x7F, 0x02 }, // switch to bank2, not allowed to perform SPIWriteRead
00043     { 0x51, 0x02 },
00044     
00045     { 0x7F, 0x03 }, // switch to bank3, not allowed to perform SPIWriteRead
00046     { 0x05, 0x0C },
00047     { 0x06, 0x0C },
00048     { 0x07, 0x0C },
00049     { 0x08, 0x0C },
00050     
00051     { 0x7F, 0x04 }, // switch to bank4, not allowed to perform SPIWriteRead
00052     { 0x05, 0x01 },
00053     { 0x53, 0x08 },
00054     
00055     { 0x7F, 0x05 }, // switch to bank5, not allowed to perform SPIWriteRead
00056     { 0x00, 0x02 },
00057     { 0x09, 0x01 },
00058     { 0x0A, 0x1C },
00059     { 0x0B, 0x24 },
00060     { 0x0C, 0x1C },
00061     { 0x0D, 0x24 },
00062     { 0x12, 0x08 },
00063     { 0x14, 0x02 },
00064     { 0x16, 0x02 },
00065     { 0x18, 0x1C },
00066     { 0x19, 0x24 },
00067     { 0x1A, 0x1C },
00068     { 0x1B, 0x24 },
00069     { 0x20, 0x08 },
00070     { 0x22, 0x02 },
00071     { 0x24, 0x02 },
00072     { 0x26, 0x88 },
00073     { 0x2F, 0x7C },
00074     { 0x30, 0x07 },
00075     { 0x3D, 0x00 },
00076     { 0x3E, 0x98 },
00077     
00078     { 0x7F, 0x06 }, // switch to bank6, not allowed to perform SPIWriteRead
00079     { 0x34, 0x03 },
00080     
00081     { 0x7F, 0x07 }, // switch to bank7, not allowed to perform SPIWriteRead
00082     { 0x00, 0x01 },
00083     { 0x02, 0xC4 },
00084     { 0x03, 0x13 },
00085     { 0x06, 0x0C },
00086     { 0x0F, 0x0A },
00087     { 0x14, 0x02 },
00088     { 0x35, 0x39 },
00089     { 0x36, 0x3F },
00090     { 0x46, 0x03 },
00091     { 0x47, 0x0F },
00092     { 0x4B, 0x97 },
00093     
00094     { 0x7F, 0x00 }, // switch to bank0, not allowed to perform SPIWriteRead
00095     { 0x09, 0x00 }, // enable write protect
00096 };
00097 #define initialize_size (sizeof(initialize)/sizeof(initialize[0]))