Orefatoi / Mbed 2 deprecated test_afLib13_uart_180423

afLib 1.3 which is supporting both SPI and UART

Dependencies:   vt100 mbed afLib_1_3

edge_utils/edge_reset_mgr.cpp@0:87662653a3c6, 2018-04-23 (annotated)

Committer:
Rhyme
Date:
Mon Apr 23 06:15:26 2018 +0000
Revision:
0:87662653a3c6
First UART working version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Rhyme 0:87662653a3c6 1 #include "mbed.h"
Rhyme 0:87662653a3c6 2 #include "edge_mgr.h"
Rhyme 0:87662653a3c6 3 #include "edge_reset_mgr.h"
Rhyme 0:87662653a3c6 4
Rhyme 0:87662653a3c6 5 /**
Rhyme 0:87662653a3c6 6 * System Reset Status Register 0 (RCM_SRS0) 0x4007_F000
Rhyme 0:87662653a3c6 7 *
Rhyme 0:87662653a3c6 8 * bit[7] : POR Power-On Reset
Rhyme 0:87662653a3c6 9 * bit[6] : PIN External Reset Pin
Rhyme 0:87662653a3c6 10 * bit[5] : WDOG Watchdog
Rhyme 0:87662653a3c6 11 * bit[4] : (Reserved)
Rhyme 0:87662653a3c6 12 * bit[3] : LOL Loss-of-Lock Reset
Rhyme 0:87662653a3c6 13 * bit[2] : LOC Loss-of-Clock Reset
Rhyme 0:87662653a3c6 14 * bit[1] : LVD Low-Voltage Detect Reset
Rhyme 0:87662653a3c6 15 * bit[0] : WAKEUP Low Leakage Wakeup Reset
Rhyme 0:87662653a3c6 16 */
Rhyme 0:87662653a3c6 17 #define REG_RCM_SRS0 (uint8_t *)0x4007F000
Rhyme 0:87662653a3c6 18 #define POR_RESET_BIT 0x80
Rhyme 0:87662653a3c6 19 #define PIN_RESET_BIT 0x40
Rhyme 0:87662653a3c6 20 #define WDG_RESET_BIT 0x20
Rhyme 0:87662653a3c6 21 #define LOL_RESET_BIT 0x08
Rhyme 0:87662653a3c6 22 #define LOC_RESET_BIT 0x04
Rhyme 0:87662653a3c6 23 #define LVD_RESET_BIT 0x02
Rhyme 0:87662653a3c6 24 #define WUP_RESET_BIT 0x01
Rhyme 0:87662653a3c6 25
Rhyme 0:87662653a3c6 26 /**
Rhyme 0:87662653a3c6 27 * System Reset Status Register 1 (RCM_SRS1) 0x4007_F001
Rhyme 0:87662653a3c6 28 *
Rhyme 0:87662653a3c6 29 * bit[7:6] (Reserved)
Rhyme 0:87662653a3c6 30 * bit[5] : SACKERR Stop Mode Acknowledge Error Reset
Rhyme 0:87662653a3c6 31 * bit[4] : (Reserved)
Rhyme 0:87662653a3c6 32 * bit[3] : MDM_AP MDM-AP System Reset Request
Rhyme 0:87662653a3c6 33 * bit[2] : SW Software Reset
Rhyme 0:87662653a3c6 34 * bit[1] : LOCKUP Core Lockup
Rhyme 0:87662653a3c6 35 * bit[0] : (Reserved)
Rhyme 0:87662653a3c6 36 */
Rhyme 0:87662653a3c6 37 #define REG_RCM_SRS1 (uint8_t *)0x4007F001
Rhyme 0:87662653a3c6 38 #define SACK_RESET_BIT 0x20
Rhyme 0:87662653a3c6 39 #define MDM_RESET_BIT 0x08
Rhyme 0:87662653a3c6 40 #define SW_RESET_BIT 0x04
Rhyme 0:87662653a3c6 41 #define LOCKUP_RESET_BIT 0x02
Rhyme 0:87662653a3c6 42
Rhyme 0:87662653a3c6 43 #define IDX_POR_RESET 0
Rhyme 0:87662653a3c6 44 #define IDX_PIN_RESET 1
Rhyme 0:87662653a3c6 45 #define IDX_WDG_RESET 2
Rhyme 0:87662653a3c6 46 #define IDX_LOL_RESET 3
Rhyme 0:87662653a3c6 47 #define IDX_LOC_RESET 4
Rhyme 0:87662653a3c6 48 #define IDX_LVD_RESET 5
Rhyme 0:87662653a3c6 49 #define IDX_WUP_RESET 6
Rhyme 0:87662653a3c6 50 #define IDX_SACK_RESET 7
Rhyme 0:87662653a3c6 51 #define IDX_MDM_RESET 8
Rhyme 0:87662653a3c6 52 #define IDX_SW_RESET 9
Rhyme 0:87662653a3c6 53 #define IDX_LOCKUP_RESET 10
Rhyme 0:87662653a3c6 54
Rhyme 0:87662653a3c6 55 const char *reset_reason[] = {
Rhyme 0:87662653a3c6 56 "Power On Reset",
Rhyme 0:87662653a3c6 57 "Reset Pin Asserted",
Rhyme 0:87662653a3c6 58 "Watch Dog Reset",
Rhyme 0:87662653a3c6 59 "Loss of Lock Reset",
Rhyme 0:87662653a3c6 60 "Loss of Clock Reset",
Rhyme 0:87662653a3c6 61 "Low Voltage Detect Reset",
Rhyme 0:87662653a3c6 62 "Low Leakage Wakeup Reset",
Rhyme 0:87662653a3c6 63 "Stop Mode Acknowledge Error Reset",
Rhyme 0:87662653a3c6 64 "MDM-AP System Reset Request",
Rhyme 0:87662653a3c6 65 "Software Reset",
Rhyme 0:87662653a3c6 66 "Core Lockup Reset",
Rhyme 0:87662653a3c6 67 0
Rhyme 0:87662653a3c6 68 } ;
Rhyme 0:87662653a3c6 69
Rhyme 0:87662653a3c6 70 void print_reset_reason(void)
Rhyme 0:87662653a3c6 71 {
Rhyme 0:87662653a3c6 72 extern char *reset_reason_str ;
Rhyme 0:87662653a3c6 73 int idx = 0 ;
Rhyme 0:87662653a3c6 74 uint8_t *data = REG_RCM_SRS0 ;
Rhyme 0:87662653a3c6 75 if (*data & POR_RESET_BIT) {
Rhyme 0:87662653a3c6 76 idx = IDX_POR_RESET ;
Rhyme 0:87662653a3c6 77 }
Rhyme 0:87662653a3c6 78 if (*data & PIN_RESET_BIT) {
Rhyme 0:87662653a3c6 79 idx = IDX_PIN_RESET ;
Rhyme 0:87662653a3c6 80 }
Rhyme 0:87662653a3c6 81 if (*data & WDG_RESET_BIT) {
Rhyme 0:87662653a3c6 82 idx = IDX_WDG_RESET ;
Rhyme 0:87662653a3c6 83 }
Rhyme 0:87662653a3c6 84 if (*data & LOL_RESET_BIT) {
Rhyme 0:87662653a3c6 85 idx = IDX_LOL_RESET ;
Rhyme 0:87662653a3c6 86 }
Rhyme 0:87662653a3c6 87 if (*data & LVD_RESET_BIT) {
Rhyme 0:87662653a3c6 88 idx = IDX_LVD_RESET ;
Rhyme 0:87662653a3c6 89 }
Rhyme 0:87662653a3c6 90 if (*data & LOC_RESET_BIT) {
Rhyme 0:87662653a3c6 91 idx = IDX_LOC_RESET ;
Rhyme 0:87662653a3c6 92 }
Rhyme 0:87662653a3c6 93 if (*data & WUP_RESET_BIT) {
Rhyme 0:87662653a3c6 94 idx = IDX_WUP_RESET ;
Rhyme 0:87662653a3c6 95 }
Rhyme 0:87662653a3c6 96 data = REG_RCM_SRS1 ;
Rhyme 0:87662653a3c6 97 if (*data & SACK_RESET_BIT) {
Rhyme 0:87662653a3c6 98 idx = IDX_SACK_RESET ;
Rhyme 0:87662653a3c6 99 }
Rhyme 0:87662653a3c6 100 if (*data & MDM_RESET_BIT) {
Rhyme 0:87662653a3c6 101 idx = IDX_MDM_RESET ;
Rhyme 0:87662653a3c6 102 }
Rhyme 0:87662653a3c6 103 if (*data & SW_RESET_BIT) {
Rhyme 0:87662653a3c6 104 idx = IDX_SW_RESET ;
Rhyme 0:87662653a3c6 105 }
Rhyme 0:87662653a3c6 106 if (*data & LOCKUP_RESET_BIT) {
Rhyme 0:87662653a3c6 107 idx = IDX_LOCKUP_RESET ;
Rhyme 0:87662653a3c6 108 }
Rhyme 0:87662653a3c6 109 tty->printf("%s\n", reset_reason[idx]) ;
Rhyme 0:87662653a3c6 110 reset_reason_str = (char *)reset_reason[idx] ;
Rhyme 0:87662653a3c6 111 }
Rhyme 0:87662653a3c6 112
Rhyme 0:87662653a3c6 113 /**
Rhyme 0:87662653a3c6 114 * Software Reset
Rhyme 0:87662653a3c6 115 *
Rhyme 0:87662653a3c6 116 * From Cortex-M0 Devices Generic User Guide
Rhyme 0:87662653a3c6 117 * 4.3.4 Application Interrupt and Reset Control Register
Rhyme 0:87662653a3c6 118 *
Rhyme 0:87662653a3c6 119 * Bit[31:16] : VECTCKEY
Rhyme 0:87662653a3c6 120 * Bit[15] : ENDIANESS
Rhyme 0:87662653a3c6 121 * Bit[14:3] : (Reserved)
Rhyme 0:87662653a3c6 122 * Bit[2] : SYSRESETREQ
Rhyme 0:87662653a3c6 123 * Bit[1] : VECTCLRACTIVE (reserved for debug use)
Rhyme 0:87662653a3c6 124 * Bit[0] : (Reserved)
Rhyme 0:87662653a3c6 125 *
Rhyme 0:87662653a3c6 126 * Note: To trigger software reset, both VECTKEY=0x05FA and SYSRESETREQ
Rhyme 0:87662653a3c6 127 * must be written at once, therefore the value will be
Rhyme 0:87662653a3c6 128 * 0x05FA0004
Rhyme 0:87662653a3c6 129 */
Rhyme 0:87662653a3c6 130
Rhyme 0:87662653a3c6 131 void software_reset(void)
Rhyme 0:87662653a3c6 132 {
Rhyme 0:87662653a3c6 133 SCB->AIRCR = 0x05FA0004 ;
Rhyme 0:87662653a3c6 134 }
Rhyme 0:87662653a3c6 135
Rhyme 0:87662653a3c6 136 /**
Rhyme 0:87662653a3c6 137 * reset_watch_dog
Rhyme 0:87662653a3c6 138 * reset the watch dog counter
Rhyme 0:87662653a3c6 139 * this function must be called within the limit (1sec)
Rhyme 0:87662653a3c6 140 */
Rhyme 0:87662653a3c6 141
Rhyme 0:87662653a3c6 142 void reset_watch_dog(void)
Rhyme 0:87662653a3c6 143 {
Rhyme 0:87662653a3c6 144 SIM->SRVCOP = (uint32_t)0x55u;
Rhyme 0:87662653a3c6 145 SIM->SRVCOP = (uint32_t)0xAAu;
Rhyme 0:87662653a3c6 146 }