Orefatoi / WakeUp

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Dependencies:   LPC1114_WakeInterruptIn

Fork of WakeUp by Erik -

Device/WakeUp_STM_RTC.cpp@17:49d9e3a3e904, 2015-04-22 (annotated)

Committer:
Sissors
Date:
Wed Apr 22 20:36:13 2015 +0000
Revision:
17:49d9e3a3e904
Parent:
15:b2a710aca356
Child:
20:68f2ee917691
Keep backup power domain always enabled for STM since the mbed library does not like it (anymore) when I disable it again.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sissors 9:29bdf5fed21a 1 #ifdef TARGET_STM
Sissors 9:29bdf5fed21a 2
Sissors 9:29bdf5fed21a 3 #include "WakeUp.h"
Sissors 9:29bdf5fed21a 4 #include "rtc_api.h"
Sissors 9:29bdf5fed21a 5
Sissors 9:29bdf5fed21a 6 #define BYTE2BCD(byte) ((byte % 10) | ((byte / 10) << 4))
Sissors 9:29bdf5fed21a 7 #define EXTI_RTC_LINE (1 << 17)
Sissors 9:29bdf5fed21a 8
Sissors 9:29bdf5fed21a 9 //Most things are pretty similar between the different STM targets.
Sissors 9:29bdf5fed21a 10 //Only the IRQ number the alarm is connected to differs. Any errors
Sissors 9:29bdf5fed21a 11 //with RTC_IRQn/RTC_Alarm_IRQn in them are related to this
Sissors 15:b2a710aca356 12 #if defined(TARGET_M4) || defined(TARGET_M3)
Sissors 9:29bdf5fed21a 13 #define RTC_IRQ RTC_Alarm_IRQn
Sissors 9:29bdf5fed21a 14 #else
Sissors 9:29bdf5fed21a 15 #define RTC_IRQ RTC_IRQn
Sissors 9:29bdf5fed21a 16 #endif
Sissors 9:29bdf5fed21a 17
Sissors 17:49d9e3a3e904 18 //Disabling the Backup Powerdomain does not seem to work nicely anymore if you want to use other RTC functions afterwards.
Sissors 17:49d9e3a3e904 19 //For now I have disabled it in code, if you find WakeUp increases your powerconsumption, try enabling it again (code is still there, just commented)
Sissors 17:49d9e3a3e904 20
Sissors 9:29bdf5fed21a 21 FunctionPointer WakeUp::callback;
Sissors 9:29bdf5fed21a 22
Sissors 9:29bdf5fed21a 23 void WakeUp::set_ms(uint32_t ms)
Sissors 9:29bdf5fed21a 24 {
Sissors 9:29bdf5fed21a 25 if (!rtc_isenabled()) { //Make sure RTC is running
Sissors 9:29bdf5fed21a 26 rtc_init();
Sissors 9:29bdf5fed21a 27 wait_us(250); //The f401 seems to want a delay after init
Sissors 9:29bdf5fed21a 28 }
Sissors 9:29bdf5fed21a 29
Sissors 17:49d9e3a3e904 30 //PWR->CR |= PWR_CR_DBP; //Enable power domain
Sissors 9:29bdf5fed21a 31 RTC->WPR = 0xCA; //Disable RTC write protection
Sissors 9:29bdf5fed21a 32 RTC->WPR = 0x53;
Sissors 9:29bdf5fed21a 33
Sissors 9:29bdf5fed21a 34 //Alarm must be disabled to change anything
Sissors 9:29bdf5fed21a 35 RTC->CR &= ~RTC_CR_ALRAE;
Sissors 9:29bdf5fed21a 36 while(!(RTC->ISR & RTC_ISR_ALRAWF));
Sissors 9:29bdf5fed21a 37
Sissors 9:29bdf5fed21a 38 if (ms == 0) { //Just disable alarm
Sissors 17:49d9e3a3e904 39 //PWR->CR &= ~PWR_CR_DBP; //Disable power domain
Sissors 9:29bdf5fed21a 40 RTC->WPR = 0xFF; //Enable RTC write protection
Sissors 9:29bdf5fed21a 41 return;
Sissors 9:29bdf5fed21a 42 }
Sissors 9:29bdf5fed21a 43
Sissors 9:29bdf5fed21a 44 //RTC prescaler + calculate how many sub-seconds should be added
Sissors 9:29bdf5fed21a 45 uint32_t prescaler = (RTC->PRER & 0x7FFF) + 1;
Sissors 9:29bdf5fed21a 46 uint32_t subsecsadd = ((ms % 1000) * prescaler) / 1000;
Sissors 9:29bdf5fed21a 47
Sissors 9:29bdf5fed21a 48 if ((ms < 1000) && (subsecsadd < 2))
Sissors 9:29bdf5fed21a 49 subsecsadd = 2; //At least 2 subsecs delay to be sure interrupt is called
Sissors 9:29bdf5fed21a 50
Sissors 9:29bdf5fed21a 51 __disable_irq(); //At this point we don't want IRQs anymore
Sissors 9:29bdf5fed21a 52
Sissors 9:29bdf5fed21a 53 //Get current time
Sissors 9:29bdf5fed21a 54 uint32_t subsecs = RTC->SSR;
Sissors 9:29bdf5fed21a 55 time_t secs = rtc_read();
Sissors 9:29bdf5fed21a 56
Sissors 9:29bdf5fed21a 57 //Calculate alarm values
Sissors 9:29bdf5fed21a 58 //Subseconds is countdown, so substract the 'added' sub-seconds and prevent underflow
Sissors 9:29bdf5fed21a 59 if (subsecs < subsecsadd) {
Sissors 9:29bdf5fed21a 60 subsecs += prescaler;
Sissors 9:29bdf5fed21a 61 secs++;
Sissors 9:29bdf5fed21a 62 }
Sissors 9:29bdf5fed21a 63 subsecs -= subsecsadd;
Sissors 9:29bdf5fed21a 64
Sissors 9:29bdf5fed21a 65 //Set seconds correctly
Sissors 9:29bdf5fed21a 66 secs += ms / 1000;
Sissors 9:29bdf5fed21a 67 struct tm *timeinfo = localtime(&secs);
Sissors 9:29bdf5fed21a 68
Sissors 9:29bdf5fed21a 69 //Enable rising edge EXTI interrupt of the RTC
Sissors 9:29bdf5fed21a 70 EXTI->IMR |= EXTI_RTC_LINE;
Sissors 9:29bdf5fed21a 71 EXTI->EMR &= ~EXTI_RTC_LINE;
Sissors 9:29bdf5fed21a 72 EXTI->RTSR |= EXTI_RTC_LINE;
Sissors 9:29bdf5fed21a 73 EXTI->FTSR &= ~EXTI_RTC_LINE;
Sissors 9:29bdf5fed21a 74
Sissors 9:29bdf5fed21a 75 //Calculate alarm register values
Sissors 9:29bdf5fed21a 76 uint32_t alarmreg = 0;
Sissors 9:29bdf5fed21a 77 alarmreg |= BYTE2BCD(timeinfo->tm_sec) << 0;
Sissors 9:29bdf5fed21a 78 alarmreg |= BYTE2BCD(timeinfo->tm_min) << 8;
Sissors 9:29bdf5fed21a 79 alarmreg |= BYTE2BCD(timeinfo->tm_hour) << 16;
Sissors 9:29bdf5fed21a 80 alarmreg |= BYTE2BCD(timeinfo->tm_mday) << 24;
Sissors 9:29bdf5fed21a 81
Sissors 9:29bdf5fed21a 82 //Enable RTC interrupt
Sissors 9:29bdf5fed21a 83 RTC->ALRMAR = alarmreg;
Sissors 9:29bdf5fed21a 84 RTC->ALRMASSR = subsecs | RTC_ALRMASSR_MASKSS; //Mask no subseconds
Sissors 9:29bdf5fed21a 85 RTC->CR |= RTC_CR_ALRAE | RTC_CR_ALRAIE; //Enable Alarm
Sissors 9:29bdf5fed21a 86
Sissors 9:29bdf5fed21a 87 RTC->WPR = 0xFF; //Enable RTC write protection
Sissors 17:49d9e3a3e904 88 //PWR->CR &= ~PWR_CR_DBP; //Disable power domain
Sissors 9:29bdf5fed21a 89
Sissors 9:29bdf5fed21a 90 __enable_irq(); //Alarm is set, so irqs can be enabled again
Sissors 9:29bdf5fed21a 91
Sissors 9:29bdf5fed21a 92 //Enable everything else
Sissors 9:29bdf5fed21a 93 NVIC_SetVector(RTC_IRQ, (uint32_t)WakeUp::irq_handler);
Sissors 9:29bdf5fed21a 94 NVIC_EnableIRQ(RTC_IRQ);
Sissors 9:29bdf5fed21a 95 }
Sissors 9:29bdf5fed21a 96
Sissors 9:29bdf5fed21a 97
Sissors 9:29bdf5fed21a 98 void WakeUp::irq_handler(void)
Sissors 9:29bdf5fed21a 99 {
Sissors 9:29bdf5fed21a 100 //Clear RTC + EXTI interrupt flags
Sissors 17:49d9e3a3e904 101 //PWR->CR |= PWR_CR_DBP; //Enable power domain
Sissors 9:29bdf5fed21a 102 RTC->ISR &= ~RTC_ISR_ALRAF;
Sissors 17:49d9e3a3e904 103 RTC->WPR = 0xCA; //Disable RTC write protection
Sissors 17:49d9e3a3e904 104 RTC->WPR = 0x53;
Sissors 17:49d9e3a3e904 105 RTC->CR &= ~RTC_CR_ALRAE;
Sissors 17:49d9e3a3e904 106 RTC->WPR = 0xFF; //Enable RTC write protection
Sissors 9:29bdf5fed21a 107 EXTI->PR = EXTI_RTC_LINE;
Sissors 17:49d9e3a3e904 108 //PWR->CR &= ~PWR_CR_DBP; //Disable power domain
Sissors 9:29bdf5fed21a 109 callback.call();
Sissors 9:29bdf5fed21a 110 }
Sissors 9:29bdf5fed21a 111
Sissors 9:29bdf5fed21a 112 void WakeUp::calibrate(void)
Sissors 9:29bdf5fed21a 113 {
Sissors 9:29bdf5fed21a 114 //RTC, we assume it is accurate enough without calibration
Sissors 9:29bdf5fed21a 115 }
Sissors 9:29bdf5fed21a 116
Sissors 9:29bdf5fed21a 117
Sissors 9:29bdf5fed21a 118 #endif