fsl_phy_mcr20a - A library implementing IEEE 802.15.4 PHY function…

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A library implementing IEEE 802.15.4 PHY functionality for the MCR20A transceiver. The PHY sublayer provides two services: the PHY data service and the PHY management service interfacing to the PHY sublayer management entity (PLME) service access point (SAP) (known as PLME-SAP). The PHY data service enables the transmission and reception of PHY protocol data units (PSDUs) over the media (radio).

Fork of fsl_phy_mcr20a by Freescale

The Freescale PHY Layer deals with the physical burst which is to be sent and/or received. It performs modulation and demodulation, transmitter and receiver switching, fragmentation, scrambling, interleaving, and error correction coding. The communication to the upper protocol layers is carried out through the Layer 1 Interface.

The PHY Layer is capable of executing the following sequences:

I (Idle)
R (Receive Sequence conditionally followed by a TxAck)
T (Transmit Sequence)
C (Standalone CCA)
CCCA (Continuous CCA)
TR (Transmit/Receive Sequence - transmit unconditionally followed by either an R or RxAck)

In addition to these sequences the PHY Layer also integrates a packet processor which determines whether the packet is MAC-compliant, and if it is, whether it is addressed to the end device. Another feature of the packet processor is Source Address Matching which can be viewed as an extension of packet filtering; however its function is very specific to its intended application (data-polling and indirect queue management by a PAN Coordinator).

Documentation

MCR20A PHY Reference Manual

PHY/PhyPacketProcessor.c@0:764779eedf2d, 2015-08-18 (annotated)

Committer:: andreikovacs
Date:: Tue Aug 18 12:41:42 2015 +0000
Revision:: 0:764779eedf2d

Initial commit

Who changed what in which revision?

User	Revision	Line number	New contents of line
andreikovacs	0:764779eedf2d	1	/*!
andreikovacs	0:764779eedf2d	2	* Copyright (c) 2015, Freescale Semiconductor, Inc.
andreikovacs	0:764779eedf2d	3	* All rights reserved.
andreikovacs	0:764779eedf2d	4	*
andreikovacs	0:764779eedf2d	5	* \file PhyPacketProcessor.c
andreikovacs	0:764779eedf2d	6	*
andreikovacs	0:764779eedf2d	7	* Redistribution and use in source and binary forms, with or without modification,
andreikovacs	0:764779eedf2d	8	* are permitted provided that the following conditions are met:
andreikovacs	0:764779eedf2d	9	*
andreikovacs	0:764779eedf2d	10	* o Redistributions of source code must retain the above copyright notice, this list
andreikovacs	0:764779eedf2d	11	* of conditions and the following disclaimer.
andreikovacs	0:764779eedf2d	12	*
andreikovacs	0:764779eedf2d	13	* o Redistributions in binary form must reproduce the above copyright notice, this
andreikovacs	0:764779eedf2d	14	* list of conditions and the following disclaimer in the documentation and/or
andreikovacs	0:764779eedf2d	15	* other materials provided with the distribution.
andreikovacs	0:764779eedf2d	16	*
andreikovacs	0:764779eedf2d	17	* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
andreikovacs	0:764779eedf2d	18	* contributors may be used to endorse or promote products derived from this
andreikovacs	0:764779eedf2d	19	* software without specific prior written permission.
andreikovacs	0:764779eedf2d	20	*
andreikovacs	0:764779eedf2d	21	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
andreikovacs	0:764779eedf2d	22	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
andreikovacs	0:764779eedf2d	23	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
andreikovacs	0:764779eedf2d	24	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
andreikovacs	0:764779eedf2d	25	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
andreikovacs	0:764779eedf2d	26	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
andreikovacs	0:764779eedf2d	27	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
andreikovacs	0:764779eedf2d	28	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
andreikovacs	0:764779eedf2d	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
andreikovacs	0:764779eedf2d	30	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
andreikovacs	0:764779eedf2d	31	*/
andreikovacs	0:764779eedf2d	32
andreikovacs	0:764779eedf2d	33
andreikovacs	0:764779eedf2d	34	/************************************************************************************
andreikovacs	0:764779eedf2d	35	*************************************************************************************
andreikovacs	0:764779eedf2d	36	* Include
andreikovacs	0:764779eedf2d	37	*************************************************************************************
andreikovacs	0:764779eedf2d	38	************************************************************************************/
andreikovacs	0:764779eedf2d	39	#include "EmbeddedTypes.h"
andreikovacs	0:764779eedf2d	40	#include "MCR20Drv.h"
andreikovacs	0:764779eedf2d	41	#include "MCR20Reg.h"
andreikovacs	0:764779eedf2d	42	#include "MCR20Overwrites.h"
andreikovacs	0:764779eedf2d	43
andreikovacs	0:764779eedf2d	44	#include "Phy.h"
andreikovacs	0:764779eedf2d	45	#include "MpmInterface.h"
andreikovacs	0:764779eedf2d	46
andreikovacs	0:764779eedf2d	47	#if 0
andreikovacs	0:764779eedf2d	48	#include "board.h"
andreikovacs	0:764779eedf2d	49	#include "fsl_os_abstraction.h"
andreikovacs	0:764779eedf2d	50	#include "fsl_gpio_driver.h"
andreikovacs	0:764779eedf2d	51
andreikovacs	0:764779eedf2d	52	extern const IRQn_Type g_portIrqId[HW_PORT_INSTANCE_COUNT];
andreikovacs	0:764779eedf2d	53	#endif
andreikovacs	0:764779eedf2d	54	/************************************************************************************
andreikovacs	0:764779eedf2d	55	*************************************************************************************
andreikovacs	0:764779eedf2d	56	* Public macros
andreikovacs	0:764779eedf2d	57	*************************************************************************************
andreikovacs	0:764779eedf2d	58	************************************************************************************/
andreikovacs	0:764779eedf2d	59
andreikovacs	0:764779eedf2d	60	// Address mode indentifiers. Used for both network and MAC interfaces
andreikovacs	0:764779eedf2d	61	#define gPhyAddrModeNoAddr_c (0)
andreikovacs	0:764779eedf2d	62	#define gPhyAddrModeInvalid_c (1)
andreikovacs	0:764779eedf2d	63	#define gPhyAddrMode16BitAddr_c (2)
andreikovacs	0:764779eedf2d	64	#define gPhyAddrMode64BitAddr_c (3)
andreikovacs	0:764779eedf2d	65
andreikovacs	0:764779eedf2d	66	#define PHY_MIN_RNG_DELAY 4
andreikovacs	0:764779eedf2d	67
andreikovacs	0:764779eedf2d	68	/************************************************************************************
andreikovacs	0:764779eedf2d	69	*************************************************************************************
andreikovacs	0:764779eedf2d	70	* Private variables
andreikovacs	0:764779eedf2d	71	*************************************************************************************
andreikovacs	0:764779eedf2d	72	************************************************************************************/
andreikovacs	0:764779eedf2d	73
andreikovacs	0:764779eedf2d	74	const uint8_t gPhyIdlePwrState = gPhyDefaultIdlePwrMode_c;
andreikovacs	0:764779eedf2d	75	const uint8_t gPhyActivePwrState = gPhyDefaultActivePwrMode_c;
andreikovacs	0:764779eedf2d	76
andreikovacs	0:764779eedf2d	77	const uint8_t gPhyIndirectQueueSize_c = 12;
andreikovacs	0:764779eedf2d	78	static uint8_t mPhyCurrentSamLvl = 12;
andreikovacs	0:764779eedf2d	79	static uint8_t mPhyPwrState = gPhyPwrIdle_c;
andreikovacs	0:764779eedf2d	80
andreikovacs	0:764779eedf2d	81	/************************************************************************************
andreikovacs	0:764779eedf2d	82	*************************************************************************************
andreikovacs	0:764779eedf2d	83	* Public Functions
andreikovacs	0:764779eedf2d	84	*************************************************************************************
andreikovacs	0:764779eedf2d	85	************************************************************************************/
andreikovacs	0:764779eedf2d	86
andreikovacs	0:764779eedf2d	87
andreikovacs	0:764779eedf2d	88	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	89	* Name: PhyGetRandomNo
andreikovacs	0:764779eedf2d	90	* Description: - This function should be called only when the Radio is idle.
andreikovacs	0:764779eedf2d	91	* The function may take a long time to run!
andreikovacs	0:764779eedf2d	92	* It is recomended to use this function only to initializa a seed at startup!
andreikovacs	0:764779eedf2d	93	* Parameters: -
andreikovacs	0:764779eedf2d	94	* Return: -
andreikovacs	0:764779eedf2d	95	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	96
andreikovacs	0:764779eedf2d	97	void PhyGetRandomNo(uint32_t *pRandomNo)
andreikovacs	0:764779eedf2d	98	{
andreikovacs	0:764779eedf2d	99	uint8_t i = 4, prevRN=0;
andreikovacs	0:764779eedf2d	100	uint8_t* ptr = (uint8_t *)pRandomNo;
andreikovacs	0:764779eedf2d	101	uint32_t startTime, endTime;
andreikovacs	0:764779eedf2d	102	uint8_t phyReg;
andreikovacs	0:764779eedf2d	103
andreikovacs	0:764779eedf2d	104	MCR20Drv_IRQ_Disable();
andreikovacs	0:764779eedf2d	105
andreikovacs	0:764779eedf2d	106	if( PhyPpGetState() )
andreikovacs	0:764779eedf2d	107	{
andreikovacs	0:764779eedf2d	108	*pRandomNo = 0;
andreikovacs	0:764779eedf2d	109	MCR20Drv_IRQ_Enable();
andreikovacs	0:764779eedf2d	110	return;
andreikovacs	0:764779eedf2d	111	}
andreikovacs	0:764779eedf2d	112
andreikovacs	0:764779eedf2d	113	while (i--)
andreikovacs	0:764779eedf2d	114	{
andreikovacs	0:764779eedf2d	115	PhyTimeReadClock(&startTime);
andreikovacs	0:764779eedf2d	116
andreikovacs	0:764779eedf2d	117	// Program a new sequence
andreikovacs	0:764779eedf2d	118	phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL1);
andreikovacs	0:764779eedf2d	119	MCR20Drv_DirectAccessSPIWrite( PHY_CTRL1, phyReg \| gRX_c);
andreikovacs	0:764779eedf2d	120
andreikovacs	0:764779eedf2d	121	// wait a variable number of symbols */
andreikovacs	0:764779eedf2d	122	do
andreikovacs	0:764779eedf2d	123	PhyTimeReadClock(&endTime);
andreikovacs	0:764779eedf2d	124	while( ((endTime - startTime) & 0x00FFFFFF) < (PHY_MIN_RNG_DELAY + (prevRN>>5)));
andreikovacs	0:764779eedf2d	125
andreikovacs	0:764779eedf2d	126	// Abort the sequence
andreikovacs	0:764779eedf2d	127	PhyAbort();
andreikovacs	0:764779eedf2d	128
andreikovacs	0:764779eedf2d	129	// Read new 8 bit random number
andreikovacs	0:764779eedf2d	130	prevRN = MCR20Drv_IndirectAccessSPIRead((uint8_t)_RNG);
andreikovacs	0:764779eedf2d	131	*ptr++ = prevRN;
andreikovacs	0:764779eedf2d	132	}
andreikovacs	0:764779eedf2d	133
andreikovacs	0:764779eedf2d	134	MCR20Drv_IRQ_Enable();
andreikovacs	0:764779eedf2d	135	}
andreikovacs	0:764779eedf2d	136
andreikovacs	0:764779eedf2d	137
andreikovacs	0:764779eedf2d	138	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	139	* Name: PhyPpSetDualPanAuto
andreikovacs	0:764779eedf2d	140	* Description: -
andreikovacs	0:764779eedf2d	141	* Parameters: -
andreikovacs	0:764779eedf2d	142	* Return: -
andreikovacs	0:764779eedf2d	143	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	144	void PhyPpSetDualPanAuto
andreikovacs	0:764779eedf2d	145	(
andreikovacs	0:764779eedf2d	146	bool_t mode
andreikovacs	0:764779eedf2d	147	)
andreikovacs	0:764779eedf2d	148	{
andreikovacs	0:764779eedf2d	149	uint8_t phyReg, phyReg2;
andreikovacs	0:764779eedf2d	150
andreikovacs	0:764779eedf2d	151	phyReg = MCR20Drv_IndirectAccessSPIRead( (uint8_t) DUAL_PAN_CTRL);
andreikovacs	0:764779eedf2d	152
andreikovacs	0:764779eedf2d	153	if( mode )
andreikovacs	0:764779eedf2d	154	{
andreikovacs	0:764779eedf2d	155	phyReg2 = phyReg \| (cDUAL_PAN_CTRL_DUAL_PAN_AUTO);
andreikovacs	0:764779eedf2d	156	}
andreikovacs	0:764779eedf2d	157	else
andreikovacs	0:764779eedf2d	158	{
andreikovacs	0:764779eedf2d	159	phyReg2 = phyReg & (~cDUAL_PAN_CTRL_DUAL_PAN_AUTO);
andreikovacs	0:764779eedf2d	160	}
andreikovacs	0:764779eedf2d	161
andreikovacs	0:764779eedf2d	162	/* Write the new value only if it has changed */
andreikovacs	0:764779eedf2d	163	if (phyReg2 != phyReg)
andreikovacs	0:764779eedf2d	164	MCR20Drv_IndirectAccessSPIWrite( (uint8_t) DUAL_PAN_CTRL, phyReg2);
andreikovacs	0:764779eedf2d	165	}
andreikovacs	0:764779eedf2d	166
andreikovacs	0:764779eedf2d	167	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	168	* Name: PhyPpGetDualPanAuto
andreikovacs	0:764779eedf2d	169	* Description: -
andreikovacs	0:764779eedf2d	170	* Parameters: -
andreikovacs	0:764779eedf2d	171	* Return: -
andreikovacs	0:764779eedf2d	172	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	173	bool_t PhyPpGetDualPanAuto
andreikovacs	0:764779eedf2d	174	(
andreikovacs	0:764779eedf2d	175	void
andreikovacs	0:764779eedf2d	176	)
andreikovacs	0:764779eedf2d	177	{
andreikovacs	0:764779eedf2d	178	uint8_t phyReg = MCR20Drv_IndirectAccessSPIRead(DUAL_PAN_CTRL);
andreikovacs	0:764779eedf2d	179	return (phyReg & cDUAL_PAN_CTRL_DUAL_PAN_AUTO) == cDUAL_PAN_CTRL_DUAL_PAN_AUTO;
andreikovacs	0:764779eedf2d	180	}
andreikovacs	0:764779eedf2d	181
andreikovacs	0:764779eedf2d	182	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	183	* Name: PhyPpSetDualPanDwell
andreikovacs	0:764779eedf2d	184	* Description: -
andreikovacs	0:764779eedf2d	185	* Parameters: -
andreikovacs	0:764779eedf2d	186	* Return: -
andreikovacs	0:764779eedf2d	187	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	188	void PhyPpSetDualPanDwell // TODO: check seq state and return phyStatus_t
andreikovacs	0:764779eedf2d	189	(
andreikovacs	0:764779eedf2d	190	uint8_t dwell
andreikovacs	0:764779eedf2d	191	)
andreikovacs	0:764779eedf2d	192	{
andreikovacs	0:764779eedf2d	193	MCR20Drv_IndirectAccessSPIWrite( (uint8_t) DUAL_PAN_DWELL, dwell);
andreikovacs	0:764779eedf2d	194	}
andreikovacs	0:764779eedf2d	195
andreikovacs	0:764779eedf2d	196	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	197	* Name: PhyPpGetDualPanDwell
andreikovacs	0:764779eedf2d	198	* Description: -
andreikovacs	0:764779eedf2d	199	* Parameters: -
andreikovacs	0:764779eedf2d	200	* Return: -
andreikovacs	0:764779eedf2d	201	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	202	uint8_t PhyPpGetDualPanDwell
andreikovacs	0:764779eedf2d	203	(
andreikovacs	0:764779eedf2d	204	void
andreikovacs	0:764779eedf2d	205	)
andreikovacs	0:764779eedf2d	206	{
andreikovacs	0:764779eedf2d	207	return MCR20Drv_IndirectAccessSPIRead( (uint8_t) DUAL_PAN_DWELL);
andreikovacs	0:764779eedf2d	208	}
andreikovacs	0:764779eedf2d	209
andreikovacs	0:764779eedf2d	210	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	211	* Name: PhyPpGetDualPanRemain
andreikovacs	0:764779eedf2d	212	* Description: -
andreikovacs	0:764779eedf2d	213	* Parameters: -
andreikovacs	0:764779eedf2d	214	* Return: - the remaining Dwell time
andreikovacs	0:764779eedf2d	215	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	216	uint8_t PhyPpGetDualPanRemain()
andreikovacs	0:764779eedf2d	217	{
andreikovacs	0:764779eedf2d	218	return (MCR20Drv_IndirectAccessSPIRead(DUAL_PAN_STS) & cDUAL_PAN_STS_DUAL_PAN_REMAIN);
andreikovacs	0:764779eedf2d	219	}
andreikovacs	0:764779eedf2d	220
andreikovacs	0:764779eedf2d	221	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	222	* Name: PhyPpSetDualPanSamLvl
andreikovacs	0:764779eedf2d	223	* Description: -
andreikovacs	0:764779eedf2d	224	* Parameters: -
andreikovacs	0:764779eedf2d	225	* Return: -
andreikovacs	0:764779eedf2d	226	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	227	void PhyPpSetDualPanSamLvl // TODO: check seq state and return phyStatus_t
andreikovacs	0:764779eedf2d	228	(
andreikovacs	0:764779eedf2d	229	uint8_t level
andreikovacs	0:764779eedf2d	230	)
andreikovacs	0:764779eedf2d	231	{
andreikovacs	0:764779eedf2d	232	uint8_t phyReg;
andreikovacs	0:764779eedf2d	233	#ifdef PHY_PARAMETERS_VALIDATION
andreikovacs	0:764779eedf2d	234	if( level > gPhyIndirectQueueSize_c )
andreikovacs	0:764779eedf2d	235	return;
andreikovacs	0:764779eedf2d	236	#endif
andreikovacs	0:764779eedf2d	237	phyReg = MCR20Drv_IndirectAccessSPIRead( (uint8_t) DUAL_PAN_CTRL);
andreikovacs	0:764779eedf2d	238
andreikovacs	0:764779eedf2d	239	phyReg &= ~cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK; // clear current lvl
andreikovacs	0:764779eedf2d	240	phyReg \|= level << cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_Shift_c; // set new lvl
andreikovacs	0:764779eedf2d	241
andreikovacs	0:764779eedf2d	242	MCR20Drv_IndirectAccessSPIWrite( (uint8_t) DUAL_PAN_CTRL, phyReg);
andreikovacs	0:764779eedf2d	243	mPhyCurrentSamLvl = level;
andreikovacs	0:764779eedf2d	244	}
andreikovacs	0:764779eedf2d	245
andreikovacs	0:764779eedf2d	246	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	247	* Name: PhyPpGetDualPanSamLvl
andreikovacs	0:764779eedf2d	248	* Description: -
andreikovacs	0:764779eedf2d	249	* Parameters: -
andreikovacs	0:764779eedf2d	250	* Return:
andreikovacs	0:764779eedf2d	251	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	252	uint8_t PhyPpGetDualPanSamLvl()
andreikovacs	0:764779eedf2d	253	{
andreikovacs	0:764779eedf2d	254	return mPhyCurrentSamLvl;
andreikovacs	0:764779eedf2d	255	}
andreikovacs	0:764779eedf2d	256
andreikovacs	0:764779eedf2d	257	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	258	* Name: PhyPpSetDualPanActiveNwk
andreikovacs	0:764779eedf2d	259	* Description: - Select Active PAN
andreikovacs	0:764779eedf2d	260	* Parameters: -
andreikovacs	0:764779eedf2d	261	* Return: -
andreikovacs	0:764779eedf2d	262	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	263	void PhyPpSetDualPanActiveNwk // TODO: check seq state and return phyStatus_t
andreikovacs	0:764779eedf2d	264	(
andreikovacs	0:764779eedf2d	265	uint8_t nwk
andreikovacs	0:764779eedf2d	266	)
andreikovacs	0:764779eedf2d	267	{
andreikovacs	0:764779eedf2d	268	uint8_t phyReg, phyReg2;
andreikovacs	0:764779eedf2d	269
andreikovacs	0:764779eedf2d	270	phyReg = MCR20Drv_IndirectAccessSPIRead( (uint8_t) DUAL_PAN_CTRL);
andreikovacs	0:764779eedf2d	271
andreikovacs	0:764779eedf2d	272	if( 0 == nwk )
andreikovacs	0:764779eedf2d	273	{
andreikovacs	0:764779eedf2d	274	phyReg2 = phyReg & (~cDUAL_PAN_CTRL_ACTIVE_NETWORK);
andreikovacs	0:764779eedf2d	275	}
andreikovacs	0:764779eedf2d	276	else
andreikovacs	0:764779eedf2d	277	{
andreikovacs	0:764779eedf2d	278	phyReg2 = phyReg \| cDUAL_PAN_CTRL_ACTIVE_NETWORK;
andreikovacs	0:764779eedf2d	279	}
andreikovacs	0:764779eedf2d	280
andreikovacs	0:764779eedf2d	281	/* Write the new value only if it has changed */
andreikovacs	0:764779eedf2d	282	if( phyReg2 != phyReg )
andreikovacs	0:764779eedf2d	283	{
andreikovacs	0:764779eedf2d	284	MCR20Drv_IndirectAccessSPIWrite( (uint8_t) DUAL_PAN_CTRL, phyReg2);
andreikovacs	0:764779eedf2d	285	}
andreikovacs	0:764779eedf2d	286	}
andreikovacs	0:764779eedf2d	287
andreikovacs	0:764779eedf2d	288	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	289	* Name: PhyPpGetDualPanActiveNwk
andreikovacs	0:764779eedf2d	290	* Description: -
andreikovacs	0:764779eedf2d	291	* Parameters: -
andreikovacs	0:764779eedf2d	292	* Return: - the Active PAN
andreikovacs	0:764779eedf2d	293	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	294	uint8_t PhyPpGetDualPanActiveNwk(void)
andreikovacs	0:764779eedf2d	295	{
andreikovacs	0:764779eedf2d	296	uint8_t phyReg;
andreikovacs	0:764779eedf2d	297
andreikovacs	0:764779eedf2d	298	phyReg = MCR20Drv_IndirectAccessSPIRead( (uint8_t)DUAL_PAN_CTRL );
andreikovacs	0:764779eedf2d	299
andreikovacs	0:764779eedf2d	300	return (phyReg & cDUAL_PAN_CTRL_CURRENT_NETWORK) > 0;
andreikovacs	0:764779eedf2d	301	}
andreikovacs	0:764779eedf2d	302
andreikovacs	0:764779eedf2d	303	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	304	* Name: PhyPpGetDualPanNwkOfRxPacket
andreikovacs	0:764779eedf2d	305	* Description: -
andreikovacs	0:764779eedf2d	306	* Parameters: -
andreikovacs	0:764779eedf2d	307	* Return: - the Active PAN
andreikovacs	0:764779eedf2d	308	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	309	uint8_t PhyPpGetPanOfRxPacket(void)
andreikovacs	0:764779eedf2d	310	{
andreikovacs	0:764779eedf2d	311	uint8_t phyReg;
andreikovacs	0:764779eedf2d	312	uint8_t PanBitMask = 0;
andreikovacs	0:764779eedf2d	313
andreikovacs	0:764779eedf2d	314	phyReg = MCR20Drv_IndirectAccessSPIRead( (uint8_t) DUAL_PAN_STS);
andreikovacs	0:764779eedf2d	315
andreikovacs	0:764779eedf2d	316	if( phyReg & cDUAL_PAN_STS_RECD_ON_PAN0 )
andreikovacs	0:764779eedf2d	317	PanBitMask \|= (1<<0);
andreikovacs	0:764779eedf2d	318
andreikovacs	0:764779eedf2d	319	if( phyReg & cDUAL_PAN_STS_RECD_ON_PAN1 )
andreikovacs	0:764779eedf2d	320	PanBitMask \|= (1<<1);
andreikovacs	0:764779eedf2d	321
andreikovacs	0:764779eedf2d	322	return PanBitMask;
andreikovacs	0:764779eedf2d	323	}
andreikovacs	0:764779eedf2d	324
andreikovacs	0:764779eedf2d	325	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	326	* Name: PhyPpSetPromiscuous
andreikovacs	0:764779eedf2d	327	* Description: -
andreikovacs	0:764779eedf2d	328	* Parameters: -
andreikovacs	0:764779eedf2d	329	* Return: -
andreikovacs	0:764779eedf2d	330	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	331	void PhyPpSetPromiscuous
andreikovacs	0:764779eedf2d	332	(
andreikovacs	0:764779eedf2d	333	bool_t mode
andreikovacs	0:764779eedf2d	334	)
andreikovacs	0:764779eedf2d	335	{
andreikovacs	0:764779eedf2d	336	uint8_t rxFrameFltReg, phyCtrl4Reg;
andreikovacs	0:764779eedf2d	337
andreikovacs	0:764779eedf2d	338	rxFrameFltReg = MCR20Drv_IndirectAccessSPIRead( (uint8_t) RX_FRAME_FILTER);
andreikovacs	0:764779eedf2d	339	phyCtrl4Reg = MCR20Drv_DirectAccessSPIRead( (uint8_t) PHY_CTRL4);
andreikovacs	0:764779eedf2d	340
andreikovacs	0:764779eedf2d	341	if( mode )
andreikovacs	0:764779eedf2d	342	{
andreikovacs	0:764779eedf2d	343	/* FRM_VER[1:0] = b00. 00: Any FrameVersion accepted (0,1,2 & 3) */
andreikovacs	0:764779eedf2d	344	/* All frame types accepted*/
andreikovacs	0:764779eedf2d	345	phyCtrl4Reg \|= cPHY_CTRL4_PROMISCUOUS;
andreikovacs	0:764779eedf2d	346	rxFrameFltReg &= ~(cRX_FRAME_FLT_FRM_VER);
andreikovacs	0:764779eedf2d	347	rxFrameFltReg \|= (cRX_FRAME_FLT_ACK_FT \| cRX_FRAME_FLT_NS_FT);
andreikovacs	0:764779eedf2d	348	}
andreikovacs	0:764779eedf2d	349	else
andreikovacs	0:764779eedf2d	350	{
andreikovacs	0:764779eedf2d	351	phyCtrl4Reg &= ~cPHY_CTRL4_PROMISCUOUS;
andreikovacs	0:764779eedf2d	352	/* FRM_VER[1:0] = b11. Accept FrameVersion 0 and 1 packets, reject all others */
andreikovacs	0:764779eedf2d	353	/* Beacon, Data and MAC command frame types accepted */
andreikovacs	0:764779eedf2d	354	rxFrameFltReg &= ~(cRX_FRAME_FLT_FRM_VER);
andreikovacs	0:764779eedf2d	355	rxFrameFltReg \|= (0x03 << cRX_FRAME_FLT_FRM_VER_Shift_c);
andreikovacs	0:764779eedf2d	356	rxFrameFltReg &= ~(cRX_FRAME_FLT_ACK_FT \| cRX_FRAME_FLT_NS_FT);
andreikovacs	0:764779eedf2d	357	}
andreikovacs	0:764779eedf2d	358
andreikovacs	0:764779eedf2d	359	MCR20Drv_IndirectAccessSPIWrite( (uint8_t) RX_FRAME_FILTER, rxFrameFltReg);
andreikovacs	0:764779eedf2d	360	MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL4, phyCtrl4Reg);
andreikovacs	0:764779eedf2d	361	}
andreikovacs	0:764779eedf2d	362
andreikovacs	0:764779eedf2d	363	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	364	* Name: PhySetActivePromiscuous()
andreikovacs	0:764779eedf2d	365	* Description: -
andreikovacs	0:764779eedf2d	366	* Parameters: -
andreikovacs	0:764779eedf2d	367	* Return: -
andreikovacs	0:764779eedf2d	368	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	369	void PhySetActivePromiscuous(bool_t state)
andreikovacs	0:764779eedf2d	370	{
andreikovacs	0:764779eedf2d	371	uint8_t phyCtrl4Reg;
andreikovacs	0:764779eedf2d	372	uint8_t phyFrameFilterReg;
andreikovacs	0:764779eedf2d	373	// bool_t currentState;
andreikovacs	0:764779eedf2d	374
andreikovacs	0:764779eedf2d	375	phyCtrl4Reg = MCR20Drv_DirectAccessSPIRead( (uint8_t) PHY_CTRL4);
andreikovacs	0:764779eedf2d	376	phyFrameFilterReg = MCR20Drv_IndirectAccessSPIRead(RX_FRAME_FILTER);
andreikovacs	0:764779eedf2d	377
andreikovacs	0:764779eedf2d	378	// currentState = (phyFrameFilterReg & cRX_FRAME_FLT_ACTIVE_PROMISCUOUS) ? TRUE : FALSE;
andreikovacs	0:764779eedf2d	379	//
andreikovacs	0:764779eedf2d	380	// if( state == currentState )
andreikovacs	0:764779eedf2d	381	// return;
andreikovacs	0:764779eedf2d	382
andreikovacs	0:764779eedf2d	383	/* if Prom is set */
andreikovacs	0:764779eedf2d	384	if( state )
andreikovacs	0:764779eedf2d	385	{
andreikovacs	0:764779eedf2d	386	if( phyCtrl4Reg & cPHY_CTRL4_PROMISCUOUS )
andreikovacs	0:764779eedf2d	387	{
andreikovacs	0:764779eedf2d	388	/* Disable Promiscuous mode */
andreikovacs	0:764779eedf2d	389	phyCtrl4Reg &= ~(cPHY_CTRL4_PROMISCUOUS);
andreikovacs	0:764779eedf2d	390
andreikovacs	0:764779eedf2d	391	/* Enable Active Promiscuous mode */
andreikovacs	0:764779eedf2d	392	phyFrameFilterReg \|= cRX_FRAME_FLT_ACTIVE_PROMISCUOUS;
andreikovacs	0:764779eedf2d	393	}
andreikovacs	0:764779eedf2d	394	}
andreikovacs	0:764779eedf2d	395	else
andreikovacs	0:764779eedf2d	396	{
andreikovacs	0:764779eedf2d	397	if( phyFrameFilterReg & cRX_FRAME_FLT_ACTIVE_PROMISCUOUS )
andreikovacs	0:764779eedf2d	398	{
andreikovacs	0:764779eedf2d	399	/* Disable Active Promiscuous mode */
andreikovacs	0:764779eedf2d	400	phyFrameFilterReg &= ~(cRX_FRAME_FLT_ACTIVE_PROMISCUOUS);
andreikovacs	0:764779eedf2d	401
andreikovacs	0:764779eedf2d	402	/* Enable Promiscuous mode */
andreikovacs	0:764779eedf2d	403	phyCtrl4Reg \|= cPHY_CTRL4_PROMISCUOUS;
andreikovacs	0:764779eedf2d	404	}
andreikovacs	0:764779eedf2d	405	}
andreikovacs	0:764779eedf2d	406
andreikovacs	0:764779eedf2d	407	MCR20Drv_DirectAccessSPIWrite((uint8_t) PHY_CTRL4, phyCtrl4Reg);
andreikovacs	0:764779eedf2d	408	MCR20Drv_IndirectAccessSPIWrite(RX_FRAME_FILTER, phyFrameFilterReg);
andreikovacs	0:764779eedf2d	409	}
andreikovacs	0:764779eedf2d	410
andreikovacs	0:764779eedf2d	411	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	412	* Name: PhyGetActivePromiscuous()
andreikovacs	0:764779eedf2d	413	* Description: - returns the state of ActivePromiscuous feature (Enabled/Disabled)
andreikovacs	0:764779eedf2d	414	* Parameters: -
andreikovacs	0:764779eedf2d	415	* Return: - TRUE/FALSE
andreikovacs	0:764779eedf2d	416	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	417	bool_t PhyGetActivePromiscuous( void )
andreikovacs	0:764779eedf2d	418	{
andreikovacs	0:764779eedf2d	419	uint8_t phyReg = MCR20Drv_IndirectAccessSPIRead(RX_FRAME_FILTER);
andreikovacs	0:764779eedf2d	420
andreikovacs	0:764779eedf2d	421	if( phyReg & cRX_FRAME_FLT_ACTIVE_PROMISCUOUS )
andreikovacs	0:764779eedf2d	422	return TRUE;
andreikovacs	0:764779eedf2d	423
andreikovacs	0:764779eedf2d	424	return FALSE;
andreikovacs	0:764779eedf2d	425	}
andreikovacs	0:764779eedf2d	426
andreikovacs	0:764779eedf2d	427	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	428	* Name: PhyPpSetPanId
andreikovacs	0:764779eedf2d	429	* Description: -
andreikovacs	0:764779eedf2d	430	* Parameters: -
andreikovacs	0:764779eedf2d	431	* Return: -
andreikovacs	0:764779eedf2d	432	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	433	phyStatus_t PhyPpSetPanId
andreikovacs	0:764779eedf2d	434	(
andreikovacs	0:764779eedf2d	435	uint8_t *pPanId,
andreikovacs	0:764779eedf2d	436	uint8_t pan
andreikovacs	0:764779eedf2d	437	)
andreikovacs	0:764779eedf2d	438	{
andreikovacs	0:764779eedf2d	439	#ifdef PHY_PARAMETERS_VALIDATION
andreikovacs	0:764779eedf2d	440	if(NULL == pPanId)
andreikovacs	0:764779eedf2d	441	{
andreikovacs	0:764779eedf2d	442	return gPhyInvalidParameter_c;
andreikovacs	0:764779eedf2d	443	}
andreikovacs	0:764779eedf2d	444	#endif // PHY_PARAMETERS_VALIDATION
andreikovacs	0:764779eedf2d	445
andreikovacs	0:764779eedf2d	446	if( 0 == pan )
andreikovacs	0:764779eedf2d	447	MCR20Drv_IndirectAccessSPIMultiByteWrite((uint8_t) MACPANID0_LSB, pPanId, 2);
andreikovacs	0:764779eedf2d	448	else
andreikovacs	0:764779eedf2d	449	MCR20Drv_IndirectAccessSPIMultiByteWrite((uint8_t) MACPANID1_LSB, pPanId, 2);
andreikovacs	0:764779eedf2d	450
andreikovacs	0:764779eedf2d	451	return gPhySuccess_c;
andreikovacs	0:764779eedf2d	452	}
andreikovacs	0:764779eedf2d	453
andreikovacs	0:764779eedf2d	454
andreikovacs	0:764779eedf2d	455	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	456	* Name: PhyPpSetShortAddr
andreikovacs	0:764779eedf2d	457	* Description: -
andreikovacs	0:764779eedf2d	458	* Parameters: -
andreikovacs	0:764779eedf2d	459	* Return: -
andreikovacs	0:764779eedf2d	460	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	461	phyStatus_t PhyPpSetShortAddr
andreikovacs	0:764779eedf2d	462	(
andreikovacs	0:764779eedf2d	463	uint8_t *pShortAddr,
andreikovacs	0:764779eedf2d	464	uint8_t pan
andreikovacs	0:764779eedf2d	465	)
andreikovacs	0:764779eedf2d	466	{
andreikovacs	0:764779eedf2d	467
andreikovacs	0:764779eedf2d	468	#ifdef PHY_PARAMETERS_VALIDATION
andreikovacs	0:764779eedf2d	469	if(NULL == pShortAddr)
andreikovacs	0:764779eedf2d	470	{
andreikovacs	0:764779eedf2d	471	return gPhyInvalidParameter_c;
andreikovacs	0:764779eedf2d	472	}
andreikovacs	0:764779eedf2d	473	#endif // PHY_PARAMETERS_VALIDATION
andreikovacs	0:764779eedf2d	474
andreikovacs	0:764779eedf2d	475	if( pan == 0 )
andreikovacs	0:764779eedf2d	476	{
andreikovacs	0:764779eedf2d	477	MCR20Drv_IndirectAccessSPIMultiByteWrite((uint8_t) MACSHORTADDRS0_LSB, pShortAddr, 2);
andreikovacs	0:764779eedf2d	478	}
andreikovacs	0:764779eedf2d	479	else
andreikovacs	0:764779eedf2d	480	{
andreikovacs	0:764779eedf2d	481	MCR20Drv_IndirectAccessSPIMultiByteWrite((uint8_t) MACSHORTADDRS1_LSB, pShortAddr, 2);
andreikovacs	0:764779eedf2d	482	}
andreikovacs	0:764779eedf2d	483
andreikovacs	0:764779eedf2d	484	return gPhySuccess_c;
andreikovacs	0:764779eedf2d	485	}
andreikovacs	0:764779eedf2d	486
andreikovacs	0:764779eedf2d	487	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	488	* Name: PhyPpSetLongAddr
andreikovacs	0:764779eedf2d	489	* Description: -
andreikovacs	0:764779eedf2d	490	* Parameters: -
andreikovacs	0:764779eedf2d	491	* Return: -
andreikovacs	0:764779eedf2d	492	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	493	phyStatus_t PhyPpSetLongAddr
andreikovacs	0:764779eedf2d	494	(
andreikovacs	0:764779eedf2d	495	uint8_t *pLongAddr,
andreikovacs	0:764779eedf2d	496	uint8_t pan
andreikovacs	0:764779eedf2d	497	)
andreikovacs	0:764779eedf2d	498	{
andreikovacs	0:764779eedf2d	499
andreikovacs	0:764779eedf2d	500	#ifdef PHY_PARAMETERS_VALIDATION
andreikovacs	0:764779eedf2d	501	if(NULL == pLongAddr)
andreikovacs	0:764779eedf2d	502	{
andreikovacs	0:764779eedf2d	503	return gPhyInvalidParameter_c;
andreikovacs	0:764779eedf2d	504	}
andreikovacs	0:764779eedf2d	505	#endif // PHY_PARAMETERS_VALIDATION
andreikovacs	0:764779eedf2d	506
andreikovacs	0:764779eedf2d	507	if( 0 == pan )
andreikovacs	0:764779eedf2d	508	MCR20Drv_IndirectAccessSPIMultiByteWrite((uint8_t) MACLONGADDRS0_0, pLongAddr, 8);
andreikovacs	0:764779eedf2d	509	else
andreikovacs	0:764779eedf2d	510	MCR20Drv_IndirectAccessSPIMultiByteWrite((uint8_t) MACLONGADDRS1_0, pLongAddr, 8);
andreikovacs	0:764779eedf2d	511
andreikovacs	0:764779eedf2d	512	return gPhySuccess_c;
andreikovacs	0:764779eedf2d	513	}
andreikovacs	0:764779eedf2d	514
andreikovacs	0:764779eedf2d	515
andreikovacs	0:764779eedf2d	516	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	517	* Name: PhyPpSetMacRole
andreikovacs	0:764779eedf2d	518	* Description: -
andreikovacs	0:764779eedf2d	519	* Parameters: -
andreikovacs	0:764779eedf2d	520	* Return: -
andreikovacs	0:764779eedf2d	521	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	522	phyStatus_t PhyPpSetMacRole
andreikovacs	0:764779eedf2d	523	(
andreikovacs	0:764779eedf2d	524	bool_t macRole,
andreikovacs	0:764779eedf2d	525	uint8_t pan
andreikovacs	0:764779eedf2d	526	)
andreikovacs	0:764779eedf2d	527	{
andreikovacs	0:764779eedf2d	528	uint8_t phyReg;
andreikovacs	0:764779eedf2d	529
andreikovacs	0:764779eedf2d	530	if( 0 == pan )
andreikovacs	0:764779eedf2d	531	{
andreikovacs	0:764779eedf2d	532	phyReg = MCR20Drv_DirectAccessSPIRead( (uint8_t) PHY_CTRL4);
andreikovacs	0:764779eedf2d	533
andreikovacs	0:764779eedf2d	534	if(gMacRole_PanCoord_c == macRole)
andreikovacs	0:764779eedf2d	535	{
andreikovacs	0:764779eedf2d	536	phyReg \|= cPHY_CTRL4_PANCORDNTR0;
andreikovacs	0:764779eedf2d	537	}
andreikovacs	0:764779eedf2d	538	else
andreikovacs	0:764779eedf2d	539	{
andreikovacs	0:764779eedf2d	540	phyReg &= ~cPHY_CTRL4_PANCORDNTR0;
andreikovacs	0:764779eedf2d	541	}
andreikovacs	0:764779eedf2d	542	MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL4, phyReg);
andreikovacs	0:764779eedf2d	543	}
andreikovacs	0:764779eedf2d	544	else
andreikovacs	0:764779eedf2d	545	{
andreikovacs	0:764779eedf2d	546	phyReg = MCR20Drv_IndirectAccessSPIRead( (uint8_t) DUAL_PAN_CTRL);
andreikovacs	0:764779eedf2d	547
andreikovacs	0:764779eedf2d	548	if(gMacRole_PanCoord_c == macRole)
andreikovacs	0:764779eedf2d	549	{
andreikovacs	0:764779eedf2d	550	phyReg \|= cDUAL_PAN_CTRL_PANCORDNTR1;
andreikovacs	0:764779eedf2d	551	}
andreikovacs	0:764779eedf2d	552	else
andreikovacs	0:764779eedf2d	553	{
andreikovacs	0:764779eedf2d	554	phyReg &= ~cDUAL_PAN_CTRL_PANCORDNTR1;
andreikovacs	0:764779eedf2d	555	}
andreikovacs	0:764779eedf2d	556	MCR20Drv_IndirectAccessSPIWrite( (uint8_t) DUAL_PAN_CTRL, phyReg);
andreikovacs	0:764779eedf2d	557	}
andreikovacs	0:764779eedf2d	558
andreikovacs	0:764779eedf2d	559	return gPhySuccess_c;
andreikovacs	0:764779eedf2d	560	}
andreikovacs	0:764779eedf2d	561
andreikovacs	0:764779eedf2d	562	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	563	* Name: PhyPpIsTxAckDataPending
andreikovacs	0:764779eedf2d	564	* Description: -
andreikovacs	0:764779eedf2d	565	* Parameters: -
andreikovacs	0:764779eedf2d	566	* Return: -
andreikovacs	0:764779eedf2d	567	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	568	bool_t PhyPpIsTxAckDataPending
andreikovacs	0:764779eedf2d	569	(
andreikovacs	0:764779eedf2d	570	void
andreikovacs	0:764779eedf2d	571	)
andreikovacs	0:764779eedf2d	572	{
andreikovacs	0:764779eedf2d	573	uint8_t srcCtrlReg;
andreikovacs	0:764779eedf2d	574
andreikovacs	0:764779eedf2d	575	srcCtrlReg = MCR20Drv_DirectAccessSPIRead(SRC_CTRL);
andreikovacs	0:764779eedf2d	576	if( srcCtrlReg & cSRC_CTRL_SRCADDR_EN )
andreikovacs	0:764779eedf2d	577	{
andreikovacs	0:764779eedf2d	578	uint8_t irqsts2Reg;
andreikovacs	0:764779eedf2d	579
andreikovacs	0:764779eedf2d	580	irqsts2Reg = MCR20Drv_DirectAccessSPIRead((uint8_t) IRQSTS2);
andreikovacs	0:764779eedf2d	581
andreikovacs	0:764779eedf2d	582	if(irqsts2Reg & cIRQSTS2_SRCADDR)
andreikovacs	0:764779eedf2d	583	return TRUE;
andreikovacs	0:764779eedf2d	584	else
andreikovacs	0:764779eedf2d	585	return FALSE;
andreikovacs	0:764779eedf2d	586	}
andreikovacs	0:764779eedf2d	587	else
andreikovacs	0:764779eedf2d	588	{
andreikovacs	0:764779eedf2d	589	return ((srcCtrlReg & cSRC_CTRL_ACK_FRM_PND) == cSRC_CTRL_ACK_FRM_PND);
andreikovacs	0:764779eedf2d	590	}
andreikovacs	0:764779eedf2d	591	}
andreikovacs	0:764779eedf2d	592
andreikovacs	0:764779eedf2d	593	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	594	* Name: PhyPpIsRxAckDataPending
andreikovacs	0:764779eedf2d	595	* Description: -
andreikovacs	0:764779eedf2d	596	* Parameters: -
andreikovacs	0:764779eedf2d	597	* Return: -
andreikovacs	0:764779eedf2d	598	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	599	bool_t PhyPpIsRxAckDataPending
andreikovacs	0:764779eedf2d	600	(
andreikovacs	0:764779eedf2d	601	void
andreikovacs	0:764779eedf2d	602	)
andreikovacs	0:764779eedf2d	603	{
andreikovacs	0:764779eedf2d	604	uint8_t irqsts1Reg;
andreikovacs	0:764779eedf2d	605	irqsts1Reg = MCR20Drv_DirectAccessSPIRead((uint8_t) IRQSTS1);
andreikovacs	0:764779eedf2d	606	if(irqsts1Reg & cIRQSTS1_RX_FRM_PEND)
andreikovacs	0:764779eedf2d	607	{
andreikovacs	0:764779eedf2d	608	return TRUE;
andreikovacs	0:764779eedf2d	609	}
andreikovacs	0:764779eedf2d	610	return FALSE;
andreikovacs	0:764779eedf2d	611	}
andreikovacs	0:764779eedf2d	612
andreikovacs	0:764779eedf2d	613	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	614	* Name: PhyPpSetFpManually
andreikovacs	0:764779eedf2d	615	* Description: -
andreikovacs	0:764779eedf2d	616	* Parameters: -
andreikovacs	0:764779eedf2d	617	* Return: -
andreikovacs	0:764779eedf2d	618	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	619	void PhyPpSetFpManually
andreikovacs	0:764779eedf2d	620	(
andreikovacs	0:764779eedf2d	621	bool_t FP
andreikovacs	0:764779eedf2d	622	)
andreikovacs	0:764779eedf2d	623	{
andreikovacs	0:764779eedf2d	624	uint8_t phyReg;
andreikovacs	0:764779eedf2d	625	/* Disable the Source Address Matching feature and set FP manually */
andreikovacs	0:764779eedf2d	626	phyReg = MCR20Drv_DirectAccessSPIRead(SRC_CTRL);
andreikovacs	0:764779eedf2d	627	phyReg &= ~(cSRC_CTRL_SRCADDR_EN);
andreikovacs	0:764779eedf2d	628	if(FP)
andreikovacs	0:764779eedf2d	629	phyReg \|= cSRC_CTRL_ACK_FRM_PND;
andreikovacs	0:764779eedf2d	630	else
andreikovacs	0:764779eedf2d	631	phyReg &= ~(cSRC_CTRL_ACK_FRM_PND);
andreikovacs	0:764779eedf2d	632	MCR20Drv_DirectAccessSPIWrite(SRC_CTRL, phyReg);
andreikovacs	0:764779eedf2d	633	}
andreikovacs	0:764779eedf2d	634
andreikovacs	0:764779eedf2d	635	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	636	* Name: PhyPpIsPollIndication
andreikovacs	0:764779eedf2d	637	* Description: -
andreikovacs	0:764779eedf2d	638	* Parameters: -
andreikovacs	0:764779eedf2d	639	* Return: -
andreikovacs	0:764779eedf2d	640	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	641	bool_t PhyPpIsPollIndication
andreikovacs	0:764779eedf2d	642	(
andreikovacs	0:764779eedf2d	643	void
andreikovacs	0:764779eedf2d	644	)
andreikovacs	0:764779eedf2d	645	{
andreikovacs	0:764779eedf2d	646	uint8_t irqsts2Reg;
andreikovacs	0:764779eedf2d	647	irqsts2Reg = MCR20Drv_DirectAccessSPIRead((uint8_t) IRQSTS2);
andreikovacs	0:764779eedf2d	648	if(irqsts2Reg & cIRQSTS2_PI)
andreikovacs	0:764779eedf2d	649	{
andreikovacs	0:764779eedf2d	650	return TRUE;
andreikovacs	0:764779eedf2d	651	}
andreikovacs	0:764779eedf2d	652	return FALSE;
andreikovacs	0:764779eedf2d	653	}
andreikovacs	0:764779eedf2d	654
andreikovacs	0:764779eedf2d	655	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	656	* Name: PhyPpSetCcaThreshold
andreikovacs	0:764779eedf2d	657	* Description: -
andreikovacs	0:764779eedf2d	658	* Parameters: -
andreikovacs	0:764779eedf2d	659	* Return: -
andreikovacs	0:764779eedf2d	660	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	661	phyStatus_t PhyPpSetCcaThreshold(uint8_t ccaThreshold)
andreikovacs	0:764779eedf2d	662	{
andreikovacs	0:764779eedf2d	663	MCR20Drv_IndirectAccessSPIWrite((uint8_t) CCA1_THRESH, (uint8_t) ccaThreshold);
andreikovacs	0:764779eedf2d	664	return gPhySuccess_c;
andreikovacs	0:764779eedf2d	665	}
andreikovacs	0:764779eedf2d	666
andreikovacs	0:764779eedf2d	667	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	668	* Name: PhyPpSetSAMState
andreikovacs	0:764779eedf2d	669	* Description: -
andreikovacs	0:764779eedf2d	670	* Parameters: -
andreikovacs	0:764779eedf2d	671	* Return: -
andreikovacs	0:764779eedf2d	672	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	673	void PhyPpSetSAMState
andreikovacs	0:764779eedf2d	674	(
andreikovacs	0:764779eedf2d	675	bool_t state
andreikovacs	0:764779eedf2d	676	)
andreikovacs	0:764779eedf2d	677	{
andreikovacs	0:764779eedf2d	678	uint8_t phyReg, newPhyReg;
andreikovacs	0:764779eedf2d	679	/* Disable/Enables the Source Address Matching feature */
andreikovacs	0:764779eedf2d	680	phyReg = MCR20Drv_DirectAccessSPIRead(SRC_CTRL);
andreikovacs	0:764779eedf2d	681	if( state )
andreikovacs	0:764779eedf2d	682	newPhyReg = phyReg \| cSRC_CTRL_SRCADDR_EN;
andreikovacs	0:764779eedf2d	683	else
andreikovacs	0:764779eedf2d	684	newPhyReg = phyReg & ~(cSRC_CTRL_SRCADDR_EN);
andreikovacs	0:764779eedf2d	685
andreikovacs	0:764779eedf2d	686	if( newPhyReg != phyReg )
andreikovacs	0:764779eedf2d	687	MCR20Drv_DirectAccessSPIWrite(SRC_CTRL, newPhyReg);
andreikovacs	0:764779eedf2d	688	}
andreikovacs	0:764779eedf2d	689
andreikovacs	0:764779eedf2d	690
andreikovacs	0:764779eedf2d	691	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	692	* Name: PhyPlmeSetFADStateRequest
andreikovacs	0:764779eedf2d	693	* Description: -
andreikovacs	0:764779eedf2d	694	* Parameters: -
andreikovacs	0:764779eedf2d	695	* Return: -
andreikovacs	0:764779eedf2d	696	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	697	uint8_t PhyPlmeSetFADStateRequest(bool_t state)
andreikovacs	0:764779eedf2d	698	{
andreikovacs	0:764779eedf2d	699	uint8_t phyReg;
andreikovacs	0:764779eedf2d	700
andreikovacs	0:764779eedf2d	701	phyReg = MCR20Drv_IndirectAccessSPIRead(ANT_AGC_CTRL);
andreikovacs	0:764779eedf2d	702	state ? (phyReg \|= cANT_AGC_CTRL_FAD_EN_Mask_c) : (phyReg &= (~((uint8_t)cANT_AGC_CTRL_FAD_EN_Mask_c)));
andreikovacs	0:764779eedf2d	703	MCR20Drv_IndirectAccessSPIWrite(ANT_AGC_CTRL, phyReg);
andreikovacs	0:764779eedf2d	704
andreikovacs	0:764779eedf2d	705	phyReg = MCR20Drv_IndirectAccessSPIRead(ANT_PAD_CTRL);
andreikovacs	0:764779eedf2d	706	state ? (phyReg \|= 0x02) : (phyReg &= ~cANT_PAD_CTRL_ANTX_EN);
andreikovacs	0:764779eedf2d	707	MCR20Drv_IndirectAccessSPIWrite(ANT_PAD_CTRL, phyReg);
andreikovacs	0:764779eedf2d	708
andreikovacs	0:764779eedf2d	709	return gPhySuccess_c;
andreikovacs	0:764779eedf2d	710	}
andreikovacs	0:764779eedf2d	711
andreikovacs	0:764779eedf2d	712	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	713	* Name: PhyPlmeSetFADThresholdRequest
andreikovacs	0:764779eedf2d	714	* Description: -
andreikovacs	0:764779eedf2d	715	* Parameters: -
andreikovacs	0:764779eedf2d	716	* Return: -
andreikovacs	0:764779eedf2d	717	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	718	uint8_t PhyPlmeSetFADThresholdRequest(uint8_t FADThreshold)
andreikovacs	0:764779eedf2d	719	{
andreikovacs	0:764779eedf2d	720	MCR20Drv_IndirectAccessSPIWrite(FAD_THR, FADThreshold);
andreikovacs	0:764779eedf2d	721	return gPhySuccess_c;
andreikovacs	0:764779eedf2d	722	}
andreikovacs	0:764779eedf2d	723
andreikovacs	0:764779eedf2d	724	uint8_t PhyPlmeSetANTPadStateRequest(bool_t antAB_on, bool_t rxtxSwitch_on)
andreikovacs	0:764779eedf2d	725	{
andreikovacs	0:764779eedf2d	726	uint8_t phyReg;
andreikovacs	0:764779eedf2d	727
andreikovacs	0:764779eedf2d	728	phyReg = MCR20Drv_IndirectAccessSPIRead(ANT_PAD_CTRL);
andreikovacs	0:764779eedf2d	729	antAB_on ? (phyReg \|= 0x02) : (phyReg &= ~0x02);
andreikovacs	0:764779eedf2d	730	rxtxSwitch_on ? (phyReg \|= 0x01) : (phyReg &= ~0x01);
andreikovacs	0:764779eedf2d	731	MCR20Drv_IndirectAccessSPIWrite(ANT_PAD_CTRL, phyReg);
andreikovacs	0:764779eedf2d	732
andreikovacs	0:764779eedf2d	733	return gPhySuccess_c;
andreikovacs	0:764779eedf2d	734	}
andreikovacs	0:764779eedf2d	735
andreikovacs	0:764779eedf2d	736	uint8_t PhyPlmeSetANTPadStrengthRequest(bool_t hiStrength)
andreikovacs	0:764779eedf2d	737	{
andreikovacs	0:764779eedf2d	738	uint8_t phyReg;
andreikovacs	0:764779eedf2d	739
andreikovacs	0:764779eedf2d	740	phyReg = MCR20Drv_IndirectAccessSPIRead(MISC_PAD_CTRL);
andreikovacs	0:764779eedf2d	741	hiStrength ? (phyReg \|= cMISC_PAD_CTRL_ANTX_CURR) : (phyReg &= ~cMISC_PAD_CTRL_ANTX_CURR);
andreikovacs	0:764779eedf2d	742	MCR20Drv_IndirectAccessSPIWrite(MISC_PAD_CTRL, phyReg);
andreikovacs	0:764779eedf2d	743
andreikovacs	0:764779eedf2d	744	return gPhySuccess_c;
andreikovacs	0:764779eedf2d	745	}
andreikovacs	0:764779eedf2d	746
andreikovacs	0:764779eedf2d	747	uint8_t PhyPlmeSetANTPadInvertedRequest(bool_t invAntA, bool_t invAntB, bool_t invTx, bool_t invRx)
andreikovacs	0:764779eedf2d	748	{
andreikovacs	0:764779eedf2d	749	uint8_t phyReg;
andreikovacs	0:764779eedf2d	750
andreikovacs	0:764779eedf2d	751	phyReg = MCR20Drv_IndirectAccessSPIRead(MISC_PAD_CTRL);
andreikovacs	0:764779eedf2d	752	invAntA ? (phyReg \|= 0x10) : (phyReg &= ~0x10);
andreikovacs	0:764779eedf2d	753	invAntB ? (phyReg \|= 0x20) : (phyReg &= ~0x20);
andreikovacs	0:764779eedf2d	754	invTx ? (phyReg \|= 0x40) : (phyReg &= ~0x40);
andreikovacs	0:764779eedf2d	755	invRx ? (phyReg \|= 0x80) : (phyReg &= ~0x80);
andreikovacs	0:764779eedf2d	756	MCR20Drv_IndirectAccessSPIWrite(MISC_PAD_CTRL, phyReg);
andreikovacs	0:764779eedf2d	757
andreikovacs	0:764779eedf2d	758	return gPhySuccess_c;
andreikovacs	0:764779eedf2d	759	}
andreikovacs	0:764779eedf2d	760
andreikovacs	0:764779eedf2d	761	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	762	* Name: PhyPlmeSetANTXStateRequest
andreikovacs	0:764779eedf2d	763	* Description: -
andreikovacs	0:764779eedf2d	764	* Parameters: -
andreikovacs	0:764779eedf2d	765	* Return: -
andreikovacs	0:764779eedf2d	766	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	767	uint8_t PhyPlmeSetANTXStateRequest(bool_t state)
andreikovacs	0:764779eedf2d	768	{
andreikovacs	0:764779eedf2d	769	uint8_t phyReg;
andreikovacs	0:764779eedf2d	770
andreikovacs	0:764779eedf2d	771	phyReg = MCR20Drv_IndirectAccessSPIRead(ANT_AGC_CTRL);
andreikovacs	0:764779eedf2d	772	state ? (phyReg \|= cANT_AGC_CTRL_ANTX_Mask_c) : (phyReg &= (~((uint8_t)cANT_AGC_CTRL_ANTX_Mask_c)));
andreikovacs	0:764779eedf2d	773	MCR20Drv_IndirectAccessSPIWrite(ANT_AGC_CTRL, phyReg);
andreikovacs	0:764779eedf2d	774
andreikovacs	0:764779eedf2d	775	return gPhySuccess_c;
andreikovacs	0:764779eedf2d	776	}
andreikovacs	0:764779eedf2d	777
andreikovacs	0:764779eedf2d	778	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	779	* Name: PhyPlmeGetANTXStateRequest
andreikovacs	0:764779eedf2d	780	* Description: -
andreikovacs	0:764779eedf2d	781	* Parameters: -
andreikovacs	0:764779eedf2d	782	* Return: -
andreikovacs	0:764779eedf2d	783	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	784	uint8_t PhyPlmeGetANTXStateRequest(void)
andreikovacs	0:764779eedf2d	785	{
andreikovacs	0:764779eedf2d	786	uint8_t phyReg;
andreikovacs	0:764779eedf2d	787
andreikovacs	0:764779eedf2d	788	phyReg = MCR20Drv_IndirectAccessSPIRead(ANT_AGC_CTRL);
andreikovacs	0:764779eedf2d	789
andreikovacs	0:764779eedf2d	790	return ((phyReg & cANT_AGC_CTRL_ANTX_Mask_c) == cANT_AGC_CTRL_ANTX_Mask_c);
andreikovacs	0:764779eedf2d	791	}
andreikovacs	0:764779eedf2d	792
andreikovacs	0:764779eedf2d	793	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	794	* Name: PhyPp_IndirectQueueInsert
andreikovacs	0:764779eedf2d	795	* Description: -
andreikovacs	0:764779eedf2d	796	* Parameters: -
andreikovacs	0:764779eedf2d	797	* Return: -
andreikovacs	0:764779eedf2d	798	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	799	phyStatus_t PhyPp_IndirectQueueInsert // TODO: to validate add to indirect queue parameters
andreikovacs	0:764779eedf2d	800	(
andreikovacs	0:764779eedf2d	801	uint8_t index,
andreikovacs	0:764779eedf2d	802	uint16_t checkSum,
andreikovacs	0:764779eedf2d	803	instanceId_t instanceId
andreikovacs	0:764779eedf2d	804	)
andreikovacs	0:764779eedf2d	805	{
andreikovacs	0:764779eedf2d	806	uint16_t srcAddressCheckSum = checkSum;
andreikovacs	0:764779eedf2d	807	uint8_t srcCtrlReg;
andreikovacs	0:764779eedf2d	808
andreikovacs	0:764779eedf2d	809	if( index >= gPhyIndirectQueueSize_c )
andreikovacs	0:764779eedf2d	810	return gPhyInvalidParameter_c;
andreikovacs	0:764779eedf2d	811
andreikovacs	0:764779eedf2d	812	srcCtrlReg = (uint8_t) ( (index & cSRC_CTRL_INDEX) << cSRC_CTRL_INDEX_Shift_c );
andreikovacs	0:764779eedf2d	813	MCR20Drv_DirectAccessSPIWrite( (uint8_t) SRC_CTRL, srcCtrlReg);
andreikovacs	0:764779eedf2d	814
andreikovacs	0:764779eedf2d	815	MCR20Drv_DirectAccessSPIMultiByteWrite( (uint8_t) SRC_ADDRS_SUM_LSB, (uint8_t *) &srcAddressCheckSum, 2);
andreikovacs	0:764779eedf2d	816
andreikovacs	0:764779eedf2d	817	srcCtrlReg \|= ( cSRC_CTRL_SRCADDR_EN \| cSRC_CTRL_INDEX_EN );
andreikovacs	0:764779eedf2d	818	MCR20Drv_DirectAccessSPIWrite( (uint8_t) SRC_CTRL, srcCtrlReg);
andreikovacs	0:764779eedf2d	819
andreikovacs	0:764779eedf2d	820	return gPhySuccess_c;
andreikovacs	0:764779eedf2d	821
andreikovacs	0:764779eedf2d	822	}
andreikovacs	0:764779eedf2d	823
andreikovacs	0:764779eedf2d	824
andreikovacs	0:764779eedf2d	825	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	826	* Name: PhyPp_RemoveFromIndirect
andreikovacs	0:764779eedf2d	827	* Description: -
andreikovacs	0:764779eedf2d	828	* Parameters: -
andreikovacs	0:764779eedf2d	829	* Return: -
andreikovacs	0:764779eedf2d	830	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	831	phyStatus_t PhyPp_RemoveFromIndirect
andreikovacs	0:764779eedf2d	832	(
andreikovacs	0:764779eedf2d	833	uint8_t index,
andreikovacs	0:764779eedf2d	834	instanceId_t instanceId
andreikovacs	0:764779eedf2d	835	)
andreikovacs	0:764779eedf2d	836	{
andreikovacs	0:764779eedf2d	837	uint8_t srcCtrlReg;
andreikovacs	0:764779eedf2d	838
andreikovacs	0:764779eedf2d	839	if( index >= gPhyIndirectQueueSize_c )
andreikovacs	0:764779eedf2d	840	return gPhyInvalidParameter_c;
andreikovacs	0:764779eedf2d	841
andreikovacs	0:764779eedf2d	842	srcCtrlReg = (uint8_t)( ( (index & cSRC_CTRL_INDEX) << cSRC_CTRL_INDEX_Shift_c )
andreikovacs	0:764779eedf2d	843	\|( cSRC_CTRL_SRCADDR_EN )
andreikovacs	0:764779eedf2d	844	\|( cSRC_CTRL_INDEX_DISABLE) );
andreikovacs	0:764779eedf2d	845
andreikovacs	0:764779eedf2d	846	MCR20Drv_DirectAccessSPIWrite( (uint8_t) SRC_CTRL, srcCtrlReg);
andreikovacs	0:764779eedf2d	847
andreikovacs	0:764779eedf2d	848	return gPhySuccess_c;
andreikovacs	0:764779eedf2d	849	}
andreikovacs	0:764779eedf2d	850
andreikovacs	0:764779eedf2d	851
andreikovacs	0:764779eedf2d	852	/*---------------------------------------------------------------------------
andreikovacs	0:764779eedf2d	853	* Name: PhyPpGetState
andreikovacs	0:764779eedf2d	854	* Description: -
andreikovacs	0:764779eedf2d	855	* Parameters: -
andreikovacs	0:764779eedf2d	856	* Return: -
andreikovacs	0:764779eedf2d	857	---------------------------------------------------------------------------/
andreikovacs	0:764779eedf2d	858	uint8_t PhyPpGetState
andreikovacs	0:764779eedf2d	859	(
andreikovacs	0:764779eedf2d	860	void
andreikovacs	0:764779eedf2d	861	)
andreikovacs	0:764779eedf2d	862	{
andreikovacs	0:764779eedf2d	863	return (uint8_t)( MCR20Drv_DirectAccessSPIRead( (uint8_t) PHY_CTRL1) & cPHY_CTRL1_XCVSEQ );
andreikovacs	0:764779eedf2d	864	}
andreikovacs	0:764779eedf2d	865
andreikovacs	0:764779eedf2d	866	/! ********************************************************************************
andreikovacs	0:764779eedf2d	867	* \brief Aborts the current sequence and force the radio to IDLE
andreikovacs	0:764779eedf2d	868	*
andreikovacs	0:764779eedf2d	869	********************************************************************************** */
andreikovacs	0:764779eedf2d	870	void PhyAbort(void)
andreikovacs	0:764779eedf2d	871	{
andreikovacs	0:764779eedf2d	872	uint8_t phyRegs[8];
andreikovacs	0:764779eedf2d	873	volatile uint8_t currentTime = 0;
andreikovacs	0:764779eedf2d	874
andreikovacs	0:764779eedf2d	875	ProtectFromMCR20Interrupt();
andreikovacs	0:764779eedf2d	876
andreikovacs	0:764779eedf2d	877	phyRegs[0] = MCR20Drv_DirectAccessSPIMultiByteRead(IRQSTS2, &phyRegs[1], 7);
andreikovacs	0:764779eedf2d	878
andreikovacs	0:764779eedf2d	879	// Disable timer trigger (for scheduled XCVSEQ)
andreikovacs	0:764779eedf2d	880	if( phyRegs[PHY_CTRL1] & cPHY_CTRL1_TMRTRIGEN )
andreikovacs	0:764779eedf2d	881	{
andreikovacs	0:764779eedf2d	882	phyRegs[PHY_CTRL1] &= (uint8_t) ~(cPHY_CTRL1_TMRTRIGEN );
andreikovacs	0:764779eedf2d	883	MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, phyRegs[PHY_CTRL1]);
andreikovacs	0:764779eedf2d	884
andreikovacs	0:764779eedf2d	885	// give the FSM enough time to start if it was triggered
andreikovacs	0:764779eedf2d	886	currentTime = (uint8_t) ( MCR20Drv_DirectAccessSPIRead(EVENT_TMR_LSB) + 2 );
andreikovacs	0:764779eedf2d	887	while(MCR20Drv_DirectAccessSPIRead(EVENT_TMR_LSB) != (uint8_t) (currentTime));
andreikovacs	0:764779eedf2d	888
andreikovacs	0:764779eedf2d	889	phyRegs[PHY_CTRL1] = MCR20Drv_DirectAccessSPIRead(PHY_CTRL1);
andreikovacs	0:764779eedf2d	890	}
andreikovacs	0:764779eedf2d	891
andreikovacs	0:764779eedf2d	892	if( (phyRegs[PHY_CTRL1] & cPHY_CTRL1_XCVSEQ) != gIdle_c )
andreikovacs	0:764779eedf2d	893	{
andreikovacs	0:764779eedf2d	894	// Abort current SEQ
andreikovacs	0:764779eedf2d	895	phyRegs[PHY_CTRL1] &= (uint8_t) ~(cPHY_CTRL1_XCVSEQ);
andreikovacs	0:764779eedf2d	896	MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, phyRegs[PHY_CTRL1]);
andreikovacs	0:764779eedf2d	897
andreikovacs	0:764779eedf2d	898	// wait for Sequence Idle (if not already)
andreikovacs	0:764779eedf2d	899	while ((MCR20Drv_DirectAccessSPIRead(SEQ_STATE) & 0x1F) != 0);
andreikovacs	0:764779eedf2d	900	}
andreikovacs	0:764779eedf2d	901
andreikovacs	0:764779eedf2d	902	// mask SEQ interrupt
andreikovacs	0:764779eedf2d	903	phyRegs[PHY_CTRL2] \|= (uint8_t) (cPHY_CTRL2_SEQMSK);
andreikovacs	0:764779eedf2d	904	// stop timers
andreikovacs	0:764779eedf2d	905	phyRegs[PHY_CTRL3] &= (uint8_t) ~(cPHY_CTRL3_TMR2CMP_EN \| cPHY_CTRL3_TMR3CMP_EN);
andreikovacs	0:764779eedf2d	906	phyRegs[PHY_CTRL4] &= (uint8_t) ~(cPHY_CTRL4_TC3TMOUT);
andreikovacs	0:764779eedf2d	907
andreikovacs	0:764779eedf2d	908	MCR20Drv_DirectAccessSPIMultiByteWrite(PHY_CTRL2, &phyRegs[PHY_CTRL2], 4);
andreikovacs	0:764779eedf2d	909
andreikovacs	0:764779eedf2d	910	// clear all PP IRQ bits to avoid unexpected interrupts
andreikovacs	0:764779eedf2d	911	phyRegs[IRQSTS3] &= 0xF0; // do not change IRQ status
andreikovacs	0:764779eedf2d	912	phyRegs[IRQSTS3] \|= (uint8_t) (cIRQSTS3_TMR3MSK \|
andreikovacs	0:764779eedf2d	913	cIRQSTS3_TMR2IRQ \|
andreikovacs	0:764779eedf2d	914	cIRQSTS3_TMR3IRQ); // mask TMR3 interrupt
andreikovacs	0:764779eedf2d	915
andreikovacs	0:764779eedf2d	916	MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, phyRegs, 3);
andreikovacs	0:764779eedf2d	917
andreikovacs	0:764779eedf2d	918	PhyIsrPassRxParams(NULL);
andreikovacs	0:764779eedf2d	919
andreikovacs	0:764779eedf2d	920	UnprotectFromMCR20Interrupt();
andreikovacs	0:764779eedf2d	921	}
andreikovacs	0:764779eedf2d	922
andreikovacs	0:764779eedf2d	923
andreikovacs	0:764779eedf2d	924	/! ********************************************************************************
andreikovacs	0:764779eedf2d	925	* \brief Initialize the 802.15.4 Radio registers
andreikovacs	0:764779eedf2d	926	*
andreikovacs	0:764779eedf2d	927	********************************************************************************** */
andreikovacs	0:764779eedf2d	928
andreikovacs	0:764779eedf2d	929	void PhyHwInit( void )
andreikovacs	0:764779eedf2d	930	{
andreikovacs	0:764779eedf2d	931	uint8_t index;
andreikovacs	0:764779eedf2d	932	uint8_t phyReg;
andreikovacs	0:764779eedf2d	933
andreikovacs	0:764779eedf2d	934	/* Initialize the transceiver SPI driver */
andreikovacs	0:764779eedf2d	935	MCR20Drv_Init();
andreikovacs	0:764779eedf2d	936	/* Configure the transceiver IRQ_B port */
andreikovacs	0:764779eedf2d	937	MCR20Drv_IRQ_PortConfig();
andreikovacs	0:764779eedf2d	938	/* Initialize the SPI driver and install PHY ISR */
andreikovacs	0:764779eedf2d	939	PHY_InstallIsr();
andreikovacs	0:764779eedf2d	940
andreikovacs	0:764779eedf2d	941	//Disable Tristate on COCO MISO for SPI reads
andreikovacs	0:764779eedf2d	942	MCR20Drv_IndirectAccessSPIWrite((uint8_t) MISC_PAD_CTRL, (uint8_t) 0x02);
andreikovacs	0:764779eedf2d	943
andreikovacs	0:764779eedf2d	944	// PHY_CTRL4 unmask global TRX interrupts, enable 16 bit mode for TC2 - TC2 prime EN
andreikovacs	0:764779eedf2d	945	MCR20Drv_DirectAccessSPIWrite(PHY_CTRL4, (uint8_t) (cPHY_CTRL4_TC2PRIME_EN \| \
andreikovacs	0:764779eedf2d	946	(gCcaCCA_MODE1_c << cPHY_CTRL4_CCATYPE_Shift_c)));
andreikovacs	0:764779eedf2d	947
andreikovacs	0:764779eedf2d	948	// clear all PP IRQ bits to avoid unexpected interrupts immediately after init, disable all timer interrupts
andreikovacs	0:764779eedf2d	949	MCR20Drv_DirectAccessSPIWrite(IRQSTS1, (uint8_t) (cIRQSTS1_PLL_UNLOCK_IRQ \| \
andreikovacs	0:764779eedf2d	950	cIRQSTS1_FILTERFAIL_IRQ \| \
andreikovacs	0:764779eedf2d	951	cIRQSTS1_RXWTRMRKIRQ \| \
andreikovacs	0:764779eedf2d	952	cIRQSTS1_CCAIRQ \| \
andreikovacs	0:764779eedf2d	953	cIRQSTS1_RXIRQ \| \
andreikovacs	0:764779eedf2d	954	cIRQSTS1_TXIRQ \| \
andreikovacs	0:764779eedf2d	955	cIRQSTS1_SEQIRQ));
andreikovacs	0:764779eedf2d	956
andreikovacs	0:764779eedf2d	957	MCR20Drv_DirectAccessSPIWrite(IRQSTS2, (uint8_t) (cIRQSTS2_ASM_IRQ \| \
andreikovacs	0:764779eedf2d	958	cIRQSTS2_PB_ERR_IRQ \| \
andreikovacs	0:764779eedf2d	959	cIRQSTS2_WAKE_IRQ));
andreikovacs	0:764779eedf2d	960
andreikovacs	0:764779eedf2d	961	MCR20Drv_DirectAccessSPIWrite(IRQSTS3, (uint8_t) (cIRQSTS3_TMR4MSK \| \
andreikovacs	0:764779eedf2d	962	cIRQSTS3_TMR3MSK \| \
andreikovacs	0:764779eedf2d	963	cIRQSTS3_TMR2MSK \| \
andreikovacs	0:764779eedf2d	964	cIRQSTS3_TMR1MSK \| \
andreikovacs	0:764779eedf2d	965	cIRQSTS3_TMR4IRQ \| \
andreikovacs	0:764779eedf2d	966	cIRQSTS3_TMR3IRQ \| \
andreikovacs	0:764779eedf2d	967	cIRQSTS3_TMR2IRQ \| \
andreikovacs	0:764779eedf2d	968	cIRQSTS3_TMR1IRQ));
andreikovacs	0:764779eedf2d	969
andreikovacs	0:764779eedf2d	970	// PHY_CTRL1 default HW settings + AUTOACK enabled
andreikovacs	0:764779eedf2d	971	MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, (uint8_t) (cPHY_CTRL1_AUTOACK));
andreikovacs	0:764779eedf2d	972
andreikovacs	0:764779eedf2d	973	// PHY_CTRL2 : disable all interrupts
andreikovacs	0:764779eedf2d	974	MCR20Drv_DirectAccessSPIWrite(PHY_CTRL2, (uint8_t) (cPHY_CTRL2_CRC_MSK \| \
andreikovacs	0:764779eedf2d	975	cPHY_CTRL2_PLL_UNLOCK_MSK \| \
andreikovacs	0:764779eedf2d	976	cPHY_CTRL2_FILTERFAIL_MSK \| \
andreikovacs	0:764779eedf2d	977	cPHY_CTRL2_RX_WMRK_MSK \| \
andreikovacs	0:764779eedf2d	978	cPHY_CTRL2_CCAMSK \| \
andreikovacs	0:764779eedf2d	979	cPHY_CTRL2_RXMSK \| \
andreikovacs	0:764779eedf2d	980	cPHY_CTRL2_TXMSK \| \
andreikovacs	0:764779eedf2d	981	cPHY_CTRL2_SEQMSK));
andreikovacs	0:764779eedf2d	982
andreikovacs	0:764779eedf2d	983	// PHY_CTRL3 : disable all timers and remaining interrupts
andreikovacs	0:764779eedf2d	984	MCR20Drv_DirectAccessSPIWrite(PHY_CTRL3, (uint8_t) (cPHY_CTRL3_ASM_MSK \| \
andreikovacs	0:764779eedf2d	985	cPHY_CTRL3_PB_ERR_MSK \| \
andreikovacs	0:764779eedf2d	986	cPHY_CTRL3_WAKE_MSK));
andreikovacs	0:764779eedf2d	987	// SRC_CTRL
andreikovacs	0:764779eedf2d	988	MCR20Drv_DirectAccessSPIWrite(SRC_CTRL, (uint8_t) (cSRC_CTRL_ACK_FRM_PND \| \
andreikovacs	0:764779eedf2d	989	(cSRC_CTRL_INDEX << cSRC_CTRL_INDEX_Shift_c)));
andreikovacs	0:764779eedf2d	990	// RX_FRAME_FILTER
andreikovacs	0:764779eedf2d	991	// FRM_VER[1:0] = b11. Accept FrameVersion 0 and 1 packets, reject all others
andreikovacs	0:764779eedf2d	992	MCR20Drv_IndirectAccessSPIWrite(RX_FRAME_FILTER, (uint8_t)(cRX_FRAME_FLT_FRM_VER \| \
andreikovacs	0:764779eedf2d	993	cRX_FRAME_FLT_BEACON_FT \| \
andreikovacs	0:764779eedf2d	994	cRX_FRAME_FLT_DATA_FT \| \
andreikovacs	0:764779eedf2d	995	cRX_FRAME_FLT_CMD_FT ));
andreikovacs	0:764779eedf2d	996	// Direct register overwrites
andreikovacs	0:764779eedf2d	997	for (index = 0; index < sizeof(overwrites_direct)/sizeof(overwrites_t); index++)
andreikovacs	0:764779eedf2d	998	MCR20Drv_DirectAccessSPIWrite(overwrites_direct[index].address, overwrites_direct[index].data);
andreikovacs	0:764779eedf2d	999
andreikovacs	0:764779eedf2d	1000	// Indirect register overwrites
andreikovacs	0:764779eedf2d	1001	for (index = 0; index < sizeof(overwrites_indirect)/sizeof(overwrites_t); index++)
andreikovacs	0:764779eedf2d	1002	MCR20Drv_IndirectAccessSPIWrite(overwrites_indirect[index].address, overwrites_indirect[index].data);
andreikovacs	0:764779eedf2d	1003
andreikovacs	0:764779eedf2d	1004	// Clear HW indirect queue
andreikovacs	0:764779eedf2d	1005	for( index = 0; index < gPhyIndirectQueueSize_c; index++ )
andreikovacs	0:764779eedf2d	1006	PhyPp_RemoveFromIndirect( index, 0 );
andreikovacs	0:764779eedf2d	1007
andreikovacs	0:764779eedf2d	1008	PhyPlmeSetCurrentChannelRequest(0x0B, 0); //2405 MHz
andreikovacs	0:764779eedf2d	1009	#if gMpmIncluded_d
andreikovacs	0:764779eedf2d	1010	PhyPlmeSetCurrentChannelRequest(0x0B, 1); //2405 MHz
andreikovacs	0:764779eedf2d	1011
andreikovacs	0:764779eedf2d	1012	// Split the HW Indirect hash table in two
andreikovacs	0:764779eedf2d	1013	PhyPpSetDualPanSamLvl( gPhyIndirectQueueSize_c/2 );
andreikovacs	0:764779eedf2d	1014	#else
andreikovacs	0:764779eedf2d	1015	// Assign HW Indirect hash table to PAN0
andreikovacs	0:764779eedf2d	1016	PhyPpSetDualPanSamLvl( gPhyIndirectQueueSize_c );
andreikovacs	0:764779eedf2d	1017	#endif
andreikovacs	0:764779eedf2d	1018
andreikovacs	0:764779eedf2d	1019	// set the power level to 0dBm
andreikovacs	0:764779eedf2d	1020	PhyPlmeSetPwrLevelRequest(0x17);
andreikovacs	0:764779eedf2d	1021	// set CCA threshold to -75 dBm
andreikovacs	0:764779eedf2d	1022	PhyPpSetCcaThreshold(0x4B);
andreikovacs	0:764779eedf2d	1023	// Set prescaller to obtain 1 symbol (16us) timebase
andreikovacs	0:764779eedf2d	1024	MCR20Drv_IndirectAccessSPIWrite(TMR_PRESCALE, 0x05);
andreikovacs	0:764779eedf2d	1025	// write default Rx watermark level
andreikovacs	0:764779eedf2d	1026	MCR20Drv_IndirectAccessSPIWrite(RX_WTR_MARK, 0);
andreikovacs	0:764779eedf2d	1027
andreikovacs	0:764779eedf2d	1028	//Enable the RxWatermark IRQ and FilterFail IRQ
andreikovacs	0:764779eedf2d	1029	phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL2);
andreikovacs	0:764779eedf2d	1030	//phyReg &= (uint8_t)~(cPHY_CTRL2_FILTERFAIL_MSK);
andreikovacs	0:764779eedf2d	1031	phyReg &= (uint8_t)~(cPHY_CTRL2_RX_WMRK_MSK);
andreikovacs	0:764779eedf2d	1032	MCR20Drv_DirectAccessSPIWrite(PHY_CTRL2, phyReg);
andreikovacs	0:764779eedf2d	1033
andreikovacs	0:764779eedf2d	1034	/* enable autodoze mode. */
andreikovacs	0:764779eedf2d	1035	phyReg = MCR20Drv_DirectAccessSPIRead( (uint8_t) PWR_MODES);
andreikovacs	0:764779eedf2d	1036	phyReg \|= (uint8_t) cPWR_MODES_AUTODOZE;
andreikovacs	0:764779eedf2d	1037	MCR20Drv_DirectAccessSPIWrite( (uint8_t) PWR_MODES, phyReg);
andreikovacs	0:764779eedf2d	1038	MCR20Drv_Set_CLK_OUT_Freq(gMCR20_ClkOutFreq_d);
andreikovacs	0:764779eedf2d	1039
andreikovacs	0:764779eedf2d	1040	// Clear IRQn Pending Status
andreikovacs	0:764779eedf2d	1041	MCR20Drv_IRQ_Clear();
andreikovacs	0:764779eedf2d	1042	//NVIC_ClearPendingIRQ(g_portIrqId[GPIO_EXTRACT_PORT(kGpioXcvrIrqPin)]);
andreikovacs	0:764779eedf2d	1043	/* enable the transceiver IRQ_B interrupt request */
andreikovacs	0:764779eedf2d	1044	MCR20Drv_IRQ_Enable();
andreikovacs	0:764779eedf2d	1045	}
andreikovacs	0:764779eedf2d	1046
andreikovacs	0:764779eedf2d	1047	/! ********************************************************************************
andreikovacs	0:764779eedf2d	1048	* \brief Change the XCVR power state
andreikovacs	0:764779eedf2d	1049	*
andreikovacs	0:764779eedf2d	1050	* \param[in] state the new XCVR power state
andreikovacs	0:764779eedf2d	1051	*
andreikovacs	0:764779eedf2d	1052	* \return phyStatus_t
andreikovacs	0:764779eedf2d	1053	*
andreikovacs	0:764779eedf2d	1054	* \pre Before entering hibernate/reset states, the MCG clock source must be changed
andreikovacs	0:764779eedf2d	1055	* to use an input other than the one generated by the XCVR!
andreikovacs	0:764779eedf2d	1056	*
andreikovacs	0:764779eedf2d	1057	* \post When XCVR is in hibernate, indirect registers cannot be accessed in burst mode
andreikovacs	0:764779eedf2d	1058	* When XCVR is in reset, all registers are inaccessible!
andreikovacs	0:764779eedf2d	1059	*
andreikovacs	0:764779eedf2d	1060	* \remarks Putting the XCVR into hibernate/reset will stop the generated clock signal!
andreikovacs	0:764779eedf2d	1061	*
andreikovacs	0:764779eedf2d	1062	********************************************************************************** */
andreikovacs	0:764779eedf2d	1063	phyStatus_t PhyPlmeSetPwrState( uint8_t state )
andreikovacs	0:764779eedf2d	1064	{
andreikovacs	0:764779eedf2d	1065	uint8_t phyPWR, xtalState;
andreikovacs	0:764779eedf2d	1066
andreikovacs	0:764779eedf2d	1067	/* Parameter validation */
andreikovacs	0:764779eedf2d	1068	if( state > gPhyPwrReset_c )
andreikovacs	0:764779eedf2d	1069	return gPhyInvalidParameter_c;
andreikovacs	0:764779eedf2d	1070
andreikovacs	0:764779eedf2d	1071	/* Check if the new power state = old power state */
andreikovacs	0:764779eedf2d	1072	if( state == mPhyPwrState )
andreikovacs	0:764779eedf2d	1073	return gPhyBusy_c;
andreikovacs	0:764779eedf2d	1074
andreikovacs	0:764779eedf2d	1075	/* Check if the XCVR is in reset power mode */
andreikovacs	0:764779eedf2d	1076	if( mPhyPwrState == gPhyPwrReset_c )
andreikovacs	0:764779eedf2d	1077	{
andreikovacs	0:764779eedf2d	1078	MCR20Drv_RST_B_Deassert();
andreikovacs	0:764779eedf2d	1079	/* Wait for transceiver to deassert IRQ pin */
andreikovacs	0:764779eedf2d	1080	while( MCR20Drv_IsIrqPending() );
andreikovacs	0:764779eedf2d	1081	/* Wait for transceiver wakeup from POR iterrupt */
andreikovacs	0:764779eedf2d	1082	while( !MCR20Drv_IsIrqPending() );
andreikovacs	0:764779eedf2d	1083	/* After reset, the radio is in Idle state */
andreikovacs	0:764779eedf2d	1084	mPhyPwrState = gPhyPwrIdle_c;
andreikovacs	0:764779eedf2d	1085	/* Restore default radio settings */
andreikovacs	0:764779eedf2d	1086	PhyHwInit();
andreikovacs	0:764779eedf2d	1087	}
andreikovacs	0:764779eedf2d	1088
andreikovacs	0:764779eedf2d	1089	if( state != gPhyPwrReset_c )
andreikovacs	0:764779eedf2d	1090	{
andreikovacs	0:764779eedf2d	1091	phyPWR = MCR20Drv_DirectAccessSPIRead( PWR_MODES );
andreikovacs	0:764779eedf2d	1092	xtalState = phyPWR & cPWR_MODES_XTALEN;
andreikovacs	0:764779eedf2d	1093	}
andreikovacs	0:764779eedf2d	1094
andreikovacs	0:764779eedf2d	1095	switch( state )
andreikovacs	0:764779eedf2d	1096	{
andreikovacs	0:764779eedf2d	1097	case gPhyPwrIdle_c:
andreikovacs	0:764779eedf2d	1098	phyPWR &= ~(cPWR_MODES_AUTODOZE);
andreikovacs	0:764779eedf2d	1099	phyPWR \|= (cPWR_MODES_XTALEN \| cPWR_MODES_PMC_MODE);
andreikovacs	0:764779eedf2d	1100	break;
andreikovacs	0:764779eedf2d	1101
andreikovacs	0:764779eedf2d	1102	case gPhyPwrAutodoze_c:
andreikovacs	0:764779eedf2d	1103	phyPWR \|= (cPWR_MODES_XTALEN \| cPWR_MODES_AUTODOZE \| cPWR_MODES_PMC_MODE);
andreikovacs	0:764779eedf2d	1104	break;
andreikovacs	0:764779eedf2d	1105
andreikovacs	0:764779eedf2d	1106	case gPhyPwrDoze_c:
andreikovacs	0:764779eedf2d	1107	phyPWR &= ~(cPWR_MODES_AUTODOZE \| cPWR_MODES_PMC_MODE);
andreikovacs	0:764779eedf2d	1108	phyPWR \|= cPWR_MODES_XTALEN;
andreikovacs	0:764779eedf2d	1109	break;
andreikovacs	0:764779eedf2d	1110
andreikovacs	0:764779eedf2d	1111	case gPhyPwrHibernate_c:
andreikovacs	0:764779eedf2d	1112	phyPWR &= ~(cPWR_MODES_XTALEN \| cPWR_MODES_AUTODOZE \| cPWR_MODES_PMC_MODE);
andreikovacs	0:764779eedf2d	1113	break;
andreikovacs	0:764779eedf2d	1114
andreikovacs	0:764779eedf2d	1115	case gPhyPwrReset_c:
andreikovacs	0:764779eedf2d	1116	MCR20Drv_IRQ_Disable();
andreikovacs	0:764779eedf2d	1117	mPhyPwrState = gPhyPwrReset_c;
andreikovacs	0:764779eedf2d	1118	MCR20Drv_RST_B_Assert();
andreikovacs	0:764779eedf2d	1119	return gPhySuccess_c;
andreikovacs	0:764779eedf2d	1120	}
andreikovacs	0:764779eedf2d	1121
andreikovacs	0:764779eedf2d	1122	mPhyPwrState = state;
andreikovacs	0:764779eedf2d	1123	MCR20Drv_DirectAccessSPIWrite( PWR_MODES, phyPWR );
andreikovacs	0:764779eedf2d	1124
andreikovacs	0:764779eedf2d	1125	if( !xtalState && (phyPWR & cPWR_MODES_XTALEN))
andreikovacs	0:764779eedf2d	1126	{
andreikovacs	0:764779eedf2d	1127	/* wait for crystal oscillator to complet its warmup */
andreikovacs	0:764779eedf2d	1128	while( ( MCR20Drv_DirectAccessSPIRead(PWR_MODES) & cPWR_MODES_XTAL_READY ) != cPWR_MODES_XTAL_READY);
andreikovacs	0:764779eedf2d	1129	/* wait for radio wakeup from hibernate interrupt */
andreikovacs	0:764779eedf2d	1130	while( ( MCR20Drv_DirectAccessSPIRead(IRQSTS2) & (cIRQSTS2_WAKE_IRQ \| cIRQSTS2_TMRSTATUS) ) != (cIRQSTS2_WAKE_IRQ \| cIRQSTS2_TMRSTATUS) );
andreikovacs	0:764779eedf2d	1131
andreikovacs	0:764779eedf2d	1132	MCR20Drv_DirectAccessSPIWrite(IRQSTS2, cIRQSTS2_WAKE_IRQ);
andreikovacs	0:764779eedf2d	1133	}
andreikovacs	0:764779eedf2d	1134
andreikovacs	0:764779eedf2d	1135	return gPhySuccess_c;
andreikovacs	0:764779eedf2d	1136	}

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Type:	Library
Created:	04 Apr 2016
Imports:	18
Forks:	0
Commits:	1
Dependents:	0
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Followers:	87

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PHY/PhyPacketProcessor.c@0:764779eedf2d, 2015-08-18 (annotated)

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