NXP / fsl_phy_mcr20a

A library implementing IEEE 802.15.4 PHY functionality for the MCR20A transceiver. The PHY sublayer provides two services: the PHY data service and the PHY management service interfacing to the PHY sublayer management entity (PLME) service access point (SAP) (known as PLME-SAP). The PHY data service enables the transmission and reception of PHY protocol data units (PSDUs) over the media (radio).

Fork of fsl_phy_mcr20a by Freescale

The Freescale PHY Layer deals with the physical burst which is to be sent and/or received. It performs modulation and demodulation, transmitter and receiver switching, fragmentation, scrambling, interleaving, and error correction coding. The communication to the upper protocol layers is carried out through the Layer 1 Interface.

The PHY Layer is capable of executing the following sequences:

  • I (Idle)
  • R (Receive Sequence conditionally followed by a TxAck)
  • T (Transmit Sequence)
  • C (Standalone CCA)
  • CCCA (Continuous CCA)
  • TR (Transmit/Receive Sequence - transmit unconditionally followed by either an R or RxAck)

In addition to these sequences the PHY Layer also integrates a packet processor which determines whether the packet is MAC-compliant, and if it is, whether it is addressed to the end device. Another feature of the packet processor is Source Address Matching which can be viewed as an extension of packet filtering; however its function is very specific to its intended application (data-polling and indirect queue management by a PAN Coordinator).

Documentation

MCR20A PHY Reference Manual

PHY/PhyISR.c@0:764779eedf2d, 2015-08-18 (annotated)

Committer:
andreikovacs
Date:
Tue Aug 18 12:41:42 2015 +0000
Revision:
0:764779eedf2d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
andreikovacs 0:764779eedf2d 1 /*!
andreikovacs 0:764779eedf2d 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
andreikovacs 0:764779eedf2d 3 * All rights reserved.
andreikovacs 0:764779eedf2d 4 *
andreikovacs 0:764779eedf2d 5 * \file PhyISR.c
andreikovacs 0:764779eedf2d 6 * PHY ISR Functions
andreikovacs 0:764779eedf2d 7 *
andreikovacs 0:764779eedf2d 8 * Redistribution and use in source and binary forms, with or without modification,
andreikovacs 0:764779eedf2d 9 * are permitted provided that the following conditions are met:
andreikovacs 0:764779eedf2d 10 *
andreikovacs 0:764779eedf2d 11 * o Redistributions of source code must retain the above copyright notice, this list
andreikovacs 0:764779eedf2d 12 * of conditions and the following disclaimer.
andreikovacs 0:764779eedf2d 13 *
andreikovacs 0:764779eedf2d 14 * o Redistributions in binary form must reproduce the above copyright notice, this
andreikovacs 0:764779eedf2d 15 * list of conditions and the following disclaimer in the documentation and/or
andreikovacs 0:764779eedf2d 16 * other materials provided with the distribution.
andreikovacs 0:764779eedf2d 17 *
andreikovacs 0:764779eedf2d 18 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
andreikovacs 0:764779eedf2d 19 * contributors may be used to endorse or promote products derived from this
andreikovacs 0:764779eedf2d 20 * software without specific prior written permission.
andreikovacs 0:764779eedf2d 21 *
andreikovacs 0:764779eedf2d 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
andreikovacs 0:764779eedf2d 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
andreikovacs 0:764779eedf2d 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
andreikovacs 0:764779eedf2d 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
andreikovacs 0:764779eedf2d 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
andreikovacs 0:764779eedf2d 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
andreikovacs 0:764779eedf2d 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
andreikovacs 0:764779eedf2d 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
andreikovacs 0:764779eedf2d 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
andreikovacs 0:764779eedf2d 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
andreikovacs 0:764779eedf2d 32 */
andreikovacs 0:764779eedf2d 33
andreikovacs 0:764779eedf2d 34 /************************************************************************************
andreikovacs 0:764779eedf2d 35 *************************************************************************************
andreikovacs 0:764779eedf2d 36 * Include
andreikovacs 0:764779eedf2d 37 *************************************************************************************
andreikovacs 0:764779eedf2d 38 ************************************************************************************/
andreikovacs 0:764779eedf2d 39 #include "EmbeddedTypes.h"
andreikovacs 0:764779eedf2d 40 //#include "board.h"
andreikovacs 0:764779eedf2d 41 #include "MCR20Drv.h"
andreikovacs 0:764779eedf2d 42 #include "MCR20Reg.h"
andreikovacs 0:764779eedf2d 43 #include "Phy.h"
andreikovacs 0:764779eedf2d 44 #include "PhyInterface.h"
andreikovacs 0:764779eedf2d 45 //#include "Gpio_IrqAdapter.h"
andreikovacs 0:764779eedf2d 46
andreikovacs 0:764779eedf2d 47 //#include "fsl_os_abstraction.h"
andreikovacs 0:764779eedf2d 48
andreikovacs 0:764779eedf2d 49 #include "XcvrSpi.h"
andreikovacs 0:764779eedf2d 50
andreikovacs 0:764779eedf2d 51 /************************************************************************************
andreikovacs 0:764779eedf2d 52 *************************************************************************************
andreikovacs 0:764779eedf2d 53 * Private macros
andreikovacs 0:764779eedf2d 54 *************************************************************************************
andreikovacs 0:764779eedf2d 55 ************************************************************************************/
andreikovacs 0:764779eedf2d 56 #if defined(MCU_MKL46Z4)
andreikovacs 0:764779eedf2d 57 #define MCR20_Irq_Priority (0xC0)
andreikovacs 0:764779eedf2d 58 #else
andreikovacs 0:764779eedf2d 59 #define MCR20_Irq_Priority (0x80)
andreikovacs 0:764779eedf2d 60 #endif
andreikovacs 0:764779eedf2d 61
andreikovacs 0:764779eedf2d 62 #define PHY_IRQSTS1_INDEX_c 0x00
andreikovacs 0:764779eedf2d 63 #define PHY_IRQSTS2_INDEX_c 0x01
andreikovacs 0:764779eedf2d 64 #define PHY_IRQSTS3_INDEX_c 0x02
andreikovacs 0:764779eedf2d 65 #define PHY_CTRL1_INDEX_c 0x03
andreikovacs 0:764779eedf2d 66 #define PHY_CTRL2_INDEX_c 0x04
andreikovacs 0:764779eedf2d 67 #define PHY_CTRL3_INDEX_c 0x05
andreikovacs 0:764779eedf2d 68 #define PHY_RX_FRM_LEN_INDEX_c 0x06
andreikovacs 0:764779eedf2d 69 #define PHY_CTRL4_INDEX_c 0x07
andreikovacs 0:764779eedf2d 70
andreikovacs 0:764779eedf2d 71 /************************************************************************************
andreikovacs 0:764779eedf2d 72 *************************************************************************************
andreikovacs 0:764779eedf2d 73 * Private memory declarations
andreikovacs 0:764779eedf2d 74 *************************************************************************************
andreikovacs 0:764779eedf2d 75 ************************************************************************************/
andreikovacs 0:764779eedf2d 76 extern Phy_PhyLocalStruct_t phyLocal[];
andreikovacs 0:764779eedf2d 77 static volatile phyRxParams_t * mpRxParams = NULL;
andreikovacs 0:764779eedf2d 78 static uint32_t mPhyTaskInstance;
andreikovacs 0:764779eedf2d 79 uint8_t mStatusAndControlRegs[8];
andreikovacs 0:764779eedf2d 80 uint8_t mPhyLastRxLQI = 0;
andreikovacs 0:764779eedf2d 81 uint8_t mPhyLastRxRSSI = 0;
andreikovacs 0:764779eedf2d 82
andreikovacs 0:764779eedf2d 83 void (*gpfPhyPreprocessData)(uint8_t *pData) = NULL;
andreikovacs 0:764779eedf2d 84
andreikovacs 0:764779eedf2d 85 #if gUsePBTransferThereshold_d
andreikovacs 0:764779eedf2d 86 static uint8_t mPhyWatermarkLevel;
andreikovacs 0:764779eedf2d 87 #define mPhyGetPBTransferThreshold(len) ((len) - 2)
andreikovacs 0:764779eedf2d 88 //#define mPhyGetPBTransferThreshold(len) ((len)*93/100)
andreikovacs 0:764779eedf2d 89 //#define mPhyGetPBTransferThreshold(len) (((len) < 20) ? ((len) - 2) : ((len) * 93 / 100))
andreikovacs 0:764779eedf2d 90 #endif
andreikovacs 0:764779eedf2d 91
andreikovacs 0:764779eedf2d 92 /************************************************************************************
andreikovacs 0:764779eedf2d 93 *************************************************************************************
andreikovacs 0:764779eedf2d 94 * Public functions
andreikovacs 0:764779eedf2d 95 *************************************************************************************
andreikovacs 0:764779eedf2d 96 ************************************************************************************/
andreikovacs 0:764779eedf2d 97
andreikovacs 0:764779eedf2d 98 /*! *********************************************************************************
andreikovacs 0:764779eedf2d 99 * \brief Sets the current PHY instance waiting for an IRQ
andreikovacs 0:764779eedf2d 100 *
andreikovacs 0:764779eedf2d 101 * \param[in] instanceId instance of the PHY
andreikovacs 0:764779eedf2d 102 *
andreikovacs 0:764779eedf2d 103 ********************************************************************************** */
andreikovacs 0:764779eedf2d 104 void PhyIsrPassTaskParams
andreikovacs 0:764779eedf2d 105 (
andreikovacs 0:764779eedf2d 106 instanceId_t instanceId
andreikovacs 0:764779eedf2d 107 )
andreikovacs 0:764779eedf2d 108 {
andreikovacs 0:764779eedf2d 109 mPhyTaskInstance = instanceId;
andreikovacs 0:764779eedf2d 110 }
andreikovacs 0:764779eedf2d 111
andreikovacs 0:764779eedf2d 112 /*! *********************************************************************************
andreikovacs 0:764779eedf2d 113 * \brief Sets the location of the Rx parameters
andreikovacs 0:764779eedf2d 114 *
andreikovacs 0:764779eedf2d 115 * \param[in] pRxParam pointer to Rx parameters
andreikovacs 0:764779eedf2d 116 *
andreikovacs 0:764779eedf2d 117 ********************************************************************************** */
andreikovacs 0:764779eedf2d 118 void PhyIsrPassRxParams
andreikovacs 0:764779eedf2d 119 (
andreikovacs 0:764779eedf2d 120 volatile phyRxParams_t * pRxParam
andreikovacs 0:764779eedf2d 121 )
andreikovacs 0:764779eedf2d 122 {
andreikovacs 0:764779eedf2d 123 mpRxParams = pRxParam;
andreikovacs 0:764779eedf2d 124 }
andreikovacs 0:764779eedf2d 125
andreikovacs 0:764779eedf2d 126 /*! *********************************************************************************
andreikovacs 0:764779eedf2d 127 * \brief Clear and mask PHY IRQ, set sequence to Idle
andreikovacs 0:764779eedf2d 128 *
andreikovacs 0:764779eedf2d 129 ********************************************************************************** */
andreikovacs 0:764779eedf2d 130 void PhyIsrSeqCleanup
andreikovacs 0:764779eedf2d 131 (
andreikovacs 0:764779eedf2d 132 void
andreikovacs 0:764779eedf2d 133 )
andreikovacs 0:764779eedf2d 134 {
andreikovacs 0:764779eedf2d 135 mStatusAndControlRegs[PHY_IRQSTS3_INDEX_c] &= 0xF0;
andreikovacs 0:764779eedf2d 136 mStatusAndControlRegs[PHY_IRQSTS3_INDEX_c] &= (uint8_t) ~( cIRQSTS3_TMR3MSK ); // unmask TMR3 interrupt
andreikovacs 0:764779eedf2d 137 mStatusAndControlRegs[PHY_CTRL1_INDEX_c] &= (uint8_t) ~( cPHY_CTRL1_XCVSEQ );
andreikovacs 0:764779eedf2d 138 mStatusAndControlRegs[PHY_CTRL2_INDEX_c] |= (uint8_t) ( cPHY_CTRL2_CCAMSK | \
andreikovacs 0:764779eedf2d 139 cPHY_CTRL2_RXMSK | \
andreikovacs 0:764779eedf2d 140 cPHY_CTRL2_TXMSK | \
andreikovacs 0:764779eedf2d 141 cPHY_CTRL2_SEQMSK );
andreikovacs 0:764779eedf2d 142
andreikovacs 0:764779eedf2d 143 // clear transceiver interrupts, mask SEQ, RX, TX and CCA interrupts and set the PHY sequencer back to IDLE
andreikovacs 0:764779eedf2d 144 MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, mStatusAndControlRegs, 5);
andreikovacs 0:764779eedf2d 145 }
andreikovacs 0:764779eedf2d 146
andreikovacs 0:764779eedf2d 147 /*! *********************************************************************************
andreikovacs 0:764779eedf2d 148 * \brief Clear and mask PHY IRQ, disable timeout, set sequence to Idle
andreikovacs 0:764779eedf2d 149 *
andreikovacs 0:764779eedf2d 150 ********************************************************************************** */
andreikovacs 0:764779eedf2d 151 void PhyIsrTimeoutCleanup
andreikovacs 0:764779eedf2d 152 (
andreikovacs 0:764779eedf2d 153 void
andreikovacs 0:764779eedf2d 154 )
andreikovacs 0:764779eedf2d 155 {
andreikovacs 0:764779eedf2d 156 mStatusAndControlRegs[PHY_IRQSTS3_INDEX_c] &= 0xF0;
andreikovacs 0:764779eedf2d 157 mStatusAndControlRegs[PHY_IRQSTS3_INDEX_c] |= (uint8_t) ( cIRQSTS3_TMR3MSK | \
andreikovacs 0:764779eedf2d 158 cIRQSTS3_TMR3IRQ); // mask and clear TMR3 interrupt
andreikovacs 0:764779eedf2d 159 mStatusAndControlRegs[PHY_CTRL1_INDEX_c] &= (uint8_t) ~( cPHY_CTRL1_XCVSEQ );
andreikovacs 0:764779eedf2d 160 mStatusAndControlRegs[PHY_CTRL2_INDEX_c] |= (uint8_t) ( cPHY_CTRL2_CCAMSK | \
andreikovacs 0:764779eedf2d 161 cPHY_CTRL2_RXMSK | \
andreikovacs 0:764779eedf2d 162 cPHY_CTRL2_TXMSK | \
andreikovacs 0:764779eedf2d 163 cPHY_CTRL2_SEQMSK );
andreikovacs 0:764779eedf2d 164
andreikovacs 0:764779eedf2d 165 // disable TMR3 comparator and timeout
andreikovacs 0:764779eedf2d 166 mStatusAndControlRegs[PHY_CTRL3_INDEX_c] &= (uint8_t) ~( cPHY_CTRL3_TMR3CMP_EN );
andreikovacs 0:764779eedf2d 167 mStatusAndControlRegs[PHY_CTRL4_INDEX_c] &= (uint8_t) ~( cPHY_CTRL4_TC3TMOUT );
andreikovacs 0:764779eedf2d 168
andreikovacs 0:764779eedf2d 169 // clear transceiver interrupts, mask mask SEQ, RX, TX, TMR3 and CCA interrupts interrupts and set the PHY sequencer back to IDLE
andreikovacs 0:764779eedf2d 170 MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, mStatusAndControlRegs, 8);
andreikovacs 0:764779eedf2d 171 }
andreikovacs 0:764779eedf2d 172
andreikovacs 0:764779eedf2d 173 /*! *********************************************************************************
andreikovacs 0:764779eedf2d 174 * \brief Scales energy level to 0-255
andreikovacs 0:764779eedf2d 175 *
andreikovacs 0:764779eedf2d 176 * \param[in] energyLevel the energ level reported by HW
andreikovacs 0:764779eedf2d 177 *
andreikovacs 0:764779eedf2d 178 * \return uint8_t the energy level scaled in 0x00-0xFF
andreikovacs 0:764779eedf2d 179 *
andreikovacs 0:764779eedf2d 180 ********************************************************************************** */
andreikovacs 0:764779eedf2d 181 uint8_t Phy_GetEnergyLevel
andreikovacs 0:764779eedf2d 182 (
andreikovacs 0:764779eedf2d 183 uint8_t energyLevel /* db */
andreikovacs 0:764779eedf2d 184 )
andreikovacs 0:764779eedf2d 185 {
andreikovacs 0:764779eedf2d 186 if(energyLevel >= 90)
andreikovacs 0:764779eedf2d 187 {
andreikovacs 0:764779eedf2d 188 /* ED value is below minimum. Return 0x00. */
andreikovacs 0:764779eedf2d 189 energyLevel = 0x00;
andreikovacs 0:764779eedf2d 190 }
andreikovacs 0:764779eedf2d 191 else if(energyLevel <= 26)
andreikovacs 0:764779eedf2d 192 {
andreikovacs 0:764779eedf2d 193 /* ED value is above maximum. Return 0xFF. */
andreikovacs 0:764779eedf2d 194 energyLevel = 0xFF;
andreikovacs 0:764779eedf2d 195 }
andreikovacs 0:764779eedf2d 196 else
andreikovacs 0:764779eedf2d 197 {
andreikovacs 0:764779eedf2d 198 /* Energy level (-90 dBm to -26 dBm ) --> varies form 0 to 64 */
andreikovacs 0:764779eedf2d 199 energyLevel = (90 - energyLevel);
andreikovacs 0:764779eedf2d 200 /* Rescale the energy level values to the 0x00-0xff range (0 to 64 translates in 0 to 255) */
andreikovacs 0:764779eedf2d 201 /* energyLevel * 3.9844 ~= 4 */
andreikovacs 0:764779eedf2d 202 /* Multiply with 4=2^2 by shifting left.
andreikovacs 0:764779eedf2d 203 The multiplication will not overflow beacause energyLevel has values between 0 and 63 */
andreikovacs 0:764779eedf2d 204 energyLevel <<= 2;
andreikovacs 0:764779eedf2d 205 }
andreikovacs 0:764779eedf2d 206
andreikovacs 0:764779eedf2d 207 return energyLevel;
andreikovacs 0:764779eedf2d 208 }
andreikovacs 0:764779eedf2d 209
andreikovacs 0:764779eedf2d 210 /*! *********************************************************************************
andreikovacs 0:764779eedf2d 211 * \brief Scales LQI to 0-255
andreikovacs 0:764779eedf2d 212 *
andreikovacs 0:764779eedf2d 213 * \param[in] hwLqi the LQI reported by HW
andreikovacs 0:764779eedf2d 214 *
andreikovacs 0:764779eedf2d 215 * \return uint8_t the LQI scaled in 0x00-0xFF
andreikovacs 0:764779eedf2d 216 *
andreikovacs 0:764779eedf2d 217 ********************************************************************************** */
andreikovacs 0:764779eedf2d 218 static uint8_t Phy_LqiConvert
andreikovacs 0:764779eedf2d 219 (
andreikovacs 0:764779eedf2d 220 uint8_t hwLqi
andreikovacs 0:764779eedf2d 221 )
andreikovacs 0:764779eedf2d 222 {
andreikovacs 0:764779eedf2d 223 uint32_t tmpLQI;
andreikovacs 0:764779eedf2d 224
andreikovacs 0:764779eedf2d 225 /* LQI Saturation Level */
andreikovacs 0:764779eedf2d 226 if (hwLqi >= 230)
andreikovacs 0:764779eedf2d 227 {
andreikovacs 0:764779eedf2d 228 return 0xFF;
andreikovacs 0:764779eedf2d 229 }
andreikovacs 0:764779eedf2d 230 else if (hwLqi <= 9)
andreikovacs 0:764779eedf2d 231 {
andreikovacs 0:764779eedf2d 232 return 0;
andreikovacs 0:764779eedf2d 233 }
andreikovacs 0:764779eedf2d 234 else
andreikovacs 0:764779eedf2d 235 {
andreikovacs 0:764779eedf2d 236 /* Rescale the LQI values from min to saturation to the 0x00 - 0xFF range */
andreikovacs 0:764779eedf2d 237 /* The LQI value mst be multiplied by ~1.1087 */
andreikovacs 0:764779eedf2d 238 /* tmpLQI = hwLqi * 7123 ~= hwLqi * 65536 * 0.1087 = hwLqi * 2^16 * 0.1087*/
andreikovacs 0:764779eedf2d 239 tmpLQI = ((uint32_t)hwLqi * (uint32_t)7123 );
andreikovacs 0:764779eedf2d 240 /* tmpLQI = (tmpLQI / 2^16) + hwLqi */
andreikovacs 0:764779eedf2d 241 tmpLQI = (uint32_t)(tmpLQI >> 16) + (uint32_t)hwLqi;
andreikovacs 0:764779eedf2d 242
andreikovacs 0:764779eedf2d 243 return (uint8_t)tmpLQI;
andreikovacs 0:764779eedf2d 244 }
andreikovacs 0:764779eedf2d 245 }
andreikovacs 0:764779eedf2d 246
andreikovacs 0:764779eedf2d 247 /*! *********************************************************************************
andreikovacs 0:764779eedf2d 248 * \brief This function returns the LQI for the las received packet
andreikovacs 0:764779eedf2d 249 *
andreikovacs 0:764779eedf2d 250 * \return uint8_t LQI value
andreikovacs 0:764779eedf2d 251 *
andreikovacs 0:764779eedf2d 252 ********************************************************************************** */
andreikovacs 0:764779eedf2d 253 uint8_t PhyGetLastRxLqiValue(void)
andreikovacs 0:764779eedf2d 254 {
andreikovacs 0:764779eedf2d 255 return mPhyLastRxLQI;
andreikovacs 0:764779eedf2d 256 }
andreikovacs 0:764779eedf2d 257
andreikovacs 0:764779eedf2d 258 /*! *********************************************************************************
andreikovacs 0:764779eedf2d 259 * \brief This function returns the RSSI for the las received packet
andreikovacs 0:764779eedf2d 260 *
andreikovacs 0:764779eedf2d 261 * \return uint8_t RSSI value
andreikovacs 0:764779eedf2d 262 *
andreikovacs 0:764779eedf2d 263 ********************************************************************************** */
andreikovacs 0:764779eedf2d 264 uint8_t PhyGetLastRxRssiValue(void)
andreikovacs 0:764779eedf2d 265 {
andreikovacs 0:764779eedf2d 266 uint32_t tempRSSI = mPhyLastRxRSSI;
andreikovacs 0:764779eedf2d 267 uint8_t comp = MCR20Drv_IndirectAccessSPIRead(LQI_OFFSET_COMP);
andreikovacs 0:764779eedf2d 268 tempRSSI += comp;
andreikovacs 0:764779eedf2d 269 tempRSSI >>= 1;
andreikovacs 0:764779eedf2d 270 comp >>=1;
andreikovacs 0:764779eedf2d 271 if(25*(tempRSSI+comp) > 4360)
andreikovacs 0:764779eedf2d 272 {
andreikovacs 0:764779eedf2d 273 return mPhyLastRxRSSI;
andreikovacs 0:764779eedf2d 274 }
andreikovacs 0:764779eedf2d 275 /*liniarization
andreikovacs 0:764779eedf2d 276 4360 - 25* RSSI (4360 - 25* RSSI)*7085 >> 18;
andreikovacs 0:764779eedf2d 277 abs(rssi)=--------------- <=>
andreikovacs 0:764779eedf2d 278 37
andreikovacs 0:764779eedf2d 279 */
andreikovacs 0:764779eedf2d 280 tempRSSI = ((4360 - 25*(tempRSSI + comp))*7085)>>18;
andreikovacs 0:764779eedf2d 281 return (uint8_t)(0x000000FF & tempRSSI);
andreikovacs 0:764779eedf2d 282 }
andreikovacs 0:764779eedf2d 283
andreikovacs 0:764779eedf2d 284 /*! *********************************************************************************
andreikovacs 0:764779eedf2d 285 * \brief PHY ISR
andreikovacs 0:764779eedf2d 286 *
andreikovacs 0:764779eedf2d 287 ********************************************************************************** */
andreikovacs 0:764779eedf2d 288 void PHY_InterruptHandler(void)
andreikovacs 0:764779eedf2d 289 {
andreikovacs 0:764779eedf2d 290 uint8_t xcvseqCopy;
andreikovacs 0:764779eedf2d 291
andreikovacs 0:764779eedf2d 292 /* The ISR may be called even if another PORTx pin has changed */
andreikovacs 0:764779eedf2d 293 //if( !PORT_HAL_IsPinIntPending(g_portBaseAddr[GPIO_EXTRACT_PORT(kGpioXcvrIrqPin)], GPIO_EXTRACT_PIN(kGpioXcvrIrqPin)) )
andreikovacs 0:764779eedf2d 294 if( !RF_isIRQ_Pending() )
andreikovacs 0:764779eedf2d 295 {
andreikovacs 0:764779eedf2d 296 return;
andreikovacs 0:764779eedf2d 297 }
andreikovacs 0:764779eedf2d 298
andreikovacs 0:764779eedf2d 299 /* Disable and clear transceiver(IRQ_B) interrupt */
andreikovacs 0:764779eedf2d 300 MCR20Drv_IRQ_Disable();
andreikovacs 0:764779eedf2d 301 MCR20Drv_IRQ_Clear();
andreikovacs 0:764779eedf2d 302
andreikovacs 0:764779eedf2d 303 /* Read transceiver interrupt status and control registers */
andreikovacs 0:764779eedf2d 304 mStatusAndControlRegs[PHY_IRQSTS1_INDEX_c] =
andreikovacs 0:764779eedf2d 305 MCR20Drv_DirectAccessSPIMultiByteRead(IRQSTS2, &mStatusAndControlRegs[1], 7);
andreikovacs 0:764779eedf2d 306 xcvseqCopy = mStatusAndControlRegs[PHY_CTRL1_INDEX_c] & cPHY_CTRL1_XCVSEQ;
andreikovacs 0:764779eedf2d 307 /* clear transceiver interrupts */
andreikovacs 0:764779eedf2d 308 MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, mStatusAndControlRegs, 3);
andreikovacs 0:764779eedf2d 309
andreikovacs 0:764779eedf2d 310 if( (mStatusAndControlRegs[PHY_IRQSTS2_INDEX_c] & cIRQSTS2_WAKE_IRQ) &&
andreikovacs 0:764779eedf2d 311 !(mStatusAndControlRegs[PHY_CTRL3_INDEX_c] & cPHY_CTRL3_WAKE_MSK) )
andreikovacs 0:764779eedf2d 312 {
andreikovacs 0:764779eedf2d 313 #ifdef MAC_PHY_DEBUG
andreikovacs 0:764779eedf2d 314 Radio_Phy_UnexpectedTransceiverReset(mPhyTaskInstance);
andreikovacs 0:764779eedf2d 315 #endif
andreikovacs 0:764779eedf2d 316 MCR20Drv_IRQ_Enable();
andreikovacs 0:764779eedf2d 317 return;
andreikovacs 0:764779eedf2d 318 }
andreikovacs 0:764779eedf2d 319
andreikovacs 0:764779eedf2d 320 /* Flter Fail IRQ */
andreikovacs 0:764779eedf2d 321 if( (mStatusAndControlRegs[PHY_IRQSTS1_INDEX_c] & cIRQSTS1_FILTERFAIL_IRQ) &&
andreikovacs 0:764779eedf2d 322 !(mStatusAndControlRegs[PHY_CTRL2_INDEX_c] & cPHY_CTRL2_FILTERFAIL_MSK) )
andreikovacs 0:764779eedf2d 323 {
andreikovacs 0:764779eedf2d 324 #if gUsePBTransferThereshold_d
andreikovacs 0:764779eedf2d 325 /* Reset the RX_WTR_MARK level since packet was dropped. */
andreikovacs 0:764779eedf2d 326 mPhyWatermarkLevel = 0;
andreikovacs 0:764779eedf2d 327 MCR20Drv_IndirectAccessSPIWrite(RX_WTR_MARK, mPhyWatermarkLevel);
andreikovacs 0:764779eedf2d 328 #endif
andreikovacs 0:764779eedf2d 329 Radio_Phy_PlmeFilterFailRx(mPhyTaskInstance);
andreikovacs 0:764779eedf2d 330 }
andreikovacs 0:764779eedf2d 331 /* Rx Watermark IRQ */
andreikovacs 0:764779eedf2d 332 else if( (mStatusAndControlRegs[PHY_IRQSTS1_INDEX_c] & cIRQSTS1_RXWTRMRKIRQ) &&
andreikovacs 0:764779eedf2d 333 !(mStatusAndControlRegs[PHY_CTRL2_INDEX_c] & cPHY_CTRL2_RX_WMRK_MSK) )
andreikovacs 0:764779eedf2d 334 {
andreikovacs 0:764779eedf2d 335 #if gUsePBTransferThereshold_d
andreikovacs 0:764779eedf2d 336 if( 0 == mPhyWatermarkLevel )
andreikovacs 0:764779eedf2d 337 {
andreikovacs 0:764779eedf2d 338 /* Check if this is a standalone RX because we could end up here during a TR sequence also. */
andreikovacs 0:764779eedf2d 339 if( xcvseqCopy == gRX_c )
andreikovacs 0:764779eedf2d 340 {
andreikovacs 0:764779eedf2d 341 /* Set the thereshold packet length at which to start the PB Burst Read.*/
andreikovacs 0:764779eedf2d 342 mPhyWatermarkLevel = mPhyGetPBTransferThreshold( mStatusAndControlRegs[PHY_RX_FRM_LEN_INDEX_c] );
andreikovacs 0:764779eedf2d 343 MCR20Drv_IndirectAccessSPIWrite(RX_WTR_MARK, mPhyWatermarkLevel);
andreikovacs 0:764779eedf2d 344 }
andreikovacs 0:764779eedf2d 345 #endif
andreikovacs 0:764779eedf2d 346 Radio_Phy_PlmeRxSfdDetect(mPhyTaskInstance, mStatusAndControlRegs[PHY_RX_FRM_LEN_INDEX_c]);
andreikovacs 0:764779eedf2d 347 #if gUsePBTransferThereshold_d
andreikovacs 0:764779eedf2d 348 }
andreikovacs 0:764779eedf2d 349 else
andreikovacs 0:764779eedf2d 350 {
andreikovacs 0:764779eedf2d 351 /* Reset RX_WTR_MARK here, because if the FCS fails, no other IRQ will arrive
andreikovacs 0:764779eedf2d 352 * and the RX will restart automatically. */
andreikovacs 0:764779eedf2d 353 mPhyWatermarkLevel = 0;
andreikovacs 0:764779eedf2d 354 MCR20Drv_IndirectAccessSPIWrite(RX_WTR_MARK, mPhyWatermarkLevel);
andreikovacs 0:764779eedf2d 355
andreikovacs 0:764779eedf2d 356 if( mpRxParams )
andreikovacs 0:764779eedf2d 357 {
andreikovacs 0:764779eedf2d 358 // Read data from PB
andreikovacs 0:764779eedf2d 359 MCR20Drv_PB_SPIBurstRead(mpRxParams->pRxData->msgData.dataInd.pPsdu, (uint8_t)(mStatusAndControlRegs[PHY_RX_FRM_LEN_INDEX_c] - 2));
andreikovacs 0:764779eedf2d 360 if( gpfPhyPreprocessData )
andreikovacs 0:764779eedf2d 361 gpfPhyPreprocessData(mpRxParams->pRxData->msgData.dataInd.pPsdu);
andreikovacs 0:764779eedf2d 362 }
andreikovacs 0:764779eedf2d 363 }
andreikovacs 0:764779eedf2d 364 #endif
andreikovacs 0:764779eedf2d 365 }
andreikovacs 0:764779eedf2d 366
andreikovacs 0:764779eedf2d 367 /* Timer 1 Compare Match */
andreikovacs 0:764779eedf2d 368 if( (mStatusAndControlRegs[PHY_IRQSTS3_INDEX_c] & cIRQSTS3_TMR1IRQ) &&
andreikovacs 0:764779eedf2d 369 !(mStatusAndControlRegs[PHY_IRQSTS3_INDEX_c] & cIRQSTS3_TMR1MSK))
andreikovacs 0:764779eedf2d 370 {
andreikovacs 0:764779eedf2d 371 // disable TMR1 comparator
andreikovacs 0:764779eedf2d 372 mStatusAndControlRegs[PHY_CTRL3_INDEX_c] &= (uint8_t) ~( cPHY_CTRL3_TMR1CMP_EN);
andreikovacs 0:764779eedf2d 373 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL3, mStatusAndControlRegs[PHY_CTRL3_INDEX_c]);
andreikovacs 0:764779eedf2d 374
andreikovacs 0:764779eedf2d 375 Radio_Phy_TimeWaitTimeoutIndication(mPhyTaskInstance);
andreikovacs 0:764779eedf2d 376 }
andreikovacs 0:764779eedf2d 377
andreikovacs 0:764779eedf2d 378 /* Sequencer interrupt, the autosequence has completed */
andreikovacs 0:764779eedf2d 379 if( (mStatusAndControlRegs[PHY_IRQSTS1_INDEX_c] & cIRQSTS1_SEQIRQ) &&
andreikovacs 0:764779eedf2d 380 !(mStatusAndControlRegs[PHY_CTRL2_INDEX_c] & cPHY_CTRL2_SEQMSK) )
andreikovacs 0:764779eedf2d 381 {
andreikovacs 0:764779eedf2d 382 // PLL unlock, the autosequence has been aborted due to PLL unlock
andreikovacs 0:764779eedf2d 383 if( mStatusAndControlRegs[PHY_IRQSTS1_INDEX_c] & cIRQSTS1_PLL_UNLOCK_IRQ )
andreikovacs 0:764779eedf2d 384 {
andreikovacs 0:764779eedf2d 385 PhyIsrSeqCleanup();
andreikovacs 0:764779eedf2d 386 Radio_Phy_PlmeSyncLossIndication(mPhyTaskInstance);
andreikovacs 0:764779eedf2d 387 MCR20Drv_IRQ_Enable();
andreikovacs 0:764779eedf2d 388 return;
andreikovacs 0:764779eedf2d 389 }
andreikovacs 0:764779eedf2d 390
andreikovacs 0:764779eedf2d 391 // TMR3 timeout, the autosequence has been aborted due to TMR3 timeout
andreikovacs 0:764779eedf2d 392 if( (mStatusAndControlRegs[PHY_IRQSTS3_INDEX_c] & cIRQSTS3_TMR3IRQ) &&
andreikovacs 0:764779eedf2d 393 !(mStatusAndControlRegs[PHY_IRQSTS1_INDEX_c] & cIRQSTS1_RXIRQ) &&
andreikovacs 0:764779eedf2d 394 (gTX_c != xcvseqCopy) )
andreikovacs 0:764779eedf2d 395 {
andreikovacs 0:764779eedf2d 396 PhyIsrTimeoutCleanup();
andreikovacs 0:764779eedf2d 397
andreikovacs 0:764779eedf2d 398 Radio_Phy_TimeRxTimeoutIndication(mPhyTaskInstance);
andreikovacs 0:764779eedf2d 399 MCR20Drv_IRQ_Enable();
andreikovacs 0:764779eedf2d 400 return;
andreikovacs 0:764779eedf2d 401 }
andreikovacs 0:764779eedf2d 402
andreikovacs 0:764779eedf2d 403 PhyIsrSeqCleanup();
andreikovacs 0:764779eedf2d 404
andreikovacs 0:764779eedf2d 405 switch(xcvseqCopy)
andreikovacs 0:764779eedf2d 406 {
andreikovacs 0:764779eedf2d 407 case gTX_c:
andreikovacs 0:764779eedf2d 408 if( (mStatusAndControlRegs[PHY_IRQSTS2_INDEX_c] & cIRQSTS2_CCA) &&
andreikovacs 0:764779eedf2d 409 (mStatusAndControlRegs[PHY_CTRL1_INDEX_c] & cPHY_CTRL1_CCABFRTX) )
andreikovacs 0:764779eedf2d 410 {
andreikovacs 0:764779eedf2d 411 Radio_Phy_PlmeCcaConfirm(gPhyChannelBusy_c, mPhyTaskInstance);
andreikovacs 0:764779eedf2d 412 }
andreikovacs 0:764779eedf2d 413 else
andreikovacs 0:764779eedf2d 414 {
andreikovacs 0:764779eedf2d 415 Radio_Phy_PdDataConfirm(mPhyTaskInstance, FALSE);
andreikovacs 0:764779eedf2d 416 }
andreikovacs 0:764779eedf2d 417 break;
andreikovacs 0:764779eedf2d 418
andreikovacs 0:764779eedf2d 419 case gTR_c:
andreikovacs 0:764779eedf2d 420 if( (mStatusAndControlRegs[PHY_IRQSTS2_INDEX_c] & cIRQSTS2_CCA) &&
andreikovacs 0:764779eedf2d 421 (mStatusAndControlRegs[PHY_CTRL1_INDEX_c] & cPHY_CTRL1_CCABFRTX) )
andreikovacs 0:764779eedf2d 422 {
andreikovacs 0:764779eedf2d 423 Radio_Phy_PlmeCcaConfirm(gPhyChannelBusy_c, mPhyTaskInstance);
andreikovacs 0:764779eedf2d 424 }
andreikovacs 0:764779eedf2d 425 else
andreikovacs 0:764779eedf2d 426 {
andreikovacs 0:764779eedf2d 427 if(NULL != mpRxParams)
andreikovacs 0:764779eedf2d 428 {
andreikovacs 0:764779eedf2d 429 // reports value of 0x00 for -105 dBm of received input power and 0xFF for 0 dBm of received input power
andreikovacs 0:764779eedf2d 430 mPhyLastRxRSSI = MCR20Drv_DirectAccessSPIRead((uint8_t) LQI_VALUE);
andreikovacs 0:764779eedf2d 431 mpRxParams->linkQuality = Phy_LqiConvert(mPhyLastRxRSSI);
andreikovacs 0:764779eedf2d 432 mPhyLastRxLQI = mpRxParams->linkQuality;
andreikovacs 0:764779eedf2d 433 MCR20Drv_DirectAccessSPIMultiByteRead( (uint8_t) TIMESTAMP_LSB, (uint8_t *)&mpRxParams->timeStamp, 3);
andreikovacs 0:764779eedf2d 434 mpRxParams->psduLength = (uint8_t)(mStatusAndControlRegs[PHY_RX_FRM_LEN_INDEX_c]); //Including FCS (2 bytes)
andreikovacs 0:764779eedf2d 435 }
andreikovacs 0:764779eedf2d 436 if( (mStatusAndControlRegs[PHY_IRQSTS1_INDEX_c] & cIRQSTS1_RX_FRM_PEND) == cIRQSTS1_RX_FRM_PEND )
andreikovacs 0:764779eedf2d 437 {
andreikovacs 0:764779eedf2d 438 Radio_Phy_PdDataConfirm(mPhyTaskInstance, TRUE);
andreikovacs 0:764779eedf2d 439 }
andreikovacs 0:764779eedf2d 440 else
andreikovacs 0:764779eedf2d 441 {
andreikovacs 0:764779eedf2d 442 Radio_Phy_PdDataConfirm(mPhyTaskInstance, FALSE);
andreikovacs 0:764779eedf2d 443 }
andreikovacs 0:764779eedf2d 444 }
andreikovacs 0:764779eedf2d 445 break;
andreikovacs 0:764779eedf2d 446
andreikovacs 0:764779eedf2d 447 case gRX_c:
andreikovacs 0:764779eedf2d 448 if( NULL != mpRxParams )
andreikovacs 0:764779eedf2d 449 {
andreikovacs 0:764779eedf2d 450 // reports value of 0x00 for -105 dBm of received input power and 0xFF for 0 dBm of received input power
andreikovacs 0:764779eedf2d 451 mPhyLastRxRSSI = MCR20Drv_DirectAccessSPIRead((uint8_t) LQI_VALUE);
andreikovacs 0:764779eedf2d 452 mpRxParams->linkQuality = Phy_LqiConvert(mPhyLastRxRSSI);
andreikovacs 0:764779eedf2d 453 mPhyLastRxLQI = mpRxParams->linkQuality;
andreikovacs 0:764779eedf2d 454 MCR20Drv_DirectAccessSPIMultiByteRead( (uint8_t) TIMESTAMP_LSB, (uint8_t *)&mpRxParams->timeStamp, 3);
andreikovacs 0:764779eedf2d 455 mpRxParams->psduLength = (uint8_t)(mStatusAndControlRegs[PHY_RX_FRM_LEN_INDEX_c]); //Including FCS (2 bytes)
andreikovacs 0:764779eedf2d 456 }
andreikovacs 0:764779eedf2d 457 Radio_Phy_PdDataIndication(mPhyTaskInstance);
andreikovacs 0:764779eedf2d 458 break;
andreikovacs 0:764779eedf2d 459
andreikovacs 0:764779eedf2d 460 case gCCA_c:
andreikovacs 0:764779eedf2d 461 if( (mStatusAndControlRegs[PHY_CTRL4_INDEX_c] & (cPHY_CTRL4_CCATYPE << cPHY_CTRL4_CCATYPE_Shift_c)) == (gCcaED_c << cPHY_CTRL4_CCATYPE_Shift_c) )
andreikovacs 0:764779eedf2d 462 {
andreikovacs 0:764779eedf2d 463 // Ed
andreikovacs 0:764779eedf2d 464 Radio_Phy_PlmeEdConfirm(MCR20Drv_DirectAccessSPIRead((uint8_t) CCA1_ED_FNL), mPhyTaskInstance);
andreikovacs 0:764779eedf2d 465 }
andreikovacs 0:764779eedf2d 466 else
andreikovacs 0:764779eedf2d 467 {
andreikovacs 0:764779eedf2d 468 // CCA
andreikovacs 0:764779eedf2d 469 if( mStatusAndControlRegs[PHY_IRQSTS2_INDEX_c] & cIRQSTS2_CCA )
andreikovacs 0:764779eedf2d 470 {
andreikovacs 0:764779eedf2d 471 #if (gUseStandaloneCCABeforeTx_d == 1)
andreikovacs 0:764779eedf2d 472 phyLocal[mPhyTaskInstance].txParams.numOfCca = 0;
andreikovacs 0:764779eedf2d 473 #endif
andreikovacs 0:764779eedf2d 474 Radio_Phy_PlmeCcaConfirm(gPhyChannelBusy_c, mPhyTaskInstance);
andreikovacs 0:764779eedf2d 475 }
andreikovacs 0:764779eedf2d 476 else
andreikovacs 0:764779eedf2d 477 {
andreikovacs 0:764779eedf2d 478 #if (gUseStandaloneCCABeforeTx_d == 1)
andreikovacs 0:764779eedf2d 479 if( phyLocal[mPhyTaskInstance].txParams.numOfCca > 0 )
andreikovacs 0:764779eedf2d 480 {
andreikovacs 0:764779eedf2d 481 mStatusAndControlRegs[PHY_CTRL1] &= (uint8_t) ~(cPHY_CTRL1_XCVSEQ);
andreikovacs 0:764779eedf2d 482
andreikovacs 0:764779eedf2d 483 if( --phyLocal[mPhyTaskInstance].txParams.numOfCca == 0 )
andreikovacs 0:764779eedf2d 484 {
andreikovacs 0:764779eedf2d 485 // perform TxRxAck sequence if required by phyTxMode
andreikovacs 0:764779eedf2d 486 if( gPhyRxAckRqd_c == phyLocal[mPhyTaskInstance].txParams.ackRequired )
andreikovacs 0:764779eedf2d 487 {
andreikovacs 0:764779eedf2d 488 mStatusAndControlRegs[PHY_CTRL1] |= (uint8_t) (cPHY_CTRL1_RXACKRQD);
andreikovacs 0:764779eedf2d 489 mStatusAndControlRegs[PHY_CTRL1] |= gTR_c;
andreikovacs 0:764779eedf2d 490 }
andreikovacs 0:764779eedf2d 491 else
andreikovacs 0:764779eedf2d 492 {
andreikovacs 0:764779eedf2d 493 mStatusAndControlRegs[PHY_CTRL1] &= (uint8_t) ~(cPHY_CTRL1_RXACKRQD);
andreikovacs 0:764779eedf2d 494 mStatusAndControlRegs[PHY_CTRL1] |= gTX_c;
andreikovacs 0:764779eedf2d 495 }
andreikovacs 0:764779eedf2d 496 }
andreikovacs 0:764779eedf2d 497 else
andreikovacs 0:764779eedf2d 498 {
andreikovacs 0:764779eedf2d 499 mStatusAndControlRegs[PHY_CTRL1] |= gCCA_c;
andreikovacs 0:764779eedf2d 500 }
andreikovacs 0:764779eedf2d 501
andreikovacs 0:764779eedf2d 502 mStatusAndControlRegs[PHY_CTRL2] &= (uint8_t) ~(cPHY_CTRL2_SEQMSK); // unmask SEQ interrupt
andreikovacs 0:764779eedf2d 503 // start the sequence immediately
andreikovacs 0:764779eedf2d 504 MCR20Drv_DirectAccessSPIMultiByteWrite(PHY_CTRL1,
andreikovacs 0:764779eedf2d 505 &mStatusAndControlRegs[PHY_CTRL1],
andreikovacs 0:764779eedf2d 506 2);
andreikovacs 0:764779eedf2d 507 }
andreikovacs 0:764779eedf2d 508 else
andreikovacs 0:764779eedf2d 509 #endif
andreikovacs 0:764779eedf2d 510 {
andreikovacs 0:764779eedf2d 511 Radio_Phy_PlmeCcaConfirm(gPhyChannelIdle_c, mPhyTaskInstance);
andreikovacs 0:764779eedf2d 512 }
andreikovacs 0:764779eedf2d 513 }
andreikovacs 0:764779eedf2d 514 }
andreikovacs 0:764779eedf2d 515 break;
andreikovacs 0:764779eedf2d 516
andreikovacs 0:764779eedf2d 517 case gCCCA_c:
andreikovacs 0:764779eedf2d 518 Radio_Phy_PlmeCcaConfirm(gPhyChannelIdle_c, mPhyTaskInstance);
andreikovacs 0:764779eedf2d 519 break;
andreikovacs 0:764779eedf2d 520
andreikovacs 0:764779eedf2d 521 default:
andreikovacs 0:764779eedf2d 522 Radio_Phy_PlmeSyncLossIndication(mPhyTaskInstance);
andreikovacs 0:764779eedf2d 523 break;
andreikovacs 0:764779eedf2d 524 }
andreikovacs 0:764779eedf2d 525 }
andreikovacs 0:764779eedf2d 526 // timers interrupt
andreikovacs 0:764779eedf2d 527 else
andreikovacs 0:764779eedf2d 528 {
andreikovacs 0:764779eedf2d 529 if( mStatusAndControlRegs[PHY_IRQSTS3_INDEX_c] & cIRQSTS3_TMR2IRQ )
andreikovacs 0:764779eedf2d 530 {
andreikovacs 0:764779eedf2d 531 // disable TMR2 comparator and time triggered action
andreikovacs 0:764779eedf2d 532 mStatusAndControlRegs[PHY_CTRL3_INDEX_c] &= (uint8_t) ~( cPHY_CTRL3_TMR2CMP_EN);
andreikovacs 0:764779eedf2d 533 mStatusAndControlRegs[PHY_CTRL1_INDEX_c] &= (uint8_t) ~( cPHY_CTRL1_TMRTRIGEN);
andreikovacs 0:764779eedf2d 534
andreikovacs 0:764779eedf2d 535 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL3, mStatusAndControlRegs[PHY_CTRL3_INDEX_c]);
andreikovacs 0:764779eedf2d 536 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, mStatusAndControlRegs[PHY_CTRL1_INDEX_c]);
andreikovacs 0:764779eedf2d 537
andreikovacs 0:764779eedf2d 538 Radio_Phy_TimeStartEventIndication(mPhyTaskInstance);
andreikovacs 0:764779eedf2d 539 }
andreikovacs 0:764779eedf2d 540
andreikovacs 0:764779eedf2d 541 if( mStatusAndControlRegs[PHY_IRQSTS3_INDEX_c] & cIRQSTS3_TMR3IRQ )
andreikovacs 0:764779eedf2d 542 {
andreikovacs 0:764779eedf2d 543 /* disable TMR3 comparator and timeout */
andreikovacs 0:764779eedf2d 544 mStatusAndControlRegs[PHY_CTRL3_INDEX_c] &= (uint8_t) ~( cPHY_CTRL3_TMR3CMP_EN);
andreikovacs 0:764779eedf2d 545 mStatusAndControlRegs[PHY_CTRL4_INDEX_c] &= (uint8_t) ~( cPHY_CTRL4_TC3TMOUT);
andreikovacs 0:764779eedf2d 546
andreikovacs 0:764779eedf2d 547 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL3, mStatusAndControlRegs[PHY_CTRL3_INDEX_c]);
andreikovacs 0:764779eedf2d 548 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL4, mStatusAndControlRegs[PHY_CTRL4_INDEX_c]);
andreikovacs 0:764779eedf2d 549
andreikovacs 0:764779eedf2d 550 /* Ensure that we're not issuing TimeoutIndication while the Automated sequence is still in progress */
andreikovacs 0:764779eedf2d 551 /* TMR3 can expire during R-T turnaround for example, case in which the sequence is not interrupted */
andreikovacs 0:764779eedf2d 552 if( gIdle_c == xcvseqCopy )
andreikovacs 0:764779eedf2d 553 {
andreikovacs 0:764779eedf2d 554 Radio_Phy_TimeRxTimeoutIndication(mPhyTaskInstance);
andreikovacs 0:764779eedf2d 555 }
andreikovacs 0:764779eedf2d 556 }
andreikovacs 0:764779eedf2d 557
andreikovacs 0:764779eedf2d 558 /* Timer 4 Compare Match */
andreikovacs 0:764779eedf2d 559 if( mStatusAndControlRegs[PHY_IRQSTS3_INDEX_c] & cIRQSTS3_TMR4IRQ )
andreikovacs 0:764779eedf2d 560 {
andreikovacs 0:764779eedf2d 561 /* disable TMR4 comparator */
andreikovacs 0:764779eedf2d 562 mStatusAndControlRegs[PHY_CTRL3_INDEX_c] &= (uint8_t) ~( cPHY_CTRL3_TMR4CMP_EN);
andreikovacs 0:764779eedf2d 563 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL3, mStatusAndControlRegs[PHY_CTRL3_INDEX_c]);
andreikovacs 0:764779eedf2d 564 }
andreikovacs 0:764779eedf2d 565 }
andreikovacs 0:764779eedf2d 566
andreikovacs 0:764779eedf2d 567 MCR20Drv_IRQ_Enable();
andreikovacs 0:764779eedf2d 568 }
andreikovacs 0:764779eedf2d 569
andreikovacs 0:764779eedf2d 570 /*! *********************************************************************************
andreikovacs 0:764779eedf2d 571 * \brief This function installs the PHY ISR
andreikovacs 0:764779eedf2d 572 *
andreikovacs 0:764779eedf2d 573 ********************************************************************************** */
andreikovacs 0:764779eedf2d 574 void PHY_InstallIsr( void )
andreikovacs 0:764779eedf2d 575 {
andreikovacs 0:764779eedf2d 576 /*Initialise RF interrupt pin*/
andreikovacs 0:764779eedf2d 577 RF_IRQ_Init();
andreikovacs 0:764779eedf2d 578
andreikovacs 0:764779eedf2d 579 //GpioInstallIsr(PHY_InterruptHandler, gGpioIsrPrioHigh_c, MCR20_Irq_Priority, kGpioXcvrIrqPin);
andreikovacs 0:764779eedf2d 580 }