MK64F12_vref.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     Redistribution and use in source and binary forms, with or without modification,
00019 **     are permitted provided that the following conditions are met:
00020 **
00021 **     o Redistributions of source code must retain the above copyright notice, this list
00022 **       of conditions and the following disclaimer.
00023 **
00024 **     o Redistributions in binary form must reproduce the above copyright notice, this
00025 **       list of conditions and the following disclaimer in the documentation and/or
00026 **       other materials provided with the distribution.
00027 **
00028 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00029 **       contributors may be used to endorse or promote products derived from this
00030 **       software without specific prior written permission.
00031 **
00032 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00033 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00034 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00035 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00036 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00037 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00038 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00039 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00040 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00041 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00042 **
00043 **     http:                 www.freescale.com
00044 **     mail:                 support@freescale.com
00045 **
00046 **     Revisions:
00047 **     - rev. 1.0 (2013-08-12)
00048 **         Initial version.
00049 **     - rev. 2.0 (2013-10-29)
00050 **         Register accessor macros added to the memory map.
00051 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00052 **         Startup file for gcc has been updated according to CMSIS 3.2.
00053 **         System initialization updated.
00054 **         MCG - registers updated.
00055 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00056 **     - rev. 2.1 (2013-10-30)
00057 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00058 **     - rev. 2.2 (2013-12-09)
00059 **         DMA - EARS register removed.
00060 **         AIPS0, AIPS1 - MPRA register updated.
00061 **     - rev. 2.3 (2014-01-24)
00062 **         Update according to reference manual rev. 2
00063 **         ENET, MCG, MCM, SIM, USB - registers updated
00064 **     - rev. 2.4 (2014-02-10)
00065 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00066 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00067 **     - rev. 2.5 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00071 **
00072 ** ###################################################################
00073 */
00074 
00075 /*
00076  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00077  *
00078  * This file was generated automatically and any changes may be lost.
00079  */
00080 #ifndef __HW_VREF_REGISTERS_H__
00081 #define __HW_VREF_REGISTERS_H__
00082 
00083 #include "MK64F12.h"
00084 #include "fsl_bitaccess.h"
00085 
00086 /*
00087  * MK64F12 VREF
00088  *
00089  * Voltage Reference
00090  *
00091  * Registers defined in this header file:
00092  * - HW_VREF_TRM - VREF Trim Register
00093  * - HW_VREF_SC - VREF Status and Control Register
00094  *
00095  * - hw_vref_t - Struct containing all module registers.
00096  */
00097 
00098 #define HW_VREF_INSTANCE_COUNT (1U) /*!< Number of instances of the VREF module. */
00099 
00100 /*******************************************************************************
00101  * HW_VREF_TRM - VREF Trim Register
00102  ******************************************************************************/
00103 
00104 /*!
00105  * @brief HW_VREF_TRM - VREF Trim Register (RW)
00106  *
00107  * Reset value: 0x00U
00108  *
00109  * This register contains bits that contain the trim data for the Voltage
00110  * Reference.
00111  */
00112 typedef union _hw_vref_trm
00113 {
00114     uint8_t U;
00115     struct _hw_vref_trm_bitfields
00116     {
00117         uint8_t TRIM : 6;              /*!< [5:0] Trim bits */
00118         uint8_t CHOPEN : 1;            /*!< [6] Chop oscillator enable. When set,
00119                                         * internal chopping operation is enabled and the internal analog offset will be
00120                                         * minimized. */
00121         uint8_t RESERVED0 : 1;         /*!< [7]  */
00122     } B;
00123 } hw_vref_trm_t;
00124 
00125 /*!
00126  * @name Constants and macros for entire VREF_TRM register
00127  */
00128 /*@{*/
00129 #define HW_VREF_TRM_ADDR(x)      ((x) + 0x0U)
00130 
00131 #define HW_VREF_TRM(x)           (*(__IO hw_vref_trm_t *) HW_VREF_TRM_ADDR(x))
00132 #define HW_VREF_TRM_RD(x)        (HW_VREF_TRM(x).U)
00133 #define HW_VREF_TRM_WR(x, v)     (HW_VREF_TRM(x).U = (v))
00134 #define HW_VREF_TRM_SET(x, v)    (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) |  (v)))
00135 #define HW_VREF_TRM_CLR(x, v)    (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) & ~(v)))
00136 #define HW_VREF_TRM_TOG(x, v)    (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) ^  (v)))
00137 /*@}*/
00138 
00139 /*
00140  * Constants & macros for individual VREF_TRM bitfields
00141  */
00142 
00143 /*!
00144  * @name Register VREF_TRM, field TRIM[5:0] (RW)
00145  *
00146  * These bits change the resulting VREF by approximately +/- 0.5 mV for each
00147  * step. Min = minimum and max = maximum voltage reference output. For minimum and
00148  * maximum voltage reference output values, refer to the Data Sheet for this chip.
00149  *
00150  * Values:
00151  * - 000000 - Min
00152  * - 111111 - Max
00153  */
00154 /*@{*/
00155 #define BP_VREF_TRM_TRIM     (0U)          /*!< Bit position for VREF_TRM_TRIM. */
00156 #define BM_VREF_TRM_TRIM     (0x3FU)       /*!< Bit mask for VREF_TRM_TRIM. */
00157 #define BS_VREF_TRM_TRIM     (6U)          /*!< Bit field size in bits for VREF_TRM_TRIM. */
00158 
00159 /*! @brief Read current value of the VREF_TRM_TRIM field. */
00160 #define BR_VREF_TRM_TRIM(x)  (HW_VREF_TRM(x).B.TRIM)
00161 
00162 /*! @brief Format value for bitfield VREF_TRM_TRIM. */
00163 #define BF_VREF_TRM_TRIM(v)  ((uint8_t)((uint8_t)(v) << BP_VREF_TRM_TRIM) & BM_VREF_TRM_TRIM)
00164 
00165 /*! @brief Set the TRIM field to a new value. */
00166 #define BW_VREF_TRM_TRIM(x, v) (HW_VREF_TRM_WR(x, (HW_VREF_TRM_RD(x) & ~BM_VREF_TRM_TRIM) | BF_VREF_TRM_TRIM(v)))
00167 /*@}*/
00168 
00169 /*!
00170  * @name Register VREF_TRM, field CHOPEN[6] (RW)
00171  *
00172  * This bit is set during factory trimming of the VREF voltage. This bit should
00173  * be written to 1 to achieve the performance stated in the data sheet.
00174  *
00175  * Values:
00176  * - 0 - Chop oscillator is disabled.
00177  * - 1 - Chop oscillator is enabled.
00178  */
00179 /*@{*/
00180 #define BP_VREF_TRM_CHOPEN   (6U)          /*!< Bit position for VREF_TRM_CHOPEN. */
00181 #define BM_VREF_TRM_CHOPEN   (0x40U)       /*!< Bit mask for VREF_TRM_CHOPEN. */
00182 #define BS_VREF_TRM_CHOPEN   (1U)          /*!< Bit field size in bits for VREF_TRM_CHOPEN. */
00183 
00184 /*! @brief Read current value of the VREF_TRM_CHOPEN field. */
00185 #define BR_VREF_TRM_CHOPEN(x) (BITBAND_ACCESS8(HW_VREF_TRM_ADDR(x), BP_VREF_TRM_CHOPEN))
00186 
00187 /*! @brief Format value for bitfield VREF_TRM_CHOPEN. */
00188 #define BF_VREF_TRM_CHOPEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_TRM_CHOPEN) & BM_VREF_TRM_CHOPEN)
00189 
00190 /*! @brief Set the CHOPEN field to a new value. */
00191 #define BW_VREF_TRM_CHOPEN(x, v) (BITBAND_ACCESS8(HW_VREF_TRM_ADDR(x), BP_VREF_TRM_CHOPEN) = (v))
00192 /*@}*/
00193 
00194 /*******************************************************************************
00195  * HW_VREF_SC - VREF Status and Control Register
00196  ******************************************************************************/
00197 
00198 /*!
00199  * @brief HW_VREF_SC - VREF Status and Control Register (RW)
00200  *
00201  * Reset value: 0x00U
00202  *
00203  * This register contains the control bits used to enable the internal voltage
00204  * reference and to select the buffer mode to be used.
00205  */
00206 typedef union _hw_vref_sc
00207 {
00208     uint8_t U;
00209     struct _hw_vref_sc_bitfields
00210     {
00211         uint8_t MODE_LV : 2;           /*!< [1:0] Buffer Mode selection */
00212         uint8_t VREFST : 1;            /*!< [2] Internal Voltage Reference stable */
00213         uint8_t RESERVED0 : 2;         /*!< [4:3]  */
00214         uint8_t ICOMPEN : 1;           /*!< [5] Second order curvature compensation
00215                                         * enable */
00216         uint8_t REGEN : 1;             /*!< [6] Regulator enable */
00217         uint8_t VREFEN : 1;            /*!< [7] Internal Voltage Reference enable */
00218     } B;
00219 } hw_vref_sc_t;
00220 
00221 /*!
00222  * @name Constants and macros for entire VREF_SC register
00223  */
00224 /*@{*/
00225 #define HW_VREF_SC_ADDR(x)       ((x) + 0x1U)
00226 
00227 #define HW_VREF_SC(x)            (*(__IO hw_vref_sc_t *) HW_VREF_SC_ADDR(x))
00228 #define HW_VREF_SC_RD(x)         (HW_VREF_SC(x).U)
00229 #define HW_VREF_SC_WR(x, v)      (HW_VREF_SC(x).U = (v))
00230 #define HW_VREF_SC_SET(x, v)     (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) |  (v)))
00231 #define HW_VREF_SC_CLR(x, v)     (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) & ~(v)))
00232 #define HW_VREF_SC_TOG(x, v)     (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) ^  (v)))
00233 /*@}*/
00234 
00235 /*
00236  * Constants & macros for individual VREF_SC bitfields
00237  */
00238 
00239 /*!
00240  * @name Register VREF_SC, field MODE_LV[1:0] (RW)
00241  *
00242  * These bits select the buffer modes for the Voltage Reference module.
00243  *
00244  * Values:
00245  * - 00 - Bandgap on only, for stabilization and startup
00246  * - 01 - High power buffer mode enabled
00247  * - 10 - Low-power buffer mode enabled
00248  * - 11 - Reserved
00249  */
00250 /*@{*/
00251 #define BP_VREF_SC_MODE_LV   (0U)          /*!< Bit position for VREF_SC_MODE_LV. */
00252 #define BM_VREF_SC_MODE_LV   (0x03U)       /*!< Bit mask for VREF_SC_MODE_LV. */
00253 #define BS_VREF_SC_MODE_LV   (2U)          /*!< Bit field size in bits for VREF_SC_MODE_LV. */
00254 
00255 /*! @brief Read current value of the VREF_SC_MODE_LV field. */
00256 #define BR_VREF_SC_MODE_LV(x) (HW_VREF_SC(x).B.MODE_LV)
00257 
00258 /*! @brief Format value for bitfield VREF_SC_MODE_LV. */
00259 #define BF_VREF_SC_MODE_LV(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_MODE_LV) & BM_VREF_SC_MODE_LV)
00260 
00261 /*! @brief Set the MODE_LV field to a new value. */
00262 #define BW_VREF_SC_MODE_LV(x, v) (HW_VREF_SC_WR(x, (HW_VREF_SC_RD(x) & ~BM_VREF_SC_MODE_LV) | BF_VREF_SC_MODE_LV(v)))
00263 /*@}*/
00264 
00265 /*!
00266  * @name Register VREF_SC, field VREFST[2] (RO)
00267  *
00268  * This bit indicates that the bandgap reference within the Voltage Reference
00269  * module has completed its startup and stabilization.
00270  *
00271  * Values:
00272  * - 0 - The module is disabled or not stable.
00273  * - 1 - The module is stable.
00274  */
00275 /*@{*/
00276 #define BP_VREF_SC_VREFST    (2U)          /*!< Bit position for VREF_SC_VREFST. */
00277 #define BM_VREF_SC_VREFST    (0x04U)       /*!< Bit mask for VREF_SC_VREFST. */
00278 #define BS_VREF_SC_VREFST    (1U)          /*!< Bit field size in bits for VREF_SC_VREFST. */
00279 
00280 /*! @brief Read current value of the VREF_SC_VREFST field. */
00281 #define BR_VREF_SC_VREFST(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFST))
00282 /*@}*/
00283 
00284 /*!
00285  * @name Register VREF_SC, field ICOMPEN[5] (RW)
00286  *
00287  * This bit is set during factory trimming of the VREF voltage. This bit should
00288  * be written to 1 to achieve the performance stated in the data sheet.
00289  *
00290  * Values:
00291  * - 0 - Disabled
00292  * - 1 - Enabled
00293  */
00294 /*@{*/
00295 #define BP_VREF_SC_ICOMPEN   (5U)          /*!< Bit position for VREF_SC_ICOMPEN. */
00296 #define BM_VREF_SC_ICOMPEN   (0x20U)       /*!< Bit mask for VREF_SC_ICOMPEN. */
00297 #define BS_VREF_SC_ICOMPEN   (1U)          /*!< Bit field size in bits for VREF_SC_ICOMPEN. */
00298 
00299 /*! @brief Read current value of the VREF_SC_ICOMPEN field. */
00300 #define BR_VREF_SC_ICOMPEN(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_ICOMPEN))
00301 
00302 /*! @brief Format value for bitfield VREF_SC_ICOMPEN. */
00303 #define BF_VREF_SC_ICOMPEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_ICOMPEN) & BM_VREF_SC_ICOMPEN)
00304 
00305 /*! @brief Set the ICOMPEN field to a new value. */
00306 #define BW_VREF_SC_ICOMPEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_ICOMPEN) = (v))
00307 /*@}*/
00308 
00309 /*!
00310  * @name Register VREF_SC, field REGEN[6] (RW)
00311  *
00312  * This bit is used to enable the internal 1.75 V regulator to produce a
00313  * constant internal voltage supply in order to reduce the sensitivity to external
00314  * supply noise and variation. If it is desired to keep the regulator enabled in very
00315  * low power modes, refer to the Chip Configuration details for a description on
00316  * how this can be achieved. This bit is set during factory trimming of the VREF
00317  * voltage. This bit should be written to 1 to achieve the performance stated in
00318  * the data sheet.
00319  *
00320  * Values:
00321  * - 0 - Internal 1.75 V regulator is disabled.
00322  * - 1 - Internal 1.75 V regulator is enabled.
00323  */
00324 /*@{*/
00325 #define BP_VREF_SC_REGEN     (6U)          /*!< Bit position for VREF_SC_REGEN. */
00326 #define BM_VREF_SC_REGEN     (0x40U)       /*!< Bit mask for VREF_SC_REGEN. */
00327 #define BS_VREF_SC_REGEN     (1U)          /*!< Bit field size in bits for VREF_SC_REGEN. */
00328 
00329 /*! @brief Read current value of the VREF_SC_REGEN field. */
00330 #define BR_VREF_SC_REGEN(x)  (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_REGEN))
00331 
00332 /*! @brief Format value for bitfield VREF_SC_REGEN. */
00333 #define BF_VREF_SC_REGEN(v)  ((uint8_t)((uint8_t)(v) << BP_VREF_SC_REGEN) & BM_VREF_SC_REGEN)
00334 
00335 /*! @brief Set the REGEN field to a new value. */
00336 #define BW_VREF_SC_REGEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_REGEN) = (v))
00337 /*@}*/
00338 
00339 /*!
00340  * @name Register VREF_SC, field VREFEN[7] (RW)
00341  *
00342  * This bit is used to enable the bandgap reference within the Voltage Reference
00343  * module. After the VREF is enabled, turning off the clock to the VREF module
00344  * via the corresponding clock gate register will not disable the VREF. VREF must
00345  * be disabled via this VREFEN bit.
00346  *
00347  * Values:
00348  * - 0 - The module is disabled.
00349  * - 1 - The module is enabled.
00350  */
00351 /*@{*/
00352 #define BP_VREF_SC_VREFEN    (7U)          /*!< Bit position for VREF_SC_VREFEN. */
00353 #define BM_VREF_SC_VREFEN    (0x80U)       /*!< Bit mask for VREF_SC_VREFEN. */
00354 #define BS_VREF_SC_VREFEN    (1U)          /*!< Bit field size in bits for VREF_SC_VREFEN. */
00355 
00356 /*! @brief Read current value of the VREF_SC_VREFEN field. */
00357 #define BR_VREF_SC_VREFEN(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFEN))
00358 
00359 /*! @brief Format value for bitfield VREF_SC_VREFEN. */
00360 #define BF_VREF_SC_VREFEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_VREFEN) & BM_VREF_SC_VREFEN)
00361 
00362 /*! @brief Set the VREFEN field to a new value. */
00363 #define BW_VREF_SC_VREFEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFEN) = (v))
00364 /*@}*/
00365 
00366 /*******************************************************************************
00367  * hw_vref_t - module struct
00368  ******************************************************************************/
00369 /*!
00370  * @brief All VREF module registers.
00371  */
00372 #pragma pack(1)
00373 typedef struct _hw_vref
00374 {
00375     __IO hw_vref_trm_t TRM ;                /*!< [0x0] VREF Trim Register */
00376     __IO hw_vref_sc_t SC ;                  /*!< [0x1] VREF Status and Control Register */
00377 } hw_vref_t;
00378 #pragma pack()
00379 
00380 /*! @brief Macro to access all VREF registers. */
00381 /*! @param x VREF module instance base address. */
00382 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00383  *     use the '&' operator, like <code>&HW_VREF(VREF_BASE)</code>. */
00384 #define HW_VREF(x)     (*(hw_vref_t *)(x))
00385 
00386 #endif /* __HW_VREF_REGISTERS_H__ */
00387 /* EOF */