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MK64F12_sim.h
00001 /* 00002 ** ################################################################### 00003 ** Compilers: Keil ARM C/C++ Compiler 00004 ** Freescale C/C++ for Embedded ARM 00005 ** GNU C Compiler 00006 ** IAR ANSI C/C++ Compiler for ARM 00007 ** 00008 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 00009 ** Version: rev. 2.5, 2014-02-10 00010 ** Build: b140604 00011 ** 00012 ** Abstract: 00013 ** Extension to the CMSIS register access layer header. 00014 ** 00015 ** Copyright (c) 2014 Freescale Semiconductor, Inc. 00016 ** All rights reserved. 00017 ** 00018 ** Redistribution and use in source and binary forms, with or without modification, 00019 ** are permitted provided that the following conditions are met: 00020 ** 00021 ** o Redistributions of source code must retain the above copyright notice, this list 00022 ** of conditions and the following disclaimer. 00023 ** 00024 ** o Redistributions in binary form must reproduce the above copyright notice, this 00025 ** list of conditions and the following disclaimer in the documentation and/or 00026 ** other materials provided with the distribution. 00027 ** 00028 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its 00029 ** contributors may be used to endorse or promote products derived from this 00030 ** software without specific prior written permission. 00031 ** 00032 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 00033 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 00034 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00035 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 00036 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 00037 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00038 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 00039 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00040 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 00041 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00042 ** 00043 ** http: www.freescale.com 00044 ** mail: support@freescale.com 00045 ** 00046 ** Revisions: 00047 ** - rev. 1.0 (2013-08-12) 00048 ** Initial version. 00049 ** - rev. 2.0 (2013-10-29) 00050 ** Register accessor macros added to the memory map. 00051 ** Symbols for Processor Expert memory map compatibility added to the memory map. 00052 ** Startup file for gcc has been updated according to CMSIS 3.2. 00053 ** System initialization updated. 00054 ** MCG - registers updated. 00055 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. 00056 ** - rev. 2.1 (2013-10-30) 00057 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. 00058 ** - rev. 2.2 (2013-12-09) 00059 ** DMA - EARS register removed. 00060 ** AIPS0, AIPS1 - MPRA register updated. 00061 ** - rev. 2.3 (2014-01-24) 00062 ** Update according to reference manual rev. 2 00063 ** ENET, MCG, MCM, SIM, USB - registers updated 00064 ** - rev. 2.4 (2014-02-10) 00065 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h 00066 ** Update of SystemInit() and SystemCoreClockUpdate() functions. 00067 ** - rev. 2.5 (2014-02-10) 00068 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h 00069 ** Update of SystemInit() and SystemCoreClockUpdate() functions. 00070 ** Module access macro module_BASES replaced by module_BASE_PTRS. 00071 ** 00072 ** ################################################################### 00073 */ 00074 00075 /* 00076 * WARNING! DO NOT EDIT THIS FILE DIRECTLY! 00077 * 00078 * This file was generated automatically and any changes may be lost. 00079 */ 00080 #ifndef __HW_SIM_REGISTERS_H__ 00081 #define __HW_SIM_REGISTERS_H__ 00082 00083 #include "MK64F12.h" 00084 #include "fsl_bitaccess.h" 00085 00086 /* 00087 * MK64F12 SIM 00088 * 00089 * System Integration Module 00090 * 00091 * Registers defined in this header file: 00092 * - HW_SIM_SOPT1 - System Options Register 1 00093 * - HW_SIM_SOPT1CFG - SOPT1 Configuration Register 00094 * - HW_SIM_SOPT2 - System Options Register 2 00095 * - HW_SIM_SOPT4 - System Options Register 4 00096 * - HW_SIM_SOPT5 - System Options Register 5 00097 * - HW_SIM_SOPT7 - System Options Register 7 00098 * - HW_SIM_SDID - System Device Identification Register 00099 * - HW_SIM_SCGC1 - System Clock Gating Control Register 1 00100 * - HW_SIM_SCGC2 - System Clock Gating Control Register 2 00101 * - HW_SIM_SCGC3 - System Clock Gating Control Register 3 00102 * - HW_SIM_SCGC4 - System Clock Gating Control Register 4 00103 * - HW_SIM_SCGC5 - System Clock Gating Control Register 5 00104 * - HW_SIM_SCGC6 - System Clock Gating Control Register 6 00105 * - HW_SIM_SCGC7 - System Clock Gating Control Register 7 00106 * - HW_SIM_CLKDIV1 - System Clock Divider Register 1 00107 * - HW_SIM_CLKDIV2 - System Clock Divider Register 2 00108 * - HW_SIM_FCFG1 - Flash Configuration Register 1 00109 * - HW_SIM_FCFG2 - Flash Configuration Register 2 00110 * - HW_SIM_UIDH - Unique Identification Register High 00111 * - HW_SIM_UIDMH - Unique Identification Register Mid-High 00112 * - HW_SIM_UIDML - Unique Identification Register Mid Low 00113 * - HW_SIM_UIDL - Unique Identification Register Low 00114 * 00115 * - hw_sim_t - Struct containing all module registers. 00116 */ 00117 00118 #define HW_SIM_INSTANCE_COUNT (1U) /*!< Number of instances of the SIM module. */ 00119 00120 /******************************************************************************* 00121 * HW_SIM_SOPT1 - System Options Register 1 00122 ******************************************************************************/ 00123 00124 /*! 00125 * @brief HW_SIM_SOPT1 - System Options Register 1 (RW) 00126 * 00127 * Reset value: 0x80000000U 00128 * 00129 * The SOPT1 register is only reset on POR or LVD. 00130 */ 00131 typedef union _hw_sim_sopt1 00132 { 00133 uint32_t U; 00134 struct _hw_sim_sopt1_bitfields 00135 { 00136 uint32_t RESERVED0 : 12; /*!< [11:0] */ 00137 uint32_t RAMSIZE : 4; /*!< [15:12] RAM size */ 00138 uint32_t RESERVED1 : 2; /*!< [17:16] */ 00139 uint32_t OSC32KSEL : 2; /*!< [19:18] 32K oscillator clock select */ 00140 uint32_t RESERVED2 : 9; /*!< [28:20] */ 00141 uint32_t USBVSTBY : 1; /*!< [29] USB voltage regulator in standby 00142 * mode during VLPR and VLPW modes */ 00143 uint32_t USBSSTBY : 1; /*!< [30] USB voltage regulator in standby 00144 * mode during Stop, VLPS, LLS and VLLS modes. */ 00145 uint32_t USBREGEN : 1; /*!< [31] USB voltage regulator enable */ 00146 } B; 00147 } hw_sim_sopt1_t; 00148 00149 /*! 00150 * @name Constants and macros for entire SIM_SOPT1 register 00151 */ 00152 /*@{*/ 00153 #define HW_SIM_SOPT1_ADDR(x) ((x) + 0x0U) 00154 00155 #define HW_SIM_SOPT1(x) (*(__IO hw_sim_sopt1_t *) HW_SIM_SOPT1_ADDR(x)) 00156 #define HW_SIM_SOPT1_RD(x) (HW_SIM_SOPT1(x).U) 00157 #define HW_SIM_SOPT1_WR(x, v) (HW_SIM_SOPT1(x).U = (v)) 00158 #define HW_SIM_SOPT1_SET(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) | (v))) 00159 #define HW_SIM_SOPT1_CLR(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) & ~(v))) 00160 #define HW_SIM_SOPT1_TOG(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) ^ (v))) 00161 /*@}*/ 00162 00163 /* 00164 * Constants & macros for individual SIM_SOPT1 bitfields 00165 */ 00166 00167 /*! 00168 * @name Register SIM_SOPT1, field RAMSIZE[15:12] (RO) 00169 * 00170 * This field specifies the amount of system RAM available on the device. 00171 * 00172 * Values: 00173 * - 0001 - 8 KB 00174 * - 0011 - 16 KB 00175 * - 0100 - 24 KB 00176 * - 0101 - 32 KB 00177 * - 0110 - 48 KB 00178 * - 0111 - 64 KB 00179 * - 1000 - 96 KB 00180 * - 1001 - 128 KB 00181 * - 1011 - 256 KB 00182 */ 00183 /*@{*/ 00184 #define BP_SIM_SOPT1_RAMSIZE (12U) /*!< Bit position for SIM_SOPT1_RAMSIZE. */ 00185 #define BM_SIM_SOPT1_RAMSIZE (0x0000F000U) /*!< Bit mask for SIM_SOPT1_RAMSIZE. */ 00186 #define BS_SIM_SOPT1_RAMSIZE (4U) /*!< Bit field size in bits for SIM_SOPT1_RAMSIZE. */ 00187 00188 /*! @brief Read current value of the SIM_SOPT1_RAMSIZE field. */ 00189 #define BR_SIM_SOPT1_RAMSIZE(x) (HW_SIM_SOPT1(x).B.RAMSIZE) 00190 /*@}*/ 00191 00192 /*! 00193 * @name Register SIM_SOPT1, field OSC32KSEL[19:18] (RW) 00194 * 00195 * Selects the 32 kHz clock source (ERCLK32K) for LPTMR. This field is reset 00196 * only on POR/LVD. 00197 * 00198 * Values: 00199 * - 00 - System oscillator (OSC32KCLK) 00200 * - 01 - Reserved 00201 * - 10 - RTC 32.768kHz oscillator 00202 * - 11 - LPO 1 kHz 00203 */ 00204 /*@{*/ 00205 #define BP_SIM_SOPT1_OSC32KSEL (18U) /*!< Bit position for SIM_SOPT1_OSC32KSEL. */ 00206 #define BM_SIM_SOPT1_OSC32KSEL (0x000C0000U) /*!< Bit mask for SIM_SOPT1_OSC32KSEL. */ 00207 #define BS_SIM_SOPT1_OSC32KSEL (2U) /*!< Bit field size in bits for SIM_SOPT1_OSC32KSEL. */ 00208 00209 /*! @brief Read current value of the SIM_SOPT1_OSC32KSEL field. */ 00210 #define BR_SIM_SOPT1_OSC32KSEL(x) (HW_SIM_SOPT1(x).B.OSC32KSEL) 00211 00212 /*! @brief Format value for bitfield SIM_SOPT1_OSC32KSEL. */ 00213 #define BF_SIM_SOPT1_OSC32KSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_OSC32KSEL) & BM_SIM_SOPT1_OSC32KSEL) 00214 00215 /*! @brief Set the OSC32KSEL field to a new value. */ 00216 #define BW_SIM_SOPT1_OSC32KSEL(x, v) (HW_SIM_SOPT1_WR(x, (HW_SIM_SOPT1_RD(x) & ~BM_SIM_SOPT1_OSC32KSEL) | BF_SIM_SOPT1_OSC32KSEL(v))) 00217 /*@}*/ 00218 00219 /*! 00220 * @name Register SIM_SOPT1, field USBVSTBY[29] (RW) 00221 * 00222 * Controls whether the USB voltage regulator is placed in standby mode during 00223 * VLPR and VLPW modes. 00224 * 00225 * Values: 00226 * - 0 - USB voltage regulator not in standby during VLPR and VLPW modes. 00227 * - 1 - USB voltage regulator in standby during VLPR and VLPW modes. 00228 */ 00229 /*@{*/ 00230 #define BP_SIM_SOPT1_USBVSTBY (29U) /*!< Bit position for SIM_SOPT1_USBVSTBY. */ 00231 #define BM_SIM_SOPT1_USBVSTBY (0x20000000U) /*!< Bit mask for SIM_SOPT1_USBVSTBY. */ 00232 #define BS_SIM_SOPT1_USBVSTBY (1U) /*!< Bit field size in bits for SIM_SOPT1_USBVSTBY. */ 00233 00234 /*! @brief Read current value of the SIM_SOPT1_USBVSTBY field. */ 00235 #define BR_SIM_SOPT1_USBVSTBY(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBVSTBY)) 00236 00237 /*! @brief Format value for bitfield SIM_SOPT1_USBVSTBY. */ 00238 #define BF_SIM_SOPT1_USBVSTBY(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBVSTBY) & BM_SIM_SOPT1_USBVSTBY) 00239 00240 /*! @brief Set the USBVSTBY field to a new value. */ 00241 #define BW_SIM_SOPT1_USBVSTBY(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBVSTBY) = (v)) 00242 /*@}*/ 00243 00244 /*! 00245 * @name Register SIM_SOPT1, field USBSSTBY[30] (RW) 00246 * 00247 * Controls whether the USB voltage regulator is placed in standby mode during 00248 * Stop, VLPS, LLS and VLLS modes. 00249 * 00250 * Values: 00251 * - 0 - USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS 00252 * modes. 00253 * - 1 - USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes. 00254 */ 00255 /*@{*/ 00256 #define BP_SIM_SOPT1_USBSSTBY (30U) /*!< Bit position for SIM_SOPT1_USBSSTBY. */ 00257 #define BM_SIM_SOPT1_USBSSTBY (0x40000000U) /*!< Bit mask for SIM_SOPT1_USBSSTBY. */ 00258 #define BS_SIM_SOPT1_USBSSTBY (1U) /*!< Bit field size in bits for SIM_SOPT1_USBSSTBY. */ 00259 00260 /*! @brief Read current value of the SIM_SOPT1_USBSSTBY field. */ 00261 #define BR_SIM_SOPT1_USBSSTBY(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBSSTBY)) 00262 00263 /*! @brief Format value for bitfield SIM_SOPT1_USBSSTBY. */ 00264 #define BF_SIM_SOPT1_USBSSTBY(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBSSTBY) & BM_SIM_SOPT1_USBSSTBY) 00265 00266 /*! @brief Set the USBSSTBY field to a new value. */ 00267 #define BW_SIM_SOPT1_USBSSTBY(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBSSTBY) = (v)) 00268 /*@}*/ 00269 00270 /*! 00271 * @name Register SIM_SOPT1, field USBREGEN[31] (RW) 00272 * 00273 * Controls whether the USB voltage regulator is enabled. 00274 * 00275 * Values: 00276 * - 0 - USB voltage regulator is disabled. 00277 * - 1 - USB voltage regulator is enabled. 00278 */ 00279 /*@{*/ 00280 #define BP_SIM_SOPT1_USBREGEN (31U) /*!< Bit position for SIM_SOPT1_USBREGEN. */ 00281 #define BM_SIM_SOPT1_USBREGEN (0x80000000U) /*!< Bit mask for SIM_SOPT1_USBREGEN. */ 00282 #define BS_SIM_SOPT1_USBREGEN (1U) /*!< Bit field size in bits for SIM_SOPT1_USBREGEN. */ 00283 00284 /*! @brief Read current value of the SIM_SOPT1_USBREGEN field. */ 00285 #define BR_SIM_SOPT1_USBREGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBREGEN)) 00286 00287 /*! @brief Format value for bitfield SIM_SOPT1_USBREGEN. */ 00288 #define BF_SIM_SOPT1_USBREGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBREGEN) & BM_SIM_SOPT1_USBREGEN) 00289 00290 /*! @brief Set the USBREGEN field to a new value. */ 00291 #define BW_SIM_SOPT1_USBREGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBREGEN) = (v)) 00292 /*@}*/ 00293 00294 /******************************************************************************* 00295 * HW_SIM_SOPT1CFG - SOPT1 Configuration Register 00296 ******************************************************************************/ 00297 00298 /*! 00299 * @brief HW_SIM_SOPT1CFG - SOPT1 Configuration Register (RW) 00300 * 00301 * Reset value: 0x00000000U 00302 * 00303 * The SOPT1CFG register is reset on System Reset not VLLS. 00304 */ 00305 typedef union _hw_sim_sopt1cfg 00306 { 00307 uint32_t U; 00308 struct _hw_sim_sopt1cfg_bitfields 00309 { 00310 uint32_t RESERVED0 : 24; /*!< [23:0] */ 00311 uint32_t URWE : 1; /*!< [24] USB voltage regulator enable write 00312 * enable */ 00313 uint32_t UVSWE : 1; /*!< [25] USB voltage regulator VLP standby write 00314 * enable */ 00315 uint32_t USSWE : 1; /*!< [26] USB voltage regulator stop standby 00316 * write enable */ 00317 uint32_t RESERVED1 : 5; /*!< [31:27] */ 00318 } B; 00319 } hw_sim_sopt1cfg_t; 00320 00321 /*! 00322 * @name Constants and macros for entire SIM_SOPT1CFG register 00323 */ 00324 /*@{*/ 00325 #define HW_SIM_SOPT1CFG_ADDR(x) ((x) + 0x4U) 00326 00327 #define HW_SIM_SOPT1CFG(x) (*(__IO hw_sim_sopt1cfg_t *) HW_SIM_SOPT1CFG_ADDR(x)) 00328 #define HW_SIM_SOPT1CFG_RD(x) (HW_SIM_SOPT1CFG(x).U) 00329 #define HW_SIM_SOPT1CFG_WR(x, v) (HW_SIM_SOPT1CFG(x).U = (v)) 00330 #define HW_SIM_SOPT1CFG_SET(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) | (v))) 00331 #define HW_SIM_SOPT1CFG_CLR(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) & ~(v))) 00332 #define HW_SIM_SOPT1CFG_TOG(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) ^ (v))) 00333 /*@}*/ 00334 00335 /* 00336 * Constants & macros for individual SIM_SOPT1CFG bitfields 00337 */ 00338 00339 /*! 00340 * @name Register SIM_SOPT1CFG, field URWE[24] (RW) 00341 * 00342 * Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This 00343 * register bit clears after a write to USBREGEN. 00344 * 00345 * Values: 00346 * - 0 - SOPT1 USBREGEN cannot be written. 00347 * - 1 - SOPT1 USBREGEN can be written. 00348 */ 00349 /*@{*/ 00350 #define BP_SIM_SOPT1CFG_URWE (24U) /*!< Bit position for SIM_SOPT1CFG_URWE. */ 00351 #define BM_SIM_SOPT1CFG_URWE (0x01000000U) /*!< Bit mask for SIM_SOPT1CFG_URWE. */ 00352 #define BS_SIM_SOPT1CFG_URWE (1U) /*!< Bit field size in bits for SIM_SOPT1CFG_URWE. */ 00353 00354 /*! @brief Read current value of the SIM_SOPT1CFG_URWE field. */ 00355 #define BR_SIM_SOPT1CFG_URWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_URWE)) 00356 00357 /*! @brief Format value for bitfield SIM_SOPT1CFG_URWE. */ 00358 #define BF_SIM_SOPT1CFG_URWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_URWE) & BM_SIM_SOPT1CFG_URWE) 00359 00360 /*! @brief Set the URWE field to a new value. */ 00361 #define BW_SIM_SOPT1CFG_URWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_URWE) = (v)) 00362 /*@}*/ 00363 00364 /*! 00365 * @name Register SIM_SOPT1CFG, field UVSWE[25] (RW) 00366 * 00367 * Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written. 00368 * This register bit clears after a write to USBVSTBY. 00369 * 00370 * Values: 00371 * - 0 - SOPT1 USBVSTBY cannot be written. 00372 * - 1 - SOPT1 USBVSTBY can be written. 00373 */ 00374 /*@{*/ 00375 #define BP_SIM_SOPT1CFG_UVSWE (25U) /*!< Bit position for SIM_SOPT1CFG_UVSWE. */ 00376 #define BM_SIM_SOPT1CFG_UVSWE (0x02000000U) /*!< Bit mask for SIM_SOPT1CFG_UVSWE. */ 00377 #define BS_SIM_SOPT1CFG_UVSWE (1U) /*!< Bit field size in bits for SIM_SOPT1CFG_UVSWE. */ 00378 00379 /*! @brief Read current value of the SIM_SOPT1CFG_UVSWE field. */ 00380 #define BR_SIM_SOPT1CFG_UVSWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_UVSWE)) 00381 00382 /*! @brief Format value for bitfield SIM_SOPT1CFG_UVSWE. */ 00383 #define BF_SIM_SOPT1CFG_UVSWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_UVSWE) & BM_SIM_SOPT1CFG_UVSWE) 00384 00385 /*! @brief Set the UVSWE field to a new value. */ 00386 #define BW_SIM_SOPT1CFG_UVSWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_UVSWE) = (v)) 00387 /*@}*/ 00388 00389 /*! 00390 * @name Register SIM_SOPT1CFG, field USSWE[26] (RW) 00391 * 00392 * Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written. 00393 * This register bit clears after a write to USBSSTBY. 00394 * 00395 * Values: 00396 * - 0 - SOPT1 USBSSTBY cannot be written. 00397 * - 1 - SOPT1 USBSSTBY can be written. 00398 */ 00399 /*@{*/ 00400 #define BP_SIM_SOPT1CFG_USSWE (26U) /*!< Bit position for SIM_SOPT1CFG_USSWE. */ 00401 #define BM_SIM_SOPT1CFG_USSWE (0x04000000U) /*!< Bit mask for SIM_SOPT1CFG_USSWE. */ 00402 #define BS_SIM_SOPT1CFG_USSWE (1U) /*!< Bit field size in bits for SIM_SOPT1CFG_USSWE. */ 00403 00404 /*! @brief Read current value of the SIM_SOPT1CFG_USSWE field. */ 00405 #define BR_SIM_SOPT1CFG_USSWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_USSWE)) 00406 00407 /*! @brief Format value for bitfield SIM_SOPT1CFG_USSWE. */ 00408 #define BF_SIM_SOPT1CFG_USSWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_USSWE) & BM_SIM_SOPT1CFG_USSWE) 00409 00410 /*! @brief Set the USSWE field to a new value. */ 00411 #define BW_SIM_SOPT1CFG_USSWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_USSWE) = (v)) 00412 /*@}*/ 00413 00414 /******************************************************************************* 00415 * HW_SIM_SOPT2 - System Options Register 2 00416 ******************************************************************************/ 00417 00418 /*! 00419 * @brief HW_SIM_SOPT2 - System Options Register 2 (RW) 00420 * 00421 * Reset value: 0x00001000U 00422 * 00423 * SOPT2 contains the controls for selecting many of the module clock source 00424 * options on this device. See the Clock Distribution chapter for more information 00425 * including clocking diagrams and definitions of device clocks. 00426 */ 00427 typedef union _hw_sim_sopt2 00428 { 00429 uint32_t U; 00430 struct _hw_sim_sopt2_bitfields 00431 { 00432 uint32_t RESERVED0 : 4; /*!< [3:0] */ 00433 uint32_t RTCCLKOUTSEL : 1; /*!< [4] RTC clock out select */ 00434 uint32_t CLKOUTSEL : 3; /*!< [7:5] CLKOUT select */ 00435 uint32_t FBSL : 2; /*!< [9:8] FlexBus security level */ 00436 uint32_t RESERVED1 : 1; /*!< [10] */ 00437 uint32_t PTD7PAD : 1; /*!< [11] PTD7 pad drive strength */ 00438 uint32_t TRACECLKSEL : 1; /*!< [12] Debug trace clock select */ 00439 uint32_t RESERVED2 : 3; /*!< [15:13] */ 00440 uint32_t PLLFLLSEL : 2; /*!< [17:16] PLL/FLL clock select */ 00441 uint32_t USBSRC : 1; /*!< [18] USB clock source select */ 00442 uint32_t RMIISRC : 1; /*!< [19] RMII clock source select */ 00443 uint32_t TIMESRC : 2; /*!< [21:20] IEEE 1588 timestamp clock source 00444 * select */ 00445 uint32_t RESERVED3 : 6; /*!< [27:22] */ 00446 uint32_t SDHCSRC : 2; /*!< [29:28] SDHC clock source select */ 00447 uint32_t RESERVED4 : 2; /*!< [31:30] */ 00448 } B; 00449 } hw_sim_sopt2_t; 00450 00451 /*! 00452 * @name Constants and macros for entire SIM_SOPT2 register 00453 */ 00454 /*@{*/ 00455 #define HW_SIM_SOPT2_ADDR(x) ((x) + 0x1004U) 00456 00457 #define HW_SIM_SOPT2(x) (*(__IO hw_sim_sopt2_t *) HW_SIM_SOPT2_ADDR(x)) 00458 #define HW_SIM_SOPT2_RD(x) (HW_SIM_SOPT2(x).U) 00459 #define HW_SIM_SOPT2_WR(x, v) (HW_SIM_SOPT2(x).U = (v)) 00460 #define HW_SIM_SOPT2_SET(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) | (v))) 00461 #define HW_SIM_SOPT2_CLR(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) & ~(v))) 00462 #define HW_SIM_SOPT2_TOG(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) ^ (v))) 00463 /*@}*/ 00464 00465 /* 00466 * Constants & macros for individual SIM_SOPT2 bitfields 00467 */ 00468 00469 /*! 00470 * @name Register SIM_SOPT2, field RTCCLKOUTSEL[4] (RW) 00471 * 00472 * Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the 00473 * RTC_CLKOUT pin. 00474 * 00475 * Values: 00476 * - 0 - RTC 1 Hz clock is output on the RTC_CLKOUT pin. 00477 * - 1 - RTC 32.768kHz clock is output on the RTC_CLKOUT pin. 00478 */ 00479 /*@{*/ 00480 #define BP_SIM_SOPT2_RTCCLKOUTSEL (4U) /*!< Bit position for SIM_SOPT2_RTCCLKOUTSEL. */ 00481 #define BM_SIM_SOPT2_RTCCLKOUTSEL (0x00000010U) /*!< Bit mask for SIM_SOPT2_RTCCLKOUTSEL. */ 00482 #define BS_SIM_SOPT2_RTCCLKOUTSEL (1U) /*!< Bit field size in bits for SIM_SOPT2_RTCCLKOUTSEL. */ 00483 00484 /*! @brief Read current value of the SIM_SOPT2_RTCCLKOUTSEL field. */ 00485 #define BR_SIM_SOPT2_RTCCLKOUTSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RTCCLKOUTSEL)) 00486 00487 /*! @brief Format value for bitfield SIM_SOPT2_RTCCLKOUTSEL. */ 00488 #define BF_SIM_SOPT2_RTCCLKOUTSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_RTCCLKOUTSEL) & BM_SIM_SOPT2_RTCCLKOUTSEL) 00489 00490 /*! @brief Set the RTCCLKOUTSEL field to a new value. */ 00491 #define BW_SIM_SOPT2_RTCCLKOUTSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RTCCLKOUTSEL) = (v)) 00492 /*@}*/ 00493 00494 /*! 00495 * @name Register SIM_SOPT2, field CLKOUTSEL[7:5] (RW) 00496 * 00497 * Selects the clock to output on the CLKOUT pin. 00498 * 00499 * Values: 00500 * - 000 - FlexBus CLKOUT 00501 * - 001 - Reserved 00502 * - 010 - Flash clock 00503 * - 011 - LPO clock (1 kHz) 00504 * - 100 - MCGIRCLK 00505 * - 101 - RTC 32.768kHz clock 00506 * - 110 - OSCERCLK0 00507 * - 111 - IRC 48 MHz clock 00508 */ 00509 /*@{*/ 00510 #define BP_SIM_SOPT2_CLKOUTSEL (5U) /*!< Bit position for SIM_SOPT2_CLKOUTSEL. */ 00511 #define BM_SIM_SOPT2_CLKOUTSEL (0x000000E0U) /*!< Bit mask for SIM_SOPT2_CLKOUTSEL. */ 00512 #define BS_SIM_SOPT2_CLKOUTSEL (3U) /*!< Bit field size in bits for SIM_SOPT2_CLKOUTSEL. */ 00513 00514 /*! @brief Read current value of the SIM_SOPT2_CLKOUTSEL field. */ 00515 #define BR_SIM_SOPT2_CLKOUTSEL(x) (HW_SIM_SOPT2(x).B.CLKOUTSEL) 00516 00517 /*! @brief Format value for bitfield SIM_SOPT2_CLKOUTSEL. */ 00518 #define BF_SIM_SOPT2_CLKOUTSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_CLKOUTSEL) & BM_SIM_SOPT2_CLKOUTSEL) 00519 00520 /*! @brief Set the CLKOUTSEL field to a new value. */ 00521 #define BW_SIM_SOPT2_CLKOUTSEL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_CLKOUTSEL) | BF_SIM_SOPT2_CLKOUTSEL(v))) 00522 /*@}*/ 00523 00524 /*! 00525 * @name Register SIM_SOPT2, field FBSL[9:8] (RW) 00526 * 00527 * If flash security is enabled, then this field affects what CPU operations can 00528 * access off-chip via the FlexBus interface. This field has no effect if flash 00529 * security is not enabled. 00530 * 00531 * Values: 00532 * - 00 - All off-chip accesses (instruction and data) via the FlexBus are 00533 * disallowed. 00534 * - 01 - All off-chip accesses (instruction and data) via the FlexBus are 00535 * disallowed. 00536 * - 10 - Off-chip instruction accesses are disallowed. Data accesses are 00537 * allowed. 00538 * - 11 - Off-chip instruction accesses and data accesses are allowed. 00539 */ 00540 /*@{*/ 00541 #define BP_SIM_SOPT2_FBSL (8U) /*!< Bit position for SIM_SOPT2_FBSL. */ 00542 #define BM_SIM_SOPT2_FBSL (0x00000300U) /*!< Bit mask for SIM_SOPT2_FBSL. */ 00543 #define BS_SIM_SOPT2_FBSL (2U) /*!< Bit field size in bits for SIM_SOPT2_FBSL. */ 00544 00545 /*! @brief Read current value of the SIM_SOPT2_FBSL field. */ 00546 #define BR_SIM_SOPT2_FBSL(x) (HW_SIM_SOPT2(x).B.FBSL) 00547 00548 /*! @brief Format value for bitfield SIM_SOPT2_FBSL. */ 00549 #define BF_SIM_SOPT2_FBSL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_FBSL) & BM_SIM_SOPT2_FBSL) 00550 00551 /*! @brief Set the FBSL field to a new value. */ 00552 #define BW_SIM_SOPT2_FBSL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_FBSL) | BF_SIM_SOPT2_FBSL(v))) 00553 /*@}*/ 00554 00555 /*! 00556 * @name Register SIM_SOPT2, field PTD7PAD[11] (RW) 00557 * 00558 * Controls the output drive strength of the PTD7 pin by selecting either one or 00559 * two pads to drive it. 00560 * 00561 * Values: 00562 * - 0 - Single-pad drive strength for PTD7. 00563 * - 1 - Double pad drive strength for PTD7. 00564 */ 00565 /*@{*/ 00566 #define BP_SIM_SOPT2_PTD7PAD (11U) /*!< Bit position for SIM_SOPT2_PTD7PAD. */ 00567 #define BM_SIM_SOPT2_PTD7PAD (0x00000800U) /*!< Bit mask for SIM_SOPT2_PTD7PAD. */ 00568 #define BS_SIM_SOPT2_PTD7PAD (1U) /*!< Bit field size in bits for SIM_SOPT2_PTD7PAD. */ 00569 00570 /*! @brief Read current value of the SIM_SOPT2_PTD7PAD field. */ 00571 #define BR_SIM_SOPT2_PTD7PAD(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_PTD7PAD)) 00572 00573 /*! @brief Format value for bitfield SIM_SOPT2_PTD7PAD. */ 00574 #define BF_SIM_SOPT2_PTD7PAD(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_PTD7PAD) & BM_SIM_SOPT2_PTD7PAD) 00575 00576 /*! @brief Set the PTD7PAD field to a new value. */ 00577 #define BW_SIM_SOPT2_PTD7PAD(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_PTD7PAD) = (v)) 00578 /*@}*/ 00579 00580 /*! 00581 * @name Register SIM_SOPT2, field TRACECLKSEL[12] (RW) 00582 * 00583 * Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace 00584 * clock source. 00585 * 00586 * Values: 00587 * - 0 - MCGOUTCLK 00588 * - 1 - Core/system clock 00589 */ 00590 /*@{*/ 00591 #define BP_SIM_SOPT2_TRACECLKSEL (12U) /*!< Bit position for SIM_SOPT2_TRACECLKSEL. */ 00592 #define BM_SIM_SOPT2_TRACECLKSEL (0x00001000U) /*!< Bit mask for SIM_SOPT2_TRACECLKSEL. */ 00593 #define BS_SIM_SOPT2_TRACECLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT2_TRACECLKSEL. */ 00594 00595 /*! @brief Read current value of the SIM_SOPT2_TRACECLKSEL field. */ 00596 #define BR_SIM_SOPT2_TRACECLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_TRACECLKSEL)) 00597 00598 /*! @brief Format value for bitfield SIM_SOPT2_TRACECLKSEL. */ 00599 #define BF_SIM_SOPT2_TRACECLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_TRACECLKSEL) & BM_SIM_SOPT2_TRACECLKSEL) 00600 00601 /*! @brief Set the TRACECLKSEL field to a new value. */ 00602 #define BW_SIM_SOPT2_TRACECLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_TRACECLKSEL) = (v)) 00603 /*@}*/ 00604 00605 /*! 00606 * @name Register SIM_SOPT2, field PLLFLLSEL[17:16] (RW) 00607 * 00608 * Selects the high frequency clock for various peripheral clocking options. 00609 * 00610 * Values: 00611 * - 00 - MCGFLLCLK clock 00612 * - 01 - MCGPLLCLK clock 00613 * - 10 - Reserved 00614 * - 11 - IRC48 MHz clock 00615 */ 00616 /*@{*/ 00617 #define BP_SIM_SOPT2_PLLFLLSEL (16U) /*!< Bit position for SIM_SOPT2_PLLFLLSEL. */ 00618 #define BM_SIM_SOPT2_PLLFLLSEL (0x00030000U) /*!< Bit mask for SIM_SOPT2_PLLFLLSEL. */ 00619 #define BS_SIM_SOPT2_PLLFLLSEL (2U) /*!< Bit field size in bits for SIM_SOPT2_PLLFLLSEL. */ 00620 00621 /*! @brief Read current value of the SIM_SOPT2_PLLFLLSEL field. */ 00622 #define BR_SIM_SOPT2_PLLFLLSEL(x) (HW_SIM_SOPT2(x).B.PLLFLLSEL) 00623 00624 /*! @brief Format value for bitfield SIM_SOPT2_PLLFLLSEL. */ 00625 #define BF_SIM_SOPT2_PLLFLLSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_PLLFLLSEL) & BM_SIM_SOPT2_PLLFLLSEL) 00626 00627 /*! @brief Set the PLLFLLSEL field to a new value. */ 00628 #define BW_SIM_SOPT2_PLLFLLSEL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_PLLFLLSEL) | BF_SIM_SOPT2_PLLFLLSEL(v))) 00629 /*@}*/ 00630 00631 /*! 00632 * @name Register SIM_SOPT2, field USBSRC[18] (RW) 00633 * 00634 * Selects the clock source for the USB 48 MHz clock. 00635 * 00636 * Values: 00637 * - 0 - External bypass clock (USB_CLKIN). 00638 * - 1 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by 00639 * SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by 00640 * SIM_CLKDIV2[USBFRAC, USBDIV]. 00641 */ 00642 /*@{*/ 00643 #define BP_SIM_SOPT2_USBSRC (18U) /*!< Bit position for SIM_SOPT2_USBSRC. */ 00644 #define BM_SIM_SOPT2_USBSRC (0x00040000U) /*!< Bit mask for SIM_SOPT2_USBSRC. */ 00645 #define BS_SIM_SOPT2_USBSRC (1U) /*!< Bit field size in bits for SIM_SOPT2_USBSRC. */ 00646 00647 /*! @brief Read current value of the SIM_SOPT2_USBSRC field. */ 00648 #define BR_SIM_SOPT2_USBSRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_USBSRC)) 00649 00650 /*! @brief Format value for bitfield SIM_SOPT2_USBSRC. */ 00651 #define BF_SIM_SOPT2_USBSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_USBSRC) & BM_SIM_SOPT2_USBSRC) 00652 00653 /*! @brief Set the USBSRC field to a new value. */ 00654 #define BW_SIM_SOPT2_USBSRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_USBSRC) = (v)) 00655 /*@}*/ 00656 00657 /*! 00658 * @name Register SIM_SOPT2, field RMIISRC[19] (RW) 00659 * 00660 * Selects the clock source for the Ethernet RMII interface 00661 * 00662 * Values: 00663 * - 0 - EXTAL clock 00664 * - 1 - External bypass clock (ENET_1588_CLKIN). 00665 */ 00666 /*@{*/ 00667 #define BP_SIM_SOPT2_RMIISRC (19U) /*!< Bit position for SIM_SOPT2_RMIISRC. */ 00668 #define BM_SIM_SOPT2_RMIISRC (0x00080000U) /*!< Bit mask for SIM_SOPT2_RMIISRC. */ 00669 #define BS_SIM_SOPT2_RMIISRC (1U) /*!< Bit field size in bits for SIM_SOPT2_RMIISRC. */ 00670 00671 /*! @brief Read current value of the SIM_SOPT2_RMIISRC field. */ 00672 #define BR_SIM_SOPT2_RMIISRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RMIISRC)) 00673 00674 /*! @brief Format value for bitfield SIM_SOPT2_RMIISRC. */ 00675 #define BF_SIM_SOPT2_RMIISRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_RMIISRC) & BM_SIM_SOPT2_RMIISRC) 00676 00677 /*! @brief Set the RMIISRC field to a new value. */ 00678 #define BW_SIM_SOPT2_RMIISRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RMIISRC) = (v)) 00679 /*@}*/ 00680 00681 /*! 00682 * @name Register SIM_SOPT2, field TIMESRC[21:20] (RW) 00683 * 00684 * Selects the clock source for the Ethernet timestamp clock. 00685 * 00686 * Values: 00687 * - 00 - Core/system clock. 00688 * - 01 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by 00689 * SOPT2[PLLFLLSEL]. 00690 * - 10 - OSCERCLK clock 00691 * - 11 - External bypass clock (ENET_1588_CLKIN). 00692 */ 00693 /*@{*/ 00694 #define BP_SIM_SOPT2_TIMESRC (20U) /*!< Bit position for SIM_SOPT2_TIMESRC. */ 00695 #define BM_SIM_SOPT2_TIMESRC (0x00300000U) /*!< Bit mask for SIM_SOPT2_TIMESRC. */ 00696 #define BS_SIM_SOPT2_TIMESRC (2U) /*!< Bit field size in bits for SIM_SOPT2_TIMESRC. */ 00697 00698 /*! @brief Read current value of the SIM_SOPT2_TIMESRC field. */ 00699 #define BR_SIM_SOPT2_TIMESRC(x) (HW_SIM_SOPT2(x).B.TIMESRC) 00700 00701 /*! @brief Format value for bitfield SIM_SOPT2_TIMESRC. */ 00702 #define BF_SIM_SOPT2_TIMESRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_TIMESRC) & BM_SIM_SOPT2_TIMESRC) 00703 00704 /*! @brief Set the TIMESRC field to a new value. */ 00705 #define BW_SIM_SOPT2_TIMESRC(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_TIMESRC) | BF_SIM_SOPT2_TIMESRC(v))) 00706 /*@}*/ 00707 00708 /*! 00709 * @name Register SIM_SOPT2, field SDHCSRC[29:28] (RW) 00710 * 00711 * Selects the clock source for the SDHC clock . 00712 * 00713 * Values: 00714 * - 00 - Core/system clock. 00715 * - 01 - MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by 00716 * SOPT2[PLLFLLSEL]. 00717 * - 10 - OSCERCLK clock 00718 * - 11 - External bypass clock (SDHC0_CLKIN) 00719 */ 00720 /*@{*/ 00721 #define BP_SIM_SOPT2_SDHCSRC (28U) /*!< Bit position for SIM_SOPT2_SDHCSRC. */ 00722 #define BM_SIM_SOPT2_SDHCSRC (0x30000000U) /*!< Bit mask for SIM_SOPT2_SDHCSRC. */ 00723 #define BS_SIM_SOPT2_SDHCSRC (2U) /*!< Bit field size in bits for SIM_SOPT2_SDHCSRC. */ 00724 00725 /*! @brief Read current value of the SIM_SOPT2_SDHCSRC field. */ 00726 #define BR_SIM_SOPT2_SDHCSRC(x) (HW_SIM_SOPT2(x).B.SDHCSRC) 00727 00728 /*! @brief Format value for bitfield SIM_SOPT2_SDHCSRC. */ 00729 #define BF_SIM_SOPT2_SDHCSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_SDHCSRC) & BM_SIM_SOPT2_SDHCSRC) 00730 00731 /*! @brief Set the SDHCSRC field to a new value. */ 00732 #define BW_SIM_SOPT2_SDHCSRC(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_SDHCSRC) | BF_SIM_SOPT2_SDHCSRC(v))) 00733 /*@}*/ 00734 00735 /******************************************************************************* 00736 * HW_SIM_SOPT4 - System Options Register 4 00737 ******************************************************************************/ 00738 00739 /*! 00740 * @brief HW_SIM_SOPT4 - System Options Register 4 (RW) 00741 * 00742 * Reset value: 0x00000000U 00743 */ 00744 typedef union _hw_sim_sopt4 00745 { 00746 uint32_t U; 00747 struct _hw_sim_sopt4_bitfields 00748 { 00749 uint32_t FTM0FLT0 : 1; /*!< [0] FTM0 Fault 0 Select */ 00750 uint32_t FTM0FLT1 : 1; /*!< [1] FTM0 Fault 1 Select */ 00751 uint32_t FTM0FLT2 : 1; /*!< [2] FTM0 Fault 2 Select */ 00752 uint32_t RESERVED0 : 1; /*!< [3] */ 00753 uint32_t FTM1FLT0 : 1; /*!< [4] FTM1 Fault 0 Select */ 00754 uint32_t RESERVED1 : 3; /*!< [7:5] */ 00755 uint32_t FTM2FLT0 : 1; /*!< [8] FTM2 Fault 0 Select */ 00756 uint32_t RESERVED2 : 3; /*!< [11:9] */ 00757 uint32_t FTM3FLT0 : 1; /*!< [12] FTM3 Fault 0 Select */ 00758 uint32_t RESERVED3 : 5; /*!< [17:13] */ 00759 uint32_t FTM1CH0SRC : 2; /*!< [19:18] FTM1 channel 0 input capture 00760 * source select */ 00761 uint32_t FTM2CH0SRC : 2; /*!< [21:20] FTM2 channel 0 input capture 00762 * source select */ 00763 uint32_t RESERVED4 : 2; /*!< [23:22] */ 00764 uint32_t FTM0CLKSEL : 1; /*!< [24] FlexTimer 0 External Clock Pin 00765 * Select */ 00766 uint32_t FTM1CLKSEL : 1; /*!< [25] FTM1 External Clock Pin Select */ 00767 uint32_t FTM2CLKSEL : 1; /*!< [26] FlexTimer 2 External Clock Pin 00768 * Select */ 00769 uint32_t FTM3CLKSEL : 1; /*!< [27] FlexTimer 3 External Clock Pin 00770 * Select */ 00771 uint32_t FTM0TRG0SRC : 1; /*!< [28] FlexTimer 0 Hardware Trigger 0 00772 * Source Select */ 00773 uint32_t FTM0TRG1SRC : 1; /*!< [29] FlexTimer 0 Hardware Trigger 1 00774 * Source Select */ 00775 uint32_t FTM3TRG0SRC : 1; /*!< [30] FlexTimer 3 Hardware Trigger 0 00776 * Source Select */ 00777 uint32_t FTM3TRG1SRC : 1; /*!< [31] FlexTimer 3 Hardware Trigger 1 00778 * Source Select */ 00779 } B; 00780 } hw_sim_sopt4_t; 00781 00782 /*! 00783 * @name Constants and macros for entire SIM_SOPT4 register 00784 */ 00785 /*@{*/ 00786 #define HW_SIM_SOPT4_ADDR(x) ((x) + 0x100CU) 00787 00788 #define HW_SIM_SOPT4(x) (*(__IO hw_sim_sopt4_t *) HW_SIM_SOPT4_ADDR(x)) 00789 #define HW_SIM_SOPT4_RD(x) (HW_SIM_SOPT4(x).U) 00790 #define HW_SIM_SOPT4_WR(x, v) (HW_SIM_SOPT4(x).U = (v)) 00791 #define HW_SIM_SOPT4_SET(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) | (v))) 00792 #define HW_SIM_SOPT4_CLR(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) & ~(v))) 00793 #define HW_SIM_SOPT4_TOG(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) ^ (v))) 00794 /*@}*/ 00795 00796 /* 00797 * Constants & macros for individual SIM_SOPT4 bitfields 00798 */ 00799 00800 /*! 00801 * @name Register SIM_SOPT4, field FTM0FLT0[0] (RW) 00802 * 00803 * Selects the source of FTM0 fault 0. The pin source for fault 0 must be 00804 * configured for the FTM module fault function through the appropriate pin control 00805 * register in the port control module. 00806 * 00807 * Values: 00808 * - 0 - FTM0_FLT0 pin 00809 * - 1 - CMP0 out 00810 */ 00811 /*@{*/ 00812 #define BP_SIM_SOPT4_FTM0FLT0 (0U) /*!< Bit position for SIM_SOPT4_FTM0FLT0. */ 00813 #define BM_SIM_SOPT4_FTM0FLT0 (0x00000001U) /*!< Bit mask for SIM_SOPT4_FTM0FLT0. */ 00814 #define BS_SIM_SOPT4_FTM0FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0FLT0. */ 00815 00816 /*! @brief Read current value of the SIM_SOPT4_FTM0FLT0 field. */ 00817 #define BR_SIM_SOPT4_FTM0FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT0)) 00818 00819 /*! @brief Format value for bitfield SIM_SOPT4_FTM0FLT0. */ 00820 #define BF_SIM_SOPT4_FTM0FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT0) & BM_SIM_SOPT4_FTM0FLT0) 00821 00822 /*! @brief Set the FTM0FLT0 field to a new value. */ 00823 #define BW_SIM_SOPT4_FTM0FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT0) = (v)) 00824 /*@}*/ 00825 00826 /*! 00827 * @name Register SIM_SOPT4, field FTM0FLT1[1] (RW) 00828 * 00829 * Selects the source of FTM0 fault 1. The pin source for fault 1 must be 00830 * configured for the FTM module fault function through the appropriate pin control 00831 * register in the port control module. 00832 * 00833 * Values: 00834 * - 0 - FTM0_FLT1 pin 00835 * - 1 - CMP1 out 00836 */ 00837 /*@{*/ 00838 #define BP_SIM_SOPT4_FTM0FLT1 (1U) /*!< Bit position for SIM_SOPT4_FTM0FLT1. */ 00839 #define BM_SIM_SOPT4_FTM0FLT1 (0x00000002U) /*!< Bit mask for SIM_SOPT4_FTM0FLT1. */ 00840 #define BS_SIM_SOPT4_FTM0FLT1 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0FLT1. */ 00841 00842 /*! @brief Read current value of the SIM_SOPT4_FTM0FLT1 field. */ 00843 #define BR_SIM_SOPT4_FTM0FLT1(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT1)) 00844 00845 /*! @brief Format value for bitfield SIM_SOPT4_FTM0FLT1. */ 00846 #define BF_SIM_SOPT4_FTM0FLT1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT1) & BM_SIM_SOPT4_FTM0FLT1) 00847 00848 /*! @brief Set the FTM0FLT1 field to a new value. */ 00849 #define BW_SIM_SOPT4_FTM0FLT1(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT1) = (v)) 00850 /*@}*/ 00851 00852 /*! 00853 * @name Register SIM_SOPT4, field FTM0FLT2[2] (RW) 00854 * 00855 * Selects the source of FTM0 fault 2. The pin source for fault 2 must be 00856 * configured for the FTM module fault function through the appropriate pin control 00857 * register in the port control module. 00858 * 00859 * Values: 00860 * - 0 - FTM0_FLT2 pin 00861 * - 1 - CMP2 out 00862 */ 00863 /*@{*/ 00864 #define BP_SIM_SOPT4_FTM0FLT2 (2U) /*!< Bit position for SIM_SOPT4_FTM0FLT2. */ 00865 #define BM_SIM_SOPT4_FTM0FLT2 (0x00000004U) /*!< Bit mask for SIM_SOPT4_FTM0FLT2. */ 00866 #define BS_SIM_SOPT4_FTM0FLT2 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0FLT2. */ 00867 00868 /*! @brief Read current value of the SIM_SOPT4_FTM0FLT2 field. */ 00869 #define BR_SIM_SOPT4_FTM0FLT2(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT2)) 00870 00871 /*! @brief Format value for bitfield SIM_SOPT4_FTM0FLT2. */ 00872 #define BF_SIM_SOPT4_FTM0FLT2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT2) & BM_SIM_SOPT4_FTM0FLT2) 00873 00874 /*! @brief Set the FTM0FLT2 field to a new value. */ 00875 #define BW_SIM_SOPT4_FTM0FLT2(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT2) = (v)) 00876 /*@}*/ 00877 00878 /*! 00879 * @name Register SIM_SOPT4, field FTM1FLT0[4] (RW) 00880 * 00881 * Selects the source of FTM1 fault 0. The pin source for fault 0 must be 00882 * configured for the FTM module fault function through the appropriate pin control 00883 * register in the port control module. 00884 * 00885 * Values: 00886 * - 0 - FTM1_FLT0 pin 00887 * - 1 - CMP0 out 00888 */ 00889 /*@{*/ 00890 #define BP_SIM_SOPT4_FTM1FLT0 (4U) /*!< Bit position for SIM_SOPT4_FTM1FLT0. */ 00891 #define BM_SIM_SOPT4_FTM1FLT0 (0x00000010U) /*!< Bit mask for SIM_SOPT4_FTM1FLT0. */ 00892 #define BS_SIM_SOPT4_FTM1FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM1FLT0. */ 00893 00894 /*! @brief Read current value of the SIM_SOPT4_FTM1FLT0 field. */ 00895 #define BR_SIM_SOPT4_FTM1FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1FLT0)) 00896 00897 /*! @brief Format value for bitfield SIM_SOPT4_FTM1FLT0. */ 00898 #define BF_SIM_SOPT4_FTM1FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1FLT0) & BM_SIM_SOPT4_FTM1FLT0) 00899 00900 /*! @brief Set the FTM1FLT0 field to a new value. */ 00901 #define BW_SIM_SOPT4_FTM1FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1FLT0) = (v)) 00902 /*@}*/ 00903 00904 /*! 00905 * @name Register SIM_SOPT4, field FTM2FLT0[8] (RW) 00906 * 00907 * Selects the source of FTM2 fault 0. The pin source for fault 0 must be 00908 * configured for the FTM module fault function through the appropriate PORTx pin 00909 * control register. 00910 * 00911 * Values: 00912 * - 0 - FTM2_FLT0 pin 00913 * - 1 - CMP0 out 00914 */ 00915 /*@{*/ 00916 #define BP_SIM_SOPT4_FTM2FLT0 (8U) /*!< Bit position for SIM_SOPT4_FTM2FLT0. */ 00917 #define BM_SIM_SOPT4_FTM2FLT0 (0x00000100U) /*!< Bit mask for SIM_SOPT4_FTM2FLT0. */ 00918 #define BS_SIM_SOPT4_FTM2FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM2FLT0. */ 00919 00920 /*! @brief Read current value of the SIM_SOPT4_FTM2FLT0 field. */ 00921 #define BR_SIM_SOPT4_FTM2FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2FLT0)) 00922 00923 /*! @brief Format value for bitfield SIM_SOPT4_FTM2FLT0. */ 00924 #define BF_SIM_SOPT4_FTM2FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2FLT0) & BM_SIM_SOPT4_FTM2FLT0) 00925 00926 /*! @brief Set the FTM2FLT0 field to a new value. */ 00927 #define BW_SIM_SOPT4_FTM2FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2FLT0) = (v)) 00928 /*@}*/ 00929 00930 /*! 00931 * @name Register SIM_SOPT4, field FTM3FLT0[12] (RW) 00932 * 00933 * Selects the source of FTM3 fault 0. The pin source for fault 0 must be 00934 * configured for the FTM module fault function through the appropriate PORTx pin 00935 * control register. 00936 * 00937 * Values: 00938 * - 0 - FTM3_FLT0 pin 00939 * - 1 - CMP0 out 00940 */ 00941 /*@{*/ 00942 #define BP_SIM_SOPT4_FTM3FLT0 (12U) /*!< Bit position for SIM_SOPT4_FTM3FLT0. */ 00943 #define BM_SIM_SOPT4_FTM3FLT0 (0x00001000U) /*!< Bit mask for SIM_SOPT4_FTM3FLT0. */ 00944 #define BS_SIM_SOPT4_FTM3FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3FLT0. */ 00945 00946 /*! @brief Read current value of the SIM_SOPT4_FTM3FLT0 field. */ 00947 #define BR_SIM_SOPT4_FTM3FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3FLT0)) 00948 00949 /*! @brief Format value for bitfield SIM_SOPT4_FTM3FLT0. */ 00950 #define BF_SIM_SOPT4_FTM3FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3FLT0) & BM_SIM_SOPT4_FTM3FLT0) 00951 00952 /*! @brief Set the FTM3FLT0 field to a new value. */ 00953 #define BW_SIM_SOPT4_FTM3FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3FLT0) = (v)) 00954 /*@}*/ 00955 00956 /*! 00957 * @name Register SIM_SOPT4, field FTM1CH0SRC[19:18] (RW) 00958 * 00959 * Selects the source for FTM1 channel 0 input capture. When the FTM is not in 00960 * input capture mode, clear this field. 00961 * 00962 * Values: 00963 * - 00 - FTM1_CH0 signal 00964 * - 01 - CMP0 output 00965 * - 10 - CMP1 output 00966 * - 11 - USB start of frame pulse 00967 */ 00968 /*@{*/ 00969 #define BP_SIM_SOPT4_FTM1CH0SRC (18U) /*!< Bit position for SIM_SOPT4_FTM1CH0SRC. */ 00970 #define BM_SIM_SOPT4_FTM1CH0SRC (0x000C0000U) /*!< Bit mask for SIM_SOPT4_FTM1CH0SRC. */ 00971 #define BS_SIM_SOPT4_FTM1CH0SRC (2U) /*!< Bit field size in bits for SIM_SOPT4_FTM1CH0SRC. */ 00972 00973 /*! @brief Read current value of the SIM_SOPT4_FTM1CH0SRC field. */ 00974 #define BR_SIM_SOPT4_FTM1CH0SRC(x) (HW_SIM_SOPT4(x).B.FTM1CH0SRC) 00975 00976 /*! @brief Format value for bitfield SIM_SOPT4_FTM1CH0SRC. */ 00977 #define BF_SIM_SOPT4_FTM1CH0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1CH0SRC) & BM_SIM_SOPT4_FTM1CH0SRC) 00978 00979 /*! @brief Set the FTM1CH0SRC field to a new value. */ 00980 #define BW_SIM_SOPT4_FTM1CH0SRC(x, v) (HW_SIM_SOPT4_WR(x, (HW_SIM_SOPT4_RD(x) & ~BM_SIM_SOPT4_FTM1CH0SRC) | BF_SIM_SOPT4_FTM1CH0SRC(v))) 00981 /*@}*/ 00982 00983 /*! 00984 * @name Register SIM_SOPT4, field FTM2CH0SRC[21:20] (RW) 00985 * 00986 * Selects the source for FTM2 channel 0 input capture. When the FTM is not in 00987 * input capture mode, clear this field. 00988 * 00989 * Values: 00990 * - 00 - FTM2_CH0 signal 00991 * - 01 - CMP0 output 00992 * - 10 - CMP1 output 00993 * - 11 - Reserved 00994 */ 00995 /*@{*/ 00996 #define BP_SIM_SOPT4_FTM2CH0SRC (20U) /*!< Bit position for SIM_SOPT4_FTM2CH0SRC. */ 00997 #define BM_SIM_SOPT4_FTM2CH0SRC (0x00300000U) /*!< Bit mask for SIM_SOPT4_FTM2CH0SRC. */ 00998 #define BS_SIM_SOPT4_FTM2CH0SRC (2U) /*!< Bit field size in bits for SIM_SOPT4_FTM2CH0SRC. */ 00999 01000 /*! @brief Read current value of the SIM_SOPT4_FTM2CH0SRC field. */ 01001 #define BR_SIM_SOPT4_FTM2CH0SRC(x) (HW_SIM_SOPT4(x).B.FTM2CH0SRC) 01002 01003 /*! @brief Format value for bitfield SIM_SOPT4_FTM2CH0SRC. */ 01004 #define BF_SIM_SOPT4_FTM2CH0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2CH0SRC) & BM_SIM_SOPT4_FTM2CH0SRC) 01005 01006 /*! @brief Set the FTM2CH0SRC field to a new value. */ 01007 #define BW_SIM_SOPT4_FTM2CH0SRC(x, v) (HW_SIM_SOPT4_WR(x, (HW_SIM_SOPT4_RD(x) & ~BM_SIM_SOPT4_FTM2CH0SRC) | BF_SIM_SOPT4_FTM2CH0SRC(v))) 01008 /*@}*/ 01009 01010 /*! 01011 * @name Register SIM_SOPT4, field FTM0CLKSEL[24] (RW) 01012 * 01013 * Selects the external pin used to drive the clock to the FTM0 module. The 01014 * selected pin must also be configured for the FTM external clock function through 01015 * the appropriate pin control register in the port control module. 01016 * 01017 * Values: 01018 * - 0 - FTM_CLK0 pin 01019 * - 1 - FTM_CLK1 pin 01020 */ 01021 /*@{*/ 01022 #define BP_SIM_SOPT4_FTM0CLKSEL (24U) /*!< Bit position for SIM_SOPT4_FTM0CLKSEL. */ 01023 #define BM_SIM_SOPT4_FTM0CLKSEL (0x01000000U) /*!< Bit mask for SIM_SOPT4_FTM0CLKSEL. */ 01024 #define BS_SIM_SOPT4_FTM0CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0CLKSEL. */ 01025 01026 /*! @brief Read current value of the SIM_SOPT4_FTM0CLKSEL field. */ 01027 #define BR_SIM_SOPT4_FTM0CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0CLKSEL)) 01028 01029 /*! @brief Format value for bitfield SIM_SOPT4_FTM0CLKSEL. */ 01030 #define BF_SIM_SOPT4_FTM0CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0CLKSEL) & BM_SIM_SOPT4_FTM0CLKSEL) 01031 01032 /*! @brief Set the FTM0CLKSEL field to a new value. */ 01033 #define BW_SIM_SOPT4_FTM0CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0CLKSEL) = (v)) 01034 /*@}*/ 01035 01036 /*! 01037 * @name Register SIM_SOPT4, field FTM1CLKSEL[25] (RW) 01038 * 01039 * Selects the external pin used to drive the clock to the FTM1 module. The 01040 * selected pin must also be configured for the FTM external clock function through 01041 * the appropriate pin control register in the port control module. 01042 * 01043 * Values: 01044 * - 0 - FTM_CLK0 pin 01045 * - 1 - FTM_CLK1 pin 01046 */ 01047 /*@{*/ 01048 #define BP_SIM_SOPT4_FTM1CLKSEL (25U) /*!< Bit position for SIM_SOPT4_FTM1CLKSEL. */ 01049 #define BM_SIM_SOPT4_FTM1CLKSEL (0x02000000U) /*!< Bit mask for SIM_SOPT4_FTM1CLKSEL. */ 01050 #define BS_SIM_SOPT4_FTM1CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM1CLKSEL. */ 01051 01052 /*! @brief Read current value of the SIM_SOPT4_FTM1CLKSEL field. */ 01053 #define BR_SIM_SOPT4_FTM1CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1CLKSEL)) 01054 01055 /*! @brief Format value for bitfield SIM_SOPT4_FTM1CLKSEL. */ 01056 #define BF_SIM_SOPT4_FTM1CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1CLKSEL) & BM_SIM_SOPT4_FTM1CLKSEL) 01057 01058 /*! @brief Set the FTM1CLKSEL field to a new value. */ 01059 #define BW_SIM_SOPT4_FTM1CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1CLKSEL) = (v)) 01060 /*@}*/ 01061 01062 /*! 01063 * @name Register SIM_SOPT4, field FTM2CLKSEL[26] (RW) 01064 * 01065 * Selects the external pin used to drive the clock to the FTM2 module. The 01066 * selected pin must also be configured for the FTM2 module external clock function 01067 * through the appropriate pin control register in the port control module. 01068 * 01069 * Values: 01070 * - 0 - FTM2 external clock driven by FTM_CLK0 pin. 01071 * - 1 - FTM2 external clock driven by FTM_CLK1 pin. 01072 */ 01073 /*@{*/ 01074 #define BP_SIM_SOPT4_FTM2CLKSEL (26U) /*!< Bit position for SIM_SOPT4_FTM2CLKSEL. */ 01075 #define BM_SIM_SOPT4_FTM2CLKSEL (0x04000000U) /*!< Bit mask for SIM_SOPT4_FTM2CLKSEL. */ 01076 #define BS_SIM_SOPT4_FTM2CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM2CLKSEL. */ 01077 01078 /*! @brief Read current value of the SIM_SOPT4_FTM2CLKSEL field. */ 01079 #define BR_SIM_SOPT4_FTM2CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2CLKSEL)) 01080 01081 /*! @brief Format value for bitfield SIM_SOPT4_FTM2CLKSEL. */ 01082 #define BF_SIM_SOPT4_FTM2CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2CLKSEL) & BM_SIM_SOPT4_FTM2CLKSEL) 01083 01084 /*! @brief Set the FTM2CLKSEL field to a new value. */ 01085 #define BW_SIM_SOPT4_FTM2CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2CLKSEL) = (v)) 01086 /*@}*/ 01087 01088 /*! 01089 * @name Register SIM_SOPT4, field FTM3CLKSEL[27] (RW) 01090 * 01091 * Selects the external pin used to drive the clock to the FTM3 module. The 01092 * selected pin must also be configured for the FTM3 module external clock function 01093 * through the appropriate pin control register in the port control module. 01094 * 01095 * Values: 01096 * - 0 - FTM3 external clock driven by FTM_CLK0 pin. 01097 * - 1 - FTM3 external clock driven by FTM_CLK1 pin. 01098 */ 01099 /*@{*/ 01100 #define BP_SIM_SOPT4_FTM3CLKSEL (27U) /*!< Bit position for SIM_SOPT4_FTM3CLKSEL. */ 01101 #define BM_SIM_SOPT4_FTM3CLKSEL (0x08000000U) /*!< Bit mask for SIM_SOPT4_FTM3CLKSEL. */ 01102 #define BS_SIM_SOPT4_FTM3CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3CLKSEL. */ 01103 01104 /*! @brief Read current value of the SIM_SOPT4_FTM3CLKSEL field. */ 01105 #define BR_SIM_SOPT4_FTM3CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3CLKSEL)) 01106 01107 /*! @brief Format value for bitfield SIM_SOPT4_FTM3CLKSEL. */ 01108 #define BF_SIM_SOPT4_FTM3CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3CLKSEL) & BM_SIM_SOPT4_FTM3CLKSEL) 01109 01110 /*! @brief Set the FTM3CLKSEL field to a new value. */ 01111 #define BW_SIM_SOPT4_FTM3CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3CLKSEL) = (v)) 01112 /*@}*/ 01113 01114 /*! 01115 * @name Register SIM_SOPT4, field FTM0TRG0SRC[28] (RW) 01116 * 01117 * Selects the source of FTM0 hardware trigger 0. 01118 * 01119 * Values: 01120 * - 0 - HSCMP0 output drives FTM0 hardware trigger 0 01121 * - 1 - FTM1 channel match drives FTM0 hardware trigger 0 01122 */ 01123 /*@{*/ 01124 #define BP_SIM_SOPT4_FTM0TRG0SRC (28U) /*!< Bit position for SIM_SOPT4_FTM0TRG0SRC. */ 01125 #define BM_SIM_SOPT4_FTM0TRG0SRC (0x10000000U) /*!< Bit mask for SIM_SOPT4_FTM0TRG0SRC. */ 01126 #define BS_SIM_SOPT4_FTM0TRG0SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0TRG0SRC. */ 01127 01128 /*! @brief Read current value of the SIM_SOPT4_FTM0TRG0SRC field. */ 01129 #define BR_SIM_SOPT4_FTM0TRG0SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG0SRC)) 01130 01131 /*! @brief Format value for bitfield SIM_SOPT4_FTM0TRG0SRC. */ 01132 #define BF_SIM_SOPT4_FTM0TRG0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0TRG0SRC) & BM_SIM_SOPT4_FTM0TRG0SRC) 01133 01134 /*! @brief Set the FTM0TRG0SRC field to a new value. */ 01135 #define BW_SIM_SOPT4_FTM0TRG0SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG0SRC) = (v)) 01136 /*@}*/ 01137 01138 /*! 01139 * @name Register SIM_SOPT4, field FTM0TRG1SRC[29] (RW) 01140 * 01141 * Selects the source of FTM0 hardware trigger 1. 01142 * 01143 * Values: 01144 * - 0 - PDB output trigger 1 drives FTM0 hardware trigger 1 01145 * - 1 - FTM2 channel match drives FTM0 hardware trigger 1 01146 */ 01147 /*@{*/ 01148 #define BP_SIM_SOPT4_FTM0TRG1SRC (29U) /*!< Bit position for SIM_SOPT4_FTM0TRG1SRC. */ 01149 #define BM_SIM_SOPT4_FTM0TRG1SRC (0x20000000U) /*!< Bit mask for SIM_SOPT4_FTM0TRG1SRC. */ 01150 #define BS_SIM_SOPT4_FTM0TRG1SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0TRG1SRC. */ 01151 01152 /*! @brief Read current value of the SIM_SOPT4_FTM0TRG1SRC field. */ 01153 #define BR_SIM_SOPT4_FTM0TRG1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG1SRC)) 01154 01155 /*! @brief Format value for bitfield SIM_SOPT4_FTM0TRG1SRC. */ 01156 #define BF_SIM_SOPT4_FTM0TRG1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0TRG1SRC) & BM_SIM_SOPT4_FTM0TRG1SRC) 01157 01158 /*! @brief Set the FTM0TRG1SRC field to a new value. */ 01159 #define BW_SIM_SOPT4_FTM0TRG1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG1SRC) = (v)) 01160 /*@}*/ 01161 01162 /*! 01163 * @name Register SIM_SOPT4, field FTM3TRG0SRC[30] (RW) 01164 * 01165 * Selects the source of FTM3 hardware trigger 0. 01166 * 01167 * Values: 01168 * - 0 - Reserved 01169 * - 1 - FTM1 channel match drives FTM3 hardware trigger 0 01170 */ 01171 /*@{*/ 01172 #define BP_SIM_SOPT4_FTM3TRG0SRC (30U) /*!< Bit position for SIM_SOPT4_FTM3TRG0SRC. */ 01173 #define BM_SIM_SOPT4_FTM3TRG0SRC (0x40000000U) /*!< Bit mask for SIM_SOPT4_FTM3TRG0SRC. */ 01174 #define BS_SIM_SOPT4_FTM3TRG0SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3TRG0SRC. */ 01175 01176 /*! @brief Read current value of the SIM_SOPT4_FTM3TRG0SRC field. */ 01177 #define BR_SIM_SOPT4_FTM3TRG0SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG0SRC)) 01178 01179 /*! @brief Format value for bitfield SIM_SOPT4_FTM3TRG0SRC. */ 01180 #define BF_SIM_SOPT4_FTM3TRG0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3TRG0SRC) & BM_SIM_SOPT4_FTM3TRG0SRC) 01181 01182 /*! @brief Set the FTM3TRG0SRC field to a new value. */ 01183 #define BW_SIM_SOPT4_FTM3TRG0SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG0SRC) = (v)) 01184 /*@}*/ 01185 01186 /*! 01187 * @name Register SIM_SOPT4, field FTM3TRG1SRC[31] (RW) 01188 * 01189 * Selects the source of FTM3 hardware trigger 1. 01190 * 01191 * Values: 01192 * - 0 - Reserved 01193 * - 1 - FTM2 channel match drives FTM3 hardware trigger 1 01194 */ 01195 /*@{*/ 01196 #define BP_SIM_SOPT4_FTM3TRG1SRC (31U) /*!< Bit position for SIM_SOPT4_FTM3TRG1SRC. */ 01197 #define BM_SIM_SOPT4_FTM3TRG1SRC (0x80000000U) /*!< Bit mask for SIM_SOPT4_FTM3TRG1SRC. */ 01198 #define BS_SIM_SOPT4_FTM3TRG1SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3TRG1SRC. */ 01199 01200 /*! @brief Read current value of the SIM_SOPT4_FTM3TRG1SRC field. */ 01201 #define BR_SIM_SOPT4_FTM3TRG1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG1SRC)) 01202 01203 /*! @brief Format value for bitfield SIM_SOPT4_FTM3TRG1SRC. */ 01204 #define BF_SIM_SOPT4_FTM3TRG1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3TRG1SRC) & BM_SIM_SOPT4_FTM3TRG1SRC) 01205 01206 /*! @brief Set the FTM3TRG1SRC field to a new value. */ 01207 #define BW_SIM_SOPT4_FTM3TRG1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG1SRC) = (v)) 01208 /*@}*/ 01209 01210 /******************************************************************************* 01211 * HW_SIM_SOPT5 - System Options Register 5 01212 ******************************************************************************/ 01213 01214 /*! 01215 * @brief HW_SIM_SOPT5 - System Options Register 5 (RW) 01216 * 01217 * Reset value: 0x00000000U 01218 */ 01219 typedef union _hw_sim_sopt5 01220 { 01221 uint32_t U; 01222 struct _hw_sim_sopt5_bitfields 01223 { 01224 uint32_t UART0TXSRC : 2; /*!< [1:0] UART 0 transmit data source 01225 * select */ 01226 uint32_t UART0RXSRC : 2; /*!< [3:2] UART 0 receive data source select 01227 * */ 01228 uint32_t UART1TXSRC : 2; /*!< [5:4] UART 1 transmit data source 01229 * select */ 01230 uint32_t UART1RXSRC : 2; /*!< [7:6] UART 1 receive data source select 01231 * */ 01232 uint32_t RESERVED0 : 24; /*!< [31:8] */ 01233 } B; 01234 } hw_sim_sopt5_t; 01235 01236 /*! 01237 * @name Constants and macros for entire SIM_SOPT5 register 01238 */ 01239 /*@{*/ 01240 #define HW_SIM_SOPT5_ADDR(x) ((x) + 0x1010U) 01241 01242 #define HW_SIM_SOPT5(x) (*(__IO hw_sim_sopt5_t *) HW_SIM_SOPT5_ADDR(x)) 01243 #define HW_SIM_SOPT5_RD(x) (HW_SIM_SOPT5(x).U) 01244 #define HW_SIM_SOPT5_WR(x, v) (HW_SIM_SOPT5(x).U = (v)) 01245 #define HW_SIM_SOPT5_SET(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) | (v))) 01246 #define HW_SIM_SOPT5_CLR(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) & ~(v))) 01247 #define HW_SIM_SOPT5_TOG(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) ^ (v))) 01248 /*@}*/ 01249 01250 /* 01251 * Constants & macros for individual SIM_SOPT5 bitfields 01252 */ 01253 01254 /*! 01255 * @name Register SIM_SOPT5, field UART0TXSRC[1:0] (RW) 01256 * 01257 * Selects the source for the UART 0 transmit data. 01258 * 01259 * Values: 01260 * - 00 - UART0_TX pin 01261 * - 01 - UART0_TX pin modulated with FTM1 channel 0 output 01262 * - 10 - UART0_TX pin modulated with FTM2 channel 0 output 01263 * - 11 - Reserved 01264 */ 01265 /*@{*/ 01266 #define BP_SIM_SOPT5_UART0TXSRC (0U) /*!< Bit position for SIM_SOPT5_UART0TXSRC. */ 01267 #define BM_SIM_SOPT5_UART0TXSRC (0x00000003U) /*!< Bit mask for SIM_SOPT5_UART0TXSRC. */ 01268 #define BS_SIM_SOPT5_UART0TXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART0TXSRC. */ 01269 01270 /*! @brief Read current value of the SIM_SOPT5_UART0TXSRC field. */ 01271 #define BR_SIM_SOPT5_UART0TXSRC(x) (HW_SIM_SOPT5(x).B.UART0TXSRC) 01272 01273 /*! @brief Format value for bitfield SIM_SOPT5_UART0TXSRC. */ 01274 #define BF_SIM_SOPT5_UART0TXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART0TXSRC) & BM_SIM_SOPT5_UART0TXSRC) 01275 01276 /*! @brief Set the UART0TXSRC field to a new value. */ 01277 #define BW_SIM_SOPT5_UART0TXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART0TXSRC) | BF_SIM_SOPT5_UART0TXSRC(v))) 01278 /*@}*/ 01279 01280 /*! 01281 * @name Register SIM_SOPT5, field UART0RXSRC[3:2] (RW) 01282 * 01283 * Selects the source for the UART 0 receive data. 01284 * 01285 * Values: 01286 * - 00 - UART0_RX pin 01287 * - 01 - CMP0 01288 * - 10 - CMP1 01289 * - 11 - Reserved 01290 */ 01291 /*@{*/ 01292 #define BP_SIM_SOPT5_UART0RXSRC (2U) /*!< Bit position for SIM_SOPT5_UART0RXSRC. */ 01293 #define BM_SIM_SOPT5_UART0RXSRC (0x0000000CU) /*!< Bit mask for SIM_SOPT5_UART0RXSRC. */ 01294 #define BS_SIM_SOPT5_UART0RXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART0RXSRC. */ 01295 01296 /*! @brief Read current value of the SIM_SOPT5_UART0RXSRC field. */ 01297 #define BR_SIM_SOPT5_UART0RXSRC(x) (HW_SIM_SOPT5(x).B.UART0RXSRC) 01298 01299 /*! @brief Format value for bitfield SIM_SOPT5_UART0RXSRC. */ 01300 #define BF_SIM_SOPT5_UART0RXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART0RXSRC) & BM_SIM_SOPT5_UART0RXSRC) 01301 01302 /*! @brief Set the UART0RXSRC field to a new value. */ 01303 #define BW_SIM_SOPT5_UART0RXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART0RXSRC) | BF_SIM_SOPT5_UART0RXSRC(v))) 01304 /*@}*/ 01305 01306 /*! 01307 * @name Register SIM_SOPT5, field UART1TXSRC[5:4] (RW) 01308 * 01309 * Selects the source for the UART 1 transmit data. 01310 * 01311 * Values: 01312 * - 00 - UART1_TX pin 01313 * - 01 - UART1_TX pin modulated with FTM1 channel 0 output 01314 * - 10 - UART1_TX pin modulated with FTM2 channel 0 output 01315 * - 11 - Reserved 01316 */ 01317 /*@{*/ 01318 #define BP_SIM_SOPT5_UART1TXSRC (4U) /*!< Bit position for SIM_SOPT5_UART1TXSRC. */ 01319 #define BM_SIM_SOPT5_UART1TXSRC (0x00000030U) /*!< Bit mask for SIM_SOPT5_UART1TXSRC. */ 01320 #define BS_SIM_SOPT5_UART1TXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART1TXSRC. */ 01321 01322 /*! @brief Read current value of the SIM_SOPT5_UART1TXSRC field. */ 01323 #define BR_SIM_SOPT5_UART1TXSRC(x) (HW_SIM_SOPT5(x).B.UART1TXSRC) 01324 01325 /*! @brief Format value for bitfield SIM_SOPT5_UART1TXSRC. */ 01326 #define BF_SIM_SOPT5_UART1TXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART1TXSRC) & BM_SIM_SOPT5_UART1TXSRC) 01327 01328 /*! @brief Set the UART1TXSRC field to a new value. */ 01329 #define BW_SIM_SOPT5_UART1TXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART1TXSRC) | BF_SIM_SOPT5_UART1TXSRC(v))) 01330 /*@}*/ 01331 01332 /*! 01333 * @name Register SIM_SOPT5, field UART1RXSRC[7:6] (RW) 01334 * 01335 * Selects the source for the UART 1 receive data. 01336 * 01337 * Values: 01338 * - 00 - UART1_RX pin 01339 * - 01 - CMP0 01340 * - 10 - CMP1 01341 * - 11 - Reserved 01342 */ 01343 /*@{*/ 01344 #define BP_SIM_SOPT5_UART1RXSRC (6U) /*!< Bit position for SIM_SOPT5_UART1RXSRC. */ 01345 #define BM_SIM_SOPT5_UART1RXSRC (0x000000C0U) /*!< Bit mask for SIM_SOPT5_UART1RXSRC. */ 01346 #define BS_SIM_SOPT5_UART1RXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART1RXSRC. */ 01347 01348 /*! @brief Read current value of the SIM_SOPT5_UART1RXSRC field. */ 01349 #define BR_SIM_SOPT5_UART1RXSRC(x) (HW_SIM_SOPT5(x).B.UART1RXSRC) 01350 01351 /*! @brief Format value for bitfield SIM_SOPT5_UART1RXSRC. */ 01352 #define BF_SIM_SOPT5_UART1RXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART1RXSRC) & BM_SIM_SOPT5_UART1RXSRC) 01353 01354 /*! @brief Set the UART1RXSRC field to a new value. */ 01355 #define BW_SIM_SOPT5_UART1RXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART1RXSRC) | BF_SIM_SOPT5_UART1RXSRC(v))) 01356 /*@}*/ 01357 01358 /******************************************************************************* 01359 * HW_SIM_SOPT7 - System Options Register 7 01360 ******************************************************************************/ 01361 01362 /*! 01363 * @brief HW_SIM_SOPT7 - System Options Register 7 (RW) 01364 * 01365 * Reset value: 0x00000000U 01366 */ 01367 typedef union _hw_sim_sopt7 01368 { 01369 uint32_t U; 01370 struct _hw_sim_sopt7_bitfields 01371 { 01372 uint32_t ADC0TRGSEL : 4; /*!< [3:0] ADC0 trigger select */ 01373 uint32_t ADC0PRETRGSEL : 1; /*!< [4] ADC0 pretrigger select */ 01374 uint32_t RESERVED0 : 2; /*!< [6:5] */ 01375 uint32_t ADC0ALTTRGEN : 1; /*!< [7] ADC0 alternate trigger enable */ 01376 uint32_t ADC1TRGSEL : 4; /*!< [11:8] ADC1 trigger select */ 01377 uint32_t ADC1PRETRGSEL : 1; /*!< [12] ADC1 pre-trigger select */ 01378 uint32_t RESERVED1 : 2; /*!< [14:13] */ 01379 uint32_t ADC1ALTTRGEN : 1; /*!< [15] ADC1 alternate trigger enable */ 01380 uint32_t RESERVED2 : 16; /*!< [31:16] */ 01381 } B; 01382 } hw_sim_sopt7_t; 01383 01384 /*! 01385 * @name Constants and macros for entire SIM_SOPT7 register 01386 */ 01387 /*@{*/ 01388 #define HW_SIM_SOPT7_ADDR(x) ((x) + 0x1018U) 01389 01390 #define HW_SIM_SOPT7(x) (*(__IO hw_sim_sopt7_t *) HW_SIM_SOPT7_ADDR(x)) 01391 #define HW_SIM_SOPT7_RD(x) (HW_SIM_SOPT7(x).U) 01392 #define HW_SIM_SOPT7_WR(x, v) (HW_SIM_SOPT7(x).U = (v)) 01393 #define HW_SIM_SOPT7_SET(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) | (v))) 01394 #define HW_SIM_SOPT7_CLR(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) & ~(v))) 01395 #define HW_SIM_SOPT7_TOG(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) ^ (v))) 01396 /*@}*/ 01397 01398 /* 01399 * Constants & macros for individual SIM_SOPT7 bitfields 01400 */ 01401 01402 /*! 01403 * @name Register SIM_SOPT7, field ADC0TRGSEL[3:0] (RW) 01404 * 01405 * Selects the ADC0 trigger source when alternative triggers are functional in 01406 * stop and VLPS modes. . 01407 * 01408 * Values: 01409 * - 0000 - PDB external trigger pin input (PDB0_EXTRG) 01410 * - 0001 - High speed comparator 0 output 01411 * - 0010 - High speed comparator 1 output 01412 * - 0011 - High speed comparator 2 output 01413 * - 0100 - PIT trigger 0 01414 * - 0101 - PIT trigger 1 01415 * - 0110 - PIT trigger 2 01416 * - 0111 - PIT trigger 3 01417 * - 1000 - FTM0 trigger 01418 * - 1001 - FTM1 trigger 01419 * - 1010 - FTM2 trigger 01420 * - 1011 - FTM3 trigger 01421 * - 1100 - RTC alarm 01422 * - 1101 - RTC seconds 01423 * - 1110 - Low-power timer (LPTMR) trigger 01424 * - 1111 - Reserved 01425 */ 01426 /*@{*/ 01427 #define BP_SIM_SOPT7_ADC0TRGSEL (0U) /*!< Bit position for SIM_SOPT7_ADC0TRGSEL. */ 01428 #define BM_SIM_SOPT7_ADC0TRGSEL (0x0000000FU) /*!< Bit mask for SIM_SOPT7_ADC0TRGSEL. */ 01429 #define BS_SIM_SOPT7_ADC0TRGSEL (4U) /*!< Bit field size in bits for SIM_SOPT7_ADC0TRGSEL. */ 01430 01431 /*! @brief Read current value of the SIM_SOPT7_ADC0TRGSEL field. */ 01432 #define BR_SIM_SOPT7_ADC0TRGSEL(x) (HW_SIM_SOPT7(x).B.ADC0TRGSEL) 01433 01434 /*! @brief Format value for bitfield SIM_SOPT7_ADC0TRGSEL. */ 01435 #define BF_SIM_SOPT7_ADC0TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0TRGSEL) & BM_SIM_SOPT7_ADC0TRGSEL) 01436 01437 /*! @brief Set the ADC0TRGSEL field to a new value. */ 01438 #define BW_SIM_SOPT7_ADC0TRGSEL(x, v) (HW_SIM_SOPT7_WR(x, (HW_SIM_SOPT7_RD(x) & ~BM_SIM_SOPT7_ADC0TRGSEL) | BF_SIM_SOPT7_ADC0TRGSEL(v))) 01439 /*@}*/ 01440 01441 /*! 01442 * @name Register SIM_SOPT7, field ADC0PRETRGSEL[4] (RW) 01443 * 01444 * Selects the ADC0 pre-trigger source when alternative triggers are enabled 01445 * through ADC0ALTTRGEN. 01446 * 01447 * Values: 01448 * - 0 - Pre-trigger A 01449 * - 1 - Pre-trigger B 01450 */ 01451 /*@{*/ 01452 #define BP_SIM_SOPT7_ADC0PRETRGSEL (4U) /*!< Bit position for SIM_SOPT7_ADC0PRETRGSEL. */ 01453 #define BM_SIM_SOPT7_ADC0PRETRGSEL (0x00000010U) /*!< Bit mask for SIM_SOPT7_ADC0PRETRGSEL. */ 01454 #define BS_SIM_SOPT7_ADC0PRETRGSEL (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC0PRETRGSEL. */ 01455 01456 /*! @brief Read current value of the SIM_SOPT7_ADC0PRETRGSEL field. */ 01457 #define BR_SIM_SOPT7_ADC0PRETRGSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0PRETRGSEL)) 01458 01459 /*! @brief Format value for bitfield SIM_SOPT7_ADC0PRETRGSEL. */ 01460 #define BF_SIM_SOPT7_ADC0PRETRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0PRETRGSEL) & BM_SIM_SOPT7_ADC0PRETRGSEL) 01461 01462 /*! @brief Set the ADC0PRETRGSEL field to a new value. */ 01463 #define BW_SIM_SOPT7_ADC0PRETRGSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0PRETRGSEL) = (v)) 01464 /*@}*/ 01465 01466 /*! 01467 * @name Register SIM_SOPT7, field ADC0ALTTRGEN[7] (RW) 01468 * 01469 * Enable alternative conversion triggers for ADC0. 01470 * 01471 * Values: 01472 * - 0 - PDB trigger selected for ADC0. 01473 * - 1 - Alternate trigger selected for ADC0. 01474 */ 01475 /*@{*/ 01476 #define BP_SIM_SOPT7_ADC0ALTTRGEN (7U) /*!< Bit position for SIM_SOPT7_ADC0ALTTRGEN. */ 01477 #define BM_SIM_SOPT7_ADC0ALTTRGEN (0x00000080U) /*!< Bit mask for SIM_SOPT7_ADC0ALTTRGEN. */ 01478 #define BS_SIM_SOPT7_ADC0ALTTRGEN (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC0ALTTRGEN. */ 01479 01480 /*! @brief Read current value of the SIM_SOPT7_ADC0ALTTRGEN field. */ 01481 #define BR_SIM_SOPT7_ADC0ALTTRGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0ALTTRGEN)) 01482 01483 /*! @brief Format value for bitfield SIM_SOPT7_ADC0ALTTRGEN. */ 01484 #define BF_SIM_SOPT7_ADC0ALTTRGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0ALTTRGEN) & BM_SIM_SOPT7_ADC0ALTTRGEN) 01485 01486 /*! @brief Set the ADC0ALTTRGEN field to a new value. */ 01487 #define BW_SIM_SOPT7_ADC0ALTTRGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0ALTTRGEN) = (v)) 01488 /*@}*/ 01489 01490 /*! 01491 * @name Register SIM_SOPT7, field ADC1TRGSEL[11:8] (RW) 01492 * 01493 * Selects the ADC1 trigger source when alternative triggers are functional in 01494 * stop and VLPS modes. 01495 * 01496 * Values: 01497 * - 0000 - PDB external trigger pin input (PDB0_EXTRG) 01498 * - 0001 - High speed comparator 0 output 01499 * - 0010 - High speed comparator 1 output 01500 * - 0011 - High speed comparator 2 output 01501 * - 0100 - PIT trigger 0 01502 * - 0101 - PIT trigger 1 01503 * - 0110 - PIT trigger 2 01504 * - 0111 - PIT trigger 3 01505 * - 1000 - FTM0 trigger 01506 * - 1001 - FTM1 trigger 01507 * - 1010 - FTM2 trigger 01508 * - 1011 - FTM3 trigger 01509 * - 1100 - RTC alarm 01510 * - 1101 - RTC seconds 01511 * - 1110 - Low-power timer (LPTMR) trigger 01512 * - 1111 - Reserved 01513 */ 01514 /*@{*/ 01515 #define BP_SIM_SOPT7_ADC1TRGSEL (8U) /*!< Bit position for SIM_SOPT7_ADC1TRGSEL. */ 01516 #define BM_SIM_SOPT7_ADC1TRGSEL (0x00000F00U) /*!< Bit mask for SIM_SOPT7_ADC1TRGSEL. */ 01517 #define BS_SIM_SOPT7_ADC1TRGSEL (4U) /*!< Bit field size in bits for SIM_SOPT7_ADC1TRGSEL. */ 01518 01519 /*! @brief Read current value of the SIM_SOPT7_ADC1TRGSEL field. */ 01520 #define BR_SIM_SOPT7_ADC1TRGSEL(x) (HW_SIM_SOPT7(x).B.ADC1TRGSEL) 01521 01522 /*! @brief Format value for bitfield SIM_SOPT7_ADC1TRGSEL. */ 01523 #define BF_SIM_SOPT7_ADC1TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1TRGSEL) & BM_SIM_SOPT7_ADC1TRGSEL) 01524 01525 /*! @brief Set the ADC1TRGSEL field to a new value. */ 01526 #define BW_SIM_SOPT7_ADC1TRGSEL(x, v) (HW_SIM_SOPT7_WR(x, (HW_SIM_SOPT7_RD(x) & ~BM_SIM_SOPT7_ADC1TRGSEL) | BF_SIM_SOPT7_ADC1TRGSEL(v))) 01527 /*@}*/ 01528 01529 /*! 01530 * @name Register SIM_SOPT7, field ADC1PRETRGSEL[12] (RW) 01531 * 01532 * Selects the ADC1 pre-trigger source when alternative triggers are enabled 01533 * through ADC1ALTTRGEN. 01534 * 01535 * Values: 01536 * - 0 - Pre-trigger A selected for ADC1. 01537 * - 1 - Pre-trigger B selected for ADC1. 01538 */ 01539 /*@{*/ 01540 #define BP_SIM_SOPT7_ADC1PRETRGSEL (12U) /*!< Bit position for SIM_SOPT7_ADC1PRETRGSEL. */ 01541 #define BM_SIM_SOPT7_ADC1PRETRGSEL (0x00001000U) /*!< Bit mask for SIM_SOPT7_ADC1PRETRGSEL. */ 01542 #define BS_SIM_SOPT7_ADC1PRETRGSEL (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC1PRETRGSEL. */ 01543 01544 /*! @brief Read current value of the SIM_SOPT7_ADC1PRETRGSEL field. */ 01545 #define BR_SIM_SOPT7_ADC1PRETRGSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1PRETRGSEL)) 01546 01547 /*! @brief Format value for bitfield SIM_SOPT7_ADC1PRETRGSEL. */ 01548 #define BF_SIM_SOPT7_ADC1PRETRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1PRETRGSEL) & BM_SIM_SOPT7_ADC1PRETRGSEL) 01549 01550 /*! @brief Set the ADC1PRETRGSEL field to a new value. */ 01551 #define BW_SIM_SOPT7_ADC1PRETRGSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1PRETRGSEL) = (v)) 01552 /*@}*/ 01553 01554 /*! 01555 * @name Register SIM_SOPT7, field ADC1ALTTRGEN[15] (RW) 01556 * 01557 * Enable alternative conversion triggers for ADC1. 01558 * 01559 * Values: 01560 * - 0 - PDB trigger selected for ADC1 01561 * - 1 - Alternate trigger selected for ADC1 as defined by ADC1TRGSEL. 01562 */ 01563 /*@{*/ 01564 #define BP_SIM_SOPT7_ADC1ALTTRGEN (15U) /*!< Bit position for SIM_SOPT7_ADC1ALTTRGEN. */ 01565 #define BM_SIM_SOPT7_ADC1ALTTRGEN (0x00008000U) /*!< Bit mask for SIM_SOPT7_ADC1ALTTRGEN. */ 01566 #define BS_SIM_SOPT7_ADC1ALTTRGEN (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC1ALTTRGEN. */ 01567 01568 /*! @brief Read current value of the SIM_SOPT7_ADC1ALTTRGEN field. */ 01569 #define BR_SIM_SOPT7_ADC1ALTTRGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1ALTTRGEN)) 01570 01571 /*! @brief Format value for bitfield SIM_SOPT7_ADC1ALTTRGEN. */ 01572 #define BF_SIM_SOPT7_ADC1ALTTRGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1ALTTRGEN) & BM_SIM_SOPT7_ADC1ALTTRGEN) 01573 01574 /*! @brief Set the ADC1ALTTRGEN field to a new value. */ 01575 #define BW_SIM_SOPT7_ADC1ALTTRGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1ALTTRGEN) = (v)) 01576 /*@}*/ 01577 01578 /******************************************************************************* 01579 * HW_SIM_SDID - System Device Identification Register 01580 ******************************************************************************/ 01581 01582 /*! 01583 * @brief HW_SIM_SDID - System Device Identification Register (RO) 01584 * 01585 * Reset value: 0x00000380U 01586 */ 01587 typedef union _hw_sim_sdid 01588 { 01589 uint32_t U; 01590 struct _hw_sim_sdid_bitfields 01591 { 01592 uint32_t PINID : 4; /*!< [3:0] Pincount identification */ 01593 uint32_t FAMID : 3; /*!< [6:4] Kinetis family identification */ 01594 uint32_t DIEID : 5; /*!< [11:7] Device Die ID */ 01595 uint32_t REVID : 4; /*!< [15:12] Device revision number */ 01596 uint32_t RESERVED0 : 4; /*!< [19:16] */ 01597 uint32_t SERIESID : 4; /*!< [23:20] Kinetis Series ID */ 01598 uint32_t SUBFAMID : 4; /*!< [27:24] Kinetis Sub-Family ID */ 01599 uint32_t FAMILYID : 4; /*!< [31:28] Kinetis Family ID */ 01600 } B; 01601 } hw_sim_sdid_t; 01602 01603 /*! 01604 * @name Constants and macros for entire SIM_SDID register 01605 */ 01606 /*@{*/ 01607 #define HW_SIM_SDID_ADDR(x) ((x) + 0x1024U) 01608 01609 #define HW_SIM_SDID(x) (*(__I hw_sim_sdid_t *) HW_SIM_SDID_ADDR(x)) 01610 #define HW_SIM_SDID_RD(x) (HW_SIM_SDID(x).U) 01611 /*@}*/ 01612 01613 /* 01614 * Constants & macros for individual SIM_SDID bitfields 01615 */ 01616 01617 /*! 01618 * @name Register SIM_SDID, field PINID[3:0] (RO) 01619 * 01620 * Specifies the pincount of the device. 01621 * 01622 * Values: 01623 * - 0000 - Reserved 01624 * - 0001 - Reserved 01625 * - 0010 - 32-pin 01626 * - 0011 - Reserved 01627 * - 0100 - 48-pin 01628 * - 0101 - 64-pin 01629 * - 0110 - 80-pin 01630 * - 0111 - 81-pin or 121-pin 01631 * - 1000 - 100-pin 01632 * - 1001 - 121-pin 01633 * - 1010 - 144-pin 01634 * - 1011 - Custom pinout (WLCSP) 01635 * - 1100 - 169-pin 01636 * - 1101 - Reserved 01637 * - 1110 - 256-pin 01638 * - 1111 - Reserved 01639 */ 01640 /*@{*/ 01641 #define BP_SIM_SDID_PINID (0U) /*!< Bit position for SIM_SDID_PINID. */ 01642 #define BM_SIM_SDID_PINID (0x0000000FU) /*!< Bit mask for SIM_SDID_PINID. */ 01643 #define BS_SIM_SDID_PINID (4U) /*!< Bit field size in bits for SIM_SDID_PINID. */ 01644 01645 /*! @brief Read current value of the SIM_SDID_PINID field. */ 01646 #define BR_SIM_SDID_PINID(x) (HW_SIM_SDID(x).B.PINID) 01647 /*@}*/ 01648 01649 /*! 01650 * @name Register SIM_SDID, field FAMID[6:4] (RO) 01651 * 01652 * This field is maintained for compatibility only, but has been superceded by 01653 * the SERIESID, FAMILYID and SUBFAMID fields in this register. 01654 * 01655 * Values: 01656 * - 000 - K1x Family (without tamper) 01657 * - 001 - K2x Family (without tamper) 01658 * - 010 - K3x Family or K1x/K6x Family (with tamper) 01659 * - 011 - K4x Family or K2x Family (with tamper) 01660 * - 100 - K6x Family (without tamper) 01661 * - 101 - K7x Family 01662 * - 110 - Reserved 01663 * - 111 - Reserved 01664 */ 01665 /*@{*/ 01666 #define BP_SIM_SDID_FAMID (4U) /*!< Bit position for SIM_SDID_FAMID. */ 01667 #define BM_SIM_SDID_FAMID (0x00000070U) /*!< Bit mask for SIM_SDID_FAMID. */ 01668 #define BS_SIM_SDID_FAMID (3U) /*!< Bit field size in bits for SIM_SDID_FAMID. */ 01669 01670 /*! @brief Read current value of the SIM_SDID_FAMID field. */ 01671 #define BR_SIM_SDID_FAMID(x) (HW_SIM_SDID(x).B.FAMID) 01672 /*@}*/ 01673 01674 /*! 01675 * @name Register SIM_SDID, field DIEID[11:7] (RO) 01676 * 01677 * Specifies the silicon feature set identication number for the device. 01678 */ 01679 /*@{*/ 01680 #define BP_SIM_SDID_DIEID (7U) /*!< Bit position for SIM_SDID_DIEID. */ 01681 #define BM_SIM_SDID_DIEID (0x00000F80U) /*!< Bit mask for SIM_SDID_DIEID. */ 01682 #define BS_SIM_SDID_DIEID (5U) /*!< Bit field size in bits for SIM_SDID_DIEID. */ 01683 01684 /*! @brief Read current value of the SIM_SDID_DIEID field. */ 01685 #define BR_SIM_SDID_DIEID(x) (HW_SIM_SDID(x).B.DIEID) 01686 /*@}*/ 01687 01688 /*! 01689 * @name Register SIM_SDID, field REVID[15:12] (RO) 01690 * 01691 * Specifies the silicon implementation number for the device. 01692 */ 01693 /*@{*/ 01694 #define BP_SIM_SDID_REVID (12U) /*!< Bit position for SIM_SDID_REVID. */ 01695 #define BM_SIM_SDID_REVID (0x0000F000U) /*!< Bit mask for SIM_SDID_REVID. */ 01696 #define BS_SIM_SDID_REVID (4U) /*!< Bit field size in bits for SIM_SDID_REVID. */ 01697 01698 /*! @brief Read current value of the SIM_SDID_REVID field. */ 01699 #define BR_SIM_SDID_REVID(x) (HW_SIM_SDID(x).B.REVID) 01700 /*@}*/ 01701 01702 /*! 01703 * @name Register SIM_SDID, field SERIESID[23:20] (RO) 01704 * 01705 * Specifies the Kinetis series of the device. 01706 * 01707 * Values: 01708 * - 0000 - Kinetis K series 01709 * - 0001 - Kinetis L series 01710 * - 0101 - Kinetis W series 01711 * - 0110 - Kinetis V series 01712 */ 01713 /*@{*/ 01714 #define BP_SIM_SDID_SERIESID (20U) /*!< Bit position for SIM_SDID_SERIESID. */ 01715 #define BM_SIM_SDID_SERIESID (0x00F00000U) /*!< Bit mask for SIM_SDID_SERIESID. */ 01716 #define BS_SIM_SDID_SERIESID (4U) /*!< Bit field size in bits for SIM_SDID_SERIESID. */ 01717 01718 /*! @brief Read current value of the SIM_SDID_SERIESID field. */ 01719 #define BR_SIM_SDID_SERIESID(x) (HW_SIM_SDID(x).B.SERIESID) 01720 /*@}*/ 01721 01722 /*! 01723 * @name Register SIM_SDID, field SUBFAMID[27:24] (RO) 01724 * 01725 * Specifies the Kinetis sub-family of the device. 01726 * 01727 * Values: 01728 * - 0000 - Kx0 Subfamily 01729 * - 0001 - Kx1 Subfamily (tamper detect) 01730 * - 0010 - Kx2 Subfamily 01731 * - 0011 - Kx3 Subfamily (tamper detect) 01732 * - 0100 - Kx4 Subfamily 01733 * - 0101 - Kx5 Subfamily (tamper detect) 01734 * - 0110 - Kx6 Subfamily 01735 */ 01736 /*@{*/ 01737 #define BP_SIM_SDID_SUBFAMID (24U) /*!< Bit position for SIM_SDID_SUBFAMID. */ 01738 #define BM_SIM_SDID_SUBFAMID (0x0F000000U) /*!< Bit mask for SIM_SDID_SUBFAMID. */ 01739 #define BS_SIM_SDID_SUBFAMID (4U) /*!< Bit field size in bits for SIM_SDID_SUBFAMID. */ 01740 01741 /*! @brief Read current value of the SIM_SDID_SUBFAMID field. */ 01742 #define BR_SIM_SDID_SUBFAMID(x) (HW_SIM_SDID(x).B.SUBFAMID) 01743 /*@}*/ 01744 01745 /*! 01746 * @name Register SIM_SDID, field FAMILYID[31:28] (RO) 01747 * 01748 * Specifies the Kinetis family of the device. 01749 * 01750 * Values: 01751 * - 0001 - K1x Family 01752 * - 0010 - K2x Family 01753 * - 0011 - K3x Family 01754 * - 0100 - K4x Family 01755 * - 0110 - K6x Family 01756 * - 0111 - K7x Family 01757 */ 01758 /*@{*/ 01759 #define BP_SIM_SDID_FAMILYID (28U) /*!< Bit position for SIM_SDID_FAMILYID. */ 01760 #define BM_SIM_SDID_FAMILYID (0xF0000000U) /*!< Bit mask for SIM_SDID_FAMILYID. */ 01761 #define BS_SIM_SDID_FAMILYID (4U) /*!< Bit field size in bits for SIM_SDID_FAMILYID. */ 01762 01763 /*! @brief Read current value of the SIM_SDID_FAMILYID field. */ 01764 #define BR_SIM_SDID_FAMILYID(x) (HW_SIM_SDID(x).B.FAMILYID) 01765 /*@}*/ 01766 01767 /******************************************************************************* 01768 * HW_SIM_SCGC1 - System Clock Gating Control Register 1 01769 ******************************************************************************/ 01770 01771 /*! 01772 * @brief HW_SIM_SCGC1 - System Clock Gating Control Register 1 (RW) 01773 * 01774 * Reset value: 0x00000000U 01775 */ 01776 typedef union _hw_sim_scgc1 01777 { 01778 uint32_t U; 01779 struct _hw_sim_scgc1_bitfields 01780 { 01781 uint32_t RESERVED0 : 6; /*!< [5:0] */ 01782 uint32_t I2C2b : 1; /*!< [6] I2C2 Clock Gate Control */ 01783 uint32_t RESERVED1 : 3; /*!< [9:7] */ 01784 uint32_t UART4b : 1; /*!< [10] UART4 Clock Gate Control */ 01785 uint32_t UART5b : 1; /*!< [11] UART5 Clock Gate Control */ 01786 uint32_t RESERVED2 : 20; /*!< [31:12] */ 01787 } B; 01788 } hw_sim_scgc1_t; 01789 01790 /*! 01791 * @name Constants and macros for entire SIM_SCGC1 register 01792 */ 01793 /*@{*/ 01794 #define HW_SIM_SCGC1_ADDR(x) ((x) + 0x1028U) 01795 01796 #define HW_SIM_SCGC1(x) (*(__IO hw_sim_scgc1_t *) HW_SIM_SCGC1_ADDR(x)) 01797 #define HW_SIM_SCGC1_RD(x) (HW_SIM_SCGC1(x).U) 01798 #define HW_SIM_SCGC1_WR(x, v) (HW_SIM_SCGC1(x).U = (v)) 01799 #define HW_SIM_SCGC1_SET(x, v) (HW_SIM_SCGC1_WR(x, HW_SIM_SCGC1_RD(x) | (v))) 01800 #define HW_SIM_SCGC1_CLR(x, v) (HW_SIM_SCGC1_WR(x, HW_SIM_SCGC1_RD(x) & ~(v))) 01801 #define HW_SIM_SCGC1_TOG(x, v) (HW_SIM_SCGC1_WR(x, HW_SIM_SCGC1_RD(x) ^ (v))) 01802 /*@}*/ 01803 01804 /* 01805 * Constants & macros for individual SIM_SCGC1 bitfields 01806 */ 01807 01808 /*! 01809 * @name Register SIM_SCGC1, field I2C2[6] (RW) 01810 * 01811 * This bit controls the clock gate to the I2C2 module. 01812 * 01813 * Values: 01814 * - 0 - Clock disabled 01815 * - 1 - Clock enabled 01816 */ 01817 /*@{*/ 01818 #define BP_SIM_SCGC1_I2C2 (6U) /*!< Bit position for SIM_SCGC1_I2C2. */ 01819 #define BM_SIM_SCGC1_I2C2 (0x00000040U) /*!< Bit mask for SIM_SCGC1_I2C2. */ 01820 #define BS_SIM_SCGC1_I2C2 (1U) /*!< Bit field size in bits for SIM_SCGC1_I2C2. */ 01821 01822 /*! @brief Read current value of the SIM_SCGC1_I2C2 field. */ 01823 #define BR_SIM_SCGC1_I2C2(x) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_I2C2)) 01824 01825 /*! @brief Format value for bitfield SIM_SCGC1_I2C2. */ 01826 #define BF_SIM_SCGC1_I2C2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC1_I2C2) & BM_SIM_SCGC1_I2C2) 01827 01828 /*! @brief Set the I2C2 field to a new value. */ 01829 #define BW_SIM_SCGC1_I2C2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_I2C2) = (v)) 01830 /*@}*/ 01831 01832 /*! 01833 * @name Register SIM_SCGC1, field UART4[10] (RW) 01834 * 01835 * This bit controls the clock gate to the UART4 module. 01836 * 01837 * Values: 01838 * - 0 - Clock disabled 01839 * - 1 - Clock enabled 01840 */ 01841 /*@{*/ 01842 #define BP_SIM_SCGC1_UART4 (10U) /*!< Bit position for SIM_SCGC1_UART4. */ 01843 #define BM_SIM_SCGC1_UART4 (0x00000400U) /*!< Bit mask for SIM_SCGC1_UART4. */ 01844 #define BS_SIM_SCGC1_UART4 (1U) /*!< Bit field size in bits for SIM_SCGC1_UART4. */ 01845 01846 /*! @brief Read current value of the SIM_SCGC1_UART4 field. */ 01847 #define BR_SIM_SCGC1_UART4(x) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART4)) 01848 01849 /*! @brief Format value for bitfield SIM_SCGC1_UART4. */ 01850 #define BF_SIM_SCGC1_UART4(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC1_UART4) & BM_SIM_SCGC1_UART4) 01851 01852 /*! @brief Set the UART4 field to a new value. */ 01853 #define BW_SIM_SCGC1_UART4(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART4) = (v)) 01854 /*@}*/ 01855 01856 /*! 01857 * @name Register SIM_SCGC1, field UART5[11] (RW) 01858 * 01859 * This bit controls the clock gate to the UART5 module. 01860 * 01861 * Values: 01862 * - 0 - Clock disabled 01863 * - 1 - Clock enabled 01864 */ 01865 /*@{*/ 01866 #define BP_SIM_SCGC1_UART5 (11U) /*!< Bit position for SIM_SCGC1_UART5. */ 01867 #define BM_SIM_SCGC1_UART5 (0x00000800U) /*!< Bit mask for SIM_SCGC1_UART5. */ 01868 #define BS_SIM_SCGC1_UART5 (1U) /*!< Bit field size in bits for SIM_SCGC1_UART5. */ 01869 01870 /*! @brief Read current value of the SIM_SCGC1_UART5 field. */ 01871 #define BR_SIM_SCGC1_UART5(x) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART5)) 01872 01873 /*! @brief Format value for bitfield SIM_SCGC1_UART5. */ 01874 #define BF_SIM_SCGC1_UART5(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC1_UART5) & BM_SIM_SCGC1_UART5) 01875 01876 /*! @brief Set the UART5 field to a new value. */ 01877 #define BW_SIM_SCGC1_UART5(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART5) = (v)) 01878 /*@}*/ 01879 01880 /******************************************************************************* 01881 * HW_SIM_SCGC2 - System Clock Gating Control Register 2 01882 ******************************************************************************/ 01883 01884 /*! 01885 * @brief HW_SIM_SCGC2 - System Clock Gating Control Register 2 (RW) 01886 * 01887 * Reset value: 0x00000000U 01888 * 01889 * DAC0 can be accessed through both AIPS0 and AIPS1. When accessing through 01890 * AIPS1, define the clock gate control bits in the SCGC2. When accessing through 01891 * AIPS0, define the clock gate control bits in SCGC6. 01892 */ 01893 typedef union _hw_sim_scgc2 01894 { 01895 uint32_t U; 01896 struct _hw_sim_scgc2_bitfields 01897 { 01898 uint32_t ENETb : 1; /*!< [0] ENET Clock Gate Control */ 01899 uint32_t RESERVED0 : 11; /*!< [11:1] */ 01900 uint32_t DAC0b : 1; /*!< [12] DAC0 Clock Gate Control */ 01901 uint32_t DAC1b : 1; /*!< [13] DAC1 Clock Gate Control */ 01902 uint32_t RESERVED1 : 18; /*!< [31:14] */ 01903 } B; 01904 } hw_sim_scgc2_t; 01905 01906 /*! 01907 * @name Constants and macros for entire SIM_SCGC2 register 01908 */ 01909 /*@{*/ 01910 #define HW_SIM_SCGC2_ADDR(x) ((x) + 0x102CU) 01911 01912 #define HW_SIM_SCGC2(x) (*(__IO hw_sim_scgc2_t *) HW_SIM_SCGC2_ADDR(x)) 01913 #define HW_SIM_SCGC2_RD(x) (HW_SIM_SCGC2(x).U) 01914 #define HW_SIM_SCGC2_WR(x, v) (HW_SIM_SCGC2(x).U = (v)) 01915 #define HW_SIM_SCGC2_SET(x, v) (HW_SIM_SCGC2_WR(x, HW_SIM_SCGC2_RD(x) | (v))) 01916 #define HW_SIM_SCGC2_CLR(x, v) (HW_SIM_SCGC2_WR(x, HW_SIM_SCGC2_RD(x) & ~(v))) 01917 #define HW_SIM_SCGC2_TOG(x, v) (HW_SIM_SCGC2_WR(x, HW_SIM_SCGC2_RD(x) ^ (v))) 01918 /*@}*/ 01919 01920 /* 01921 * Constants & macros for individual SIM_SCGC2 bitfields 01922 */ 01923 01924 /*! 01925 * @name Register SIM_SCGC2, field ENET[0] (RW) 01926 * 01927 * This bit controls the clock gate to the ENET module. 01928 * 01929 * Values: 01930 * - 0 - Clock disabled 01931 * - 1 - Clock enabled 01932 */ 01933 /*@{*/ 01934 #define BP_SIM_SCGC2_ENET (0U) /*!< Bit position for SIM_SCGC2_ENET. */ 01935 #define BM_SIM_SCGC2_ENET (0x00000001U) /*!< Bit mask for SIM_SCGC2_ENET. */ 01936 #define BS_SIM_SCGC2_ENET (1U) /*!< Bit field size in bits for SIM_SCGC2_ENET. */ 01937 01938 /*! @brief Read current value of the SIM_SCGC2_ENET field. */ 01939 #define BR_SIM_SCGC2_ENET(x) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_ENET)) 01940 01941 /*! @brief Format value for bitfield SIM_SCGC2_ENET. */ 01942 #define BF_SIM_SCGC2_ENET(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC2_ENET) & BM_SIM_SCGC2_ENET) 01943 01944 /*! @brief Set the ENET field to a new value. */ 01945 #define BW_SIM_SCGC2_ENET(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_ENET) = (v)) 01946 /*@}*/ 01947 01948 /*! 01949 * @name Register SIM_SCGC2, field DAC0[12] (RW) 01950 * 01951 * This bit controls the clock gate to the DAC0 module. 01952 * 01953 * Values: 01954 * - 0 - Clock disabled 01955 * - 1 - Clock enabled 01956 */ 01957 /*@{*/ 01958 #define BP_SIM_SCGC2_DAC0 (12U) /*!< Bit position for SIM_SCGC2_DAC0. */ 01959 #define BM_SIM_SCGC2_DAC0 (0x00001000U) /*!< Bit mask for SIM_SCGC2_DAC0. */ 01960 #define BS_SIM_SCGC2_DAC0 (1U) /*!< Bit field size in bits for SIM_SCGC2_DAC0. */ 01961 01962 /*! @brief Read current value of the SIM_SCGC2_DAC0 field. */ 01963 #define BR_SIM_SCGC2_DAC0(x) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC0)) 01964 01965 /*! @brief Format value for bitfield SIM_SCGC2_DAC0. */ 01966 #define BF_SIM_SCGC2_DAC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC2_DAC0) & BM_SIM_SCGC2_DAC0) 01967 01968 /*! @brief Set the DAC0 field to a new value. */ 01969 #define BW_SIM_SCGC2_DAC0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC0) = (v)) 01970 /*@}*/ 01971 01972 /*! 01973 * @name Register SIM_SCGC2, field DAC1[13] (RW) 01974 * 01975 * This bit controls the clock gate to the DAC1 module. 01976 * 01977 * Values: 01978 * - 0 - Clock disabled 01979 * - 1 - Clock enabled 01980 */ 01981 /*@{*/ 01982 #define BP_SIM_SCGC2_DAC1 (13U) /*!< Bit position for SIM_SCGC2_DAC1. */ 01983 #define BM_SIM_SCGC2_DAC1 (0x00002000U) /*!< Bit mask for SIM_SCGC2_DAC1. */ 01984 #define BS_SIM_SCGC2_DAC1 (1U) /*!< Bit field size in bits for SIM_SCGC2_DAC1. */ 01985 01986 /*! @brief Read current value of the SIM_SCGC2_DAC1 field. */ 01987 #define BR_SIM_SCGC2_DAC1(x) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC1)) 01988 01989 /*! @brief Format value for bitfield SIM_SCGC2_DAC1. */ 01990 #define BF_SIM_SCGC2_DAC1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC2_DAC1) & BM_SIM_SCGC2_DAC1) 01991 01992 /*! @brief Set the DAC1 field to a new value. */ 01993 #define BW_SIM_SCGC2_DAC1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC1) = (v)) 01994 /*@}*/ 01995 01996 /******************************************************************************* 01997 * HW_SIM_SCGC3 - System Clock Gating Control Register 3 01998 ******************************************************************************/ 01999 02000 /*! 02001 * @brief HW_SIM_SCGC3 - System Clock Gating Control Register 3 (RW) 02002 * 02003 * Reset value: 0x00000000U 02004 * 02005 * FTM2 and RNGA can be accessed through both AIPS0 and AIPS1. When accessing 02006 * through AIPS1, define the clock gate control bits in the SCGC3. When accessing 02007 * through AIPS0, define the clock gate control bits in SCGC6. 02008 */ 02009 typedef union _hw_sim_scgc3 02010 { 02011 uint32_t U; 02012 struct _hw_sim_scgc3_bitfields 02013 { 02014 uint32_t RNGA : 1; /*!< [0] RNGA Clock Gate Control */ 02015 uint32_t RESERVED0 : 11; /*!< [11:1] */ 02016 uint32_t SPI2b : 1; /*!< [12] SPI2 Clock Gate Control */ 02017 uint32_t RESERVED1 : 4; /*!< [16:13] */ 02018 uint32_t SDHCb : 1; /*!< [17] SDHC Clock Gate Control */ 02019 uint32_t RESERVED2 : 6; /*!< [23:18] */ 02020 uint32_t FTM2b : 1; /*!< [24] FTM2 Clock Gate Control */ 02021 uint32_t FTM3b : 1; /*!< [25] FTM3 Clock Gate Control */ 02022 uint32_t RESERVED3 : 1; /*!< [26] */ 02023 uint32_t ADC1b : 1; /*!< [27] ADC1 Clock Gate Control */ 02024 uint32_t RESERVED4 : 4; /*!< [31:28] */ 02025 } B; 02026 } hw_sim_scgc3_t; 02027 02028 /*! 02029 * @name Constants and macros for entire SIM_SCGC3 register 02030 */ 02031 /*@{*/ 02032 #define HW_SIM_SCGC3_ADDR(x) ((x) + 0x1030U) 02033 02034 #define HW_SIM_SCGC3(x) (*(__IO hw_sim_scgc3_t *) HW_SIM_SCGC3_ADDR(x)) 02035 #define HW_SIM_SCGC3_RD(x) (HW_SIM_SCGC3(x).U) 02036 #define HW_SIM_SCGC3_WR(x, v) (HW_SIM_SCGC3(x).U = (v)) 02037 #define HW_SIM_SCGC3_SET(x, v) (HW_SIM_SCGC3_WR(x, HW_SIM_SCGC3_RD(x) | (v))) 02038 #define HW_SIM_SCGC3_CLR(x, v) (HW_SIM_SCGC3_WR(x, HW_SIM_SCGC3_RD(x) & ~(v))) 02039 #define HW_SIM_SCGC3_TOG(x, v) (HW_SIM_SCGC3_WR(x, HW_SIM_SCGC3_RD(x) ^ (v))) 02040 /*@}*/ 02041 02042 /* 02043 * Constants & macros for individual SIM_SCGC3 bitfields 02044 */ 02045 02046 /*! 02047 * @name Register SIM_SCGC3, field RNGA[0] (RW) 02048 * 02049 * This bit controls the clock gate to the RNGA module. 02050 * 02051 * Values: 02052 * - 0 - Clock disabled 02053 * - 1 - Clock enabled 02054 */ 02055 /*@{*/ 02056 #define BP_SIM_SCGC3_RNGA (0U) /*!< Bit position for SIM_SCGC3_RNGA. */ 02057 #define BM_SIM_SCGC3_RNGA (0x00000001U) /*!< Bit mask for SIM_SCGC3_RNGA. */ 02058 #define BS_SIM_SCGC3_RNGA (1U) /*!< Bit field size in bits for SIM_SCGC3_RNGA. */ 02059 02060 /*! @brief Read current value of the SIM_SCGC3_RNGA field. */ 02061 #define BR_SIM_SCGC3_RNGA(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_RNGA)) 02062 02063 /*! @brief Format value for bitfield SIM_SCGC3_RNGA. */ 02064 #define BF_SIM_SCGC3_RNGA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_RNGA) & BM_SIM_SCGC3_RNGA) 02065 02066 /*! @brief Set the RNGA field to a new value. */ 02067 #define BW_SIM_SCGC3_RNGA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_RNGA) = (v)) 02068 /*@}*/ 02069 02070 /*! 02071 * @name Register SIM_SCGC3, field SPI2[12] (RW) 02072 * 02073 * This bit controls the clock gate to the SPI2 module. 02074 * 02075 * Values: 02076 * - 0 - Clock disabled 02077 * - 1 - Clock enabled 02078 */ 02079 /*@{*/ 02080 #define BP_SIM_SCGC3_SPI2 (12U) /*!< Bit position for SIM_SCGC3_SPI2. */ 02081 #define BM_SIM_SCGC3_SPI2 (0x00001000U) /*!< Bit mask for SIM_SCGC3_SPI2. */ 02082 #define BS_SIM_SCGC3_SPI2 (1U) /*!< Bit field size in bits for SIM_SCGC3_SPI2. */ 02083 02084 /*! @brief Read current value of the SIM_SCGC3_SPI2 field. */ 02085 #define BR_SIM_SCGC3_SPI2(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SPI2)) 02086 02087 /*! @brief Format value for bitfield SIM_SCGC3_SPI2. */ 02088 #define BF_SIM_SCGC3_SPI2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_SPI2) & BM_SIM_SCGC3_SPI2) 02089 02090 /*! @brief Set the SPI2 field to a new value. */ 02091 #define BW_SIM_SCGC3_SPI2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SPI2) = (v)) 02092 /*@}*/ 02093 02094 /*! 02095 * @name Register SIM_SCGC3, field SDHC[17] (RW) 02096 * 02097 * This bit controls the clock gate to the SDHC module. 02098 * 02099 * Values: 02100 * - 0 - Clock disabled 02101 * - 1 - Clock enabled 02102 */ 02103 /*@{*/ 02104 #define BP_SIM_SCGC3_SDHC (17U) /*!< Bit position for SIM_SCGC3_SDHC. */ 02105 #define BM_SIM_SCGC3_SDHC (0x00020000U) /*!< Bit mask for SIM_SCGC3_SDHC. */ 02106 #define BS_SIM_SCGC3_SDHC (1U) /*!< Bit field size in bits for SIM_SCGC3_SDHC. */ 02107 02108 /*! @brief Read current value of the SIM_SCGC3_SDHC field. */ 02109 #define BR_SIM_SCGC3_SDHC(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SDHC)) 02110 02111 /*! @brief Format value for bitfield SIM_SCGC3_SDHC. */ 02112 #define BF_SIM_SCGC3_SDHC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_SDHC) & BM_SIM_SCGC3_SDHC) 02113 02114 /*! @brief Set the SDHC field to a new value. */ 02115 #define BW_SIM_SCGC3_SDHC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SDHC) = (v)) 02116 /*@}*/ 02117 02118 /*! 02119 * @name Register SIM_SCGC3, field FTM2[24] (RW) 02120 * 02121 * This bit controls the clock gate to the FTM2 module. 02122 * 02123 * Values: 02124 * - 0 - Clock disabled 02125 * - 1 - Clock enabled 02126 */ 02127 /*@{*/ 02128 #define BP_SIM_SCGC3_FTM2 (24U) /*!< Bit position for SIM_SCGC3_FTM2. */ 02129 #define BM_SIM_SCGC3_FTM2 (0x01000000U) /*!< Bit mask for SIM_SCGC3_FTM2. */ 02130 #define BS_SIM_SCGC3_FTM2 (1U) /*!< Bit field size in bits for SIM_SCGC3_FTM2. */ 02131 02132 /*! @brief Read current value of the SIM_SCGC3_FTM2 field. */ 02133 #define BR_SIM_SCGC3_FTM2(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM2)) 02134 02135 /*! @brief Format value for bitfield SIM_SCGC3_FTM2. */ 02136 #define BF_SIM_SCGC3_FTM2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_FTM2) & BM_SIM_SCGC3_FTM2) 02137 02138 /*! @brief Set the FTM2 field to a new value. */ 02139 #define BW_SIM_SCGC3_FTM2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM2) = (v)) 02140 /*@}*/ 02141 02142 /*! 02143 * @name Register SIM_SCGC3, field FTM3[25] (RW) 02144 * 02145 * This bit controls the clock gate to the FTM3 module. 02146 * 02147 * Values: 02148 * - 0 - Clock disabled 02149 * - 1 - Clock enabled 02150 */ 02151 /*@{*/ 02152 #define BP_SIM_SCGC3_FTM3 (25U) /*!< Bit position for SIM_SCGC3_FTM3. */ 02153 #define BM_SIM_SCGC3_FTM3 (0x02000000U) /*!< Bit mask for SIM_SCGC3_FTM3. */ 02154 #define BS_SIM_SCGC3_FTM3 (1U) /*!< Bit field size in bits for SIM_SCGC3_FTM3. */ 02155 02156 /*! @brief Read current value of the SIM_SCGC3_FTM3 field. */ 02157 #define BR_SIM_SCGC3_FTM3(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM3)) 02158 02159 /*! @brief Format value for bitfield SIM_SCGC3_FTM3. */ 02160 #define BF_SIM_SCGC3_FTM3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_FTM3) & BM_SIM_SCGC3_FTM3) 02161 02162 /*! @brief Set the FTM3 field to a new value. */ 02163 #define BW_SIM_SCGC3_FTM3(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM3) = (v)) 02164 /*@}*/ 02165 02166 /*! 02167 * @name Register SIM_SCGC3, field ADC1[27] (RW) 02168 * 02169 * This bit controls the clock gate to the ADC1 module. 02170 * 02171 * Values: 02172 * - 0 - Clock disabled 02173 * - 1 - Clock enabled 02174 */ 02175 /*@{*/ 02176 #define BP_SIM_SCGC3_ADC1 (27U) /*!< Bit position for SIM_SCGC3_ADC1. */ 02177 #define BM_SIM_SCGC3_ADC1 (0x08000000U) /*!< Bit mask for SIM_SCGC3_ADC1. */ 02178 #define BS_SIM_SCGC3_ADC1 (1U) /*!< Bit field size in bits for SIM_SCGC3_ADC1. */ 02179 02180 /*! @brief Read current value of the SIM_SCGC3_ADC1 field. */ 02181 #define BR_SIM_SCGC3_ADC1(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_ADC1)) 02182 02183 /*! @brief Format value for bitfield SIM_SCGC3_ADC1. */ 02184 #define BF_SIM_SCGC3_ADC1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_ADC1) & BM_SIM_SCGC3_ADC1) 02185 02186 /*! @brief Set the ADC1 field to a new value. */ 02187 #define BW_SIM_SCGC3_ADC1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_ADC1) = (v)) 02188 /*@}*/ 02189 02190 /******************************************************************************* 02191 * HW_SIM_SCGC4 - System Clock Gating Control Register 4 02192 ******************************************************************************/ 02193 02194 /*! 02195 * @brief HW_SIM_SCGC4 - System Clock Gating Control Register 4 (RW) 02196 * 02197 * Reset value: 0xF0100030U 02198 */ 02199 typedef union _hw_sim_scgc4 02200 { 02201 uint32_t U; 02202 struct _hw_sim_scgc4_bitfields 02203 { 02204 uint32_t RESERVED0 : 1; /*!< [0] */ 02205 uint32_t EWMb : 1; /*!< [1] EWM Clock Gate Control */ 02206 uint32_t CMTb : 1; /*!< [2] CMT Clock Gate Control */ 02207 uint32_t RESERVED1 : 3; /*!< [5:3] */ 02208 uint32_t I2C0b : 1; /*!< [6] I2C0 Clock Gate Control */ 02209 uint32_t I2C1b : 1; /*!< [7] I2C1 Clock Gate Control */ 02210 uint32_t RESERVED2 : 2; /*!< [9:8] */ 02211 uint32_t UART0b : 1; /*!< [10] UART0 Clock Gate Control */ 02212 uint32_t UART1b : 1; /*!< [11] UART1 Clock Gate Control */ 02213 uint32_t UART2b : 1; /*!< [12] UART2 Clock Gate Control */ 02214 uint32_t UART3b : 1; /*!< [13] UART3 Clock Gate Control */ 02215 uint32_t RESERVED3 : 4; /*!< [17:14] */ 02216 uint32_t USBOTG : 1; /*!< [18] USB Clock Gate Control */ 02217 uint32_t CMP : 1; /*!< [19] Comparator Clock Gate Control */ 02218 uint32_t VREFb : 1; /*!< [20] VREF Clock Gate Control */ 02219 uint32_t RESERVED4 : 11; /*!< [31:21] */ 02220 } B; 02221 } hw_sim_scgc4_t; 02222 02223 /*! 02224 * @name Constants and macros for entire SIM_SCGC4 register 02225 */ 02226 /*@{*/ 02227 #define HW_SIM_SCGC4_ADDR(x) ((x) + 0x1034U) 02228 02229 #define HW_SIM_SCGC4(x) (*(__IO hw_sim_scgc4_t *) HW_SIM_SCGC4_ADDR(x)) 02230 #define HW_SIM_SCGC4_RD(x) (HW_SIM_SCGC4(x).U) 02231 #define HW_SIM_SCGC4_WR(x, v) (HW_SIM_SCGC4(x).U = (v)) 02232 #define HW_SIM_SCGC4_SET(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) | (v))) 02233 #define HW_SIM_SCGC4_CLR(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) & ~(v))) 02234 #define HW_SIM_SCGC4_TOG(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) ^ (v))) 02235 /*@}*/ 02236 02237 /* 02238 * Constants & macros for individual SIM_SCGC4 bitfields 02239 */ 02240 02241 /*! 02242 * @name Register SIM_SCGC4, field EWM[1] (RW) 02243 * 02244 * This bit controls the clock gate to the EWM module. 02245 * 02246 * Values: 02247 * - 0 - Clock disabled 02248 * - 1 - Clock enabled 02249 */ 02250 /*@{*/ 02251 #define BP_SIM_SCGC4_EWM (1U) /*!< Bit position for SIM_SCGC4_EWM. */ 02252 #define BM_SIM_SCGC4_EWM (0x00000002U) /*!< Bit mask for SIM_SCGC4_EWM. */ 02253 #define BS_SIM_SCGC4_EWM (1U) /*!< Bit field size in bits for SIM_SCGC4_EWM. */ 02254 02255 /*! @brief Read current value of the SIM_SCGC4_EWM field. */ 02256 #define BR_SIM_SCGC4_EWM(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_EWM)) 02257 02258 /*! @brief Format value for bitfield SIM_SCGC4_EWM. */ 02259 #define BF_SIM_SCGC4_EWM(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_EWM) & BM_SIM_SCGC4_EWM) 02260 02261 /*! @brief Set the EWM field to a new value. */ 02262 #define BW_SIM_SCGC4_EWM(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_EWM) = (v)) 02263 /*@}*/ 02264 02265 /*! 02266 * @name Register SIM_SCGC4, field CMT[2] (RW) 02267 * 02268 * This bit controls the clock gate to the CMT module. 02269 * 02270 * Values: 02271 * - 0 - Clock disabled 02272 * - 1 - Clock enabled 02273 */ 02274 /*@{*/ 02275 #define BP_SIM_SCGC4_CMT (2U) /*!< Bit position for SIM_SCGC4_CMT. */ 02276 #define BM_SIM_SCGC4_CMT (0x00000004U) /*!< Bit mask for SIM_SCGC4_CMT. */ 02277 #define BS_SIM_SCGC4_CMT (1U) /*!< Bit field size in bits for SIM_SCGC4_CMT. */ 02278 02279 /*! @brief Read current value of the SIM_SCGC4_CMT field. */ 02280 #define BR_SIM_SCGC4_CMT(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMT)) 02281 02282 /*! @brief Format value for bitfield SIM_SCGC4_CMT. */ 02283 #define BF_SIM_SCGC4_CMT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_CMT) & BM_SIM_SCGC4_CMT) 02284 02285 /*! @brief Set the CMT field to a new value. */ 02286 #define BW_SIM_SCGC4_CMT(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMT) = (v)) 02287 /*@}*/ 02288 02289 /*! 02290 * @name Register SIM_SCGC4, field I2C0[6] (RW) 02291 * 02292 * This bit controls the clock gate to the I 2 C0 module. 02293 * 02294 * Values: 02295 * - 0 - Clock disabled 02296 * - 1 - Clock enabled 02297 */ 02298 /*@{*/ 02299 #define BP_SIM_SCGC4_I2C0 (6U) /*!< Bit position for SIM_SCGC4_I2C0. */ 02300 #define BM_SIM_SCGC4_I2C0 (0x00000040U) /*!< Bit mask for SIM_SCGC4_I2C0. */ 02301 #define BS_SIM_SCGC4_I2C0 (1U) /*!< Bit field size in bits for SIM_SCGC4_I2C0. */ 02302 02303 /*! @brief Read current value of the SIM_SCGC4_I2C0 field. */ 02304 #define BR_SIM_SCGC4_I2C0(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C0)) 02305 02306 /*! @brief Format value for bitfield SIM_SCGC4_I2C0. */ 02307 #define BF_SIM_SCGC4_I2C0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_I2C0) & BM_SIM_SCGC4_I2C0) 02308 02309 /*! @brief Set the I2C0 field to a new value. */ 02310 #define BW_SIM_SCGC4_I2C0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C0) = (v)) 02311 /*@}*/ 02312 02313 /*! 02314 * @name Register SIM_SCGC4, field I2C1[7] (RW) 02315 * 02316 * This bit controls the clock gate to the I 2 C1 module. 02317 * 02318 * Values: 02319 * - 0 - Clock disabled 02320 * - 1 - Clock enabled 02321 */ 02322 /*@{*/ 02323 #define BP_SIM_SCGC4_I2C1 (7U) /*!< Bit position for SIM_SCGC4_I2C1. */ 02324 #define BM_SIM_SCGC4_I2C1 (0x00000080U) /*!< Bit mask for SIM_SCGC4_I2C1. */ 02325 #define BS_SIM_SCGC4_I2C1 (1U) /*!< Bit field size in bits for SIM_SCGC4_I2C1. */ 02326 02327 /*! @brief Read current value of the SIM_SCGC4_I2C1 field. */ 02328 #define BR_SIM_SCGC4_I2C1(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C1)) 02329 02330 /*! @brief Format value for bitfield SIM_SCGC4_I2C1. */ 02331 #define BF_SIM_SCGC4_I2C1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_I2C1) & BM_SIM_SCGC4_I2C1) 02332 02333 /*! @brief Set the I2C1 field to a new value. */ 02334 #define BW_SIM_SCGC4_I2C1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C1) = (v)) 02335 /*@}*/ 02336 02337 /*! 02338 * @name Register SIM_SCGC4, field UART0[10] (RW) 02339 * 02340 * This bit controls the clock gate to the UART0 module. 02341 * 02342 * Values: 02343 * - 0 - Clock disabled 02344 * - 1 - Clock enabled 02345 */ 02346 /*@{*/ 02347 #define BP_SIM_SCGC4_UART0 (10U) /*!< Bit position for SIM_SCGC4_UART0. */ 02348 #define BM_SIM_SCGC4_UART0 (0x00000400U) /*!< Bit mask for SIM_SCGC4_UART0. */ 02349 #define BS_SIM_SCGC4_UART0 (1U) /*!< Bit field size in bits for SIM_SCGC4_UART0. */ 02350 02351 /*! @brief Read current value of the SIM_SCGC4_UART0 field. */ 02352 #define BR_SIM_SCGC4_UART0(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART0)) 02353 02354 /*! @brief Format value for bitfield SIM_SCGC4_UART0. */ 02355 #define BF_SIM_SCGC4_UART0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART0) & BM_SIM_SCGC4_UART0) 02356 02357 /*! @brief Set the UART0 field to a new value. */ 02358 #define BW_SIM_SCGC4_UART0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART0) = (v)) 02359 /*@}*/ 02360 02361 /*! 02362 * @name Register SIM_SCGC4, field UART1[11] (RW) 02363 * 02364 * This bit controls the clock gate to the UART1 module. 02365 * 02366 * Values: 02367 * - 0 - Clock disabled 02368 * - 1 - Clock enabled 02369 */ 02370 /*@{*/ 02371 #define BP_SIM_SCGC4_UART1 (11U) /*!< Bit position for SIM_SCGC4_UART1. */ 02372 #define BM_SIM_SCGC4_UART1 (0x00000800U) /*!< Bit mask for SIM_SCGC4_UART1. */ 02373 #define BS_SIM_SCGC4_UART1 (1U) /*!< Bit field size in bits for SIM_SCGC4_UART1. */ 02374 02375 /*! @brief Read current value of the SIM_SCGC4_UART1 field. */ 02376 #define BR_SIM_SCGC4_UART1(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART1)) 02377 02378 /*! @brief Format value for bitfield SIM_SCGC4_UART1. */ 02379 #define BF_SIM_SCGC4_UART1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART1) & BM_SIM_SCGC4_UART1) 02380 02381 /*! @brief Set the UART1 field to a new value. */ 02382 #define BW_SIM_SCGC4_UART1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART1) = (v)) 02383 /*@}*/ 02384 02385 /*! 02386 * @name Register SIM_SCGC4, field UART2[12] (RW) 02387 * 02388 * This bit controls the clock gate to the UART2 module. 02389 * 02390 * Values: 02391 * - 0 - Clock disabled 02392 * - 1 - Clock enabled 02393 */ 02394 /*@{*/ 02395 #define BP_SIM_SCGC4_UART2 (12U) /*!< Bit position for SIM_SCGC4_UART2. */ 02396 #define BM_SIM_SCGC4_UART2 (0x00001000U) /*!< Bit mask for SIM_SCGC4_UART2. */ 02397 #define BS_SIM_SCGC4_UART2 (1U) /*!< Bit field size in bits for SIM_SCGC4_UART2. */ 02398 02399 /*! @brief Read current value of the SIM_SCGC4_UART2 field. */ 02400 #define BR_SIM_SCGC4_UART2(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART2)) 02401 02402 /*! @brief Format value for bitfield SIM_SCGC4_UART2. */ 02403 #define BF_SIM_SCGC4_UART2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART2) & BM_SIM_SCGC4_UART2) 02404 02405 /*! @brief Set the UART2 field to a new value. */ 02406 #define BW_SIM_SCGC4_UART2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART2) = (v)) 02407 /*@}*/ 02408 02409 /*! 02410 * @name Register SIM_SCGC4, field UART3[13] (RW) 02411 * 02412 * This bit controls the clock gate to the UART3 module. 02413 * 02414 * Values: 02415 * - 0 - Clock disabled 02416 * - 1 - Clock enabled 02417 */ 02418 /*@{*/ 02419 #define BP_SIM_SCGC4_UART3 (13U) /*!< Bit position for SIM_SCGC4_UART3. */ 02420 #define BM_SIM_SCGC4_UART3 (0x00002000U) /*!< Bit mask for SIM_SCGC4_UART3. */ 02421 #define BS_SIM_SCGC4_UART3 (1U) /*!< Bit field size in bits for SIM_SCGC4_UART3. */ 02422 02423 /*! @brief Read current value of the SIM_SCGC4_UART3 field. */ 02424 #define BR_SIM_SCGC4_UART3(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART3)) 02425 02426 /*! @brief Format value for bitfield SIM_SCGC4_UART3. */ 02427 #define BF_SIM_SCGC4_UART3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART3) & BM_SIM_SCGC4_UART3) 02428 02429 /*! @brief Set the UART3 field to a new value. */ 02430 #define BW_SIM_SCGC4_UART3(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART3) = (v)) 02431 /*@}*/ 02432 02433 /*! 02434 * @name Register SIM_SCGC4, field USBOTG[18] (RW) 02435 * 02436 * This bit controls the clock gate to the USB module. 02437 * 02438 * Values: 02439 * - 0 - Clock disabled 02440 * - 1 - Clock enabled 02441 */ 02442 /*@{*/ 02443 #define BP_SIM_SCGC4_USBOTG (18U) /*!< Bit position for SIM_SCGC4_USBOTG. */ 02444 #define BM_SIM_SCGC4_USBOTG (0x00040000U) /*!< Bit mask for SIM_SCGC4_USBOTG. */ 02445 #define BS_SIM_SCGC4_USBOTG (1U) /*!< Bit field size in bits for SIM_SCGC4_USBOTG. */ 02446 02447 /*! @brief Read current value of the SIM_SCGC4_USBOTG field. */ 02448 #define BR_SIM_SCGC4_USBOTG(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_USBOTG)) 02449 02450 /*! @brief Format value for bitfield SIM_SCGC4_USBOTG. */ 02451 #define BF_SIM_SCGC4_USBOTG(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_USBOTG) & BM_SIM_SCGC4_USBOTG) 02452 02453 /*! @brief Set the USBOTG field to a new value. */ 02454 #define BW_SIM_SCGC4_USBOTG(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_USBOTG) = (v)) 02455 /*@}*/ 02456 02457 /*! 02458 * @name Register SIM_SCGC4, field CMP[19] (RW) 02459 * 02460 * This bit controls the clock gate to the comparator module. 02461 * 02462 * Values: 02463 * - 0 - Clock disabled 02464 * - 1 - Clock enabled 02465 */ 02466 /*@{*/ 02467 #define BP_SIM_SCGC4_CMP (19U) /*!< Bit position for SIM_SCGC4_CMP. */ 02468 #define BM_SIM_SCGC4_CMP (0x00080000U) /*!< Bit mask for SIM_SCGC4_CMP. */ 02469 #define BS_SIM_SCGC4_CMP (1U) /*!< Bit field size in bits for SIM_SCGC4_CMP. */ 02470 02471 /*! @brief Read current value of the SIM_SCGC4_CMP field. */ 02472 #define BR_SIM_SCGC4_CMP(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMP)) 02473 02474 /*! @brief Format value for bitfield SIM_SCGC4_CMP. */ 02475 #define BF_SIM_SCGC4_CMP(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_CMP) & BM_SIM_SCGC4_CMP) 02476 02477 /*! @brief Set the CMP field to a new value. */ 02478 #define BW_SIM_SCGC4_CMP(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMP) = (v)) 02479 /*@}*/ 02480 02481 /*! 02482 * @name Register SIM_SCGC4, field VREF[20] (RW) 02483 * 02484 * This bit controls the clock gate to the VREF module. 02485 * 02486 * Values: 02487 * - 0 - Clock disabled 02488 * - 1 - Clock enabled 02489 */ 02490 /*@{*/ 02491 #define BP_SIM_SCGC4_VREF (20U) /*!< Bit position for SIM_SCGC4_VREF. */ 02492 #define BM_SIM_SCGC4_VREF (0x00100000U) /*!< Bit mask for SIM_SCGC4_VREF. */ 02493 #define BS_SIM_SCGC4_VREF (1U) /*!< Bit field size in bits for SIM_SCGC4_VREF. */ 02494 02495 /*! @brief Read current value of the SIM_SCGC4_VREF field. */ 02496 #define BR_SIM_SCGC4_VREF(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_VREF)) 02497 02498 /*! @brief Format value for bitfield SIM_SCGC4_VREF. */ 02499 #define BF_SIM_SCGC4_VREF(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_VREF) & BM_SIM_SCGC4_VREF) 02500 02501 /*! @brief Set the VREF field to a new value. */ 02502 #define BW_SIM_SCGC4_VREF(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_VREF) = (v)) 02503 /*@}*/ 02504 02505 /******************************************************************************* 02506 * HW_SIM_SCGC5 - System Clock Gating Control Register 5 02507 ******************************************************************************/ 02508 02509 /*! 02510 * @brief HW_SIM_SCGC5 - System Clock Gating Control Register 5 (RW) 02511 * 02512 * Reset value: 0x00040182U 02513 */ 02514 typedef union _hw_sim_scgc5 02515 { 02516 uint32_t U; 02517 struct _hw_sim_scgc5_bitfields 02518 { 02519 uint32_t LPTMR : 1; /*!< [0] Low Power Timer Access Control */ 02520 uint32_t RESERVED0 : 8; /*!< [8:1] */ 02521 uint32_t PORTAb : 1; /*!< [9] Port A Clock Gate Control */ 02522 uint32_t PORTBb : 1; /*!< [10] Port B Clock Gate Control */ 02523 uint32_t PORTCb : 1; /*!< [11] Port C Clock Gate Control */ 02524 uint32_t PORTDb : 1; /*!< [12] Port D Clock Gate Control */ 02525 uint32_t PORTEb : 1; /*!< [13] Port E Clock Gate Control */ 02526 uint32_t RESERVED1 : 18; /*!< [31:14] */ 02527 } B; 02528 } hw_sim_scgc5_t; 02529 02530 /*! 02531 * @name Constants and macros for entire SIM_SCGC5 register 02532 */ 02533 /*@{*/ 02534 #define HW_SIM_SCGC5_ADDR(x) ((x) + 0x1038U) 02535 02536 #define HW_SIM_SCGC5(x) (*(__IO hw_sim_scgc5_t *) HW_SIM_SCGC5_ADDR(x)) 02537 #define HW_SIM_SCGC5_RD(x) (HW_SIM_SCGC5(x).U) 02538 #define HW_SIM_SCGC5_WR(x, v) (HW_SIM_SCGC5(x).U = (v)) 02539 #define HW_SIM_SCGC5_SET(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) | (v))) 02540 #define HW_SIM_SCGC5_CLR(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) & ~(v))) 02541 #define HW_SIM_SCGC5_TOG(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) ^ (v))) 02542 /*@}*/ 02543 02544 /* 02545 * Constants & macros for individual SIM_SCGC5 bitfields 02546 */ 02547 02548 /*! 02549 * @name Register SIM_SCGC5, field LPTMR[0] (RW) 02550 * 02551 * This bit controls software access to the Low Power Timer module. 02552 * 02553 * Values: 02554 * - 0 - Access disabled 02555 * - 1 - Access enabled 02556 */ 02557 /*@{*/ 02558 #define BP_SIM_SCGC5_LPTMR (0U) /*!< Bit position for SIM_SCGC5_LPTMR. */ 02559 #define BM_SIM_SCGC5_LPTMR (0x00000001U) /*!< Bit mask for SIM_SCGC5_LPTMR. */ 02560 #define BS_SIM_SCGC5_LPTMR (1U) /*!< Bit field size in bits for SIM_SCGC5_LPTMR. */ 02561 02562 /*! @brief Read current value of the SIM_SCGC5_LPTMR field. */ 02563 #define BR_SIM_SCGC5_LPTMR(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_LPTMR)) 02564 02565 /*! @brief Format value for bitfield SIM_SCGC5_LPTMR. */ 02566 #define BF_SIM_SCGC5_LPTMR(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_LPTMR) & BM_SIM_SCGC5_LPTMR) 02567 02568 /*! @brief Set the LPTMR field to a new value. */ 02569 #define BW_SIM_SCGC5_LPTMR(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_LPTMR) = (v)) 02570 /*@}*/ 02571 02572 /*! 02573 * @name Register SIM_SCGC5, field PORTA[9] (RW) 02574 * 02575 * This bit controls the clock gate to the Port A module. 02576 * 02577 * Values: 02578 * - 0 - Clock disabled 02579 * - 1 - Clock enabled 02580 */ 02581 /*@{*/ 02582 #define BP_SIM_SCGC5_PORTA (9U) /*!< Bit position for SIM_SCGC5_PORTA. */ 02583 #define BM_SIM_SCGC5_PORTA (0x00000200U) /*!< Bit mask for SIM_SCGC5_PORTA. */ 02584 #define BS_SIM_SCGC5_PORTA (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTA. */ 02585 02586 /*! @brief Read current value of the SIM_SCGC5_PORTA field. */ 02587 #define BR_SIM_SCGC5_PORTA(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTA)) 02588 02589 /*! @brief Format value for bitfield SIM_SCGC5_PORTA. */ 02590 #define BF_SIM_SCGC5_PORTA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTA) & BM_SIM_SCGC5_PORTA) 02591 02592 /*! @brief Set the PORTA field to a new value. */ 02593 #define BW_SIM_SCGC5_PORTA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTA) = (v)) 02594 /*@}*/ 02595 02596 /*! 02597 * @name Register SIM_SCGC5, field PORTB[10] (RW) 02598 * 02599 * This bit controls the clock gate to the Port B module. 02600 * 02601 * Values: 02602 * - 0 - Clock disabled 02603 * - 1 - Clock enabled 02604 */ 02605 /*@{*/ 02606 #define BP_SIM_SCGC5_PORTB (10U) /*!< Bit position for SIM_SCGC5_PORTB. */ 02607 #define BM_SIM_SCGC5_PORTB (0x00000400U) /*!< Bit mask for SIM_SCGC5_PORTB. */ 02608 #define BS_SIM_SCGC5_PORTB (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTB. */ 02609 02610 /*! @brief Read current value of the SIM_SCGC5_PORTB field. */ 02611 #define BR_SIM_SCGC5_PORTB(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTB)) 02612 02613 /*! @brief Format value for bitfield SIM_SCGC5_PORTB. */ 02614 #define BF_SIM_SCGC5_PORTB(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTB) & BM_SIM_SCGC5_PORTB) 02615 02616 /*! @brief Set the PORTB field to a new value. */ 02617 #define BW_SIM_SCGC5_PORTB(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTB) = (v)) 02618 /*@}*/ 02619 02620 /*! 02621 * @name Register SIM_SCGC5, field PORTC[11] (RW) 02622 * 02623 * This bit controls the clock gate to the Port C module. 02624 * 02625 * Values: 02626 * - 0 - Clock disabled 02627 * - 1 - Clock enabled 02628 */ 02629 /*@{*/ 02630 #define BP_SIM_SCGC5_PORTC (11U) /*!< Bit position for SIM_SCGC5_PORTC. */ 02631 #define BM_SIM_SCGC5_PORTC (0x00000800U) /*!< Bit mask for SIM_SCGC5_PORTC. */ 02632 #define BS_SIM_SCGC5_PORTC (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTC. */ 02633 02634 /*! @brief Read current value of the SIM_SCGC5_PORTC field. */ 02635 #define BR_SIM_SCGC5_PORTC(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTC)) 02636 02637 /*! @brief Format value for bitfield SIM_SCGC5_PORTC. */ 02638 #define BF_SIM_SCGC5_PORTC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTC) & BM_SIM_SCGC5_PORTC) 02639 02640 /*! @brief Set the PORTC field to a new value. */ 02641 #define BW_SIM_SCGC5_PORTC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTC) = (v)) 02642 /*@}*/ 02643 02644 /*! 02645 * @name Register SIM_SCGC5, field PORTD[12] (RW) 02646 * 02647 * This bit controls the clock gate to the Port D module. 02648 * 02649 * Values: 02650 * - 0 - Clock disabled 02651 * - 1 - Clock enabled 02652 */ 02653 /*@{*/ 02654 #define BP_SIM_SCGC5_PORTD (12U) /*!< Bit position for SIM_SCGC5_PORTD. */ 02655 #define BM_SIM_SCGC5_PORTD (0x00001000U) /*!< Bit mask for SIM_SCGC5_PORTD. */ 02656 #define BS_SIM_SCGC5_PORTD (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTD. */ 02657 02658 /*! @brief Read current value of the SIM_SCGC5_PORTD field. */ 02659 #define BR_SIM_SCGC5_PORTD(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTD)) 02660 02661 /*! @brief Format value for bitfield SIM_SCGC5_PORTD. */ 02662 #define BF_SIM_SCGC5_PORTD(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTD) & BM_SIM_SCGC5_PORTD) 02663 02664 /*! @brief Set the PORTD field to a new value. */ 02665 #define BW_SIM_SCGC5_PORTD(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTD) = (v)) 02666 /*@}*/ 02667 02668 /*! 02669 * @name Register SIM_SCGC5, field PORTE[13] (RW) 02670 * 02671 * This bit controls the clock gate to the Port E module. 02672 * 02673 * Values: 02674 * - 0 - Clock disabled 02675 * - 1 - Clock enabled 02676 */ 02677 /*@{*/ 02678 #define BP_SIM_SCGC5_PORTE (13U) /*!< Bit position for SIM_SCGC5_PORTE. */ 02679 #define BM_SIM_SCGC5_PORTE (0x00002000U) /*!< Bit mask for SIM_SCGC5_PORTE. */ 02680 #define BS_SIM_SCGC5_PORTE (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTE. */ 02681 02682 /*! @brief Read current value of the SIM_SCGC5_PORTE field. */ 02683 #define BR_SIM_SCGC5_PORTE(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTE)) 02684 02685 /*! @brief Format value for bitfield SIM_SCGC5_PORTE. */ 02686 #define BF_SIM_SCGC5_PORTE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTE) & BM_SIM_SCGC5_PORTE) 02687 02688 /*! @brief Set the PORTE field to a new value. */ 02689 #define BW_SIM_SCGC5_PORTE(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTE) = (v)) 02690 /*@}*/ 02691 02692 /******************************************************************************* 02693 * HW_SIM_SCGC6 - System Clock Gating Control Register 6 02694 ******************************************************************************/ 02695 02696 /*! 02697 * @brief HW_SIM_SCGC6 - System Clock Gating Control Register 6 (RW) 02698 * 02699 * Reset value: 0x40000001U 02700 * 02701 * DAC0, FTM2, and RNGA can be accessed through both AIPS0 and AIPS1. When 02702 * accessing through AIPS1, define the clock gate control bits in the SCGC2 and SCGC3. 02703 * When accessing through AIPS0, define the clock gate control bits in SCGC6. 02704 */ 02705 typedef union _hw_sim_scgc6 02706 { 02707 uint32_t U; 02708 struct _hw_sim_scgc6_bitfields 02709 { 02710 uint32_t FTF : 1; /*!< [0] Flash Memory Clock Gate Control */ 02711 uint32_t DMAMUXb : 1; /*!< [1] DMA Mux Clock Gate Control */ 02712 uint32_t RESERVED0 : 2; /*!< [3:2] */ 02713 uint32_t FLEXCAN0 : 1; /*!< [4] FlexCAN0 Clock Gate Control */ 02714 uint32_t RESERVED1 : 4; /*!< [8:5] */ 02715 uint32_t RNGA : 1; /*!< [9] RNGA Clock Gate Control */ 02716 uint32_t RESERVED2 : 2; /*!< [11:10] */ 02717 uint32_t SPI0b : 1; /*!< [12] SPI0 Clock Gate Control */ 02718 uint32_t SPI1b : 1; /*!< [13] SPI1 Clock Gate Control */ 02719 uint32_t RESERVED3 : 1; /*!< [14] */ 02720 uint32_t I2S : 1; /*!< [15] I2S Clock Gate Control */ 02721 uint32_t RESERVED4 : 2; /*!< [17:16] */ 02722 uint32_t CRC : 1; /*!< [18] CRC Clock Gate Control */ 02723 uint32_t RESERVED5 : 2; /*!< [20:19] */ 02724 uint32_t USBDCDb : 1; /*!< [21] USB DCD Clock Gate Control */ 02725 uint32_t PDB : 1; /*!< [22] PDB Clock Gate Control */ 02726 uint32_t PITb : 1; /*!< [23] PIT Clock Gate Control */ 02727 uint32_t FTM0b : 1; /*!< [24] FTM0 Clock Gate Control */ 02728 uint32_t FTM1b : 1; /*!< [25] FTM1 Clock Gate Control */ 02729 uint32_t FTM2b : 1; /*!< [26] FTM2 Clock Gate Control */ 02730 uint32_t ADC0b : 1; /*!< [27] ADC0 Clock Gate Control */ 02731 uint32_t RESERVED6 : 1; /*!< [28] */ 02732 uint32_t RTCb : 1; /*!< [29] RTC Access Control */ 02733 uint32_t RESERVED7 : 1; /*!< [30] */ 02734 uint32_t DAC0b : 1; /*!< [31] DAC0 Clock Gate Control */ 02735 } B; 02736 } hw_sim_scgc6_t; 02737 02738 /*! 02739 * @name Constants and macros for entire SIM_SCGC6 register 02740 */ 02741 /*@{*/ 02742 #define HW_SIM_SCGC6_ADDR(x) ((x) + 0x103CU) 02743 02744 #define HW_SIM_SCGC6(x) (*(__IO hw_sim_scgc6_t *) HW_SIM_SCGC6_ADDR(x)) 02745 #define HW_SIM_SCGC6_RD(x) (HW_SIM_SCGC6(x).U) 02746 #define HW_SIM_SCGC6_WR(x, v) (HW_SIM_SCGC6(x).U = (v)) 02747 #define HW_SIM_SCGC6_SET(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) | (v))) 02748 #define HW_SIM_SCGC6_CLR(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) & ~(v))) 02749 #define HW_SIM_SCGC6_TOG(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) ^ (v))) 02750 /*@}*/ 02751 02752 /* 02753 * Constants & macros for individual SIM_SCGC6 bitfields 02754 */ 02755 02756 /*! 02757 * @name Register SIM_SCGC6, field FTF[0] (RW) 02758 * 02759 * This bit controls the clock gate to the flash memory. Flash reads are still 02760 * supported while the flash memory is clock gated, but entry into low power modes 02761 * is blocked. 02762 * 02763 * Values: 02764 * - 0 - Clock disabled 02765 * - 1 - Clock enabled 02766 */ 02767 /*@{*/ 02768 #define BP_SIM_SCGC6_FTF (0U) /*!< Bit position for SIM_SCGC6_FTF. */ 02769 #define BM_SIM_SCGC6_FTF (0x00000001U) /*!< Bit mask for SIM_SCGC6_FTF. */ 02770 #define BS_SIM_SCGC6_FTF (1U) /*!< Bit field size in bits for SIM_SCGC6_FTF. */ 02771 02772 /*! @brief Read current value of the SIM_SCGC6_FTF field. */ 02773 #define BR_SIM_SCGC6_FTF(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTF)) 02774 02775 /*! @brief Format value for bitfield SIM_SCGC6_FTF. */ 02776 #define BF_SIM_SCGC6_FTF(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTF) & BM_SIM_SCGC6_FTF) 02777 02778 /*! @brief Set the FTF field to a new value. */ 02779 #define BW_SIM_SCGC6_FTF(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTF) = (v)) 02780 /*@}*/ 02781 02782 /*! 02783 * @name Register SIM_SCGC6, field DMAMUX[1] (RW) 02784 * 02785 * This bit controls the clock gate to the DMA Mux module. 02786 * 02787 * Values: 02788 * - 0 - Clock disabled 02789 * - 1 - Clock enabled 02790 */ 02791 /*@{*/ 02792 #define BP_SIM_SCGC6_DMAMUX (1U) /*!< Bit position for SIM_SCGC6_DMAMUX. */ 02793 #define BM_SIM_SCGC6_DMAMUX (0x00000002U) /*!< Bit mask for SIM_SCGC6_DMAMUX. */ 02794 #define BS_SIM_SCGC6_DMAMUX (1U) /*!< Bit field size in bits for SIM_SCGC6_DMAMUX. */ 02795 02796 /*! @brief Read current value of the SIM_SCGC6_DMAMUX field. */ 02797 #define BR_SIM_SCGC6_DMAMUX(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DMAMUX)) 02798 02799 /*! @brief Format value for bitfield SIM_SCGC6_DMAMUX. */ 02800 #define BF_SIM_SCGC6_DMAMUX(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_DMAMUX) & BM_SIM_SCGC6_DMAMUX) 02801 02802 /*! @brief Set the DMAMUX field to a new value. */ 02803 #define BW_SIM_SCGC6_DMAMUX(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DMAMUX) = (v)) 02804 /*@}*/ 02805 02806 /*! 02807 * @name Register SIM_SCGC6, field FLEXCAN0[4] (RW) 02808 * 02809 * This bit controls the clock gate to the FlexCAN0 module. 02810 * 02811 * Values: 02812 * - 0 - Clock disabled 02813 * - 1 - Clock enabled 02814 */ 02815 /*@{*/ 02816 #define BP_SIM_SCGC6_FLEXCAN0 (4U) /*!< Bit position for SIM_SCGC6_FLEXCAN0. */ 02817 #define BM_SIM_SCGC6_FLEXCAN0 (0x00000010U) /*!< Bit mask for SIM_SCGC6_FLEXCAN0. */ 02818 #define BS_SIM_SCGC6_FLEXCAN0 (1U) /*!< Bit field size in bits for SIM_SCGC6_FLEXCAN0. */ 02819 02820 /*! @brief Read current value of the SIM_SCGC6_FLEXCAN0 field. */ 02821 #define BR_SIM_SCGC6_FLEXCAN0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FLEXCAN0)) 02822 02823 /*! @brief Format value for bitfield SIM_SCGC6_FLEXCAN0. */ 02824 #define BF_SIM_SCGC6_FLEXCAN0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FLEXCAN0) & BM_SIM_SCGC6_FLEXCAN0) 02825 02826 /*! @brief Set the FLEXCAN0 field to a new value. */ 02827 #define BW_SIM_SCGC6_FLEXCAN0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FLEXCAN0) = (v)) 02828 /*@}*/ 02829 02830 /*! 02831 * @name Register SIM_SCGC6, field RNGA[9] (RW) 02832 * 02833 * This bit controls the clock gate to the RNGA module. 02834 */ 02835 /*@{*/ 02836 #define BP_SIM_SCGC6_RNGA (9U) /*!< Bit position for SIM_SCGC6_RNGA. */ 02837 #define BM_SIM_SCGC6_RNGA (0x00000200U) /*!< Bit mask for SIM_SCGC6_RNGA. */ 02838 #define BS_SIM_SCGC6_RNGA (1U) /*!< Bit field size in bits for SIM_SCGC6_RNGA. */ 02839 02840 /*! @brief Read current value of the SIM_SCGC6_RNGA field. */ 02841 #define BR_SIM_SCGC6_RNGA(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RNGA)) 02842 02843 /*! @brief Format value for bitfield SIM_SCGC6_RNGA. */ 02844 #define BF_SIM_SCGC6_RNGA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_RNGA) & BM_SIM_SCGC6_RNGA) 02845 02846 /*! @brief Set the RNGA field to a new value. */ 02847 #define BW_SIM_SCGC6_RNGA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RNGA) = (v)) 02848 /*@}*/ 02849 02850 /*! 02851 * @name Register SIM_SCGC6, field SPI0[12] (RW) 02852 * 02853 * This bit controls the clock gate to the SPI0 module. 02854 * 02855 * Values: 02856 * - 0 - Clock disabled 02857 * - 1 - Clock enabled 02858 */ 02859 /*@{*/ 02860 #define BP_SIM_SCGC6_SPI0 (12U) /*!< Bit position for SIM_SCGC6_SPI0. */ 02861 #define BM_SIM_SCGC6_SPI0 (0x00001000U) /*!< Bit mask for SIM_SCGC6_SPI0. */ 02862 #define BS_SIM_SCGC6_SPI0 (1U) /*!< Bit field size in bits for SIM_SCGC6_SPI0. */ 02863 02864 /*! @brief Read current value of the SIM_SCGC6_SPI0 field. */ 02865 #define BR_SIM_SCGC6_SPI0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI0)) 02866 02867 /*! @brief Format value for bitfield SIM_SCGC6_SPI0. */ 02868 #define BF_SIM_SCGC6_SPI0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_SPI0) & BM_SIM_SCGC6_SPI0) 02869 02870 /*! @brief Set the SPI0 field to a new value. */ 02871 #define BW_SIM_SCGC6_SPI0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI0) = (v)) 02872 /*@}*/ 02873 02874 /*! 02875 * @name Register SIM_SCGC6, field SPI1[13] (RW) 02876 * 02877 * This bit controls the clock gate to the SPI1 module. 02878 * 02879 * Values: 02880 * - 0 - Clock disabled 02881 * - 1 - Clock enabled 02882 */ 02883 /*@{*/ 02884 #define BP_SIM_SCGC6_SPI1 (13U) /*!< Bit position for SIM_SCGC6_SPI1. */ 02885 #define BM_SIM_SCGC6_SPI1 (0x00002000U) /*!< Bit mask for SIM_SCGC6_SPI1. */ 02886 #define BS_SIM_SCGC6_SPI1 (1U) /*!< Bit field size in bits for SIM_SCGC6_SPI1. */ 02887 02888 /*! @brief Read current value of the SIM_SCGC6_SPI1 field. */ 02889 #define BR_SIM_SCGC6_SPI1(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI1)) 02890 02891 /*! @brief Format value for bitfield SIM_SCGC6_SPI1. */ 02892 #define BF_SIM_SCGC6_SPI1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_SPI1) & BM_SIM_SCGC6_SPI1) 02893 02894 /*! @brief Set the SPI1 field to a new value. */ 02895 #define BW_SIM_SCGC6_SPI1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI1) = (v)) 02896 /*@}*/ 02897 02898 /*! 02899 * @name Register SIM_SCGC6, field I2S[15] (RW) 02900 * 02901 * This bit controls the clock gate to the I 2 S module. 02902 * 02903 * Values: 02904 * - 0 - Clock disabled 02905 * - 1 - Clock enabled 02906 */ 02907 /*@{*/ 02908 #define BP_SIM_SCGC6_I2S (15U) /*!< Bit position for SIM_SCGC6_I2S. */ 02909 #define BM_SIM_SCGC6_I2S (0x00008000U) /*!< Bit mask for SIM_SCGC6_I2S. */ 02910 #define BS_SIM_SCGC6_I2S (1U) /*!< Bit field size in bits for SIM_SCGC6_I2S. */ 02911 02912 /*! @brief Read current value of the SIM_SCGC6_I2S field. */ 02913 #define BR_SIM_SCGC6_I2S(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_I2S)) 02914 02915 /*! @brief Format value for bitfield SIM_SCGC6_I2S. */ 02916 #define BF_SIM_SCGC6_I2S(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_I2S) & BM_SIM_SCGC6_I2S) 02917 02918 /*! @brief Set the I2S field to a new value. */ 02919 #define BW_SIM_SCGC6_I2S(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_I2S) = (v)) 02920 /*@}*/ 02921 02922 /*! 02923 * @name Register SIM_SCGC6, field CRC[18] (RW) 02924 * 02925 * This bit controls the clock gate to the CRC module. 02926 * 02927 * Values: 02928 * - 0 - Clock disabled 02929 * - 1 - Clock enabled 02930 */ 02931 /*@{*/ 02932 #define BP_SIM_SCGC6_CRC (18U) /*!< Bit position for SIM_SCGC6_CRC. */ 02933 #define BM_SIM_SCGC6_CRC (0x00040000U) /*!< Bit mask for SIM_SCGC6_CRC. */ 02934 #define BS_SIM_SCGC6_CRC (1U) /*!< Bit field size in bits for SIM_SCGC6_CRC. */ 02935 02936 /*! @brief Read current value of the SIM_SCGC6_CRC field. */ 02937 #define BR_SIM_SCGC6_CRC(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_CRC)) 02938 02939 /*! @brief Format value for bitfield SIM_SCGC6_CRC. */ 02940 #define BF_SIM_SCGC6_CRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_CRC) & BM_SIM_SCGC6_CRC) 02941 02942 /*! @brief Set the CRC field to a new value. */ 02943 #define BW_SIM_SCGC6_CRC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_CRC) = (v)) 02944 /*@}*/ 02945 02946 /*! 02947 * @name Register SIM_SCGC6, field USBDCD[21] (RW) 02948 * 02949 * This bit controls the clock gate to the USB DCD module. 02950 * 02951 * Values: 02952 * - 0 - Clock disabled 02953 * - 1 - Clock enabled 02954 */ 02955 /*@{*/ 02956 #define BP_SIM_SCGC6_USBDCD (21U) /*!< Bit position for SIM_SCGC6_USBDCD. */ 02957 #define BM_SIM_SCGC6_USBDCD (0x00200000U) /*!< Bit mask for SIM_SCGC6_USBDCD. */ 02958 #define BS_SIM_SCGC6_USBDCD (1U) /*!< Bit field size in bits for SIM_SCGC6_USBDCD. */ 02959 02960 /*! @brief Read current value of the SIM_SCGC6_USBDCD field. */ 02961 #define BR_SIM_SCGC6_USBDCD(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_USBDCD)) 02962 02963 /*! @brief Format value for bitfield SIM_SCGC6_USBDCD. */ 02964 #define BF_SIM_SCGC6_USBDCD(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_USBDCD) & BM_SIM_SCGC6_USBDCD) 02965 02966 /*! @brief Set the USBDCD field to a new value. */ 02967 #define BW_SIM_SCGC6_USBDCD(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_USBDCD) = (v)) 02968 /*@}*/ 02969 02970 /*! 02971 * @name Register SIM_SCGC6, field PDB[22] (RW) 02972 * 02973 * This bit controls the clock gate to the PDB module. 02974 * 02975 * Values: 02976 * - 0 - Clock disabled 02977 * - 1 - Clock enabled 02978 */ 02979 /*@{*/ 02980 #define BP_SIM_SCGC6_PDB (22U) /*!< Bit position for SIM_SCGC6_PDB. */ 02981 #define BM_SIM_SCGC6_PDB (0x00400000U) /*!< Bit mask for SIM_SCGC6_PDB. */ 02982 #define BS_SIM_SCGC6_PDB (1U) /*!< Bit field size in bits for SIM_SCGC6_PDB. */ 02983 02984 /*! @brief Read current value of the SIM_SCGC6_PDB field. */ 02985 #define BR_SIM_SCGC6_PDB(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PDB)) 02986 02987 /*! @brief Format value for bitfield SIM_SCGC6_PDB. */ 02988 #define BF_SIM_SCGC6_PDB(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_PDB) & BM_SIM_SCGC6_PDB) 02989 02990 /*! @brief Set the PDB field to a new value. */ 02991 #define BW_SIM_SCGC6_PDB(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PDB) = (v)) 02992 /*@}*/ 02993 02994 /*! 02995 * @name Register SIM_SCGC6, field PIT[23] (RW) 02996 * 02997 * This bit controls the clock gate to the PIT module. 02998 * 02999 * Values: 03000 * - 0 - Clock disabled 03001 * - 1 - Clock enabled 03002 */ 03003 /*@{*/ 03004 #define BP_SIM_SCGC6_PIT (23U) /*!< Bit position for SIM_SCGC6_PIT. */ 03005 #define BM_SIM_SCGC6_PIT (0x00800000U) /*!< Bit mask for SIM_SCGC6_PIT. */ 03006 #define BS_SIM_SCGC6_PIT (1U) /*!< Bit field size in bits for SIM_SCGC6_PIT. */ 03007 03008 /*! @brief Read current value of the SIM_SCGC6_PIT field. */ 03009 #define BR_SIM_SCGC6_PIT(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PIT)) 03010 03011 /*! @brief Format value for bitfield SIM_SCGC6_PIT. */ 03012 #define BF_SIM_SCGC6_PIT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_PIT) & BM_SIM_SCGC6_PIT) 03013 03014 /*! @brief Set the PIT field to a new value. */ 03015 #define BW_SIM_SCGC6_PIT(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PIT) = (v)) 03016 /*@}*/ 03017 03018 /*! 03019 * @name Register SIM_SCGC6, field FTM0[24] (RW) 03020 * 03021 * This bit controls the clock gate to the FTM0 module. 03022 * 03023 * Values: 03024 * - 0 - Clock disabled 03025 * - 1 - Clock enabled 03026 */ 03027 /*@{*/ 03028 #define BP_SIM_SCGC6_FTM0 (24U) /*!< Bit position for SIM_SCGC6_FTM0. */ 03029 #define BM_SIM_SCGC6_FTM0 (0x01000000U) /*!< Bit mask for SIM_SCGC6_FTM0. */ 03030 #define BS_SIM_SCGC6_FTM0 (1U) /*!< Bit field size in bits for SIM_SCGC6_FTM0. */ 03031 03032 /*! @brief Read current value of the SIM_SCGC6_FTM0 field. */ 03033 #define BR_SIM_SCGC6_FTM0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM0)) 03034 03035 /*! @brief Format value for bitfield SIM_SCGC6_FTM0. */ 03036 #define BF_SIM_SCGC6_FTM0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM0) & BM_SIM_SCGC6_FTM0) 03037 03038 /*! @brief Set the FTM0 field to a new value. */ 03039 #define BW_SIM_SCGC6_FTM0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM0) = (v)) 03040 /*@}*/ 03041 03042 /*! 03043 * @name Register SIM_SCGC6, field FTM1[25] (RW) 03044 * 03045 * This bit controls the clock gate to the FTM1 module. 03046 * 03047 * Values: 03048 * - 0 - Clock disabled 03049 * - 1 - Clock enabled 03050 */ 03051 /*@{*/ 03052 #define BP_SIM_SCGC6_FTM1 (25U) /*!< Bit position for SIM_SCGC6_FTM1. */ 03053 #define BM_SIM_SCGC6_FTM1 (0x02000000U) /*!< Bit mask for SIM_SCGC6_FTM1. */ 03054 #define BS_SIM_SCGC6_FTM1 (1U) /*!< Bit field size in bits for SIM_SCGC6_FTM1. */ 03055 03056 /*! @brief Read current value of the SIM_SCGC6_FTM1 field. */ 03057 #define BR_SIM_SCGC6_FTM1(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM1)) 03058 03059 /*! @brief Format value for bitfield SIM_SCGC6_FTM1. */ 03060 #define BF_SIM_SCGC6_FTM1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM1) & BM_SIM_SCGC6_FTM1) 03061 03062 /*! @brief Set the FTM1 field to a new value. */ 03063 #define BW_SIM_SCGC6_FTM1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM1) = (v)) 03064 /*@}*/ 03065 03066 /*! 03067 * @name Register SIM_SCGC6, field FTM2[26] (RW) 03068 * 03069 * This bit controls the clock gate to the FTM2 module. 03070 * 03071 * Values: 03072 * - 0 - Clock disabled 03073 * - 1 - Clock enabled 03074 */ 03075 /*@{*/ 03076 #define BP_SIM_SCGC6_FTM2 (26U) /*!< Bit position for SIM_SCGC6_FTM2. */ 03077 #define BM_SIM_SCGC6_FTM2 (0x04000000U) /*!< Bit mask for SIM_SCGC6_FTM2. */ 03078 #define BS_SIM_SCGC6_FTM2 (1U) /*!< Bit field size in bits for SIM_SCGC6_FTM2. */ 03079 03080 /*! @brief Read current value of the SIM_SCGC6_FTM2 field. */ 03081 #define BR_SIM_SCGC6_FTM2(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM2)) 03082 03083 /*! @brief Format value for bitfield SIM_SCGC6_FTM2. */ 03084 #define BF_SIM_SCGC6_FTM2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM2) & BM_SIM_SCGC6_FTM2) 03085 03086 /*! @brief Set the FTM2 field to a new value. */ 03087 #define BW_SIM_SCGC6_FTM2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM2) = (v)) 03088 /*@}*/ 03089 03090 /*! 03091 * @name Register SIM_SCGC6, field ADC0[27] (RW) 03092 * 03093 * This bit controls the clock gate to the ADC0 module. 03094 * 03095 * Values: 03096 * - 0 - Clock disabled 03097 * - 1 - Clock enabled 03098 */ 03099 /*@{*/ 03100 #define BP_SIM_SCGC6_ADC0 (27U) /*!< Bit position for SIM_SCGC6_ADC0. */ 03101 #define BM_SIM_SCGC6_ADC0 (0x08000000U) /*!< Bit mask for SIM_SCGC6_ADC0. */ 03102 #define BS_SIM_SCGC6_ADC0 (1U) /*!< Bit field size in bits for SIM_SCGC6_ADC0. */ 03103 03104 /*! @brief Read current value of the SIM_SCGC6_ADC0 field. */ 03105 #define BR_SIM_SCGC6_ADC0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC0)) 03106 03107 /*! @brief Format value for bitfield SIM_SCGC6_ADC0. */ 03108 #define BF_SIM_SCGC6_ADC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_ADC0) & BM_SIM_SCGC6_ADC0) 03109 03110 /*! @brief Set the ADC0 field to a new value. */ 03111 #define BW_SIM_SCGC6_ADC0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC0) = (v)) 03112 /*@}*/ 03113 03114 /*! 03115 * @name Register SIM_SCGC6, field RTC[29] (RW) 03116 * 03117 * This bit controls software access and interrupts to the RTC module. 03118 * 03119 * Values: 03120 * - 0 - Access and interrupts disabled 03121 * - 1 - Access and interrupts enabled 03122 */ 03123 /*@{*/ 03124 #define BP_SIM_SCGC6_RTC (29U) /*!< Bit position for SIM_SCGC6_RTC. */ 03125 #define BM_SIM_SCGC6_RTC (0x20000000U) /*!< Bit mask for SIM_SCGC6_RTC. */ 03126 #define BS_SIM_SCGC6_RTC (1U) /*!< Bit field size in bits for SIM_SCGC6_RTC. */ 03127 03128 /*! @brief Read current value of the SIM_SCGC6_RTC field. */ 03129 #define BR_SIM_SCGC6_RTC(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RTC)) 03130 03131 /*! @brief Format value for bitfield SIM_SCGC6_RTC. */ 03132 #define BF_SIM_SCGC6_RTC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_RTC) & BM_SIM_SCGC6_RTC) 03133 03134 /*! @brief Set the RTC field to a new value. */ 03135 #define BW_SIM_SCGC6_RTC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RTC) = (v)) 03136 /*@}*/ 03137 03138 /*! 03139 * @name Register SIM_SCGC6, field DAC0[31] (RW) 03140 * 03141 * This bit controls the clock gate to the DAC0 module. 03142 * 03143 * Values: 03144 * - 0 - Clock disabled 03145 * - 1 - Clock enabled 03146 */ 03147 /*@{*/ 03148 #define BP_SIM_SCGC6_DAC0 (31U) /*!< Bit position for SIM_SCGC6_DAC0. */ 03149 #define BM_SIM_SCGC6_DAC0 (0x80000000U) /*!< Bit mask for SIM_SCGC6_DAC0. */ 03150 #define BS_SIM_SCGC6_DAC0 (1U) /*!< Bit field size in bits for SIM_SCGC6_DAC0. */ 03151 03152 /*! @brief Read current value of the SIM_SCGC6_DAC0 field. */ 03153 #define BR_SIM_SCGC6_DAC0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DAC0)) 03154 03155 /*! @brief Format value for bitfield SIM_SCGC6_DAC0. */ 03156 #define BF_SIM_SCGC6_DAC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_DAC0) & BM_SIM_SCGC6_DAC0) 03157 03158 /*! @brief Set the DAC0 field to a new value. */ 03159 #define BW_SIM_SCGC6_DAC0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DAC0) = (v)) 03160 /*@}*/ 03161 03162 /******************************************************************************* 03163 * HW_SIM_SCGC7 - System Clock Gating Control Register 7 03164 ******************************************************************************/ 03165 03166 /*! 03167 * @brief HW_SIM_SCGC7 - System Clock Gating Control Register 7 (RW) 03168 * 03169 * Reset value: 0x00000006U 03170 */ 03171 typedef union _hw_sim_scgc7 03172 { 03173 uint32_t U; 03174 struct _hw_sim_scgc7_bitfields 03175 { 03176 uint32_t FLEXBUS : 1; /*!< [0] FlexBus Clock Gate Control */ 03177 uint32_t DMA : 1; /*!< [1] DMA Clock Gate Control */ 03178 uint32_t MPUb : 1; /*!< [2] MPU Clock Gate Control */ 03179 uint32_t RESERVED0 : 29; /*!< [31:3] */ 03180 } B; 03181 } hw_sim_scgc7_t; 03182 03183 /*! 03184 * @name Constants and macros for entire SIM_SCGC7 register 03185 */ 03186 /*@{*/ 03187 #define HW_SIM_SCGC7_ADDR(x) ((x) + 0x1040U) 03188 03189 #define HW_SIM_SCGC7(x) (*(__IO hw_sim_scgc7_t *) HW_SIM_SCGC7_ADDR(x)) 03190 #define HW_SIM_SCGC7_RD(x) (HW_SIM_SCGC7(x).U) 03191 #define HW_SIM_SCGC7_WR(x, v) (HW_SIM_SCGC7(x).U = (v)) 03192 #define HW_SIM_SCGC7_SET(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) | (v))) 03193 #define HW_SIM_SCGC7_CLR(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) & ~(v))) 03194 #define HW_SIM_SCGC7_TOG(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) ^ (v))) 03195 /*@}*/ 03196 03197 /* 03198 * Constants & macros for individual SIM_SCGC7 bitfields 03199 */ 03200 03201 /*! 03202 * @name Register SIM_SCGC7, field FLEXBUS[0] (RW) 03203 * 03204 * This bit controls the clock gate to the FlexBus module. 03205 * 03206 * Values: 03207 * - 0 - Clock disabled 03208 * - 1 - Clock enabled 03209 */ 03210 /*@{*/ 03211 #define BP_SIM_SCGC7_FLEXBUS (0U) /*!< Bit position for SIM_SCGC7_FLEXBUS. */ 03212 #define BM_SIM_SCGC7_FLEXBUS (0x00000001U) /*!< Bit mask for SIM_SCGC7_FLEXBUS. */ 03213 #define BS_SIM_SCGC7_FLEXBUS (1U) /*!< Bit field size in bits for SIM_SCGC7_FLEXBUS. */ 03214 03215 /*! @brief Read current value of the SIM_SCGC7_FLEXBUS field. */ 03216 #define BR_SIM_SCGC7_FLEXBUS(x) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_FLEXBUS)) 03217 03218 /*! @brief Format value for bitfield SIM_SCGC7_FLEXBUS. */ 03219 #define BF_SIM_SCGC7_FLEXBUS(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_FLEXBUS) & BM_SIM_SCGC7_FLEXBUS) 03220 03221 /*! @brief Set the FLEXBUS field to a new value. */ 03222 #define BW_SIM_SCGC7_FLEXBUS(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_FLEXBUS) = (v)) 03223 /*@}*/ 03224 03225 /*! 03226 * @name Register SIM_SCGC7, field DMA[1] (RW) 03227 * 03228 * This bit controls the clock gate to the DMA module. 03229 * 03230 * Values: 03231 * - 0 - Clock disabled 03232 * - 1 - Clock enabled 03233 */ 03234 /*@{*/ 03235 #define BP_SIM_SCGC7_DMA (1U) /*!< Bit position for SIM_SCGC7_DMA. */ 03236 #define BM_SIM_SCGC7_DMA (0x00000002U) /*!< Bit mask for SIM_SCGC7_DMA. */ 03237 #define BS_SIM_SCGC7_DMA (1U) /*!< Bit field size in bits for SIM_SCGC7_DMA. */ 03238 03239 /*! @brief Read current value of the SIM_SCGC7_DMA field. */ 03240 #define BR_SIM_SCGC7_DMA(x) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_DMA)) 03241 03242 /*! @brief Format value for bitfield SIM_SCGC7_DMA. */ 03243 #define BF_SIM_SCGC7_DMA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_DMA) & BM_SIM_SCGC7_DMA) 03244 03245 /*! @brief Set the DMA field to a new value. */ 03246 #define BW_SIM_SCGC7_DMA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_DMA) = (v)) 03247 /*@}*/ 03248 03249 /*! 03250 * @name Register SIM_SCGC7, field MPU[2] (RW) 03251 * 03252 * This bit controls the clock gate to the MPU module. 03253 * 03254 * Values: 03255 * - 0 - Clock disabled 03256 * - 1 - Clock enabled 03257 */ 03258 /*@{*/ 03259 #define BP_SIM_SCGC7_MPU (2U) /*!< Bit position for SIM_SCGC7_MPU. */ 03260 #define BM_SIM_SCGC7_MPU (0x00000004U) /*!< Bit mask for SIM_SCGC7_MPU. */ 03261 #define BS_SIM_SCGC7_MPU (1U) /*!< Bit field size in bits for SIM_SCGC7_MPU. */ 03262 03263 /*! @brief Read current value of the SIM_SCGC7_MPU field. */ 03264 #define BR_SIM_SCGC7_MPU(x) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_MPU)) 03265 03266 /*! @brief Format value for bitfield SIM_SCGC7_MPU. */ 03267 #define BF_SIM_SCGC7_MPU(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_MPU) & BM_SIM_SCGC7_MPU) 03268 03269 /*! @brief Set the MPU field to a new value. */ 03270 #define BW_SIM_SCGC7_MPU(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_MPU) = (v)) 03271 /*@}*/ 03272 03273 /******************************************************************************* 03274 * HW_SIM_CLKDIV1 - System Clock Divider Register 1 03275 ******************************************************************************/ 03276 03277 /*! 03278 * @brief HW_SIM_CLKDIV1 - System Clock Divider Register 1 (RW) 03279 * 03280 * Reset value: 0x00010000U 03281 * 03282 * When updating CLKDIV1, update all fields using the one write command. 03283 * Attempting to write an invalid clock ratio to the CLKDIV1 register will cause the 03284 * write to be ignored. The maximum divide ratio that can be programmed between 03285 * core/system clock and the other divided clocks is divide by 8. When OUTDIV1 equals 03286 * 0000 (divide by 1), the other dividers cannot be set higher than 0111 (divide 03287 * by 8). The CLKDIV1 register cannot be written to when the device is in VLPR 03288 * mode. 03289 */ 03290 typedef union _hw_sim_clkdiv1 03291 { 03292 uint32_t U; 03293 struct _hw_sim_clkdiv1_bitfields 03294 { 03295 uint32_t RESERVED0 : 16; /*!< [15:0] */ 03296 uint32_t OUTDIV4 : 4; /*!< [19:16] Clock 4 output divider value */ 03297 uint32_t OUTDIV3 : 4; /*!< [23:20] Clock 3 output divider value */ 03298 uint32_t OUTDIV2 : 4; /*!< [27:24] Clock 2 output divider value */ 03299 uint32_t OUTDIV1 : 4; /*!< [31:28] Clock 1 output divider value */ 03300 } B; 03301 } hw_sim_clkdiv1_t; 03302 03303 /*! 03304 * @name Constants and macros for entire SIM_CLKDIV1 register 03305 */ 03306 /*@{*/ 03307 #define HW_SIM_CLKDIV1_ADDR(x) ((x) + 0x1044U) 03308 03309 #define HW_SIM_CLKDIV1(x) (*(__IO hw_sim_clkdiv1_t *) HW_SIM_CLKDIV1_ADDR(x)) 03310 #define HW_SIM_CLKDIV1_RD(x) (HW_SIM_CLKDIV1(x).U) 03311 #define HW_SIM_CLKDIV1_WR(x, v) (HW_SIM_CLKDIV1(x).U = (v)) 03312 #define HW_SIM_CLKDIV1_SET(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) | (v))) 03313 #define HW_SIM_CLKDIV1_CLR(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) & ~(v))) 03314 #define HW_SIM_CLKDIV1_TOG(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) ^ (v))) 03315 /*@}*/ 03316 03317 /* 03318 * Constants & macros for individual SIM_CLKDIV1 bitfields 03319 */ 03320 03321 /*! 03322 * @name Register SIM_CLKDIV1, field OUTDIV4[19:16] (RW) 03323 * 03324 * This field sets the divide value for the flash clock from MCGOUTCLK. At the 03325 * end of reset, it is loaded with either 0001 or 1111 depending on 03326 * FTF_FOPT[LPBOOT]. The flash clock frequency must be an integer divide of the system clock 03327 * frequency. 03328 * 03329 * Values: 03330 * - 0000 - Divide-by-1. 03331 * - 0001 - Divide-by-2. 03332 * - 0010 - Divide-by-3. 03333 * - 0011 - Divide-by-4. 03334 * - 0100 - Divide-by-5. 03335 * - 0101 - Divide-by-6. 03336 * - 0110 - Divide-by-7. 03337 * - 0111 - Divide-by-8. 03338 * - 1000 - Divide-by-9. 03339 * - 1001 - Divide-by-10. 03340 * - 1010 - Divide-by-11. 03341 * - 1011 - Divide-by-12. 03342 * - 1100 - Divide-by-13. 03343 * - 1101 - Divide-by-14. 03344 * - 1110 - Divide-by-15. 03345 * - 1111 - Divide-by-16. 03346 */ 03347 /*@{*/ 03348 #define BP_SIM_CLKDIV1_OUTDIV4 (16U) /*!< Bit position for SIM_CLKDIV1_OUTDIV4. */ 03349 #define BM_SIM_CLKDIV1_OUTDIV4 (0x000F0000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV4. */ 03350 #define BS_SIM_CLKDIV1_OUTDIV4 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV4. */ 03351 03352 /*! @brief Read current value of the SIM_CLKDIV1_OUTDIV4 field. */ 03353 #define BR_SIM_CLKDIV1_OUTDIV4(x) (HW_SIM_CLKDIV1(x).B.OUTDIV4) 03354 03355 /*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV4. */ 03356 #define BF_SIM_CLKDIV1_OUTDIV4(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV4) & BM_SIM_CLKDIV1_OUTDIV4) 03357 03358 /*! @brief Set the OUTDIV4 field to a new value. */ 03359 #define BW_SIM_CLKDIV1_OUTDIV4(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV4) | BF_SIM_CLKDIV1_OUTDIV4(v))) 03360 /*@}*/ 03361 03362 /*! 03363 * @name Register SIM_CLKDIV1, field OUTDIV3[23:20] (RW) 03364 * 03365 * This field sets the divide value for the FlexBus clock (external pin FB_CLK) 03366 * from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111 03367 * depending on FTF_FOPT[LPBOOT]. The FlexBus clock frequency must be an integer 03368 * divide of the system clock frequency. 03369 * 03370 * Values: 03371 * - 0000 - Divide-by-1. 03372 * - 0001 - Divide-by-2. 03373 * - 0010 - Divide-by-3. 03374 * - 0011 - Divide-by-4. 03375 * - 0100 - Divide-by-5. 03376 * - 0101 - Divide-by-6. 03377 * - 0110 - Divide-by-7. 03378 * - 0111 - Divide-by-8. 03379 * - 1000 - Divide-by-9. 03380 * - 1001 - Divide-by-10. 03381 * - 1010 - Divide-by-11. 03382 * - 1011 - Divide-by-12. 03383 * - 1100 - Divide-by-13. 03384 * - 1101 - Divide-by-14. 03385 * - 1110 - Divide-by-15. 03386 * - 1111 - Divide-by-16. 03387 */ 03388 /*@{*/ 03389 #define BP_SIM_CLKDIV1_OUTDIV3 (20U) /*!< Bit position for SIM_CLKDIV1_OUTDIV3. */ 03390 #define BM_SIM_CLKDIV1_OUTDIV3 (0x00F00000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV3. */ 03391 #define BS_SIM_CLKDIV1_OUTDIV3 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV3. */ 03392 03393 /*! @brief Read current value of the SIM_CLKDIV1_OUTDIV3 field. */ 03394 #define BR_SIM_CLKDIV1_OUTDIV3(x) (HW_SIM_CLKDIV1(x).B.OUTDIV3) 03395 03396 /*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV3. */ 03397 #define BF_SIM_CLKDIV1_OUTDIV3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV3) & BM_SIM_CLKDIV1_OUTDIV3) 03398 03399 /*! @brief Set the OUTDIV3 field to a new value. */ 03400 #define BW_SIM_CLKDIV1_OUTDIV3(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV3) | BF_SIM_CLKDIV1_OUTDIV3(v))) 03401 /*@}*/ 03402 03403 /*! 03404 * @name Register SIM_CLKDIV1, field OUTDIV2[27:24] (RW) 03405 * 03406 * This field sets the divide value for the bus clock from MCGOUTCLK. At the end 03407 * of reset, it is loaded with either 0000 or 0111 depending on 03408 * FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock 03409 * frequency. 03410 * 03411 * Values: 03412 * - 0000 - Divide-by-1. 03413 * - 0001 - Divide-by-2. 03414 * - 0010 - Divide-by-3. 03415 * - 0011 - Divide-by-4. 03416 * - 0100 - Divide-by-5. 03417 * - 0101 - Divide-by-6. 03418 * - 0110 - Divide-by-7. 03419 * - 0111 - Divide-by-8. 03420 * - 1000 - Divide-by-9. 03421 * - 1001 - Divide-by-10. 03422 * - 1010 - Divide-by-11. 03423 * - 1011 - Divide-by-12. 03424 * - 1100 - Divide-by-13. 03425 * - 1101 - Divide-by-14. 03426 * - 1110 - Divide-by-15. 03427 * - 1111 - Divide-by-16. 03428 */ 03429 /*@{*/ 03430 #define BP_SIM_CLKDIV1_OUTDIV2 (24U) /*!< Bit position for SIM_CLKDIV1_OUTDIV2. */ 03431 #define BM_SIM_CLKDIV1_OUTDIV2 (0x0F000000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV2. */ 03432 #define BS_SIM_CLKDIV1_OUTDIV2 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV2. */ 03433 03434 /*! @brief Read current value of the SIM_CLKDIV1_OUTDIV2 field. */ 03435 #define BR_SIM_CLKDIV1_OUTDIV2(x) (HW_SIM_CLKDIV1(x).B.OUTDIV2) 03436 03437 /*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV2. */ 03438 #define BF_SIM_CLKDIV1_OUTDIV2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV2) & BM_SIM_CLKDIV1_OUTDIV2) 03439 03440 /*! @brief Set the OUTDIV2 field to a new value. */ 03441 #define BW_SIM_CLKDIV1_OUTDIV2(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV2) | BF_SIM_CLKDIV1_OUTDIV2(v))) 03442 /*@}*/ 03443 03444 /*! 03445 * @name Register SIM_CLKDIV1, field OUTDIV1[31:28] (RW) 03446 * 03447 * This field sets the divide value for the core/system clock from MCGOUTCLK. At 03448 * the end of reset, it is loaded with either 0000 or 0111 depending on 03449 * FTF_FOPT[LPBOOT]. 03450 * 03451 * Values: 03452 * - 0000 - Divide-by-1. 03453 * - 0001 - Divide-by-2. 03454 * - 0010 - Divide-by-3. 03455 * - 0011 - Divide-by-4. 03456 * - 0100 - Divide-by-5. 03457 * - 0101 - Divide-by-6. 03458 * - 0110 - Divide-by-7. 03459 * - 0111 - Divide-by-8. 03460 * - 1000 - Divide-by-9. 03461 * - 1001 - Divide-by-10. 03462 * - 1010 - Divide-by-11. 03463 * - 1011 - Divide-by-12. 03464 * - 1100 - Divide-by-13. 03465 * - 1101 - Divide-by-14. 03466 * - 1110 - Divide-by-15. 03467 * - 1111 - Divide-by-16. 03468 */ 03469 /*@{*/ 03470 #define BP_SIM_CLKDIV1_OUTDIV1 (28U) /*!< Bit position for SIM_CLKDIV1_OUTDIV1. */ 03471 #define BM_SIM_CLKDIV1_OUTDIV1 (0xF0000000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV1. */ 03472 #define BS_SIM_CLKDIV1_OUTDIV1 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV1. */ 03473 03474 /*! @brief Read current value of the SIM_CLKDIV1_OUTDIV1 field. */ 03475 #define BR_SIM_CLKDIV1_OUTDIV1(x) (HW_SIM_CLKDIV1(x).B.OUTDIV1) 03476 03477 /*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV1. */ 03478 #define BF_SIM_CLKDIV1_OUTDIV1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV1) & BM_SIM_CLKDIV1_OUTDIV1) 03479 03480 /*! @brief Set the OUTDIV1 field to a new value. */ 03481 #define BW_SIM_CLKDIV1_OUTDIV1(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV1) | BF_SIM_CLKDIV1_OUTDIV1(v))) 03482 /*@}*/ 03483 03484 /******************************************************************************* 03485 * HW_SIM_CLKDIV2 - System Clock Divider Register 2 03486 ******************************************************************************/ 03487 03488 /*! 03489 * @brief HW_SIM_CLKDIV2 - System Clock Divider Register 2 (RW) 03490 * 03491 * Reset value: 0x00000000U 03492 */ 03493 typedef union _hw_sim_clkdiv2 03494 { 03495 uint32_t U; 03496 struct _hw_sim_clkdiv2_bitfields 03497 { 03498 uint32_t USBFRAC : 1; /*!< [0] USB clock divider fraction */ 03499 uint32_t USBDIV : 3; /*!< [3:1] USB clock divider divisor */ 03500 uint32_t RESERVED0 : 28; /*!< [31:4] */ 03501 } B; 03502 } hw_sim_clkdiv2_t; 03503 03504 /*! 03505 * @name Constants and macros for entire SIM_CLKDIV2 register 03506 */ 03507 /*@{*/ 03508 #define HW_SIM_CLKDIV2_ADDR(x) ((x) + 0x1048U) 03509 03510 #define HW_SIM_CLKDIV2(x) (*(__IO hw_sim_clkdiv2_t *) HW_SIM_CLKDIV2_ADDR(x)) 03511 #define HW_SIM_CLKDIV2_RD(x) (HW_SIM_CLKDIV2(x).U) 03512 #define HW_SIM_CLKDIV2_WR(x, v) (HW_SIM_CLKDIV2(x).U = (v)) 03513 #define HW_SIM_CLKDIV2_SET(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) | (v))) 03514 #define HW_SIM_CLKDIV2_CLR(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) & ~(v))) 03515 #define HW_SIM_CLKDIV2_TOG(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) ^ (v))) 03516 /*@}*/ 03517 03518 /* 03519 * Constants & macros for individual SIM_CLKDIV2 bitfields 03520 */ 03521 03522 /*! 03523 * @name Register SIM_CLKDIV2, field USBFRAC[0] (RW) 03524 * 03525 * This field sets the fraction multiply value for the fractional clock divider 03526 * when the MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 03527 * 1). Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ] 03528 */ 03529 /*@{*/ 03530 #define BP_SIM_CLKDIV2_USBFRAC (0U) /*!< Bit position for SIM_CLKDIV2_USBFRAC. */ 03531 #define BM_SIM_CLKDIV2_USBFRAC (0x00000001U) /*!< Bit mask for SIM_CLKDIV2_USBFRAC. */ 03532 #define BS_SIM_CLKDIV2_USBFRAC (1U) /*!< Bit field size in bits for SIM_CLKDIV2_USBFRAC. */ 03533 03534 /*! @brief Read current value of the SIM_CLKDIV2_USBFRAC field. */ 03535 #define BR_SIM_CLKDIV2_USBFRAC(x) (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR(x), BP_SIM_CLKDIV2_USBFRAC)) 03536 03537 /*! @brief Format value for bitfield SIM_CLKDIV2_USBFRAC. */ 03538 #define BF_SIM_CLKDIV2_USBFRAC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV2_USBFRAC) & BM_SIM_CLKDIV2_USBFRAC) 03539 03540 /*! @brief Set the USBFRAC field to a new value. */ 03541 #define BW_SIM_CLKDIV2_USBFRAC(x, v) (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR(x), BP_SIM_CLKDIV2_USBFRAC) = (v)) 03542 /*@}*/ 03543 03544 /*! 03545 * @name Register SIM_CLKDIV2, field USBDIV[3:1] (RW) 03546 * 03547 * This field sets the divide value for the fractional clock divider when the 03548 * MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). Divider 03549 * output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ] 03550 */ 03551 /*@{*/ 03552 #define BP_SIM_CLKDIV2_USBDIV (1U) /*!< Bit position for SIM_CLKDIV2_USBDIV. */ 03553 #define BM_SIM_CLKDIV2_USBDIV (0x0000000EU) /*!< Bit mask for SIM_CLKDIV2_USBDIV. */ 03554 #define BS_SIM_CLKDIV2_USBDIV (3U) /*!< Bit field size in bits for SIM_CLKDIV2_USBDIV. */ 03555 03556 /*! @brief Read current value of the SIM_CLKDIV2_USBDIV field. */ 03557 #define BR_SIM_CLKDIV2_USBDIV(x) (HW_SIM_CLKDIV2(x).B.USBDIV) 03558 03559 /*! @brief Format value for bitfield SIM_CLKDIV2_USBDIV. */ 03560 #define BF_SIM_CLKDIV2_USBDIV(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV2_USBDIV) & BM_SIM_CLKDIV2_USBDIV) 03561 03562 /*! @brief Set the USBDIV field to a new value. */ 03563 #define BW_SIM_CLKDIV2_USBDIV(x, v) (HW_SIM_CLKDIV2_WR(x, (HW_SIM_CLKDIV2_RD(x) & ~BM_SIM_CLKDIV2_USBDIV) | BF_SIM_CLKDIV2_USBDIV(v))) 03564 /*@}*/ 03565 03566 /******************************************************************************* 03567 * HW_SIM_FCFG1 - Flash Configuration Register 1 03568 ******************************************************************************/ 03569 03570 /*! 03571 * @brief HW_SIM_FCFG1 - Flash Configuration Register 1 (RW) 03572 * 03573 * Reset value: 0xFF0F0F00U 03574 * 03575 * For devices with FlexNVM: The reset value of EESIZE and DEPART are based on 03576 * user programming in user IFR via the PGMPART flash command. For devices with 03577 * program flash only: 03578 */ 03579 typedef union _hw_sim_fcfg1 03580 { 03581 uint32_t U; 03582 struct _hw_sim_fcfg1_bitfields 03583 { 03584 uint32_t FLASHDIS : 1; /*!< [0] Flash Disable */ 03585 uint32_t FLASHDOZE : 1; /*!< [1] Flash Doze */ 03586 uint32_t RESERVED0 : 6; /*!< [7:2] */ 03587 uint32_t DEPART : 4; /*!< [11:8] FlexNVM partition */ 03588 uint32_t RESERVED1 : 4; /*!< [15:12] */ 03589 uint32_t EESIZE : 4; /*!< [19:16] EEPROM size */ 03590 uint32_t RESERVED2 : 4; /*!< [23:20] */ 03591 uint32_t PFSIZE : 4; /*!< [27:24] Program flash size */ 03592 uint32_t NVMSIZE : 4; /*!< [31:28] FlexNVM size */ 03593 } B; 03594 } hw_sim_fcfg1_t; 03595 03596 /*! 03597 * @name Constants and macros for entire SIM_FCFG1 register 03598 */ 03599 /*@{*/ 03600 #define HW_SIM_FCFG1_ADDR(x) ((x) + 0x104CU) 03601 03602 #define HW_SIM_FCFG1(x) (*(__IO hw_sim_fcfg1_t *) HW_SIM_FCFG1_ADDR(x)) 03603 #define HW_SIM_FCFG1_RD(x) (HW_SIM_FCFG1(x).U) 03604 #define HW_SIM_FCFG1_WR(x, v) (HW_SIM_FCFG1(x).U = (v)) 03605 #define HW_SIM_FCFG1_SET(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) | (v))) 03606 #define HW_SIM_FCFG1_CLR(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) & ~(v))) 03607 #define HW_SIM_FCFG1_TOG(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) ^ (v))) 03608 /*@}*/ 03609 03610 /* 03611 * Constants & macros for individual SIM_FCFG1 bitfields 03612 */ 03613 03614 /*! 03615 * @name Register SIM_FCFG1, field FLASHDIS[0] (RW) 03616 * 03617 * Flash accesses are disabled (and generate a bus error) and the Flash memory 03618 * is placed in a low power state. This bit should not be changed during VLP 03619 * modes. Relocate the interrupt vectors out of Flash memory before disabling the 03620 * Flash. 03621 * 03622 * Values: 03623 * - 0 - Flash is enabled 03624 * - 1 - Flash is disabled 03625 */ 03626 /*@{*/ 03627 #define BP_SIM_FCFG1_FLASHDIS (0U) /*!< Bit position for SIM_FCFG1_FLASHDIS. */ 03628 #define BM_SIM_FCFG1_FLASHDIS (0x00000001U) /*!< Bit mask for SIM_FCFG1_FLASHDIS. */ 03629 #define BS_SIM_FCFG1_FLASHDIS (1U) /*!< Bit field size in bits for SIM_FCFG1_FLASHDIS. */ 03630 03631 /*! @brief Read current value of the SIM_FCFG1_FLASHDIS field. */ 03632 #define BR_SIM_FCFG1_FLASHDIS(x) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDIS)) 03633 03634 /*! @brief Format value for bitfield SIM_FCFG1_FLASHDIS. */ 03635 #define BF_SIM_FCFG1_FLASHDIS(v) ((uint32_t)((uint32_t)(v) << BP_SIM_FCFG1_FLASHDIS) & BM_SIM_FCFG1_FLASHDIS) 03636 03637 /*! @brief Set the FLASHDIS field to a new value. */ 03638 #define BW_SIM_FCFG1_FLASHDIS(x, v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDIS) = (v)) 03639 /*@}*/ 03640 03641 /*! 03642 * @name Register SIM_FCFG1, field FLASHDOZE[1] (RW) 03643 * 03644 * When set, Flash memory is disabled for the duration of Wait mode. An attempt 03645 * by the DMA or other bus master to access the Flash when the Flash is disabled 03646 * will result in a bus error. This bit should be clear during VLP modes. The 03647 * Flash will be automatically enabled again at the end of Wait mode so interrupt 03648 * vectors do not need to be relocated out of Flash memory. The wakeup time from 03649 * Wait mode is extended when this bit is set. 03650 * 03651 * Values: 03652 * - 0 - Flash remains enabled during Wait mode 03653 * - 1 - Flash is disabled for the duration of Wait mode 03654 */ 03655 /*@{*/ 03656 #define BP_SIM_FCFG1_FLASHDOZE (1U) /*!< Bit position for SIM_FCFG1_FLASHDOZE. */ 03657 #define BM_SIM_FCFG1_FLASHDOZE (0x00000002U) /*!< Bit mask for SIM_FCFG1_FLASHDOZE. */ 03658 #define BS_SIM_FCFG1_FLASHDOZE (1U) /*!< Bit field size in bits for SIM_FCFG1_FLASHDOZE. */ 03659 03660 /*! @brief Read current value of the SIM_FCFG1_FLASHDOZE field. */ 03661 #define BR_SIM_FCFG1_FLASHDOZE(x) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDOZE)) 03662 03663 /*! @brief Format value for bitfield SIM_FCFG1_FLASHDOZE. */ 03664 #define BF_SIM_FCFG1_FLASHDOZE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_FCFG1_FLASHDOZE) & BM_SIM_FCFG1_FLASHDOZE) 03665 03666 /*! @brief Set the FLASHDOZE field to a new value. */ 03667 #define BW_SIM_FCFG1_FLASHDOZE(x, v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDOZE) = (v)) 03668 /*@}*/ 03669 03670 /*! 03671 * @name Register SIM_FCFG1, field DEPART[11:8] (RO) 03672 * 03673 * For devices with FlexNVM: Data flash / EEPROM backup split . See DEPART bit 03674 * description in FTFE chapter. For devices without FlexNVM: Reserved 03675 */ 03676 /*@{*/ 03677 #define BP_SIM_FCFG1_DEPART (8U) /*!< Bit position for SIM_FCFG1_DEPART. */ 03678 #define BM_SIM_FCFG1_DEPART (0x00000F00U) /*!< Bit mask for SIM_FCFG1_DEPART. */ 03679 #define BS_SIM_FCFG1_DEPART (4U) /*!< Bit field size in bits for SIM_FCFG1_DEPART. */ 03680 03681 /*! @brief Read current value of the SIM_FCFG1_DEPART field. */ 03682 #define BR_SIM_FCFG1_DEPART(x) (HW_SIM_FCFG1(x).B.DEPART) 03683 /*@}*/ 03684 03685 /*! 03686 * @name Register SIM_FCFG1, field EESIZE[19:16] (RO) 03687 * 03688 * EEPROM data size . 03689 * 03690 * Values: 03691 * - 0000 - 16 KB 03692 * - 0001 - 8 KB 03693 * - 0010 - 4 KB 03694 * - 0011 - 2 KB 03695 * - 0100 - 1 KB 03696 * - 0101 - 512 Bytes 03697 * - 0110 - 256 Bytes 03698 * - 0111 - 128 Bytes 03699 * - 1000 - 64 Bytes 03700 * - 1001 - 32 Bytes 03701 * - 1111 - 0 Bytes 03702 */ 03703 /*@{*/ 03704 #define BP_SIM_FCFG1_EESIZE (16U) /*!< Bit position for SIM_FCFG1_EESIZE. */ 03705 #define BM_SIM_FCFG1_EESIZE (0x000F0000U) /*!< Bit mask for SIM_FCFG1_EESIZE. */ 03706 #define BS_SIM_FCFG1_EESIZE (4U) /*!< Bit field size in bits for SIM_FCFG1_EESIZE. */ 03707 03708 /*! @brief Read current value of the SIM_FCFG1_EESIZE field. */ 03709 #define BR_SIM_FCFG1_EESIZE(x) (HW_SIM_FCFG1(x).B.EESIZE) 03710 /*@}*/ 03711 03712 /*! 03713 * @name Register SIM_FCFG1, field PFSIZE[27:24] (RO) 03714 * 03715 * This field specifies the amount of program flash memory available on the 03716 * device . Undefined values are reserved. 03717 * 03718 * Values: 03719 * - 0011 - 32 KB of program flash memory 03720 * - 0101 - 64 KB of program flash memory 03721 * - 0111 - 128 KB of program flash memory 03722 * - 1001 - 256 KB of program flash memory 03723 * - 1011 - 512 KB of program flash memory 03724 * - 1101 - 1024 KB of program flash memory 03725 * - 1111 - 1024 KB of program flash memory 03726 */ 03727 /*@{*/ 03728 #define BP_SIM_FCFG1_PFSIZE (24U) /*!< Bit position for SIM_FCFG1_PFSIZE. */ 03729 #define BM_SIM_FCFG1_PFSIZE (0x0F000000U) /*!< Bit mask for SIM_FCFG1_PFSIZE. */ 03730 #define BS_SIM_FCFG1_PFSIZE (4U) /*!< Bit field size in bits for SIM_FCFG1_PFSIZE. */ 03731 03732 /*! @brief Read current value of the SIM_FCFG1_PFSIZE field. */ 03733 #define BR_SIM_FCFG1_PFSIZE(x) (HW_SIM_FCFG1(x).B.PFSIZE) 03734 /*@}*/ 03735 03736 /*! 03737 * @name Register SIM_FCFG1, field NVMSIZE[31:28] (RO) 03738 * 03739 * This field specifies the amount of FlexNVM memory available on the device . 03740 * Undefined values are reserved. 03741 * 03742 * Values: 03743 * - 0000 - 0 KB of FlexNVM 03744 * - 0011 - 32 KB of FlexNVM 03745 * - 0101 - 64 KB of FlexNVM 03746 * - 0111 - 128 KB of FlexNVM 03747 * - 1001 - 256 KB of FlexNVM 03748 * - 1011 - 512 KB of FlexNVM 03749 * - 1111 - 512 KB of FlexNVM 03750 */ 03751 /*@{*/ 03752 #define BP_SIM_FCFG1_NVMSIZE (28U) /*!< Bit position for SIM_FCFG1_NVMSIZE. */ 03753 #define BM_SIM_FCFG1_NVMSIZE (0xF0000000U) /*!< Bit mask for SIM_FCFG1_NVMSIZE. */ 03754 #define BS_SIM_FCFG1_NVMSIZE (4U) /*!< Bit field size in bits for SIM_FCFG1_NVMSIZE. */ 03755 03756 /*! @brief Read current value of the SIM_FCFG1_NVMSIZE field. */ 03757 #define BR_SIM_FCFG1_NVMSIZE(x) (HW_SIM_FCFG1(x).B.NVMSIZE) 03758 /*@}*/ 03759 03760 /******************************************************************************* 03761 * HW_SIM_FCFG2 - Flash Configuration Register 2 03762 ******************************************************************************/ 03763 03764 /*! 03765 * @brief HW_SIM_FCFG2 - Flash Configuration Register 2 (RO) 03766 * 03767 * Reset value: 0x7F7F0000U 03768 */ 03769 typedef union _hw_sim_fcfg2 03770 { 03771 uint32_t U; 03772 struct _hw_sim_fcfg2_bitfields 03773 { 03774 uint32_t RESERVED0 : 16; /*!< [15:0] */ 03775 uint32_t MAXADDR1 : 7; /*!< [22:16] Max address block 1 */ 03776 uint32_t PFLSH : 1; /*!< [23] Program flash only */ 03777 uint32_t MAXADDR0 : 7; /*!< [30:24] Max address block 0 */ 03778 uint32_t RESERVED1 : 1; /*!< [31] */ 03779 } B; 03780 } hw_sim_fcfg2_t; 03781 03782 /*! 03783 * @name Constants and macros for entire SIM_FCFG2 register 03784 */ 03785 /*@{*/ 03786 #define HW_SIM_FCFG2_ADDR(x) ((x) + 0x1050U) 03787 03788 #define HW_SIM_FCFG2(x) (*(__I hw_sim_fcfg2_t *) HW_SIM_FCFG2_ADDR(x)) 03789 #define HW_SIM_FCFG2_RD(x) (HW_SIM_FCFG2(x).U) 03790 /*@}*/ 03791 03792 /* 03793 * Constants & macros for individual SIM_FCFG2 bitfields 03794 */ 03795 03796 /*! 03797 * @name Register SIM_FCFG2, field MAXADDR1[22:16] (RO) 03798 * 03799 * For devices with FlexNVM: This field concatenated with 13 trailing zeros plus 03800 * the FlexNVM base address indicates the first invalid address of the FlexNVM 03801 * flash block. For example, if MAXADDR1 = 0x20 the first invalid address of 03802 * FlexNVM flash block is 0x4_0000 + 0x1000_0000 . This would be the MAXADDR1 value 03803 * for a device with 256 KB FlexNVM. For devices with program flash only: This 03804 * field equals zero if there is only one program flash block, otherwise it equals 03805 * the value of the MAXADDR0 field. For example, with MAXADDR0 = MAXADDR1 = 0x20 03806 * the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000. This would be 03807 * the MAXADDR1 value for a device with 512 KB program flash memory across two 03808 * flash blocks and no FlexNVM. 03809 */ 03810 /*@{*/ 03811 #define BP_SIM_FCFG2_MAXADDR1 (16U) /*!< Bit position for SIM_FCFG2_MAXADDR1. */ 03812 #define BM_SIM_FCFG2_MAXADDR1 (0x007F0000U) /*!< Bit mask for SIM_FCFG2_MAXADDR1. */ 03813 #define BS_SIM_FCFG2_MAXADDR1 (7U) /*!< Bit field size in bits for SIM_FCFG2_MAXADDR1. */ 03814 03815 /*! @brief Read current value of the SIM_FCFG2_MAXADDR1 field. */ 03816 #define BR_SIM_FCFG2_MAXADDR1(x) (HW_SIM_FCFG2(x).B.MAXADDR1) 03817 /*@}*/ 03818 03819 /*! 03820 * @name Register SIM_FCFG2, field PFLSH[23] (RO) 03821 * 03822 * For devices with FlexNVM, this bit is always clear. For devices without 03823 * FlexNVM, this bit is always set. 03824 * 03825 * Values: 03826 * - 0 - Device supports FlexNVM 03827 * - 1 - Program Flash only, device does not support FlexNVM 03828 */ 03829 /*@{*/ 03830 #define BP_SIM_FCFG2_PFLSH (23U) /*!< Bit position for SIM_FCFG2_PFLSH. */ 03831 #define BM_SIM_FCFG2_PFLSH (0x00800000U) /*!< Bit mask for SIM_FCFG2_PFLSH. */ 03832 #define BS_SIM_FCFG2_PFLSH (1U) /*!< Bit field size in bits for SIM_FCFG2_PFLSH. */ 03833 03834 /*! @brief Read current value of the SIM_FCFG2_PFLSH field. */ 03835 #define BR_SIM_FCFG2_PFLSH(x) (BITBAND_ACCESS32(HW_SIM_FCFG2_ADDR(x), BP_SIM_FCFG2_PFLSH)) 03836 /*@}*/ 03837 03838 /*! 03839 * @name Register SIM_FCFG2, field MAXADDR0[30:24] (RO) 03840 * 03841 * This field concatenated with 13 trailing zeros indicates the first invalid 03842 * address of each program flash block. For example, if MAXADDR0 = 0x20 the first 03843 * invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0 03844 * value for a device with 256 KB program flash in flash block 0. 03845 */ 03846 /*@{*/ 03847 #define BP_SIM_FCFG2_MAXADDR0 (24U) /*!< Bit position for SIM_FCFG2_MAXADDR0. */ 03848 #define BM_SIM_FCFG2_MAXADDR0 (0x7F000000U) /*!< Bit mask for SIM_FCFG2_MAXADDR0. */ 03849 #define BS_SIM_FCFG2_MAXADDR0 (7U) /*!< Bit field size in bits for SIM_FCFG2_MAXADDR0. */ 03850 03851 /*! @brief Read current value of the SIM_FCFG2_MAXADDR0 field. */ 03852 #define BR_SIM_FCFG2_MAXADDR0(x) (HW_SIM_FCFG2(x).B.MAXADDR0) 03853 /*@}*/ 03854 03855 /******************************************************************************* 03856 * HW_SIM_UIDH - Unique Identification Register High 03857 ******************************************************************************/ 03858 03859 /*! 03860 * @brief HW_SIM_UIDH - Unique Identification Register High (RO) 03861 * 03862 * Reset value: 0x00000000U 03863 */ 03864 typedef union _hw_sim_uidh 03865 { 03866 uint32_t U; 03867 struct _hw_sim_uidh_bitfields 03868 { 03869 uint32_t UID : 32; /*!< [31:0] Unique Identification */ 03870 } B; 03871 } hw_sim_uidh_t; 03872 03873 /*! 03874 * @name Constants and macros for entire SIM_UIDH register 03875 */ 03876 /*@{*/ 03877 #define HW_SIM_UIDH_ADDR(x) ((x) + 0x1054U) 03878 03879 #define HW_SIM_UIDH(x) (*(__I hw_sim_uidh_t *) HW_SIM_UIDH_ADDR(x)) 03880 #define HW_SIM_UIDH_RD(x) (HW_SIM_UIDH(x).U) 03881 /*@}*/ 03882 03883 /* 03884 * Constants & macros for individual SIM_UIDH bitfields 03885 */ 03886 03887 /*! 03888 * @name Register SIM_UIDH, field UID[31:0] (RO) 03889 * 03890 * Unique identification for the device. 03891 */ 03892 /*@{*/ 03893 #define BP_SIM_UIDH_UID (0U) /*!< Bit position for SIM_UIDH_UID. */ 03894 #define BM_SIM_UIDH_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDH_UID. */ 03895 #define BS_SIM_UIDH_UID (32U) /*!< Bit field size in bits for SIM_UIDH_UID. */ 03896 03897 /*! @brief Read current value of the SIM_UIDH_UID field. */ 03898 #define BR_SIM_UIDH_UID(x) (HW_SIM_UIDH(x).U) 03899 /*@}*/ 03900 03901 /******************************************************************************* 03902 * HW_SIM_UIDMH - Unique Identification Register Mid-High 03903 ******************************************************************************/ 03904 03905 /*! 03906 * @brief HW_SIM_UIDMH - Unique Identification Register Mid-High (RO) 03907 * 03908 * Reset value: 0x00000000U 03909 */ 03910 typedef union _hw_sim_uidmh 03911 { 03912 uint32_t U; 03913 struct _hw_sim_uidmh_bitfields 03914 { 03915 uint32_t UID : 32; /*!< [31:0] Unique Identification */ 03916 } B; 03917 } hw_sim_uidmh_t; 03918 03919 /*! 03920 * @name Constants and macros for entire SIM_UIDMH register 03921 */ 03922 /*@{*/ 03923 #define HW_SIM_UIDMH_ADDR(x) ((x) + 0x1058U) 03924 03925 #define HW_SIM_UIDMH(x) (*(__I hw_sim_uidmh_t *) HW_SIM_UIDMH_ADDR(x)) 03926 #define HW_SIM_UIDMH_RD(x) (HW_SIM_UIDMH(x).U) 03927 /*@}*/ 03928 03929 /* 03930 * Constants & macros for individual SIM_UIDMH bitfields 03931 */ 03932 03933 /*! 03934 * @name Register SIM_UIDMH, field UID[31:0] (RO) 03935 * 03936 * Unique identification for the device. 03937 */ 03938 /*@{*/ 03939 #define BP_SIM_UIDMH_UID (0U) /*!< Bit position for SIM_UIDMH_UID. */ 03940 #define BM_SIM_UIDMH_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDMH_UID. */ 03941 #define BS_SIM_UIDMH_UID (32U) /*!< Bit field size in bits for SIM_UIDMH_UID. */ 03942 03943 /*! @brief Read current value of the SIM_UIDMH_UID field. */ 03944 #define BR_SIM_UIDMH_UID(x) (HW_SIM_UIDMH(x).U) 03945 /*@}*/ 03946 03947 /******************************************************************************* 03948 * HW_SIM_UIDML - Unique Identification Register Mid Low 03949 ******************************************************************************/ 03950 03951 /*! 03952 * @brief HW_SIM_UIDML - Unique Identification Register Mid Low (RO) 03953 * 03954 * Reset value: 0x00000000U 03955 */ 03956 typedef union _hw_sim_uidml 03957 { 03958 uint32_t U; 03959 struct _hw_sim_uidml_bitfields 03960 { 03961 uint32_t UID : 32; /*!< [31:0] Unique Identification */ 03962 } B; 03963 } hw_sim_uidml_t; 03964 03965 /*! 03966 * @name Constants and macros for entire SIM_UIDML register 03967 */ 03968 /*@{*/ 03969 #define HW_SIM_UIDML_ADDR(x) ((x) + 0x105CU) 03970 03971 #define HW_SIM_UIDML(x) (*(__I hw_sim_uidml_t *) HW_SIM_UIDML_ADDR(x)) 03972 #define HW_SIM_UIDML_RD(x) (HW_SIM_UIDML(x).U) 03973 /*@}*/ 03974 03975 /* 03976 * Constants & macros for individual SIM_UIDML bitfields 03977 */ 03978 03979 /*! 03980 * @name Register SIM_UIDML, field UID[31:0] (RO) 03981 * 03982 * Unique identification for the device. 03983 */ 03984 /*@{*/ 03985 #define BP_SIM_UIDML_UID (0U) /*!< Bit position for SIM_UIDML_UID. */ 03986 #define BM_SIM_UIDML_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDML_UID. */ 03987 #define BS_SIM_UIDML_UID (32U) /*!< Bit field size in bits for SIM_UIDML_UID. */ 03988 03989 /*! @brief Read current value of the SIM_UIDML_UID field. */ 03990 #define BR_SIM_UIDML_UID(x) (HW_SIM_UIDML(x).U) 03991 /*@}*/ 03992 03993 /******************************************************************************* 03994 * HW_SIM_UIDL - Unique Identification Register Low 03995 ******************************************************************************/ 03996 03997 /*! 03998 * @brief HW_SIM_UIDL - Unique Identification Register Low (RO) 03999 * 04000 * Reset value: 0x00000000U 04001 */ 04002 typedef union _hw_sim_uidl 04003 { 04004 uint32_t U; 04005 struct _hw_sim_uidl_bitfields 04006 { 04007 uint32_t UID : 32; /*!< [31:0] Unique Identification */ 04008 } B; 04009 } hw_sim_uidl_t; 04010 04011 /*! 04012 * @name Constants and macros for entire SIM_UIDL register 04013 */ 04014 /*@{*/ 04015 #define HW_SIM_UIDL_ADDR(x) ((x) + 0x1060U) 04016 04017 #define HW_SIM_UIDL(x) (*(__I hw_sim_uidl_t *) HW_SIM_UIDL_ADDR(x)) 04018 #define HW_SIM_UIDL_RD(x) (HW_SIM_UIDL(x).U) 04019 /*@}*/ 04020 04021 /* 04022 * Constants & macros for individual SIM_UIDL bitfields 04023 */ 04024 04025 /*! 04026 * @name Register SIM_UIDL, field UID[31:0] (RO) 04027 * 04028 * Unique identification for the device. 04029 */ 04030 /*@{*/ 04031 #define BP_SIM_UIDL_UID (0U) /*!< Bit position for SIM_UIDL_UID. */ 04032 #define BM_SIM_UIDL_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDL_UID. */ 04033 #define BS_SIM_UIDL_UID (32U) /*!< Bit field size in bits for SIM_UIDL_UID. */ 04034 04035 /*! @brief Read current value of the SIM_UIDL_UID field. */ 04036 #define BR_SIM_UIDL_UID(x) (HW_SIM_UIDL(x).U) 04037 /*@}*/ 04038 04039 /******************************************************************************* 04040 * hw_sim_t - module struct 04041 ******************************************************************************/ 04042 /*! 04043 * @brief All SIM module registers. 04044 */ 04045 #pragma pack(1) 04046 typedef struct _hw_sim 04047 { 04048 __IO hw_sim_sopt1_t SOPT1 ; /*!< [0x0] System Options Register 1 */ 04049 __IO hw_sim_sopt1cfg_t SOPT1CFG ; /*!< [0x4] SOPT1 Configuration Register */ 04050 uint8_t _reserved0[4092]; 04051 __IO hw_sim_sopt2_t SOPT2 ; /*!< [0x1004] System Options Register 2 */ 04052 uint8_t _reserved1[4]; 04053 __IO hw_sim_sopt4_t SOPT4 ; /*!< [0x100C] System Options Register 4 */ 04054 __IO hw_sim_sopt5_t SOPT5 ; /*!< [0x1010] System Options Register 5 */ 04055 uint8_t _reserved2[4]; 04056 __IO hw_sim_sopt7_t SOPT7 ; /*!< [0x1018] System Options Register 7 */ 04057 uint8_t _reserved3[8]; 04058 __I hw_sim_sdid_t SDID ; /*!< [0x1024] System Device Identification Register */ 04059 __IO hw_sim_scgc1_t SCGC1 ; /*!< [0x1028] System Clock Gating Control Register 1 */ 04060 __IO hw_sim_scgc2_t SCGC2 ; /*!< [0x102C] System Clock Gating Control Register 2 */ 04061 __IO hw_sim_scgc3_t SCGC3 ; /*!< [0x1030] System Clock Gating Control Register 3 */ 04062 __IO hw_sim_scgc4_t SCGC4 ; /*!< [0x1034] System Clock Gating Control Register 4 */ 04063 __IO hw_sim_scgc5_t SCGC5 ; /*!< [0x1038] System Clock Gating Control Register 5 */ 04064 __IO hw_sim_scgc6_t SCGC6 ; /*!< [0x103C] System Clock Gating Control Register 6 */ 04065 __IO hw_sim_scgc7_t SCGC7 ; /*!< [0x1040] System Clock Gating Control Register 7 */ 04066 __IO hw_sim_clkdiv1_t CLKDIV1 ; /*!< [0x1044] System Clock Divider Register 1 */ 04067 __IO hw_sim_clkdiv2_t CLKDIV2 ; /*!< [0x1048] System Clock Divider Register 2 */ 04068 __IO hw_sim_fcfg1_t FCFG1 ; /*!< [0x104C] Flash Configuration Register 1 */ 04069 __I hw_sim_fcfg2_t FCFG2 ; /*!< [0x1050] Flash Configuration Register 2 */ 04070 __I hw_sim_uidh_t UIDH ; /*!< [0x1054] Unique Identification Register High */ 04071 __I hw_sim_uidmh_t UIDMH ; /*!< [0x1058] Unique Identification Register Mid-High */ 04072 __I hw_sim_uidml_t UIDML ; /*!< [0x105C] Unique Identification Register Mid Low */ 04073 __I hw_sim_uidl_t UIDL ; /*!< [0x1060] Unique Identification Register Low */ 04074 } hw_sim_t; 04075 #pragma pack() 04076 04077 /*! @brief Macro to access all SIM registers. */ 04078 /*! @param x SIM module instance base address. */ 04079 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, 04080 * use the '&' operator, like <code>&HW_SIM(SIM_BASE)</code>. */ 04081 #define HW_SIM(x) (*(hw_sim_t *)(x)) 04082 04083 #endif /* __HW_SIM_REGISTERS_H__ */ 04084 /* EOF */
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