MK64F12_adc.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     Redistribution and use in source and binary forms, with or without modification,
00019 **     are permitted provided that the following conditions are met:
00020 **
00021 **     o Redistributions of source code must retain the above copyright notice, this list
00022 **       of conditions and the following disclaimer.
00023 **
00024 **     o Redistributions in binary form must reproduce the above copyright notice, this
00025 **       list of conditions and the following disclaimer in the documentation and/or
00026 **       other materials provided with the distribution.
00027 **
00028 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00029 **       contributors may be used to endorse or promote products derived from this
00030 **       software without specific prior written permission.
00031 **
00032 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00033 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00034 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00035 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00036 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00037 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00038 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00039 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00040 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00041 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00042 **
00043 **     http:                 www.freescale.com
00044 **     mail:                 support@freescale.com
00045 **
00046 **     Revisions:
00047 **     - rev. 1.0 (2013-08-12)
00048 **         Initial version.
00049 **     - rev. 2.0 (2013-10-29)
00050 **         Register accessor macros added to the memory map.
00051 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00052 **         Startup file for gcc has been updated according to CMSIS 3.2.
00053 **         System initialization updated.
00054 **         MCG - registers updated.
00055 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00056 **     - rev. 2.1 (2013-10-30)
00057 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00058 **     - rev. 2.2 (2013-12-09)
00059 **         DMA - EARS register removed.
00060 **         AIPS0, AIPS1 - MPRA register updated.
00061 **     - rev. 2.3 (2014-01-24)
00062 **         Update according to reference manual rev. 2
00063 **         ENET, MCG, MCM, SIM, USB - registers updated
00064 **     - rev. 2.4 (2014-02-10)
00065 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00066 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00067 **     - rev. 2.5 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00071 **
00072 ** ###################################################################
00073 */
00074 
00075 /*
00076  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00077  *
00078  * This file was generated automatically and any changes may be lost.
00079  */
00080 #ifndef __HW_ADC_REGISTERS_H__
00081 #define __HW_ADC_REGISTERS_H__
00082 
00083 #include "MK64F12.h"
00084 #include "fsl_bitaccess.h"
00085 
00086 /*
00087  * MK64F12 ADC
00088  *
00089  * Analog-to-Digital Converter
00090  *
00091  * Registers defined in this header file:
00092  * - HW_ADC_SC1n - ADC Status and Control Registers 1
00093  * - HW_ADC_CFG1 - ADC Configuration Register 1
00094  * - HW_ADC_CFG2 - ADC Configuration Register 2
00095  * - HW_ADC_Rn - ADC Data Result Register
00096  * - HW_ADC_CV1 - Compare Value Registers
00097  * - HW_ADC_CV2 - Compare Value Registers
00098  * - HW_ADC_SC2 - Status and Control Register 2
00099  * - HW_ADC_SC3 - Status and Control Register 3
00100  * - HW_ADC_OFS - ADC Offset Correction Register
00101  * - HW_ADC_PG - ADC Plus-Side Gain Register
00102  * - HW_ADC_MG - ADC Minus-Side Gain Register
00103  * - HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register
00104  * - HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register
00105  * - HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register
00106  * - HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register
00107  * - HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register
00108  * - HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register
00109  * - HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register
00110  * - HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register
00111  * - HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register
00112  * - HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register
00113  * - HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register
00114  * - HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register
00115  * - HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register
00116  * - HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register
00117  *
00118  * - hw_adc_t - Struct containing all module registers.
00119  */
00120 
00121 #define HW_ADC_INSTANCE_COUNT (2U) /*!< Number of instances of the ADC module. */
00122 #define HW_ADC0 (0U) /*!< Instance number for ADC0. */
00123 #define HW_ADC1 (1U) /*!< Instance number for ADC1. */
00124 
00125 /*******************************************************************************
00126  * HW_ADC_SC1n - ADC Status and Control Registers 1
00127  ******************************************************************************/
00128 
00129 /*!
00130  * @brief HW_ADC_SC1n - ADC Status and Control Registers 1 (RW)
00131  *
00132  * Reset value: 0x0000001FU
00133  *
00134  * SC1A is used for both software and hardware trigger modes of operation. To
00135  * allow sequential conversions of the ADC to be triggered by internal peripherals,
00136  * the ADC can have more than one status and control register: one for each
00137  * conversion. The SC1B-SC1n registers indicate potentially multiple SC1 registers
00138  * for use only in hardware trigger mode. See the chip configuration information
00139  * about the number of SC1n registers specific to this device. The SC1n registers
00140  * have identical fields, and are used in a "ping-pong" approach to control ADC
00141  * operation. At any one point in time, only one of the SC1n registers is actively
00142  * controlling ADC conversions. Updating SC1A while SC1n is actively controlling
00143  * a conversion is allowed, and vice-versa for any of the SC1n registers specific
00144  * to this MCU. Writing SC1A while SC1A is actively controlling a conversion
00145  * aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0,
00146  * writes to SC1A subsequently initiate a new conversion, if SC1[ADCH] contains a
00147  * value other than all 1s. Writing any of the SC1n registers while that specific
00148  * SC1n register is actively controlling a conversion aborts the current conversion.
00149  * None of the SC1B-SC1n registers are used for software trigger operation and
00150  * therefore writes to the SC1B-SC1n registers do not initiate a new conversion.
00151  */
00152 typedef union _hw_adc_sc1n
00153 {
00154     uint32_t U;
00155     struct _hw_adc_sc1n_bitfields
00156     {
00157         uint32_t ADCH : 5;             /*!< [4:0] Input channel select */
00158         uint32_t DIFF : 1;             /*!< [5] Differential Mode Enable */
00159         uint32_t AIEN : 1;             /*!< [6] Interrupt Enable */
00160         uint32_t COCO : 1;             /*!< [7] Conversion Complete Flag */
00161         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
00162     } B;
00163 } hw_adc_sc1n_t;
00164 
00165 /*!
00166  * @name Constants and macros for entire ADC_SC1n register
00167  */
00168 /*@{*/
00169 #define HW_ADC_SC1n_COUNT (2U)
00170 
00171 #define HW_ADC_SC1n_ADDR(x, n)   ((x) + 0x0U + (0x4U * (n)))
00172 
00173 #define HW_ADC_SC1n(x, n)        (*(__IO hw_adc_sc1n_t *) HW_ADC_SC1n_ADDR(x, n))
00174 #define HW_ADC_SC1n_RD(x, n)     (HW_ADC_SC1n(x, n).U)
00175 #define HW_ADC_SC1n_WR(x, n, v)  (HW_ADC_SC1n(x, n).U = (v))
00176 #define HW_ADC_SC1n_SET(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) |  (v)))
00177 #define HW_ADC_SC1n_CLR(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) & ~(v)))
00178 #define HW_ADC_SC1n_TOG(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) ^  (v)))
00179 /*@}*/
00180 
00181 /*
00182  * Constants & macros for individual ADC_SC1n bitfields
00183  */
00184 
00185 /*!
00186  * @name Register ADC_SC1n, field ADCH[4:0] (RW)
00187  *
00188  * Selects one of the input channels. The input channel decode depends on the
00189  * value of DIFF. DAD0-DAD3 are associated with the input pin pairs DADPx and
00190  * DADMx. Some of the input channel options in the bitfield-setting descriptions might
00191  * not be available for your device. For the actual ADC channel assignments for
00192  * your device, see the Chip Configuration details. The successive approximation
00193  * converter subsystem is turned off when the channel select bits are all set,
00194  * that is, ADCH = 11111. This feature allows explicit disabling of the ADC and
00195  * isolation of the input channel from all sources. Terminating continuous
00196  * conversions this way prevents an additional single conversion from being performed. It
00197  * is not necessary to set ADCH to all 1s to place the ADC in a low-power state
00198  * when continuous conversions are not enabled because the module automatically
00199  * enters a low-power state when a conversion completes.
00200  *
00201  * Values:
00202  * - 00000 - When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is
00203  *     selected as input.
00204  * - 00001 - When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is
00205  *     selected as input.
00206  * - 00010 - When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is
00207  *     selected as input.
00208  * - 00011 - When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is
00209  *     selected as input.
00210  * - 00100 - When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
00211  * - 00101 - When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
00212  * - 00110 - When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
00213  * - 00111 - When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
00214  * - 01000 - When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
00215  * - 01001 - When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
00216  * - 01010 - When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
00217  * - 01011 - When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
00218  * - 01100 - When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
00219  * - 01101 - When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
00220  * - 01110 - When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
00221  * - 01111 - When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
00222  * - 10000 - When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
00223  * - 10001 - When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
00224  * - 10010 - When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
00225  * - 10011 - When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
00226  * - 10100 - When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
00227  * - 10101 - When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
00228  * - 10110 - When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
00229  * - 10111 - When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
00230  * - 11000 - Reserved.
00231  * - 11001 - Reserved.
00232  * - 11010 - When DIFF=0, Temp Sensor (single-ended) is selected as input; when
00233  *     DIFF=1, Temp Sensor (differential) is selected as input.
00234  * - 11011 - When DIFF=0, Bandgap (single-ended) is selected as input; when
00235  *     DIFF=1, Bandgap (differential) is selected as input.
00236  * - 11100 - Reserved.
00237  * - 11101 - When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH
00238  *     (differential) is selected as input. Voltage reference selected is determined
00239  *     by SC2[REFSEL].
00240  * - 11110 - When DIFF=0,VREFSL is selected as input; when DIFF=1, it is
00241  *     reserved. Voltage reference selected is determined by SC2[REFSEL].
00242  * - 11111 - Module is disabled.
00243  */
00244 /*@{*/
00245 #define BP_ADC_SC1n_ADCH     (0U)          /*!< Bit position for ADC_SC1n_ADCH. */
00246 #define BM_ADC_SC1n_ADCH     (0x0000001FU) /*!< Bit mask for ADC_SC1n_ADCH. */
00247 #define BS_ADC_SC1n_ADCH     (5U)          /*!< Bit field size in bits for ADC_SC1n_ADCH. */
00248 
00249 /*! @brief Read current value of the ADC_SC1n_ADCH field. */
00250 #define BR_ADC_SC1n_ADCH(x, n) (HW_ADC_SC1n(x, n).B.ADCH)
00251 
00252 /*! @brief Format value for bitfield ADC_SC1n_ADCH. */
00253 #define BF_ADC_SC1n_ADCH(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_SC1n_ADCH) & BM_ADC_SC1n_ADCH)
00254 
00255 /*! @brief Set the ADCH field to a new value. */
00256 #define BW_ADC_SC1n_ADCH(x, n, v) (HW_ADC_SC1n_WR(x, n, (HW_ADC_SC1n_RD(x, n) & ~BM_ADC_SC1n_ADCH) | BF_ADC_SC1n_ADCH(v)))
00257 /*@}*/
00258 
00259 /*!
00260  * @name Register ADC_SC1n, field DIFF[5] (RW)
00261  *
00262  * Configures the ADC to operate in differential mode. When enabled, this mode
00263  * automatically selects from the differential channels, and changes the
00264  * conversion algorithm and the number of cycles to complete a conversion.
00265  *
00266  * Values:
00267  * - 0 - Single-ended conversions and input channels are selected.
00268  * - 1 - Differential conversions and input channels are selected.
00269  */
00270 /*@{*/
00271 #define BP_ADC_SC1n_DIFF     (5U)          /*!< Bit position for ADC_SC1n_DIFF. */
00272 #define BM_ADC_SC1n_DIFF     (0x00000020U) /*!< Bit mask for ADC_SC1n_DIFF. */
00273 #define BS_ADC_SC1n_DIFF     (1U)          /*!< Bit field size in bits for ADC_SC1n_DIFF. */
00274 
00275 /*! @brief Read current value of the ADC_SC1n_DIFF field. */
00276 #define BR_ADC_SC1n_DIFF(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_DIFF))
00277 
00278 /*! @brief Format value for bitfield ADC_SC1n_DIFF. */
00279 #define BF_ADC_SC1n_DIFF(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_SC1n_DIFF) & BM_ADC_SC1n_DIFF)
00280 
00281 /*! @brief Set the DIFF field to a new value. */
00282 #define BW_ADC_SC1n_DIFF(x, n, v) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_DIFF) = (v))
00283 /*@}*/
00284 
00285 /*!
00286  * @name Register ADC_SC1n, field AIEN[6] (RW)
00287  *
00288  * Enables conversion complete interrupts. When COCO becomes set while the
00289  * respective AIEN is high, an interrupt is asserted.
00290  *
00291  * Values:
00292  * - 0 - Conversion complete interrupt is disabled.
00293  * - 1 - Conversion complete interrupt is enabled.
00294  */
00295 /*@{*/
00296 #define BP_ADC_SC1n_AIEN     (6U)          /*!< Bit position for ADC_SC1n_AIEN. */
00297 #define BM_ADC_SC1n_AIEN     (0x00000040U) /*!< Bit mask for ADC_SC1n_AIEN. */
00298 #define BS_ADC_SC1n_AIEN     (1U)          /*!< Bit field size in bits for ADC_SC1n_AIEN. */
00299 
00300 /*! @brief Read current value of the ADC_SC1n_AIEN field. */
00301 #define BR_ADC_SC1n_AIEN(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_AIEN))
00302 
00303 /*! @brief Format value for bitfield ADC_SC1n_AIEN. */
00304 #define BF_ADC_SC1n_AIEN(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_SC1n_AIEN) & BM_ADC_SC1n_AIEN)
00305 
00306 /*! @brief Set the AIEN field to a new value. */
00307 #define BW_ADC_SC1n_AIEN(x, n, v) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_AIEN) = (v))
00308 /*@}*/
00309 
00310 /*!
00311  * @name Register ADC_SC1n, field COCO[7] (RO)
00312  *
00313  * This is a read-only field that is set each time a conversion is completed
00314  * when the compare function is disabled, or SC2[ACFE]=0 and the hardware average
00315  * function is disabled, or SC3[AVGE]=0. When the compare function is enabled, or
00316  * SC2[ACFE]=1, COCO is set upon completion of a conversion only if the compare
00317  * result is true. When the hardware average function is enabled, or SC3[AVGE]=1,
00318  * COCO is set upon completion of the selected number of conversions (determined
00319  * by AVGS). COCO in SC1A is also set at the completion of a calibration sequence.
00320  * COCO is cleared when the respective SC1n register is written or when the
00321  * respective Rn register is read.
00322  *
00323  * Values:
00324  * - 0 - Conversion is not completed.
00325  * - 1 - Conversion is completed.
00326  */
00327 /*@{*/
00328 #define BP_ADC_SC1n_COCO     (7U)          /*!< Bit position for ADC_SC1n_COCO. */
00329 #define BM_ADC_SC1n_COCO     (0x00000080U) /*!< Bit mask for ADC_SC1n_COCO. */
00330 #define BS_ADC_SC1n_COCO     (1U)          /*!< Bit field size in bits for ADC_SC1n_COCO. */
00331 
00332 /*! @brief Read current value of the ADC_SC1n_COCO field. */
00333 #define BR_ADC_SC1n_COCO(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_COCO))
00334 /*@}*/
00335 
00336 /*******************************************************************************
00337  * HW_ADC_CFG1 - ADC Configuration Register 1
00338  ******************************************************************************/
00339 
00340 /*!
00341  * @brief HW_ADC_CFG1 - ADC Configuration Register 1 (RW)
00342  *
00343  * Reset value: 0x00000000U
00344  *
00345  * The configuration Register 1 (CFG1) selects the mode of operation, clock
00346  * source, clock divide, and configuration for low power or long sample time.
00347  */
00348 typedef union _hw_adc_cfg1
00349 {
00350     uint32_t U;
00351     struct _hw_adc_cfg1_bitfields
00352     {
00353         uint32_t ADICLK : 2;           /*!< [1:0] Input Clock Select */
00354         uint32_t MODE : 2;             /*!< [3:2] Conversion mode selection */
00355         uint32_t ADLSMP : 1;           /*!< [4] Sample Time Configuration */
00356         uint32_t ADIV : 2;             /*!< [6:5] Clock Divide Select */
00357         uint32_t ADLPC : 1;            /*!< [7] Low-Power Configuration */
00358         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
00359     } B;
00360 } hw_adc_cfg1_t;
00361 
00362 /*!
00363  * @name Constants and macros for entire ADC_CFG1 register
00364  */
00365 /*@{*/
00366 #define HW_ADC_CFG1_ADDR(x)      ((x) + 0x8U)
00367 
00368 #define HW_ADC_CFG1(x)           (*(__IO hw_adc_cfg1_t *) HW_ADC_CFG1_ADDR(x))
00369 #define HW_ADC_CFG1_RD(x)        (HW_ADC_CFG1(x).U)
00370 #define HW_ADC_CFG1_WR(x, v)     (HW_ADC_CFG1(x).U = (v))
00371 #define HW_ADC_CFG1_SET(x, v)    (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) |  (v)))
00372 #define HW_ADC_CFG1_CLR(x, v)    (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) & ~(v)))
00373 #define HW_ADC_CFG1_TOG(x, v)    (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) ^  (v)))
00374 /*@}*/
00375 
00376 /*
00377  * Constants & macros for individual ADC_CFG1 bitfields
00378  */
00379 
00380 /*!
00381  * @name Register ADC_CFG1, field ADICLK[1:0] (RW)
00382  *
00383  * Selects the input clock source to generate the internal clock, ADCK. Note
00384  * that when the ADACK clock source is selected, it is not required to be active
00385  * prior to conversion start. When it is selected and it is not active prior to a
00386  * conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at
00387  * the start of a conversion and deactivated when conversions are terminated. In
00388  * this case, there is an associated clock startup delay each time the clock
00389  * source is re-activated.
00390  *
00391  * Values:
00392  * - 00 - Bus clock
00393  * - 01 - Alternate clock 2 (ALTCLK2)
00394  * - 10 - Alternate clock (ALTCLK)
00395  * - 11 - Asynchronous clock (ADACK)
00396  */
00397 /*@{*/
00398 #define BP_ADC_CFG1_ADICLK   (0U)          /*!< Bit position for ADC_CFG1_ADICLK. */
00399 #define BM_ADC_CFG1_ADICLK   (0x00000003U) /*!< Bit mask for ADC_CFG1_ADICLK. */
00400 #define BS_ADC_CFG1_ADICLK   (2U)          /*!< Bit field size in bits for ADC_CFG1_ADICLK. */
00401 
00402 /*! @brief Read current value of the ADC_CFG1_ADICLK field. */
00403 #define BR_ADC_CFG1_ADICLK(x) (HW_ADC_CFG1(x).B.ADICLK)
00404 
00405 /*! @brief Format value for bitfield ADC_CFG1_ADICLK. */
00406 #define BF_ADC_CFG1_ADICLK(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADICLK) & BM_ADC_CFG1_ADICLK)
00407 
00408 /*! @brief Set the ADICLK field to a new value. */
00409 #define BW_ADC_CFG1_ADICLK(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_ADICLK) | BF_ADC_CFG1_ADICLK(v)))
00410 /*@}*/
00411 
00412 /*!
00413  * @name Register ADC_CFG1, field MODE[3:2] (RW)
00414  *
00415  * Selects the ADC resolution mode.
00416  *
00417  * Values:
00418  * - 00 - When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is
00419  *     differential 9-bit conversion with 2's complement output.
00420  * - 01 - When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is
00421  *     differential 13-bit conversion with 2's complement output.
00422  * - 10 - When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is
00423  *     differential 11-bit conversion with 2's complement output
00424  * - 11 - When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is
00425  *     differential 16-bit conversion with 2's complement output
00426  */
00427 /*@{*/
00428 #define BP_ADC_CFG1_MODE     (2U)          /*!< Bit position for ADC_CFG1_MODE. */
00429 #define BM_ADC_CFG1_MODE     (0x0000000CU) /*!< Bit mask for ADC_CFG1_MODE. */
00430 #define BS_ADC_CFG1_MODE     (2U)          /*!< Bit field size in bits for ADC_CFG1_MODE. */
00431 
00432 /*! @brief Read current value of the ADC_CFG1_MODE field. */
00433 #define BR_ADC_CFG1_MODE(x)  (HW_ADC_CFG1(x).B.MODE)
00434 
00435 /*! @brief Format value for bitfield ADC_CFG1_MODE. */
00436 #define BF_ADC_CFG1_MODE(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_MODE) & BM_ADC_CFG1_MODE)
00437 
00438 /*! @brief Set the MODE field to a new value. */
00439 #define BW_ADC_CFG1_MODE(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_MODE) | BF_ADC_CFG1_MODE(v)))
00440 /*@}*/
00441 
00442 /*!
00443  * @name Register ADC_CFG1, field ADLSMP[4] (RW)
00444  *
00445  * Selects between different sample times based on the conversion mode selected.
00446  * This field adjusts the sample period to allow higher impedance inputs to be
00447  * accurately sampled or to maximize conversion speed for lower impedance inputs.
00448  * Longer sample times can also be used to lower overall power consumption if
00449  * continuous conversions are enabled and high conversion rates are not required.
00450  * When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the
00451  * extent of the long sample time.
00452  *
00453  * Values:
00454  * - 0 - Short sample time.
00455  * - 1 - Long sample time.
00456  */
00457 /*@{*/
00458 #define BP_ADC_CFG1_ADLSMP   (4U)          /*!< Bit position for ADC_CFG1_ADLSMP. */
00459 #define BM_ADC_CFG1_ADLSMP   (0x00000010U) /*!< Bit mask for ADC_CFG1_ADLSMP. */
00460 #define BS_ADC_CFG1_ADLSMP   (1U)          /*!< Bit field size in bits for ADC_CFG1_ADLSMP. */
00461 
00462 /*! @brief Read current value of the ADC_CFG1_ADLSMP field. */
00463 #define BR_ADC_CFG1_ADLSMP(x) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLSMP))
00464 
00465 /*! @brief Format value for bitfield ADC_CFG1_ADLSMP. */
00466 #define BF_ADC_CFG1_ADLSMP(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADLSMP) & BM_ADC_CFG1_ADLSMP)
00467 
00468 /*! @brief Set the ADLSMP field to a new value. */
00469 #define BW_ADC_CFG1_ADLSMP(x, v) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLSMP) = (v))
00470 /*@}*/
00471 
00472 /*!
00473  * @name Register ADC_CFG1, field ADIV[6:5] (RW)
00474  *
00475  * Selects the divide ratio used by the ADC to generate the internal clock ADCK.
00476  *
00477  * Values:
00478  * - 00 - The divide ratio is 1 and the clock rate is input clock.
00479  * - 01 - The divide ratio is 2 and the clock rate is (input clock)/2.
00480  * - 10 - The divide ratio is 4 and the clock rate is (input clock)/4.
00481  * - 11 - The divide ratio is 8 and the clock rate is (input clock)/8.
00482  */
00483 /*@{*/
00484 #define BP_ADC_CFG1_ADIV     (5U)          /*!< Bit position for ADC_CFG1_ADIV. */
00485 #define BM_ADC_CFG1_ADIV     (0x00000060U) /*!< Bit mask for ADC_CFG1_ADIV. */
00486 #define BS_ADC_CFG1_ADIV     (2U)          /*!< Bit field size in bits for ADC_CFG1_ADIV. */
00487 
00488 /*! @brief Read current value of the ADC_CFG1_ADIV field. */
00489 #define BR_ADC_CFG1_ADIV(x)  (HW_ADC_CFG1(x).B.ADIV)
00490 
00491 /*! @brief Format value for bitfield ADC_CFG1_ADIV. */
00492 #define BF_ADC_CFG1_ADIV(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADIV) & BM_ADC_CFG1_ADIV)
00493 
00494 /*! @brief Set the ADIV field to a new value. */
00495 #define BW_ADC_CFG1_ADIV(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_ADIV) | BF_ADC_CFG1_ADIV(v)))
00496 /*@}*/
00497 
00498 /*!
00499  * @name Register ADC_CFG1, field ADLPC[7] (RW)
00500  *
00501  * Controls the power configuration of the successive approximation converter.
00502  * This optimizes power consumption when higher sample rates are not required.
00503  *
00504  * Values:
00505  * - 0 - Normal power configuration.
00506  * - 1 - Low-power configuration. The power is reduced at the expense of maximum
00507  *     clock speed.
00508  */
00509 /*@{*/
00510 #define BP_ADC_CFG1_ADLPC    (7U)          /*!< Bit position for ADC_CFG1_ADLPC. */
00511 #define BM_ADC_CFG1_ADLPC    (0x00000080U) /*!< Bit mask for ADC_CFG1_ADLPC. */
00512 #define BS_ADC_CFG1_ADLPC    (1U)          /*!< Bit field size in bits for ADC_CFG1_ADLPC. */
00513 
00514 /*! @brief Read current value of the ADC_CFG1_ADLPC field. */
00515 #define BR_ADC_CFG1_ADLPC(x) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLPC))
00516 
00517 /*! @brief Format value for bitfield ADC_CFG1_ADLPC. */
00518 #define BF_ADC_CFG1_ADLPC(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADLPC) & BM_ADC_CFG1_ADLPC)
00519 
00520 /*! @brief Set the ADLPC field to a new value. */
00521 #define BW_ADC_CFG1_ADLPC(x, v) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLPC) = (v))
00522 /*@}*/
00523 
00524 /*******************************************************************************
00525  * HW_ADC_CFG2 - ADC Configuration Register 2
00526  ******************************************************************************/
00527 
00528 /*!
00529  * @brief HW_ADC_CFG2 - ADC Configuration Register 2 (RW)
00530  *
00531  * Reset value: 0x00000000U
00532  *
00533  * Configuration Register 2 (CFG2) selects the special high-speed configuration
00534  * for very high speed conversions and selects the long sample time duration
00535  * during long sample mode.
00536  */
00537 typedef union _hw_adc_cfg2
00538 {
00539     uint32_t U;
00540     struct _hw_adc_cfg2_bitfields
00541     {
00542         uint32_t ADLSTS : 2;           /*!< [1:0] Long Sample Time Select */
00543         uint32_t ADHSC : 1;            /*!< [2] High-Speed Configuration */
00544         uint32_t ADACKEN : 1;          /*!< [3] Asynchronous Clock Output Enable */
00545         uint32_t MUXSEL : 1;           /*!< [4] ADC Mux Select */
00546         uint32_t RESERVED0 : 27;       /*!< [31:5]  */
00547     } B;
00548 } hw_adc_cfg2_t;
00549 
00550 /*!
00551  * @name Constants and macros for entire ADC_CFG2 register
00552  */
00553 /*@{*/
00554 #define HW_ADC_CFG2_ADDR(x)      ((x) + 0xCU)
00555 
00556 #define HW_ADC_CFG2(x)           (*(__IO hw_adc_cfg2_t *) HW_ADC_CFG2_ADDR(x))
00557 #define HW_ADC_CFG2_RD(x)        (HW_ADC_CFG2(x).U)
00558 #define HW_ADC_CFG2_WR(x, v)     (HW_ADC_CFG2(x).U = (v))
00559 #define HW_ADC_CFG2_SET(x, v)    (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) |  (v)))
00560 #define HW_ADC_CFG2_CLR(x, v)    (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) & ~(v)))
00561 #define HW_ADC_CFG2_TOG(x, v)    (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) ^  (v)))
00562 /*@}*/
00563 
00564 /*
00565  * Constants & macros for individual ADC_CFG2 bitfields
00566  */
00567 
00568 /*!
00569  * @name Register ADC_CFG2, field ADLSTS[1:0] (RW)
00570  *
00571  * Selects between the extended sample times when long sample time is selected,
00572  * that is, when CFG1[ADLSMP]=1. This allows higher impedance inputs to be
00573  * accurately sampled or to maximize conversion speed for lower impedance inputs.
00574  * Longer sample times can also be used to lower overall power consumption when
00575  * continuous conversions are enabled if high conversion rates are not required.
00576  *
00577  * Values:
00578  * - 00 - Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles
00579  *     total.
00580  * - 01 - 12 extra ADCK cycles; 16 ADCK cycles total sample time.
00581  * - 10 - 6 extra ADCK cycles; 10 ADCK cycles total sample time.
00582  * - 11 - 2 extra ADCK cycles; 6 ADCK cycles total sample time.
00583  */
00584 /*@{*/
00585 #define BP_ADC_CFG2_ADLSTS   (0U)          /*!< Bit position for ADC_CFG2_ADLSTS. */
00586 #define BM_ADC_CFG2_ADLSTS   (0x00000003U) /*!< Bit mask for ADC_CFG2_ADLSTS. */
00587 #define BS_ADC_CFG2_ADLSTS   (2U)          /*!< Bit field size in bits for ADC_CFG2_ADLSTS. */
00588 
00589 /*! @brief Read current value of the ADC_CFG2_ADLSTS field. */
00590 #define BR_ADC_CFG2_ADLSTS(x) (HW_ADC_CFG2(x).B.ADLSTS)
00591 
00592 /*! @brief Format value for bitfield ADC_CFG2_ADLSTS. */
00593 #define BF_ADC_CFG2_ADLSTS(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_ADLSTS) & BM_ADC_CFG2_ADLSTS)
00594 
00595 /*! @brief Set the ADLSTS field to a new value. */
00596 #define BW_ADC_CFG2_ADLSTS(x, v) (HW_ADC_CFG2_WR(x, (HW_ADC_CFG2_RD(x) & ~BM_ADC_CFG2_ADLSTS) | BF_ADC_CFG2_ADLSTS(v)))
00597 /*@}*/
00598 
00599 /*!
00600  * @name Register ADC_CFG2, field ADHSC[2] (RW)
00601  *
00602  * Configures the ADC for very high-speed operation. The conversion sequence is
00603  * altered with 2 ADCK cycles added to the conversion time to allow higher speed
00604  * conversion clocks.
00605  *
00606  * Values:
00607  * - 0 - Normal conversion sequence selected.
00608  * - 1 - High-speed conversion sequence selected with 2 additional ADCK cycles
00609  *     to total conversion time.
00610  */
00611 /*@{*/
00612 #define BP_ADC_CFG2_ADHSC    (2U)          /*!< Bit position for ADC_CFG2_ADHSC. */
00613 #define BM_ADC_CFG2_ADHSC    (0x00000004U) /*!< Bit mask for ADC_CFG2_ADHSC. */
00614 #define BS_ADC_CFG2_ADHSC    (1U)          /*!< Bit field size in bits for ADC_CFG2_ADHSC. */
00615 
00616 /*! @brief Read current value of the ADC_CFG2_ADHSC field. */
00617 #define BR_ADC_CFG2_ADHSC(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADHSC))
00618 
00619 /*! @brief Format value for bitfield ADC_CFG2_ADHSC. */
00620 #define BF_ADC_CFG2_ADHSC(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_ADHSC) & BM_ADC_CFG2_ADHSC)
00621 
00622 /*! @brief Set the ADHSC field to a new value. */
00623 #define BW_ADC_CFG2_ADHSC(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADHSC) = (v))
00624 /*@}*/
00625 
00626 /*!
00627  * @name Register ADC_CFG2, field ADACKEN[3] (RW)
00628  *
00629  * Enables the asynchronous clock source and the clock source output regardless
00630  * of the conversion and status of CFG1[ADICLK]. Based on MCU configuration, the
00631  * asynchronous clock may be used by other modules. See chip configuration
00632  * information. Setting this field allows the clock to be used even while the ADC is
00633  * idle or operating from a different clock source. Also, latency of initiating a
00634  * single or first-continuous conversion with the asynchronous clock selected is
00635  * reduced because the ADACK clock is already operational.
00636  *
00637  * Values:
00638  * - 0 - Asynchronous clock output disabled; Asynchronous clock is enabled only
00639  *     if selected by ADICLK and a conversion is active.
00640  * - 1 - Asynchronous clock and clock output is enabled regardless of the state
00641  *     of the ADC.
00642  */
00643 /*@{*/
00644 #define BP_ADC_CFG2_ADACKEN  (3U)          /*!< Bit position for ADC_CFG2_ADACKEN. */
00645 #define BM_ADC_CFG2_ADACKEN  (0x00000008U) /*!< Bit mask for ADC_CFG2_ADACKEN. */
00646 #define BS_ADC_CFG2_ADACKEN  (1U)          /*!< Bit field size in bits for ADC_CFG2_ADACKEN. */
00647 
00648 /*! @brief Read current value of the ADC_CFG2_ADACKEN field. */
00649 #define BR_ADC_CFG2_ADACKEN(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADACKEN))
00650 
00651 /*! @brief Format value for bitfield ADC_CFG2_ADACKEN. */
00652 #define BF_ADC_CFG2_ADACKEN(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_ADACKEN) & BM_ADC_CFG2_ADACKEN)
00653 
00654 /*! @brief Set the ADACKEN field to a new value. */
00655 #define BW_ADC_CFG2_ADACKEN(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADACKEN) = (v))
00656 /*@}*/
00657 
00658 /*!
00659  * @name Register ADC_CFG2, field MUXSEL[4] (RW)
00660  *
00661  * Changes the ADC mux setting to select between alternate sets of ADC channels.
00662  *
00663  * Values:
00664  * - 0 - ADxxa channels are selected.
00665  * - 1 - ADxxb channels are selected.
00666  */
00667 /*@{*/
00668 #define BP_ADC_CFG2_MUXSEL   (4U)          /*!< Bit position for ADC_CFG2_MUXSEL. */
00669 #define BM_ADC_CFG2_MUXSEL   (0x00000010U) /*!< Bit mask for ADC_CFG2_MUXSEL. */
00670 #define BS_ADC_CFG2_MUXSEL   (1U)          /*!< Bit field size in bits for ADC_CFG2_MUXSEL. */
00671 
00672 /*! @brief Read current value of the ADC_CFG2_MUXSEL field. */
00673 #define BR_ADC_CFG2_MUXSEL(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_MUXSEL))
00674 
00675 /*! @brief Format value for bitfield ADC_CFG2_MUXSEL. */
00676 #define BF_ADC_CFG2_MUXSEL(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_MUXSEL) & BM_ADC_CFG2_MUXSEL)
00677 
00678 /*! @brief Set the MUXSEL field to a new value. */
00679 #define BW_ADC_CFG2_MUXSEL(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_MUXSEL) = (v))
00680 /*@}*/
00681 
00682 /*******************************************************************************
00683  * HW_ADC_Rn - ADC Data Result Register
00684  ******************************************************************************/
00685 
00686 /*!
00687  * @brief HW_ADC_Rn - ADC Data Result Register (RO)
00688  *
00689  * Reset value: 0x00000000U
00690  *
00691  * The data result registers (Rn) contain the result of an ADC conversion of the
00692  * channel selected by the corresponding status and channel control register
00693  * (SC1A:SC1n). For every status and channel control register, there is a
00694  * corresponding data result register. Unused bits in R n are cleared in unsigned
00695  * right-aligned modes and carry the sign bit (MSB) in sign-extended 2's complement modes.
00696  * For example, when configured for 10-bit single-ended mode, D[15:10] are
00697  * cleared. When configured for 11-bit differential mode, D[15:10] carry the sign bit,
00698  * that is, bit 10 extended through bit 15. The following table describes the
00699  * behavior of the data result registers in the different modes of operation. Data
00700  * result register description Conversion mode D15 D14 D13 D12 D11 D10 D9 D8 D7
00701  * D6 D5 D4 D3 D2 D1 D0 Format 16-bit differential S D D D D D D D D D D D D D D D
00702  * Signed 2's complement 16-bit single-ended D D D D D D D D D D D D D D D D
00703  * Unsigned right justified 13-bit differential S S S S D D D D D D D D D D D D
00704  * Sign-extended 2's complement 12-bit single-ended 0 0 0 0 D D D D D D D D D D D D
00705  * Unsigned right-justified 11-bit differential S S S S S S D D D D D D D D D D
00706  * Sign-extended 2's complement 10-bit single-ended 0 0 0 0 0 0 D D D D D D D D D D
00707  * Unsigned right-justified 9-bit differential S S S S S S S S D D D D D D D D
00708  * Sign-extended 2's complement 8-bit single-ended 0 0 0 0 0 0 0 0 D D D D D D D D
00709  * Unsigned right-justified S: Sign bit or sign bit extension; D: Data, which is
00710  * 2's complement data if indicated
00711  */
00712 typedef union _hw_adc_rn
00713 {
00714     uint32_t U;
00715     struct _hw_adc_rn_bitfields
00716     {
00717         uint32_t D : 16;               /*!< [15:0] Data result */
00718         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00719     } B;
00720 } hw_adc_rn_t;
00721 
00722 /*!
00723  * @name Constants and macros for entire ADC_Rn register
00724  */
00725 /*@{*/
00726 #define HW_ADC_Rn_COUNT (2U)
00727 
00728 #define HW_ADC_Rn_ADDR(x, n)     ((x) + 0x10U + (0x4U * (n)))
00729 
00730 #define HW_ADC_Rn(x, n)          (*(__I hw_adc_rn_t *) HW_ADC_Rn_ADDR(x, n))
00731 #define HW_ADC_Rn_RD(x, n)       (HW_ADC_Rn(x, n).U)
00732 /*@}*/
00733 
00734 /*
00735  * Constants & macros for individual ADC_Rn bitfields
00736  */
00737 
00738 /*!
00739  * @name Register ADC_Rn, field D[15:0] (RO)
00740  */
00741 /*@{*/
00742 #define BP_ADC_Rn_D          (0U)          /*!< Bit position for ADC_Rn_D. */
00743 #define BM_ADC_Rn_D          (0x0000FFFFU) /*!< Bit mask for ADC_Rn_D. */
00744 #define BS_ADC_Rn_D          (16U)         /*!< Bit field size in bits for ADC_Rn_D. */
00745 
00746 /*! @brief Read current value of the ADC_Rn_D field. */
00747 #define BR_ADC_Rn_D(x, n)    (HW_ADC_Rn(x, n).B.D)
00748 /*@}*/
00749 
00750 /*******************************************************************************
00751  * HW_ADC_CV1 - Compare Value Registers
00752  ******************************************************************************/
00753 
00754 /*!
00755  * @brief HW_ADC_CV1 - Compare Value Registers (RW)
00756  *
00757  * Reset value: 0x00000000U
00758  *
00759  * The Compare Value Registers (CV1 and CV2) contain a compare value used to
00760  * compare the conversion result when the compare function is enabled, that is,
00761  * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
00762  * different modes of operation for both bit position definition and value format
00763  * using unsigned or sign-extended 2's complement. Therefore, the compare function
00764  * uses only the CVn fields that are related to the ADC mode of operation. The
00765  * compare value 2 register (CV2) is used only when the compare range function is
00766  * enabled, that is, SC2[ACREN]=1.
00767  */
00768 typedef union _hw_adc_cv1
00769 {
00770     uint32_t U;
00771     struct _hw_adc_cv1_bitfields
00772     {
00773         uint32_t CV : 16;              /*!< [15:0] Compare Value. */
00774         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00775     } B;
00776 } hw_adc_cv1_t;
00777 
00778 /*!
00779  * @name Constants and macros for entire ADC_CV1 register
00780  */
00781 /*@{*/
00782 #define HW_ADC_CV1_ADDR(x)       ((x) + 0x18U)
00783 
00784 #define HW_ADC_CV1(x)            (*(__IO hw_adc_cv1_t *) HW_ADC_CV1_ADDR(x))
00785 #define HW_ADC_CV1_RD(x)         (HW_ADC_CV1(x).U)
00786 #define HW_ADC_CV1_WR(x, v)      (HW_ADC_CV1(x).U = (v))
00787 #define HW_ADC_CV1_SET(x, v)     (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) |  (v)))
00788 #define HW_ADC_CV1_CLR(x, v)     (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) & ~(v)))
00789 #define HW_ADC_CV1_TOG(x, v)     (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) ^  (v)))
00790 /*@}*/
00791 
00792 /*
00793  * Constants & macros for individual ADC_CV1 bitfields
00794  */
00795 
00796 /*!
00797  * @name Register ADC_CV1, field CV[15:0] (RW)
00798  */
00799 /*@{*/
00800 #define BP_ADC_CV1_CV        (0U)          /*!< Bit position for ADC_CV1_CV. */
00801 #define BM_ADC_CV1_CV        (0x0000FFFFU) /*!< Bit mask for ADC_CV1_CV. */
00802 #define BS_ADC_CV1_CV        (16U)         /*!< Bit field size in bits for ADC_CV1_CV. */
00803 
00804 /*! @brief Read current value of the ADC_CV1_CV field. */
00805 #define BR_ADC_CV1_CV(x)     (HW_ADC_CV1(x).B.CV)
00806 
00807 /*! @brief Format value for bitfield ADC_CV1_CV. */
00808 #define BF_ADC_CV1_CV(v)     ((uint32_t)((uint32_t)(v) << BP_ADC_CV1_CV) & BM_ADC_CV1_CV)
00809 
00810 /*! @brief Set the CV field to a new value. */
00811 #define BW_ADC_CV1_CV(x, v)  (HW_ADC_CV1_WR(x, (HW_ADC_CV1_RD(x) & ~BM_ADC_CV1_CV) | BF_ADC_CV1_CV(v)))
00812 /*@}*/
00813 
00814 /*******************************************************************************
00815  * HW_ADC_CV2 - Compare Value Registers
00816  ******************************************************************************/
00817 
00818 /*!
00819  * @brief HW_ADC_CV2 - Compare Value Registers (RW)
00820  *
00821  * Reset value: 0x00000000U
00822  *
00823  * The Compare Value Registers (CV1 and CV2) contain a compare value used to
00824  * compare the conversion result when the compare function is enabled, that is,
00825  * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
00826  * different modes of operation for both bit position definition and value format
00827  * using unsigned or sign-extended 2's complement. Therefore, the compare function
00828  * uses only the CVn fields that are related to the ADC mode of operation. The
00829  * compare value 2 register (CV2) is used only when the compare range function is
00830  * enabled, that is, SC2[ACREN]=1.
00831  */
00832 typedef union _hw_adc_cv2
00833 {
00834     uint32_t U;
00835     struct _hw_adc_cv2_bitfields
00836     {
00837         uint32_t CV : 16;              /*!< [15:0] Compare Value. */
00838         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00839     } B;
00840 } hw_adc_cv2_t;
00841 
00842 /*!
00843  * @name Constants and macros for entire ADC_CV2 register
00844  */
00845 /*@{*/
00846 #define HW_ADC_CV2_ADDR(x)       ((x) + 0x1CU)
00847 
00848 #define HW_ADC_CV2(x)            (*(__IO hw_adc_cv2_t *) HW_ADC_CV2_ADDR(x))
00849 #define HW_ADC_CV2_RD(x)         (HW_ADC_CV2(x).U)
00850 #define HW_ADC_CV2_WR(x, v)      (HW_ADC_CV2(x).U = (v))
00851 #define HW_ADC_CV2_SET(x, v)     (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) |  (v)))
00852 #define HW_ADC_CV2_CLR(x, v)     (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) & ~(v)))
00853 #define HW_ADC_CV2_TOG(x, v)     (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) ^  (v)))
00854 /*@}*/
00855 
00856 /*
00857  * Constants & macros for individual ADC_CV2 bitfields
00858  */
00859 
00860 /*!
00861  * @name Register ADC_CV2, field CV[15:0] (RW)
00862  */
00863 /*@{*/
00864 #define BP_ADC_CV2_CV        (0U)          /*!< Bit position for ADC_CV2_CV. */
00865 #define BM_ADC_CV2_CV        (0x0000FFFFU) /*!< Bit mask for ADC_CV2_CV. */
00866 #define BS_ADC_CV2_CV        (16U)         /*!< Bit field size in bits for ADC_CV2_CV. */
00867 
00868 /*! @brief Read current value of the ADC_CV2_CV field. */
00869 #define BR_ADC_CV2_CV(x)     (HW_ADC_CV2(x).B.CV)
00870 
00871 /*! @brief Format value for bitfield ADC_CV2_CV. */
00872 #define BF_ADC_CV2_CV(v)     ((uint32_t)((uint32_t)(v) << BP_ADC_CV2_CV) & BM_ADC_CV2_CV)
00873 
00874 /*! @brief Set the CV field to a new value. */
00875 #define BW_ADC_CV2_CV(x, v)  (HW_ADC_CV2_WR(x, (HW_ADC_CV2_RD(x) & ~BM_ADC_CV2_CV) | BF_ADC_CV2_CV(v)))
00876 /*@}*/
00877 
00878 /*******************************************************************************
00879  * HW_ADC_SC2 - Status and Control Register 2
00880  ******************************************************************************/
00881 
00882 /*!
00883  * @brief HW_ADC_SC2 - Status and Control Register 2 (RW)
00884  *
00885  * Reset value: 0x00000000U
00886  *
00887  * The status and control register 2 (SC2) contains the conversion active,
00888  * hardware/software trigger select, compare function, and voltage reference select of
00889  * the ADC module.
00890  */
00891 typedef union _hw_adc_sc2
00892 {
00893     uint32_t U;
00894     struct _hw_adc_sc2_bitfields
00895     {
00896         uint32_t REFSEL : 2;           /*!< [1:0] Voltage Reference Selection */
00897         uint32_t DMAEN : 1;            /*!< [2] DMA Enable */
00898         uint32_t ACREN : 1;            /*!< [3] Compare Function Range Enable */
00899         uint32_t ACFGT : 1;            /*!< [4] Compare Function Greater Than Enable */
00900         uint32_t ACFE : 1;             /*!< [5] Compare Function Enable */
00901         uint32_t ADTRG : 1;            /*!< [6] Conversion Trigger Select */
00902         uint32_t ADACT : 1;            /*!< [7] Conversion Active */
00903         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
00904     } B;
00905 } hw_adc_sc2_t;
00906 
00907 /*!
00908  * @name Constants and macros for entire ADC_SC2 register
00909  */
00910 /*@{*/
00911 #define HW_ADC_SC2_ADDR(x)       ((x) + 0x20U)
00912 
00913 #define HW_ADC_SC2(x)            (*(__IO hw_adc_sc2_t *) HW_ADC_SC2_ADDR(x))
00914 #define HW_ADC_SC2_RD(x)         (HW_ADC_SC2(x).U)
00915 #define HW_ADC_SC2_WR(x, v)      (HW_ADC_SC2(x).U = (v))
00916 #define HW_ADC_SC2_SET(x, v)     (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) |  (v)))
00917 #define HW_ADC_SC2_CLR(x, v)     (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) & ~(v)))
00918 #define HW_ADC_SC2_TOG(x, v)     (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) ^  (v)))
00919 /*@}*/
00920 
00921 /*
00922  * Constants & macros for individual ADC_SC2 bitfields
00923  */
00924 
00925 /*!
00926  * @name Register ADC_SC2, field REFSEL[1:0] (RW)
00927  *
00928  * Selects the voltage reference source used for conversions.
00929  *
00930  * Values:
00931  * - 00 - Default voltage reference pin pair, that is, external pins VREFH and
00932  *     VREFL
00933  * - 01 - Alternate reference pair, that is, VALTH and VALTL . This pair may be
00934  *     additional external pins or internal sources depending on the MCU
00935  *     configuration. See the chip configuration information for details specific to this
00936  *     MCU
00937  * - 10 - Reserved
00938  * - 11 - Reserved
00939  */
00940 /*@{*/
00941 #define BP_ADC_SC2_REFSEL    (0U)          /*!< Bit position for ADC_SC2_REFSEL. */
00942 #define BM_ADC_SC2_REFSEL    (0x00000003U) /*!< Bit mask for ADC_SC2_REFSEL. */
00943 #define BS_ADC_SC2_REFSEL    (2U)          /*!< Bit field size in bits for ADC_SC2_REFSEL. */
00944 
00945 /*! @brief Read current value of the ADC_SC2_REFSEL field. */
00946 #define BR_ADC_SC2_REFSEL(x) (HW_ADC_SC2(x).B.REFSEL)
00947 
00948 /*! @brief Format value for bitfield ADC_SC2_REFSEL. */
00949 #define BF_ADC_SC2_REFSEL(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_REFSEL) & BM_ADC_SC2_REFSEL)
00950 
00951 /*! @brief Set the REFSEL field to a new value. */
00952 #define BW_ADC_SC2_REFSEL(x, v) (HW_ADC_SC2_WR(x, (HW_ADC_SC2_RD(x) & ~BM_ADC_SC2_REFSEL) | BF_ADC_SC2_REFSEL(v)))
00953 /*@}*/
00954 
00955 /*!
00956  * @name Register ADC_SC2, field DMAEN[2] (RW)
00957  *
00958  * Values:
00959  * - 0 - DMA is disabled.
00960  * - 1 - DMA is enabled and will assert the ADC DMA request during an ADC
00961  *     conversion complete event noted when any of the SC1n[COCO] flags is asserted.
00962  */
00963 /*@{*/
00964 #define BP_ADC_SC2_DMAEN     (2U)          /*!< Bit position for ADC_SC2_DMAEN. */
00965 #define BM_ADC_SC2_DMAEN     (0x00000004U) /*!< Bit mask for ADC_SC2_DMAEN. */
00966 #define BS_ADC_SC2_DMAEN     (1U)          /*!< Bit field size in bits for ADC_SC2_DMAEN. */
00967 
00968 /*! @brief Read current value of the ADC_SC2_DMAEN field. */
00969 #define BR_ADC_SC2_DMAEN(x)  (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_DMAEN))
00970 
00971 /*! @brief Format value for bitfield ADC_SC2_DMAEN. */
00972 #define BF_ADC_SC2_DMAEN(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_DMAEN) & BM_ADC_SC2_DMAEN)
00973 
00974 /*! @brief Set the DMAEN field to a new value. */
00975 #define BW_ADC_SC2_DMAEN(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_DMAEN) = (v))
00976 /*@}*/
00977 
00978 /*!
00979  * @name Register ADC_SC2, field ACREN[3] (RW)
00980  *
00981  * Configures the compare function to check if the conversion result of the
00982  * input being monitored is either between or outside the range formed by CV1 and CV2
00983  * determined by the value of ACFGT. ACFE must be set for ACFGT to have any
00984  * effect.
00985  *
00986  * Values:
00987  * - 0 - Range function disabled. Only CV1 is compared.
00988  * - 1 - Range function enabled. Both CV1 and CV2 are compared.
00989  */
00990 /*@{*/
00991 #define BP_ADC_SC2_ACREN     (3U)          /*!< Bit position for ADC_SC2_ACREN. */
00992 #define BM_ADC_SC2_ACREN     (0x00000008U) /*!< Bit mask for ADC_SC2_ACREN. */
00993 #define BS_ADC_SC2_ACREN     (1U)          /*!< Bit field size in bits for ADC_SC2_ACREN. */
00994 
00995 /*! @brief Read current value of the ADC_SC2_ACREN field. */
00996 #define BR_ADC_SC2_ACREN(x)  (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACREN))
00997 
00998 /*! @brief Format value for bitfield ADC_SC2_ACREN. */
00999 #define BF_ADC_SC2_ACREN(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ACREN) & BM_ADC_SC2_ACREN)
01000 
01001 /*! @brief Set the ACREN field to a new value. */
01002 #define BW_ADC_SC2_ACREN(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACREN) = (v))
01003 /*@}*/
01004 
01005 /*!
01006  * @name Register ADC_SC2, field ACFGT[4] (RW)
01007  *
01008  * Configures the compare function to check the conversion result relative to
01009  * the CV1 and CV2 based upon the value of ACREN. ACFE must be set for ACFGT to
01010  * have any effect.
01011  *
01012  * Values:
01013  * - 0 - Configures less than threshold, outside range not inclusive and inside
01014  *     range not inclusive; functionality based on the values placed in CV1 and
01015  *     CV2.
01016  * - 1 - Configures greater than or equal to threshold, outside and inside
01017  *     ranges inclusive; functionality based on the values placed in CV1 and CV2.
01018  */
01019 /*@{*/
01020 #define BP_ADC_SC2_ACFGT     (4U)          /*!< Bit position for ADC_SC2_ACFGT. */
01021 #define BM_ADC_SC2_ACFGT     (0x00000010U) /*!< Bit mask for ADC_SC2_ACFGT. */
01022 #define BS_ADC_SC2_ACFGT     (1U)          /*!< Bit field size in bits for ADC_SC2_ACFGT. */
01023 
01024 /*! @brief Read current value of the ADC_SC2_ACFGT field. */
01025 #define BR_ADC_SC2_ACFGT(x)  (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFGT))
01026 
01027 /*! @brief Format value for bitfield ADC_SC2_ACFGT. */
01028 #define BF_ADC_SC2_ACFGT(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ACFGT) & BM_ADC_SC2_ACFGT)
01029 
01030 /*! @brief Set the ACFGT field to a new value. */
01031 #define BW_ADC_SC2_ACFGT(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFGT) = (v))
01032 /*@}*/
01033 
01034 /*!
01035  * @name Register ADC_SC2, field ACFE[5] (RW)
01036  *
01037  * Enables the compare function.
01038  *
01039  * Values:
01040  * - 0 - Compare function disabled.
01041  * - 1 - Compare function enabled.
01042  */
01043 /*@{*/
01044 #define BP_ADC_SC2_ACFE      (5U)          /*!< Bit position for ADC_SC2_ACFE. */
01045 #define BM_ADC_SC2_ACFE      (0x00000020U) /*!< Bit mask for ADC_SC2_ACFE. */
01046 #define BS_ADC_SC2_ACFE      (1U)          /*!< Bit field size in bits for ADC_SC2_ACFE. */
01047 
01048 /*! @brief Read current value of the ADC_SC2_ACFE field. */
01049 #define BR_ADC_SC2_ACFE(x)   (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFE))
01050 
01051 /*! @brief Format value for bitfield ADC_SC2_ACFE. */
01052 #define BF_ADC_SC2_ACFE(v)   ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ACFE) & BM_ADC_SC2_ACFE)
01053 
01054 /*! @brief Set the ACFE field to a new value. */
01055 #define BW_ADC_SC2_ACFE(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFE) = (v))
01056 /*@}*/
01057 
01058 /*!
01059  * @name Register ADC_SC2, field ADTRG[6] (RW)
01060  *
01061  * Selects the type of trigger used for initiating a conversion. Two types of
01062  * trigger are selectable: Software trigger: When software trigger is selected, a
01063  * conversion is initiated following a write to SC1A. Hardware trigger: When
01064  * hardware trigger is selected, a conversion is initiated following the assertion of
01065  * the ADHWT input after a pulse of the ADHWTSn input.
01066  *
01067  * Values:
01068  * - 0 - Software trigger selected.
01069  * - 1 - Hardware trigger selected.
01070  */
01071 /*@{*/
01072 #define BP_ADC_SC2_ADTRG     (6U)          /*!< Bit position for ADC_SC2_ADTRG. */
01073 #define BM_ADC_SC2_ADTRG     (0x00000040U) /*!< Bit mask for ADC_SC2_ADTRG. */
01074 #define BS_ADC_SC2_ADTRG     (1U)          /*!< Bit field size in bits for ADC_SC2_ADTRG. */
01075 
01076 /*! @brief Read current value of the ADC_SC2_ADTRG field. */
01077 #define BR_ADC_SC2_ADTRG(x)  (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADTRG))
01078 
01079 /*! @brief Format value for bitfield ADC_SC2_ADTRG. */
01080 #define BF_ADC_SC2_ADTRG(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ADTRG) & BM_ADC_SC2_ADTRG)
01081 
01082 /*! @brief Set the ADTRG field to a new value. */
01083 #define BW_ADC_SC2_ADTRG(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADTRG) = (v))
01084 /*@}*/
01085 
01086 /*!
01087  * @name Register ADC_SC2, field ADACT[7] (RO)
01088  *
01089  * Indicates that a conversion or hardware averaging is in progress. ADACT is
01090  * set when a conversion is initiated and cleared when a conversion is completed or
01091  * aborted.
01092  *
01093  * Values:
01094  * - 0 - Conversion not in progress.
01095  * - 1 - Conversion in progress.
01096  */
01097 /*@{*/
01098 #define BP_ADC_SC2_ADACT     (7U)          /*!< Bit position for ADC_SC2_ADACT. */
01099 #define BM_ADC_SC2_ADACT     (0x00000080U) /*!< Bit mask for ADC_SC2_ADACT. */
01100 #define BS_ADC_SC2_ADACT     (1U)          /*!< Bit field size in bits for ADC_SC2_ADACT. */
01101 
01102 /*! @brief Read current value of the ADC_SC2_ADACT field. */
01103 #define BR_ADC_SC2_ADACT(x)  (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADACT))
01104 /*@}*/
01105 
01106 /*******************************************************************************
01107  * HW_ADC_SC3 - Status and Control Register 3
01108  ******************************************************************************/
01109 
01110 /*!
01111  * @brief HW_ADC_SC3 - Status and Control Register 3 (RW)
01112  *
01113  * Reset value: 0x00000000U
01114  *
01115  * The Status and Control Register 3 (SC3) controls the calibration, continuous
01116  * convert, and hardware averaging functions of the ADC module.
01117  */
01118 typedef union _hw_adc_sc3
01119 {
01120     uint32_t U;
01121     struct _hw_adc_sc3_bitfields
01122     {
01123         uint32_t AVGS : 2;             /*!< [1:0] Hardware Average Select */
01124         uint32_t AVGE : 1;             /*!< [2] Hardware Average Enable */
01125         uint32_t ADCO : 1;             /*!< [3] Continuous Conversion Enable */
01126         uint32_t RESERVED0 : 2;        /*!< [5:4]  */
01127         uint32_t CALF : 1;             /*!< [6] Calibration Failed Flag */
01128         uint32_t CAL : 1;              /*!< [7] Calibration */
01129         uint32_t RESERVED1 : 24;       /*!< [31:8]  */
01130     } B;
01131 } hw_adc_sc3_t;
01132 
01133 /*!
01134  * @name Constants and macros for entire ADC_SC3 register
01135  */
01136 /*@{*/
01137 #define HW_ADC_SC3_ADDR(x)       ((x) + 0x24U)
01138 
01139 #define HW_ADC_SC3(x)            (*(__IO hw_adc_sc3_t *) HW_ADC_SC3_ADDR(x))
01140 #define HW_ADC_SC3_RD(x)         (HW_ADC_SC3(x).U)
01141 #define HW_ADC_SC3_WR(x, v)      (HW_ADC_SC3(x).U = (v))
01142 #define HW_ADC_SC3_SET(x, v)     (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) |  (v)))
01143 #define HW_ADC_SC3_CLR(x, v)     (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) & ~(v)))
01144 #define HW_ADC_SC3_TOG(x, v)     (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) ^  (v)))
01145 /*@}*/
01146 
01147 /*
01148  * Constants & macros for individual ADC_SC3 bitfields
01149  */
01150 
01151 /*!
01152  * @name Register ADC_SC3, field AVGS[1:0] (RW)
01153  *
01154  * Determines how many ADC conversions will be averaged to create the ADC
01155  * average result.
01156  *
01157  * Values:
01158  * - 00 - 4 samples averaged.
01159  * - 01 - 8 samples averaged.
01160  * - 10 - 16 samples averaged.
01161  * - 11 - 32 samples averaged.
01162  */
01163 /*@{*/
01164 #define BP_ADC_SC3_AVGS      (0U)          /*!< Bit position for ADC_SC3_AVGS. */
01165 #define BM_ADC_SC3_AVGS      (0x00000003U) /*!< Bit mask for ADC_SC3_AVGS. */
01166 #define BS_ADC_SC3_AVGS      (2U)          /*!< Bit field size in bits for ADC_SC3_AVGS. */
01167 
01168 /*! @brief Read current value of the ADC_SC3_AVGS field. */
01169 #define BR_ADC_SC3_AVGS(x)   (HW_ADC_SC3(x).B.AVGS)
01170 
01171 /*! @brief Format value for bitfield ADC_SC3_AVGS. */
01172 #define BF_ADC_SC3_AVGS(v)   ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_AVGS) & BM_ADC_SC3_AVGS)
01173 
01174 /*! @brief Set the AVGS field to a new value. */
01175 #define BW_ADC_SC3_AVGS(x, v) (HW_ADC_SC3_WR(x, (HW_ADC_SC3_RD(x) & ~BM_ADC_SC3_AVGS) | BF_ADC_SC3_AVGS(v)))
01176 /*@}*/
01177 
01178 /*!
01179  * @name Register ADC_SC3, field AVGE[2] (RW)
01180  *
01181  * Enables the hardware average function of the ADC.
01182  *
01183  * Values:
01184  * - 0 - Hardware average function disabled.
01185  * - 1 - Hardware average function enabled.
01186  */
01187 /*@{*/
01188 #define BP_ADC_SC3_AVGE      (2U)          /*!< Bit position for ADC_SC3_AVGE. */
01189 #define BM_ADC_SC3_AVGE      (0x00000004U) /*!< Bit mask for ADC_SC3_AVGE. */
01190 #define BS_ADC_SC3_AVGE      (1U)          /*!< Bit field size in bits for ADC_SC3_AVGE. */
01191 
01192 /*! @brief Read current value of the ADC_SC3_AVGE field. */
01193 #define BR_ADC_SC3_AVGE(x)   (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_AVGE))
01194 
01195 /*! @brief Format value for bitfield ADC_SC3_AVGE. */
01196 #define BF_ADC_SC3_AVGE(v)   ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_AVGE) & BM_ADC_SC3_AVGE)
01197 
01198 /*! @brief Set the AVGE field to a new value. */
01199 #define BW_ADC_SC3_AVGE(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_AVGE) = (v))
01200 /*@}*/
01201 
01202 /*!
01203  * @name Register ADC_SC3, field ADCO[3] (RW)
01204  *
01205  * Enables continuous conversions.
01206  *
01207  * Values:
01208  * - 0 - One conversion or one set of conversions if the hardware average
01209  *     function is enabled, that is, AVGE=1, after initiating a conversion.
01210  * - 1 - Continuous conversions or sets of conversions if the hardware average
01211  *     function is enabled, that is, AVGE=1, after initiating a conversion.
01212  */
01213 /*@{*/
01214 #define BP_ADC_SC3_ADCO      (3U)          /*!< Bit position for ADC_SC3_ADCO. */
01215 #define BM_ADC_SC3_ADCO      (0x00000008U) /*!< Bit mask for ADC_SC3_ADCO. */
01216 #define BS_ADC_SC3_ADCO      (1U)          /*!< Bit field size in bits for ADC_SC3_ADCO. */
01217 
01218 /*! @brief Read current value of the ADC_SC3_ADCO field. */
01219 #define BR_ADC_SC3_ADCO(x)   (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_ADCO))
01220 
01221 /*! @brief Format value for bitfield ADC_SC3_ADCO. */
01222 #define BF_ADC_SC3_ADCO(v)   ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_ADCO) & BM_ADC_SC3_ADCO)
01223 
01224 /*! @brief Set the ADCO field to a new value. */
01225 #define BW_ADC_SC3_ADCO(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_ADCO) = (v))
01226 /*@}*/
01227 
01228 /*!
01229  * @name Register ADC_SC3, field CALF[6] (RO)
01230  *
01231  * Displays the result of the calibration sequence. The calibration sequence
01232  * will fail if SC2[ADTRG] = 1, any ADC register is written, or any stop mode is
01233  * entered before the calibration sequence completes. Writing 1 to CALF clears it.
01234  *
01235  * Values:
01236  * - 0 - Calibration completed normally.
01237  * - 1 - Calibration failed. ADC accuracy specifications are not guaranteed.
01238  */
01239 /*@{*/
01240 #define BP_ADC_SC3_CALF      (6U)          /*!< Bit position for ADC_SC3_CALF. */
01241 #define BM_ADC_SC3_CALF      (0x00000040U) /*!< Bit mask for ADC_SC3_CALF. */
01242 #define BS_ADC_SC3_CALF      (1U)          /*!< Bit field size in bits for ADC_SC3_CALF. */
01243 
01244 /*! @brief Read current value of the ADC_SC3_CALF field. */
01245 #define BR_ADC_SC3_CALF(x)   (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CALF))
01246 /*@}*/
01247 
01248 /*!
01249  * @name Register ADC_SC3, field CAL[7] (RW)
01250  *
01251  * Begins the calibration sequence when set. This field stays set while the
01252  * calibration is in progress and is cleared when the calibration sequence is
01253  * completed. CALF must be checked to determine the result of the calibration sequence.
01254  * Once started, the calibration routine cannot be interrupted by writes to the
01255  * ADC registers or the results will be invalid and CALF will set. Setting CAL
01256  * will abort any current conversion.
01257  */
01258 /*@{*/
01259 #define BP_ADC_SC3_CAL       (7U)          /*!< Bit position for ADC_SC3_CAL. */
01260 #define BM_ADC_SC3_CAL       (0x00000080U) /*!< Bit mask for ADC_SC3_CAL. */
01261 #define BS_ADC_SC3_CAL       (1U)          /*!< Bit field size in bits for ADC_SC3_CAL. */
01262 
01263 /*! @brief Read current value of the ADC_SC3_CAL field. */
01264 #define BR_ADC_SC3_CAL(x)    (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CAL))
01265 
01266 /*! @brief Format value for bitfield ADC_SC3_CAL. */
01267 #define BF_ADC_SC3_CAL(v)    ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_CAL) & BM_ADC_SC3_CAL)
01268 
01269 /*! @brief Set the CAL field to a new value. */
01270 #define BW_ADC_SC3_CAL(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CAL) = (v))
01271 /*@}*/
01272 
01273 /*******************************************************************************
01274  * HW_ADC_OFS - ADC Offset Correction Register
01275  ******************************************************************************/
01276 
01277 /*!
01278  * @brief HW_ADC_OFS - ADC Offset Correction Register (RW)
01279  *
01280  * Reset value: 0x00000004U
01281  *
01282  * The ADC Offset Correction Register (OFS) contains the user-selected or
01283  * calibration-generated offset error correction value. This register is a 2's
01284  * complement, left-justified, 16-bit value . The value in OFS is subtracted from the
01285  * conversion and the result is transferred into the result registers, Rn. If the
01286  * result is greater than the maximum or less than the minimum result value, it is
01287  * forced to the appropriate limit for the current mode of operation.
01288  */
01289 typedef union _hw_adc_ofs
01290 {
01291     uint32_t U;
01292     struct _hw_adc_ofs_bitfields
01293     {
01294         uint32_t OFS : 16;             /*!< [15:0] Offset Error Correction Value */
01295         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
01296     } B;
01297 } hw_adc_ofs_t;
01298 
01299 /*!
01300  * @name Constants and macros for entire ADC_OFS register
01301  */
01302 /*@{*/
01303 #define HW_ADC_OFS_ADDR(x)       ((x) + 0x28U)
01304 
01305 #define HW_ADC_OFS(x)            (*(__IO hw_adc_ofs_t *) HW_ADC_OFS_ADDR(x))
01306 #define HW_ADC_OFS_RD(x)         (HW_ADC_OFS(x).U)
01307 #define HW_ADC_OFS_WR(x, v)      (HW_ADC_OFS(x).U = (v))
01308 #define HW_ADC_OFS_SET(x, v)     (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) |  (v)))
01309 #define HW_ADC_OFS_CLR(x, v)     (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) & ~(v)))
01310 #define HW_ADC_OFS_TOG(x, v)     (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) ^  (v)))
01311 /*@}*/
01312 
01313 /*
01314  * Constants & macros for individual ADC_OFS bitfields
01315  */
01316 
01317 /*!
01318  * @name Register ADC_OFS, field OFS[15:0] (RW)
01319  */
01320 /*@{*/
01321 #define BP_ADC_OFS_OFS       (0U)          /*!< Bit position for ADC_OFS_OFS. */
01322 #define BM_ADC_OFS_OFS       (0x0000FFFFU) /*!< Bit mask for ADC_OFS_OFS. */
01323 #define BS_ADC_OFS_OFS       (16U)         /*!< Bit field size in bits for ADC_OFS_OFS. */
01324 
01325 /*! @brief Read current value of the ADC_OFS_OFS field. */
01326 #define BR_ADC_OFS_OFS(x)    (HW_ADC_OFS(x).B.OFS)
01327 
01328 /*! @brief Format value for bitfield ADC_OFS_OFS. */
01329 #define BF_ADC_OFS_OFS(v)    ((uint32_t)((uint32_t)(v) << BP_ADC_OFS_OFS) & BM_ADC_OFS_OFS)
01330 
01331 /*! @brief Set the OFS field to a new value. */
01332 #define BW_ADC_OFS_OFS(x, v) (HW_ADC_OFS_WR(x, (HW_ADC_OFS_RD(x) & ~BM_ADC_OFS_OFS) | BF_ADC_OFS_OFS(v)))
01333 /*@}*/
01334 
01335 /*******************************************************************************
01336  * HW_ADC_PG - ADC Plus-Side Gain Register
01337  ******************************************************************************/
01338 
01339 /*!
01340  * @brief HW_ADC_PG - ADC Plus-Side Gain Register (RW)
01341  *
01342  * Reset value: 0x00008200U
01343  *
01344  * The Plus-Side Gain Register (PG) contains the gain error correction for the
01345  * plus-side input in differential mode or the overall conversion in single-ended
01346  * mode. PG, a 16-bit real number in binary format, is the gain adjustment
01347  * factor, with the radix point fixed between ADPG15 and ADPG14. This register must be
01348  * written by the user with the value described in the calibration procedure.
01349  * Otherwise, the gain error specifications may not be met.
01350  */
01351 typedef union _hw_adc_pg
01352 {
01353     uint32_t U;
01354     struct _hw_adc_pg_bitfields
01355     {
01356         uint32_t PG : 16;              /*!< [15:0] Plus-Side Gain */
01357         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
01358     } B;
01359 } hw_adc_pg_t;
01360 
01361 /*!
01362  * @name Constants and macros for entire ADC_PG register
01363  */
01364 /*@{*/
01365 #define HW_ADC_PG_ADDR(x)        ((x) + 0x2CU)
01366 
01367 #define HW_ADC_PG(x)             (*(__IO hw_adc_pg_t *) HW_ADC_PG_ADDR(x))
01368 #define HW_ADC_PG_RD(x)          (HW_ADC_PG(x).U)
01369 #define HW_ADC_PG_WR(x, v)       (HW_ADC_PG(x).U = (v))
01370 #define HW_ADC_PG_SET(x, v)      (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) |  (v)))
01371 #define HW_ADC_PG_CLR(x, v)      (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) & ~(v)))
01372 #define HW_ADC_PG_TOG(x, v)      (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) ^  (v)))
01373 /*@}*/
01374 
01375 /*
01376  * Constants & macros for individual ADC_PG bitfields
01377  */
01378 
01379 /*!
01380  * @name Register ADC_PG, field PG[15:0] (RW)
01381  */
01382 /*@{*/
01383 #define BP_ADC_PG_PG         (0U)          /*!< Bit position for ADC_PG_PG. */
01384 #define BM_ADC_PG_PG         (0x0000FFFFU) /*!< Bit mask for ADC_PG_PG. */
01385 #define BS_ADC_PG_PG         (16U)         /*!< Bit field size in bits for ADC_PG_PG. */
01386 
01387 /*! @brief Read current value of the ADC_PG_PG field. */
01388 #define BR_ADC_PG_PG(x)      (HW_ADC_PG(x).B.PG)
01389 
01390 /*! @brief Format value for bitfield ADC_PG_PG. */
01391 #define BF_ADC_PG_PG(v)      ((uint32_t)((uint32_t)(v) << BP_ADC_PG_PG) & BM_ADC_PG_PG)
01392 
01393 /*! @brief Set the PG field to a new value. */
01394 #define BW_ADC_PG_PG(x, v)   (HW_ADC_PG_WR(x, (HW_ADC_PG_RD(x) & ~BM_ADC_PG_PG) | BF_ADC_PG_PG(v)))
01395 /*@}*/
01396 
01397 /*******************************************************************************
01398  * HW_ADC_MG - ADC Minus-Side Gain Register
01399  ******************************************************************************/
01400 
01401 /*!
01402  * @brief HW_ADC_MG - ADC Minus-Side Gain Register (RW)
01403  *
01404  * Reset value: 0x00008200U
01405  *
01406  * The Minus-Side Gain Register (MG) contains the gain error correction for the
01407  * minus-side input in differential mode. This register is ignored in
01408  * single-ended mode. MG, a 16-bit real number in binary format, is the gain adjustment
01409  * factor, with the radix point fixed between ADMG15 and ADMG14. This register must
01410  * be written by the user with the value described in the calibration procedure.
01411  * Otherwise, the gain error specifications may not be met.
01412  */
01413 typedef union _hw_adc_mg
01414 {
01415     uint32_t U;
01416     struct _hw_adc_mg_bitfields
01417     {
01418         uint32_t MG : 16;              /*!< [15:0] Minus-Side Gain */
01419         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
01420     } B;
01421 } hw_adc_mg_t;
01422 
01423 /*!
01424  * @name Constants and macros for entire ADC_MG register
01425  */
01426 /*@{*/
01427 #define HW_ADC_MG_ADDR(x)        ((x) + 0x30U)
01428 
01429 #define HW_ADC_MG(x)             (*(__IO hw_adc_mg_t *) HW_ADC_MG_ADDR(x))
01430 #define HW_ADC_MG_RD(x)          (HW_ADC_MG(x).U)
01431 #define HW_ADC_MG_WR(x, v)       (HW_ADC_MG(x).U = (v))
01432 #define HW_ADC_MG_SET(x, v)      (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) |  (v)))
01433 #define HW_ADC_MG_CLR(x, v)      (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) & ~(v)))
01434 #define HW_ADC_MG_TOG(x, v)      (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) ^  (v)))
01435 /*@}*/
01436 
01437 /*
01438  * Constants & macros for individual ADC_MG bitfields
01439  */
01440 
01441 /*!
01442  * @name Register ADC_MG, field MG[15:0] (RW)
01443  */
01444 /*@{*/
01445 #define BP_ADC_MG_MG         (0U)          /*!< Bit position for ADC_MG_MG. */
01446 #define BM_ADC_MG_MG         (0x0000FFFFU) /*!< Bit mask for ADC_MG_MG. */
01447 #define BS_ADC_MG_MG         (16U)         /*!< Bit field size in bits for ADC_MG_MG. */
01448 
01449 /*! @brief Read current value of the ADC_MG_MG field. */
01450 #define BR_ADC_MG_MG(x)      (HW_ADC_MG(x).B.MG)
01451 
01452 /*! @brief Format value for bitfield ADC_MG_MG. */
01453 #define BF_ADC_MG_MG(v)      ((uint32_t)((uint32_t)(v) << BP_ADC_MG_MG) & BM_ADC_MG_MG)
01454 
01455 /*! @brief Set the MG field to a new value. */
01456 #define BW_ADC_MG_MG(x, v)   (HW_ADC_MG_WR(x, (HW_ADC_MG_RD(x) & ~BM_ADC_MG_MG) | BF_ADC_MG_MG(v)))
01457 /*@}*/
01458 
01459 /*******************************************************************************
01460  * HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register
01461  ******************************************************************************/
01462 
01463 /*!
01464  * @brief HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register (RW)
01465  *
01466  * Reset value: 0x0000000AU
01467  *
01468  * The Plus-Side General Calibration Value Registers (CLPx) contain calibration
01469  * information that is generated by the calibration function. These registers
01470  * contain seven calibration values of varying widths: CLP0[5:0], CLP1[6:0],
01471  * CLP2[7:0], CLP3[8:0], CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set
01472  * when the self-calibration sequence is done, that is, CAL is cleared. If these
01473  * registers are written by the user after calibration, the linearity error
01474  * specifications may not be met.
01475  */
01476 typedef union _hw_adc_clpd
01477 {
01478     uint32_t U;
01479     struct _hw_adc_clpd_bitfields
01480     {
01481         uint32_t CLPD : 6;             /*!< [5:0]  */
01482         uint32_t RESERVED0 : 26;       /*!< [31:6]  */
01483     } B;
01484 } hw_adc_clpd_t;
01485 
01486 /*!
01487  * @name Constants and macros for entire ADC_CLPD register
01488  */
01489 /*@{*/
01490 #define HW_ADC_CLPD_ADDR(x)      ((x) + 0x34U)
01491 
01492 #define HW_ADC_CLPD(x)           (*(__IO hw_adc_clpd_t *) HW_ADC_CLPD_ADDR(x))
01493 #define HW_ADC_CLPD_RD(x)        (HW_ADC_CLPD(x).U)
01494 #define HW_ADC_CLPD_WR(x, v)     (HW_ADC_CLPD(x).U = (v))
01495 #define HW_ADC_CLPD_SET(x, v)    (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) |  (v)))
01496 #define HW_ADC_CLPD_CLR(x, v)    (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) & ~(v)))
01497 #define HW_ADC_CLPD_TOG(x, v)    (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) ^  (v)))
01498 /*@}*/
01499 
01500 /*
01501  * Constants & macros for individual ADC_CLPD bitfields
01502  */
01503 
01504 /*!
01505  * @name Register ADC_CLPD, field CLPD[5:0] (RW)
01506  *
01507  * Calibration Value
01508  */
01509 /*@{*/
01510 #define BP_ADC_CLPD_CLPD     (0U)          /*!< Bit position for ADC_CLPD_CLPD. */
01511 #define BM_ADC_CLPD_CLPD     (0x0000003FU) /*!< Bit mask for ADC_CLPD_CLPD. */
01512 #define BS_ADC_CLPD_CLPD     (6U)          /*!< Bit field size in bits for ADC_CLPD_CLPD. */
01513 
01514 /*! @brief Read current value of the ADC_CLPD_CLPD field. */
01515 #define BR_ADC_CLPD_CLPD(x)  (HW_ADC_CLPD(x).B.CLPD)
01516 
01517 /*! @brief Format value for bitfield ADC_CLPD_CLPD. */
01518 #define BF_ADC_CLPD_CLPD(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLPD_CLPD) & BM_ADC_CLPD_CLPD)
01519 
01520 /*! @brief Set the CLPD field to a new value. */
01521 #define BW_ADC_CLPD_CLPD(x, v) (HW_ADC_CLPD_WR(x, (HW_ADC_CLPD_RD(x) & ~BM_ADC_CLPD_CLPD) | BF_ADC_CLPD_CLPD(v)))
01522 /*@}*/
01523 
01524 /*******************************************************************************
01525  * HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register
01526  ******************************************************************************/
01527 
01528 /*!
01529  * @brief HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register (RW)
01530  *
01531  * Reset value: 0x00000020U
01532  *
01533  * For more information, see CLPD register description.
01534  */
01535 typedef union _hw_adc_clps
01536 {
01537     uint32_t U;
01538     struct _hw_adc_clps_bitfields
01539     {
01540         uint32_t CLPS : 6;             /*!< [5:0]  */
01541         uint32_t RESERVED0 : 26;       /*!< [31:6]  */
01542     } B;
01543 } hw_adc_clps_t;
01544 
01545 /*!
01546  * @name Constants and macros for entire ADC_CLPS register
01547  */
01548 /*@{*/
01549 #define HW_ADC_CLPS_ADDR(x)      ((x) + 0x38U)
01550 
01551 #define HW_ADC_CLPS(x)           (*(__IO hw_adc_clps_t *) HW_ADC_CLPS_ADDR(x))
01552 #define HW_ADC_CLPS_RD(x)        (HW_ADC_CLPS(x).U)
01553 #define HW_ADC_CLPS_WR(x, v)     (HW_ADC_CLPS(x).U = (v))
01554 #define HW_ADC_CLPS_SET(x, v)    (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) |  (v)))
01555 #define HW_ADC_CLPS_CLR(x, v)    (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) & ~(v)))
01556 #define HW_ADC_CLPS_TOG(x, v)    (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) ^  (v)))
01557 /*@}*/
01558 
01559 /*
01560  * Constants & macros for individual ADC_CLPS bitfields
01561  */
01562 
01563 /*!
01564  * @name Register ADC_CLPS, field CLPS[5:0] (RW)
01565  *
01566  * Calibration Value
01567  */
01568 /*@{*/
01569 #define BP_ADC_CLPS_CLPS     (0U)          /*!< Bit position for ADC_CLPS_CLPS. */
01570 #define BM_ADC_CLPS_CLPS     (0x0000003FU) /*!< Bit mask for ADC_CLPS_CLPS. */
01571 #define BS_ADC_CLPS_CLPS     (6U)          /*!< Bit field size in bits for ADC_CLPS_CLPS. */
01572 
01573 /*! @brief Read current value of the ADC_CLPS_CLPS field. */
01574 #define BR_ADC_CLPS_CLPS(x)  (HW_ADC_CLPS(x).B.CLPS)
01575 
01576 /*! @brief Format value for bitfield ADC_CLPS_CLPS. */
01577 #define BF_ADC_CLPS_CLPS(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLPS_CLPS) & BM_ADC_CLPS_CLPS)
01578 
01579 /*! @brief Set the CLPS field to a new value. */
01580 #define BW_ADC_CLPS_CLPS(x, v) (HW_ADC_CLPS_WR(x, (HW_ADC_CLPS_RD(x) & ~BM_ADC_CLPS_CLPS) | BF_ADC_CLPS_CLPS(v)))
01581 /*@}*/
01582 
01583 /*******************************************************************************
01584  * HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register
01585  ******************************************************************************/
01586 
01587 /*!
01588  * @brief HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register (RW)
01589  *
01590  * Reset value: 0x00000200U
01591  *
01592  * For more information, see CLPD register description.
01593  */
01594 typedef union _hw_adc_clp4
01595 {
01596     uint32_t U;
01597     struct _hw_adc_clp4_bitfields
01598     {
01599         uint32_t CLP4 : 10;            /*!< [9:0]  */
01600         uint32_t RESERVED0 : 22;       /*!< [31:10]  */
01601     } B;
01602 } hw_adc_clp4_t;
01603 
01604 /*!
01605  * @name Constants and macros for entire ADC_CLP4 register
01606  */
01607 /*@{*/
01608 #define HW_ADC_CLP4_ADDR(x)      ((x) + 0x3CU)
01609 
01610 #define HW_ADC_CLP4(x)           (*(__IO hw_adc_clp4_t *) HW_ADC_CLP4_ADDR(x))
01611 #define HW_ADC_CLP4_RD(x)        (HW_ADC_CLP4(x).U)
01612 #define HW_ADC_CLP4_WR(x, v)     (HW_ADC_CLP4(x).U = (v))
01613 #define HW_ADC_CLP4_SET(x, v)    (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) |  (v)))
01614 #define HW_ADC_CLP4_CLR(x, v)    (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) & ~(v)))
01615 #define HW_ADC_CLP4_TOG(x, v)    (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) ^  (v)))
01616 /*@}*/
01617 
01618 /*
01619  * Constants & macros for individual ADC_CLP4 bitfields
01620  */
01621 
01622 /*!
01623  * @name Register ADC_CLP4, field CLP4[9:0] (RW)
01624  *
01625  * Calibration Value
01626  */
01627 /*@{*/
01628 #define BP_ADC_CLP4_CLP4     (0U)          /*!< Bit position for ADC_CLP4_CLP4. */
01629 #define BM_ADC_CLP4_CLP4     (0x000003FFU) /*!< Bit mask for ADC_CLP4_CLP4. */
01630 #define BS_ADC_CLP4_CLP4     (10U)         /*!< Bit field size in bits for ADC_CLP4_CLP4. */
01631 
01632 /*! @brief Read current value of the ADC_CLP4_CLP4 field. */
01633 #define BR_ADC_CLP4_CLP4(x)  (HW_ADC_CLP4(x).B.CLP4)
01634 
01635 /*! @brief Format value for bitfield ADC_CLP4_CLP4. */
01636 #define BF_ADC_CLP4_CLP4(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLP4_CLP4) & BM_ADC_CLP4_CLP4)
01637 
01638 /*! @brief Set the CLP4 field to a new value. */
01639 #define BW_ADC_CLP4_CLP4(x, v) (HW_ADC_CLP4_WR(x, (HW_ADC_CLP4_RD(x) & ~BM_ADC_CLP4_CLP4) | BF_ADC_CLP4_CLP4(v)))
01640 /*@}*/
01641 
01642 /*******************************************************************************
01643  * HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register
01644  ******************************************************************************/
01645 
01646 /*!
01647  * @brief HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register (RW)
01648  *
01649  * Reset value: 0x00000100U
01650  *
01651  * For more information, see CLPD register description.
01652  */
01653 typedef union _hw_adc_clp3
01654 {
01655     uint32_t U;
01656     struct _hw_adc_clp3_bitfields
01657     {
01658         uint32_t CLP3 : 9;             /*!< [8:0]  */
01659         uint32_t RESERVED0 : 23;       /*!< [31:9]  */
01660     } B;
01661 } hw_adc_clp3_t;
01662 
01663 /*!
01664  * @name Constants and macros for entire ADC_CLP3 register
01665  */
01666 /*@{*/
01667 #define HW_ADC_CLP3_ADDR(x)      ((x) + 0x40U)
01668 
01669 #define HW_ADC_CLP3(x)           (*(__IO hw_adc_clp3_t *) HW_ADC_CLP3_ADDR(x))
01670 #define HW_ADC_CLP3_RD(x)        (HW_ADC_CLP3(x).U)
01671 #define HW_ADC_CLP3_WR(x, v)     (HW_ADC_CLP3(x).U = (v))
01672 #define HW_ADC_CLP3_SET(x, v)    (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) |  (v)))
01673 #define HW_ADC_CLP3_CLR(x, v)    (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) & ~(v)))
01674 #define HW_ADC_CLP3_TOG(x, v)    (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) ^  (v)))
01675 /*@}*/
01676 
01677 /*
01678  * Constants & macros for individual ADC_CLP3 bitfields
01679  */
01680 
01681 /*!
01682  * @name Register ADC_CLP3, field CLP3[8:0] (RW)
01683  *
01684  * Calibration Value
01685  */
01686 /*@{*/
01687 #define BP_ADC_CLP3_CLP3     (0U)          /*!< Bit position for ADC_CLP3_CLP3. */
01688 #define BM_ADC_CLP3_CLP3     (0x000001FFU) /*!< Bit mask for ADC_CLP3_CLP3. */
01689 #define BS_ADC_CLP3_CLP3     (9U)          /*!< Bit field size in bits for ADC_CLP3_CLP3. */
01690 
01691 /*! @brief Read current value of the ADC_CLP3_CLP3 field. */
01692 #define BR_ADC_CLP3_CLP3(x)  (HW_ADC_CLP3(x).B.CLP3)
01693 
01694 /*! @brief Format value for bitfield ADC_CLP3_CLP3. */
01695 #define BF_ADC_CLP3_CLP3(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLP3_CLP3) & BM_ADC_CLP3_CLP3)
01696 
01697 /*! @brief Set the CLP3 field to a new value. */
01698 #define BW_ADC_CLP3_CLP3(x, v) (HW_ADC_CLP3_WR(x, (HW_ADC_CLP3_RD(x) & ~BM_ADC_CLP3_CLP3) | BF_ADC_CLP3_CLP3(v)))
01699 /*@}*/
01700 
01701 /*******************************************************************************
01702  * HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register
01703  ******************************************************************************/
01704 
01705 /*!
01706  * @brief HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register (RW)
01707  *
01708  * Reset value: 0x00000080U
01709  *
01710  * For more information, see CLPD register description.
01711  */
01712 typedef union _hw_adc_clp2
01713 {
01714     uint32_t U;
01715     struct _hw_adc_clp2_bitfields
01716     {
01717         uint32_t CLP2 : 8;             /*!< [7:0]  */
01718         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
01719     } B;
01720 } hw_adc_clp2_t;
01721 
01722 /*!
01723  * @name Constants and macros for entire ADC_CLP2 register
01724  */
01725 /*@{*/
01726 #define HW_ADC_CLP2_ADDR(x)      ((x) + 0x44U)
01727 
01728 #define HW_ADC_CLP2(x)           (*(__IO hw_adc_clp2_t *) HW_ADC_CLP2_ADDR(x))
01729 #define HW_ADC_CLP2_RD(x)        (HW_ADC_CLP2(x).U)
01730 #define HW_ADC_CLP2_WR(x, v)     (HW_ADC_CLP2(x).U = (v))
01731 #define HW_ADC_CLP2_SET(x, v)    (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) |  (v)))
01732 #define HW_ADC_CLP2_CLR(x, v)    (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) & ~(v)))
01733 #define HW_ADC_CLP2_TOG(x, v)    (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) ^  (v)))
01734 /*@}*/
01735 
01736 /*
01737  * Constants & macros for individual ADC_CLP2 bitfields
01738  */
01739 
01740 /*!
01741  * @name Register ADC_CLP2, field CLP2[7:0] (RW)
01742  *
01743  * Calibration Value
01744  */
01745 /*@{*/
01746 #define BP_ADC_CLP2_CLP2     (0U)          /*!< Bit position for ADC_CLP2_CLP2. */
01747 #define BM_ADC_CLP2_CLP2     (0x000000FFU) /*!< Bit mask for ADC_CLP2_CLP2. */
01748 #define BS_ADC_CLP2_CLP2     (8U)          /*!< Bit field size in bits for ADC_CLP2_CLP2. */
01749 
01750 /*! @brief Read current value of the ADC_CLP2_CLP2 field. */
01751 #define BR_ADC_CLP2_CLP2(x)  (HW_ADC_CLP2(x).B.CLP2)
01752 
01753 /*! @brief Format value for bitfield ADC_CLP2_CLP2. */
01754 #define BF_ADC_CLP2_CLP2(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLP2_CLP2) & BM_ADC_CLP2_CLP2)
01755 
01756 /*! @brief Set the CLP2 field to a new value. */
01757 #define BW_ADC_CLP2_CLP2(x, v) (HW_ADC_CLP2_WR(x, (HW_ADC_CLP2_RD(x) & ~BM_ADC_CLP2_CLP2) | BF_ADC_CLP2_CLP2(v)))
01758 /*@}*/
01759 
01760 /*******************************************************************************
01761  * HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register
01762  ******************************************************************************/
01763 
01764 /*!
01765  * @brief HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register (RW)
01766  *
01767  * Reset value: 0x00000040U
01768  *
01769  * For more information, see CLPD register description.
01770  */
01771 typedef union _hw_adc_clp1
01772 {
01773     uint32_t U;
01774     struct _hw_adc_clp1_bitfields
01775     {
01776         uint32_t CLP1 : 7;             /*!< [6:0]  */
01777         uint32_t RESERVED0 : 25;       /*!< [31:7]  */
01778     } B;
01779 } hw_adc_clp1_t;
01780 
01781 /*!
01782  * @name Constants and macros for entire ADC_CLP1 register
01783  */
01784 /*@{*/
01785 #define HW_ADC_CLP1_ADDR(x)      ((x) + 0x48U)
01786 
01787 #define HW_ADC_CLP1(x)           (*(__IO hw_adc_clp1_t *) HW_ADC_CLP1_ADDR(x))
01788 #define HW_ADC_CLP1_RD(x)        (HW_ADC_CLP1(x).U)
01789 #define HW_ADC_CLP1_WR(x, v)     (HW_ADC_CLP1(x).U = (v))
01790 #define HW_ADC_CLP1_SET(x, v)    (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) |  (v)))
01791 #define HW_ADC_CLP1_CLR(x, v)    (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) & ~(v)))
01792 #define HW_ADC_CLP1_TOG(x, v)    (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) ^  (v)))
01793 /*@}*/
01794 
01795 /*
01796  * Constants & macros for individual ADC_CLP1 bitfields
01797  */
01798 
01799 /*!
01800  * @name Register ADC_CLP1, field CLP1[6:0] (RW)
01801  *
01802  * Calibration Value
01803  */
01804 /*@{*/
01805 #define BP_ADC_CLP1_CLP1     (0U)          /*!< Bit position for ADC_CLP1_CLP1. */
01806 #define BM_ADC_CLP1_CLP1     (0x0000007FU) /*!< Bit mask for ADC_CLP1_CLP1. */
01807 #define BS_ADC_CLP1_CLP1     (7U)          /*!< Bit field size in bits for ADC_CLP1_CLP1. */
01808 
01809 /*! @brief Read current value of the ADC_CLP1_CLP1 field. */
01810 #define BR_ADC_CLP1_CLP1(x)  (HW_ADC_CLP1(x).B.CLP1)
01811 
01812 /*! @brief Format value for bitfield ADC_CLP1_CLP1. */
01813 #define BF_ADC_CLP1_CLP1(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLP1_CLP1) & BM_ADC_CLP1_CLP1)
01814 
01815 /*! @brief Set the CLP1 field to a new value. */
01816 #define BW_ADC_CLP1_CLP1(x, v) (HW_ADC_CLP1_WR(x, (HW_ADC_CLP1_RD(x) & ~BM_ADC_CLP1_CLP1) | BF_ADC_CLP1_CLP1(v)))
01817 /*@}*/
01818 
01819 /*******************************************************************************
01820  * HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register
01821  ******************************************************************************/
01822 
01823 /*!
01824  * @brief HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register (RW)
01825  *
01826  * Reset value: 0x00000020U
01827  *
01828  * For more information, see CLPD register description.
01829  */
01830 typedef union _hw_adc_clp0
01831 {
01832     uint32_t U;
01833     struct _hw_adc_clp0_bitfields
01834     {
01835         uint32_t CLP0 : 6;             /*!< [5:0]  */
01836         uint32_t RESERVED0 : 26;       /*!< [31:6]  */
01837     } B;
01838 } hw_adc_clp0_t;
01839 
01840 /*!
01841  * @name Constants and macros for entire ADC_CLP0 register
01842  */
01843 /*@{*/
01844 #define HW_ADC_CLP0_ADDR(x)      ((x) + 0x4CU)
01845 
01846 #define HW_ADC_CLP0(x)           (*(__IO hw_adc_clp0_t *) HW_ADC_CLP0_ADDR(x))
01847 #define HW_ADC_CLP0_RD(x)        (HW_ADC_CLP0(x).U)
01848 #define HW_ADC_CLP0_WR(x, v)     (HW_ADC_CLP0(x).U = (v))
01849 #define HW_ADC_CLP0_SET(x, v)    (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) |  (v)))
01850 #define HW_ADC_CLP0_CLR(x, v)    (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) & ~(v)))
01851 #define HW_ADC_CLP0_TOG(x, v)    (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) ^  (v)))
01852 /*@}*/
01853 
01854 /*
01855  * Constants & macros for individual ADC_CLP0 bitfields
01856  */
01857 
01858 /*!
01859  * @name Register ADC_CLP0, field CLP0[5:0] (RW)
01860  *
01861  * Calibration Value
01862  */
01863 /*@{*/
01864 #define BP_ADC_CLP0_CLP0     (0U)          /*!< Bit position for ADC_CLP0_CLP0. */
01865 #define BM_ADC_CLP0_CLP0     (0x0000003FU) /*!< Bit mask for ADC_CLP0_CLP0. */
01866 #define BS_ADC_CLP0_CLP0     (6U)          /*!< Bit field size in bits for ADC_CLP0_CLP0. */
01867 
01868 /*! @brief Read current value of the ADC_CLP0_CLP0 field. */
01869 #define BR_ADC_CLP0_CLP0(x)  (HW_ADC_CLP0(x).B.CLP0)
01870 
01871 /*! @brief Format value for bitfield ADC_CLP0_CLP0. */
01872 #define BF_ADC_CLP0_CLP0(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLP0_CLP0) & BM_ADC_CLP0_CLP0)
01873 
01874 /*! @brief Set the CLP0 field to a new value. */
01875 #define BW_ADC_CLP0_CLP0(x, v) (HW_ADC_CLP0_WR(x, (HW_ADC_CLP0_RD(x) & ~BM_ADC_CLP0_CLP0) | BF_ADC_CLP0_CLP0(v)))
01876 /*@}*/
01877 
01878 /*******************************************************************************
01879  * HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register
01880  ******************************************************************************/
01881 
01882 /*!
01883  * @brief HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register (RW)
01884  *
01885  * Reset value: 0x0000000AU
01886  *
01887  * The Minus-Side General Calibration Value (CLMx) registers contain calibration
01888  * information that is generated by the calibration function. These registers
01889  * contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0],
01890  * CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are automatically
01891  * set when the self-calibration sequence is done, that is, CAL is cleared. If
01892  * these registers are written by the user after calibration, the linearity error
01893  * specifications may not be met.
01894  */
01895 typedef union _hw_adc_clmd
01896 {
01897     uint32_t U;
01898     struct _hw_adc_clmd_bitfields
01899     {
01900         uint32_t CLMD : 6;             /*!< [5:0]  */
01901         uint32_t RESERVED0 : 26;       /*!< [31:6]  */
01902     } B;
01903 } hw_adc_clmd_t;
01904 
01905 /*!
01906  * @name Constants and macros for entire ADC_CLMD register
01907  */
01908 /*@{*/
01909 #define HW_ADC_CLMD_ADDR(x)      ((x) + 0x54U)
01910 
01911 #define HW_ADC_CLMD(x)           (*(__IO hw_adc_clmd_t *) HW_ADC_CLMD_ADDR(x))
01912 #define HW_ADC_CLMD_RD(x)        (HW_ADC_CLMD(x).U)
01913 #define HW_ADC_CLMD_WR(x, v)     (HW_ADC_CLMD(x).U = (v))
01914 #define HW_ADC_CLMD_SET(x, v)    (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) |  (v)))
01915 #define HW_ADC_CLMD_CLR(x, v)    (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) & ~(v)))
01916 #define HW_ADC_CLMD_TOG(x, v)    (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) ^  (v)))
01917 /*@}*/
01918 
01919 /*
01920  * Constants & macros for individual ADC_CLMD bitfields
01921  */
01922 
01923 /*!
01924  * @name Register ADC_CLMD, field CLMD[5:0] (RW)
01925  *
01926  * Calibration Value
01927  */
01928 /*@{*/
01929 #define BP_ADC_CLMD_CLMD     (0U)          /*!< Bit position for ADC_CLMD_CLMD. */
01930 #define BM_ADC_CLMD_CLMD     (0x0000003FU) /*!< Bit mask for ADC_CLMD_CLMD. */
01931 #define BS_ADC_CLMD_CLMD     (6U)          /*!< Bit field size in bits for ADC_CLMD_CLMD. */
01932 
01933 /*! @brief Read current value of the ADC_CLMD_CLMD field. */
01934 #define BR_ADC_CLMD_CLMD(x)  (HW_ADC_CLMD(x).B.CLMD)
01935 
01936 /*! @brief Format value for bitfield ADC_CLMD_CLMD. */
01937 #define BF_ADC_CLMD_CLMD(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLMD_CLMD) & BM_ADC_CLMD_CLMD)
01938 
01939 /*! @brief Set the CLMD field to a new value. */
01940 #define BW_ADC_CLMD_CLMD(x, v) (HW_ADC_CLMD_WR(x, (HW_ADC_CLMD_RD(x) & ~BM_ADC_CLMD_CLMD) | BF_ADC_CLMD_CLMD(v)))
01941 /*@}*/
01942 
01943 /*******************************************************************************
01944  * HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register
01945  ******************************************************************************/
01946 
01947 /*!
01948  * @brief HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register (RW)
01949  *
01950  * Reset value: 0x00000020U
01951  *
01952  * For more information, see CLMD register description.
01953  */
01954 typedef union _hw_adc_clms
01955 {
01956     uint32_t U;
01957     struct _hw_adc_clms_bitfields
01958     {
01959         uint32_t CLMS : 6;             /*!< [5:0]  */
01960         uint32_t RESERVED0 : 26;       /*!< [31:6]  */
01961     } B;
01962 } hw_adc_clms_t;
01963 
01964 /*!
01965  * @name Constants and macros for entire ADC_CLMS register
01966  */
01967 /*@{*/
01968 #define HW_ADC_CLMS_ADDR(x)      ((x) + 0x58U)
01969 
01970 #define HW_ADC_CLMS(x)           (*(__IO hw_adc_clms_t *) HW_ADC_CLMS_ADDR(x))
01971 #define HW_ADC_CLMS_RD(x)        (HW_ADC_CLMS(x).U)
01972 #define HW_ADC_CLMS_WR(x, v)     (HW_ADC_CLMS(x).U = (v))
01973 #define HW_ADC_CLMS_SET(x, v)    (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) |  (v)))
01974 #define HW_ADC_CLMS_CLR(x, v)    (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) & ~(v)))
01975 #define HW_ADC_CLMS_TOG(x, v)    (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) ^  (v)))
01976 /*@}*/
01977 
01978 /*
01979  * Constants & macros for individual ADC_CLMS bitfields
01980  */
01981 
01982 /*!
01983  * @name Register ADC_CLMS, field CLMS[5:0] (RW)
01984  *
01985  * Calibration Value
01986  */
01987 /*@{*/
01988 #define BP_ADC_CLMS_CLMS     (0U)          /*!< Bit position for ADC_CLMS_CLMS. */
01989 #define BM_ADC_CLMS_CLMS     (0x0000003FU) /*!< Bit mask for ADC_CLMS_CLMS. */
01990 #define BS_ADC_CLMS_CLMS     (6U)          /*!< Bit field size in bits for ADC_CLMS_CLMS. */
01991 
01992 /*! @brief Read current value of the ADC_CLMS_CLMS field. */
01993 #define BR_ADC_CLMS_CLMS(x)  (HW_ADC_CLMS(x).B.CLMS)
01994 
01995 /*! @brief Format value for bitfield ADC_CLMS_CLMS. */
01996 #define BF_ADC_CLMS_CLMS(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLMS_CLMS) & BM_ADC_CLMS_CLMS)
01997 
01998 /*! @brief Set the CLMS field to a new value. */
01999 #define BW_ADC_CLMS_CLMS(x, v) (HW_ADC_CLMS_WR(x, (HW_ADC_CLMS_RD(x) & ~BM_ADC_CLMS_CLMS) | BF_ADC_CLMS_CLMS(v)))
02000 /*@}*/
02001 
02002 /*******************************************************************************
02003  * HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register
02004  ******************************************************************************/
02005 
02006 /*!
02007  * @brief HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register (RW)
02008  *
02009  * Reset value: 0x00000200U
02010  *
02011  * For more information, see CLMD register description.
02012  */
02013 typedef union _hw_adc_clm4
02014 {
02015     uint32_t U;
02016     struct _hw_adc_clm4_bitfields
02017     {
02018         uint32_t CLM4 : 10;            /*!< [9:0]  */
02019         uint32_t RESERVED0 : 22;       /*!< [31:10]  */
02020     } B;
02021 } hw_adc_clm4_t;
02022 
02023 /*!
02024  * @name Constants and macros for entire ADC_CLM4 register
02025  */
02026 /*@{*/
02027 #define HW_ADC_CLM4_ADDR(x)      ((x) + 0x5CU)
02028 
02029 #define HW_ADC_CLM4(x)           (*(__IO hw_adc_clm4_t *) HW_ADC_CLM4_ADDR(x))
02030 #define HW_ADC_CLM4_RD(x)        (HW_ADC_CLM4(x).U)
02031 #define HW_ADC_CLM4_WR(x, v)     (HW_ADC_CLM4(x).U = (v))
02032 #define HW_ADC_CLM4_SET(x, v)    (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) |  (v)))
02033 #define HW_ADC_CLM4_CLR(x, v)    (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) & ~(v)))
02034 #define HW_ADC_CLM4_TOG(x, v)    (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) ^  (v)))
02035 /*@}*/
02036 
02037 /*
02038  * Constants & macros for individual ADC_CLM4 bitfields
02039  */
02040 
02041 /*!
02042  * @name Register ADC_CLM4, field CLM4[9:0] (RW)
02043  *
02044  * Calibration Value
02045  */
02046 /*@{*/
02047 #define BP_ADC_CLM4_CLM4     (0U)          /*!< Bit position for ADC_CLM4_CLM4. */
02048 #define BM_ADC_CLM4_CLM4     (0x000003FFU) /*!< Bit mask for ADC_CLM4_CLM4. */
02049 #define BS_ADC_CLM4_CLM4     (10U)         /*!< Bit field size in bits for ADC_CLM4_CLM4. */
02050 
02051 /*! @brief Read current value of the ADC_CLM4_CLM4 field. */
02052 #define BR_ADC_CLM4_CLM4(x)  (HW_ADC_CLM4(x).B.CLM4)
02053 
02054 /*! @brief Format value for bitfield ADC_CLM4_CLM4. */
02055 #define BF_ADC_CLM4_CLM4(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLM4_CLM4) & BM_ADC_CLM4_CLM4)
02056 
02057 /*! @brief Set the CLM4 field to a new value. */
02058 #define BW_ADC_CLM4_CLM4(x, v) (HW_ADC_CLM4_WR(x, (HW_ADC_CLM4_RD(x) & ~BM_ADC_CLM4_CLM4) | BF_ADC_CLM4_CLM4(v)))
02059 /*@}*/
02060 
02061 /*******************************************************************************
02062  * HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register
02063  ******************************************************************************/
02064 
02065 /*!
02066  * @brief HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register (RW)
02067  *
02068  * Reset value: 0x00000100U
02069  *
02070  * For more information, see CLMD register description.
02071  */
02072 typedef union _hw_adc_clm3
02073 {
02074     uint32_t U;
02075     struct _hw_adc_clm3_bitfields
02076     {
02077         uint32_t CLM3 : 9;             /*!< [8:0]  */
02078         uint32_t RESERVED0 : 23;       /*!< [31:9]  */
02079     } B;
02080 } hw_adc_clm3_t;
02081 
02082 /*!
02083  * @name Constants and macros for entire ADC_CLM3 register
02084  */
02085 /*@{*/
02086 #define HW_ADC_CLM3_ADDR(x)      ((x) + 0x60U)
02087 
02088 #define HW_ADC_CLM3(x)           (*(__IO hw_adc_clm3_t *) HW_ADC_CLM3_ADDR(x))
02089 #define HW_ADC_CLM3_RD(x)        (HW_ADC_CLM3(x).U)
02090 #define HW_ADC_CLM3_WR(x, v)     (HW_ADC_CLM3(x).U = (v))
02091 #define HW_ADC_CLM3_SET(x, v)    (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) |  (v)))
02092 #define HW_ADC_CLM3_CLR(x, v)    (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) & ~(v)))
02093 #define HW_ADC_CLM3_TOG(x, v)    (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) ^  (v)))
02094 /*@}*/
02095 
02096 /*
02097  * Constants & macros for individual ADC_CLM3 bitfields
02098  */
02099 
02100 /*!
02101  * @name Register ADC_CLM3, field CLM3[8:0] (RW)
02102  *
02103  * Calibration Value
02104  */
02105 /*@{*/
02106 #define BP_ADC_CLM3_CLM3     (0U)          /*!< Bit position for ADC_CLM3_CLM3. */
02107 #define BM_ADC_CLM3_CLM3     (0x000001FFU) /*!< Bit mask for ADC_CLM3_CLM3. */
02108 #define BS_ADC_CLM3_CLM3     (9U)          /*!< Bit field size in bits for ADC_CLM3_CLM3. */
02109 
02110 /*! @brief Read current value of the ADC_CLM3_CLM3 field. */
02111 #define BR_ADC_CLM3_CLM3(x)  (HW_ADC_CLM3(x).B.CLM3)
02112 
02113 /*! @brief Format value for bitfield ADC_CLM3_CLM3. */
02114 #define BF_ADC_CLM3_CLM3(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLM3_CLM3) & BM_ADC_CLM3_CLM3)
02115 
02116 /*! @brief Set the CLM3 field to a new value. */
02117 #define BW_ADC_CLM3_CLM3(x, v) (HW_ADC_CLM3_WR(x, (HW_ADC_CLM3_RD(x) & ~BM_ADC_CLM3_CLM3) | BF_ADC_CLM3_CLM3(v)))
02118 /*@}*/
02119 
02120 /*******************************************************************************
02121  * HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register
02122  ******************************************************************************/
02123 
02124 /*!
02125  * @brief HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register (RW)
02126  *
02127  * Reset value: 0x00000080U
02128  *
02129  * For more information, see CLMD register description.
02130  */
02131 typedef union _hw_adc_clm2
02132 {
02133     uint32_t U;
02134     struct _hw_adc_clm2_bitfields
02135     {
02136         uint32_t CLM2 : 8;             /*!< [7:0]  */
02137         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
02138     } B;
02139 } hw_adc_clm2_t;
02140 
02141 /*!
02142  * @name Constants and macros for entire ADC_CLM2 register
02143  */
02144 /*@{*/
02145 #define HW_ADC_CLM2_ADDR(x)      ((x) + 0x64U)
02146 
02147 #define HW_ADC_CLM2(x)           (*(__IO hw_adc_clm2_t *) HW_ADC_CLM2_ADDR(x))
02148 #define HW_ADC_CLM2_RD(x)        (HW_ADC_CLM2(x).U)
02149 #define HW_ADC_CLM2_WR(x, v)     (HW_ADC_CLM2(x).U = (v))
02150 #define HW_ADC_CLM2_SET(x, v)    (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) |  (v)))
02151 #define HW_ADC_CLM2_CLR(x, v)    (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) & ~(v)))
02152 #define HW_ADC_CLM2_TOG(x, v)    (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) ^  (v)))
02153 /*@}*/
02154 
02155 /*
02156  * Constants & macros for individual ADC_CLM2 bitfields
02157  */
02158 
02159 /*!
02160  * @name Register ADC_CLM2, field CLM2[7:0] (RW)
02161  *
02162  * Calibration Value
02163  */
02164 /*@{*/
02165 #define BP_ADC_CLM2_CLM2     (0U)          /*!< Bit position for ADC_CLM2_CLM2. */
02166 #define BM_ADC_CLM2_CLM2     (0x000000FFU) /*!< Bit mask for ADC_CLM2_CLM2. */
02167 #define BS_ADC_CLM2_CLM2     (8U)          /*!< Bit field size in bits for ADC_CLM2_CLM2. */
02168 
02169 /*! @brief Read current value of the ADC_CLM2_CLM2 field. */
02170 #define BR_ADC_CLM2_CLM2(x)  (HW_ADC_CLM2(x).B.CLM2)
02171 
02172 /*! @brief Format value for bitfield ADC_CLM2_CLM2. */
02173 #define BF_ADC_CLM2_CLM2(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLM2_CLM2) & BM_ADC_CLM2_CLM2)
02174 
02175 /*! @brief Set the CLM2 field to a new value. */
02176 #define BW_ADC_CLM2_CLM2(x, v) (HW_ADC_CLM2_WR(x, (HW_ADC_CLM2_RD(x) & ~BM_ADC_CLM2_CLM2) | BF_ADC_CLM2_CLM2(v)))
02177 /*@}*/
02178 
02179 /*******************************************************************************
02180  * HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register
02181  ******************************************************************************/
02182 
02183 /*!
02184  * @brief HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register (RW)
02185  *
02186  * Reset value: 0x00000040U
02187  *
02188  * For more information, see CLMD register description.
02189  */
02190 typedef union _hw_adc_clm1
02191 {
02192     uint32_t U;
02193     struct _hw_adc_clm1_bitfields
02194     {
02195         uint32_t CLM1 : 7;             /*!< [6:0]  */
02196         uint32_t RESERVED0 : 25;       /*!< [31:7]  */
02197     } B;
02198 } hw_adc_clm1_t;
02199 
02200 /*!
02201  * @name Constants and macros for entire ADC_CLM1 register
02202  */
02203 /*@{*/
02204 #define HW_ADC_CLM1_ADDR(x)      ((x) + 0x68U)
02205 
02206 #define HW_ADC_CLM1(x)           (*(__IO hw_adc_clm1_t *) HW_ADC_CLM1_ADDR(x))
02207 #define HW_ADC_CLM1_RD(x)        (HW_ADC_CLM1(x).U)
02208 #define HW_ADC_CLM1_WR(x, v)     (HW_ADC_CLM1(x).U = (v))
02209 #define HW_ADC_CLM1_SET(x, v)    (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) |  (v)))
02210 #define HW_ADC_CLM1_CLR(x, v)    (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) & ~(v)))
02211 #define HW_ADC_CLM1_TOG(x, v)    (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) ^  (v)))
02212 /*@}*/
02213 
02214 /*
02215  * Constants & macros for individual ADC_CLM1 bitfields
02216  */
02217 
02218 /*!
02219  * @name Register ADC_CLM1, field CLM1[6:0] (RW)
02220  *
02221  * Calibration Value
02222  */
02223 /*@{*/
02224 #define BP_ADC_CLM1_CLM1     (0U)          /*!< Bit position for ADC_CLM1_CLM1. */
02225 #define BM_ADC_CLM1_CLM1     (0x0000007FU) /*!< Bit mask for ADC_CLM1_CLM1. */
02226 #define BS_ADC_CLM1_CLM1     (7U)          /*!< Bit field size in bits for ADC_CLM1_CLM1. */
02227 
02228 /*! @brief Read current value of the ADC_CLM1_CLM1 field. */
02229 #define BR_ADC_CLM1_CLM1(x)  (HW_ADC_CLM1(x).B.CLM1)
02230 
02231 /*! @brief Format value for bitfield ADC_CLM1_CLM1. */
02232 #define BF_ADC_CLM1_CLM1(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLM1_CLM1) & BM_ADC_CLM1_CLM1)
02233 
02234 /*! @brief Set the CLM1 field to a new value. */
02235 #define BW_ADC_CLM1_CLM1(x, v) (HW_ADC_CLM1_WR(x, (HW_ADC_CLM1_RD(x) & ~BM_ADC_CLM1_CLM1) | BF_ADC_CLM1_CLM1(v)))
02236 /*@}*/
02237 
02238 /*******************************************************************************
02239  * HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register
02240  ******************************************************************************/
02241 
02242 /*!
02243  * @brief HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register (RW)
02244  *
02245  * Reset value: 0x00000020U
02246  *
02247  * For more information, see CLMD register description.
02248  */
02249 typedef union _hw_adc_clm0
02250 {
02251     uint32_t U;
02252     struct _hw_adc_clm0_bitfields
02253     {
02254         uint32_t CLM0 : 6;             /*!< [5:0]  */
02255         uint32_t RESERVED0 : 26;       /*!< [31:6]  */
02256     } B;
02257 } hw_adc_clm0_t;
02258 
02259 /*!
02260  * @name Constants and macros for entire ADC_CLM0 register
02261  */
02262 /*@{*/
02263 #define HW_ADC_CLM0_ADDR(x)      ((x) + 0x6CU)
02264 
02265 #define HW_ADC_CLM0(x)           (*(__IO hw_adc_clm0_t *) HW_ADC_CLM0_ADDR(x))
02266 #define HW_ADC_CLM0_RD(x)        (HW_ADC_CLM0(x).U)
02267 #define HW_ADC_CLM0_WR(x, v)     (HW_ADC_CLM0(x).U = (v))
02268 #define HW_ADC_CLM0_SET(x, v)    (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) |  (v)))
02269 #define HW_ADC_CLM0_CLR(x, v)    (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) & ~(v)))
02270 #define HW_ADC_CLM0_TOG(x, v)    (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) ^  (v)))
02271 /*@}*/
02272 
02273 /*
02274  * Constants & macros for individual ADC_CLM0 bitfields
02275  */
02276 
02277 /*!
02278  * @name Register ADC_CLM0, field CLM0[5:0] (RW)
02279  *
02280  * Calibration Value
02281  */
02282 /*@{*/
02283 #define BP_ADC_CLM0_CLM0     (0U)          /*!< Bit position for ADC_CLM0_CLM0. */
02284 #define BM_ADC_CLM0_CLM0     (0x0000003FU) /*!< Bit mask for ADC_CLM0_CLM0. */
02285 #define BS_ADC_CLM0_CLM0     (6U)          /*!< Bit field size in bits for ADC_CLM0_CLM0. */
02286 
02287 /*! @brief Read current value of the ADC_CLM0_CLM0 field. */
02288 #define BR_ADC_CLM0_CLM0(x)  (HW_ADC_CLM0(x).B.CLM0)
02289 
02290 /*! @brief Format value for bitfield ADC_CLM0_CLM0. */
02291 #define BF_ADC_CLM0_CLM0(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLM0_CLM0) & BM_ADC_CLM0_CLM0)
02292 
02293 /*! @brief Set the CLM0 field to a new value. */
02294 #define BW_ADC_CLM0_CLM0(x, v) (HW_ADC_CLM0_WR(x, (HW_ADC_CLM0_RD(x) & ~BM_ADC_CLM0_CLM0) | BF_ADC_CLM0_CLM0(v)))
02295 /*@}*/
02296 
02297 /*******************************************************************************
02298  * hw_adc_t - module struct
02299  ******************************************************************************/
02300 /*!
02301  * @brief All ADC module registers.
02302  */
02303 #pragma pack(1)
02304 typedef struct _hw_adc
02305 {
02306     __IO hw_adc_sc1n_t SC1n [2];            /*!< [0x0] ADC Status and Control Registers 1 */
02307     __IO hw_adc_cfg1_t CFG1 ;               /*!< [0x8] ADC Configuration Register 1 */
02308     __IO hw_adc_cfg2_t CFG2 ;               /*!< [0xC] ADC Configuration Register 2 */
02309     __I hw_adc_rn_t Rn [2];                 /*!< [0x10] ADC Data Result Register */
02310     __IO hw_adc_cv1_t CV1 ;                 /*!< [0x18] Compare Value Registers */
02311     __IO hw_adc_cv2_t CV2 ;                 /*!< [0x1C] Compare Value Registers */
02312     __IO hw_adc_sc2_t SC2 ;                 /*!< [0x20] Status and Control Register 2 */
02313     __IO hw_adc_sc3_t SC3 ;                 /*!< [0x24] Status and Control Register 3 */
02314     __IO hw_adc_ofs_t OFS ;                 /*!< [0x28] ADC Offset Correction Register */
02315     __IO hw_adc_pg_t PG ;                   /*!< [0x2C] ADC Plus-Side Gain Register */
02316     __IO hw_adc_mg_t MG ;                   /*!< [0x30] ADC Minus-Side Gain Register */
02317     __IO hw_adc_clpd_t CLPD ;               /*!< [0x34] ADC Plus-Side General Calibration Value Register */
02318     __IO hw_adc_clps_t CLPS ;               /*!< [0x38] ADC Plus-Side General Calibration Value Register */
02319     __IO hw_adc_clp4_t CLP4 ;               /*!< [0x3C] ADC Plus-Side General Calibration Value Register */
02320     __IO hw_adc_clp3_t CLP3 ;               /*!< [0x40] ADC Plus-Side General Calibration Value Register */
02321     __IO hw_adc_clp2_t CLP2 ;               /*!< [0x44] ADC Plus-Side General Calibration Value Register */
02322     __IO hw_adc_clp1_t CLP1 ;               /*!< [0x48] ADC Plus-Side General Calibration Value Register */
02323     __IO hw_adc_clp0_t CLP0 ;               /*!< [0x4C] ADC Plus-Side General Calibration Value Register */
02324     uint8_t _reserved0[4];
02325     __IO hw_adc_clmd_t CLMD ;               /*!< [0x54] ADC Minus-Side General Calibration Value Register */
02326     __IO hw_adc_clms_t CLMS ;               /*!< [0x58] ADC Minus-Side General Calibration Value Register */
02327     __IO hw_adc_clm4_t CLM4 ;               /*!< [0x5C] ADC Minus-Side General Calibration Value Register */
02328     __IO hw_adc_clm3_t CLM3 ;               /*!< [0x60] ADC Minus-Side General Calibration Value Register */
02329     __IO hw_adc_clm2_t CLM2 ;               /*!< [0x64] ADC Minus-Side General Calibration Value Register */
02330     __IO hw_adc_clm1_t CLM1 ;               /*!< [0x68] ADC Minus-Side General Calibration Value Register */
02331     __IO hw_adc_clm0_t CLM0 ;               /*!< [0x6C] ADC Minus-Side General Calibration Value Register */
02332 } hw_adc_t;
02333 #pragma pack()
02334 
02335 /*! @brief Macro to access all ADC registers. */
02336 /*! @param x ADC module instance base address. */
02337 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
02338  *     use the '&' operator, like <code>&HW_ADC(ADC0_BASE)</code>. */
02339 #define HW_ADC(x)      (*(hw_adc_t *)(x))
02340 
02341 #endif /* __HW_ADC_REGISTERS_H__ */
02342 /* EOF */