Diff: MAX1471_regs.h

Revision:

0:99e9397112f0

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/MAX1471_regs.h	Fri Oct 04 15:15:06 2019 +0300
@@ -0,0 +1,94 @@
+/*
+ * Max1471_regs.h
+ *
+ *  Created on: Dec 17, 2018
+ *      Author: Erman.Komurcu
+ */
+
+#ifndef MAX1471_MAX1471_REGS_H_
+#define MAX1471_MAX1471_REGS_H_
+
+/**
+ * @brief PWR_CFG  (0x00)
+ *
+ * @description	Power Configuration Register
+ */
+typedef union {
+    unsigned char raw;
+    struct {
+    	unsigned char sleep		: 1;    /**< Sleep mode */
+    	unsigned char askpd_en 	: 1;    /**< ASK peak detector enable */
+    	unsigned char askbb_en 	: 1;    /**< ASK baseband enabled */
+    	unsigned char fskpd_en  : 1;    /**< FSK peak detector enable */
+    	unsigned char fskbb_en  : 1;	/**< FSK baseband enable */
+    	unsigned char mixer_en  : 1;    /**< Mixer enable */
+    	unsigned char agc_en    : 1;    /**< AGC enable */
+        unsigned char lna_en	: 1;    /**< LNA enable */
+    } bits;
+} max1471_reg_pwr_cfg_t;
+
+/**
+ * @brief CFG  (0x01)
+ *
+ * @description	 Configuration Register
+ */
+typedef union {
+    unsigned char raw;
+    struct {
+    	unsigned char drx_mode	: 1;    /**< Receive mode */
+    	unsigned char toff_ps0 	: 1;    /**< Off-timer prescale */
+    	unsigned char toff_ps1 	: 1;    /**< Off-timer prescale */
+    	unsigned char dout_ask  : 1;    /**< ASKOUT enable */
+    	unsigned char dout_fsk  : 1;	/**< FSKOUT enable */
+    	unsigned char fskcallsb : 1;    /**< FSK accurate calibration */
+    	unsigned char gainset   : 1;    /**< Gain set */
+        unsigned char 			: 1;    /**< Don"t care */
+    } bits;
+} max1471_reg_cfg_t;
+
+/**
+ * @brief CTRL  (0x02)
+ *
+ * @description	 Control Register
+ */
+typedef union {
+    unsigned char raw;
+    struct {
+    	unsigned char fsk_cal_en: 1;    /**< FSK calibration enable */
+    	unsigned char pol_cal_en: 1;    /**< Polling timer calibration enable */
+    	unsigned char asktrk_en	: 1;    /**< ASK peak detector track enable */
+    	unsigned char fsktrk_en : 1;    /**< FSK peak detector track enable */
+    	unsigned char			: 1;	/**< Don't care */
+    	unsigned char agclock 	: 1;    /**< AGC lock */
+        unsigned char 			: 1;    /**< Don"t care */
+    } bits;
+} max1471_reg_ctrl_t;
+
+/**
+ * @brief STAT  (0x09)
+ *
+ * @description	 Status Register
+ */
+typedef union {
+    unsigned char raw;
+    struct {
+    	unsigned char fsk_cal_done	: 1;    /**< FSK calibration done */
+    	unsigned char pol_cal_done	: 1;    /**< Polling timer calibration done */
+    	unsigned char				: 3;    /**< Don't care */
+    	unsigned char clkalive		: 1;    /**< Clock/crystal alive */
+    	unsigned char agcst			: 1;	/**< AGC state */
+    	unsigned char lockdet 		: 1;    /**< Lock detect */
+    } bits;
+} max1471_reg_stat_t;
+/**
+ * @brief Register Set
+ *
+ */
+typedef struct {
+	max1471_reg_pwr_cfg_t	reg_pwr_cfg;
+	max1471_reg_cfg_t		reg_cfg;
+	max1471_reg_ctrl_t		reg_ctrl;
+	max1471_reg_stat_t		reg_stat;
+} max1471_reg_map_t;
+
+#endif /* MAX1471_MAX1471_REGS_H_ */