Maxim Integrated
Maxim Integrated's IoT development kit.
Dependencies: MAX30101 MAX30003 MAX113XX_Pixi MAX30205 max32630fthr USBDevice
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MAX11301Hex.h
00001 /******************************************************************************* 00002 * Copyright (C) 2018 Maxim Integrated Products, Inc., All Rights Reserved. 00003 * 00004 * Permission is hereby granted, free of charge, to any person obtaining a 00005 * copy of this software and associated documentation files (the "Software"), 00006 * to deal in the Software without restriction, including without limitation 00007 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 00008 * and/or sell copies of the Software, and to permit persons to whom the 00009 * Software is furnished to do so, subject to the following conditions: 00010 * 00011 * The above copyright notice and this permission notice shall be included 00012 * in all copies or substantial portions of the Software. 00013 * 00014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 00015 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 00016 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 00017 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES 00018 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 00019 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 00020 * OTHER DEALINGS IN THE SOFTWARE. 00021 * 00022 * Except as contained in this notice, the name of Maxim Integrated 00023 * Products, Inc. shall not be used except as stated in the Maxim Integrated 00024 * Products, Inc. Branding Policy. 00025 * 00026 * The mere transfer of this software does not imply any licenses 00027 * of trade secrets, proprietary technology, copyrights, patents, 00028 * trademarks, maskwork rights, or any other form of intellectual 00029 * property whatsoever. Maxim Integrated Products, Inc. retains all 00030 * ownership rights. 00031 ******************************************************************************* 00032 */ 00033 /// Generated by: MAX11300/01/11/12 Configuration Software (Ver. 1.1.0.5) 04/08/2017 13:35 00034 /// Description: New Empty Design 00035 /// Port P0: 00036 /// Port P1: 00037 /// Port P2: 00038 /// Port P3: 00039 /// Port P4: 00040 /// Port P5: 00041 /// Port P6: 00042 /// Port P7: 00043 /// Port P8: 00044 /// Port P9: 00045 /// Port P10: 00046 /// Port P11: 00047 /// Port P12: 00048 /// Port P13: 00049 /// Port P14: 00050 /// Port P15: 00051 /// Port P16: 00052 /// Port P17: 00053 /// Port P18: 00054 /// Port P19: 00055 /// Notes: Optional: Enter design notes here 00056 #ifndef _MAX11300_DESIGNVALUE_H_ 00057 #define _MAX11300_DESIGNVALUE_H_ 00058 00059 /// Supply voltage on AVSSIO 00060 #define MAX11300_AVSSIO_VOLTAGE -7.5 00061 00062 /// Supply voltage on AVDDIO 00063 #define MAX11300_AVDDIO_VOLTAGE 7.5 00064 00065 /// Supply voltage on DVDD 00066 #define MAX11300_DVDD_VOLTAGE 3.3 00067 00068 /// Supply voltage on AVDD 00069 #define MAX11300_AVDD_VOLTAGE 5 00070 00071 /// Supply voltage on DAC_REF 00072 #define MAX11300_DAC_REF_VOLTAGE 2.5 00073 00074 /// Supply voltage on ADC_EXT_REF 00075 #define MAX11300_ADC_EXT_REF_VOLTAGE 2.5 00076 00077 /// SPI first byte when writing MAX11300 (7-bit address in bits 0x7E; LSB=0 for write) 00078 #define MAX11300Addr_SPI_Write(RegAddr) ( (RegAddr << 1) ) 00079 00080 /// SPI first byte when reading MAX11300 (7-bit address in bits 0x7E; LSB=1 for read) 00081 #define MAX11300Addr_SPI_Read(RegAddr) ( (RegAddr << 1) | 1 ) 00082 00083 /// MAX11300EVKIT Register Addresses 00084 typedef enum MAX11300RegAddressEnum { 00085 00086 /// 0x00 r/o dev_id Device Identification 00087 dev_id = 0x00, 00088 00089 /// 0x01 r/o interrupt_flag Interrupt flags 00090 interrupt_flag = 0x01, 00091 00092 /// 0x02 r/o adc_status_15_to_0 new ADC data available 00093 adc_status_15_to_0 = 0x02, 00094 00095 /// 0x03 r/o adc_status_19_to_16 new ADC data available 00096 adc_status_19_to_16 = 0x03, 00097 00098 /// 0x04 r/o dac_oi_status_15_to_0 DAC Overcurrent Interrupt 00099 dac_oi_status_15_to_0 = 0x04, 00100 00101 /// 0x05 r/o dac_oi_status_19_to_16 DAC Overcurrent Interrupt 00102 dac_oi_status_19_to_16 = 0x05, 00103 00104 /// 0x06 r/o gpi_status_15_to_0 GPI event ready 00105 gpi_status_15_to_0 = 0x06, 00106 00107 /// 0x07 r/o gpi_status_19_to_16 GPI event ready 00108 gpi_status_19_to_16 = 0x07, 00109 00110 /// 0x08 r/o tmp_int_data Internal Temeprature 00111 tmp_int_data = 0x08, 00112 00113 /// 0x09 r/o tmp_ext1_data External Temperature D0P/D0N 00114 tmp_ext1_data = 0x09, 00115 00116 /// 0x0a r/o tmp_ext2_data External Temperature D1P/D1N 00117 tmp_ext2_data = 0x0a, 00118 00119 /// 0x0b r/o gpi_data_15_to_0 GPI input ports data 00120 gpi_data_15_to_0 = 0x0b, 00121 00122 /// 0x0c r/o gpi_data_19_to_16 GPI input ports data 00123 gpi_data_19_to_16 = 0x0c, 00124 00125 /// 0x0d r/w gpo_data_15_to_0 GPO output ports data 00126 gpo_data_15_to_0 = 0x0d, 00127 00128 /// 0x0e r/w gpo_data_19_to_16 GPO output ports data 00129 gpo_data_19_to_16 = 0x0e, 00130 00131 /// 0x0f r/o reserved_0F reserved 00132 reserved_0F = 0x0f, 00133 00134 /// 0x10 r/w device_control Global device control register 00135 device_control = 0x10, 00136 00137 /// 0x11 r/w interrupt_mask interrupt mask (1 = disable interrupt source) 00138 interrupt_mask = 0x11, 00139 00140 /// 0x12 r/w gpi_irqmode_7_to_0 GPI port 0 to 7 mode register 00141 gpi_irqmode_7_to_0 = 0x12, 00142 00143 /// 0x13 r/w gpi_irqmode_15_to_8 GPI port 8 to 15 mode register 00144 gpi_irqmode_15_to_8 = 0x13, 00145 00146 /// 0x14 r/w gpi_irqmode_19_to_16 GPI port 16 to 19 mode register 00147 gpi_irqmode_19_to_16 = 0x14, 00148 00149 /// 0x15 r/w gpi_irqmode_31_to_24 (reserved) 00150 gpi_irqmode_31_to_24 = 0x15, 00151 00152 /// 0x16 r/w dac_preset_data_1 DAC preset activated by <see cref="device_control"/> 00153 dac_preset_data_1 = 0x16, 00154 00155 /// 0x17 r/w dac_preset_data_2 DAC preset activated by <see cref="device_control"/> 00156 dac_preset_data_2 = 0x17, 00157 00158 /// 0x18 r/w tmp_mon_cfg Temperautre Monitor Configuration 00159 tmp_mon_cfg = 0x18, 00160 00161 /// 0x19 r/w tmp_mon_int_hi_thresh Internal Temeprature Hot Threshold 00162 tmp_mon_int_hi_thresh = 0x19, 00163 00164 /// 0x1a r/w tmp_mon_int_lo_thresh Internal Temeprature Cold Threshold 00165 tmp_mon_int_lo_thresh = 0x1a, 00166 00167 /// 0x1b r/w tmp_mon_ext1_hi_thresh External Temperature D0P/D0N Hot Threshold 00168 tmp_mon_ext1_hi_thresh = 0x1b, 00169 00170 /// 0x1c r/w tmp_mon_ext1_lo_thresh External Temperature D0P/D0N Cold Threshold 00171 tmp_mon_ext1_lo_thresh = 0x1c, 00172 00173 /// 0x1d r/w tmp_mon_ext2_hi_thresh External Temperature D1P/D1N Hot Threshold 00174 tmp_mon_ext2_hi_thresh = 0x1d, 00175 00176 /// 0x1e r/w tmp_mon_ext2_lo_thresh External Temperature D1P/D1N Cold Threshold 00177 tmp_mon_ext2_lo_thresh = 0x1e, 00178 00179 /// 0x1f r/w reserved_1F reserved 00180 reserved_1F = 0x1f, 00181 00182 /// 0x20 r/w port_cfg_00 PIXI port 0 configuration register 00183 port_cfg_00 = 0x20, 00184 00185 /// 0x21 r/w port_cfg_01 PIXI port 1 configuration register 00186 port_cfg_01 = 0x21, 00187 00188 /// 0x22 r/w port_cfg_02 PIXI port 2 configuration register 00189 port_cfg_02 = 0x22, 00190 00191 /// 0x23 r/w port_cfg_03 PIXI port 3 configuration register 00192 port_cfg_03 = 0x23, 00193 00194 /// 0x24 r/w port_cfg_04 PIXI port 4 configuration register 00195 port_cfg_04 = 0x24, 00196 00197 /// 0x25 r/w port_cfg_05 PIXI port 5 configuration register 00198 port_cfg_05 = 0x25, 00199 00200 /// 0x26 r/w port_cfg_06 PIXI port 6 configuration register 00201 port_cfg_06 = 0x26, 00202 00203 /// 0x27 r/w port_cfg_07 PIXI port 7 configuration register 00204 port_cfg_07 = 0x27, 00205 00206 /// 0x28 r/w port_cfg_08 PIXI port 8 configuration register 00207 port_cfg_08 = 0x28, 00208 00209 /// 0x29 r/w port_cfg_09 PIXI port 9 configuration register 00210 port_cfg_09 = 0x29, 00211 00212 /// 0x2a r/w port_cfg_10 PIXI port 10 configuration register 00213 port_cfg_10 = 0x2a, 00214 00215 /// 0x2b r/w port_cfg_11 PIXI port 11 configuration register 00216 port_cfg_11 = 0x2b, 00217 00218 /// 0x2c r/w port_cfg_12 PIXI port 12 configuration register 00219 port_cfg_12 = 0x2c, 00220 00221 /// 0x2d r/w port_cfg_13 PIXI port 13 configuration register 00222 port_cfg_13 = 0x2d, 00223 00224 /// 0x2e r/w port_cfg_14 PIXI port 14 configuration register 00225 port_cfg_14 = 0x2e, 00226 00227 /// 0x2f r/w port_cfg_15 PIXI port 15 configuration register 00228 port_cfg_15 = 0x2f, 00229 00230 /// 0x30 r/w port_cfg_16 PIXI port 16 configuration register 00231 port_cfg_16 = 0x30, 00232 00233 /// 0x31 r/w port_cfg_17 PIXI port 17 configuration register 00234 port_cfg_17 = 0x31, 00235 00236 /// 0x32 r/w port_cfg_18 PIXI port 18 configuration register 00237 port_cfg_18 = 0x32, 00238 00239 /// 0x33 r/w port_cfg_19 PIXI port 19 configuration register 00240 port_cfg_19 = 0x33, 00241 00242 /// 0x40 r/o adc_data_port_00 PIXI port 0 Analog to Digital Converter register 00243 adc_data_port_00 = 0x40, 00244 00245 /// 0x41 r/o adc_data_port_01 PIXI port 1 Analog to Digital Converter register 00246 adc_data_port_01 = 0x41, 00247 00248 /// 0x42 r/o adc_data_port_02 PIXI port 2 Analog to Digital Converter register 00249 adc_data_port_02 = 0x42, 00250 00251 /// 0x43 r/o adc_data_port_03 PIXI port 3 Analog to Digital Converter register 00252 adc_data_port_03 = 0x43, 00253 00254 /// 0x44 r/o adc_data_port_04 PIXI port 4 Analog to Digital Converter register 00255 adc_data_port_04 = 0x44, 00256 00257 /// 0x45 r/o adc_data_port_05 PIXI port 5 Analog to Digital Converter register 00258 adc_data_port_05 = 0x45, 00259 00260 /// 0x46 r/o adc_data_port_06 PIXI port 6 Analog to Digital Converter register 00261 adc_data_port_06 = 0x46, 00262 00263 /// 0x47 r/o adc_data_port_07 PIXI port 7 Analog to Digital Converter register 00264 adc_data_port_07 = 0x47, 00265 00266 /// 0x48 r/o adc_data_port_08 PIXI port 8 Analog to Digital Converter register 00267 adc_data_port_08 = 0x48, 00268 00269 /// 0x49 r/o adc_data_port_09 PIXI port 9 Analog to Digital Converter register 00270 adc_data_port_09 = 0x49, 00271 00272 /// 0x4a r/o adc_data_port_10 PIXI port 10 Analog to Digital Converter register 00273 adc_data_port_10 = 0x4a, 00274 00275 /// 0x4b r/o adc_data_port_11 PIXI port 11 Analog to Digital Converter register 00276 adc_data_port_11 = 0x4b, 00277 00278 /// 0x4c r/o adc_data_port_12 PIXI port 12 Analog to Digital Converter register 00279 adc_data_port_12 = 0x4c, 00280 00281 /// 0x4d r/o adc_data_port_13 PIXI port 13 Analog to Digital Converter register 00282 adc_data_port_13 = 0x4d, 00283 00284 /// 0x4e r/o adc_data_port_14 PIXI port 14 Analog to Digital Converter register 00285 adc_data_port_14 = 0x4e, 00286 00287 /// 0x4f r/o adc_data_port_15 PIXI port 15 Analog to Digital Converter register 00288 adc_data_port_15 = 0x4f, 00289 00290 /// 0x50 r/o adc_data_port_16 PIXI port 16 Analog to Digital Converter register 00291 adc_data_port_16 = 0x50, 00292 00293 /// 0x51 r/o adc_data_port_17 PIXI port 17 Analog to Digital Converter register 00294 adc_data_port_17 = 0x51, 00295 00296 /// 0x52 r/o adc_data_port_18 PIXI port 18 Analog to Digital Converter register 00297 adc_data_port_18 = 0x52, 00298 00299 /// 0x53 r/o adc_data_port_19 PIXI port 19 Analog to Digital Converter register 00300 adc_data_port_19 = 0x53, 00301 00302 /// 0x60 r/w dac_data_port_00 PIXI port 0 Digital to Analog Converter register 00303 dac_data_port_00 = 0x60, 00304 00305 /// 0x61 r/w dac_data_port_01 PIXI port 1 Digital to Analog Converter register 00306 dac_data_port_01 = 0x61, 00307 00308 /// 0x62 r/w dac_data_port_02 PIXI port 2 Digital to Analog Converter register 00309 dac_data_port_02 = 0x62, 00310 00311 /// 0x63 r/w dac_data_port_03 PIXI port 3 Digital to Analog Converter register 00312 dac_data_port_03 = 0x63, 00313 00314 /// 0x64 r/w dac_data_port_04 PIXI port 4 Digital to Analog Converter register 00315 dac_data_port_04 = 0x64, 00316 00317 /// 0x65 r/w dac_data_port_05 PIXI port 5 Digital to Analog Converter register 00318 dac_data_port_05 = 0x65, 00319 00320 /// 0x66 r/w dac_data_port_06 PIXI port 6 Digital to Analog Converter register 00321 dac_data_port_06 = 0x66, 00322 00323 /// 0x67 r/w dac_data_port_07 PIXI port 7 Digital to Analog Converter register 00324 dac_data_port_07 = 0x67, 00325 00326 /// 0x68 r/w dac_data_port_08 PIXI port 8 Digital to Analog Converter register 00327 dac_data_port_08 = 0x68, 00328 00329 /// 0x69 r/w dac_data_port_09 PIXI port 9 Digital to Analog Converter register 00330 dac_data_port_09 = 0x69, 00331 00332 /// 0x6a r/w dac_data_port_10 PIXI port 10 Digital to Analog Converter register 00333 dac_data_port_10 = 0x6a, 00334 00335 /// 0x6b r/w dac_data_port_11 PIXI port 11 Digital to Analog Converter register 00336 dac_data_port_11 = 0x6b, 00337 00338 /// 0x6c r/w dac_data_port_12 PIXI port 12 Digital to Analog Converter register 00339 dac_data_port_12 = 0x6c, 00340 00341 /// 0x6d r/w dac_data_port_13 PIXI port 13 Digital to Analog Converter register 00342 dac_data_port_13 = 0x6d, 00343 00344 /// 0x6e r/w dac_data_port_14 PIXI port 14 Digital to Analog Converter register 00345 dac_data_port_14 = 0x6e, 00346 00347 /// 0x6f r/w dac_data_port_15 PIXI port 15 Digital to Analog Converter register 00348 dac_data_port_15 = 0x6f, 00349 00350 /// 0x70 r/w dac_data_port_16 PIXI port 16 Digital to Analog Converter register 00351 dac_data_port_16 = 0x70, 00352 00353 /// 0x71 r/w dac_data_port_17 PIXI port 17 Digital to Analog Converter register 00354 dac_data_port_17 = 0x71, 00355 00356 /// 0x72 r/w dac_data_port_18 PIXI port 18 Digital to Analog Converter register 00357 dac_data_port_18 = 0x72, 00358 00359 /// 0x73 r/w dac_data_port_19 PIXI port 19 Digital to Analog Converter register 00360 dac_data_port_19 = 0x73, 00361 00362 } MAX11300RegAddress_t; 00363 00364 /// 0x00 r/o dev_id Device Identification 00365 /// <code>1111xxxxxxxxxxxx</code> PART Part field 00366 /// <code>xxxx11xxxxxxxxxx</code> REV Revision 00367 /// <code>xxxxxx11xxxxxxxx</code> IFMODE Inteface Mode 00368 /// <code>xxxxxxxx11xxxxxx</code> IFSP Inteface Speed 00369 /// <code>xxxxxxxxxx11xxxx</code> NBRPRTS Number of ports 00370 /// <code>xxxxxxxxxxxx11xx</code> RES Resolution 00371 /// <code>xxxxxxxxxxxxxx11</code> VRNG Voltage Range 00372 #define dev_id_PART 0xf000 00373 #define dev_id_REV 0x0c00 00374 #define dev_id_IFMODE 0x0300 00375 #define dev_id_IFSP 0x00c0 00376 #define dev_id_NBRPRTS 0x0030 00377 #define dev_id_RES 0x000c 00378 #define dev_id_VRNG 0x0003 00379 00380 /// 0x01 r/o interrupt_flag Interrupt flags 00381 /// <code>1xxxxxxxxxxxxxxx</code> VMON High Voltage Supply Monitor 00382 /// <code>x1xxxxxxxxxxxxxx</code> TMPEXT2HOT External Temperature D1P/D1N Hot 00383 /// <code>xx1xxxxxxxxxxxxx</code> TMPEXT2COLD External Temperature D1P/D1N Cold 00384 /// <code>xxx1xxxxxxxxxxxx</code> TMPEXT2NEW External Temperature D1P/D1N New 00385 /// <code>xxxx1xxxxxxxxxxx</code> TMPEXT1HOT External Temperature D0P/D0N Hot 00386 /// <code>xxxxx1xxxxxxxxxx</code> TMPEXT1COLD External Temperature D0P/D0N Cold 00387 /// <code>xxxxxx1xxxxxxxxx</code> TMPEXT1NEW External Temperature D0P/D0N New 00388 /// <code>xxxxxxx1xxxxxxxx</code> TMPINTHOT Internal Temeprature Hot 00389 /// <code>xxxxxxxx1xxxxxxx</code> TMPINTCOLD Internal Temeprature Cold 00390 /// <code>xxxxxxxxx1xxxxxx</code> TMPINTNEW Internal Temeprature New 00391 /// <code>xxxxxxxxxx1xxxxx</code> DACOI DAC over-current 00392 /// <code>xxxxxxxxxxx1xxxx</code> GPIDM GPI event missed 00393 /// <code>xxxxxxxxxxxx1xxx</code> GPIDR GPI event ready 00394 /// <code>xxxxxxxxxxxxx1xx</code> ADCDM ADC data missed 00395 /// <code>xxxxxxxxxxxxxx1x</code> ADCDR ADC data ready 00396 /// <code>xxxxxxxxxxxxxxx1</code> ADCFLAG ADC conversion/sweep complete 00397 #define interrupt_flag_VMON 0x8000 00398 #define interrupt_flag_TMPEXT2HOT 0x4000 00399 #define interrupt_flag_TMPEXT2COLD 0x2000 00400 #define interrupt_flag_TMPEXT2NEW 0x1000 00401 #define interrupt_flag_TMPEXT1HOT 0x0800 00402 #define interrupt_flag_TMPEXT1COLD 0x0400 00403 #define interrupt_flag_TMPEXT1NEW 0x0200 00404 #define interrupt_flag_TMPINTHOT 0x0100 00405 #define interrupt_flag_TMPINTCOLD 0x0080 00406 #define interrupt_flag_TMPINTNEW 0x0040 00407 #define interrupt_flag_DACOI 0x0020 00408 #define interrupt_flag_GPIDM 0x0010 00409 #define interrupt_flag_GPIDR 0x0008 00410 #define interrupt_flag_ADCDM 0x0004 00411 #define interrupt_flag_ADCDR 0x0002 00412 #define interrupt_flag_ADCFLAG 0x0001 00413 00414 /// 0x02 r/o adc_status_15_to_0 new ADC data available 00415 /// <code>1xxxxxxxxxxxxxxx</code> ADCST15 ADCST[15] new <see cref="adc_data_port_15"/> 00416 /// <code>x1xxxxxxxxxxxxxx</code> ADCST14 ADCST[14] new <see cref="adc_data_port_14"/> 00417 /// <code>xx1xxxxxxxxxxxxx</code> ADCST13 ADCST[13] new <see cref="adc_data_port_13"/> 00418 /// <code>xxx1xxxxxxxxxxxx</code> ADCST12 ADCST[12] new <see cref="adc_data_port_12"/> 00419 /// <code>xxxx1xxxxxxxxxxx</code> ADCST11 ADCST[11] new <see cref="adc_data_port_11"/> 00420 /// <code>xxxxx1xxxxxxxxxx</code> ADCST10 ADCST[10] new <see cref="adc_data_port_10"/> 00421 /// <code>xxxxxx1xxxxxxxxx</code> ADCST09 ADCST[9] new <see cref="adc_data_port_09"/> 00422 /// <code>xxxxxxx1xxxxxxxx</code> ADCST08 ADCST[8] new <see cref="adc_data_port_08"/> 00423 /// <code>xxxxxxxx1xxxxxxx</code> ADCST07 ADCST[7] new <see cref="adc_data_port_07"/> 00424 /// <code>xxxxxxxxx1xxxxxx</code> ADCST06 ADCST[6] new <see cref="adc_data_port_06"/> 00425 /// <code>xxxxxxxxxx1xxxxx</code> ADCST05 ADCST[5] new <see cref="adc_data_port_05"/> 00426 /// <code>xxxxxxxxxxx1xxxx</code> ADCST04 ADCST[4] new <see cref="adc_data_port_04"/> 00427 /// <code>xxxxxxxxxxxx1xxx</code> ADCST03 ADCST[3] new <see cref="adc_data_port_03"/> 00428 /// <code>xxxxxxxxxxxxx1xx</code> ADCST02 ADCST[2] new <see cref="adc_data_port_02"/> 00429 /// <code>xxxxxxxxxxxxxx1x</code> ADCST01 ADCST[1] new <see cref="adc_data_port_01"/> 00430 /// <code>xxxxxxxxxxxxxxx1</code> ADCST00 ADCST[0] new <see cref="adc_data_port_00"/> 00431 #define adc_status_15_to_0_ADCST15 0x8000 00432 #define adc_status_15_to_0_ADCST14 0x4000 00433 #define adc_status_15_to_0_ADCST13 0x2000 00434 #define adc_status_15_to_0_ADCST12 0x1000 00435 #define adc_status_15_to_0_ADCST11 0x0800 00436 #define adc_status_15_to_0_ADCST10 0x0400 00437 #define adc_status_15_to_0_ADCST09 0x0200 00438 #define adc_status_15_to_0_ADCST08 0x0100 00439 #define adc_status_15_to_0_ADCST07 0x0080 00440 #define adc_status_15_to_0_ADCST06 0x0040 00441 #define adc_status_15_to_0_ADCST05 0x0020 00442 #define adc_status_15_to_0_ADCST04 0x0010 00443 #define adc_status_15_to_0_ADCST03 0x0008 00444 #define adc_status_15_to_0_ADCST02 0x0004 00445 #define adc_status_15_to_0_ADCST01 0x0002 00446 #define adc_status_15_to_0_ADCST00 0x0001 00447 00448 /// 0x03 r/o adc_status_19_to_16 new ADC data available 00449 /// <code>1xxxxxxxxxxxxxxx</code> ADCST31 ADCST[31] new <see cref="adc_data_port_31"/> 00450 /// <code>x1xxxxxxxxxxxxxx</code> ADCST30 ADCST[30] new <see cref="adc_data_port_30"/> 00451 /// <code>xx1xxxxxxxxxxxxx</code> ADCST29 ADCST[29] new <see cref="adc_data_port_29"/> 00452 /// <code>xxx1xxxxxxxxxxxx</code> ADCST28 ADCST[28] new <see cref="adc_data_port_28"/> 00453 /// <code>xxxx1xxxxxxxxxxx</code> ADCST27 ADCST[27] new <see cref="adc_data_port_27"/> 00454 /// <code>xxxxx1xxxxxxxxxx</code> ADCST26 ADCST[26] new <see cref="adc_data_port_26"/> 00455 /// <code>xxxxxx1xxxxxxxxx</code> ADCST25 ADCST[25] new <see cref="adc_data_port_25"/> 00456 /// <code>xxxxxxx1xxxxxxxx</code> ADCST24 ADCST[24] new <see cref="adc_data_port_24"/> 00457 /// <code>xxxxxxxx1xxxxxxx</code> ADCST23 ADCST[23] new <see cref="adc_data_port_23"/> 00458 /// <code>xxxxxxxxx1xxxxxx</code> ADCST22 ADCST[22] new <see cref="adc_data_port_22"/> 00459 /// <code>xxxxxxxxxx1xxxxx</code> ADCST21 ADCST[21] new <see cref="adc_data_port_21"/> 00460 /// <code>xxxxxxxxxxx1xxxx</code> ADCST20 ADCST[20] new <see cref="adc_data_port_20"/> 00461 /// <code>xxxxxxxxxxxx1xxx</code> ADCST19 ADCST[19] new <see cref="adc_data_port_19"/> 00462 /// <code>xxxxxxxxxxxxx1xx</code> ADCST18 ADCST[18] new <see cref="adc_data_port_18"/> 00463 /// <code>xxxxxxxxxxxxxx1x</code> ADCST17 ADCST[17] new <see cref="adc_data_port_17"/> 00464 /// <code>xxxxxxxxxxxxxxx1</code> ADCST16 ADCST[16] new <see cref="adc_data_port_16"/> 00465 #define adc_status_19_to_16_ADCST31 0x8000 00466 #define adc_status_19_to_16_ADCST30 0x4000 00467 #define adc_status_19_to_16_ADCST29 0x2000 00468 #define adc_status_19_to_16_ADCST28 0x1000 00469 #define adc_status_19_to_16_ADCST27 0x0800 00470 #define adc_status_19_to_16_ADCST26 0x0400 00471 #define adc_status_19_to_16_ADCST25 0x0200 00472 #define adc_status_19_to_16_ADCST24 0x0100 00473 #define adc_status_19_to_16_ADCST23 0x0080 00474 #define adc_status_19_to_16_ADCST22 0x0040 00475 #define adc_status_19_to_16_ADCST21 0x0020 00476 #define adc_status_19_to_16_ADCST20 0x0010 00477 #define adc_status_19_to_16_ADCST19 0x0008 00478 #define adc_status_19_to_16_ADCST18 0x0004 00479 #define adc_status_19_to_16_ADCST17 0x0002 00480 #define adc_status_19_to_16_ADCST16 0x0001 00481 00482 /// 0x04 r/o dac_oi_status_15_to_0 DAC Overcurrent Interrupt 00483 /// <code>1xxxxxxxxxxxxxxx</code> DACOIST15 DACOIST[15] new <see cref="dac_data_port_15"/> 00484 /// <code>x1xxxxxxxxxxxxxx</code> DACOIST14 DACOIST[14] new <see cref="dac_data_port_14"/> 00485 /// <code>xx1xxxxxxxxxxxxx</code> DACOIST13 DACOIST[13] new <see cref="dac_data_port_13"/> 00486 /// <code>xxx1xxxxxxxxxxxx</code> DACOIST12 DACOIST[12] new <see cref="dac_data_port_12"/> 00487 /// <code>xxxx1xxxxxxxxxxx</code> DACOIST11 DACOIST[11] new <see cref="dac_data_port_11"/> 00488 /// <code>xxxxx1xxxxxxxxxx</code> DACOIST10 DACOIST[10] new <see cref="dac_data_port_10"/> 00489 /// <code>xxxxxx1xxxxxxxxx</code> DACOIST09 DACOIST[9] new <see cref="dac_data_port_09"/> 00490 /// <code>xxxxxxx1xxxxxxxx</code> DACOIST08 DACOIST[8] new <see cref="dac_data_port_08"/> 00491 /// <code>xxxxxxxx1xxxxxxx</code> DACOIST07 DACOIST[7] new <see cref="dac_data_port_07"/> 00492 /// <code>xxxxxxxxx1xxxxxx</code> DACOIST06 DACOIST[6] new <see cref="dac_data_port_06"/> 00493 /// <code>xxxxxxxxxx1xxxxx</code> DACOIST05 DACOIST[5] new <see cref="dac_data_port_05"/> 00494 /// <code>xxxxxxxxxxx1xxxx</code> DACOIST04 DACOIST[4] new <see cref="dac_data_port_04"/> 00495 /// <code>xxxxxxxxxxxx1xxx</code> DACOIST03 DACOIST[3] new <see cref="dac_data_port_03"/> 00496 /// <code>xxxxxxxxxxxxx1xx</code> DACOIST02 DACOIST[2] new <see cref="dac_data_port_02"/> 00497 /// <code>xxxxxxxxxxxxxx1x</code> DACOIST01 DACOIST[1] new <see cref="dac_data_port_01"/> 00498 /// <code>xxxxxxxxxxxxxxx1</code> DACOIST00 DACOIST[0] new <see cref="dac_data_port_00"/> 00499 #define dac_oi_status_15_to_0_DACOIST15 0x8000 00500 #define dac_oi_status_15_to_0_DACOIST14 0x4000 00501 #define dac_oi_status_15_to_0_DACOIST13 0x2000 00502 #define dac_oi_status_15_to_0_DACOIST12 0x1000 00503 #define dac_oi_status_15_to_0_DACOIST11 0x0800 00504 #define dac_oi_status_15_to_0_DACOIST10 0x0400 00505 #define dac_oi_status_15_to_0_DACOIST09 0x0200 00506 #define dac_oi_status_15_to_0_DACOIST08 0x0100 00507 #define dac_oi_status_15_to_0_DACOIST07 0x0080 00508 #define dac_oi_status_15_to_0_DACOIST06 0x0040 00509 #define dac_oi_status_15_to_0_DACOIST05 0x0020 00510 #define dac_oi_status_15_to_0_DACOIST04 0x0010 00511 #define dac_oi_status_15_to_0_DACOIST03 0x0008 00512 #define dac_oi_status_15_to_0_DACOIST02 0x0004 00513 #define dac_oi_status_15_to_0_DACOIST01 0x0002 00514 #define dac_oi_status_15_to_0_DACOIST00 0x0001 00515 00516 /// 0x05 r/o dac_oi_status_19_to_16 DAC Overcurrent Interrupt 00517 /// <code>1xxxxxxxxxxxxxxx</code> DACOIST31 DACOIST[31] new <see cref="dac_data_port_31"/> 00518 /// <code>x1xxxxxxxxxxxxxx</code> DACOIST30 DACOIST[30] new <see cref="dac_data_port_30"/> 00519 /// <code>xx1xxxxxxxxxxxxx</code> DACOIST29 DACOIST[29] new <see cref="dac_data_port_29"/> 00520 /// <code>xxx1xxxxxxxxxxxx</code> DACOIST28 DACOIST[28] new <see cref="dac_data_port_28"/> 00521 /// <code>xxxx1xxxxxxxxxxx</code> DACOIST27 DACOIST[27] new <see cref="dac_data_port_27"/> 00522 /// <code>xxxxx1xxxxxxxxxx</code> DACOIST26 DACOIST[26] new <see cref="dac_data_port_26"/> 00523 /// <code>xxxxxx1xxxxxxxxx</code> DACOIST25 DACOIST[25] new <see cref="dac_data_port_25"/> 00524 /// <code>xxxxxxx1xxxxxxxx</code> DACOIST24 DACOIST[24] new <see cref="dac_data_port_24"/> 00525 /// <code>xxxxxxxx1xxxxxxx</code> DACOIST23 DACOIST[23] new <see cref="dac_data_port_23"/> 00526 /// <code>xxxxxxxxx1xxxxxx</code> DACOIST22 DACOIST[22] new <see cref="dac_data_port_22"/> 00527 /// <code>xxxxxxxxxx1xxxxx</code> DACOIST21 DACOIST[21] new <see cref="dac_data_port_21"/> 00528 /// <code>xxxxxxxxxxx1xxxx</code> DACOIST20 DACOIST[20] new <see cref="dac_data_port_20"/> 00529 /// <code>xxxxxxxxxxxx1xxx</code> DACOIST19 DACOIST[19] new <see cref="dac_data_port_19"/> 00530 /// <code>xxxxxxxxxxxxx1xx</code> DACOIST18 DACOIST[18] new <see cref="dac_data_port_18"/> 00531 /// <code>xxxxxxxxxxxxxx1x</code> DACOIST17 DACOIST[17] new <see cref="dac_data_port_17"/> 00532 /// <code>xxxxxxxxxxxxxxx1</code> DACOIST16 DACOIST[16] new <see cref="dac_data_port_16"/> 00533 #define dac_oi_status_19_to_16_DACOIST31 0x8000 00534 #define dac_oi_status_19_to_16_DACOIST30 0x4000 00535 #define dac_oi_status_19_to_16_DACOIST29 0x2000 00536 #define dac_oi_status_19_to_16_DACOIST28 0x1000 00537 #define dac_oi_status_19_to_16_DACOIST27 0x0800 00538 #define dac_oi_status_19_to_16_DACOIST26 0x0400 00539 #define dac_oi_status_19_to_16_DACOIST25 0x0200 00540 #define dac_oi_status_19_to_16_DACOIST24 0x0100 00541 #define dac_oi_status_19_to_16_DACOIST23 0x0080 00542 #define dac_oi_status_19_to_16_DACOIST22 0x0040 00543 #define dac_oi_status_19_to_16_DACOIST21 0x0020 00544 #define dac_oi_status_19_to_16_DACOIST20 0x0010 00545 #define dac_oi_status_19_to_16_DACOIST19 0x0008 00546 #define dac_oi_status_19_to_16_DACOIST18 0x0004 00547 #define dac_oi_status_19_to_16_DACOIST17 0x0002 00548 #define dac_oi_status_19_to_16_DACOIST16 0x0001 00549 00550 /// 0x06 r/o gpi_status_15_to_0 GPI event ready 00551 /// <code>1xxxxxxxxxxxxxxx</code> GPIST15 GPIST[15] 00552 /// <code>x1xxxxxxxxxxxxxx</code> GPIST14 GPIST[14] 00553 /// <code>xx1xxxxxxxxxxxxx</code> GPIST13 GPIST[13] 00554 /// <code>xxx1xxxxxxxxxxxx</code> GPIST12 GPIST[12] 00555 /// <code>xxxx1xxxxxxxxxxx</code> GPIST11 GPIST[11] 00556 /// <code>xxxxx1xxxxxxxxxx</code> GPIST10 GPIST[10] 00557 /// <code>xxxxxx1xxxxxxxxx</code> GPIST09 GPIST[9] 00558 /// <code>xxxxxxx1xxxxxxxx</code> GPIST08 GPIST[8] 00559 /// <code>xxxxxxxx1xxxxxxx</code> GPIST07 GPIST[7] 00560 /// <code>xxxxxxxxx1xxxxxx</code> GPIST06 GPIST[6] 00561 /// <code>xxxxxxxxxx1xxxxx</code> GPIST05 GPIST[5] 00562 /// <code>xxxxxxxxxxx1xxxx</code> GPIST04 GPIST[4] 00563 /// <code>xxxxxxxxxxxx1xxx</code> GPIST03 GPIST[3] 00564 /// <code>xxxxxxxxxxxxx1xx</code> GPIST02 GPIST[2] 00565 /// <code>xxxxxxxxxxxxxx1x</code> GPIST01 GPIST[1] 00566 /// <code>xxxxxxxxxxxxxxx1</code> GPIST00 GPIST[0] 00567 #define gpi_status_15_to_0_GPIST15 0x8000 00568 #define gpi_status_15_to_0_GPIST14 0x4000 00569 #define gpi_status_15_to_0_GPIST13 0x2000 00570 #define gpi_status_15_to_0_GPIST12 0x1000 00571 #define gpi_status_15_to_0_GPIST11 0x0800 00572 #define gpi_status_15_to_0_GPIST10 0x0400 00573 #define gpi_status_15_to_0_GPIST09 0x0200 00574 #define gpi_status_15_to_0_GPIST08 0x0100 00575 #define gpi_status_15_to_0_GPIST07 0x0080 00576 #define gpi_status_15_to_0_GPIST06 0x0040 00577 #define gpi_status_15_to_0_GPIST05 0x0020 00578 #define gpi_status_15_to_0_GPIST04 0x0010 00579 #define gpi_status_15_to_0_GPIST03 0x0008 00580 #define gpi_status_15_to_0_GPIST02 0x0004 00581 #define gpi_status_15_to_0_GPIST01 0x0002 00582 #define gpi_status_15_to_0_GPIST00 0x0001 00583 00584 /// 0x07 r/o gpi_status_19_to_16 GPI event ready 00585 /// <code>1xxxxxxxxxxxxxxx</code> GPIST31 GPIST[31] 00586 /// <code>x1xxxxxxxxxxxxxx</code> GPIST30 GPIST[30] 00587 /// <code>xx1xxxxxxxxxxxxx</code> GPIST29 GPIST[29] 00588 /// <code>xxx1xxxxxxxxxxxx</code> GPIST28 GPIST[28] 00589 /// <code>xxxx1xxxxxxxxxxx</code> GPIST27 GPIST[27] 00590 /// <code>xxxxx1xxxxxxxxxx</code> GPIST26 GPIST[26] 00591 /// <code>xxxxxx1xxxxxxxxx</code> GPIST25 GPIST[25] 00592 /// <code>xxxxxxx1xxxxxxxx</code> GPIST24 GPIST[24] 00593 /// <code>xxxxxxxx1xxxxxxx</code> GPIST23 GPIST[23] 00594 /// <code>xxxxxxxxx1xxxxxx</code> GPIST22 GPIST[22] 00595 /// <code>xxxxxxxxxx1xxxxx</code> GPIST21 GPIST[21] 00596 /// <code>xxxxxxxxxxx1xxxx</code> GPIST20 GPIST[20] 00597 /// <code>xxxxxxxxxxxx1xxx</code> GPIST19 GPIST[19] 00598 /// <code>xxxxxxxxxxxxx1xx</code> GPIST18 GPIST[18] 00599 /// <code>xxxxxxxxxxxxxx1x</code> GPIST17 GPIST[17] 00600 /// <code>xxxxxxxxxxxxxxx1</code> GPIST16 GPIST[16] 00601 #define gpi_status_19_to_16_GPIST31 0x8000 00602 #define gpi_status_19_to_16_GPIST30 0x4000 00603 #define gpi_status_19_to_16_GPIST29 0x2000 00604 #define gpi_status_19_to_16_GPIST28 0x1000 00605 #define gpi_status_19_to_16_GPIST27 0x0800 00606 #define gpi_status_19_to_16_GPIST26 0x0400 00607 #define gpi_status_19_to_16_GPIST25 0x0200 00608 #define gpi_status_19_to_16_GPIST24 0x0100 00609 #define gpi_status_19_to_16_GPIST23 0x0080 00610 #define gpi_status_19_to_16_GPIST22 0x0040 00611 #define gpi_status_19_to_16_GPIST21 0x0020 00612 #define gpi_status_19_to_16_GPIST20 0x0010 00613 #define gpi_status_19_to_16_GPIST19 0x0008 00614 #define gpi_status_19_to_16_GPIST18 0x0004 00615 #define gpi_status_19_to_16_GPIST17 0x0002 00616 #define gpi_status_19_to_16_GPIST16 0x0001 00617 00618 /// 0x08 r/o tmp_int_data Internal Temeprature 00619 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement 00620 #define tmp_int_data_tempcode 0x0fff 00621 00622 /// 0x09 r/o tmp_ext1_data External Temperature D0P/D0N 00623 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement 00624 #define tmp_ext1_data_tempcode 0x0fff 00625 00626 /// 0x0a r/o tmp_ext2_data External Temperature D1P/D1N 00627 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement 00628 #define tmp_ext2_data_tempcode 0x0fff 00629 00630 /// 0x0b r/o gpi_data_15_to_0 GPI input ports data 00631 /// <code>1xxxxxxxxxxxxxxx</code> GPIDAT15 GPIDAT[15] 00632 /// <code>x1xxxxxxxxxxxxxx</code> GPIDAT14 GPIDAT[14] 00633 /// <code>xx1xxxxxxxxxxxxx</code> GPIDAT13 GPIDAT[13] 00634 /// <code>xxx1xxxxxxxxxxxx</code> GPIDAT12 GPIDAT[12] 00635 /// <code>xxxx1xxxxxxxxxxx</code> GPIDAT11 GPIDAT[11] 00636 /// <code>xxxxx1xxxxxxxxxx</code> GPIDAT10 GPIDAT[10] 00637 /// <code>xxxxxx1xxxxxxxxx</code> GPIDAT09 GPIDAT[9] 00638 /// <code>xxxxxxx1xxxxxxxx</code> GPIDAT08 GPIDAT[8] 00639 /// <code>xxxxxxxx1xxxxxxx</code> GPIDAT07 GPIDAT[7] 00640 /// <code>xxxxxxxxx1xxxxxx</code> GPIDAT06 GPIDAT[6] 00641 /// <code>xxxxxxxxxx1xxxxx</code> GPIDAT05 GPIDAT[5] 00642 /// <code>xxxxxxxxxxx1xxxx</code> GPIDAT04 GPIDAT[4] 00643 /// <code>xxxxxxxxxxxx1xxx</code> GPIDAT03 GPIDAT[3] 00644 /// <code>xxxxxxxxxxxxx1xx</code> GPIDAT02 GPIDAT[2] 00645 /// <code>xxxxxxxxxxxxxx1x</code> GPIDAT01 GPIDAT[1] 00646 /// <code>xxxxxxxxxxxxxxx1</code> GPIDAT00 GPIDAT[0] 00647 #define gpi_data_15_to_0_GPIDAT15 0x8000 00648 #define gpi_data_15_to_0_GPIDAT14 0x4000 00649 #define gpi_data_15_to_0_GPIDAT13 0x2000 00650 #define gpi_data_15_to_0_GPIDAT12 0x1000 00651 #define gpi_data_15_to_0_GPIDAT11 0x0800 00652 #define gpi_data_15_to_0_GPIDAT10 0x0400 00653 #define gpi_data_15_to_0_GPIDAT09 0x0200 00654 #define gpi_data_15_to_0_GPIDAT08 0x0100 00655 #define gpi_data_15_to_0_GPIDAT07 0x0080 00656 #define gpi_data_15_to_0_GPIDAT06 0x0040 00657 #define gpi_data_15_to_0_GPIDAT05 0x0020 00658 #define gpi_data_15_to_0_GPIDAT04 0x0010 00659 #define gpi_data_15_to_0_GPIDAT03 0x0008 00660 #define gpi_data_15_to_0_GPIDAT02 0x0004 00661 #define gpi_data_15_to_0_GPIDAT01 0x0002 00662 #define gpi_data_15_to_0_GPIDAT00 0x0001 00663 00664 /// 0x0c r/o gpi_data_19_to_16 GPI input ports data 00665 /// <code>1xxxxxxxxxxxxxxx</code> GPIDAT31 GPIDAT[31] 00666 /// <code>x1xxxxxxxxxxxxxx</code> GPIDAT30 GPIDAT[30] 00667 /// <code>xx1xxxxxxxxxxxxx</code> GPIDAT29 GPIDAT[29] 00668 /// <code>xxx1xxxxxxxxxxxx</code> GPIDAT28 GPIDAT[28] 00669 /// <code>xxxx1xxxxxxxxxxx</code> GPIDAT27 GPIDAT[27] 00670 /// <code>xxxxx1xxxxxxxxxx</code> GPIDAT26 GPIDAT[26] 00671 /// <code>xxxxxx1xxxxxxxxx</code> GPIDAT25 GPIDAT[25] 00672 /// <code>xxxxxxx1xxxxxxxx</code> GPIDAT24 GPIDAT[24] 00673 /// <code>xxxxxxxx1xxxxxxx</code> GPIDAT23 GPIDAT[23] 00674 /// <code>xxxxxxxxx1xxxxxx</code> GPIDAT22 GPIDAT[22] 00675 /// <code>xxxxxxxxxx1xxxxx</code> GPIDAT21 GPIDAT[21] 00676 /// <code>xxxxxxxxxxx1xxxx</code> GPIDAT20 GPIDAT[20] 00677 /// <code>xxxxxxxxxxxx1xxx</code> GPIDAT19 GPIDAT[19] 00678 /// <code>xxxxxxxxxxxxx1xx</code> GPIDAT18 GPIDAT[18] 00679 /// <code>xxxxxxxxxxxxxx1x</code> GPIDAT17 GPIDAT[17] 00680 /// <code>xxxxxxxxxxxxxxx1</code> GPIDAT16 GPIDAT[16] 00681 #define gpi_data_19_to_16_GPIDAT31 0x8000 00682 #define gpi_data_19_to_16_GPIDAT30 0x4000 00683 #define gpi_data_19_to_16_GPIDAT29 0x2000 00684 #define gpi_data_19_to_16_GPIDAT28 0x1000 00685 #define gpi_data_19_to_16_GPIDAT27 0x0800 00686 #define gpi_data_19_to_16_GPIDAT26 0x0400 00687 #define gpi_data_19_to_16_GPIDAT25 0x0200 00688 #define gpi_data_19_to_16_GPIDAT24 0x0100 00689 #define gpi_data_19_to_16_GPIDAT23 0x0080 00690 #define gpi_data_19_to_16_GPIDAT22 0x0040 00691 #define gpi_data_19_to_16_GPIDAT21 0x0020 00692 #define gpi_data_19_to_16_GPIDAT20 0x0010 00693 #define gpi_data_19_to_16_GPIDAT19 0x0008 00694 #define gpi_data_19_to_16_GPIDAT18 0x0004 00695 #define gpi_data_19_to_16_GPIDAT17 0x0002 00696 #define gpi_data_19_to_16_GPIDAT16 0x0001 00697 00698 /// 0x0d r/w gpo_data_15_to_0 GPO output ports data 00699 /// <code>1xxxxxxxxxxxxxxx</code> GPODAT15 GPODAT[15] 00700 /// <code>x1xxxxxxxxxxxxxx</code> GPODAT14 GPODAT[14] 00701 /// <code>xx1xxxxxxxxxxxxx</code> GPODAT13 GPODAT[13] 00702 /// <code>xxx1xxxxxxxxxxxx</code> GPODAT12 GPODAT[12] 00703 /// <code>xxxx1xxxxxxxxxxx</code> GPODAT11 GPODAT[11] 00704 /// <code>xxxxx1xxxxxxxxxx</code> GPODAT10 GPODAT[10] 00705 /// <code>xxxxxx1xxxxxxxxx</code> GPODAT09 GPODAT[9] 00706 /// <code>xxxxxxx1xxxxxxxx</code> GPODAT08 GPODAT[8] 00707 /// <code>xxxxxxxx1xxxxxxx</code> GPODAT07 GPODAT[7] 00708 /// <code>xxxxxxxxx1xxxxxx</code> GPODAT06 GPODAT[6] 00709 /// <code>xxxxxxxxxx1xxxxx</code> GPODAT05 GPODAT[5] 00710 /// <code>xxxxxxxxxxx1xxxx</code> GPODAT04 GPODAT[4] 00711 /// <code>xxxxxxxxxxxx1xxx</code> GPODAT03 GPODAT[3] 00712 /// <code>xxxxxxxxxxxxx1xx</code> GPODAT02 GPODAT[2] 00713 /// <code>xxxxxxxxxxxxxx1x</code> GPODAT01 GPODAT[1] 00714 /// <code>xxxxxxxxxxxxxxx1</code> GPODAT00 GPODAT[0] 00715 #define gpo_data_15_to_0_GPODAT15 0x8000 00716 #define gpo_data_15_to_0_GPODAT14 0x4000 00717 #define gpo_data_15_to_0_GPODAT13 0x2000 00718 #define gpo_data_15_to_0_GPODAT12 0x1000 00719 #define gpo_data_15_to_0_GPODAT11 0x0800 00720 #define gpo_data_15_to_0_GPODAT10 0x0400 00721 #define gpo_data_15_to_0_GPODAT09 0x0200 00722 #define gpo_data_15_to_0_GPODAT08 0x0100 00723 #define gpo_data_15_to_0_GPODAT07 0x0080 00724 #define gpo_data_15_to_0_GPODAT06 0x0040 00725 #define gpo_data_15_to_0_GPODAT05 0x0020 00726 #define gpo_data_15_to_0_GPODAT04 0x0010 00727 #define gpo_data_15_to_0_GPODAT03 0x0008 00728 #define gpo_data_15_to_0_GPODAT02 0x0004 00729 #define gpo_data_15_to_0_GPODAT01 0x0002 00730 #define gpo_data_15_to_0_GPODAT00 0x0001 00731 #define gpo_data_15_to_0_DESIGNVALUE 0x0000 00732 00733 /// 0x0e r/w gpo_data_19_to_16 GPO output ports data 00734 /// <code>1xxxxxxxxxxxxxxx</code> GPODAT31 GPODAT[31] 00735 /// <code>x1xxxxxxxxxxxxxx</code> GPODAT30 GPODAT[30] 00736 /// <code>xx1xxxxxxxxxxxxx</code> GPODAT29 GPODAT[29] 00737 /// <code>xxx1xxxxxxxxxxxx</code> GPODAT28 GPODAT[28] 00738 /// <code>xxxx1xxxxxxxxxxx</code> GPODAT27 GPODAT[27] 00739 /// <code>xxxxx1xxxxxxxxxx</code> GPODAT26 GPODAT[26] 00740 /// <code>xxxxxx1xxxxxxxxx</code> GPODAT25 GPODAT[25] 00741 /// <code>xxxxxxx1xxxxxxxx</code> GPODAT24 GPODAT[24] 00742 /// <code>xxxxxxxx1xxxxxxx</code> GPODAT23 GPODAT[23] 00743 /// <code>xxxxxxxxx1xxxxxx</code> GPODAT22 GPODAT[22] 00744 /// <code>xxxxxxxxxx1xxxxx</code> GPODAT21 GPODAT[21] 00745 /// <code>xxxxxxxxxxx1xxxx</code> GPODAT20 GPODAT[20] 00746 /// <code>xxxxxxxxxxxx1xxx</code> GPODAT19 GPODAT[19] 00747 /// <code>xxxxxxxxxxxxx1xx</code> GPODAT18 GPODAT[18] 00748 /// <code>xxxxxxxxxxxxxx1x</code> GPODAT17 GPODAT[17] 00749 /// <code>xxxxxxxxxxxxxxx1</code> GPODAT16 GPODAT[16] 00750 #define gpo_data_19_to_16_GPODAT31 0x8000 00751 #define gpo_data_19_to_16_GPODAT30 0x4000 00752 #define gpo_data_19_to_16_GPODAT29 0x2000 00753 #define gpo_data_19_to_16_GPODAT28 0x1000 00754 #define gpo_data_19_to_16_GPODAT27 0x0800 00755 #define gpo_data_19_to_16_GPODAT26 0x0400 00756 #define gpo_data_19_to_16_GPODAT25 0x0200 00757 #define gpo_data_19_to_16_GPODAT24 0x0100 00758 #define gpo_data_19_to_16_GPODAT23 0x0080 00759 #define gpo_data_19_to_16_GPODAT22 0x0040 00760 #define gpo_data_19_to_16_GPODAT21 0x0020 00761 #define gpo_data_19_to_16_GPODAT20 0x0010 00762 #define gpo_data_19_to_16_GPODAT19 0x0008 00763 #define gpo_data_19_to_16_GPODAT18 0x0004 00764 #define gpo_data_19_to_16_GPODAT17 0x0002 00765 #define gpo_data_19_to_16_GPODAT16 0x0001 00766 #define gpo_data_19_to_16_DESIGNVALUE 0x0000 00767 00768 /// 0x0f r/o reserved_0F reserved 00769 00770 00771 /// 0x10 r/w device_control Global device control register 00772 /// <code>1xxxxxxxxxxxxxxx</code> RESET Soft reset command 00773 /// - 0 = No operation 00774 /// - 1 = Perform power-on reset. (This bit is self-clearing.) 00775 /// <code>x1xxxxxxxxxxxxxx</code> BRST Burst Mode 00776 /// - 0 = Automatically increment register address in serial interface burst mode. 00777 /// - 1 = Burst Read cycle through only the ADC data ports; 00778 /// Burst Write cycle through only the DAC data ports. 00779 /// <code>xx1xxxxxxxxxxxxx</code> LPEN Low Power Enable 00780 /// - 0 = Normal operation 00781 /// - 1 = Sleep mode 00782 /// <code>xxx1xxxxxxxxxxxx</code> RS_CANCEL series resistance cancelation on external temperature monitors D0P/D0N and D1P/D1N 00783 /// - 0 = Disable series resistance cancelation on external temperature monitors D0P/D0N and D1P/D1N 00784 /// - 1 = Enable series resistance cancelation on external temperature monitors D0P/D0N and D1P/D1N 00785 /// <code>xxxx1xxxxxxxxxxx</code> TMPPER temperature monitor period 00786 /// - 0 = min IH period is 32.5μsec, hold time of SAMPLE is 7μsec. 00787 /// - 1 = min IH period is 65.0μsec, hold time of SAMPLE is 15μsec. 00788 /// <code>xxxxx1xxxxxxxxxx</code> TMPCTLEXT1 monitor external temperature D1P/D1N 00789 /// <code>xxxxxx1xxxxxxxxx</code> TMPCTLEXT0 monitor external temperature D0P/D0N 00790 /// <code>xxxxxxx1xxxxxxxx</code> TMPCTLINT monitor internal temperature 00791 /// <code>xxxxxxxx1xxxxxxx</code> THSHDN Thermal Shutdown 00792 /// - 0 = Disable Thermal Shutdown 00793 /// - 1 = Enable Thermal Shutdown: reset all ports to hi-Z if <see cref="tmp_int_data"/> is greater than 145 degrees C 00794 /// <code>xxxxxxxxx1xxxxxx</code> DACREF DAC voltage reference 00795 /// - 0 = External DAC voltage reference 00796 /// - 1 = Internal DAC voltage reference 00797 /// <code>xxxxxxxxxx11xxxx</code> ADCCONV ADC conversion rate 00798 /// - 0 = 200Ksps 00799 /// - 1 = 250Ksps 00800 /// - 2 = 333Ksps 00801 /// - 3 = 400Ksps 00802 /// <code>xxxxxxxxxxxx11xx</code> DACCTL DAC update mode 00803 /// - 0 = Update DAC values in normal sequence 00804 /// - 1 = Update DAC immediately after dac_data_port_xx write 00805 /// - 2 = All DAC data registers loaded with <see cref="dac_preset_data_1"/> 00806 /// - 3 = All DAC data registers loaded with <see cref="dac_preset_data_2"/> 00807 /// <code>xxxxxxxxxxxxxx11</code> ADCCTL ADC conversion mode 00808 /// - 0 = Idle mode 00809 /// - 1 = Single sweep triggered by CNVTB pin 00810 /// - 2 = Single conversion triggered by CNVTB pin 00811 /// - 3 = Continuous sweep 00812 #define device_control_RESET 0x8000 00813 #define device_control_BRST 0x4000 00814 #define device_control_LPEN 0x2000 00815 #define device_control_RS_CANCEL 0x1000 00816 #define device_control_TMPPER 0x0800 00817 #define device_control_TMPCTLEXT1 0x0400 00818 #define device_control_TMPCTLEXT0 0x0200 00819 #define device_control_TMPCTLINT 0x0100 00820 #define device_control_THSHDN 0x0080 00821 #define device_control_DACREF 0x0040 00822 #define device_control_ADCCONV 0x0030 00823 #define device_control_DACCTL 0x000c 00824 #define device_control_ADCCTL 0x0003 00825 #define device_control_DESIGNVALUE 0x00c6 00826 00827 /// 0x11 r/w interrupt_mask interrupt mask (1 = disable interrupt source) 00828 /// <code>1xxxxxxxxxxxxxxx</code> VMON High Voltage Supply Monitor 00829 /// <code>x1xxxxxxxxxxxxxx</code> TMPEXT2HOT External Temperature D1P/D1N Hot 00830 /// <code>xx1xxxxxxxxxxxxx</code> TMPEXT2COLD External Temperature D1P/D1N Cold 00831 /// <code>xxx1xxxxxxxxxxxx</code> TMPEXT2NEW External Temperature D1P/D1N New 00832 /// <code>xxxx1xxxxxxxxxxx</code> TMPEXT1HOT External Temperature D0P/D0N Hot 00833 /// <code>xxxxx1xxxxxxxxxx</code> TMPEXT1COLD External Temperature D0P/D0N Cold 00834 /// <code>xxxxxx1xxxxxxxxx</code> TMPEXT1NEW External Temperature D0P/D0N New 00835 /// <code>xxxxxxx1xxxxxxxx</code> TMPINTHOT Internal Temeprature Hot 00836 /// <code>xxxxxxxx1xxxxxxx</code> TMPINTCOLD Internal Temeprature Cold 00837 /// <code>xxxxxxxxx1xxxxxx</code> TMPINTNEW Internal Temeprature New 00838 /// <code>xxxxxxxxxx1xxxxx</code> DACOI DAC over-current 00839 /// <code>xxxxxxxxxxx1xxxx</code> GPIDM GPI event missed 00840 /// <code>xxxxxxxxxxxx1xxx</code> GPIDR GPI event ready 00841 /// <code>xxxxxxxxxxxxx1xx</code> ADCDM ADC data missed 00842 /// <code>xxxxxxxxxxxxxx1x</code> ADCDR ADC data ready 00843 /// <code>xxxxxxxxxxxxxxx1</code> ADCFLAG ADC conversion/sweep complete 00844 #define interrupt_mask_VMON 0x8000 00845 #define interrupt_mask_TMPEXT2HOT 0x4000 00846 #define interrupt_mask_TMPEXT2COLD 0x2000 00847 #define interrupt_mask_TMPEXT2NEW 0x1000 00848 #define interrupt_mask_TMPEXT1HOT 0x0800 00849 #define interrupt_mask_TMPEXT1COLD 0x0400 00850 #define interrupt_mask_TMPEXT1NEW 0x0200 00851 #define interrupt_mask_TMPINTHOT 0x0100 00852 #define interrupt_mask_TMPINTCOLD 0x0080 00853 #define interrupt_mask_TMPINTNEW 0x0040 00854 #define interrupt_mask_DACOI 0x0020 00855 #define interrupt_mask_GPIDM 0x0010 00856 #define interrupt_mask_GPIDR 0x0008 00857 #define interrupt_mask_ADCDM 0x0004 00858 #define interrupt_mask_ADCDR 0x0002 00859 #define interrupt_mask_ADCFLAG 0x0001 00860 #define interrupt_mask_DESIGNVALUE 0xffff 00861 00862 /// 0x12 r/w gpi_irqmode_7_to_0 GPI port 0 to 7 mode register 00863 /// <code>11xxxxxxxxxxxxxx</code> GPIMD07 GPIMD[7] 00864 /// <code>xx11xxxxxxxxxxxx</code> GPIMD06 GPIMD[6] 00865 /// <code>xxxx11xxxxxxxxxx</code> GPIMD05 GPIMD[5] 00866 /// <code>xxxxxx11xxxxxxxx</code> GPIMD04 GPIMD[4] 00867 /// <code>xxxxxxxx11xxxxxx</code> GPIMD03 GPIMD[3] 00868 /// <code>xxxxxxxxxx11xxxx</code> GPIMD02 GPIMD[2] 00869 /// <code>xxxxxxxxxxxx11xx</code> GPIMD01 GPIMD[1] 00870 /// <code>xxxxxxxxxxxxxx11</code> GPIMD00 GPIMD[0] 00871 /// <para>GPIMD[portId] interrupt mask bits: 00872 /// - 0 = masked 00873 /// - 1 = detect positive edge 00874 /// - 2 = detect negative edge 00875 /// - 3 = detect positive or negative edge 00876 /// </para> 00877 #define gpi_irqmode_7_to_0_GPIMD07 0xc000 00878 #define gpi_irqmode_7_to_0_GPIMD06 0x3000 00879 #define gpi_irqmode_7_to_0_GPIMD05 0x0c00 00880 #define gpi_irqmode_7_to_0_GPIMD04 0x0300 00881 #define gpi_irqmode_7_to_0_GPIMD03 0x00c0 00882 #define gpi_irqmode_7_to_0_GPIMD02 0x0030 00883 #define gpi_irqmode_7_to_0_GPIMD01 0x000c 00884 #define gpi_irqmode_7_to_0_GPIMD00 0x0003 00885 #define gpi_irqmode_7_to_0_DESIGNVALUE 0x0000 00886 00887 /// 0x13 r/w gpi_irqmode_15_to_8 GPI port 8 to 15 mode register 00888 /// <code>11xxxxxxxxxxxxxx</code> GPIMD15 GPIMD[15] 00889 /// <code>xx11xxxxxxxxxxxx</code> GPIMD14 GPIMD[14] 00890 /// <code>xxxx11xxxxxxxxxx</code> GPIMD13 GPIMD[13] 00891 /// <code>xxxxxx11xxxxxxxx</code> GPIMD12 GPIMD[12] 00892 /// <code>xxxxxxxx11xxxxxx</code> GPIMD11 GPIMD[11] 00893 /// <code>xxxxxxxxxx11xxxx</code> GPIMD10 GPIMD[10] 00894 /// <code>xxxxxxxxxxxx11xx</code> GPIMD09 GPIMD[9] 00895 /// <code>xxxxxxxxxxxxxx11</code> GPIMD08 GPIMD[8] 00896 /// <para>GPIMD[portId] interrupt mask bits: 00897 /// - 0 = masked 00898 /// - 1 = detect positive edge 00899 /// - 2 = detect negative edge 00900 /// - 3 = detect positive or negative edge 00901 /// </para> 00902 #define gpi_irqmode_15_to_8_GPIMD15 0xc000 00903 #define gpi_irqmode_15_to_8_GPIMD14 0x3000 00904 #define gpi_irqmode_15_to_8_GPIMD13 0x0c00 00905 #define gpi_irqmode_15_to_8_GPIMD12 0x0300 00906 #define gpi_irqmode_15_to_8_GPIMD11 0x00c0 00907 #define gpi_irqmode_15_to_8_GPIMD10 0x0030 00908 #define gpi_irqmode_15_to_8_GPIMD09 0x000c 00909 #define gpi_irqmode_15_to_8_GPIMD08 0x0003 00910 #define gpi_irqmode_15_to_8_DESIGNVALUE 0x0000 00911 00912 /// 0x14 r/w gpi_irqmode_19_to_16 GPI port 16 to 19 mode register 00913 /// <code>11xxxxxxxxxxxxxx</code> GPIMD23 GPIMD[23] 00914 /// <code>xx11xxxxxxxxxxxx</code> GPIMD22 GPIMD[22] 00915 /// <code>xxxx11xxxxxxxxxx</code> GPIMD21 GPIMD[21] 00916 /// <code>xxxxxx11xxxxxxxx</code> GPIMD20 GPIMD[20] 00917 /// <code>xxxxxxxx11xxxxxx</code> GPIMD19 GPIMD[19] 00918 /// <code>xxxxxxxxxx11xxxx</code> GPIMD18 GPIMD[18] 00919 /// <code>xxxxxxxxxxxx11xx</code> GPIMD17 GPIMD[17] 00920 /// <code>xxxxxxxxxxxxxx11</code> GPIMD16 GPIMD[16] 00921 /// <para>GPIMD[portId] interrupt mask bits: 00922 /// - 0 = masked 00923 /// - 1 = detect positive edge 00924 /// - 2 = detect negative edge 00925 /// - 3 = detect positive or negative edge 00926 /// </para> 00927 #define gpi_irqmode_19_to_16_GPIMD23 0xc000 00928 #define gpi_irqmode_19_to_16_GPIMD22 0x3000 00929 #define gpi_irqmode_19_to_16_GPIMD21 0x0c00 00930 #define gpi_irqmode_19_to_16_GPIMD20 0x0300 00931 #define gpi_irqmode_19_to_16_GPIMD19 0x00c0 00932 #define gpi_irqmode_19_to_16_GPIMD18 0x0030 00933 #define gpi_irqmode_19_to_16_GPIMD17 0x000c 00934 #define gpi_irqmode_19_to_16_GPIMD16 0x0003 00935 #define gpi_irqmode_19_to_16_DESIGNVALUE 0x0000 00936 00937 /// 0x15 r/w gpi_irqmode_31_to_24 (reserved) 00938 /// <code>11xxxxxxxxxxxxxx</code> GPIMD31 GPIMD[31] 00939 /// <code>xx11xxxxxxxxxxxx</code> GPIMD30 GPIMD[30] 00940 /// <code>xxxx11xxxxxxxxxx</code> GPIMD29 GPIMD[29] 00941 /// <code>xxxxxx11xxxxxxxx</code> GPIMD28 GPIMD[28] 00942 /// <code>xxxxxxxx11xxxxxx</code> GPIMD27 GPIMD[27] 00943 /// <code>xxxxxxxxxx11xxxx</code> GPIMD26 GPIMD[26] 00944 /// <code>xxxxxxxxxxxx11xx</code> GPIMD25 GPIMD[25] 00945 /// <code>xxxxxxxxxxxxxx11</code> GPIMD24 GPIMD[24] 00946 /// <para>GPIMD[portId] interrupt mask bits: 00947 /// - 0 = masked 00948 /// - 1 = detect positive edge 00949 /// - 2 = detect negative edge 00950 /// - 3 = detect positive or negative edge 00951 /// </para> 00952 #define gpi_irqmode_31_to_24_GPIMD31 0xc000 00953 #define gpi_irqmode_31_to_24_GPIMD30 0x3000 00954 #define gpi_irqmode_31_to_24_GPIMD29 0x0c00 00955 #define gpi_irqmode_31_to_24_GPIMD28 0x0300 00956 #define gpi_irqmode_31_to_24_GPIMD27 0x00c0 00957 #define gpi_irqmode_31_to_24_GPIMD26 0x0030 00958 #define gpi_irqmode_31_to_24_GPIMD25 0x000c 00959 #define gpi_irqmode_31_to_24_GPIMD24 0x0003 00960 00961 /// 0x16 r/w dac_preset_data_1 DAC preset activated by <see cref="device_control"/> 00962 /// <code>xxxx111111111111</code> daccode 12-bit DAC code 00963 #define dac_preset_data_1_daccode 0x0fff 00964 #define dac_preset_data_1_DESIGNVALUE 0x0000 00965 00966 /// 0x17 r/w dac_preset_data_2 DAC preset activated by <see cref="device_control"/> 00967 /// <code>xxxx111111111111</code> daccode 12-bit DAC code 00968 #define dac_preset_data_2_daccode 0x0fff 00969 #define dac_preset_data_2_DESIGNVALUE 0x0000 00970 00971 /// 0x18 r/w tmp_mon_cfg Temperautre Monitor Configuration 00972 /// <code>xxxxxxxxxx11xxxx</code> TMPEXT2MONCFG average 4, 8, 16, or 32 measurements 00973 /// <code>xxxxxxxxxxxx11xx</code> TMPEXT1MONCFG average 4, 8, 16, or 32 measurements 00974 /// <code>xxxxxxxxxxxxxx11</code> TMPINTMONCFG average 4, 8, 16, or 32 measurements 00975 /// <para>Temperautre Monitor Configuration: 00976 /// - 0 = 4 measurements (default) 00977 /// - 1 = 8 measurements 00978 /// - 2 = 16 measurements 00979 /// - 3 = 32 measurements 00980 /// </para> 00981 #define tmp_mon_cfg_TMPEXT2MONCFG 0x0030 00982 #define tmp_mon_cfg_TMPEXT1MONCFG 0x000c 00983 #define tmp_mon_cfg_TMPINTMONCFG 0x0003 00984 #define tmp_mon_cfg_DESIGNVALUE 0x0000 00985 00986 /// 0x19 r/w tmp_mon_int_hi_thresh Internal Temeprature Hot Threshold 00987 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement 00988 #define tmp_mon_int_hi_thresh_tempcode 0x0fff 00989 #define tmp_mon_int_hi_thresh_DESIGNVALUE 0x07ff 00990 00991 /// 0x1a r/w tmp_mon_int_lo_thresh Internal Temeprature Cold Threshold 00992 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement 00993 #define tmp_mon_int_lo_thresh_tempcode 0x0fff 00994 #define tmp_mon_int_lo_thresh_DESIGNVALUE 0x0800 00995 00996 /// 0x1b r/w tmp_mon_ext1_hi_thresh External Temperature D0P/D0N Hot Threshold 00997 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement 00998 #define tmp_mon_ext1_hi_thresh_tempcode 0x0fff 00999 #define tmp_mon_ext1_hi_thresh_DESIGNVALUE 0x07ff 01000 01001 /// 0x1c r/w tmp_mon_ext1_lo_thresh External Temperature D0P/D0N Cold Threshold 01002 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement 01003 #define tmp_mon_ext1_lo_thresh_tempcode 0x0fff 01004 #define tmp_mon_ext1_lo_thresh_DESIGNVALUE 0x0800 01005 01006 /// 0x1d r/w tmp_mon_ext2_hi_thresh External Temperature D1P/D1N Hot Threshold 01007 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement 01008 #define tmp_mon_ext2_hi_thresh_tempcode 0x0fff 01009 #define tmp_mon_ext2_hi_thresh_DESIGNVALUE 0x07ff 01010 01011 /// 0x1e r/w tmp_mon_ext2_lo_thresh External Temperature D1P/D1N Cold Threshold 01012 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement 01013 #define tmp_mon_ext2_lo_thresh_tempcode 0x0fff 01014 #define tmp_mon_ext2_lo_thresh_DESIGNVALUE 0x0800 01015 01016 /// 0x1f r/w reserved_1F reserved 01017 01018 01019 /// 0x20 r/w port_cfg_00 PIXI port 0 configuration register 01020 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode 01021 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV 01022 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range 01023 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP 01024 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31 01025 #define port_cfg_00_PortCfgFuncID 0xf000 01026 #define port_cfg_00_funcprm_avrInv 0x0800 01027 #define port_cfg_00_funcprm_range 0x0700 01028 #define port_cfg_00_funcprm_nsamples 0x00e0 01029 #define port_cfg_00_funcprm_port 0x001f 01030 #define port_cfg_00_DESIGNVALUE 0x5200 01031 01032 /// 0x21 r/w port_cfg_01 PIXI port 1 configuration register 01033 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode 01034 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV 01035 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range 01036 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP 01037 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31 01038 #define port_cfg_01_PortCfgFuncID 0xf000 01039 #define port_cfg_01_funcprm_avrInv 0x0800 01040 #define port_cfg_01_funcprm_range 0x0700 01041 #define port_cfg_01_funcprm_nsamples 0x00e0 01042 #define port_cfg_01_funcprm_port 0x001f 01043 #define port_cfg_01_DESIGNVALUE 0x5200 01044 01045 /// 0x22 r/w port_cfg_02 PIXI port 2 configuration register 01046 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode 01047 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV 01048 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range 01049 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP 01050 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31 01051 #define port_cfg_02_PortCfgFuncID 0xf000 01052 #define port_cfg_02_funcprm_avrInv 0x0800 01053 #define port_cfg_02_funcprm_range 0x0700 01054 #define port_cfg_02_funcprm_nsamples 0x00e0 01055 #define port_cfg_02_funcprm_port 0x001f 01056 #define port_cfg_02_DESIGNVALUE 0x0000 01057 01058 /// 0x23 r/w port_cfg_03 PIXI port 3 configuration register 01059 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode 01060 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV 01061 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range 01062 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP 01063 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31 01064 #define port_cfg_03_PortCfgFuncID 0xf000 01065 #define port_cfg_03_funcprm_avrInv 0x0800 01066 #define port_cfg_03_funcprm_range 0x0700 01067 #define port_cfg_03_funcprm_nsamples 0x00e0 01068 #define port_cfg_03_funcprm_port 0x001f 01069 #define port_cfg_03_DESIGNVALUE 0x0000 01070 01071 /// 0x24 r/w port_cfg_04 PIXI port 4 configuration register 01072 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode 01073 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV 01074 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range 01075 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP 01076 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31 01077 #define port_cfg_04_PortCfgFuncID 0xf000 01078 #define port_cfg_04_funcprm_avrInv 0x0800 01079 #define port_cfg_04_funcprm_range 0x0700 01080 #define port_cfg_04_funcprm_nsamples 0x00e0 01081 #define port_cfg_04_funcprm_port 0x001f 01082 #define port_cfg_04_DESIGNVALUE 0x0000 01083 01084 /// 0x25 r/w port_cfg_05 PIXI port 5 configuration register 01085 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode 01086 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV 01087 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range 01088 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP 01089 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31 01090 #define port_cfg_05_PortCfgFuncID 0xf000 01091 #define port_cfg_05_funcprm_avrInv 0x0800 01092 #define port_cfg_05_funcprm_range 0x0700 01093 #define port_cfg_05_funcprm_nsamples 0x00e0 01094 #define port_cfg_05_funcprm_port 0x001f 01095 #define port_cfg_05_DESIGNVALUE 0x0000 01096 01097 /// 0x26 r/w port_cfg_06 PIXI port 6 configuration register 01098 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode 01099 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV 01100 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range 01101 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP 01102 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31 01103 #define port_cfg_06_PortCfgFuncID 0xf000 01104 #define port_cfg_06_funcprm_avrInv 0x0800 01105 #define port_cfg_06_funcprm_range 0x0700 01106 #define port_cfg_06_funcprm_nsamples 0x00e0 01107 #define port_cfg_06_funcprm_port 0x001f 01108 #define port_cfg_06_DESIGNVALUE 0x0000 01109 01110 /// 0x27 r/w port_cfg_07 PIXI port 7 configuration register 01111 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode 01112 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV 01113 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range 01114 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP 01115 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31 01116 #define port_cfg_07_PortCfgFuncID 0xf000 01117 #define port_cfg_07_funcprm_avrInv 0x0800 01118 #define port_cfg_07_funcprm_range 0x0700 01119 #define port_cfg_07_funcprm_nsamples 0x00e0 01120 #define port_cfg_07_funcprm_port 0x001f 01121 #define port_cfg_07_DESIGNVALUE 0x0000 01122 01123 /// 0x28 r/w port_cfg_08 PIXI port 8 configuration register 01124 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode 01125 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV 01126 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range 01127 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP 01128 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31 01129 #define port_cfg_08_PortCfgFuncID 0xf000 01130 #define port_cfg_08_funcprm_avrInv 0x0800 01131 #define port_cfg_08_funcprm_range 0x0700 01132 #define port_cfg_08_funcprm_nsamples 0x00e0 01133 #define port_cfg_08_funcprm_port 0x001f 01134 #define port_cfg_08_DESIGNVALUE 0x0000 01135 01136 /// 0x29 r/w port_cfg_09 PIXI port 9 configuration register 01137 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode 01138 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV 01139 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range 01140 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP 01141 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31 01142 #define port_cfg_09_PortCfgFuncID 0xf000 01143 #define port_cfg_09_funcprm_avrInv 0x0800 01144 #define port_cfg_09_funcprm_range 0x0700 01145 #define port_cfg_09_funcprm_nsamples 0x00e0 01146 #define port_cfg_09_funcprm_port 0x001f 01147 #define port_cfg_09_DESIGNVALUE 0x7260 01148 01149 /// 0x2a r/w port_cfg_10 PIXI port 10 configuration register 01150 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode 01151 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV 01152 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range 01153 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP 01154 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31 01155 #define port_cfg_10_PortCfgFuncID 0xf000 01156 #define port_cfg_10_funcprm_avrInv 0x0800 01157 #define port_cfg_10_funcprm_range 0x0700 01158 #define port_cfg_10_funcprm_nsamples 0x00e0 01159 #define port_cfg_10_funcprm_port 0x001f 01160 #define port_cfg_10_DESIGNVALUE 0x0000 01161 01162 /// 0x2b r/w port_cfg_11 PIXI port 11 configuration register 01163 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode 01164 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV 01165 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range 01166 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP 01167 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31 01168 #define port_cfg_11_PortCfgFuncID 0xf000 01169 #define port_cfg_11_funcprm_avrInv 0x0800 01170 #define port_cfg_11_funcprm_range 0x0700 01171 #define port_cfg_11_funcprm_nsamples 0x00e0 01172 #define port_cfg_11_funcprm_port 0x001f 01173 #define port_cfg_11_DESIGNVALUE 0x0000 01174 01175 /// 0x2c r/w port_cfg_12 PIXI port 12 configuration register 01176 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode 01177 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV 01178 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range 01179 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP 01180 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31 01181 #define port_cfg_12_PortCfgFuncID 0xf000 01182 #define port_cfg_12_funcprm_avrInv 0x0800 01183 #define port_cfg_12_funcprm_range 0x0700 01184 #define port_cfg_12_funcprm_nsamples 0x00e0 01185 #define port_cfg_12_funcprm_port 0x001f 01186 #define port_cfg_12_DESIGNVALUE 0x0000 01187 01188 /// 0x2d r/w port_cfg_13 PIXI port 13 configuration register 01189 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode 01190 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV 01191 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range 01192 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP 01193 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31 01194 #define port_cfg_13_PortCfgFuncID 0xf000 01195 #define port_cfg_13_funcprm_avrInv 0x0800 01196 #define port_cfg_13_funcprm_range 0x0700 01197 #define port_cfg_13_funcprm_nsamples 0x00e0 01198 #define port_cfg_13_funcprm_port 0x001f 01199 #define port_cfg_13_DESIGNVALUE 0x0000 01200 01201 /// 0x2e r/w port_cfg_14 PIXI port 14 configuration register 01202 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode 01203 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV 01204 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range 01205 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP 01206 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31 01207 #define port_cfg_14_PortCfgFuncID 0xf000 01208 #define port_cfg_14_funcprm_avrInv 0x0800 01209 #define port_cfg_14_funcprm_range 0x0700 01210 #define port_cfg_14_funcprm_nsamples 0x00e0 01211 #define port_cfg_14_funcprm_port 0x001f 01212 #define port_cfg_14_DESIGNVALUE 0x0000 01213 01214 /// 0x2f r/w port_cfg_15 PIXI port 15 configuration register 01215 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode 01216 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV 01217 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range 01218 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP 01219 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31 01220 #define port_cfg_15_PortCfgFuncID 0xf000 01221 #define port_cfg_15_funcprm_avrInv 0x0800 01222 #define port_cfg_15_funcprm_range 0x0700 01223 #define port_cfg_15_funcprm_nsamples 0x00e0 01224 #define port_cfg_15_funcprm_port 0x001f 01225 #define port_cfg_15_DESIGNVALUE 0x0000 01226 01227 /// 0x30 r/w port_cfg_16 PIXI port 16 configuration register 01228 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode 01229 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV 01230 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range 01231 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP 01232 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31 01233 #define port_cfg_16_PortCfgFuncID 0xf000 01234 #define port_cfg_16_funcprm_avrInv 0x0800 01235 #define port_cfg_16_funcprm_range 0x0700 01236 #define port_cfg_16_funcprm_nsamples 0x00e0 01237 #define port_cfg_16_funcprm_port 0x001f 01238 #define port_cfg_16_DESIGNVALUE 0x0000 01239 01240 /// 0x31 r/w port_cfg_17 PIXI port 17 configuration register 01241 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode 01242 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV 01243 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range 01244 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP 01245 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31 01246 #define port_cfg_17_PortCfgFuncID 0xf000 01247 #define port_cfg_17_funcprm_avrInv 0x0800 01248 #define port_cfg_17_funcprm_range 0x0700 01249 #define port_cfg_17_funcprm_nsamples 0x00e0 01250 #define port_cfg_17_funcprm_port 0x001f 01251 #define port_cfg_17_DESIGNVALUE 0x0000 01252 01253 /// 0x32 r/w port_cfg_18 PIXI port 18 configuration register 01254 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode 01255 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV 01256 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range 01257 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP 01258 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31 01259 #define port_cfg_18_PortCfgFuncID 0xf000 01260 #define port_cfg_18_funcprm_avrInv 0x0800 01261 #define port_cfg_18_funcprm_range 0x0700 01262 #define port_cfg_18_funcprm_nsamples 0x00e0 01263 #define port_cfg_18_funcprm_port 0x001f 01264 #define port_cfg_18_DESIGNVALUE 0x0000 01265 01266 /// 0x33 r/w port_cfg_19 PIXI port 19 configuration register 01267 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode 01268 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV 01269 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range 01270 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP 01271 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31 01272 #define port_cfg_19_PortCfgFuncID 0xf000 01273 #define port_cfg_19_funcprm_avrInv 0x0800 01274 #define port_cfg_19_funcprm_range 0x0700 01275 #define port_cfg_19_funcprm_nsamples 0x00e0 01276 #define port_cfg_19_funcprm_port 0x001f 01277 #define port_cfg_19_DESIGNVALUE 0x0000 01278 01279 /// 0x40 r/o adc_data_port_00 PIXI port 0 Analog to Digital Converter register 01280 /// <code>xxxx111111111111</code> adccode 12-bit ADC code 01281 #define adc_data_port_00_adccode 0x0fff 01282 01283 /// 0x41 r/o adc_data_port_01 PIXI port 1 Analog to Digital Converter register 01284 /// <code>xxxx111111111111</code> adccode 12-bit ADC code 01285 #define adc_data_port_01_adccode 0x0fff 01286 01287 /// 0x42 r/o adc_data_port_02 PIXI port 2 Analog to Digital Converter register 01288 /// <code>xxxx111111111111</code> adccode 12-bit ADC code 01289 #define adc_data_port_02_adccode 0x0fff 01290 01291 /// 0x43 r/o adc_data_port_03 PIXI port 3 Analog to Digital Converter register 01292 /// <code>xxxx111111111111</code> adccode 12-bit ADC code 01293 #define adc_data_port_03_adccode 0x0fff 01294 01295 /// 0x44 r/o adc_data_port_04 PIXI port 4 Analog to Digital Converter register 01296 /// <code>xxxx111111111111</code> adccode 12-bit ADC code 01297 #define adc_data_port_04_adccode 0x0fff 01298 01299 /// 0x45 r/o adc_data_port_05 PIXI port 5 Analog to Digital Converter register 01300 /// <code>xxxx111111111111</code> adccode 12-bit ADC code 01301 #define adc_data_port_05_adccode 0x0fff 01302 01303 /// 0x46 r/o adc_data_port_06 PIXI port 6 Analog to Digital Converter register 01304 /// <code>xxxx111111111111</code> adccode 12-bit ADC code 01305 #define adc_data_port_06_adccode 0x0fff 01306 01307 /// 0x47 r/o adc_data_port_07 PIXI port 7 Analog to Digital Converter register 01308 /// <code>xxxx111111111111</code> adccode 12-bit ADC code 01309 #define adc_data_port_07_adccode 0x0fff 01310 01311 /// 0x48 r/o adc_data_port_08 PIXI port 8 Analog to Digital Converter register 01312 /// <code>xxxx111111111111</code> adccode 12-bit ADC code 01313 #define adc_data_port_08_adccode 0x0fff 01314 01315 /// 0x49 r/o adc_data_port_09 PIXI port 9 Analog to Digital Converter register 01316 /// <code>xxxx111111111111</code> adccode 12-bit ADC code 01317 #define adc_data_port_09_adccode 0x0fff 01318 01319 /// 0x4a r/o adc_data_port_10 PIXI port 10 Analog to Digital Converter register 01320 /// <code>xxxx111111111111</code> adccode 12-bit ADC code 01321 #define adc_data_port_10_adccode 0x0fff 01322 01323 /// 0x4b r/o adc_data_port_11 PIXI port 11 Analog to Digital Converter register 01324 /// <code>xxxx111111111111</code> adccode 12-bit ADC code 01325 #define adc_data_port_11_adccode 0x0fff 01326 01327 /// 0x4c r/o adc_data_port_12 PIXI port 12 Analog to Digital Converter register 01328 /// <code>xxxx111111111111</code> adccode 12-bit ADC code 01329 #define adc_data_port_12_adccode 0x0fff 01330 01331 /// 0x4d r/o adc_data_port_13 PIXI port 13 Analog to Digital Converter register 01332 /// <code>xxxx111111111111</code> adccode 12-bit ADC code 01333 #define adc_data_port_13_adccode 0x0fff 01334 01335 /// 0x4e r/o adc_data_port_14 PIXI port 14 Analog to Digital Converter register 01336 /// <code>xxxx111111111111</code> adccode 12-bit ADC code 01337 #define adc_data_port_14_adccode 0x0fff 01338 01339 /// 0x4f r/o adc_data_port_15 PIXI port 15 Analog to Digital Converter register 01340 /// <code>xxxx111111111111</code> adccode 12-bit ADC code 01341 #define adc_data_port_15_adccode 0x0fff 01342 01343 /// 0x50 r/o adc_data_port_16 PIXI port 16 Analog to Digital Converter register 01344 /// <code>xxxx111111111111</code> adccode 12-bit ADC code 01345 #define adc_data_port_16_adccode 0x0fff 01346 01347 /// 0x51 r/o adc_data_port_17 PIXI port 17 Analog to Digital Converter register 01348 /// <code>xxxx111111111111</code> adccode 12-bit ADC code 01349 #define adc_data_port_17_adccode 0x0fff 01350 01351 /// 0x52 r/o adc_data_port_18 PIXI port 18 Analog to Digital Converter register 01352 /// <code>xxxx111111111111</code> adccode 12-bit ADC code 01353 #define adc_data_port_18_adccode 0x0fff 01354 01355 /// 0x53 r/o adc_data_port_19 PIXI port 19 Analog to Digital Converter register 01356 /// <code>xxxx111111111111</code> adccode 12-bit ADC code 01357 #define adc_data_port_19_adccode 0x0fff 01358 01359 /// 0x60 r/w dac_data_port_00 PIXI port 0 Digital to Analog Converter register 01360 /// <code>xxxx111111111111</code> daccode 12-bit DAC code 01361 #define dac_data_port_00_daccode 0x0fff 01362 #define dac_data_port_00_DESIGNVALUE 0x0666 01363 01364 /// 0x61 r/w dac_data_port_01 PIXI port 1 Digital to Analog Converter register 01365 /// <code>xxxx111111111111</code> daccode 12-bit DAC code 01366 #define dac_data_port_01_daccode 0x0fff 01367 #define dac_data_port_01_DESIGNVALUE 0x0666 01368 01369 /// 0x62 r/w dac_data_port_02 PIXI port 2 Digital to Analog Converter register 01370 /// <code>xxxx111111111111</code> daccode 12-bit DAC code 01371 #define dac_data_port_02_daccode 0x0fff 01372 #define dac_data_port_02_DESIGNVALUE 0x0000 01373 01374 /// 0x63 r/w dac_data_port_03 PIXI port 3 Digital to Analog Converter register 01375 /// <code>xxxx111111111111</code> daccode 12-bit DAC code 01376 #define dac_data_port_03_daccode 0x0fff 01377 #define dac_data_port_03_DESIGNVALUE 0x0000 01378 01379 /// 0x64 r/w dac_data_port_04 PIXI port 4 Digital to Analog Converter register 01380 /// <code>xxxx111111111111</code> daccode 12-bit DAC code 01381 #define dac_data_port_04_daccode 0x0fff 01382 #define dac_data_port_04_DESIGNVALUE 0x0000 01383 01384 /// 0x65 r/w dac_data_port_05 PIXI port 5 Digital to Analog Converter register 01385 /// <code>xxxx111111111111</code> daccode 12-bit DAC code 01386 #define dac_data_port_05_daccode 0x0fff 01387 #define dac_data_port_05_DESIGNVALUE 0x0000 01388 01389 /// 0x66 r/w dac_data_port_06 PIXI port 6 Digital to Analog Converter register 01390 /// <code>xxxx111111111111</code> daccode 12-bit DAC code 01391 #define dac_data_port_06_daccode 0x0fff 01392 #define dac_data_port_06_DESIGNVALUE 0x0000 01393 01394 /// 0x67 r/w dac_data_port_07 PIXI port 7 Digital to Analog Converter register 01395 /// <code>xxxx111111111111</code> daccode 12-bit DAC code 01396 #define dac_data_port_07_daccode 0x0fff 01397 #define dac_data_port_07_DESIGNVALUE 0x0000 01398 01399 /// 0x68 r/w dac_data_port_08 PIXI port 8 Digital to Analog Converter register 01400 /// <code>xxxx111111111111</code> daccode 12-bit DAC code 01401 #define dac_data_port_08_daccode 0x0fff 01402 #define dac_data_port_08_DESIGNVALUE 0x0000 01403 01404 /// 0x69 r/w dac_data_port_09 PIXI port 9 Digital to Analog Converter register 01405 /// <code>xxxx111111111111</code> daccode 12-bit DAC code 01406 #define dac_data_port_09_daccode 0x0fff 01407 #define dac_data_port_09_DESIGNVALUE 0x0000 01408 01409 /// 0x6a r/w dac_data_port_10 PIXI port 10 Digital to Analog Converter register 01410 /// <code>xxxx111111111111</code> daccode 12-bit DAC code 01411 #define dac_data_port_10_daccode 0x0fff 01412 #define dac_data_port_10_DESIGNVALUE 0x0000 01413 01414 /// 0x6b r/w dac_data_port_11 PIXI port 11 Digital to Analog Converter register 01415 /// <code>xxxx111111111111</code> daccode 12-bit DAC code 01416 #define dac_data_port_11_daccode 0x0fff 01417 #define dac_data_port_11_DESIGNVALUE 0x0000 01418 01419 /// 0x6c r/w dac_data_port_12 PIXI port 12 Digital to Analog Converter register 01420 /// <code>xxxx111111111111</code> daccode 12-bit DAC code 01421 #define dac_data_port_12_daccode 0x0fff 01422 #define dac_data_port_12_DESIGNVALUE 0x0000 01423 01424 /// 0x6d r/w dac_data_port_13 PIXI port 13 Digital to Analog Converter register 01425 /// <code>xxxx111111111111</code> daccode 12-bit DAC code 01426 #define dac_data_port_13_daccode 0x0fff 01427 #define dac_data_port_13_DESIGNVALUE 0x0000 01428 01429 /// 0x6e r/w dac_data_port_14 PIXI port 14 Digital to Analog Converter register 01430 /// <code>xxxx111111111111</code> daccode 12-bit DAC code 01431 #define dac_data_port_14_daccode 0x0fff 01432 #define dac_data_port_14_DESIGNVALUE 0x0000 01433 01434 /// 0x6f r/w dac_data_port_15 PIXI port 15 Digital to Analog Converter register 01435 /// <code>xxxx111111111111</code> daccode 12-bit DAC code 01436 #define dac_data_port_15_daccode 0x0fff 01437 #define dac_data_port_15_DESIGNVALUE 0x0000 01438 01439 /// 0x70 r/w dac_data_port_16 PIXI port 16 Digital to Analog Converter register 01440 /// <code>xxxx111111111111</code> daccode 12-bit DAC code 01441 #define dac_data_port_16_daccode 0x0fff 01442 #define dac_data_port_16_DESIGNVALUE 0x0000 01443 01444 /// 0x71 r/w dac_data_port_17 PIXI port 17 Digital to Analog Converter register 01445 /// <code>xxxx111111111111</code> daccode 12-bit DAC code 01446 #define dac_data_port_17_daccode 0x0fff 01447 #define dac_data_port_17_DESIGNVALUE 0x0000 01448 01449 /// 0x72 r/w dac_data_port_18 PIXI port 18 Digital to Analog Converter register 01450 /// <code>xxxx111111111111</code> daccode 12-bit DAC code 01451 #define dac_data_port_18_daccode 0x0fff 01452 #define dac_data_port_18_DESIGNVALUE 0x0000 01453 01454 /// 0x73 r/w dac_data_port_19 PIXI port 19 Digital to Analog Converter register 01455 /// <code>xxxx111111111111</code> daccode 12-bit DAC code 01456 #define dac_data_port_19_daccode 0x0fff 01457 #define dac_data_port_19_DESIGNVALUE 0x0000 01458 01459 /// Initialize registers in sequence recommended by PIXI Port Configuration Flow Chart. 01460 /// Requires user-provided function MAX11300regWrite(regAddress8, regData16) 01461 /// Requires user-provided function MAX11300initDelayus(delay_us) 01462 /// 01463 /// PIXI ports to configure as Mode 0 HighImpedance: 01464 /// portIndex 2 PIXI port P2 01465 /// portIndex 3 PIXI port P3 01466 /// portIndex 4 PIXI port P4 01467 /// portIndex 5 PIXI port P5 01468 /// portIndex 6 PIXI port P6 01469 /// portIndex 7 PIXI port P7 01470 /// portIndex 8 PIXI port P8 01471 /// portIndex 10 PIXI port P10 01472 /// portIndex 11 PIXI port P11 01473 /// portIndex 12 PIXI port P12 01474 /// portIndex 13 PIXI port P13 01475 /// portIndex 14 PIXI port P14 01476 /// portIndex 15 PIXI port P15 01477 /// portIndex 16 PIXI port P16 01478 /// portIndex 17 PIXI port P17 01479 /// portIndex 18 PIXI port P18 01480 /// portIndex 19 PIXI port P19 01481 /// PIXI ports to configure as Mode 1 GPIOinPgmThreshold: 01482 /// none 01483 /// PIXI ports to configure as Mode 2 GPIOinOutBidirLevelTrans: 01484 /// none 01485 /// PIXI ports to configure as Mode 3 GPIOoutRegDrivenOutputDAClevel: 01486 /// none 01487 /// PIXI ports to configure as Mode 4 GPIOoutUnidirOutputDAClevel: 01488 /// none 01489 /// PIXI ports to configure as Mode 5 DACout: 01490 /// portIndex 0 PIXI port P0 01491 /// portIndex 1 PIXI port P1 01492 /// PIXI ports to configure as Mode 6 DACoutWithADCmonitor: 01493 /// none 01494 /// PIXI ports to configure as Mode 7 ADCinPosSingleEnded: 01495 /// portIndex 9 PIXI port P9 01496 /// PIXI ports to configure as Mode 8 ADCinPosDifferential: 01497 /// none 01498 /// PIXI ports to configure as Mode 9 ADCinNegDifferential: 01499 /// none 01500 /// PIXI ports to configure as Mode 10 DACoutADCinNegDifferential: 01501 /// none 01502 /// PIXI ports to configure as Mode 11 GPIOBidirAnalogSwitchExtControlled: 01503 /// none 01504 /// PIXI ports to configure as Mode 12 GPIOBidirAnalogSwitch: 01505 /// none 01506 /// PIXI ports to configure as Mode 13 Reserved13: 01507 /// none 01508 /// PIXI ports to configure as Mode 14 Reserved14: 01509 /// none 01510 /// PIXI ports to configure as Mode 15 Reserved15: 01511 /// none 01512 /// 01513 //inline void MAX11301init() 01514 //{ 01515 // extern bool MAX11301regWrite(int regAddress8, int regData16); 01516 // extern void MAX11301initDelayus(int delay_us); 01517 // 01518 // // ------------------------------------------------------ 01519 // // Soft Reset device registers by device_control 8000_RESET 01520 // // ------------------------------------------------------ 01521 // MAX11300regWrite(device_control, 0x8000); // 1xxx xxxx xxxx xxxx RESET Soft reset command 01522 // 01523 // // ------------------------------------------------------ 01524 // // FLOWCHART: "Configure device_control 4000_BRST, 0080_THSHDN, 0030_ADCCONV" 01525 // // ------------------------------------------------------ 01526 // MAX11300regWrite(device_control, (device_control_DESIGNVALUE & 0x40B0)); 01527 // 01528 // // ------------------------------------------------------ 01529 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" 01530 // // ------------------------------------------------------ 01531 // // PIXI ports to configure as Mode 1 GPIOinPgmThreshold: 01532 // // none 01533 // // PIXI ports to configure as Mode 3 GPIOoutRegDrivenOutputDAClevel: 01534 // // none 01535 // // PIXI ports to configure as Mode 4 GPIOoutUnidirOutputDAClevel: 01536 // // none 01537 // // PIXI ports to configure as Mode 5 DACout: 01538 // // portIndex 0 PIXI port P0 01539 // // portIndex 1 PIXI port P1 01540 // // PIXI ports to configure as Mode 6 DACoutWithADCmonitor: 01541 // // none 01542 // // PIXI ports to configure as Mode 10 DACoutADCinNegDifferential: 01543 // // none 01544 // // ------------------------------------------------------ 01545 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y" 01546 // // FLOWCHART: "Configure device_control 0040_DACREF, 000C_DACCTL" 01547 // // ------------------------------------------------------ 01548 // MAX11300regWrite(device_control, (device_control_DESIGNVALUE & 0x40FC)); 01549 // 01550 // // ------------------------------------------------------ 01551 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y" 01552 // // FLOWCHART: "Wait 200us" 01553 // // ------------------------------------------------------ 01554 // MAX11300initDelayus(200); 01555 // 01556 // // ------------------------------------------------------ 01557 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y" 01558 // // Configure DACDAT[i] for ports in mode 5 DACout: 01559 // // portIndex 0 PIXI port P0 01560 // // ------------------------------------------------------ 01561 // MAX11300regWrite(dac_data_port_00, dac_data_port_00_DESIGNVALUE); 01562 // 01563 // // ------------------------------------------------------ 01564 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y" 01565 // // FLOWCHART: "Wait 1ms" 01566 // // ------------------------------------------------------ 01567 // MAX11300initDelayus(1000); 01568 // 01569 // // ------------------------------------------------------ 01570 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y" 01571 // // Configure DACDAT[i] for ports in mode 5 DACout: 01572 // // portIndex 1 PIXI port P1 01573 // // ------------------------------------------------------ 01574 // MAX11300regWrite(dac_data_port_01, dac_data_port_01_DESIGNVALUE); 01575 // 01576 // // ------------------------------------------------------ 01577 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y" 01578 // // FLOWCHART: "Wait 1ms" 01579 // // ------------------------------------------------------ 01580 // MAX11300initDelayus(1000); 01581 // 01582 // 01583 // // ------------------------------------------------------ 01584 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y" 01585 // // FLOWCHART: "Enter DACPRSTDAT1 or DACPRSTDAT2" 01586 // // ------------------------------------------------------ 01587 // MAX11300regWrite(dac_preset_data_1, dac_preset_data_1_DESIGNVALUE); 01588 // MAX11300regWrite(dac_preset_data_2, dac_preset_data_2_DESIGNVALUE); 01589 // 01590 // // ------------------------------------------------------ 01591 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y" 01592 // // FLOWCHART: "Wait 200us x number of ports in mode 1" 01593 // // ------------------------------------------------------ 01594 // 01595 // // ------------------------------------------------------ 01596 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y" 01597 // // FLOWCHART: "Configure GPODAT[i] for ports in mode 3" 01598 // // ------------------------------------------------------ 01599 // 01600 // // ------------------------------------------------------ 01601 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y" 01602 // // Configure FUNCID[i] FUNCPRM[i] for ports in mode 5 DACout: 01603 // // portIndex 0 PIXI port P0 01604 // // ------------------------------------------------------ 01605 // MAX11300regWrite(port_cfg_00, port_cfg_00_DESIGNVALUE); 01606 // 01607 // // ------------------------------------------------------ 01608 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y" 01609 // // FLOWCHART: "Wait 1ms" 01610 // // ------------------------------------------------------ 01611 // MAX11300initDelayus(1000); 01612 // 01613 // // ------------------------------------------------------ 01614 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y" 01615 // // Configure FUNCID[i] FUNCPRM[i] for ports in mode 5 DACout: 01616 // // portIndex 1 PIXI port P1 01617 // // ------------------------------------------------------ 01618 // MAX11300regWrite(port_cfg_01, port_cfg_01_DESIGNVALUE); 01619 // 01620 // // ------------------------------------------------------ 01621 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y" 01622 // // FLOWCHART: "Wait 1ms" 01623 // // ------------------------------------------------------ 01624 // MAX11300initDelayus(1000); 01625 // 01626 // // ------------------------------------------------------ 01627 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y" 01628 // // FLOWCHART: "Configure GPIMD[i] for ports in mode 1" 01629 // // ------------------------------------------------------ 01630 // MAX11300regWrite(gpi_irqmode_7_to_0, gpi_irqmode_7_to_0_DESIGNVALUE); 01631 // MAX11300regWrite(gpi_irqmode_15_to_8, gpi_irqmode_15_to_8_DESIGNVALUE); 01632 // MAX11300regWrite(gpi_irqmode_19_to_16, gpi_irqmode_19_to_16_DESIGNVALUE); 01633 // 01634 // 01635 // // ------------------------------------------------------ 01636 // // FLOWCHART: decision "Is mode 7, 8, or 9 used?" 01637 // // ------------------------------------------------------ 01638 // // PIXI ports to configure as Mode 7 ADCinPosSingleEnded: 01639 // // portIndex 9 PIXI port P9 01640 // // PIXI ports to configure as Mode 8 ADCinPosDifferential: 01641 // // none 01642 // // PIXI ports to configure as Mode 9 ADCinNegDifferential: 01643 // // none 01644 // // ------------------------------------------------------ 01645 // // FLOWCHART: decision "Is mode 7, 8, or 9 used?" branch "Y" 01646 // // Configure FUNCID[i] FUNCPRM[i] for ports in mode 7 ADCinPosSingleEnded: 01647 // // portIndex 9 PIXI port P9 01648 // // ------------------------------------------------------ 01649 // MAX11300regWrite(port_cfg_09, port_cfg_09_DESIGNVALUE); 01650 // 01651 // // ------------------------------------------------------ 01652 // // FLOWCHART: decision "Is mode 7, 8, or 9 used?" branch "Y" 01653 // // FLOWCHART: "Wait 100us" 01654 // // ------------------------------------------------------ 01655 // MAX11300initDelayus(100); 01656 // 01657 // // ------------------------------------------------------ 01658 // // FLOWCHART: decision "Is mode 7, 8, or 9 used?" branch "Y" 01659 // // FLOWCHART: "Configure device_control 0003_ADCCTL" 01660 // // ------------------------------------------------------ 01661 // MAX11300regWrite(device_control, (device_control_DESIGNVALUE & 0x40FF)); 01662 // 01663 // 01664 // // ------------------------------------------------------ 01665 // // FLOWCHART: decision "Is mode 2, 11, or 12 used?" 01666 // // ------------------------------------------------------ 01667 // 01668 // // ------------------------------------------------------ 01669 // // FLOWCHART: decision "Are temperature sensors used?" 01670 // // ------------------------------------------------------ 01671 // 01672 // // ------------------------------------------------------ 01673 // // Configure final device_control design value 2000_LPEN 01674 // // ------------------------------------------------------ 01675 // MAX11300regWrite(device_control, (device_control_DESIGNVALUE)); 01676 // 01677 // // ------------------------------------------------------ 01678 // // FLOWCHART: Configure Interrupt Masks 01679 // // ------------------------------------------------------ 01680 // MAX11300regWrite(interrupt_mask, interrupt_mask_DESIGNVALUE); 01681 // 01682 // 01683 //} 01684 01685 01686 #endif /* _MAX11300_DESIGNVALUE_H_ */ 01687 01688 // End of file 01689
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