MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output BuckBoost, 1-LDO for Long Battery Life Mbed Driver
MAX77643_2_regs.h@0:55f664e8c56c, 2022-08-26 (annotated)
- Committer:
- Okan Sahin
- Date:
- Fri Aug 26 14:20:53 2022 +0300
- Revision:
- 0:55f664e8c56c
Initial Commit
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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Okan Sahin |
0:55f664e8c56c | 1 | /******************************************************************************* |
Okan Sahin |
0:55f664e8c56c | 2 | * Copyright(C) Analog Devices Inc., All Rights Reserved. |
Okan Sahin |
0:55f664e8c56c | 3 | * |
Okan Sahin |
0:55f664e8c56c | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
Okan Sahin |
0:55f664e8c56c | 5 | * copy of this software and associated documentation files(the "Software"), |
Okan Sahin |
0:55f664e8c56c | 6 | * to deal in the Software without restriction, including without limitation |
Okan Sahin |
0:55f664e8c56c | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
Okan Sahin |
0:55f664e8c56c | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
Okan Sahin |
0:55f664e8c56c | 9 | * Software is furnished to do so, subject to the following conditions: |
Okan Sahin |
0:55f664e8c56c | 10 | * |
Okan Sahin |
0:55f664e8c56c | 11 | * The above copyright notice and this permission notice shall be included |
Okan Sahin |
0:55f664e8c56c | 12 | * in all copies or substantial portions of the Software. |
Okan Sahin |
0:55f664e8c56c | 13 | * |
Okan Sahin |
0:55f664e8c56c | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
Okan Sahin |
0:55f664e8c56c | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
Okan Sahin |
0:55f664e8c56c | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
Okan Sahin |
0:55f664e8c56c | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
Okan Sahin |
0:55f664e8c56c | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
Okan Sahin |
0:55f664e8c56c | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
Okan Sahin |
0:55f664e8c56c | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
Okan Sahin |
0:55f664e8c56c | 21 | * |
Okan Sahin |
0:55f664e8c56c | 22 | * Except as contained in this notice, the name of Analog Devices Inc. |
Okan Sahin |
0:55f664e8c56c | 23 | * shall not be used except as stated in the Analog Devices Inc. |
Okan Sahin |
0:55f664e8c56c | 24 | * Branding Policy. |
Okan Sahin |
0:55f664e8c56c | 25 | * |
Okan Sahin |
0:55f664e8c56c | 26 | * The mere transfer of this software does not imply any licenses |
Okan Sahin |
0:55f664e8c56c | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
Okan Sahin |
0:55f664e8c56c | 28 | * trademarks, maskwork rights, or any other form of intellectual |
Okan Sahin |
0:55f664e8c56c | 29 | * property whatsoever. Analog Devices Inc.retains all ownership rights. |
Okan Sahin |
0:55f664e8c56c | 30 | ******************************************************************************* |
Okan Sahin |
0:55f664e8c56c | 31 | */ |
Okan Sahin |
0:55f664e8c56c | 32 | |
Okan Sahin |
0:55f664e8c56c | 33 | #ifndef MAX77643_2_REGS_H_ |
Okan Sahin |
0:55f664e8c56c | 34 | #define MAX77643_2_REGS_H_ |
Okan Sahin |
0:55f664e8c56c | 35 | |
Okan Sahin |
0:55f664e8c56c | 36 | /** |
Okan Sahin |
0:55f664e8c56c | 37 | * @brief INT_GLBL0 Register |
Okan Sahin |
0:55f664e8c56c | 38 | * |
Okan Sahin |
0:55f664e8c56c | 39 | * Address : 0x00 |
Okan Sahin |
0:55f664e8c56c | 40 | */ |
Okan Sahin |
0:55f664e8c56c | 41 | typedef union { |
Okan Sahin |
0:55f664e8c56c | 42 | unsigned char raw; |
Okan Sahin |
0:55f664e8c56c | 43 | struct { |
Okan Sahin |
0:55f664e8c56c | 44 | unsigned char gpi0_f : 1; /**< GPI Falling Interrupt. Bit 0. |
Okan Sahin |
0:55f664e8c56c | 45 | Note that "GPI" refers to the GPIO programmed to be an input. |
Okan Sahin |
0:55f664e8c56c | 46 | 0 = No GPI falling edges have occurred since the last time this bit was read. |
Okan Sahin |
0:55f664e8c56c | 47 | 1 = A GPI falling edge has occurred since the last time this bit was read. */ |
Okan Sahin |
0:55f664e8c56c | 48 | unsigned char gpi0_r : 1; /**< GPI Rising Interrupt. Bit 1. |
Okan Sahin |
0:55f664e8c56c | 49 | Note that "GPI" refers to the GPIO programmed to be an input. |
Okan Sahin |
0:55f664e8c56c | 50 | 0 = No GPI rising edges have occurred since the last time this bit was read. |
Okan Sahin |
0:55f664e8c56c | 51 | 1 = A GPI rising edge has occurred since the last time this bit was read. */ |
Okan Sahin |
0:55f664e8c56c | 52 | unsigned char nen_f : 1; /**< nEN Falling Interrupt.Bit 2. |
Okan Sahin |
0:55f664e8c56c | 53 | 0 = No nEN falling edges have occurred since the last time this bit was read. |
Okan Sahin |
0:55f664e8c56c | 54 | 1 = A nEN falling edge as occurred since the last time this bit was read. */ |
Okan Sahin |
0:55f664e8c56c | 55 | unsigned char nen_r : 1; /**< nEN Rising Interrupt. Bit 3. |
Okan Sahin |
0:55f664e8c56c | 56 | 0 = No nEN rising edges have occurred since the last time this bit was read. |
Okan Sahin |
0:55f664e8c56c | 57 | 1 = A nEN rising edge as occurred since the last time this bit was read. */ |
Okan Sahin |
0:55f664e8c56c | 58 | unsigned char tjal1_r : 1; /**< Thermal Alarm 1 Rising Interrupt. Bit 4. |
Okan Sahin |
0:55f664e8c56c | 59 | 0 = The junction temperature has not risen above TJAL1 since the last time this bit was read. |
Okan Sahin |
0:55f664e8c56c | 60 | 1 = The junction temperature has risen above TJAL1 since the last time this bit was read. */ |
Okan Sahin |
0:55f664e8c56c | 61 | unsigned char tjal2_r : 1; /**< Thermal Alarm 2 Rising Interrupt. Bit 5. |
Okan Sahin |
0:55f664e8c56c | 62 | 0 = The junction temperature has not risen above TJAL2 since the last time this bit was read. |
Okan Sahin |
0:55f664e8c56c | 63 | 1 = The junction temperature has risen above TJAL2 since the last time this bit was read. */ |
Okan Sahin |
0:55f664e8c56c | 64 | unsigned char dod_r : 1; /**< LDO Dropout Detector Rising Interrupt. Bit 6. |
Okan Sahin |
0:55f664e8c56c | 65 | 0 = The LDO has not detected dropout since the last time this bit was read. |
Okan Sahin |
0:55f664e8c56c | 66 | 1 = The LDO has detected dropout since the last time this bit was read. */ |
Okan Sahin |
0:55f664e8c56c | 67 | unsigned char rsvd : 1; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 7. */ |
Okan Sahin |
0:55f664e8c56c | 68 | } bits; |
Okan Sahin |
0:55f664e8c56c | 69 | } reg_int_glbl0_t; |
Okan Sahin |
0:55f664e8c56c | 70 | |
Okan Sahin |
0:55f664e8c56c | 71 | /** |
Okan Sahin |
0:55f664e8c56c | 72 | * @brief INT_GLBL1 Register |
Okan Sahin |
0:55f664e8c56c | 73 | * |
Okan Sahin |
0:55f664e8c56c | 74 | * Address : 0x01 |
Okan Sahin |
0:55f664e8c56c | 75 | */ |
Okan Sahin |
0:55f664e8c56c | 76 | typedef union { |
Okan Sahin |
0:55f664e8c56c | 77 | unsigned char raw; |
Okan Sahin |
0:55f664e8c56c | 78 | struct { |
Okan Sahin |
0:55f664e8c56c | 79 | unsigned char gpi1_f : 1; /**< GPI Falling Interrupt. Bit 0. |
Okan Sahin |
0:55f664e8c56c | 80 | Note that "GPI" refers to the GPIO programmed to be an input. |
Okan Sahin |
0:55f664e8c56c | 81 | 0 = No GPI falling edges have occurred since the last time this bit was read. |
Okan Sahin |
0:55f664e8c56c | 82 | 1 = A GPI falling edge has occurred since the last time this bit was read. */ |
Okan Sahin |
0:55f664e8c56c | 83 | unsigned char gpi1_r : 1; /**< GPI Rising Interrupt. Bit 1. |
Okan Sahin |
0:55f664e8c56c | 84 | Note that "GPI" refers to the GPIO programmed to be an input. |
Okan Sahin |
0:55f664e8c56c | 85 | 0 = No GPI rising edges have occurred since the last time this bit was read. |
Okan Sahin |
0:55f664e8c56c | 86 | 1 = A GPI rising edge has occurred since the last time this bit was read. */ |
Okan Sahin |
0:55f664e8c56c | 87 | unsigned char sbb0_f : 1; /**< SBB0 Fault Indicator. Bit 2. |
Okan Sahin |
0:55f664e8c56c | 88 | 0 = No fault has occurred on SBB0 since the last time this bit was read. |
Okan Sahin |
0:55f664e8c56c | 89 | 1 = SBB0 has fallen out of regulation since the last time this bit was read. */ |
Okan Sahin |
0:55f664e8c56c | 90 | unsigned char sbb1_f : 1; /**< SBB1 Fault Indicator. Bit 3. |
Okan Sahin |
0:55f664e8c56c | 91 | 0 = No fault has occurred on SBB1 since the last time this bit was read. |
Okan Sahin |
0:55f664e8c56c | 92 | 1 = SBB1 has fallen out of regulation since the last time this bit was read. */ |
Okan Sahin |
0:55f664e8c56c | 93 | unsigned char sbb2_f : 1; /**< SBB2 Fault Indicator. Bit 4. |
Okan Sahin |
0:55f664e8c56c | 94 | 0 = No fault has occurred on SBB2 since the last time this bit was read. |
Okan Sahin |
0:55f664e8c56c | 95 | 1 = SBB2 has fallen out of regulation since the last time this bit was read. */ |
Okan Sahin |
0:55f664e8c56c | 96 | unsigned char ldo_f : 1; /**< LDO0 Fault Interrupt. Bit 5. |
Okan Sahin |
0:55f664e8c56c | 97 | 0 = No fault has occurred on LDO0 since the last time this bit was read. |
Okan Sahin |
0:55f664e8c56c | 98 | 1 = LDO0 has fallen out of regulation since the last time this bit was read. */ |
Okan Sahin |
0:55f664e8c56c | 99 | unsigned char rsvd : 2; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 7:6. */ |
Okan Sahin |
0:55f664e8c56c | 100 | } bits; |
Okan Sahin |
0:55f664e8c56c | 101 | } reg_int_glbl1_t; |
Okan Sahin |
0:55f664e8c56c | 102 | |
Okan Sahin |
0:55f664e8c56c | 103 | /** |
Okan Sahin |
0:55f664e8c56c | 104 | * @brief ERCFLAG Register |
Okan Sahin |
0:55f664e8c56c | 105 | * |
Okan Sahin |
0:55f664e8c56c | 106 | * Address : 0x02 |
Okan Sahin |
0:55f664e8c56c | 107 | */ |
Okan Sahin |
0:55f664e8c56c | 108 | typedef union { |
Okan Sahin |
0:55f664e8c56c | 109 | unsigned char raw; |
Okan Sahin |
0:55f664e8c56c | 110 | struct { |
Okan Sahin |
0:55f664e8c56c | 111 | unsigned char tovld : 1; /**< Thermal Overload. Bit 0. |
Okan Sahin |
0:55f664e8c56c | 112 | 0 = Thermal overload has not occurred since the last read of this register. |
Okan Sahin |
0:55f664e8c56c | 113 | 1 = Thermal overload has occurred since the list read of this register. |
Okan Sahin |
0:55f664e8c56c | 114 | This indicates that the junction temperature has exceeded 165ºC. */ |
Okan Sahin |
0:55f664e8c56c | 115 | unsigned char inovlo : 1; /**< IN Domain Overvoltage Lockout. Bit 1. |
Okan Sahin |
0:55f664e8c56c | 116 | 0 = The IN domain overvoltage lockout has not occurred since the last read of this register. |
Okan Sahin |
0:55f664e8c56c | 117 | 1 = The IN domain overvoltage lockout has occurred since the last read of this register */ |
Okan Sahin |
0:55f664e8c56c | 118 | unsigned char inuvlo : 1; /**< IN Domain Undervoltage Lockout. Bit 2. |
Okan Sahin |
0:55f664e8c56c | 119 | 0 = The IN domain undervoltage lockout has not occurred since the last read of this register. |
Okan Sahin |
0:55f664e8c56c | 120 | 1 = The IN domain undervoltage lockout has occurred since the last read of this register */ |
Okan Sahin |
0:55f664e8c56c | 121 | unsigned char mrst_f : 1; /**< Manual Reset Timer. Bit 3. |
Okan Sahin |
0:55f664e8c56c | 122 | 0 = A Manual Reset has not occurred since this last read of this register. |
Okan Sahin |
0:55f664e8c56c | 123 | 1 = A Manual Reset has occurred since this last read of this register. */ |
Okan Sahin |
0:55f664e8c56c | 124 | unsigned char sft_off_f : 1; /**< Software Off Flag. Bit 4. |
Okan Sahin |
0:55f664e8c56c | 125 | 0 = The SFT_OFF function has not occurred since the last read of this register. |
Okan Sahin |
0:55f664e8c56c | 126 | 1 = The SFT_OFF function has occurred since the last read of this register. */ |
Okan Sahin |
0:55f664e8c56c | 127 | unsigned char sft_crst_f : 1; /**< Software Cold Reset Flag. Bit 5. |
Okan Sahin |
0:55f664e8c56c | 128 | 0 = The software cold reset has not occurred since the last read of this register. |
Okan Sahin |
0:55f664e8c56c | 129 | 1 = The software cold reset has occurred since the last read of this register. */ |
Okan Sahin |
0:55f664e8c56c | 130 | unsigned char wdt_exp_f : 1; /**< Watchdog Timer OFF or RESET Flag. Bit 6. |
Okan Sahin |
0:55f664e8c56c | 131 | This bit sets when the watchdog timer expires and causes a power-off or a reset; based on WDT_MODE bitfield setting. |
Okan Sahin |
0:55f664e8c56c | 132 | 0 = Watchdog timer has not caused a power-off or reset since the last time this bit was read. |
Okan Sahin |
0:55f664e8c56c | 133 | 1 = Watchdog timer has expired and caused a power-off or reset since the last time this bit was read. */ |
Okan Sahin |
0:55f664e8c56c | 134 | unsigned char sbb_fault_f : 1; /**< SBBx Fault and Shutdown Flag. Bit 7. |
Okan Sahin |
0:55f664e8c56c | 135 | This bit sets when a SBBx fault and consequent SBBx shutdown occurs. |
Okan Sahin |
0:55f664e8c56c | 136 | 0 = No SBB shutdown occurred since the last time this bit was read. |
Okan Sahin |
0:55f664e8c56c | 137 | 1 = SBBx fault and SBB shutdown occurred since the last time this bit was read. */ |
Okan Sahin |
0:55f664e8c56c | 138 | } bits; |
Okan Sahin |
0:55f664e8c56c | 139 | } reg_ercflag_t; |
Okan Sahin |
0:55f664e8c56c | 140 | |
Okan Sahin |
0:55f664e8c56c | 141 | /** |
Okan Sahin |
0:55f664e8c56c | 142 | * @brief STAT_GLBL Register |
Okan Sahin |
0:55f664e8c56c | 143 | * |
Okan Sahin |
0:55f664e8c56c | 144 | * Address : 0x03 |
Okan Sahin |
0:55f664e8c56c | 145 | */ |
Okan Sahin |
0:55f664e8c56c | 146 | typedef union { |
Okan Sahin |
0:55f664e8c56c | 147 | unsigned char raw; |
Okan Sahin |
0:55f664e8c56c | 148 | struct { |
Okan Sahin |
0:55f664e8c56c | 149 | unsigned char stat_irq : 1; /**< Software Version of the nIRQ MOSFET gate drive. Bit 0. |
Okan Sahin |
0:55f664e8c56c | 150 | 0 = unmasked gate drive is logic low |
Okan Sahin |
0:55f664e8c56c | 151 | 1 = unmasked gate drive is logic high */ |
Okan Sahin |
0:55f664e8c56c | 152 | unsigned char stat_en : 1; /**< Debounced Status for the nEN input. Bit 1. |
Okan Sahin |
0:55f664e8c56c | 153 | 0 = nEN is not active (logic high) |
Okan Sahin |
0:55f664e8c56c | 154 | 1 = nEN is active (logic low) */ |
Okan Sahin |
0:55f664e8c56c | 155 | unsigned char tjal1_s : 1; /**< Thermal Alarm 1 Status. Bit 2. |
Okan Sahin |
0:55f664e8c56c | 156 | 0 = The junction temperature is less than TJAL1 |
Okan Sahin |
0:55f664e8c56c | 157 | 1 = The junction temperature is greater than TJAL1 */ |
Okan Sahin |
0:55f664e8c56c | 158 | unsigned char tjal2_s : 1; /**< Thermal Alarm 2 Status. Bit 3. |
Okan Sahin |
0:55f664e8c56c | 159 | 0 = The junction temperature is less than TJAL2 |
Okan Sahin |
0:55f664e8c56c | 160 | 1 = The junction temperature is greater than TJAL2 */ |
Okan Sahin |
0:55f664e8c56c | 161 | unsigned char dod_s : 1; /**< LDO1 Dropout Detector Rising Status. Bit 4. |
Okan Sahin |
0:55f664e8c56c | 162 | 0 = LDO1 is not in dropout |
Okan Sahin |
0:55f664e8c56c | 163 | 1 = LDO1 is in dropout */ |
Okan Sahin |
0:55f664e8c56c | 164 | unsigned char rsvd : 1; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 5. */ |
Okan Sahin |
0:55f664e8c56c | 165 | unsigned char bok : 1; /**< BOK Interrupt Status. Bit 6. |
Okan Sahin |
0:55f664e8c56c | 166 | 0 = Main Bias is not ready. |
Okan Sahin |
0:55f664e8c56c | 167 | 1 = Main Bias enabled and ready. */ |
Okan Sahin |
0:55f664e8c56c | 168 | unsigned char didm : 1; /**< Device Identification Bits for Metal Options. Bit 7. |
Okan Sahin |
0:55f664e8c56c | 169 | 0 = MAX77643_2 |
Okan Sahin |
0:55f664e8c56c | 170 | 1 = Reserved */ |
Okan Sahin |
0:55f664e8c56c | 171 | } bits; |
Okan Sahin |
0:55f664e8c56c | 172 | } reg_stat_glbl_t; |
Okan Sahin |
0:55f664e8c56c | 173 | |
Okan Sahin |
0:55f664e8c56c | 174 | /** |
Okan Sahin |
0:55f664e8c56c | 175 | * @brief INTM_GLBL0 Register |
Okan Sahin |
0:55f664e8c56c | 176 | * |
Okan Sahin |
0:55f664e8c56c | 177 | * Address : 0x04 |
Okan Sahin |
0:55f664e8c56c | 178 | */ |
Okan Sahin |
0:55f664e8c56c | 179 | typedef union { |
Okan Sahin |
0:55f664e8c56c | 180 | unsigned char raw; |
Okan Sahin |
0:55f664e8c56c | 181 | struct { |
Okan Sahin |
0:55f664e8c56c | 182 | unsigned char gpi0_fm : 1; /**< GPI Falling Interrupt Mask. Bit 0. |
Okan Sahin |
0:55f664e8c56c | 183 | 0 = Unmasked. If GPI_F goes from 0 to 1, then nIRQ goes low. |
Okan Sahin |
0:55f664e8c56c | 184 | nIRQ goes high when all interrupt bits are cleared. |
Okan Sahin |
0:55f664e8c56c | 185 | 1 = Masked. nIRQ does not go low due to GPI_F. */ |
Okan Sahin |
0:55f664e8c56c | 186 | unsigned char gpi0_rm : 1; /**< GPI Rising Interrupt Mask. Bit 1. |
Okan Sahin |
0:55f664e8c56c | 187 | 0 = Unmasked. If GPI_R goes from 0 to 1, then nIRQ goes low. |
Okan Sahin |
0:55f664e8c56c | 188 | nIRQ goes high when all interrupt bits are cleared. |
Okan Sahin |
0:55f664e8c56c | 189 | 1 = Masked. nIRQ does not go low due to GPI_R. */ |
Okan Sahin |
0:55f664e8c56c | 190 | unsigned char nen_fm : 1; /**< nEN Falling Interrupt Mask. Bit 2. |
Okan Sahin |
0:55f664e8c56c | 191 | 0 = Unmasked. If nEN_F goes from 0 to 1, then nIRQ goes low. |
Okan Sahin |
0:55f664e8c56c | 192 | nIRQ goes high when all interrupt bits are cleared. |
Okan Sahin |
0:55f664e8c56c | 193 | 1 = Masked. nIRQ does not go low due to nEN_F. */ |
Okan Sahin |
0:55f664e8c56c | 194 | unsigned char nen_rm : 1; /**< nEN Rising Interrupt Mask. Bit 3. |
Okan Sahin |
0:55f664e8c56c | 195 | 0 = Unmasked. If nEN_R goes from 0 to 1, then nIRQ goes low. |
Okan Sahin |
0:55f664e8c56c | 196 | nIRQ goes high when all interrupt bits are cleared. |
Okan Sahin |
0:55f664e8c56c | 197 | 1 = Masked. nIRQ does not go low due to nEN_R. */ |
Okan Sahin |
0:55f664e8c56c | 198 | unsigned char tjal1_rm : 1; /**< Thermal Alarm 1 Rising Interrupt Mask. Bit 4. |
Okan Sahin |
0:55f664e8c56c | 199 | 0 = Unmasked. If TJAL1_R goes from 0 to 1, then nIRQ goes low. |
Okan Sahin |
0:55f664e8c56c | 200 | nIRQ goes high when all interrupt bits are cleared. |
Okan Sahin |
0:55f664e8c56c | 201 | 1 = Masked. nIRQ does not go low due to TJAL1_R. */ |
Okan Sahin |
0:55f664e8c56c | 202 | unsigned char tjal2_rm : 1; /**< Thermal Alarm 2 Rising Interrupt Mask. Bit 5. |
Okan Sahin |
0:55f664e8c56c | 203 | 0 = Unmasked. If TJAL2_R goes from 0 to 1, then nIRQ goes low. |
Okan Sahin |
0:55f664e8c56c | 204 | nIRQ goes high when all interrupt bits are cleared. |
Okan Sahin |
0:55f664e8c56c | 205 | 1 = Masked. nIRQ does not go low due to TJAL2_R. */ |
Okan Sahin |
0:55f664e8c56c | 206 | unsigned char dod_rm : 1; /**< LDO Dropout Detector Rising Interrupt Mask. Bit 6. |
Okan Sahin |
0:55f664e8c56c | 207 | 0 = Unmasked. If DOD1_R goes from 0 to 1, then nIRQ goes low. |
Okan Sahin |
0:55f664e8c56c | 208 | nIRQ goes high when all interrupt bits are cleared. |
Okan Sahin |
0:55f664e8c56c | 209 | 1 = Masked. nIRQ does not go low due to DOD1_R. */ |
Okan Sahin |
0:55f664e8c56c | 210 | unsigned char rsvd : 1; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 7. */ |
Okan Sahin |
0:55f664e8c56c | 211 | } bits; |
Okan Sahin |
0:55f664e8c56c | 212 | } reg_intm_glbl0_t; |
Okan Sahin |
0:55f664e8c56c | 213 | |
Okan Sahin |
0:55f664e8c56c | 214 | /** |
Okan Sahin |
0:55f664e8c56c | 215 | * @brief INTM_GLBL1 Register |
Okan Sahin |
0:55f664e8c56c | 216 | * |
Okan Sahin |
0:55f664e8c56c | 217 | * Address : 0x05 |
Okan Sahin |
0:55f664e8c56c | 218 | */ |
Okan Sahin |
0:55f664e8c56c | 219 | typedef union { |
Okan Sahin |
0:55f664e8c56c | 220 | unsigned char raw; |
Okan Sahin |
0:55f664e8c56c | 221 | struct { |
Okan Sahin |
0:55f664e8c56c | 222 | unsigned char gpi1_fm : 1; /**< GPI Falling Interrupt Mask. Bit 0. |
Okan Sahin |
0:55f664e8c56c | 223 | 0 = Unmasked. If GPI_F goes from 0 to 1, then nIRQ goes low. |
Okan Sahin |
0:55f664e8c56c | 224 | nIRQ goes high when all interrupt bits are cleared. |
Okan Sahin |
0:55f664e8c56c | 225 | 1 = Masked. nIRQ does not go low due to GPI_F. */ |
Okan Sahin |
0:55f664e8c56c | 226 | unsigned char gpi1_rm : 1; /**< GPI Rising Interrupt Mask. Bit 1. |
Okan Sahin |
0:55f664e8c56c | 227 | 0 = Unmasked. If GPI_R goes from 0 to 1, then nIRQ goes low. |
Okan Sahin |
0:55f664e8c56c | 228 | nIRQ goes high when all interrupt bits are cleared. |
Okan Sahin |
0:55f664e8c56c | 229 | 1 = Masked. nIRQ does not go low due to GPI_R. */ |
Okan Sahin |
0:55f664e8c56c | 230 | unsigned char sbb0_fm : 1; /**< SBB0 Fault Interrupt Mask. Bit 2. |
Okan Sahin |
0:55f664e8c56c | 231 | 0 = Unmasked. If SBB0_F goes from 0 to 1, then nIRQ goes low. |
Okan Sahin |
0:55f664e8c56c | 232 | nIRQ goes high when all interrupt bits are cleared.. |
Okan Sahin |
0:55f664e8c56c | 233 | 1 = Masked. nIRQ does not go low due to SBB0_F. */ |
Okan Sahin |
0:55f664e8c56c | 234 | unsigned char sbb1_fm : 1; /**< SBB1 Fault Interrupt Mask. Bit 3. |
Okan Sahin |
0:55f664e8c56c | 235 | 0 = Unmasked. If SBB1_F goes from 0 to 1, then nIRQ goes low. |
Okan Sahin |
0:55f664e8c56c | 236 | nIRQ goes high when all interrupt bits are cleared.. |
Okan Sahin |
0:55f664e8c56c | 237 | 1 = Masked. nIRQ does not go low due to SBB1_F. */ |
Okan Sahin |
0:55f664e8c56c | 238 | unsigned char sbb2_fm : 1; /**< SBB2 Fault Interrupt Mask. Bit 4. |
Okan Sahin |
0:55f664e8c56c | 239 | 0 = Unmasked. If SBB2_F goes from 0 to 1, then nIRQ goes low. |
Okan Sahin |
0:55f664e8c56c | 240 | nIRQ goes high when all interrupt bits are cleared.. |
Okan Sahin |
0:55f664e8c56c | 241 | 1 = Masked. nIRQ does not go low due to SBB2_F. */ |
Okan Sahin |
0:55f664e8c56c | 242 | unsigned char ldo_m : 1; /**< LDO0 Fault Interrupt. Bit 5. |
Okan Sahin |
0:55f664e8c56c | 243 | 0 = Unmasked. If LDO0_F goes from 0 to 1, then nIRQ goes low. |
Okan Sahin |
0:55f664e8c56c | 244 | nIRQ goes high when all interrupt bits are cleared. |
Okan Sahin |
0:55f664e8c56c | 245 | 1 = Masked. nIRQ does not go low due to LDO0_F. */ |
Okan Sahin |
0:55f664e8c56c | 246 | unsigned char rsvd : 2; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 7:6. */ |
Okan Sahin |
0:55f664e8c56c | 247 | } bits; |
Okan Sahin |
0:55f664e8c56c | 248 | } reg_intm_glbl1_t; |
Okan Sahin |
0:55f664e8c56c | 249 | |
Okan Sahin |
0:55f664e8c56c | 250 | /** |
Okan Sahin |
0:55f664e8c56c | 251 | * @brief CNFG_GLBL0 Register |
Okan Sahin |
0:55f664e8c56c | 252 | * |
Okan Sahin |
0:55f664e8c56c | 253 | * Address : 0x06 |
Okan Sahin |
0:55f664e8c56c | 254 | */ |
Okan Sahin |
0:55f664e8c56c | 255 | typedef union { |
Okan Sahin |
0:55f664e8c56c | 256 | unsigned char raw; |
Okan Sahin |
0:55f664e8c56c | 257 | struct { |
Okan Sahin |
0:55f664e8c56c | 258 | unsigned char sft_ctrl : 2; /**< Software Reset Functions. Bit 1:0. |
Okan Sahin |
0:55f664e8c56c | 259 | 0b00 = No Action |
Okan Sahin |
0:55f664e8c56c | 260 | 0b01 = Software Cold Reset (SFT_CRST). The device powers down, resets, and the powers up again. |
Okan Sahin |
0:55f664e8c56c | 261 | 0b10 = Software Off (SFT_OFF). The device powers down, resets, and then remains off and waiting for a wake-up event. |
Okan Sahin |
0:55f664e8c56c | 262 | 0b11 = Auto Wake Up (SFT_AUTO). */ |
Okan Sahin |
0:55f664e8c56c | 263 | unsigned char dben_nen : 1; /**< Debounce Timer Enable for the nEN Pin. Bit 2. |
Okan Sahin |
0:55f664e8c56c | 264 | 0 = 500μs Debounce |
Okan Sahin |
0:55f664e8c56c | 265 | 1 = 30ms Debounce */ |
Okan Sahin |
0:55f664e8c56c | 266 | unsigned char nen_mode : 2; /**< nEN Input (ON-KEY) Default Configuration Mode. Bit 4:3. |
Okan Sahin |
0:55f664e8c56c | 267 | 0b00 = Push-button mode |
Okan Sahin |
0:55f664e8c56c | 268 | 0b01 = Slide-switch mode |
Okan Sahin |
0:55f664e8c56c | 269 | 0b10 = Logic mode |
Okan Sahin |
0:55f664e8c56c | 270 | 0b11 = Reserved */ |
Okan Sahin |
0:55f664e8c56c | 271 | unsigned char sbia_lpm : 1; /**< Main Bias Low-Power Mode Software Request. Bit 5. |
Okan Sahin |
0:55f664e8c56c | 272 | 0 = Main Bias requested to be in Normal-Power Mode by software. |
Okan Sahin |
0:55f664e8c56c | 273 | 1 = Main Bias request to be in Low-Power Mode by software. */ |
Okan Sahin |
0:55f664e8c56c | 274 | unsigned char t_mrst : 1; /**< Sets the Manual Reset Time (tMRST). Bit 6. |
Okan Sahin |
0:55f664e8c56c | 275 | 0 = 8s |
Okan Sahin |
0:55f664e8c56c | 276 | 1 = 4s */ |
Okan Sahin |
0:55f664e8c56c | 277 | unsigned char pu_dis : 1; /**< nEN Internal Pullup Resistor. Bit 7. |
Okan Sahin |
0:55f664e8c56c | 278 | 0 = Strong internal nEN pullup (200kΩ) |
Okan Sahin |
0:55f664e8c56c | 279 | 1 = Weak internal nEN pullup (10MΩ) */ |
Okan Sahin |
0:55f664e8c56c | 280 | } bits; |
Okan Sahin |
0:55f664e8c56c | 281 | } reg_cnfg_glbl0_t; |
Okan Sahin |
0:55f664e8c56c | 282 | |
Okan Sahin |
0:55f664e8c56c | 283 | /** |
Okan Sahin |
0:55f664e8c56c | 284 | * @brief CNFG_GLBL1 Register |
Okan Sahin |
0:55f664e8c56c | 285 | * |
Okan Sahin |
0:55f664e8c56c | 286 | * Address : 0x07 |
Okan Sahin |
0:55f664e8c56c | 287 | */ |
Okan Sahin |
0:55f664e8c56c | 288 | typedef union { |
Okan Sahin |
0:55f664e8c56c | 289 | unsigned char raw; |
Okan Sahin |
0:55f664e8c56c | 290 | struct { |
Okan Sahin |
0:55f664e8c56c | 291 | unsigned char auto_wkt : 2; /**< Auto Wake-Up Timer. Bit 1:0. |
Okan Sahin |
0:55f664e8c56c | 292 | 0b00 = 100ms Auto Wake-up Time |
Okan Sahin |
0:55f664e8c56c | 293 | 0b01 = 200ms Auto Wake-up Time |
Okan Sahin |
0:55f664e8c56c | 294 | 0b10 = 500ms Auto Wake-up Time |
Okan Sahin |
0:55f664e8c56c | 295 | 0b11 = 1000ms Auto Wake-up Time */ |
Okan Sahin |
0:55f664e8c56c | 296 | unsigned char sbb_f_shutdn : 1; /**< SBB Shutdown from SBB Fault. Bit 2. |
Okan Sahin |
0:55f664e8c56c | 297 | 0 = 500μs Debounce |
Okan Sahin |
0:55f664e8c56c | 298 | 1 = 30ms Debounce */ |
Okan Sahin |
0:55f664e8c56c | 299 | unsigned char rsvd : 5; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care */ |
Okan Sahin |
0:55f664e8c56c | 300 | } bits; |
Okan Sahin |
0:55f664e8c56c | 301 | } reg_cnfg_glbl1_t; |
Okan Sahin |
0:55f664e8c56c | 302 | |
Okan Sahin |
0:55f664e8c56c | 303 | /** |
Okan Sahin |
0:55f664e8c56c | 304 | * @brief CNFG_GPIO0 Register |
Okan Sahin |
0:55f664e8c56c | 305 | * |
Okan Sahin |
0:55f664e8c56c | 306 | * Address : 0x08 |
Okan Sahin |
0:55f664e8c56c | 307 | */ |
Okan Sahin |
0:55f664e8c56c | 308 | typedef union { |
Okan Sahin |
0:55f664e8c56c | 309 | unsigned char raw; |
Okan Sahin |
0:55f664e8c56c | 310 | struct { |
Okan Sahin |
0:55f664e8c56c | 311 | unsigned char gpo_dir : 1; /**< GPIO Direction. Bit 0. |
Okan Sahin |
0:55f664e8c56c | 312 | 0 = General purpose output (GPO) |
Okan Sahin |
0:55f664e8c56c | 313 | 1 = General purpose input (GPI) */ |
Okan Sahin |
0:55f664e8c56c | 314 | unsigned char gpo_di : 1; /**< GPIO Digital Input Value. Bit 1. |
Okan Sahin |
0:55f664e8c56c | 315 | 0 = Input logic low |
Okan Sahin |
0:55f664e8c56c | 316 | 1 = Input logic high */ |
Okan Sahin |
0:55f664e8c56c | 317 | unsigned char gpo_drv : 1; /**< General Purpose Output Driver Type. Bit 2. |
Okan Sahin |
0:55f664e8c56c | 318 | This bit is a don't care when DIR = 1 (configured as input) When set for GPO (DIR = 0): |
Okan Sahin |
0:55f664e8c56c | 319 | 0 = Open-Drain |
Okan Sahin |
0:55f664e8c56c | 320 | 1 = Push-Pull */ |
Okan Sahin |
0:55f664e8c56c | 321 | unsigned char gpo_do : 1; /**< General Purpose Output Data Output. Bit 3. |
Okan Sahin |
0:55f664e8c56c | 322 | This bit is a don't care when DIR = 1 (configured as input). When set for GPO (DIR = 0): |
Okan Sahin |
0:55f664e8c56c | 323 | 0 = GPIO is output is logic low |
Okan Sahin |
0:55f664e8c56c | 324 | 1 = GPIO is output logic high when set as push-pull output (DRV = 1). */ |
Okan Sahin |
0:55f664e8c56c | 325 | unsigned char dben_gpi : 1; /**< General Purpose Input Debounce Timer Enable. Bit 4. |
Okan Sahin |
0:55f664e8c56c | 326 | 0 = no debounce |
Okan Sahin |
0:55f664e8c56c | 327 | 1 = 30ms debounce */ |
Okan Sahin |
0:55f664e8c56c | 328 | unsigned char alt_gpio : 1; /**< Alternate Mode Enable for GPIO0. Bit 5. |
Okan Sahin |
0:55f664e8c56c | 329 | 0 = Standard GPIO. |
Okan Sahin |
0:55f664e8c56c | 330 | 1 = Active-high input, Force USB Suspend (FUS). FUS is only active if the FUS_M bit is set to 0. */ |
Okan Sahin |
0:55f664e8c56c | 331 | unsigned char rsvd : 2; /**< Reserved. Bit 7:6. Unutilized bit. Write to 0. Reads are don't care. */ |
Okan Sahin |
0:55f664e8c56c | 332 | } bits; |
Okan Sahin |
0:55f664e8c56c | 333 | } reg_cnfg_gpio0_t; |
Okan Sahin |
0:55f664e8c56c | 334 | |
Okan Sahin |
0:55f664e8c56c | 335 | /** |
Okan Sahin |
0:55f664e8c56c | 336 | * @brief CNFG_GPIO1 Register |
Okan Sahin |
0:55f664e8c56c | 337 | * |
Okan Sahin |
0:55f664e8c56c | 338 | * Address : 0x09 |
Okan Sahin |
0:55f664e8c56c | 339 | */ |
Okan Sahin |
0:55f664e8c56c | 340 | typedef union { |
Okan Sahin |
0:55f664e8c56c | 341 | unsigned char raw; |
Okan Sahin |
0:55f664e8c56c | 342 | struct { |
Okan Sahin |
0:55f664e8c56c | 343 | unsigned char gpo_dir : 1; /**< GPIO Direction. Bit 0. |
Okan Sahin |
0:55f664e8c56c | 344 | 0 = General purpose output (GPO) |
Okan Sahin |
0:55f664e8c56c | 345 | 1 = General purpose input (GPI) */ |
Okan Sahin |
0:55f664e8c56c | 346 | unsigned char gpo_di : 1; /**< GPIO Digital Input Value. Bit 1. |
Okan Sahin |
0:55f664e8c56c | 347 | 0 = Input logic low |
Okan Sahin |
0:55f664e8c56c | 348 | 1 = Input logic high */ |
Okan Sahin |
0:55f664e8c56c | 349 | unsigned char gpo_drv : 1; /**< General Purpose Output Driver Type. Bit 2. |
Okan Sahin |
0:55f664e8c56c | 350 | This bit is a don't care when DIR = 1 (configured as input) When set for GPO (DIR = 0): |
Okan Sahin |
0:55f664e8c56c | 351 | 0 = Open-Drain |
Okan Sahin |
0:55f664e8c56c | 352 | 1 = Push-Pull */ |
Okan Sahin |
0:55f664e8c56c | 353 | unsigned char gpo_do : 1; /**< General Purpose Output Data Output. Bit 3. |
Okan Sahin |
0:55f664e8c56c | 354 | This bit is a don't care when DIR = 1 (configured as input). When set for GPO (DIR = 0): |
Okan Sahin |
0:55f664e8c56c | 355 | 0 = GPIO is output is logic low |
Okan Sahin |
0:55f664e8c56c | 356 | 1 = GPIO is output logic high when set as push-pull output (DRV = 1). */ |
Okan Sahin |
0:55f664e8c56c | 357 | unsigned char dben_gpi : 1; /**< General Purpose Input Debounce Timer Enable. Bit 4. |
Okan Sahin |
0:55f664e8c56c | 358 | 0 = no debounce |
Okan Sahin |
0:55f664e8c56c | 359 | 1 = 30ms debounce */ |
Okan Sahin |
0:55f664e8c56c | 360 | unsigned char alt_gpio : 1; /**< Alternate Mode Enable for GPIO1. Bit 5. |
Okan Sahin |
0:55f664e8c56c | 361 | 0 = Standard GPIO. |
Okan Sahin |
0:55f664e8c56c | 362 | 1 = Active-high output of SBB2's Flexible Power Sequencer (FPS) slot. */ |
Okan Sahin |
0:55f664e8c56c | 363 | unsigned char rsvd : 2; /**< Reserved. Bit 7:6. |
Okan Sahin |
0:55f664e8c56c | 364 | Unutilized bit. Write to 0. Reads are don't care. */ |
Okan Sahin |
0:55f664e8c56c | 365 | } bits; |
Okan Sahin |
0:55f664e8c56c | 366 | } reg_cnfg_gpio1_t; |
Okan Sahin |
0:55f664e8c56c | 367 | |
Okan Sahin |
0:55f664e8c56c | 368 | /** |
Okan Sahin |
0:55f664e8c56c | 369 | * @brief CID Register |
Okan Sahin |
0:55f664e8c56c | 370 | * |
Okan Sahin |
0:55f664e8c56c | 371 | * Address : 0x10 |
Okan Sahin |
0:55f664e8c56c | 372 | */ |
Okan Sahin |
0:55f664e8c56c | 373 | typedef union { |
Okan Sahin |
0:55f664e8c56c | 374 | unsigned char raw; |
Okan Sahin |
0:55f664e8c56c | 375 | struct { |
Okan Sahin |
0:55f664e8c56c | 376 | unsigned char cid : 5; /**< Chip Identification Code. Bit 4:0. |
Okan Sahin |
0:55f664e8c56c | 377 | The Chip Identification Code refers to a set of reset values in the register map, or the "OTP configuration.". */ |
Okan Sahin |
0:55f664e8c56c | 378 | unsigned char : 3; /**< Bit 7:5. */ |
Okan Sahin |
0:55f664e8c56c | 379 | } bits; |
Okan Sahin |
0:55f664e8c56c | 380 | } reg_cid_t; |
Okan Sahin |
0:55f664e8c56c | 381 | |
Okan Sahin |
0:55f664e8c56c | 382 | /** |
Okan Sahin |
0:55f664e8c56c | 383 | * @brief CNFG_WDT Register |
Okan Sahin |
0:55f664e8c56c | 384 | * |
Okan Sahin |
0:55f664e8c56c | 385 | * Address : 0x17 |
Okan Sahin |
0:55f664e8c56c | 386 | */ |
Okan Sahin |
0:55f664e8c56c | 387 | typedef union { |
Okan Sahin |
0:55f664e8c56c | 388 | unsigned char raw; |
Okan Sahin |
0:55f664e8c56c | 389 | struct { |
Okan Sahin |
0:55f664e8c56c | 390 | unsigned char wdt_lock : 1; /**< Factory-Set Safety Bit for the Watchdog Timer. Bit 0. |
Okan Sahin |
0:55f664e8c56c | 391 | 0 = Watchdog timer can be enabled and disabled with WDT_EN. |
Okan Sahin |
0:55f664e8c56c | 392 | 1 = Watchdog timer can not be disabled with WDT_EN. |
Okan Sahin |
0:55f664e8c56c | 393 | However, WDT_EN can still be used to enable the watchdog timer. */ |
Okan Sahin |
0:55f664e8c56c | 394 | unsigned char wdt_en : 1; /**< Watchdog Timer Enable. Bit 1. |
Okan Sahin |
0:55f664e8c56c | 395 | 0 = Watchdog timer is not enabled. |
Okan Sahin |
0:55f664e8c56c | 396 | 1 = Watchdog timer is enabled. The timer will expire if not reset by setting WDT_CLR. */ |
Okan Sahin |
0:55f664e8c56c | 397 | unsigned char wdt_clr : 1; /**< Watchdog Timer Clear Control. Bit 2. |
Okan Sahin |
0:55f664e8c56c | 398 | 0 = Watchdog timer period is not reset. |
Okan Sahin |
0:55f664e8c56c | 399 | 1 = Watchdog timer is reset back to tWD. */ |
Okan Sahin |
0:55f664e8c56c | 400 | unsigned char wdt_mode : 1; /**< Watchdog Timer Expired Action. Bit 3. |
Okan Sahin |
0:55f664e8c56c | 401 | 0 = Watchdog timer expire causes power-off. |
Okan Sahin |
0:55f664e8c56c | 402 | 1 = Watchdog timer expire causes power-reset. */ |
Okan Sahin |
0:55f664e8c56c | 403 | unsigned char wdt_per : 2; /**< Watchdog Timer Period. Bit 5:4. |
Okan Sahin |
0:55f664e8c56c | 404 | 0b00 = 16 seconds 0b01 = 32 seconds |
Okan Sahin |
0:55f664e8c56c | 405 | 0b10 = 64 seconds 0b11 = 128 seconds. */ |
Okan Sahin |
0:55f664e8c56c | 406 | unsigned char rsvd : 2; /**< Reserved. Bit 7:6. |
Okan Sahin |
0:55f664e8c56c | 407 | Unutilized bit. Write to 0. Reads are don't care. */ |
Okan Sahin |
0:55f664e8c56c | 408 | } bits; |
Okan Sahin |
0:55f664e8c56c | 409 | } reg_cnfg_wdt_t; |
Okan Sahin |
0:55f664e8c56c | 410 | |
Okan Sahin |
0:55f664e8c56c | 411 | /** |
Okan Sahin |
0:55f664e8c56c | 412 | * @brief CNFG_SBB_TOP |
Okan Sahin |
0:55f664e8c56c | 413 | * |
Okan Sahin |
0:55f664e8c56c | 414 | * Address : 0x28 |
Okan Sahin |
0:55f664e8c56c | 415 | */ |
Okan Sahin |
0:55f664e8c56c | 416 | typedef union { |
Okan Sahin |
0:55f664e8c56c | 417 | unsigned char raw; |
Okan Sahin |
0:55f664e8c56c | 418 | struct |
Okan Sahin |
0:55f664e8c56c | 419 | { |
Okan Sahin |
0:55f664e8c56c | 420 | unsigned char drv_sbb : 2; /**< SIMO Buck-Boost (all channels) Drive Strength Trim. Bit 1:0. |
Okan Sahin |
0:55f664e8c56c | 421 | 0b00 = Fastest transition time |
Okan Sahin |
0:55f664e8c56c | 422 | 0b01 = A little slower than 0b00 |
Okan Sahin |
0:55f664e8c56c | 423 | 0b10 = A little slower than 0b01 |
Okan Sahin |
0:55f664e8c56c | 424 | 0b11 = A little slower than 0b10 */ |
Okan Sahin |
0:55f664e8c56c | 425 | unsigned char : 5; /**< Bit 6:2.*/ |
Okan Sahin |
0:55f664e8c56c | 426 | unsigned char dis_lpm : 1; /**< Disables the automatic Low Power Mode for Each SIMO Channel. Bit 7. |
Okan Sahin |
0:55f664e8c56c | 427 | 0b0 = Automatic Low Power Mode for each SIMO channel |
Okan Sahin |
0:55f664e8c56c | 428 | 0b1 = Disable LPM feature for each SIMO channel */ |
Okan Sahin |
0:55f664e8c56c | 429 | } bits; |
Okan Sahin |
0:55f664e8c56c | 430 | } reg_cnfg_sbb_top_t; |
Okan Sahin |
0:55f664e8c56c | 431 | |
Okan Sahin |
0:55f664e8c56c | 432 | /** |
Okan Sahin |
0:55f664e8c56c | 433 | * @brief CNFG_SBB0_A |
Okan Sahin |
0:55f664e8c56c | 434 | * |
Okan Sahin |
0:55f664e8c56c | 435 | * Address : 0x29 |
Okan Sahin |
0:55f664e8c56c | 436 | */ |
Okan Sahin |
0:55f664e8c56c | 437 | typedef union { |
Okan Sahin |
0:55f664e8c56c | 438 | unsigned char raw; |
Okan Sahin |
0:55f664e8c56c | 439 | struct |
Okan Sahin |
0:55f664e8c56c | 440 | { |
Okan Sahin |
0:55f664e8c56c | 441 | unsigned char tv_sbb0 : 8; /**< SIMO Buck-Boost Channel 0 Target Output Voltage. Bit 7:0. |
Okan Sahin |
0:55f664e8c56c | 442 | 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V |
Okan Sahin |
0:55f664e8c56c | 443 | 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V |
Okan Sahin |
0:55f664e8c56c | 444 | 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V |
Okan Sahin |
0:55f664e8c56c | 445 | ... |
Okan Sahin |
0:55f664e8c56c | 446 | 0xC5 = 5.425V 0xC6 = 5.450V 0xC7 = 5.475V |
Okan Sahin |
0:55f664e8c56c | 447 | 0xC8 to 0xFF = 5.500V */ |
Okan Sahin |
0:55f664e8c56c | 448 | } bits; |
Okan Sahin |
0:55f664e8c56c | 449 | } reg_cnfg_sbb0_a_t; |
Okan Sahin |
0:55f664e8c56c | 450 | |
Okan Sahin |
0:55f664e8c56c | 451 | /** |
Okan Sahin |
0:55f664e8c56c | 452 | * @brief CNFG_SBB0_B |
Okan Sahin |
0:55f664e8c56c | 453 | * |
Okan Sahin |
0:55f664e8c56c | 454 | * Address : 0x2A |
Okan Sahin |
0:55f664e8c56c | 455 | */ |
Okan Sahin |
0:55f664e8c56c | 456 | typedef union { |
Okan Sahin |
0:55f664e8c56c | 457 | unsigned char raw; |
Okan Sahin |
0:55f664e8c56c | 458 | struct |
Okan Sahin |
0:55f664e8c56c | 459 | { |
Okan Sahin |
0:55f664e8c56c | 460 | unsigned char en_sbb0 : 3; /**< Enable Control for SIMO Buck-Boost Channel 0, |
Okan Sahin |
0:55f664e8c56c | 461 | selecting either an FPS slot the channel powers-up and powers-down in |
Okan Sahin |
0:55f664e8c56c | 462 | or whether the channel is forced on or off. Bit 2:0. |
Okan Sahin |
0:55f664e8c56c | 463 | 0b000 = FPS slot 0 0b001 = FPS slot 1 |
Okan Sahin |
0:55f664e8c56c | 464 | 0b010 = FPS slot 2 0b011 = FPS slot 3 |
Okan Sahin |
0:55f664e8c56c | 465 | 0b100 = Off irrespective of FPS |
Okan Sahin |
0:55f664e8c56c | 466 | 0b101 = same as 0b100 0b110 = On irrespective of FPS |
Okan Sahin |
0:55f664e8c56c | 467 | 0b111 = same as 0b110 */ |
Okan Sahin |
0:55f664e8c56c | 468 | unsigned char ade_sbb0 : 1; /**< SIMO Buck-Boost Channel 0 Active-Discharge Enable. Bit 3. |
Okan Sahin |
0:55f664e8c56c | 469 | 0 = The active discharge function is disabled. |
Okan Sahin |
0:55f664e8c56c | 470 | When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load. |
Okan Sahin |
0:55f664e8c56c | 471 | 1 = The active discharge function is enabled. |
Okan Sahin |
0:55f664e8c56c | 472 | When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */ |
Okan Sahin |
0:55f664e8c56c | 473 | unsigned char ip_sbb0 : 2; /**< SIMO Buck-Boost Channel 0 Peak Current Limit. Bit 5:4 |
Okan Sahin |
0:55f664e8c56c | 474 | 0b00 = 1.000A 0b01 = 0.750A |
Okan Sahin |
0:55f664e8c56c | 475 | 0b10 = 0.500A 0b11 = 0.333A*/ |
Okan Sahin |
0:55f664e8c56c | 476 | unsigned char op_mode0 : 2; /**< Operation mode of SBB0. Bit 6. |
Okan Sahin |
0:55f664e8c56c | 477 | 0b00 = Automatic |
Okan Sahin |
0:55f664e8c56c | 478 | 0b01 = Buck mode |
Okan Sahin |
0:55f664e8c56c | 479 | 0b10 = Boost mode |
Okan Sahin |
0:55f664e8c56c | 480 | 0b11 = Buck-boost mode*/ |
Okan Sahin |
0:55f664e8c56c | 481 | } bits; |
Okan Sahin |
0:55f664e8c56c | 482 | } reg_cnfg_sbb0_b_t; |
Okan Sahin |
0:55f664e8c56c | 483 | |
Okan Sahin |
0:55f664e8c56c | 484 | /** |
Okan Sahin |
0:55f664e8c56c | 485 | * @brief CNFG_SBB1_A |
Okan Sahin |
0:55f664e8c56c | 486 | * |
Okan Sahin |
0:55f664e8c56c | 487 | * Address : 0x2B |
Okan Sahin |
0:55f664e8c56c | 488 | */ |
Okan Sahin |
0:55f664e8c56c | 489 | typedef union { |
Okan Sahin |
0:55f664e8c56c | 490 | unsigned char raw; |
Okan Sahin |
0:55f664e8c56c | 491 | struct |
Okan Sahin |
0:55f664e8c56c | 492 | { |
Okan Sahin |
0:55f664e8c56c | 493 | unsigned char tv_sbb1 : 8; /**< SIMO Buck-Boost Channel 1 Target Output Voltage. Bit 7:0. |
Okan Sahin |
0:55f664e8c56c | 494 | 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V |
Okan Sahin |
0:55f664e8c56c | 495 | 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V |
Okan Sahin |
0:55f664e8c56c | 496 | 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V |
Okan Sahin |
0:55f664e8c56c | 497 | ... |
Okan Sahin |
0:55f664e8c56c | 498 | 0xC5 = 5.425V 0xC6 = 5.450V 0xC7 = 5.475V |
Okan Sahin |
0:55f664e8c56c | 499 | 0xC8 to 0xFF = 5.500V */ |
Okan Sahin |
0:55f664e8c56c | 500 | } bits; |
Okan Sahin |
0:55f664e8c56c | 501 | } reg_cnfg_sbb1_a_t; |
Okan Sahin |
0:55f664e8c56c | 502 | |
Okan Sahin |
0:55f664e8c56c | 503 | /** |
Okan Sahin |
0:55f664e8c56c | 504 | * @brief CNFG_SBB1_B |
Okan Sahin |
0:55f664e8c56c | 505 | * |
Okan Sahin |
0:55f664e8c56c | 506 | * Address : 0x3C |
Okan Sahin |
0:55f664e8c56c | 507 | */ |
Okan Sahin |
0:55f664e8c56c | 508 | typedef union { |
Okan Sahin |
0:55f664e8c56c | 509 | unsigned char raw; |
Okan Sahin |
0:55f664e8c56c | 510 | struct |
Okan Sahin |
0:55f664e8c56c | 511 | { |
Okan Sahin |
0:55f664e8c56c | 512 | unsigned char en_sbb1 : 3; /**< Enable Control for SIMO Buck-Boost Channel 1, |
Okan Sahin |
0:55f664e8c56c | 513 | selecting either an FPS slot the channel powers-up and powers-down in |
Okan Sahin |
0:55f664e8c56c | 514 | or whether the channel is forced on or off. Bit 2:0. |
Okan Sahin |
0:55f664e8c56c | 515 | 0b000 = FPS slot 0 0b001 = FPS slot 1 |
Okan Sahin |
0:55f664e8c56c | 516 | 0b010 = FPS slot 2 0b011 = FPS slot 3 |
Okan Sahin |
0:55f664e8c56c | 517 | 0b100 = Off irrespective of FPS |
Okan Sahin |
0:55f664e8c56c | 518 | 0b101 = same as 0b100 0b110 = On irrespective of FPS |
Okan Sahin |
0:55f664e8c56c | 519 | 0b111 = same as 0b110 */ |
Okan Sahin |
0:55f664e8c56c | 520 | unsigned char ade_sbb1 : 1; /**< SIMO Buck-Boost Channel 1 Active-Discharge Enable. Bit 3. |
Okan Sahin |
0:55f664e8c56c | 521 | 0 = The active discharge function is disabled. |
Okan Sahin |
0:55f664e8c56c | 522 | When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load. |
Okan Sahin |
0:55f664e8c56c | 523 | 1 = The active discharge function is enabled. |
Okan Sahin |
0:55f664e8c56c | 524 | When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */ |
Okan Sahin |
0:55f664e8c56c | 525 | unsigned char ip_sbb1 : 2; /**< SIMO Buck-Boost Channel 1 Peak Current Limit. Bit 5:4. |
Okan Sahin |
0:55f664e8c56c | 526 | 0b00 = 1.000A 0b01 = 0.750A |
Okan Sahin |
0:55f664e8c56c | 527 | 0b10 = 0.500A 0b11 = 0.333A*/ |
Okan Sahin |
0:55f664e8c56c | 528 | unsigned char op_mode1 : 2; /**< Operation mode of SBB1. Bit 7:6. |
Okan Sahin |
0:55f664e8c56c | 529 | 0b00 = Automatic |
Okan Sahin |
0:55f664e8c56c | 530 | 0b01 = Buck mode |
Okan Sahin |
0:55f664e8c56c | 531 | 0b10 = Boost mode |
Okan Sahin |
0:55f664e8c56c | 532 | 0b11 = Buck-boost mode*/ |
Okan Sahin |
0:55f664e8c56c | 533 | } bits; |
Okan Sahin |
0:55f664e8c56c | 534 | } reg_cnfg_sbb1_b_t; |
Okan Sahin |
0:55f664e8c56c | 535 | |
Okan Sahin |
0:55f664e8c56c | 536 | /** |
Okan Sahin |
0:55f664e8c56c | 537 | * @brief CNFG_SBB2_A |
Okan Sahin |
0:55f664e8c56c | 538 | * |
Okan Sahin |
0:55f664e8c56c | 539 | * Address : 0x2D |
Okan Sahin |
0:55f664e8c56c | 540 | */ |
Okan Sahin |
0:55f664e8c56c | 541 | typedef union { |
Okan Sahin |
0:55f664e8c56c | 542 | unsigned char raw; |
Okan Sahin |
0:55f664e8c56c | 543 | struct |
Okan Sahin |
0:55f664e8c56c | 544 | { |
Okan Sahin |
0:55f664e8c56c | 545 | unsigned char tv_sbb2 : 8; /**< SIMO Buck-Boost Channel 2 Target Output Voltage. Bit 7:0. |
Okan Sahin |
0:55f664e8c56c | 546 | 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V |
Okan Sahin |
0:55f664e8c56c | 547 | 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V |
Okan Sahin |
0:55f664e8c56c | 548 | 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V |
Okan Sahin |
0:55f664e8c56c | 549 | ... |
Okan Sahin |
0:55f664e8c56c | 550 | 0xC5 = 5.425V 0xC6 = 5.450V 0xC7 = 5.475V |
Okan Sahin |
0:55f664e8c56c | 551 | 0xC8 to 0xFF = 5.500V */ |
Okan Sahin |
0:55f664e8c56c | 552 | } bits; |
Okan Sahin |
0:55f664e8c56c | 553 | } reg_cnfg_sbb2_a_t; |
Okan Sahin |
0:55f664e8c56c | 554 | |
Okan Sahin |
0:55f664e8c56c | 555 | /** |
Okan Sahin |
0:55f664e8c56c | 556 | * @brief CNFG_SBB2_B |
Okan Sahin |
0:55f664e8c56c | 557 | * |
Okan Sahin |
0:55f664e8c56c | 558 | * Address : 0x2E |
Okan Sahin |
0:55f664e8c56c | 559 | */ |
Okan Sahin |
0:55f664e8c56c | 560 | typedef union { |
Okan Sahin |
0:55f664e8c56c | 561 | unsigned char raw; |
Okan Sahin |
0:55f664e8c56c | 562 | struct |
Okan Sahin |
0:55f664e8c56c | 563 | { |
Okan Sahin |
0:55f664e8c56c | 564 | unsigned char en_sbb2 : 3; /**< Enable Control for SIMO Buck-Boost Channel 2, |
Okan Sahin |
0:55f664e8c56c | 565 | selecting either an FPS slot the channel powers-up and powers-down in |
Okan Sahin |
0:55f664e8c56c | 566 | or whether the channel is forced on or off. Bit 2:0. |
Okan Sahin |
0:55f664e8c56c | 567 | 0b000 = FPS slot 0 0b001 = FPS slot 1 |
Okan Sahin |
0:55f664e8c56c | 568 | 0b010 = FPS slot 2 0b011 = FPS slot 3 |
Okan Sahin |
0:55f664e8c56c | 569 | 0b100 = Off irrespective of FPS |
Okan Sahin |
0:55f664e8c56c | 570 | 0b101 = same as 0b100 0b110 = On irrespective of FPS |
Okan Sahin |
0:55f664e8c56c | 571 | 0b111 = same as 0b110 */ |
Okan Sahin |
0:55f664e8c56c | 572 | unsigned char ade_sbb2 : 1; /**< SIMO Buck-Boost Channel 2 Active-Discharge Enable Bit 3. |
Okan Sahin |
0:55f664e8c56c | 573 | 0 = The active discharge function is disabled. |
Okan Sahin |
0:55f664e8c56c | 574 | When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load. |
Okan Sahin |
0:55f664e8c56c | 575 | 1 = The active discharge function is enabled. |
Okan Sahin |
0:55f664e8c56c | 576 | When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */ |
Okan Sahin |
0:55f664e8c56c | 577 | unsigned char ip_sbb2 : 2; /**< SIMO Buck-Boost Channel 2 Peak Current Limit. Bit 5:4. |
Okan Sahin |
0:55f664e8c56c | 578 | 0b00 = 1.000A 0b01 = 0.750A |
Okan Sahin |
0:55f664e8c56c | 579 | 0b10 = 0.500A 0b11 = 0.333A*/ |
Okan Sahin |
0:55f664e8c56c | 580 | unsigned char op_mode2 : 2; /**< Operation mode of SBB2. Bit 7:6. |
Okan Sahin |
0:55f664e8c56c | 581 | 0b00 = Automatic |
Okan Sahin |
0:55f664e8c56c | 582 | 0b01 = Buck mode |
Okan Sahin |
0:55f664e8c56c | 583 | 0b10 = Boost mode |
Okan Sahin |
0:55f664e8c56c | 584 | 0b11 = Buck-boost mode*/ |
Okan Sahin |
0:55f664e8c56c | 585 | } bits; |
Okan Sahin |
0:55f664e8c56c | 586 | } reg_cnfg_sbb2_b_t; |
Okan Sahin |
0:55f664e8c56c | 587 | |
Okan Sahin |
0:55f664e8c56c | 588 | /** |
Okan Sahin |
0:55f664e8c56c | 589 | * @brief CNFG_DVS_SBB0_A |
Okan Sahin |
0:55f664e8c56c | 590 | * |
Okan Sahin |
0:55f664e8c56c | 591 | * Address : 0x2F |
Okan Sahin |
0:55f664e8c56c | 592 | */ |
Okan Sahin |
0:55f664e8c56c | 593 | typedef union { |
Okan Sahin |
0:55f664e8c56c | 594 | unsigned char raw; |
Okan Sahin |
0:55f664e8c56c | 595 | struct |
Okan Sahin |
0:55f664e8c56c | 596 | { |
Okan Sahin |
0:55f664e8c56c | 597 | unsigned char tv_sbb0_dvs : 8; /**< SIMO Buck-Boost Channel 0 Target Output Voltage. Bit 7:0. |
Okan Sahin |
0:55f664e8c56c | 598 | 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V |
Okan Sahin |
0:55f664e8c56c | 599 | 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V |
Okan Sahin |
0:55f664e8c56c | 600 | 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V |
Okan Sahin |
0:55f664e8c56c | 601 | ... |
Okan Sahin |
0:55f664e8c56c | 602 | 0xC5 = 5.425V 0xC6 = 5.450V 0xC7 = 5.475V |
Okan Sahin |
0:55f664e8c56c | 603 | 0xC8 to 0xFF = 5.500V */ |
Okan Sahin |
0:55f664e8c56c | 604 | } bits; |
Okan Sahin |
0:55f664e8c56c | 605 | } reg_cnfg_dvs_sbb0_a_t; |
Okan Sahin |
0:55f664e8c56c | 606 | |
Okan Sahin |
0:55f664e8c56c | 607 | /** |
Okan Sahin |
0:55f664e8c56c | 608 | * @brief CNFG_LDO0_A |
Okan Sahin |
0:55f664e8c56c | 609 | * |
Okan Sahin |
0:55f664e8c56c | 610 | * Address : 0x38 |
Okan Sahin |
0:55f664e8c56c | 611 | */ |
Okan Sahin |
0:55f664e8c56c | 612 | typedef union { |
Okan Sahin |
0:55f664e8c56c | 613 | unsigned char raw; |
Okan Sahin |
0:55f664e8c56c | 614 | struct |
Okan Sahin |
0:55f664e8c56c | 615 | { |
Okan Sahin |
0:55f664e8c56c | 616 | unsigned char tv_ldo0 : 7; /**< LDO0 Target Output Voltage. Bit 6:0. |
Okan Sahin |
0:55f664e8c56c | 617 | 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V |
Okan Sahin |
0:55f664e8c56c | 618 | 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V |
Okan Sahin |
0:55f664e8c56c | 619 | 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V |
Okan Sahin |
0:55f664e8c56c | 620 | ... |
Okan Sahin |
0:55f664e8c56c | 621 | 0x7E = 3.650V |
Okan Sahin |
0:55f664e8c56c | 622 | 0x7F = 3.675V |
Okan Sahin |
0:55f664e8c56c | 623 | When TV_LDO[7] = 0, TV_LDO[6:0] sets the |
Okan Sahin |
0:55f664e8c56c | 624 | LDO's output voltage range from 0.5V to 3.675V. |
Okan Sahin |
0:55f664e8c56c | 625 | When TV_LDO[7] = 1, TV_LDO[6:0] sets the |
Okan Sahin |
0:55f664e8c56c | 626 | LDO's output voltage from 1.825V to 5V. */ |
Okan Sahin |
0:55f664e8c56c | 627 | unsigned char tv_ofs_ldo : 1; /**< LDO0 Output Voltage. Bit7. |
Okan Sahin |
0:55f664e8c56c | 628 | This bit applies a 1.325V offset to the output voltage of the LDO0. |
Okan Sahin |
0:55f664e8c56c | 629 | 0b0 = No Offset, 0b1 = 1.325V Offset |
Okan Sahin |
0:55f664e8c56c | 630 | */ |
Okan Sahin |
0:55f664e8c56c | 631 | |
Okan Sahin |
0:55f664e8c56c | 632 | } bits; |
Okan Sahin |
0:55f664e8c56c | 633 | } reg_cnfg_ldo0_a_t; |
Okan Sahin |
0:55f664e8c56c | 634 | |
Okan Sahin |
0:55f664e8c56c | 635 | /** |
Okan Sahin |
0:55f664e8c56c | 636 | * @brief CNFG_LDO0_B |
Okan Sahin |
0:55f664e8c56c | 637 | * |
Okan Sahin |
0:55f664e8c56c | 638 | * Address : 0x39 |
Okan Sahin |
0:55f664e8c56c | 639 | */ |
Okan Sahin |
0:55f664e8c56c | 640 | typedef union { |
Okan Sahin |
0:55f664e8c56c | 641 | unsigned char raw; |
Okan Sahin |
0:55f664e8c56c | 642 | struct |
Okan Sahin |
0:55f664e8c56c | 643 | { |
Okan Sahin |
0:55f664e8c56c | 644 | unsigned char en_ldo : 3; /**< Enable Control for LDO0, |
Okan Sahin |
0:55f664e8c56c | 645 | selecting either an FPS slot the channel powers-up and |
Okan Sahin |
0:55f664e8c56c | 646 | powersdown in or whether the channel is forced on or off. Bit 2:0. |
Okan Sahin |
0:55f664e8c56c | 647 | 0b000 = FPS slot 0 0b001 = FPS slot 1 |
Okan Sahin |
0:55f664e8c56c | 648 | 0b010 = FPS slot 2 0b011 = FPS slot 3 |
Okan Sahin |
0:55f664e8c56c | 649 | 0b100 = Off irrespective of FPS |
Okan Sahin |
0:55f664e8c56c | 650 | 0b101 = same as 0b100 0b110 = On irrespective of FPS |
Okan Sahin |
0:55f664e8c56c | 651 | 0b111 = same as 0b110 */ |
Okan Sahin |
0:55f664e8c56c | 652 | unsigned char ade_ldo : 1; /**< LDO0 Active-Discharge Enable. Bit 3. |
Okan Sahin |
0:55f664e8c56c | 653 | 0 = The active discharge function is disabled. |
Okan Sahin |
0:55f664e8c56c | 654 | 1 = The active discharge function is enabled.*/ |
Okan Sahin |
0:55f664e8c56c | 655 | unsigned char ldo_md : 1; /**< Operation Mode of LDO0. Bit 4. |
Okan Sahin |
0:55f664e8c56c | 656 | 0b0 = Low dropout linear regulator (LDO) mode |
Okan Sahin |
0:55f664e8c56c | 657 | 0b1 = Load switch (LSW) mode*/ |
Okan Sahin |
0:55f664e8c56c | 658 | unsigned char rsvd : 3; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. */ |
Okan Sahin |
0:55f664e8c56c | 659 | } bits; |
Okan Sahin |
0:55f664e8c56c | 660 | } reg_cnfg_ldo0_b_t; |
Okan Sahin |
0:55f664e8c56c | 661 | |
Okan Sahin |
0:55f664e8c56c | 662 | #endif /* MAX77643_2_REGS_H_ */ |