Maxim Integrated / MAX5715

Maxim Integrated MAX5715 12-bit 4-channel voltage-output DAC

Dependents:   MAX5715BOB_Tester MAX5715BOB_12bit_4ch_SPI_DAC MAX5715BOB_Serial_Tester

MAX5715.cpp@6:d8d589ad1f5e, 2019-09-27 (annotated)

Committer:
whismanoid
Date:
Fri Sep 27 21:15:44 2019 -0700
Revision:
6:d8d589ad1f5e
Parent:
5:7894decf9375 
Added tag 2019-09-27_r1.0 for changeset 7894decf9375

Who changed what in which revision?

UserRevisionLine numberNew contents of line
whismanoid 0:777851395940 1 // /*******************************************************************************
whismanoid 0:777851395940 2 // * Copyright (C) 2019 Maxim Integrated Products, Inc., All Rights Reserved.
whismanoid 0:777851395940 3 // *
whismanoid 0:777851395940 4 // * Permission is hereby granted, free of charge, to any person obtaining a
whismanoid 0:777851395940 5 // * copy of this software and associated documentation files (the "Software"),
whismanoid 0:777851395940 6 // * to deal in the Software without restriction, including without limitation
whismanoid 0:777851395940 7 // * the rights to use, copy, modify, merge, publish, distribute, sublicense,
whismanoid 0:777851395940 8 // * and/or sell copies of the Software, and to permit persons to whom the
whismanoid 0:777851395940 9 // * Software is furnished to do so, subject to the following conditions:
whismanoid 0:777851395940 10 // *
whismanoid 0:777851395940 11 // * The above copyright notice and this permission notice shall be included
whismanoid 0:777851395940 12 // * in all copies or substantial portions of the Software.
whismanoid 0:777851395940 13 // *
whismanoid 0:777851395940 14 // * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
whismanoid 0:777851395940 15 // * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
whismanoid 0:777851395940 16 // * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
whismanoid 0:777851395940 17 // * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
whismanoid 0:777851395940 18 // * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
whismanoid 0:777851395940 19 // * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
whismanoid 0:777851395940 20 // * OTHER DEALINGS IN THE SOFTWARE.
whismanoid 0:777851395940 21 // *
whismanoid 0:777851395940 22 // * Except as contained in this notice, the name of Maxim Integrated
whismanoid 0:777851395940 23 // * Products, Inc. shall not be used except as stated in the Maxim Integrated
whismanoid 0:777851395940 24 // * Products, Inc. Branding Policy.
whismanoid 0:777851395940 25 // *
whismanoid 0:777851395940 26 // * The mere transfer of this software does not imply any licenses
whismanoid 0:777851395940 27 // * of trade secrets, proprietary technology, copyrights, patents,
whismanoid 0:777851395940 28 // * trademarks, maskwork rights, or any other form of intellectual
whismanoid 0:777851395940 29 // * property whatsoever. Maxim Integrated Products, Inc. retains all
whismanoid 0:777851395940 30 // * ownership rights.
whismanoid 0:777851395940 31 // *******************************************************************************
whismanoid 0:777851395940 32 // */
whismanoid 0:777851395940 33 // *********************************************************************
whismanoid 0:777851395940 34 // @file MAX5715.cpp
whismanoid 0:777851395940 35 // *********************************************************************
whismanoid 0:777851395940 36 // Device Driver file
whismanoid 0:777851395940 37 // DO NOT EDIT; except areas designated "CUSTOMIZE". Automatically generated file.
whismanoid 0:777851395940 38 // generated by XMLSystemOfDevicesToMBED.py
whismanoid 0:777851395940 39 // System Name = ExampleSystem
whismanoid 0:777851395940 40 // System Description = Device driver example
whismanoid 0:777851395940 41
whismanoid 0:777851395940 42 #include "MAX5715.h"
whismanoid 0:777851395940 43
whismanoid 0:777851395940 44 // Device Name = MAX5715
whismanoid 0:777851395940 45 // Device Description = Ultra-Small, 12-Bit, 4-Channel, Buffered Output Voltage DAC with Internal Reference and SPI Interface
whismanoid 5:7894decf9375 46 // Device DeviceBriefDescription = 12-bit 4-ch SPI VOUT DAC
whismanoid 0:777851395940 47 // Device Manufacturer = Maxim Integrated
whismanoid 0:777851395940 48 // Device PartNumber = MAX5715AAUD+
whismanoid 0:777851395940 49 // Device RegValue_Width = DataWidth16bit_HL
whismanoid 0:777851395940 50 //
whismanoid 0:777851395940 51 // DAC NumChannels = 4
whismanoid 0:777851395940 52 // DAC ResolutionBits = 12
whismanoid 0:777851395940 53 //
whismanoid 0:777851395940 54 // SPI CS = ActiveLow
whismanoid 0:777851395940 55 // SPI FrameStart = CS
whismanoid 0:777851395940 56 // SPI CPOL = 1
whismanoid 0:777851395940 57 // SPI CPHA = 0
whismanoid 0:777851395940 58 // SPI MOSI and MISO Data are both stable on Falling edge of SCLK
whismanoid 0:777851395940 59 // SPI SCLK Idle High
whismanoid 0:777851395940 60 // SPI SCLKMaxMHz = 50
whismanoid 0:777851395940 61 // SPI SCLKMinMHz = 0
whismanoid 0:777851395940 62 //
whismanoid 0:777851395940 63 // InputPin Name = LDAC#
whismanoid 0:777851395940 64 // InputPin Description = Dedicated Active-Low Asynchronous Load DAC.
whismanoid 0:777851395940 65 // InputPin Function = Trigger
whismanoid 0:777851395940 66 //
whismanoid 0:777851395940 67 // InputPin Name = CLR#
whismanoid 0:777851395940 68 // InputPin Description = Active-Low Clear Input.
whismanoid 0:777851395940 69 // InputPin Function = Trigger
whismanoid 0:777851395940 70 //
whismanoid 0:777851395940 71 // InputPin Name = REF
whismanoid 0:777851395940 72 // InputPin Description = Reference Voltage Input/Output.
whismanoid 0:777851395940 73 // Software selectable to be external reference or internal 2.048V, 2.500V, or 4.096V reference.
whismanoid 0:777851395940 74 // Default is external reference mode.
whismanoid 0:777851395940 75 // InputPin Function = Reference
whismanoid 0:777851395940 76 //
whismanoid 0:777851395940 77 // OutputPin Name = OUTA
whismanoid 0:777851395940 78 // OutputPin Description = Buffered Channel A DAC Output
whismanoid 0:777851395940 79 // OutputPin Function = Analog
whismanoid 0:777851395940 80 //
whismanoid 0:777851395940 81 // OutputPin Name = OUTB
whismanoid 0:777851395940 82 // OutputPin Description = Buffered Channel B DAC Output
whismanoid 0:777851395940 83 // OutputPin Function = Analog
whismanoid 0:777851395940 84 //
whismanoid 0:777851395940 85 // OutputPin Name = OUTC
whismanoid 0:777851395940 86 // OutputPin Description = Buffered Channel C DAC Output
whismanoid 0:777851395940 87 // OutputPin Function = Analog
whismanoid 0:777851395940 88 //
whismanoid 0:777851395940 89 // OutputPin Name = OUTD
whismanoid 0:777851395940 90 // OutputPin Description = Buffered Channel D DAC Output
whismanoid 0:777851395940 91 // OutputPin Function = Analog
whismanoid 0:777851395940 92 //
whismanoid 0:777851395940 93 // OutputPin Name = RDY#
whismanoid 0:777851395940 94 // OutputPin Description = SPI RDY Output. In daisy-chained applications connect RDY to the CSB of the next device in the chain.
whismanoid 0:777851395940 95 // OutputPin Function = DaisyChain
whismanoid 0:777851395940 96 //
whismanoid 0:777851395940 97 // SupplyPin Name = VDD
whismanoid 0:777851395940 98 // SupplyPin Description = Supply Voltage Input. Bypass VDD with a 0.1uF capacitor to GND.
whismanoid 0:777851395940 99 // SupplyPin VinMax = 5.5
whismanoid 0:777851395940 100 // SupplyPin VinMin = 2.7 (unless configured DAC VRefInternal = 4.096V, then VinMin = 4.5V)
whismanoid 0:777851395940 101 // SupplyPin Function = Analog
whismanoid 0:777851395940 102 //
whismanoid 0:777851395940 103 // SupplyPin Name = VDDIO
whismanoid 0:777851395940 104 // SupplyPin Description = Digital Interface Power-Supply Input
whismanoid 0:777851395940 105 // SupplyPin VinMax = 5.5
whismanoid 0:777851395940 106 // SupplyPin VinMin = 1.8
whismanoid 0:777851395940 107 // SupplyPin Function = Digital
whismanoid 0:777851395940 108 //
whismanoid 0:777851395940 109
whismanoid 0:777851395940 110 MAX5715::MAX5715(SPI &spi, DigitalOut &cs_pin, // SPI interface
whismanoid 0:777851395940 111 DigitalOut &LDACb_pin, // Digital Trigger Input to MAX5715 device
whismanoid 0:777851395940 112 DigitalOut &CLRb_pin, // Digital Trigger Input to MAX5715 device
whismanoid 0:777851395940 113 // AnalogOut &REF_pin, // Reference Input to MAX5715 device
whismanoid 0:777851395940 114 // AnalogIn &OUTA_pin, // Analog Output from MAX5715 device
whismanoid 0:777851395940 115 // AnalogIn &OUTB_pin, // Analog Output from MAX5715 device
whismanoid 0:777851395940 116 // AnalogIn &OUTC_pin, // Analog Output from MAX5715 device
whismanoid 0:777851395940 117 // AnalogIn &OUTD_pin, // Analog Output from MAX5715 device
whismanoid 0:777851395940 118 // DigitalIn &RDYb_pin, // Digital DaisyChain Output from MAX5715 device
whismanoid 0:777851395940 119 MAX5715_ic_t ic_variant)
whismanoid 0:777851395940 120 : m_spi(spi), m_cs_pin(cs_pin), // SPI interface
whismanoid 0:777851395940 121 m_LDACb_pin(LDACb_pin), // Digital Trigger Input to MAX5715 device
whismanoid 0:777851395940 122 m_CLRb_pin(CLRb_pin), // Digital Trigger Input to MAX5715 device
whismanoid 0:777851395940 123 // m_REF_pin(REF_pin), // Reference Input to MAX5715 device
whismanoid 0:777851395940 124 // m_OUTA_pin(OUTA_pin), // Analog Output from MAX5715 device
whismanoid 0:777851395940 125 // m_OUTB_pin(OUTB_pin), // Analog Output from MAX5715 device
whismanoid 0:777851395940 126 // m_OUTC_pin(OUTC_pin), // Analog Output from MAX5715 device
whismanoid 0:777851395940 127 // m_OUTD_pin(OUTD_pin), // Analog Output from MAX5715 device
whismanoid 0:777851395940 128 // m_RDYb_pin(RDYb_pin), // Digital DaisyChain Output from MAX5715 device
whismanoid 0:777851395940 129 m_ic_variant(ic_variant)
whismanoid 0:777851395940 130 {
whismanoid 0:777851395940 131 // SPI CS = ActiveLow
whismanoid 0:777851395940 132 // SPI FrameStart = CS
whismanoid 0:777851395940 133 m_SPI_cs_state = 1;
whismanoid 0:777851395940 134 m_cs_pin = m_SPI_cs_state;
whismanoid 0:777851395940 135
whismanoid 0:777851395940 136 // SPI CPOL = 1
whismanoid 0:777851395940 137 // SPI CPHA = 0
whismanoid 0:777851395940 138 // SPI MOSI and MISO Data are both stable on Falling edge of SCLK
whismanoid 0:777851395940 139 // SPI SCLK Idle High
whismanoid 0:777851395940 140 m_SPI_dataMode = 2; //SPI_MODE2; // CPOL=1,CPHA=0: Falling Edge stable; SCLK idle High
whismanoid 0:777851395940 141 m_spi.format(8,m_SPI_dataMode); // int bits_must_be_8, int mode=0_3 CPOL=0,CPHA=0
whismanoid 0:777851395940 142
whismanoid 0:777851395940 143 // SPI SCLKMaxMHz = 50
whismanoid 0:777851395940 144 // SPI SCLKMinMHz = 0
whismanoid 0:777851395940 145 //#define SPI_SCLK_Hz 48000000 // 48MHz
whismanoid 0:777851395940 146 //#define SPI_SCLK_Hz 24000000 // 24MHz
whismanoid 0:777851395940 147 //#define SPI_SCLK_Hz 12000000 // 12MHz
whismanoid 5:7894decf9375 148 //#define SPI_SCLK_Hz 6000000 // 6MHz
whismanoid 0:777851395940 149 //#define SPI_SCLK_Hz 4000000 // 4MHz
whismanoid 0:777851395940 150 //#define SPI_SCLK_Hz 2000000 // 2MHz
whismanoid 0:777851395940 151 //#define SPI_SCLK_Hz 1000000 // 1MHz
whismanoid 0:777851395940 152 m_SPI_SCLK_Hz = 12000000; // 12MHz; MAX5715 limit is 50MHz
whismanoid 0:777851395940 153 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 0:777851395940 154
whismanoid 5:7894decf9375 155 //
whismanoid 5:7894decf9375 156 // LDACb Trigger Input to MAX5715 device
whismanoid 5:7894decf9375 157 m_LDACb_pin = 1; // output logic high -- initial value in constructor
whismanoid 5:7894decf9375 158 //
whismanoid 5:7894decf9375 159 // CLRb Trigger Input to MAX5715 device
whismanoid 5:7894decf9375 160 m_CLRb_pin = 1; // output logic high -- initial value in constructor
whismanoid 5:7894decf9375 161 //
whismanoid 5:7894decf9375 162 // REF Reference Input to MAX5715 device
whismanoid 0:777851395940 163 //
whismanoid 5:7894decf9375 164 // OUTA Analog Output from device
whismanoid 5:7894decf9375 165 //
whismanoid 5:7894decf9375 166 // OUTB Analog Output from device
whismanoid 5:7894decf9375 167 //
whismanoid 5:7894decf9375 168 // OUTC Analog Output from device
whismanoid 5:7894decf9375 169 //
whismanoid 5:7894decf9375 170 // OUTD Analog Output from device
whismanoid 5:7894decf9375 171 //
whismanoid 5:7894decf9375 172 // RDYb DaisyChain Output from device
whismanoid 0:777851395940 173 }
whismanoid 0:777851395940 174
whismanoid 0:777851395940 175 MAX5715::~MAX5715()
whismanoid 0:777851395940 176 {
whismanoid 0:777851395940 177 // do nothing
whismanoid 0:777851395940 178 }
whismanoid 0:777851395940 179
whismanoid 5:7894decf9375 180 /// set SPI SCLK frequency
whismanoid 0:777851395940 181 void MAX5715::spi_frequency(int spi_sclk_Hz)
whismanoid 0:777851395940 182 {
whismanoid 0:777851395940 183 m_SPI_SCLK_Hz = spi_sclk_Hz;
whismanoid 0:777851395940 184 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 0:777851395940 185 }
whismanoid 0:777851395940 186
whismanoid 0:777851395940 187 // Assert SPI Chip Select
whismanoid 0:777851395940 188 // SPI chip-select for MAX5715
whismanoid 0:777851395940 189 //
whismanoid 0:777851395940 190 void MAX5715::SPIoutputCS(int isLogicHigh)
whismanoid 0:777851395940 191 {
whismanoid 0:777851395940 192 m_SPI_cs_state = isLogicHigh;
whismanoid 0:777851395940 193 m_cs_pin = m_SPI_cs_state;
whismanoid 0:777851395940 194 }
whismanoid 0:777851395940 195
whismanoid 0:777851395940 196 // SPI write 24 bits
whismanoid 0:777851395940 197 // SPI interface to MAX5715 shift 24 bits mosiData into MAX5715 DIN
whismanoid 0:777851395940 198 //
whismanoid 0:777851395940 199 void MAX5715::SPIwrite24bits(int8_t mosiData8_FF0000, int16_t mosiData16_00FFFF)
whismanoid 0:777851395940 200 {
whismanoid 0:777851395940 201 size_t byteCount = 3;
whismanoid 0:777851395940 202 static char mosiData[3];
whismanoid 0:777851395940 203 static char misoData[3];
whismanoid 0:777851395940 204 mosiData[0] = mosiData8_FF0000;
whismanoid 0:777851395940 205 mosiData[1] = (char)((mosiData16_00FFFF >> 8) & 0xFF); // MSByte
whismanoid 0:777851395940 206 mosiData[2] = (char)((mosiData16_00FFFF >> 0) & 0xFF); // LSByte
whismanoid 0:777851395940 207 //
whismanoid 0:777851395940 208 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 0:777851395940 209 //~ noInterrupts();
whismanoid 0:777851395940 210 //
whismanoid 0:777851395940 211 //~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid 0:777851395940 212 //
whismanoid 0:777851395940 213 unsigned int numBytesTransferred = m_spi.write(mosiData, byteCount, misoData, byteCount);
whismanoid 0:777851395940 214 //~ SPI.transfer(mosiData8_FF0000);
whismanoid 0:777851395940 215 //~ SPI.transfer(mosiData16_00FF00);
whismanoid 0:777851395940 216 //~ SPI.transfer(mosiData16_0000FF);
whismanoid 0:777851395940 217 //
whismanoid 0:777851395940 218 //~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid 0:777851395940 219 //
whismanoid 0:777851395940 220 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 0:777851395940 221 //~ interrupts();
whismanoid 5:7894decf9375 222 // Optional Diagnostic function to print SPI transactions
whismanoid 5:7894decf9375 223 if (onSPIprint)
whismanoid 5:7894decf9375 224 {
whismanoid 5:7894decf9375 225 onSPIprint(byteCount, (uint8_t*)mosiData, (uint8_t*)misoData);
whismanoid 5:7894decf9375 226 }
whismanoid 0:777851395940 227 //
whismanoid 0:777851395940 228 // VERIFY: SPIwrite24bits print diagnostic information
whismanoid 0:777851395940 229 //cmdLine.serial().printf(" MOSI->"));
whismanoid 0:777851395940 230 //cmdLine.serial().printf(" 0x"));
whismanoid 0:777851395940 231 //Serial.print( (mosiData8_FF0000 & 0xFF), HEX);
whismanoid 0:777851395940 232 //cmdLine.serial().printf(" 0x"));
whismanoid 0:777851395940 233 //Serial.print( (mosiData16_00FF00 & 0xFF), HEX);
whismanoid 0:777851395940 234 //cmdLine.serial().printf(" 0x"));
whismanoid 0:777851395940 235 //Serial.print( (mosiData16_0000FF & 0xFF), HEX);
whismanoid 0:777851395940 236 // hex dump mosiData[0..byteCount-1]
whismanoid 0:777851395940 237 #if HAS_MICROUSBSERIAL
whismanoid 0:777851395940 238 cmdLine_microUSBserial.serial().printf("\r\nSPI");
whismanoid 0:777851395940 239 if (byteCount > 7) {
whismanoid 0:777851395940 240 cmdLine_microUSBserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 0:777851395940 241 }
whismanoid 0:777851395940 242 cmdLine_microUSBserial.serial().printf(" MOSI->");
whismanoid 0:777851395940 243 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 0:777851395940 244 {
whismanoid 0:777851395940 245 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 0:777851395940 246 }
whismanoid 0:777851395940 247 // hex dump misoData[0..byteCount-1]
whismanoid 0:777851395940 248 cmdLine_microUSBserial.serial().printf(" MISO<-");
whismanoid 0:777851395940 249 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 0:777851395940 250 {
whismanoid 0:777851395940 251 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 0:777851395940 252 }
whismanoid 0:777851395940 253 cmdLine_microUSBserial.serial().printf(" ");
whismanoid 0:777851395940 254 #endif
whismanoid 0:777851395940 255 #if HAS_DAPLINK_SERIAL
whismanoid 0:777851395940 256 cmdLine_DAPLINKserial.serial().printf("\r\nSPI");
whismanoid 0:777851395940 257 if (byteCount > 7) {
whismanoid 0:777851395940 258 cmdLine_DAPLINKserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 0:777851395940 259 }
whismanoid 0:777851395940 260 cmdLine_DAPLINKserial.serial().printf(" MOSI->");
whismanoid 0:777851395940 261 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 0:777851395940 262 {
whismanoid 0:777851395940 263 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 0:777851395940 264 }
whismanoid 0:777851395940 265 // hex dump misoData[0..byteCount-1]
whismanoid 0:777851395940 266 cmdLine_DAPLINKserial.serial().printf(" MISO<-");
whismanoid 0:777851395940 267 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 0:777851395940 268 {
whismanoid 0:777851395940 269 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 0:777851395940 270 }
whismanoid 0:777851395940 271 cmdLine_DAPLINKserial.serial().printf(" ");
whismanoid 0:777851395940 272 #endif
whismanoid 0:777851395940 273 // VERIFY: DIAGNOSTIC: print MAX5715 device register write
whismanoid 0:777851395940 274 // TODO: MAX5715_print_register_verbose(mosiData8_FF0000, mosiData16_00FFFF);
whismanoid 0:777851395940 275 //
whismanoid 0:777851395940 276 // int misoData16 = (misoData16_FF00 << 8) | misoData16_00FF;
whismanoid 0:777851395940 277 // return misoData16;
whismanoid 0:777851395940 278 }
whismanoid 0:777851395940 279
whismanoid 0:777851395940 280 // Assert MAX5715 LDAC pin : High = inactive, Low = load DAC.
whismanoid 0:777851395940 281 //
whismanoid 0:777851395940 282 void MAX5715::LDACboutputValue(int isLogicHigh)
whismanoid 0:777851395940 283 {
whismanoid 0:777851395940 284 // m_LDACb_pin.output(); // only applicable to DigitalInOut
whismanoid 0:777851395940 285 m_LDACb_pin = isLogicHigh;
whismanoid 0:777851395940 286 }
whismanoid 0:777851395940 287
whismanoid 0:777851395940 288 // Assert MAX5715 CLR pin : High = inactive, Low = clear DAC.
whismanoid 0:777851395940 289 //
whismanoid 0:777851395940 290 void MAX5715::CLRboutputValue(int isLogicHigh)
whismanoid 0:777851395940 291 {
whismanoid 0:777851395940 292 // m_CLRb_pin.output(); // only applicable to DigitalInOut
whismanoid 0:777851395940 293 m_CLRb_pin = isLogicHigh;
whismanoid 0:777851395940 294 }
whismanoid 0:777851395940 295
whismanoid 0:777851395940 296 //----------------------------------------
whismanoid 5:7894decf9375 297 // Menu item '!'
whismanoid 0:777851395940 298 // Initialize device
whismanoid 0:777851395940 299 // @return 1 on success; 0 on failure
whismanoid 0:777851395940 300 uint8_t MAX5715::Init(void)
whismanoid 0:777851395940 301 {
whismanoid 0:777851395940 302
whismanoid 0:777851395940 303 //----------------------------------------
whismanoid 0:777851395940 304 // Initialize device
whismanoid 0:777851395940 305 //----------------------------------------
whismanoid 0:777851395940 306 // Perform Software Reset
whismanoid 0:777851395940 307 if (!SW_RESET()) {
whismanoid 0:777851395940 308 return 0; // failure
whismanoid 0:777851395940 309 }
whismanoid 0:777851395940 310 //----------------------------------------
whismanoid 0:777851395940 311 // Turn on the reference output pin
whismanoid 0:777851395940 312 REF(REF_AlwaysOn_2V500);
whismanoid 0:777851395940 313 //
whismanoid 0:777851395940 314 //~ Serial.println(F(" success"));
whismanoid 0:777851395940 315 //~ return;
whismanoid 0:777851395940 316 return 1; // success
whismanoid 0:777851395940 317 }
whismanoid 0:777851395940 318
whismanoid 0:777851395940 319 //----------------------------------------
whismanoid 0:777851395940 320 // Return the DAC register value corresponding to physical voltage.
whismanoid 0:777851395940 321 // Does not perform any offset or gain correction.
whismanoid 0:777851395940 322 //
whismanoid 0:777851395940 323 // @pre VRef = Voltage of REF input, in Volts
whismanoid 0:777851395940 324 // @param[in] voltage = physical voltage in Volts
whismanoid 0:777851395940 325 // @return raw 12-bit MAX5715 code (right justified).
whismanoid 0:777851395940 326 uint16_t MAX5715::DACCodeOfVoltage(double voltageV)
whismanoid 0:777851395940 327 {
whismanoid 0:777851395940 328
whismanoid 0:777851395940 329 //----------------------------------------
whismanoid 0:777851395940 330 // Linear map min and max endpoints
whismanoid 0:777851395940 331 const double MaxScaleVoltage = VRef; // voltage of maximum code 0x0fff
whismanoid 0:777851395940 332 const double MinScaleVoltage = 0.0; // voltage of minimum code 0x000
whismanoid 0:777851395940 333 const uint16_t FULL_SCALE_CODE_12BIT = 0x0fff;
whismanoid 0:777851395940 334 const uint16_t MaxCode = FULL_SCALE_CODE_12BIT;
whismanoid 0:777851395940 335 const uint16_t MinCode = 0x000;
whismanoid 0:777851395940 336 double codeFraction = (voltageV - MinScaleVoltage) / (MaxScaleVoltage - MinScaleVoltage);
whismanoid 0:777851395940 337 double dacRegValueIdeal = ((codeFraction * (double)(MaxCode - MinCode + 1)) + MinCode + 0.5);
whismanoid 0:777851395940 338 uint16_t dacRegValue = (uint16_t)dacRegValueIdeal;
whismanoid 0:777851395940 339 if (dacRegValueIdeal > MaxCode)
whismanoid 0:777851395940 340 {
whismanoid 0:777851395940 341 dacRegValue = MaxCode;
whismanoid 0:777851395940 342 } else if (dacRegValueIdeal < MinCode)
whismanoid 0:777851395940 343 {
whismanoid 0:777851395940 344 dacRegValue = MinCode;
whismanoid 0:777851395940 345 }
whismanoid 0:777851395940 346 return dacRegValue;
whismanoid 0:777851395940 347 }
whismanoid 0:777851395940 348
whismanoid 0:777851395940 349 //----------------------------------------
whismanoid 0:777851395940 350 // Return the physical voltage corresponding to DAC register.
whismanoid 0:777851395940 351 // Does not perform any offset or gain correction.
whismanoid 0:777851395940 352 //
whismanoid 0:777851395940 353 // @pre VRef = Voltage of REF input, in Volts
whismanoid 0:777851395940 354 // @param[in] value_u12: raw 12-bit MAX5715 code (right justified).
whismanoid 0:777851395940 355 // @return physical voltage corresponding to MAX5715 code.
whismanoid 0:777851395940 356 double MAX5715::VoltageOfCode(uint16_t value_u12)
whismanoid 0:777851395940 357 {
whismanoid 0:777851395940 358
whismanoid 0:777851395940 359 //----------------------------------------
whismanoid 0:777851395940 360 // Linear map min and max endpoints
whismanoid 0:777851395940 361 double MaxScaleVoltage = VRef; // voltage of maximum code 0x0fff
whismanoid 0:777851395940 362 double MinScaleVoltage = 0.0; // voltage of minimum code 0x000
whismanoid 0:777851395940 363 const uint16_t FULL_SCALE_CODE_12BIT = 0x0fff;
whismanoid 0:777851395940 364 const uint16_t MaxCode = FULL_SCALE_CODE_12BIT;
whismanoid 0:777851395940 365 const uint16_t MinCode = 0x000;
whismanoid 0:777851395940 366 double codeFraction = ((double)value_u12 - MinCode) / (MaxCode - MinCode + 1);
whismanoid 0:777851395940 367 return MinScaleVoltage + ((MaxScaleVoltage - MinScaleVoltage) * codeFraction);
whismanoid 0:777851395940 368 }
whismanoid 0:777851395940 369
whismanoid 0:777851395940 370 //----------------------------------------
whismanoid 0:777851395940 371 // CMD_1000_0000_dddd_dddd_dddd_0000_CODEall
whismanoid 0:777851395940 372 //
whismanoid 0:777851395940 373 // Writes data to all CODE registers
whismanoid 0:777851395940 374 // @post updates g_MAX5815_device.Shadow_0010_nnnn_CODE[0..3]
whismanoid 0:777851395940 375 // @post updates g_MAX5815_device.CODE[0..3]
whismanoid 0:777851395940 376 void MAX5715::CODEall(uint16_t dacCodeLsbs)
whismanoid 0:777851395940 377 {
whismanoid 0:777851395940 378
whismanoid 0:777851395940 379 //----------------------------------------
whismanoid 0:777851395940 380 // Define command code
whismanoid 0:777851395940 381 uint8_t command_regAddress = CMD_1000_0000_dddd_dddd_dddd_0000_CODEall;
whismanoid 0:777851395940 382 uint16_t regValue = (dacCodeLsbs << 4); // left-align dddd_dddd_dddd_0000
whismanoid 0:777851395940 383
whismanoid 0:777851395940 384 //----------------------------------------
whismanoid 0:777851395940 385 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 386 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 387 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 388 SPIoutputCS(0);
whismanoid 0:777851395940 389 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 390 SPIoutputCS(1);
whismanoid 0:777851395940 391
whismanoid 0:777851395940 392 //----------------------------------------
whismanoid 0:777851395940 393 // shadow of write-only register CODE 0010_nnnn[channel_0_3]
whismanoid 0:777851395940 394 // Each bit of channels_bitmask_DCBA maps to an index of g_MAX5815_device.Shadow_0010_nnnn_CODE[0..3]
whismanoid 0:777851395940 395 if (channels_bitmask_DCBA & (1 << 0)) {
whismanoid 0:777851395940 396 CODE[0] = dacCodeLsbs;
whismanoid 0:777851395940 397 Shadow_0010_nnnn_CODE[0] = regValue;
whismanoid 0:777851395940 398 }
whismanoid 0:777851395940 399 if (channels_bitmask_DCBA & (1 << 1)) {
whismanoid 0:777851395940 400 CODE[1] = dacCodeLsbs;
whismanoid 0:777851395940 401 Shadow_0010_nnnn_CODE[1] = regValue;
whismanoid 0:777851395940 402 }
whismanoid 0:777851395940 403 if (channels_bitmask_DCBA & (1 << 2)) {
whismanoid 0:777851395940 404 CODE[2] = dacCodeLsbs;
whismanoid 0:777851395940 405 Shadow_0010_nnnn_CODE[2] = regValue;
whismanoid 0:777851395940 406 }
whismanoid 0:777851395940 407 if (channels_bitmask_DCBA & (1 << 3)) {
whismanoid 0:777851395940 408 CODE[3] = dacCodeLsbs;
whismanoid 0:777851395940 409 Shadow_0010_nnnn_CODE[3] = regValue;
whismanoid 0:777851395940 410 }
whismanoid 0:777851395940 411 }
whismanoid 0:777851395940 412
whismanoid 0:777851395940 413 //----------------------------------------
whismanoid 0:777851395940 414 // CMD_0000_nnnn_dddd_dddd_dddd_0000_CODEn
whismanoid 0:777851395940 415 //
whismanoid 0:777851395940 416 // Writes data to the selected CODE register(s)
whismanoid 0:777851395940 417 //
whismanoid 0:777851395940 418 // @param[in] channel_0_3 = DAC Selection: 0=OUTA, 1=OUTB, 2=OUTC, 3=OUTD, 4..15=ALL OUTA,OUTB,OUTC,OUTD
whismanoid 0:777851395940 419 // @post updates g_MAX5815_device.Shadow_0010_nnnn_CODE[0..3]
whismanoid 0:777851395940 420 // @post updates g_MAX5815_device.CODE[0..3]
whismanoid 0:777851395940 421 void MAX5715::CODEn(uint8_t channel_0_3, uint16_t dacCodeLsbs)
whismanoid 0:777851395940 422 {
whismanoid 0:777851395940 423
whismanoid 0:777851395940 424 //----------------------------------------
whismanoid 0:777851395940 425 // update channel selection from channel_0_3
whismanoid 0:777851395940 426 channelNumber_0_3 = channel_0_3;
whismanoid 0:777851395940 427 switch (channelNumber_0_3) {
whismanoid 0:777851395940 428 case 0:
whismanoid 0:777851395940 429 channels_bitmask_DCBA = 0x01; // OUTA only
whismanoid 0:777851395940 430 break;
whismanoid 0:777851395940 431 case 1:
whismanoid 0:777851395940 432 channels_bitmask_DCBA = 0x02; // OUTB only
whismanoid 0:777851395940 433 break;
whismanoid 0:777851395940 434 case 2:
whismanoid 0:777851395940 435 channels_bitmask_DCBA = 0x04; // OUTC only
whismanoid 0:777851395940 436 break;
whismanoid 0:777851395940 437 case 3:
whismanoid 0:777851395940 438 channels_bitmask_DCBA = 0x08; // OUTD only
whismanoid 0:777851395940 439 break;
whismanoid 0:777851395940 440 default:
whismanoid 0:777851395940 441 channels_bitmask_DCBA = 0x0F; // ALL OUTA,OUTB,OUTC,OUTD
whismanoid 0:777851395940 442 }
whismanoid 0:777851395940 443
whismanoid 0:777851395940 444 //----------------------------------------
whismanoid 0:777851395940 445 // Define command code
whismanoid 0:777851395940 446 uint8_t command_regAddress = CMD_0000_nnnn_dddd_dddd_dddd_0000_CODEn | (channel_0_3 & 0x0F);
whismanoid 0:777851395940 447 uint16_t regValue = (dacCodeLsbs << 4); // left-align dddd_dddd_dddd_0000
whismanoid 0:777851395940 448
whismanoid 0:777851395940 449 //----------------------------------------
whismanoid 0:777851395940 450 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 451 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 452 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 453 SPIoutputCS(0);
whismanoid 0:777851395940 454 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 455 SPIoutputCS(1);
whismanoid 0:777851395940 456
whismanoid 0:777851395940 457 //----------------------------------------
whismanoid 0:777851395940 458 // shadow of write-only register CODE 0010_nnnn[channel_0_3]
whismanoid 0:777851395940 459 // Each bit of channels_bitmask_DCBA maps to an index of g_MAX5815_device.Shadow_0010_nnnn_CODE[0..3]
whismanoid 0:777851395940 460 if (channels_bitmask_DCBA & (1 << 0)) {
whismanoid 0:777851395940 461 CODE[0] = dacCodeLsbs;
whismanoid 0:777851395940 462 Shadow_0010_nnnn_CODE[0] = regValue;
whismanoid 0:777851395940 463 }
whismanoid 0:777851395940 464 if (channels_bitmask_DCBA & (1 << 1)) {
whismanoid 0:777851395940 465 CODE[1] = dacCodeLsbs;
whismanoid 0:777851395940 466 Shadow_0010_nnnn_CODE[1] = regValue;
whismanoid 0:777851395940 467 }
whismanoid 0:777851395940 468 if (channels_bitmask_DCBA & (1 << 2)) {
whismanoid 0:777851395940 469 CODE[2] = dacCodeLsbs;
whismanoid 0:777851395940 470 Shadow_0010_nnnn_CODE[2] = regValue;
whismanoid 0:777851395940 471 }
whismanoid 0:777851395940 472 if (channels_bitmask_DCBA & (1 << 3)) {
whismanoid 0:777851395940 473 CODE[3] = dacCodeLsbs;
whismanoid 0:777851395940 474 Shadow_0010_nnnn_CODE[3] = regValue;
whismanoid 0:777851395940 475 }
whismanoid 0:777851395940 476 }
whismanoid 0:777851395940 477
whismanoid 0:777851395940 478 //----------------------------------------
whismanoid 0:777851395940 479 // CMD_1000_0010_dddd_dddd_dddd_0000_CODEallLOADall
whismanoid 0:777851395940 480 //
whismanoid 0:777851395940 481 // Simultaneously writes data to all CODE registers while updating all DAC registers
whismanoid 0:777851395940 482 // @post updates g_MAX5815_device.Shadow_0010_nnnn_CODE[0..3]
whismanoid 0:777851395940 483 // @post updates g_MAX5815_device.CODE[0..3]
whismanoid 0:777851395940 484 void MAX5715::CODEallLOADall(uint16_t dacCodeLsbs)
whismanoid 0:777851395940 485 {
whismanoid 0:777851395940 486
whismanoid 0:777851395940 487 //----------------------------------------
whismanoid 0:777851395940 488 // Define command code
whismanoid 0:777851395940 489 uint8_t command_regAddress = CMD_1000_0010_dddd_dddd_dddd_0000_CODEallLOADall;
whismanoid 0:777851395940 490 uint16_t regValue = (dacCodeLsbs << 4); // left-align dddd_dddd_dddd_0000
whismanoid 0:777851395940 491
whismanoid 0:777851395940 492 //----------------------------------------
whismanoid 0:777851395940 493 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 494 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 495 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 496 SPIoutputCS(0);
whismanoid 0:777851395940 497 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 498 SPIoutputCS(1);
whismanoid 0:777851395940 499
whismanoid 0:777851395940 500 //----------------------------------------
whismanoid 0:777851395940 501 // shadow of write-only register CODE 0010_nnnn[channel_0_3]
whismanoid 0:777851395940 502 // Each bit of channels_bitmask_DCBA maps to an index of g_MAX5815_device.Shadow_0010_nnnn_CODE[0..3]
whismanoid 0:777851395940 503 CODE[0] = dacCodeLsbs;
whismanoid 0:777851395940 504 Shadow_0010_nnnn_CODE[0] = regValue;
whismanoid 0:777851395940 505 CODE[1] = dacCodeLsbs;
whismanoid 0:777851395940 506 Shadow_0010_nnnn_CODE[1] = regValue;
whismanoid 0:777851395940 507 CODE[2] = dacCodeLsbs;
whismanoid 0:777851395940 508 Shadow_0010_nnnn_CODE[2] = regValue;
whismanoid 0:777851395940 509 CODE[3] = dacCodeLsbs;
whismanoid 0:777851395940 510 Shadow_0010_nnnn_CODE[3] = regValue;
whismanoid 0:777851395940 511 }
whismanoid 0:777851395940 512
whismanoid 0:777851395940 513 //----------------------------------------
whismanoid 0:777851395940 514 // CMD_0010_nnnn_dddd_dddd_dddd_0000_CODEnLOADall
whismanoid 0:777851395940 515 //
whismanoid 0:777851395940 516 // Simultaneously writes data to the selected CODE register(s) while updating all DAC registers.
whismanoid 0:777851395940 517 //
whismanoid 0:777851395940 518 // @param[in] channel_0_3 = DAC Selection: 0=OUTA, 1=OUTB, 2=OUTC, 3=OUTD, 4..15=ALL OUTA,OUTB,OUTC,OUTD
whismanoid 0:777851395940 519 // @post updates g_MAX5815_device.Shadow_0010_nnnn_CODE[0..3]
whismanoid 0:777851395940 520 // @post updates g_MAX5815_device.CODE[0..3]
whismanoid 0:777851395940 521 void MAX5715::CODEnLOADall(uint8_t channel_0_3, uint16_t dacCodeLsbs)
whismanoid 0:777851395940 522 {
whismanoid 0:777851395940 523
whismanoid 0:777851395940 524 //----------------------------------------
whismanoid 0:777851395940 525 // update channel selection from channel_0_3
whismanoid 0:777851395940 526 channelNumber_0_3 = channel_0_3;
whismanoid 0:777851395940 527 switch (channelNumber_0_3) {
whismanoid 0:777851395940 528 case 0:
whismanoid 0:777851395940 529 channels_bitmask_DCBA = 0x01; // OUTA only
whismanoid 0:777851395940 530 break;
whismanoid 0:777851395940 531 case 1:
whismanoid 0:777851395940 532 channels_bitmask_DCBA = 0x02; // OUTB only
whismanoid 0:777851395940 533 break;
whismanoid 0:777851395940 534 case 2:
whismanoid 0:777851395940 535 channels_bitmask_DCBA = 0x04; // OUTC only
whismanoid 0:777851395940 536 break;
whismanoid 0:777851395940 537 case 3:
whismanoid 0:777851395940 538 channels_bitmask_DCBA = 0x08; // OUTD only
whismanoid 0:777851395940 539 break;
whismanoid 0:777851395940 540 default:
whismanoid 0:777851395940 541 channels_bitmask_DCBA = 0x0F; // ALL OUTA,OUTB,OUTC,OUTD
whismanoid 0:777851395940 542 }
whismanoid 0:777851395940 543
whismanoid 0:777851395940 544 //----------------------------------------
whismanoid 0:777851395940 545 // Define command code
whismanoid 0:777851395940 546 uint8_t command_regAddress = CMD_0010_nnnn_dddd_dddd_dddd_0000_CODEnLOADall | (channel_0_3 & 0x0F);
whismanoid 0:777851395940 547 uint16_t regValue = (dacCodeLsbs << 4); // left-align dddd_dddd_dddd_0000
whismanoid 0:777851395940 548
whismanoid 0:777851395940 549 //----------------------------------------
whismanoid 0:777851395940 550 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 551 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 552 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 553 SPIoutputCS(0);
whismanoid 0:777851395940 554 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 555 SPIoutputCS(1);
whismanoid 0:777851395940 556
whismanoid 0:777851395940 557 //----------------------------------------
whismanoid 0:777851395940 558 // shadow of write-only register CODE 0010_nnnn[channel_0_3]
whismanoid 0:777851395940 559 // Each bit of channels_bitmask_DCBA maps to an index of g_MAX5815_device.Shadow_0010_nnnn_CODE[0..3]
whismanoid 0:777851395940 560 if (channels_bitmask_DCBA & (1 << 0)) {
whismanoid 0:777851395940 561 CODE[0] = dacCodeLsbs;
whismanoid 0:777851395940 562 Shadow_0010_nnnn_CODE[0] = regValue;
whismanoid 0:777851395940 563 }
whismanoid 0:777851395940 564 if (channels_bitmask_DCBA & (1 << 1)) {
whismanoid 0:777851395940 565 CODE[1] = dacCodeLsbs;
whismanoid 0:777851395940 566 Shadow_0010_nnnn_CODE[1] = regValue;
whismanoid 0:777851395940 567 }
whismanoid 0:777851395940 568 if (channels_bitmask_DCBA & (1 << 2)) {
whismanoid 0:777851395940 569 CODE[2] = dacCodeLsbs;
whismanoid 0:777851395940 570 Shadow_0010_nnnn_CODE[2] = regValue;
whismanoid 0:777851395940 571 }
whismanoid 0:777851395940 572 if (channels_bitmask_DCBA & (1 << 3)) {
whismanoid 0:777851395940 573 CODE[3] = dacCodeLsbs;
whismanoid 0:777851395940 574 Shadow_0010_nnnn_CODE[3] = regValue;
whismanoid 0:777851395940 575 }
whismanoid 0:777851395940 576 }
whismanoid 0:777851395940 577
whismanoid 0:777851395940 578 //----------------------------------------
whismanoid 0:777851395940 579 // CMD_0011_nnnn_dddd_dddd_dddd_0000_CODEnLOADn
whismanoid 0:777851395940 580 //
whismanoid 0:777851395940 581 // Simultaneously writes data to the selected CODE register(s) while updating selected DAC register(s)
whismanoid 0:777851395940 582 //
whismanoid 0:777851395940 583 // @param[in] channel_0_3 = DAC Selection: 0=OUTA, 1=OUTB, 2=OUTC, 3=OUTD, 4..15=ALL OUTA,OUTB,OUTC,OUTD
whismanoid 0:777851395940 584 // @post updates g_MAX5815_device.Shadow_0010_nnnn_CODE[0..3]
whismanoid 0:777851395940 585 // @post updates g_MAX5815_device.CODE[0..3]
whismanoid 0:777851395940 586 void MAX5715::CODEnLOADn(uint8_t channel_0_3, uint16_t dacCodeLsbs)
whismanoid 0:777851395940 587 {
whismanoid 0:777851395940 588
whismanoid 0:777851395940 589 //----------------------------------------
whismanoid 0:777851395940 590 // update channel selection from channel_0_3
whismanoid 0:777851395940 591 channelNumber_0_3 = channel_0_3;
whismanoid 0:777851395940 592 switch (channelNumber_0_3) {
whismanoid 0:777851395940 593 case 0:
whismanoid 0:777851395940 594 channels_bitmask_DCBA = 0x01; // OUTA only
whismanoid 0:777851395940 595 break;
whismanoid 0:777851395940 596 case 1:
whismanoid 0:777851395940 597 channels_bitmask_DCBA = 0x02; // OUTB only
whismanoid 0:777851395940 598 break;
whismanoid 0:777851395940 599 case 2:
whismanoid 0:777851395940 600 channels_bitmask_DCBA = 0x04; // OUTC only
whismanoid 0:777851395940 601 break;
whismanoid 0:777851395940 602 case 3:
whismanoid 0:777851395940 603 channels_bitmask_DCBA = 0x08; // OUTD only
whismanoid 0:777851395940 604 break;
whismanoid 0:777851395940 605 default:
whismanoid 0:777851395940 606 channels_bitmask_DCBA = 0x0F; // ALL OUTA,OUTB,OUTC,OUTD
whismanoid 0:777851395940 607 }
whismanoid 0:777851395940 608
whismanoid 0:777851395940 609 //----------------------------------------
whismanoid 0:777851395940 610 // Define command code
whismanoid 0:777851395940 611 uint8_t command_regAddress = CMD_0011_nnnn_dddd_dddd_dddd_0000_CODEnLOADn | (channel_0_3 & 0x0F);
whismanoid 0:777851395940 612 uint16_t regValue = (dacCodeLsbs << 4); // left-align dddd_dddd_dddd_0000
whismanoid 0:777851395940 613
whismanoid 0:777851395940 614 //----------------------------------------
whismanoid 0:777851395940 615 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 616 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 617 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 618 SPIoutputCS(0);
whismanoid 0:777851395940 619 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 620 SPIoutputCS(1);
whismanoid 0:777851395940 621
whismanoid 0:777851395940 622 //----------------------------------------
whismanoid 0:777851395940 623 // shadow of write-only register CODE 0010_nnnn[channel_0_3]
whismanoid 0:777851395940 624 // Each bit of channels_bitmask_DCBA maps to an index of g_MAX5815_device.Shadow_0010_nnnn_CODE[0..3]
whismanoid 0:777851395940 625 if (channels_bitmask_DCBA & (1 << 0)) {
whismanoid 0:777851395940 626 CODE[0] = dacCodeLsbs;
whismanoid 0:777851395940 627 Shadow_0010_nnnn_CODE[0] = regValue;
whismanoid 0:777851395940 628 }
whismanoid 0:777851395940 629 if (channels_bitmask_DCBA & (1 << 1)) {
whismanoid 0:777851395940 630 CODE[1] = dacCodeLsbs;
whismanoid 0:777851395940 631 Shadow_0010_nnnn_CODE[1] = regValue;
whismanoid 0:777851395940 632 }
whismanoid 0:777851395940 633 if (channels_bitmask_DCBA & (1 << 2)) {
whismanoid 0:777851395940 634 CODE[2] = dacCodeLsbs;
whismanoid 0:777851395940 635 Shadow_0010_nnnn_CODE[2] = regValue;
whismanoid 0:777851395940 636 }
whismanoid 0:777851395940 637 if (channels_bitmask_DCBA & (1 << 3)) {
whismanoid 0:777851395940 638 CODE[3] = dacCodeLsbs;
whismanoid 0:777851395940 639 Shadow_0010_nnnn_CODE[3] = regValue;
whismanoid 0:777851395940 640 }
whismanoid 0:777851395940 641 }
whismanoid 0:777851395940 642
whismanoid 0:777851395940 643 //----------------------------------------
whismanoid 0:777851395940 644 // CMD_0110_0000_0000_dcba_0000_0000_CONFIGn_LATCHED
whismanoid 0:777851395940 645 //
whismanoid 0:777851395940 646 // Sets the DAC Latch Mode of the selected DACs.
whismanoid 0:777851395940 647 // Only DACS with a 1 in the selection bit are updated by the command.
whismanoid 0:777851395940 648 // LD_EN = 0: DAC latch is operational (LOAD and LDAC controlled)
whismanoid 0:777851395940 649 //
whismanoid 0:777851395940 650 // @param[in] channels_bitmask_DCBA = channel select bitmap
whismanoid 0:777851395940 651 // bit 1000 = channel D
whismanoid 0:777851395940 652 // bit 0100 = channel C
whismanoid 0:777851395940 653 // bit 0010 = channel B
whismanoid 0:777851395940 654 // bit 0001 = channel A
whismanoid 0:777851395940 655 void MAX5715::CONFIGn_LATCHED(uint8_t channels_bitmask_DCBA)
whismanoid 0:777851395940 656 {
whismanoid 0:777851395940 657
whismanoid 0:777851395940 658 //----------------------------------------
whismanoid 0:777851395940 659 // update channel selection from channels_bitmask_DCBA
whismanoid 0:777851395940 660 channels_bitmask_DCBA = channels_bitmask_DCBA;
whismanoid 0:777851395940 661 if (channels_bitmask_DCBA == 0x0F) {
whismanoid 0:777851395940 662 channelNumber_0_3 = 0x0F; // ALL OUTA,OUTB,OUTC,OUTD
whismanoid 0:777851395940 663 }
whismanoid 0:777851395940 664 else if ((channels_bitmask_DCBA & 0x01) != 0) {
whismanoid 0:777851395940 665 channelNumber_0_3 = 0x00; // OUTA only
whismanoid 0:777851395940 666 }
whismanoid 0:777851395940 667 else if ((channels_bitmask_DCBA & 0x02) != 0) {
whismanoid 0:777851395940 668 channelNumber_0_3 = 0x01; // OUTB only
whismanoid 0:777851395940 669 }
whismanoid 0:777851395940 670 else if ((channels_bitmask_DCBA & 0x04) != 0) {
whismanoid 0:777851395940 671 channelNumber_0_3 = 0x02; // OUTC only
whismanoid 0:777851395940 672 }
whismanoid 0:777851395940 673 else {
whismanoid 0:777851395940 674 channelNumber_0_3 = 0x03; // OUTD only
whismanoid 0:777851395940 675 }
whismanoid 0:777851395940 676
whismanoid 0:777851395940 677 //----------------------------------------
whismanoid 0:777851395940 678 // Define command code
whismanoid 0:777851395940 679 uint8_t command_regAddress = CMD_0110_0000_0000_dcba_0000_0000_CONFIGn_LATCHED;
whismanoid 0:777851395940 680 uint16_t regValue = ((channels_bitmask_DCBA & 0x0F) << 8); // align field 0000_dcba_0000_0000
whismanoid 0:777851395940 681
whismanoid 0:777851395940 682 //----------------------------------------
whismanoid 0:777851395940 683 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 684 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 685 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 686 SPIoutputCS(0);
whismanoid 0:777851395940 687 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 688 SPIoutputCS(1);
whismanoid 0:777851395940 689 }
whismanoid 0:777851395940 690
whismanoid 0:777851395940 691 //----------------------------------------
whismanoid 0:777851395940 692 // CMD_0110_0001_0000_dcba_0000_0000_CONFIGn_TRANSPARENT
whismanoid 0:777851395940 693 //
whismanoid 0:777851395940 694 // Sets the DAC Latch Mode of the selected DACs.
whismanoid 0:777851395940 695 // Only DACS with a 1 in the selection bit are updated by the command.
whismanoid 0:777851395940 696 // LD_EN = 1: DAC latch is transparent
whismanoid 0:777851395940 697 //
whismanoid 0:777851395940 698 // @param[in] channels_bitmask_DCBA = channel select bitmap
whismanoid 0:777851395940 699 // bit 1000 = channel D
whismanoid 0:777851395940 700 // bit 0100 = channel C
whismanoid 0:777851395940 701 // bit 0010 = channel B
whismanoid 0:777851395940 702 // bit 0001 = channel A
whismanoid 0:777851395940 703 void MAX5715::CONFIGn_TRANSPARENT(uint8_t channels_bitmask_DCBA)
whismanoid 0:777851395940 704 {
whismanoid 0:777851395940 705
whismanoid 0:777851395940 706 //----------------------------------------
whismanoid 0:777851395940 707 // update channel selection from channels_bitmask_DCBA
whismanoid 0:777851395940 708 channels_bitmask_DCBA = channels_bitmask_DCBA;
whismanoid 0:777851395940 709 if (channels_bitmask_DCBA == 0x0F) {
whismanoid 0:777851395940 710 channelNumber_0_3 = 0x0F; // ALL OUTA,OUTB,OUTC,OUTD
whismanoid 0:777851395940 711 }
whismanoid 0:777851395940 712 else if ((channels_bitmask_DCBA & 0x01) != 0) {
whismanoid 0:777851395940 713 channelNumber_0_3 = 0x00; // OUTA only
whismanoid 0:777851395940 714 }
whismanoid 0:777851395940 715 else if ((channels_bitmask_DCBA & 0x02) != 0) {
whismanoid 0:777851395940 716 channelNumber_0_3 = 0x01; // OUTB only
whismanoid 0:777851395940 717 }
whismanoid 0:777851395940 718 else if ((channels_bitmask_DCBA & 0x04) != 0) {
whismanoid 0:777851395940 719 channelNumber_0_3 = 0x02; // OUTC only
whismanoid 0:777851395940 720 }
whismanoid 0:777851395940 721 else {
whismanoid 0:777851395940 722 channelNumber_0_3 = 0x03; // OUTD only
whismanoid 0:777851395940 723 }
whismanoid 0:777851395940 724
whismanoid 0:777851395940 725 //----------------------------------------
whismanoid 0:777851395940 726 // Define command code
whismanoid 0:777851395940 727 uint8_t command_regAddress = CMD_0110_0001_0000_dcba_0000_0000_CONFIGn_TRANSPARENT;
whismanoid 0:777851395940 728 uint16_t regValue = ((channels_bitmask_DCBA & 0x0F) << 8); // align field 0000_dcba_0000_0000
whismanoid 0:777851395940 729
whismanoid 0:777851395940 730 //----------------------------------------
whismanoid 0:777851395940 731 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 732 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 733 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 734 SPIoutputCS(0);
whismanoid 0:777851395940 735 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 736 SPIoutputCS(1);
whismanoid 0:777851395940 737 }
whismanoid 0:777851395940 738
whismanoid 0:777851395940 739 //----------------------------------------
whismanoid 0:777851395940 740 // CMD_0110_1000_0000_0000_0000_0000_CONFIGall_LATCHED
whismanoid 0:777851395940 741 //
whismanoid 0:777851395940 742 // Sets the DAC Latch Mode of all DACs.
whismanoid 0:777851395940 743 // LD_EN = 0: DAC latch is operational (LOAD and LDAC controlled)
whismanoid 0:777851395940 744 void MAX5715::CONFIGall_LATCHED(void)
whismanoid 0:777851395940 745 {
whismanoid 0:777851395940 746
whismanoid 0:777851395940 747 //----------------------------------------
whismanoid 0:777851395940 748 // Define command code
whismanoid 0:777851395940 749 uint8_t command_regAddress = CMD_0110_1000_0000_0000_0000_0000_CONFIGall_LATCHED;
whismanoid 0:777851395940 750 uint16_t regValue = 0; // 0000_0000_0000_0000
whismanoid 0:777851395940 751
whismanoid 0:777851395940 752 //----------------------------------------
whismanoid 0:777851395940 753 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 754 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 755 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 756 SPIoutputCS(0);
whismanoid 0:777851395940 757 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 758 SPIoutputCS(1);
whismanoid 0:777851395940 759 }
whismanoid 0:777851395940 760
whismanoid 0:777851395940 761 //----------------------------------------
whismanoid 0:777851395940 762 // CMD_0110_1001_0000_0000_0000_0000_CONFIGall_TRANSPARENT
whismanoid 0:777851395940 763 //
whismanoid 0:777851395940 764 // Sets the DAC Latch Mode of all DACs.
whismanoid 0:777851395940 765 // LD_EN = 1: DAC latch is transparent
whismanoid 0:777851395940 766 void MAX5715::CONFIGall_TRANSPARENT(void)
whismanoid 0:777851395940 767 {
whismanoid 0:777851395940 768
whismanoid 0:777851395940 769 //----------------------------------------
whismanoid 0:777851395940 770 // Define command code
whismanoid 0:777851395940 771 uint8_t command_regAddress = CMD_0110_1001_0000_0000_0000_0000_CONFIGall_TRANSPARENT;
whismanoid 0:777851395940 772 uint16_t regValue = 0; // 0000_0000_0000_0000
whismanoid 0:777851395940 773
whismanoid 0:777851395940 774 //----------------------------------------
whismanoid 0:777851395940 775 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 776 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 777 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 778 SPIoutputCS(0);
whismanoid 0:777851395940 779 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 780 SPIoutputCS(1);
whismanoid 0:777851395940 781 }
whismanoid 0:777851395940 782
whismanoid 0:777851395940 783 //----------------------------------------
whismanoid 0:777851395940 784 // CMD_1000_0001_0000_0000_0000_0000_LOADall
whismanoid 0:777851395940 785 //
whismanoid 0:777851395940 786 // Updates all DAC latches with current CODE register data
whismanoid 0:777851395940 787 void MAX5715::LOADall(void)
whismanoid 0:777851395940 788 {
whismanoid 0:777851395940 789
whismanoid 0:777851395940 790 //----------------------------------------
whismanoid 0:777851395940 791 // Define command code
whismanoid 0:777851395940 792 uint8_t command_regAddress = CMD_1000_0001_0000_0000_0000_0000_LOADall;
whismanoid 0:777851395940 793 uint16_t regValue = 0; // 0000_0000_0000_0000
whismanoid 0:777851395940 794
whismanoid 0:777851395940 795 //----------------------------------------
whismanoid 0:777851395940 796 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 797 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 798 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 799 SPIoutputCS(0);
whismanoid 0:777851395940 800 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 801 SPIoutputCS(1);
whismanoid 0:777851395940 802 }
whismanoid 0:777851395940 803
whismanoid 0:777851395940 804 //----------------------------------------
whismanoid 0:777851395940 805 // CMD_0001_nnnn_0000_0000_0000_0000_LOADn
whismanoid 0:777851395940 806 //
whismanoid 0:777851395940 807 // Transfers data from the selected CODE register(s) to the selected DAC register(s).
whismanoid 0:777851395940 808 //
whismanoid 0:777851395940 809 // @param[in] channel_0_3 = DAC Selection: 0=OUTA, 1=OUTB, 2=OUTC, 3=OUTD, 4..15=ALL OUTA,OUTB,OUTC,OUTD
whismanoid 0:777851395940 810 void MAX5715::LOADn(uint8_t channel_0_3)
whismanoid 0:777851395940 811 {
whismanoid 0:777851395940 812
whismanoid 0:777851395940 813 //----------------------------------------
whismanoid 0:777851395940 814 // update channel selection from channel_0_3
whismanoid 0:777851395940 815 channelNumber_0_3 = channel_0_3;
whismanoid 0:777851395940 816 switch (channelNumber_0_3) {
whismanoid 0:777851395940 817 case 0:
whismanoid 0:777851395940 818 channels_bitmask_DCBA = 0x01; // OUTA only
whismanoid 0:777851395940 819 break;
whismanoid 0:777851395940 820 case 1:
whismanoid 0:777851395940 821 channels_bitmask_DCBA = 0x02; // OUTB only
whismanoid 0:777851395940 822 break;
whismanoid 0:777851395940 823 case 2:
whismanoid 0:777851395940 824 channels_bitmask_DCBA = 0x04; // OUTC only
whismanoid 0:777851395940 825 break;
whismanoid 0:777851395940 826 case 3:
whismanoid 0:777851395940 827 channels_bitmask_DCBA = 0x08; // OUTD only
whismanoid 0:777851395940 828 break;
whismanoid 0:777851395940 829 default:
whismanoid 0:777851395940 830 channels_bitmask_DCBA = 0x0F; // ALL OUTA,OUTB,OUTC,OUTD
whismanoid 0:777851395940 831 }
whismanoid 0:777851395940 832
whismanoid 0:777851395940 833 //----------------------------------------
whismanoid 0:777851395940 834 // Define command code
whismanoid 0:777851395940 835 uint8_t command_regAddress = CMD_0001_nnnn_0000_0000_0000_0000_LOADn | (channel_0_3 & 0x0F);
whismanoid 0:777851395940 836 uint16_t regValue = (0 << 4); // left-align dddd_dddd_dddd_0000
whismanoid 0:777851395940 837
whismanoid 0:777851395940 838 //----------------------------------------
whismanoid 0:777851395940 839 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 840 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 841 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 842 SPIoutputCS(0);
whismanoid 0:777851395940 843 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 844 SPIoutputCS(1);
whismanoid 0:777851395940 845 }
whismanoid 0:777851395940 846
whismanoid 0:777851395940 847 //----------------------------------------
whismanoid 0:777851395940 848 // CMD_0100_0000_0000_dcba_0000_0000_POWERn_Normal
whismanoid 5:7894decf9375 849 // CMD_0100_0001_0000_dcba_0000_0000_POWERn_PD1k
whismanoid 5:7894decf9375 850 // CMD_0100_0010_0000_dcba_0000_0000_POWERn_PD100k
whismanoid 5:7894decf9375 851 // CMD_0100_0011_0000_dcba_0000_0000_POWERn_PDHiZ
whismanoid 0:777851395940 852 //
whismanoid 0:777851395940 853 // Sets the power mode of the selected DACs
whismanoid 0:777851395940 854 // (DACs selected with a 1 in the corresponding DACn bit are updated,
whismanoid 0:777851395940 855 // DACs with a 0 in the corresponding DACn bit are not impacted)
whismanoid 0:777851395940 856 //
whismanoid 0:777851395940 857 // @param[in] channels_bitmask_DCBA = channel select bitmap
whismanoid 0:777851395940 858 // bit 1000 = channel D
whismanoid 0:777851395940 859 // bit 0100 = channel C
whismanoid 0:777851395940 860 // bit 0010 = channel B
whismanoid 0:777851395940 861 // bit 0001 = channel A
whismanoid 0:777851395940 862 // @param[in] powerValue = power configuration for selected channel
whismanoid 0:777851395940 863 void MAX5715::POWER(uint8_t channels_bitmask_DCBA, MAX5715_POWER_enum_t powerValue)
whismanoid 0:777851395940 864 {
whismanoid 0:777851395940 865
whismanoid 0:777851395940 866 //----------------------------------------
whismanoid 0:777851395940 867 // update channel selection from channels_bitmask_DCBA
whismanoid 0:777851395940 868 channels_bitmask_DCBA = channels_bitmask_DCBA;
whismanoid 0:777851395940 869 if (channels_bitmask_DCBA == 0x0F) {
whismanoid 0:777851395940 870 channelNumber_0_3 = 0x0F; // ALL OUTA,OUTB,OUTC,OUTD
whismanoid 0:777851395940 871 }
whismanoid 0:777851395940 872 else if ((channels_bitmask_DCBA & 0x01) != 0) {
whismanoid 0:777851395940 873 channelNumber_0_3 = 0x00; // OUTA only
whismanoid 0:777851395940 874 }
whismanoid 0:777851395940 875 else if ((channels_bitmask_DCBA & 0x02) != 0) {
whismanoid 0:777851395940 876 channelNumber_0_3 = 0x01; // OUTB only
whismanoid 0:777851395940 877 }
whismanoid 0:777851395940 878 else if ((channels_bitmask_DCBA & 0x04) != 0) {
whismanoid 0:777851395940 879 channelNumber_0_3 = 0x02; // OUTC only
whismanoid 0:777851395940 880 }
whismanoid 0:777851395940 881 else {
whismanoid 0:777851395940 882 channelNumber_0_3 = 0x03; // OUTD only
whismanoid 0:777851395940 883 }
whismanoid 0:777851395940 884
whismanoid 0:777851395940 885 //----------------------------------------
whismanoid 0:777851395940 886 // select command_regAddress based on condition
whismanoid 0:777851395940 887 uint8_t command_regAddress = CMD_0100_0000_0000_dcba_0000_0000_POWERn_Normal; // diagnostic
whismanoid 0:777851395940 888 uint16_t regValue = ((channels_bitmask_DCBA & 0x0F) << 8); // 0000_dcba_0000_0000
whismanoid 0:777851395940 889 // select command_regAddress from list of 4 values, based on condition
whismanoid 3:a3f0518094f4 890 if (powerValue == POWERn_Normal) {
whismanoid 3:a3f0518094f4 891 command_regAddress = CMD_0100_0000_0000_dcba_0000_0000_POWERn_Normal;
whismanoid 0:777851395940 892 }
whismanoid 0:777851395940 893 if (powerValue == POWERn_PD1k) {
whismanoid 0:777851395940 894 command_regAddress = CMD_0100_0001_0000_dcba_0000_0000_POWERn_PD1k;
whismanoid 0:777851395940 895 }
whismanoid 3:a3f0518094f4 896 if (powerValue == POWERn_PD100k) {
whismanoid 3:a3f0518094f4 897 command_regAddress = CMD_0100_0010_0000_dcba_0000_0000_POWERn_PD100k;
whismanoid 0:777851395940 898 }
whismanoid 0:777851395940 899 if (powerValue == POWERn_PDHiZ) {
whismanoid 0:777851395940 900 command_regAddress = CMD_0100_0011_0000_dcba_0000_0000_POWERn_PDHiZ;
whismanoid 0:777851395940 901 }
whismanoid 0:777851395940 902
whismanoid 0:777851395940 903 //----------------------------------------
whismanoid 0:777851395940 904 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 905 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 906 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 907 SPIoutputCS(0);
whismanoid 0:777851395940 908 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 909 SPIoutputCS(1);
whismanoid 0:777851395940 910 }
whismanoid 0:777851395940 911
whismanoid 0:777851395940 912 //----------------------------------------
whismanoid 0:777851395940 913 // CMD_0111_0000_0000_0000_0000_0000_REF_EXT
whismanoid 0:777851395940 914 // CMD_0111_0001_0000_0000_0000_0000_REF_2V500
whismanoid 0:777851395940 915 // CMD_0111_0010_0000_0000_0000_0000_REF_2V048
whismanoid 0:777851395940 916 // CMD_0111_0011_0000_0000_0000_0000_REF_4V096
whismanoid 0:777851395940 917 // CMD_0111_0100_0000_0000_0000_0000_REF_AlwaysOn_EXT
whismanoid 0:777851395940 918 // CMD_0111_0101_0000_0000_0000_0000_REF_AlwaysOn_2V500
whismanoid 0:777851395940 919 // CMD_0111_0110_0000_0000_0000_0000_REF_AlwaysOn_2V048
whismanoid 0:777851395940 920 // CMD_0111_0111_0000_0000_0000_0000_REF_AlwaysOn_4V096
whismanoid 0:777851395940 921 //
whismanoid 0:777851395940 922 // Sets the reference operating mode.
whismanoid 0:777851395940 923 // REF Power (B18): 0 = Internal reference is only powered if at least one DAC is powered
whismanoid 0:777851395940 924 // 1 = Internal reference is always powered
whismanoid 5:7894decf9375 925 void MAX5715::REF(MAX5715_REF_enum_t ref)
whismanoid 0:777851395940 926 {
whismanoid 0:777851395940 927
whismanoid 0:777851395940 928 //----------------------------------------
whismanoid 0:777851395940 929 // select command_regAddress based on condition
whismanoid 0:777851395940 930 uint8_t command_regAddress = CMD_0111_0110_0000_0000_0000_0000_REF_AlwaysOn_2V048; // diagnostic
whismanoid 0:777851395940 931 uint16_t regValue = 0; // 0000_0000_0000_0000
whismanoid 0:777851395940 932 // select command_regAddress from list of 8 values, based on condition
whismanoid 5:7894decf9375 933 if (ref == REF_EXT) {
whismanoid 3:a3f0518094f4 934 command_regAddress = CMD_0111_0000_0000_0000_0000_0000_REF_EXT;
whismanoid 3:a3f0518094f4 935 }
whismanoid 5:7894decf9375 936 if (ref == REF_2V500) {
whismanoid 3:a3f0518094f4 937 command_regAddress = CMD_0111_0001_0000_0000_0000_0000_REF_2V500;
whismanoid 3:a3f0518094f4 938 VRef = 2.500;
whismanoid 3:a3f0518094f4 939 }
whismanoid 5:7894decf9375 940 if (ref == REF_2V048) {
whismanoid 3:a3f0518094f4 941 command_regAddress = CMD_0111_0010_0000_0000_0000_0000_REF_2V048;
whismanoid 3:a3f0518094f4 942 VRef = 2.048;
whismanoid 3:a3f0518094f4 943 }
whismanoid 5:7894decf9375 944 if (ref == REF_4V096) {
whismanoid 0:777851395940 945 command_regAddress = CMD_0111_0011_0000_0000_0000_0000_REF_4V096;
whismanoid 0:777851395940 946 VRef = 4.096;
whismanoid 0:777851395940 947 }
whismanoid 5:7894decf9375 948 if (ref == REF_AlwaysOn_EXT) {
whismanoid 0:777851395940 949 command_regAddress = CMD_0111_0100_0000_0000_0000_0000_REF_AlwaysOn_EXT;
whismanoid 0:777851395940 950 }
whismanoid 5:7894decf9375 951 if (ref == REF_AlwaysOn_2V500) {
whismanoid 3:a3f0518094f4 952 command_regAddress = CMD_0111_0101_0000_0000_0000_0000_REF_AlwaysOn_2V500;
whismanoid 0:777851395940 953 VRef = 2.500;
whismanoid 0:777851395940 954 }
whismanoid 5:7894decf9375 955 if (ref == REF_AlwaysOn_2V048) {
whismanoid 0:777851395940 956 command_regAddress = CMD_0111_0110_0000_0000_0000_0000_REF_AlwaysOn_2V048;
whismanoid 0:777851395940 957 VRef = 2.048;
whismanoid 0:777851395940 958 }
whismanoid 5:7894decf9375 959 if (ref == REF_AlwaysOn_4V096) {
whismanoid 0:777851395940 960 command_regAddress = CMD_0111_0111_0000_0000_0000_0000_REF_AlwaysOn_4V096;
whismanoid 0:777851395940 961 VRef = 4.096;
whismanoid 0:777851395940 962 }
whismanoid 0:777851395940 963
whismanoid 0:777851395940 964 //----------------------------------------
whismanoid 0:777851395940 965 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 966 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 967 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 968 SPIoutputCS(0);
whismanoid 0:777851395940 969 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 970 SPIoutputCS(1);
whismanoid 0:777851395940 971
whismanoid 0:777851395940 972 //----------------------------------------
whismanoid 0:777851395940 973 // shadow of write-only register REF CMD_0111_0rrr
whismanoid 0:777851395940 974 Shadow_0111_0rrr_REF = regValue;
whismanoid 0:777851395940 975 }
whismanoid 0:777851395940 976
whismanoid 0:777851395940 977 //----------------------------------------
whismanoid 0:777851395940 978 // CMD_0101_0000_0000_0000_0000_0000_SW_CLEAR
whismanoid 0:777851395940 979 //
whismanoid 0:777851395940 980 // Software Clear
whismanoid 0:777851395940 981 // All CODE and DAC registers cleared to their default values.
whismanoid 0:777851395940 982 //
whismanoid 0:777851395940 983 // @return 1 on success; 0 on failure
whismanoid 0:777851395940 984 uint8_t MAX5715::SW_CLEAR(void)
whismanoid 0:777851395940 985 {
whismanoid 0:777851395940 986
whismanoid 0:777851395940 987 //----------------------------------------
whismanoid 0:777851395940 988 // Define command code
whismanoid 0:777851395940 989 uint8_t command_regAddress = CMD_0101_0000_0000_0000_0000_0000_SW_CLEAR;
whismanoid 0:777851395940 990 uint16_t regValue = 0; // 0000_0000_0000_0000
whismanoid 0:777851395940 991
whismanoid 0:777851395940 992 //----------------------------------------
whismanoid 0:777851395940 993 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 994 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 995 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 996 SPIoutputCS(0);
whismanoid 0:777851395940 997 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 998 SPIoutputCS(1);
whismanoid 0:777851395940 999
whismanoid 0:777851395940 1000 //----------------------------------------
whismanoid 0:777851395940 1001 // after successful SW_RESET, update shadow registers
whismanoid 0:777851395940 1002 // assume SPI write was successful
whismanoid 0:777851395940 1003 if (1)
whismanoid 0:777851395940 1004 {
whismanoid 0:777851395940 1005 // shadow of write-only register CODE[channel_0_3] CMD_0010_nnnn
whismanoid 0:777851395940 1006 Shadow_0010_nnnn_CODE[0] = 0x0000;
whismanoid 0:777851395940 1007 Shadow_0010_nnnn_CODE[1] = 0x0000;
whismanoid 0:777851395940 1008 Shadow_0010_nnnn_CODE[2] = 0x0000;
whismanoid 0:777851395940 1009 Shadow_0010_nnnn_CODE[3] = 0x0000;
whismanoid 0:777851395940 1010 //
whismanoid 0:777851395940 1011 // shadow of write-only register POWER[channel_0_3] CMD_0100_00pp
whismanoid 0:777851395940 1012 //Shadow_0100_00pp_POWER[0] = POWERn_Normal;
whismanoid 0:777851395940 1013 //Shadow_0100_00pp_POWER[1] = POWERn_Normal;
whismanoid 0:777851395940 1014 //Shadow_0100_00pp_POWER[2] = POWERn_Normal;
whismanoid 0:777851395940 1015 //Shadow_0100_00pp_POWER[3] = POWERn_Normal;
whismanoid 0:777851395940 1016 //
whismanoid 0:777851395940 1017 // shadow of write-only register CONFIG[channel_0_3] CMD_0110_a00t
whismanoid 0:777851395940 1018 //Shadow_0110_a00t_CONFIG[0] = 0; // normal (latched, not transparent)
whismanoid 0:777851395940 1019 //Shadow_0110_a00t_CONFIG[1] = 0; // normal (latched, not transparent)
whismanoid 0:777851395940 1020 //Shadow_0110_a00t_CONFIG[2] = 0; // normal (latched, not transparent)
whismanoid 0:777851395940 1021 //Shadow_0110_a00t_CONFIG[3] = 0; // normal (latched, not transparent)
whismanoid 0:777851395940 1022 //
whismanoid 0:777851395940 1023 // shadow of write-only register REF CMD_0111_0rrr
whismanoid 0:777851395940 1024 //Shadow_0111_0rrr_REF = REF_EXT;
whismanoid 0:777851395940 1025 //
whismanoid 0:777851395940 1026 // shadow of CODE field of write-only register CODE[channel_0_3] CMD_0010_nnnn
whismanoid 0:777851395940 1027 CODE[0] = 0x0000;
whismanoid 0:777851395940 1028 CODE[1] = 0x0000;
whismanoid 0:777851395940 1029 CODE[2] = 0x0000;
whismanoid 0:777851395940 1030 CODE[3] = 0x0000;
whismanoid 0:777851395940 1031 //
whismanoid 0:777851395940 1032 }
whismanoid 0:777851395940 1033
whismanoid 0:777851395940 1034 //----------------------------------------
whismanoid 0:777851395940 1035 // success
whismanoid 0:777851395940 1036 return 1;
whismanoid 0:777851395940 1037 }
whismanoid 0:777851395940 1038
whismanoid 0:777851395940 1039 //----------------------------------------
whismanoid 0:777851395940 1040 // CMD_0101_0001_0000_0000_0000_0000_SW_RESET
whismanoid 0:777851395940 1041 //
whismanoid 0:777851395940 1042 // Software Reset
whismanoid 0:777851395940 1043 // All CODE, DAC, and control registers returned to their default values,
whismanoid 0:777851395940 1044 // simulating a power cycle reset.
whismanoid 0:777851395940 1045 //
whismanoid 0:777851395940 1046 // @return 1 on success; 0 on failure
whismanoid 0:777851395940 1047 uint8_t MAX5715::SW_RESET(void)
whismanoid 0:777851395940 1048 {
whismanoid 0:777851395940 1049
whismanoid 0:777851395940 1050 //----------------------------------------
whismanoid 0:777851395940 1051 // Define command code
whismanoid 0:777851395940 1052 uint8_t command_regAddress = CMD_0101_0001_0000_0000_0000_0000_SW_RESET;
whismanoid 0:777851395940 1053 uint16_t regValue = 0; // 0000_0000_0000_0000
whismanoid 0:777851395940 1054
whismanoid 0:777851395940 1055 //----------------------------------------
whismanoid 0:777851395940 1056 // SPI write 8-bit regAddress and 16-bit regValue
whismanoid 0:777851395940 1057 // int16_t mosiData16 = ((command_regAddress << 8) & 0xFF00) | ((regValue >> 8) & 0xFF);
whismanoid 0:777851395940 1058 // int8_t mosiData8_0000FF = (regValue & 0xFF);
whismanoid 0:777851395940 1059 SPIoutputCS(0);
whismanoid 0:777851395940 1060 SPIwrite24bits(command_regAddress, regValue);
whismanoid 0:777851395940 1061 SPIoutputCS(1);
whismanoid 0:777851395940 1062
whismanoid 0:777851395940 1063 //----------------------------------------
whismanoid 0:777851395940 1064 // after successful SW_RESET, update shadow registers
whismanoid 0:777851395940 1065 // assume SPI write was successful
whismanoid 0:777851395940 1066 if (1)
whismanoid 0:777851395940 1067 {
whismanoid 0:777851395940 1068 // shadow of write-only register CODE[channel_0_3] CMD_0010_nnnn
whismanoid 0:777851395940 1069 Shadow_0010_nnnn_CODE[0] = 0x0000;
whismanoid 0:777851395940 1070 Shadow_0010_nnnn_CODE[1] = 0x0000;
whismanoid 0:777851395940 1071 Shadow_0010_nnnn_CODE[2] = 0x0000;
whismanoid 0:777851395940 1072 Shadow_0010_nnnn_CODE[3] = 0x0000;
whismanoid 0:777851395940 1073 //
whismanoid 0:777851395940 1074 // shadow of write-only register POWER[channel_0_3] CMD_0100_00pp
whismanoid 0:777851395940 1075 Shadow_0100_00pp_POWER[0] = POWERn_Normal;
whismanoid 0:777851395940 1076 Shadow_0100_00pp_POWER[1] = POWERn_Normal;
whismanoid 0:777851395940 1077 Shadow_0100_00pp_POWER[2] = POWERn_Normal;
whismanoid 0:777851395940 1078 Shadow_0100_00pp_POWER[3] = POWERn_Normal;
whismanoid 0:777851395940 1079 //
whismanoid 0:777851395940 1080 // shadow of write-only register CONFIG[channel_0_3] CMD_0110_a00t
whismanoid 0:777851395940 1081 Shadow_0110_a00t_CONFIG[0] = 0; // normal (latched, not transparent)
whismanoid 0:777851395940 1082 Shadow_0110_a00t_CONFIG[1] = 0; // normal (latched, not transparent)
whismanoid 0:777851395940 1083 Shadow_0110_a00t_CONFIG[2] = 0; // normal (latched, not transparent)
whismanoid 0:777851395940 1084 Shadow_0110_a00t_CONFIG[3] = 0; // normal (latched, not transparent)
whismanoid 0:777851395940 1085 //
whismanoid 0:777851395940 1086 // shadow of write-only register REF CMD_0111_0rrr
whismanoid 0:777851395940 1087 Shadow_0111_0rrr_REF = REF_EXT;
whismanoid 0:777851395940 1088 //
whismanoid 0:777851395940 1089 // shadow of CODE field of write-only register CODE[channel_0_3] CMD_0010_nnnn
whismanoid 0:777851395940 1090 CODE[0] = 0x0000;
whismanoid 0:777851395940 1091 CODE[1] = 0x0000;
whismanoid 0:777851395940 1092 CODE[2] = 0x0000;
whismanoid 0:777851395940 1093 CODE[3] = 0x0000;
whismanoid 0:777851395940 1094 //
whismanoid 0:777851395940 1095 }
whismanoid 0:777851395940 1096
whismanoid 0:777851395940 1097 //----------------------------------------
whismanoid 0:777851395940 1098 // success
whismanoid 0:777851395940 1099 return 1;
whismanoid 0:777851395940 1100 }
whismanoid 0:777851395940 1101
whismanoid 0:777851395940 1102
whismanoid 0:777851395940 1103 // End of file