Maxim Integrated / Mbed OS Host_Software_MAX32664GWEB_HR_EXTENDED

ME11B Sample Code in Maxim Integrated Team

Dependencies:   BMI160 max32630hsp3 MemoryLCD USBDevice

Fork of Host_Software_MAX32664GWEB_HR_EXTENDED by Seyhmus Cacina

Drivers/USBDevice/USBDevice/USBRegs_STM32.h@0:ac4dea3e2894, 2019-03-18 (annotated)

Committer:
seyhmus.cacina
Date:
Mon Mar 18 10:21:53 2019 +0300
Revision:
0:ac4dea3e2894
ME11B Sample Code First Commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
seyhmus.cacina 0:ac4dea3e2894 1 /**
seyhmus.cacina 0:ac4dea3e2894 2 ******************************************************************************
seyhmus.cacina 0:ac4dea3e2894 3 * @file usb_regs.h
seyhmus.cacina 0:ac4dea3e2894 4 * @author MCD Application Team
seyhmus.cacina 0:ac4dea3e2894 5 * @version V2.1.0
seyhmus.cacina 0:ac4dea3e2894 6 * @date 19-March-2012
seyhmus.cacina 0:ac4dea3e2894 7 * @brief hardware registers
seyhmus.cacina 0:ac4dea3e2894 8 ******************************************************************************
seyhmus.cacina 0:ac4dea3e2894 9 * @attention
seyhmus.cacina 0:ac4dea3e2894 10 *
seyhmus.cacina 0:ac4dea3e2894 11 * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
seyhmus.cacina 0:ac4dea3e2894 12 *
seyhmus.cacina 0:ac4dea3e2894 13 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
seyhmus.cacina 0:ac4dea3e2894 14 * You may not use this file except in compliance with the License.
seyhmus.cacina 0:ac4dea3e2894 15 * You may obtain a copy of the License at:
seyhmus.cacina 0:ac4dea3e2894 16 *
seyhmus.cacina 0:ac4dea3e2894 17 * http://www.st.com/software_license_agreement_liberty_v2
seyhmus.cacina 0:ac4dea3e2894 18 *
seyhmus.cacina 0:ac4dea3e2894 19 * Unless required by applicable law or agreed to in writing, software
seyhmus.cacina 0:ac4dea3e2894 20 * distributed under the License is distributed on an "AS IS" BASIS,
seyhmus.cacina 0:ac4dea3e2894 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
seyhmus.cacina 0:ac4dea3e2894 22 * See the License for the specific language governing permissions and
seyhmus.cacina 0:ac4dea3e2894 23 * limitations under the License.
seyhmus.cacina 0:ac4dea3e2894 24 *
seyhmus.cacina 0:ac4dea3e2894 25 ******************************************************************************
seyhmus.cacina 0:ac4dea3e2894 26 */
seyhmus.cacina 0:ac4dea3e2894 27
seyhmus.cacina 0:ac4dea3e2894 28 #ifndef __USB_OTG_REGS_H__
seyhmus.cacina 0:ac4dea3e2894 29 #define __USB_OTG_REGS_H__
seyhmus.cacina 0:ac4dea3e2894 30
seyhmus.cacina 0:ac4dea3e2894 31 typedef struct //000h
seyhmus.cacina 0:ac4dea3e2894 32 {
seyhmus.cacina 0:ac4dea3e2894 33 __IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/
seyhmus.cacina 0:ac4dea3e2894 34 __IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/
seyhmus.cacina 0:ac4dea3e2894 35 __IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/
seyhmus.cacina 0:ac4dea3e2894 36 __IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/
seyhmus.cacina 0:ac4dea3e2894 37 __IO uint32_t GRSTCTL; /* Core Reset Register 010h*/
seyhmus.cacina 0:ac4dea3e2894 38 __IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/
seyhmus.cacina 0:ac4dea3e2894 39 __IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/
seyhmus.cacina 0:ac4dea3e2894 40 __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/
seyhmus.cacina 0:ac4dea3e2894 41 __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/
seyhmus.cacina 0:ac4dea3e2894 42 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
seyhmus.cacina 0:ac4dea3e2894 43 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/
seyhmus.cacina 0:ac4dea3e2894 44 __IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
seyhmus.cacina 0:ac4dea3e2894 45 uint32_t Reserved30[2]; /* Reserved 030h*/
seyhmus.cacina 0:ac4dea3e2894 46 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
seyhmus.cacina 0:ac4dea3e2894 47 __IO uint32_t CID; /* User ID Register 03Ch*/
seyhmus.cacina 0:ac4dea3e2894 48 uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
seyhmus.cacina 0:ac4dea3e2894 49 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
seyhmus.cacina 0:ac4dea3e2894 50 __IO uint32_t DIEPTXF[3];/* dev Periodic Transmit FIFO */
seyhmus.cacina 0:ac4dea3e2894 51 }
seyhmus.cacina 0:ac4dea3e2894 52 USB_OTG_GREGS;
seyhmus.cacina 0:ac4dea3e2894 53
seyhmus.cacina 0:ac4dea3e2894 54 typedef struct // 800h
seyhmus.cacina 0:ac4dea3e2894 55 {
seyhmus.cacina 0:ac4dea3e2894 56 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
seyhmus.cacina 0:ac4dea3e2894 57 __IO uint32_t DCTL; /* dev Control Register 804h*/
seyhmus.cacina 0:ac4dea3e2894 58 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
seyhmus.cacina 0:ac4dea3e2894 59 uint32_t Reserved0C; /* Reserved 80Ch*/
seyhmus.cacina 0:ac4dea3e2894 60 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
seyhmus.cacina 0:ac4dea3e2894 61 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
seyhmus.cacina 0:ac4dea3e2894 62 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
seyhmus.cacina 0:ac4dea3e2894 63 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
seyhmus.cacina 0:ac4dea3e2894 64 uint32_t Reserved20; /* Reserved 820h*/
seyhmus.cacina 0:ac4dea3e2894 65 uint32_t Reserved9; /* Reserved 824h*/
seyhmus.cacina 0:ac4dea3e2894 66 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
seyhmus.cacina 0:ac4dea3e2894 67 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
seyhmus.cacina 0:ac4dea3e2894 68 __IO uint32_t DTHRCTL; /* dev thr 830h*/
seyhmus.cacina 0:ac4dea3e2894 69 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
seyhmus.cacina 0:ac4dea3e2894 70 }
seyhmus.cacina 0:ac4dea3e2894 71 USB_OTG_DREGS;
seyhmus.cacina 0:ac4dea3e2894 72
seyhmus.cacina 0:ac4dea3e2894 73 typedef struct
seyhmus.cacina 0:ac4dea3e2894 74 {
seyhmus.cacina 0:ac4dea3e2894 75 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
seyhmus.cacina 0:ac4dea3e2894 76 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
seyhmus.cacina 0:ac4dea3e2894 77 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
seyhmus.cacina 0:ac4dea3e2894 78 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
seyhmus.cacina 0:ac4dea3e2894 79 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
seyhmus.cacina 0:ac4dea3e2894 80 uint32_t Reserved14;
seyhmus.cacina 0:ac4dea3e2894 81 __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
seyhmus.cacina 0:ac4dea3e2894 82 uint32_t Reserved1C; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
seyhmus.cacina 0:ac4dea3e2894 83 }
seyhmus.cacina 0:ac4dea3e2894 84 USB_OTG_INEPREGS;
seyhmus.cacina 0:ac4dea3e2894 85
seyhmus.cacina 0:ac4dea3e2894 86 typedef struct
seyhmus.cacina 0:ac4dea3e2894 87 {
seyhmus.cacina 0:ac4dea3e2894 88 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
seyhmus.cacina 0:ac4dea3e2894 89 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
seyhmus.cacina 0:ac4dea3e2894 90 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
seyhmus.cacina 0:ac4dea3e2894 91 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
seyhmus.cacina 0:ac4dea3e2894 92 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
seyhmus.cacina 0:ac4dea3e2894 93 uint32_t Reserved14[3];
seyhmus.cacina 0:ac4dea3e2894 94 }
seyhmus.cacina 0:ac4dea3e2894 95 USB_OTG_OUTEPREGS;
seyhmus.cacina 0:ac4dea3e2894 96
seyhmus.cacina 0:ac4dea3e2894 97 typedef struct
seyhmus.cacina 0:ac4dea3e2894 98 {
seyhmus.cacina 0:ac4dea3e2894 99 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
seyhmus.cacina 0:ac4dea3e2894 100 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
seyhmus.cacina 0:ac4dea3e2894 101 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
seyhmus.cacina 0:ac4dea3e2894 102 uint32_t Reserved40C; /* Reserved 40Ch*/
seyhmus.cacina 0:ac4dea3e2894 103 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
seyhmus.cacina 0:ac4dea3e2894 104 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
seyhmus.cacina 0:ac4dea3e2894 105 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
seyhmus.cacina 0:ac4dea3e2894 106 }
seyhmus.cacina 0:ac4dea3e2894 107 USB_OTG_HREGS;
seyhmus.cacina 0:ac4dea3e2894 108
seyhmus.cacina 0:ac4dea3e2894 109 typedef struct
seyhmus.cacina 0:ac4dea3e2894 110 {
seyhmus.cacina 0:ac4dea3e2894 111 __IO uint32_t HCCHAR;
seyhmus.cacina 0:ac4dea3e2894 112 __IO uint32_t HCSPLT;
seyhmus.cacina 0:ac4dea3e2894 113 __IO uint32_t HCINT;
seyhmus.cacina 0:ac4dea3e2894 114 __IO uint32_t HCINTMSK;
seyhmus.cacina 0:ac4dea3e2894 115 __IO uint32_t HCTSIZ;
seyhmus.cacina 0:ac4dea3e2894 116 uint32_t Reserved[3];
seyhmus.cacina 0:ac4dea3e2894 117 }
seyhmus.cacina 0:ac4dea3e2894 118 USB_OTG_HC_REGS;
seyhmus.cacina 0:ac4dea3e2894 119
seyhmus.cacina 0:ac4dea3e2894 120 typedef struct
seyhmus.cacina 0:ac4dea3e2894 121 {
seyhmus.cacina 0:ac4dea3e2894 122 USB_OTG_GREGS GREGS;
seyhmus.cacina 0:ac4dea3e2894 123 uint32_t RESERVED0[188];
seyhmus.cacina 0:ac4dea3e2894 124 USB_OTG_HREGS HREGS;
seyhmus.cacina 0:ac4dea3e2894 125 uint32_t RESERVED1[9];
seyhmus.cacina 0:ac4dea3e2894 126 __IO uint32_t HPRT;
seyhmus.cacina 0:ac4dea3e2894 127 uint32_t RESERVED2[47];
seyhmus.cacina 0:ac4dea3e2894 128 USB_OTG_HC_REGS HC_REGS[8];
seyhmus.cacina 0:ac4dea3e2894 129 uint32_t RESERVED3[128];
seyhmus.cacina 0:ac4dea3e2894 130 USB_OTG_DREGS DREGS;
seyhmus.cacina 0:ac4dea3e2894 131 uint32_t RESERVED4[50];
seyhmus.cacina 0:ac4dea3e2894 132 USB_OTG_INEPREGS INEP_REGS[4];
seyhmus.cacina 0:ac4dea3e2894 133 uint32_t RESERVED5[96];
seyhmus.cacina 0:ac4dea3e2894 134 USB_OTG_OUTEPREGS OUTEP_REGS[4];
seyhmus.cacina 0:ac4dea3e2894 135 uint32_t RESERVED6[160];
seyhmus.cacina 0:ac4dea3e2894 136 __IO uint32_t PCGCCTL;
seyhmus.cacina 0:ac4dea3e2894 137 uint32_t RESERVED7[127];
seyhmus.cacina 0:ac4dea3e2894 138 __IO uint32_t FIFO[4][1024];
seyhmus.cacina 0:ac4dea3e2894 139 }
seyhmus.cacina 0:ac4dea3e2894 140 USB_OTG_CORE_REGS;
seyhmus.cacina 0:ac4dea3e2894 141
seyhmus.cacina 0:ac4dea3e2894 142
seyhmus.cacina 0:ac4dea3e2894 143 #define OTG_FS_BASE (AHB2PERIPH_BASE + 0x0000)
seyhmus.cacina 0:ac4dea3e2894 144 #define OTG_FS ((USB_OTG_CORE_REGS *) OTG_FS_BASE)
seyhmus.cacina 0:ac4dea3e2894 145
seyhmus.cacina 0:ac4dea3e2894 146 #endif //__USB_OTG_REGS_H__
seyhmus.cacina 0:ac4dea3e2894 147
seyhmus.cacina 0:ac4dea3e2894 148 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
seyhmus.cacina 0:ac4dea3e2894 149