Maxim Integrated / Mbed OS Host_Software_MAX32664GWEB_HR_EXTENDED

ME11B Sample Code in Maxim Integrated Team

Dependencies:   BMI160 max32630hsp3 MemoryLCD USBDevice

Fork of Host_Software_MAX32664GWEB_HR_EXTENDED by Seyhmus Cacina

Drivers/USBDevice/USBDevice/USBHAL_LPC17.cpp@0:ac4dea3e2894, 2019-03-18 (annotated)

Committer:
seyhmus.cacina
Date:
Mon Mar 18 10:21:53 2019 +0300
Revision:
0:ac4dea3e2894
ME11B Sample Code First Commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
seyhmus.cacina 0:ac4dea3e2894 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
seyhmus.cacina 0:ac4dea3e2894 2 *
seyhmus.cacina 0:ac4dea3e2894 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
seyhmus.cacina 0:ac4dea3e2894 4 * and associated documentation files (the "Software"), to deal in the Software without
seyhmus.cacina 0:ac4dea3e2894 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
seyhmus.cacina 0:ac4dea3e2894 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
seyhmus.cacina 0:ac4dea3e2894 7 * Software is furnished to do so, subject to the following conditions:
seyhmus.cacina 0:ac4dea3e2894 8 *
seyhmus.cacina 0:ac4dea3e2894 9 * The above copyright notice and this permission notice shall be included in all copies or
seyhmus.cacina 0:ac4dea3e2894 10 * substantial portions of the Software.
seyhmus.cacina 0:ac4dea3e2894 11 *
seyhmus.cacina 0:ac4dea3e2894 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
seyhmus.cacina 0:ac4dea3e2894 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
seyhmus.cacina 0:ac4dea3e2894 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
seyhmus.cacina 0:ac4dea3e2894 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
seyhmus.cacina 0:ac4dea3e2894 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
seyhmus.cacina 0:ac4dea3e2894 17 */
seyhmus.cacina 0:ac4dea3e2894 18
seyhmus.cacina 0:ac4dea3e2894 19 #if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC2460)
seyhmus.cacina 0:ac4dea3e2894 20
seyhmus.cacina 0:ac4dea3e2894 21 #include "USBHAL.h"
seyhmus.cacina 0:ac4dea3e2894 22
seyhmus.cacina 0:ac4dea3e2894 23
seyhmus.cacina 0:ac4dea3e2894 24 // Get endpoint direction
seyhmus.cacina 0:ac4dea3e2894 25 #define IN_EP(endpoint) ((endpoint) & 1U ? true : false)
seyhmus.cacina 0:ac4dea3e2894 26 #define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
seyhmus.cacina 0:ac4dea3e2894 27
seyhmus.cacina 0:ac4dea3e2894 28 // Convert physical endpoint number to register bit
seyhmus.cacina 0:ac4dea3e2894 29 #define EP(endpoint) (1UL<<endpoint)
seyhmus.cacina 0:ac4dea3e2894 30
seyhmus.cacina 0:ac4dea3e2894 31 // Power Control for Peripherals register
seyhmus.cacina 0:ac4dea3e2894 32 #define PCUSB (1UL<<31)
seyhmus.cacina 0:ac4dea3e2894 33
seyhmus.cacina 0:ac4dea3e2894 34 // USB Clock Control register
seyhmus.cacina 0:ac4dea3e2894 35 #define DEV_CLK_EN (1UL<<1)
seyhmus.cacina 0:ac4dea3e2894 36 #define AHB_CLK_EN (1UL<<4)
seyhmus.cacina 0:ac4dea3e2894 37
seyhmus.cacina 0:ac4dea3e2894 38 // USB Clock Status register
seyhmus.cacina 0:ac4dea3e2894 39 #define DEV_CLK_ON (1UL<<1)
seyhmus.cacina 0:ac4dea3e2894 40 #define AHB_CLK_ON (1UL<<4)
seyhmus.cacina 0:ac4dea3e2894 41
seyhmus.cacina 0:ac4dea3e2894 42 // USB Device Interupt registers
seyhmus.cacina 0:ac4dea3e2894 43 #define FRAME (1UL<<0)
seyhmus.cacina 0:ac4dea3e2894 44 #define EP_FAST (1UL<<1)
seyhmus.cacina 0:ac4dea3e2894 45 #define EP_SLOW (1UL<<2)
seyhmus.cacina 0:ac4dea3e2894 46 #define DEV_STAT (1UL<<3)
seyhmus.cacina 0:ac4dea3e2894 47 #define CCEMPTY (1UL<<4)
seyhmus.cacina 0:ac4dea3e2894 48 #define CDFULL (1UL<<5)
seyhmus.cacina 0:ac4dea3e2894 49 #define RxENDPKT (1UL<<6)
seyhmus.cacina 0:ac4dea3e2894 50 #define TxENDPKT (1UL<<7)
seyhmus.cacina 0:ac4dea3e2894 51 #define EP_RLZED (1UL<<8)
seyhmus.cacina 0:ac4dea3e2894 52 #define ERR_INT (1UL<<9)
seyhmus.cacina 0:ac4dea3e2894 53
seyhmus.cacina 0:ac4dea3e2894 54 // USB Control register
seyhmus.cacina 0:ac4dea3e2894 55 #define RD_EN (1<<0)
seyhmus.cacina 0:ac4dea3e2894 56 #define WR_EN (1<<1)
seyhmus.cacina 0:ac4dea3e2894 57 #define LOG_ENDPOINT(endpoint) ((endpoint>>1)<<2)
seyhmus.cacina 0:ac4dea3e2894 58
seyhmus.cacina 0:ac4dea3e2894 59 // USB Receive Packet Length register
seyhmus.cacina 0:ac4dea3e2894 60 #define DV (1UL<<10)
seyhmus.cacina 0:ac4dea3e2894 61 #define PKT_RDY (1UL<<11)
seyhmus.cacina 0:ac4dea3e2894 62 #define PKT_LNGTH_MASK (0x3ff)
seyhmus.cacina 0:ac4dea3e2894 63
seyhmus.cacina 0:ac4dea3e2894 64 // Serial Interface Engine (SIE)
seyhmus.cacina 0:ac4dea3e2894 65 #define SIE_WRITE (0x01)
seyhmus.cacina 0:ac4dea3e2894 66 #define SIE_READ (0x02)
seyhmus.cacina 0:ac4dea3e2894 67 #define SIE_COMMAND (0x05)
seyhmus.cacina 0:ac4dea3e2894 68 #define SIE_CMD_CODE(phase, data) ((phase<<8)|(data<<16))
seyhmus.cacina 0:ac4dea3e2894 69
seyhmus.cacina 0:ac4dea3e2894 70 // SIE Command codes
seyhmus.cacina 0:ac4dea3e2894 71 #define SIE_CMD_SET_ADDRESS (0xD0)
seyhmus.cacina 0:ac4dea3e2894 72 #define SIE_CMD_CONFIGURE_DEVICE (0xD8)
seyhmus.cacina 0:ac4dea3e2894 73 #define SIE_CMD_SET_MODE (0xF3)
seyhmus.cacina 0:ac4dea3e2894 74 #define SIE_CMD_READ_FRAME_NUMBER (0xF5)
seyhmus.cacina 0:ac4dea3e2894 75 #define SIE_CMD_READ_TEST_REGISTER (0xFD)
seyhmus.cacina 0:ac4dea3e2894 76 #define SIE_CMD_SET_DEVICE_STATUS (0xFE)
seyhmus.cacina 0:ac4dea3e2894 77 #define SIE_CMD_GET_DEVICE_STATUS (0xFE)
seyhmus.cacina 0:ac4dea3e2894 78 #define SIE_CMD_GET_ERROR_CODE (0xFF)
seyhmus.cacina 0:ac4dea3e2894 79 #define SIE_CMD_READ_ERROR_STATUS (0xFB)
seyhmus.cacina 0:ac4dea3e2894 80
seyhmus.cacina 0:ac4dea3e2894 81 #define SIE_CMD_SELECT_ENDPOINT(endpoint) (0x00+endpoint)
seyhmus.cacina 0:ac4dea3e2894 82 #define SIE_CMD_SELECT_ENDPOINT_CLEAR_INTERRUPT(endpoint) (0x40+endpoint)
seyhmus.cacina 0:ac4dea3e2894 83 #define SIE_CMD_SET_ENDPOINT_STATUS(endpoint) (0x40+endpoint)
seyhmus.cacina 0:ac4dea3e2894 84
seyhmus.cacina 0:ac4dea3e2894 85 #define SIE_CMD_CLEAR_BUFFER (0xF2)
seyhmus.cacina 0:ac4dea3e2894 86 #define SIE_CMD_VALIDATE_BUFFER (0xFA)
seyhmus.cacina 0:ac4dea3e2894 87
seyhmus.cacina 0:ac4dea3e2894 88 // SIE Device Status register
seyhmus.cacina 0:ac4dea3e2894 89 #define SIE_DS_CON (1<<0)
seyhmus.cacina 0:ac4dea3e2894 90 #define SIE_DS_CON_CH (1<<1)
seyhmus.cacina 0:ac4dea3e2894 91 #define SIE_DS_SUS (1<<2)
seyhmus.cacina 0:ac4dea3e2894 92 #define SIE_DS_SUS_CH (1<<3)
seyhmus.cacina 0:ac4dea3e2894 93 #define SIE_DS_RST (1<<4)
seyhmus.cacina 0:ac4dea3e2894 94
seyhmus.cacina 0:ac4dea3e2894 95 // SIE Device Set Address register
seyhmus.cacina 0:ac4dea3e2894 96 #define SIE_DSA_DEV_EN (1<<7)
seyhmus.cacina 0:ac4dea3e2894 97
seyhmus.cacina 0:ac4dea3e2894 98 // SIE Configue Device register
seyhmus.cacina 0:ac4dea3e2894 99 #define SIE_CONF_DEVICE (1<<0)
seyhmus.cacina 0:ac4dea3e2894 100
seyhmus.cacina 0:ac4dea3e2894 101 // Select Endpoint register
seyhmus.cacina 0:ac4dea3e2894 102 #define SIE_SE_FE (1<<0)
seyhmus.cacina 0:ac4dea3e2894 103 #define SIE_SE_ST (1<<1)
seyhmus.cacina 0:ac4dea3e2894 104 #define SIE_SE_STP (1<<2)
seyhmus.cacina 0:ac4dea3e2894 105 #define SIE_SE_PO (1<<3)
seyhmus.cacina 0:ac4dea3e2894 106 #define SIE_SE_EPN (1<<4)
seyhmus.cacina 0:ac4dea3e2894 107 #define SIE_SE_B_1_FULL (1<<5)
seyhmus.cacina 0:ac4dea3e2894 108 #define SIE_SE_B_2_FULL (1<<6)
seyhmus.cacina 0:ac4dea3e2894 109
seyhmus.cacina 0:ac4dea3e2894 110 // Set Endpoint Status command
seyhmus.cacina 0:ac4dea3e2894 111 #define SIE_SES_ST (1<<0)
seyhmus.cacina 0:ac4dea3e2894 112 #define SIE_SES_DA (1<<5)
seyhmus.cacina 0:ac4dea3e2894 113 #define SIE_SES_RF_MO (1<<6)
seyhmus.cacina 0:ac4dea3e2894 114 #define SIE_SES_CND_ST (1<<7)
seyhmus.cacina 0:ac4dea3e2894 115
seyhmus.cacina 0:ac4dea3e2894 116
seyhmus.cacina 0:ac4dea3e2894 117 USBHAL * USBHAL::instance;
seyhmus.cacina 0:ac4dea3e2894 118
seyhmus.cacina 0:ac4dea3e2894 119 static volatile int epComplete;
seyhmus.cacina 0:ac4dea3e2894 120 static uint32_t endpointStallState;
seyhmus.cacina 0:ac4dea3e2894 121
seyhmus.cacina 0:ac4dea3e2894 122 static void SIECommand(uint32_t command) {
seyhmus.cacina 0:ac4dea3e2894 123 // The command phase of a SIE transaction
seyhmus.cacina 0:ac4dea3e2894 124 LPC_USB->USBDevIntClr = CCEMPTY;
seyhmus.cacina 0:ac4dea3e2894 125 LPC_USB->USBCmdCode = SIE_CMD_CODE(SIE_COMMAND, command);
seyhmus.cacina 0:ac4dea3e2894 126 while (!(LPC_USB->USBDevIntSt & CCEMPTY));
seyhmus.cacina 0:ac4dea3e2894 127 }
seyhmus.cacina 0:ac4dea3e2894 128
seyhmus.cacina 0:ac4dea3e2894 129 static void SIEWriteData(uint8_t data) {
seyhmus.cacina 0:ac4dea3e2894 130 // The data write phase of a SIE transaction
seyhmus.cacina 0:ac4dea3e2894 131 LPC_USB->USBDevIntClr = CCEMPTY;
seyhmus.cacina 0:ac4dea3e2894 132 LPC_USB->USBCmdCode = SIE_CMD_CODE(SIE_WRITE, data);
seyhmus.cacina 0:ac4dea3e2894 133 while (!(LPC_USB->USBDevIntSt & CCEMPTY));
seyhmus.cacina 0:ac4dea3e2894 134 }
seyhmus.cacina 0:ac4dea3e2894 135
seyhmus.cacina 0:ac4dea3e2894 136 static uint8_t SIEReadData(uint32_t command) {
seyhmus.cacina 0:ac4dea3e2894 137 // The data read phase of a SIE transaction
seyhmus.cacina 0:ac4dea3e2894 138 LPC_USB->USBDevIntClr = CDFULL;
seyhmus.cacina 0:ac4dea3e2894 139 LPC_USB->USBCmdCode = SIE_CMD_CODE(SIE_READ, command);
seyhmus.cacina 0:ac4dea3e2894 140 while (!(LPC_USB->USBDevIntSt & CDFULL));
seyhmus.cacina 0:ac4dea3e2894 141 return (uint8_t)LPC_USB->USBCmdData;
seyhmus.cacina 0:ac4dea3e2894 142 }
seyhmus.cacina 0:ac4dea3e2894 143
seyhmus.cacina 0:ac4dea3e2894 144 static void SIEsetDeviceStatus(uint8_t status) {
seyhmus.cacina 0:ac4dea3e2894 145 // Write SIE device status register
seyhmus.cacina 0:ac4dea3e2894 146 SIECommand(SIE_CMD_SET_DEVICE_STATUS);
seyhmus.cacina 0:ac4dea3e2894 147 SIEWriteData(status);
seyhmus.cacina 0:ac4dea3e2894 148 }
seyhmus.cacina 0:ac4dea3e2894 149
seyhmus.cacina 0:ac4dea3e2894 150 static uint8_t SIEgetDeviceStatus(void) {
seyhmus.cacina 0:ac4dea3e2894 151 // Read SIE device status register
seyhmus.cacina 0:ac4dea3e2894 152 SIECommand(SIE_CMD_GET_DEVICE_STATUS);
seyhmus.cacina 0:ac4dea3e2894 153 return SIEReadData(SIE_CMD_GET_DEVICE_STATUS);
seyhmus.cacina 0:ac4dea3e2894 154 }
seyhmus.cacina 0:ac4dea3e2894 155
seyhmus.cacina 0:ac4dea3e2894 156 void SIEsetAddress(uint8_t address) {
seyhmus.cacina 0:ac4dea3e2894 157 // Write SIE device address register
seyhmus.cacina 0:ac4dea3e2894 158 SIECommand(SIE_CMD_SET_ADDRESS);
seyhmus.cacina 0:ac4dea3e2894 159 SIEWriteData((address & 0x7f) | SIE_DSA_DEV_EN);
seyhmus.cacina 0:ac4dea3e2894 160 }
seyhmus.cacina 0:ac4dea3e2894 161
seyhmus.cacina 0:ac4dea3e2894 162 static uint8_t SIEselectEndpoint(uint8_t endpoint) {
seyhmus.cacina 0:ac4dea3e2894 163 // SIE select endpoint command
seyhmus.cacina 0:ac4dea3e2894 164 SIECommand(SIE_CMD_SELECT_ENDPOINT(endpoint));
seyhmus.cacina 0:ac4dea3e2894 165 return SIEReadData(SIE_CMD_SELECT_ENDPOINT(endpoint));
seyhmus.cacina 0:ac4dea3e2894 166 }
seyhmus.cacina 0:ac4dea3e2894 167
seyhmus.cacina 0:ac4dea3e2894 168 static uint8_t SIEclearBuffer(void) {
seyhmus.cacina 0:ac4dea3e2894 169 // SIE clear buffer command
seyhmus.cacina 0:ac4dea3e2894 170 SIECommand(SIE_CMD_CLEAR_BUFFER);
seyhmus.cacina 0:ac4dea3e2894 171 return SIEReadData(SIE_CMD_CLEAR_BUFFER);
seyhmus.cacina 0:ac4dea3e2894 172 }
seyhmus.cacina 0:ac4dea3e2894 173
seyhmus.cacina 0:ac4dea3e2894 174 static void SIEvalidateBuffer(void) {
seyhmus.cacina 0:ac4dea3e2894 175 // SIE validate buffer command
seyhmus.cacina 0:ac4dea3e2894 176 SIECommand(SIE_CMD_VALIDATE_BUFFER);
seyhmus.cacina 0:ac4dea3e2894 177 }
seyhmus.cacina 0:ac4dea3e2894 178
seyhmus.cacina 0:ac4dea3e2894 179 static void SIEsetEndpointStatus(uint8_t endpoint, uint8_t status) {
seyhmus.cacina 0:ac4dea3e2894 180 // SIE set endpoint status command
seyhmus.cacina 0:ac4dea3e2894 181 SIECommand(SIE_CMD_SET_ENDPOINT_STATUS(endpoint));
seyhmus.cacina 0:ac4dea3e2894 182 SIEWriteData(status);
seyhmus.cacina 0:ac4dea3e2894 183 }
seyhmus.cacina 0:ac4dea3e2894 184
seyhmus.cacina 0:ac4dea3e2894 185 static uint16_t SIEgetFrameNumber(void) __attribute__ ((unused));
seyhmus.cacina 0:ac4dea3e2894 186 static uint16_t SIEgetFrameNumber(void) {
seyhmus.cacina 0:ac4dea3e2894 187 // Read current frame number
seyhmus.cacina 0:ac4dea3e2894 188 uint16_t lowByte;
seyhmus.cacina 0:ac4dea3e2894 189 uint16_t highByte;
seyhmus.cacina 0:ac4dea3e2894 190
seyhmus.cacina 0:ac4dea3e2894 191 SIECommand(SIE_CMD_READ_FRAME_NUMBER);
seyhmus.cacina 0:ac4dea3e2894 192 lowByte = SIEReadData(SIE_CMD_READ_FRAME_NUMBER);
seyhmus.cacina 0:ac4dea3e2894 193 highByte = SIEReadData(SIE_CMD_READ_FRAME_NUMBER);
seyhmus.cacina 0:ac4dea3e2894 194
seyhmus.cacina 0:ac4dea3e2894 195 return (highByte << 8) | lowByte;
seyhmus.cacina 0:ac4dea3e2894 196 }
seyhmus.cacina 0:ac4dea3e2894 197
seyhmus.cacina 0:ac4dea3e2894 198 static void SIEconfigureDevice(void) {
seyhmus.cacina 0:ac4dea3e2894 199 // SIE Configure device command
seyhmus.cacina 0:ac4dea3e2894 200 SIECommand(SIE_CMD_CONFIGURE_DEVICE);
seyhmus.cacina 0:ac4dea3e2894 201 SIEWriteData(SIE_CONF_DEVICE);
seyhmus.cacina 0:ac4dea3e2894 202 }
seyhmus.cacina 0:ac4dea3e2894 203
seyhmus.cacina 0:ac4dea3e2894 204 static void SIEunconfigureDevice(void) {
seyhmus.cacina 0:ac4dea3e2894 205 // SIE Configure device command
seyhmus.cacina 0:ac4dea3e2894 206 SIECommand(SIE_CMD_CONFIGURE_DEVICE);
seyhmus.cacina 0:ac4dea3e2894 207 SIEWriteData(0);
seyhmus.cacina 0:ac4dea3e2894 208 }
seyhmus.cacina 0:ac4dea3e2894 209
seyhmus.cacina 0:ac4dea3e2894 210 static void SIEconnect(void) {
seyhmus.cacina 0:ac4dea3e2894 211 // Connect USB device
seyhmus.cacina 0:ac4dea3e2894 212 uint8_t status = SIEgetDeviceStatus();
seyhmus.cacina 0:ac4dea3e2894 213 SIEsetDeviceStatus(status | SIE_DS_CON);
seyhmus.cacina 0:ac4dea3e2894 214 }
seyhmus.cacina 0:ac4dea3e2894 215
seyhmus.cacina 0:ac4dea3e2894 216
seyhmus.cacina 0:ac4dea3e2894 217 static void SIEdisconnect(void) {
seyhmus.cacina 0:ac4dea3e2894 218 // Disconnect USB device
seyhmus.cacina 0:ac4dea3e2894 219 uint8_t status = SIEgetDeviceStatus();
seyhmus.cacina 0:ac4dea3e2894 220 SIEsetDeviceStatus(status & ~SIE_DS_CON);
seyhmus.cacina 0:ac4dea3e2894 221 }
seyhmus.cacina 0:ac4dea3e2894 222
seyhmus.cacina 0:ac4dea3e2894 223
seyhmus.cacina 0:ac4dea3e2894 224 static uint8_t selectEndpointClearInterrupt(uint8_t endpoint) {
seyhmus.cacina 0:ac4dea3e2894 225 // Implemented using using EP_INT_CLR.
seyhmus.cacina 0:ac4dea3e2894 226 LPC_USB->USBEpIntClr = EP(endpoint);
seyhmus.cacina 0:ac4dea3e2894 227 while (!(LPC_USB->USBDevIntSt & CDFULL));
seyhmus.cacina 0:ac4dea3e2894 228 return (uint8_t)LPC_USB->USBCmdData;
seyhmus.cacina 0:ac4dea3e2894 229 }
seyhmus.cacina 0:ac4dea3e2894 230
seyhmus.cacina 0:ac4dea3e2894 231
seyhmus.cacina 0:ac4dea3e2894 232 static void enableEndpointEvent(uint8_t endpoint) {
seyhmus.cacina 0:ac4dea3e2894 233 // Enable an endpoint interrupt
seyhmus.cacina 0:ac4dea3e2894 234 LPC_USB->USBEpIntEn |= EP(endpoint);
seyhmus.cacina 0:ac4dea3e2894 235 }
seyhmus.cacina 0:ac4dea3e2894 236
seyhmus.cacina 0:ac4dea3e2894 237 static void disableEndpointEvent(uint8_t endpoint) __attribute__ ((unused));
seyhmus.cacina 0:ac4dea3e2894 238 static void disableEndpointEvent(uint8_t endpoint) {
seyhmus.cacina 0:ac4dea3e2894 239 // Disable an endpoint interrupt
seyhmus.cacina 0:ac4dea3e2894 240 LPC_USB->USBEpIntEn &= ~EP(endpoint);
seyhmus.cacina 0:ac4dea3e2894 241 }
seyhmus.cacina 0:ac4dea3e2894 242
seyhmus.cacina 0:ac4dea3e2894 243 static volatile uint32_t __attribute__((used)) dummyRead;
seyhmus.cacina 0:ac4dea3e2894 244 uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
seyhmus.cacina 0:ac4dea3e2894 245 // Read from an OUT endpoint
seyhmus.cacina 0:ac4dea3e2894 246 uint32_t size;
seyhmus.cacina 0:ac4dea3e2894 247 uint32_t i;
seyhmus.cacina 0:ac4dea3e2894 248 uint32_t data = 0;
seyhmus.cacina 0:ac4dea3e2894 249 uint8_t offset;
seyhmus.cacina 0:ac4dea3e2894 250
seyhmus.cacina 0:ac4dea3e2894 251 LPC_USB->USBCtrl = LOG_ENDPOINT(endpoint) | RD_EN;
seyhmus.cacina 0:ac4dea3e2894 252 while (!(LPC_USB->USBRxPLen & PKT_RDY));
seyhmus.cacina 0:ac4dea3e2894 253
seyhmus.cacina 0:ac4dea3e2894 254 size = LPC_USB->USBRxPLen & PKT_LNGTH_MASK;
seyhmus.cacina 0:ac4dea3e2894 255
seyhmus.cacina 0:ac4dea3e2894 256 offset = 0;
seyhmus.cacina 0:ac4dea3e2894 257
seyhmus.cacina 0:ac4dea3e2894 258 if (size > 0) {
seyhmus.cacina 0:ac4dea3e2894 259 for (i=0; i<size; i++) {
seyhmus.cacina 0:ac4dea3e2894 260 if (offset==0) {
seyhmus.cacina 0:ac4dea3e2894 261 // Fetch up to four bytes of data as a word
seyhmus.cacina 0:ac4dea3e2894 262 data = LPC_USB->USBRxData;
seyhmus.cacina 0:ac4dea3e2894 263 }
seyhmus.cacina 0:ac4dea3e2894 264
seyhmus.cacina 0:ac4dea3e2894 265 // extract a byte
seyhmus.cacina 0:ac4dea3e2894 266 *buffer = (data>>offset) & 0xff;
seyhmus.cacina 0:ac4dea3e2894 267 buffer++;
seyhmus.cacina 0:ac4dea3e2894 268
seyhmus.cacina 0:ac4dea3e2894 269 // move on to the next byte
seyhmus.cacina 0:ac4dea3e2894 270 offset = (offset + 8) % 32;
seyhmus.cacina 0:ac4dea3e2894 271 }
seyhmus.cacina 0:ac4dea3e2894 272 } else {
seyhmus.cacina 0:ac4dea3e2894 273 dummyRead = LPC_USB->USBRxData;
seyhmus.cacina 0:ac4dea3e2894 274 }
seyhmus.cacina 0:ac4dea3e2894 275
seyhmus.cacina 0:ac4dea3e2894 276 LPC_USB->USBCtrl = 0;
seyhmus.cacina 0:ac4dea3e2894 277
seyhmus.cacina 0:ac4dea3e2894 278 if ((endpoint >> 1) % 3 || (endpoint >> 1) == 0) {
seyhmus.cacina 0:ac4dea3e2894 279 SIEselectEndpoint(endpoint);
seyhmus.cacina 0:ac4dea3e2894 280 SIEclearBuffer();
seyhmus.cacina 0:ac4dea3e2894 281 }
seyhmus.cacina 0:ac4dea3e2894 282
seyhmus.cacina 0:ac4dea3e2894 283 return size;
seyhmus.cacina 0:ac4dea3e2894 284 }
seyhmus.cacina 0:ac4dea3e2894 285
seyhmus.cacina 0:ac4dea3e2894 286 static void endpointWritecore(uint8_t endpoint, uint8_t *buffer, uint32_t size) {
seyhmus.cacina 0:ac4dea3e2894 287 // Write to an IN endpoint
seyhmus.cacina 0:ac4dea3e2894 288 uint32_t temp, data;
seyhmus.cacina 0:ac4dea3e2894 289 uint8_t offset;
seyhmus.cacina 0:ac4dea3e2894 290
seyhmus.cacina 0:ac4dea3e2894 291 LPC_USB->USBCtrl = LOG_ENDPOINT(endpoint) | WR_EN;
seyhmus.cacina 0:ac4dea3e2894 292
seyhmus.cacina 0:ac4dea3e2894 293 LPC_USB->USBTxPLen = size;
seyhmus.cacina 0:ac4dea3e2894 294 offset = 0;
seyhmus.cacina 0:ac4dea3e2894 295 data = 0;
seyhmus.cacina 0:ac4dea3e2894 296
seyhmus.cacina 0:ac4dea3e2894 297 if (size>0) {
seyhmus.cacina 0:ac4dea3e2894 298 do {
seyhmus.cacina 0:ac4dea3e2894 299 // Fetch next data byte into a word-sized temporary variable
seyhmus.cacina 0:ac4dea3e2894 300 temp = *buffer++;
seyhmus.cacina 0:ac4dea3e2894 301
seyhmus.cacina 0:ac4dea3e2894 302 // Add to current data word
seyhmus.cacina 0:ac4dea3e2894 303 temp = temp << offset;
seyhmus.cacina 0:ac4dea3e2894 304 data = data | temp;
seyhmus.cacina 0:ac4dea3e2894 305
seyhmus.cacina 0:ac4dea3e2894 306 // move on to the next byte
seyhmus.cacina 0:ac4dea3e2894 307 offset = (offset + 8) % 32;
seyhmus.cacina 0:ac4dea3e2894 308 size--;
seyhmus.cacina 0:ac4dea3e2894 309
seyhmus.cacina 0:ac4dea3e2894 310 if ((offset==0) || (size==0)) {
seyhmus.cacina 0:ac4dea3e2894 311 // Write the word to the endpoint
seyhmus.cacina 0:ac4dea3e2894 312 LPC_USB->USBTxData = data;
seyhmus.cacina 0:ac4dea3e2894 313 data = 0;
seyhmus.cacina 0:ac4dea3e2894 314 }
seyhmus.cacina 0:ac4dea3e2894 315 } while (size>0);
seyhmus.cacina 0:ac4dea3e2894 316 } else {
seyhmus.cacina 0:ac4dea3e2894 317 LPC_USB->USBTxData = 0;
seyhmus.cacina 0:ac4dea3e2894 318 }
seyhmus.cacina 0:ac4dea3e2894 319
seyhmus.cacina 0:ac4dea3e2894 320 // Clear WR_EN to cover zero length packet case
seyhmus.cacina 0:ac4dea3e2894 321 LPC_USB->USBCtrl=0;
seyhmus.cacina 0:ac4dea3e2894 322
seyhmus.cacina 0:ac4dea3e2894 323 SIEselectEndpoint(endpoint);
seyhmus.cacina 0:ac4dea3e2894 324 SIEvalidateBuffer();
seyhmus.cacina 0:ac4dea3e2894 325 }
seyhmus.cacina 0:ac4dea3e2894 326
seyhmus.cacina 0:ac4dea3e2894 327 USBHAL::USBHAL(void) {
seyhmus.cacina 0:ac4dea3e2894 328 // Disable IRQ
seyhmus.cacina 0:ac4dea3e2894 329 NVIC_DisableIRQ(USB_IRQn);
seyhmus.cacina 0:ac4dea3e2894 330
seyhmus.cacina 0:ac4dea3e2894 331 // fill in callback array
seyhmus.cacina 0:ac4dea3e2894 332 epCallback[0] = &USBHAL::EP1_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 333 epCallback[1] = &USBHAL::EP1_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 334 epCallback[2] = &USBHAL::EP2_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 335 epCallback[3] = &USBHAL::EP2_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 336 epCallback[4] = &USBHAL::EP3_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 337 epCallback[5] = &USBHAL::EP3_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 338 epCallback[6] = &USBHAL::EP4_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 339 epCallback[7] = &USBHAL::EP4_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 340 epCallback[8] = &USBHAL::EP5_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 341 epCallback[9] = &USBHAL::EP5_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 342 epCallback[10] = &USBHAL::EP6_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 343 epCallback[11] = &USBHAL::EP6_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 344 epCallback[12] = &USBHAL::EP7_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 345 epCallback[13] = &USBHAL::EP7_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 346 epCallback[14] = &USBHAL::EP8_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 347 epCallback[15] = &USBHAL::EP8_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 348 epCallback[16] = &USBHAL::EP9_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 349 epCallback[17] = &USBHAL::EP9_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 350 epCallback[18] = &USBHAL::EP10_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 351 epCallback[19] = &USBHAL::EP10_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 352 epCallback[20] = &USBHAL::EP11_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 353 epCallback[21] = &USBHAL::EP11_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 354 epCallback[22] = &USBHAL::EP12_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 355 epCallback[23] = &USBHAL::EP12_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 356 epCallback[24] = &USBHAL::EP13_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 357 epCallback[25] = &USBHAL::EP13_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 358 epCallback[26] = &USBHAL::EP14_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 359 epCallback[27] = &USBHAL::EP14_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 360 epCallback[28] = &USBHAL::EP15_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 361 epCallback[29] = &USBHAL::EP15_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 362
seyhmus.cacina 0:ac4dea3e2894 363 // Enable power to USB device controller
seyhmus.cacina 0:ac4dea3e2894 364 LPC_SC->PCONP |= PCUSB;
seyhmus.cacina 0:ac4dea3e2894 365
seyhmus.cacina 0:ac4dea3e2894 366 // Enable USB clocks
seyhmus.cacina 0:ac4dea3e2894 367 LPC_USB->USBClkCtrl |= DEV_CLK_EN | AHB_CLK_EN;
seyhmus.cacina 0:ac4dea3e2894 368 while (LPC_USB->USBClkSt != (DEV_CLK_ON | AHB_CLK_ON));
seyhmus.cacina 0:ac4dea3e2894 369
seyhmus.cacina 0:ac4dea3e2894 370 // Configure pins P0.29 and P0.30 to be USB D+ and USB D-
seyhmus.cacina 0:ac4dea3e2894 371 LPC_PINCON->PINSEL1 &= 0xc3ffffff;
seyhmus.cacina 0:ac4dea3e2894 372 LPC_PINCON->PINSEL1 |= 0x14000000;
seyhmus.cacina 0:ac4dea3e2894 373
seyhmus.cacina 0:ac4dea3e2894 374 // Disconnect USB device
seyhmus.cacina 0:ac4dea3e2894 375 SIEdisconnect();
seyhmus.cacina 0:ac4dea3e2894 376
seyhmus.cacina 0:ac4dea3e2894 377 // Configure pin P2.9 to be Connect
seyhmus.cacina 0:ac4dea3e2894 378 LPC_PINCON->PINSEL4 &= 0xfffcffff;
seyhmus.cacina 0:ac4dea3e2894 379 LPC_PINCON->PINSEL4 |= 0x00040000;
seyhmus.cacina 0:ac4dea3e2894 380
seyhmus.cacina 0:ac4dea3e2894 381 // Connect must be low for at least 2.5uS
seyhmus.cacina 0:ac4dea3e2894 382 wait(0.3);
seyhmus.cacina 0:ac4dea3e2894 383
seyhmus.cacina 0:ac4dea3e2894 384 // Set the maximum packet size for the control endpoints
seyhmus.cacina 0:ac4dea3e2894 385 realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
seyhmus.cacina 0:ac4dea3e2894 386 realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
seyhmus.cacina 0:ac4dea3e2894 387
seyhmus.cacina 0:ac4dea3e2894 388 // Attach IRQ
seyhmus.cacina 0:ac4dea3e2894 389 instance = this;
seyhmus.cacina 0:ac4dea3e2894 390 NVIC_SetVector(USB_IRQn, (uint32_t)&_usbisr);
seyhmus.cacina 0:ac4dea3e2894 391
seyhmus.cacina 0:ac4dea3e2894 392 // Enable interrupts for device events and EP0
seyhmus.cacina 0:ac4dea3e2894 393 LPC_USB->USBDevIntEn = EP_SLOW | DEV_STAT | FRAME;
seyhmus.cacina 0:ac4dea3e2894 394 enableEndpointEvent(EP0IN);
seyhmus.cacina 0:ac4dea3e2894 395 enableEndpointEvent(EP0OUT);
seyhmus.cacina 0:ac4dea3e2894 396 }
seyhmus.cacina 0:ac4dea3e2894 397
seyhmus.cacina 0:ac4dea3e2894 398 USBHAL::~USBHAL(void) {
seyhmus.cacina 0:ac4dea3e2894 399 // Ensure device disconnected
seyhmus.cacina 0:ac4dea3e2894 400 SIEdisconnect();
seyhmus.cacina 0:ac4dea3e2894 401 // Disable USB interrupts
seyhmus.cacina 0:ac4dea3e2894 402 NVIC_DisableIRQ(USB_IRQn);
seyhmus.cacina 0:ac4dea3e2894 403 }
seyhmus.cacina 0:ac4dea3e2894 404
seyhmus.cacina 0:ac4dea3e2894 405 void USBHAL::connect(void) {
seyhmus.cacina 0:ac4dea3e2894 406 NVIC_EnableIRQ(USB_IRQn);
seyhmus.cacina 0:ac4dea3e2894 407 // Connect USB device
seyhmus.cacina 0:ac4dea3e2894 408 SIEconnect();
seyhmus.cacina 0:ac4dea3e2894 409 }
seyhmus.cacina 0:ac4dea3e2894 410
seyhmus.cacina 0:ac4dea3e2894 411 void USBHAL::disconnect(void) {
seyhmus.cacina 0:ac4dea3e2894 412 NVIC_DisableIRQ(USB_IRQn);
seyhmus.cacina 0:ac4dea3e2894 413 // Disconnect USB device
seyhmus.cacina 0:ac4dea3e2894 414 SIEdisconnect();
seyhmus.cacina 0:ac4dea3e2894 415 }
seyhmus.cacina 0:ac4dea3e2894 416
seyhmus.cacina 0:ac4dea3e2894 417 void USBHAL::configureDevice(void) {
seyhmus.cacina 0:ac4dea3e2894 418 SIEconfigureDevice();
seyhmus.cacina 0:ac4dea3e2894 419 }
seyhmus.cacina 0:ac4dea3e2894 420
seyhmus.cacina 0:ac4dea3e2894 421 void USBHAL::unconfigureDevice(void) {
seyhmus.cacina 0:ac4dea3e2894 422 SIEunconfigureDevice();
seyhmus.cacina 0:ac4dea3e2894 423 }
seyhmus.cacina 0:ac4dea3e2894 424
seyhmus.cacina 0:ac4dea3e2894 425 void USBHAL::setAddress(uint8_t address) {
seyhmus.cacina 0:ac4dea3e2894 426 SIEsetAddress(address);
seyhmus.cacina 0:ac4dea3e2894 427 }
seyhmus.cacina 0:ac4dea3e2894 428
seyhmus.cacina 0:ac4dea3e2894 429 void USBHAL::EP0setup(uint8_t *buffer) {
seyhmus.cacina 0:ac4dea3e2894 430 endpointReadcore(EP0OUT, buffer);
seyhmus.cacina 0:ac4dea3e2894 431 }
seyhmus.cacina 0:ac4dea3e2894 432
seyhmus.cacina 0:ac4dea3e2894 433 void USBHAL::EP0read(void) {
seyhmus.cacina 0:ac4dea3e2894 434 // Not required
seyhmus.cacina 0:ac4dea3e2894 435 }
seyhmus.cacina 0:ac4dea3e2894 436
seyhmus.cacina 0:ac4dea3e2894 437 void USBHAL::EP0readStage(void) {
seyhmus.cacina 0:ac4dea3e2894 438 // Not required
seyhmus.cacina 0:ac4dea3e2894 439 }
seyhmus.cacina 0:ac4dea3e2894 440
seyhmus.cacina 0:ac4dea3e2894 441 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
seyhmus.cacina 0:ac4dea3e2894 442 return endpointReadcore(EP0OUT, buffer);
seyhmus.cacina 0:ac4dea3e2894 443 }
seyhmus.cacina 0:ac4dea3e2894 444
seyhmus.cacina 0:ac4dea3e2894 445 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
seyhmus.cacina 0:ac4dea3e2894 446 endpointWritecore(EP0IN, buffer, size);
seyhmus.cacina 0:ac4dea3e2894 447 }
seyhmus.cacina 0:ac4dea3e2894 448
seyhmus.cacina 0:ac4dea3e2894 449 void USBHAL::EP0getWriteResult(void) {
seyhmus.cacina 0:ac4dea3e2894 450 // Not required
seyhmus.cacina 0:ac4dea3e2894 451 }
seyhmus.cacina 0:ac4dea3e2894 452
seyhmus.cacina 0:ac4dea3e2894 453 void USBHAL::EP0stall(void) {
seyhmus.cacina 0:ac4dea3e2894 454 // This will stall both control endpoints
seyhmus.cacina 0:ac4dea3e2894 455 stallEndpoint(EP0OUT);
seyhmus.cacina 0:ac4dea3e2894 456 }
seyhmus.cacina 0:ac4dea3e2894 457
seyhmus.cacina 0:ac4dea3e2894 458 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
seyhmus.cacina 0:ac4dea3e2894 459 return EP_PENDING;
seyhmus.cacina 0:ac4dea3e2894 460 }
seyhmus.cacina 0:ac4dea3e2894 461
seyhmus.cacina 0:ac4dea3e2894 462 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
seyhmus.cacina 0:ac4dea3e2894 463
seyhmus.cacina 0:ac4dea3e2894 464 //for isochronous endpoint, we don't wait an interrupt
seyhmus.cacina 0:ac4dea3e2894 465 if ((endpoint >> 1) % 3 || (endpoint >> 1) == 0) {
seyhmus.cacina 0:ac4dea3e2894 466 if (!(epComplete & EP(endpoint)))
seyhmus.cacina 0:ac4dea3e2894 467 return EP_PENDING;
seyhmus.cacina 0:ac4dea3e2894 468 }
seyhmus.cacina 0:ac4dea3e2894 469
seyhmus.cacina 0:ac4dea3e2894 470 *bytesRead = endpointReadcore(endpoint, buffer);
seyhmus.cacina 0:ac4dea3e2894 471 epComplete &= ~EP(endpoint);
seyhmus.cacina 0:ac4dea3e2894 472 return EP_COMPLETED;
seyhmus.cacina 0:ac4dea3e2894 473 }
seyhmus.cacina 0:ac4dea3e2894 474
seyhmus.cacina 0:ac4dea3e2894 475 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
seyhmus.cacina 0:ac4dea3e2894 476 if (getEndpointStallState(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 477 return EP_STALLED;
seyhmus.cacina 0:ac4dea3e2894 478 }
seyhmus.cacina 0:ac4dea3e2894 479
seyhmus.cacina 0:ac4dea3e2894 480 epComplete &= ~EP(endpoint);
seyhmus.cacina 0:ac4dea3e2894 481
seyhmus.cacina 0:ac4dea3e2894 482 endpointWritecore(endpoint, data, size);
seyhmus.cacina 0:ac4dea3e2894 483 return EP_PENDING;
seyhmus.cacina 0:ac4dea3e2894 484 }
seyhmus.cacina 0:ac4dea3e2894 485
seyhmus.cacina 0:ac4dea3e2894 486 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
seyhmus.cacina 0:ac4dea3e2894 487 if (epComplete & EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 488 epComplete &= ~EP(endpoint);
seyhmus.cacina 0:ac4dea3e2894 489 return EP_COMPLETED;
seyhmus.cacina 0:ac4dea3e2894 490 }
seyhmus.cacina 0:ac4dea3e2894 491
seyhmus.cacina 0:ac4dea3e2894 492 return EP_PENDING;
seyhmus.cacina 0:ac4dea3e2894 493 }
seyhmus.cacina 0:ac4dea3e2894 494
seyhmus.cacina 0:ac4dea3e2894 495 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) {
seyhmus.cacina 0:ac4dea3e2894 496 // Realise an endpoint
seyhmus.cacina 0:ac4dea3e2894 497 LPC_USB->USBDevIntClr = EP_RLZED;
seyhmus.cacina 0:ac4dea3e2894 498 LPC_USB->USBReEp |= EP(endpoint);
seyhmus.cacina 0:ac4dea3e2894 499 LPC_USB->USBEpInd = endpoint;
seyhmus.cacina 0:ac4dea3e2894 500 LPC_USB->USBMaxPSize = maxPacket;
seyhmus.cacina 0:ac4dea3e2894 501
seyhmus.cacina 0:ac4dea3e2894 502 while (!(LPC_USB->USBDevIntSt & EP_RLZED));
seyhmus.cacina 0:ac4dea3e2894 503 LPC_USB->USBDevIntClr = EP_RLZED;
seyhmus.cacina 0:ac4dea3e2894 504
seyhmus.cacina 0:ac4dea3e2894 505 // Clear stall state
seyhmus.cacina 0:ac4dea3e2894 506 endpointStallState &= ~EP(endpoint);
seyhmus.cacina 0:ac4dea3e2894 507
seyhmus.cacina 0:ac4dea3e2894 508 enableEndpointEvent(endpoint);
seyhmus.cacina 0:ac4dea3e2894 509 return true;
seyhmus.cacina 0:ac4dea3e2894 510 }
seyhmus.cacina 0:ac4dea3e2894 511
seyhmus.cacina 0:ac4dea3e2894 512 void USBHAL::stallEndpoint(uint8_t endpoint) {
seyhmus.cacina 0:ac4dea3e2894 513 // Stall an endpoint
seyhmus.cacina 0:ac4dea3e2894 514 if ( (endpoint==EP0IN) || (endpoint==EP0OUT) ) {
seyhmus.cacina 0:ac4dea3e2894 515 // Conditionally stall both control endpoints
seyhmus.cacina 0:ac4dea3e2894 516 SIEsetEndpointStatus(EP0OUT, SIE_SES_CND_ST);
seyhmus.cacina 0:ac4dea3e2894 517 } else {
seyhmus.cacina 0:ac4dea3e2894 518 SIEsetEndpointStatus(endpoint, SIE_SES_ST);
seyhmus.cacina 0:ac4dea3e2894 519
seyhmus.cacina 0:ac4dea3e2894 520 // Update stall state
seyhmus.cacina 0:ac4dea3e2894 521 endpointStallState |= EP(endpoint);
seyhmus.cacina 0:ac4dea3e2894 522 }
seyhmus.cacina 0:ac4dea3e2894 523 }
seyhmus.cacina 0:ac4dea3e2894 524
seyhmus.cacina 0:ac4dea3e2894 525 void USBHAL::unstallEndpoint(uint8_t endpoint) {
seyhmus.cacina 0:ac4dea3e2894 526 // Unstall an endpoint. The endpoint will also be reinitialised
seyhmus.cacina 0:ac4dea3e2894 527 SIEsetEndpointStatus(endpoint, 0);
seyhmus.cacina 0:ac4dea3e2894 528
seyhmus.cacina 0:ac4dea3e2894 529 // Update stall state
seyhmus.cacina 0:ac4dea3e2894 530 endpointStallState &= ~EP(endpoint);
seyhmus.cacina 0:ac4dea3e2894 531 }
seyhmus.cacina 0:ac4dea3e2894 532
seyhmus.cacina 0:ac4dea3e2894 533 bool USBHAL::getEndpointStallState(uint8_t endpoint) {
seyhmus.cacina 0:ac4dea3e2894 534 // Returns true if endpoint stalled
seyhmus.cacina 0:ac4dea3e2894 535 return endpointStallState & EP(endpoint);
seyhmus.cacina 0:ac4dea3e2894 536 }
seyhmus.cacina 0:ac4dea3e2894 537
seyhmus.cacina 0:ac4dea3e2894 538 void USBHAL::remoteWakeup(void) {
seyhmus.cacina 0:ac4dea3e2894 539 // Remote wakeup
seyhmus.cacina 0:ac4dea3e2894 540 uint8_t status;
seyhmus.cacina 0:ac4dea3e2894 541
seyhmus.cacina 0:ac4dea3e2894 542 // Enable USB clocks
seyhmus.cacina 0:ac4dea3e2894 543 LPC_USB->USBClkCtrl |= DEV_CLK_EN | AHB_CLK_EN;
seyhmus.cacina 0:ac4dea3e2894 544 while (LPC_USB->USBClkSt != (DEV_CLK_ON | AHB_CLK_ON));
seyhmus.cacina 0:ac4dea3e2894 545
seyhmus.cacina 0:ac4dea3e2894 546 status = SIEgetDeviceStatus();
seyhmus.cacina 0:ac4dea3e2894 547 SIEsetDeviceStatus(status & ~SIE_DS_SUS);
seyhmus.cacina 0:ac4dea3e2894 548 }
seyhmus.cacina 0:ac4dea3e2894 549
seyhmus.cacina 0:ac4dea3e2894 550 void USBHAL::_usbisr(void) {
seyhmus.cacina 0:ac4dea3e2894 551 instance->usbisr();
seyhmus.cacina 0:ac4dea3e2894 552 }
seyhmus.cacina 0:ac4dea3e2894 553
seyhmus.cacina 0:ac4dea3e2894 554
seyhmus.cacina 0:ac4dea3e2894 555 void USBHAL::usbisr(void) {
seyhmus.cacina 0:ac4dea3e2894 556 uint8_t devStat;
seyhmus.cacina 0:ac4dea3e2894 557
seyhmus.cacina 0:ac4dea3e2894 558 if (LPC_USB->USBDevIntSt & FRAME) {
seyhmus.cacina 0:ac4dea3e2894 559 // Start of frame event
seyhmus.cacina 0:ac4dea3e2894 560 SOF(SIEgetFrameNumber());
seyhmus.cacina 0:ac4dea3e2894 561 // Clear interrupt status flag
seyhmus.cacina 0:ac4dea3e2894 562 LPC_USB->USBDevIntClr = FRAME;
seyhmus.cacina 0:ac4dea3e2894 563 }
seyhmus.cacina 0:ac4dea3e2894 564
seyhmus.cacina 0:ac4dea3e2894 565 if (LPC_USB->USBDevIntSt & DEV_STAT) {
seyhmus.cacina 0:ac4dea3e2894 566 // Device Status interrupt
seyhmus.cacina 0:ac4dea3e2894 567 // Must clear the interrupt status flag before reading the device status from the SIE
seyhmus.cacina 0:ac4dea3e2894 568 LPC_USB->USBDevIntClr = DEV_STAT;
seyhmus.cacina 0:ac4dea3e2894 569
seyhmus.cacina 0:ac4dea3e2894 570 // Read device status from SIE
seyhmus.cacina 0:ac4dea3e2894 571 devStat = SIEgetDeviceStatus();
seyhmus.cacina 0:ac4dea3e2894 572 //printf("devStat: %d\r\n", devStat);
seyhmus.cacina 0:ac4dea3e2894 573
seyhmus.cacina 0:ac4dea3e2894 574 if (devStat & SIE_DS_SUS_CH) {
seyhmus.cacina 0:ac4dea3e2894 575 // Suspend status changed
seyhmus.cacina 0:ac4dea3e2894 576 if((devStat & SIE_DS_SUS) != 0) {
seyhmus.cacina 0:ac4dea3e2894 577 suspendStateChanged(0);
seyhmus.cacina 0:ac4dea3e2894 578 }
seyhmus.cacina 0:ac4dea3e2894 579 }
seyhmus.cacina 0:ac4dea3e2894 580
seyhmus.cacina 0:ac4dea3e2894 581 if (devStat & SIE_DS_RST) {
seyhmus.cacina 0:ac4dea3e2894 582 // Bus reset
seyhmus.cacina 0:ac4dea3e2894 583 if((devStat & SIE_DS_SUS) == 0) {
seyhmus.cacina 0:ac4dea3e2894 584 suspendStateChanged(1);
seyhmus.cacina 0:ac4dea3e2894 585 }
seyhmus.cacina 0:ac4dea3e2894 586 busReset();
seyhmus.cacina 0:ac4dea3e2894 587 }
seyhmus.cacina 0:ac4dea3e2894 588 }
seyhmus.cacina 0:ac4dea3e2894 589
seyhmus.cacina 0:ac4dea3e2894 590 if (LPC_USB->USBDevIntSt & EP_SLOW) {
seyhmus.cacina 0:ac4dea3e2894 591 // (Slow) Endpoint Interrupt
seyhmus.cacina 0:ac4dea3e2894 592
seyhmus.cacina 0:ac4dea3e2894 593 // Process each endpoint interrupt
seyhmus.cacina 0:ac4dea3e2894 594 if (LPC_USB->USBEpIntSt & EP(EP0OUT)) {
seyhmus.cacina 0:ac4dea3e2894 595 if (selectEndpointClearInterrupt(EP0OUT) & SIE_SE_STP) {
seyhmus.cacina 0:ac4dea3e2894 596 // this is a setup packet
seyhmus.cacina 0:ac4dea3e2894 597 EP0setupCallback();
seyhmus.cacina 0:ac4dea3e2894 598 } else {
seyhmus.cacina 0:ac4dea3e2894 599 EP0out();
seyhmus.cacina 0:ac4dea3e2894 600 }
seyhmus.cacina 0:ac4dea3e2894 601 LPC_USB->USBDevIntClr = EP_SLOW;
seyhmus.cacina 0:ac4dea3e2894 602 }
seyhmus.cacina 0:ac4dea3e2894 603
seyhmus.cacina 0:ac4dea3e2894 604 if (LPC_USB->USBEpIntSt & EP(EP0IN)) {
seyhmus.cacina 0:ac4dea3e2894 605 selectEndpointClearInterrupt(EP0IN);
seyhmus.cacina 0:ac4dea3e2894 606 LPC_USB->USBDevIntClr = EP_SLOW;
seyhmus.cacina 0:ac4dea3e2894 607 EP0in();
seyhmus.cacina 0:ac4dea3e2894 608 }
seyhmus.cacina 0:ac4dea3e2894 609
seyhmus.cacina 0:ac4dea3e2894 610 for (uint8_t num = 2; num < 16*2; num++) {
seyhmus.cacina 0:ac4dea3e2894 611 if (LPC_USB->USBEpIntSt & EP(num)) {
seyhmus.cacina 0:ac4dea3e2894 612 selectEndpointClearInterrupt(num);
seyhmus.cacina 0:ac4dea3e2894 613 epComplete |= EP(num);
seyhmus.cacina 0:ac4dea3e2894 614 LPC_USB->USBDevIntClr = EP_SLOW;
seyhmus.cacina 0:ac4dea3e2894 615 if ((instance->*(epCallback[num - 2]))()) {
seyhmus.cacina 0:ac4dea3e2894 616 epComplete &= ~EP(num);
seyhmus.cacina 0:ac4dea3e2894 617 }
seyhmus.cacina 0:ac4dea3e2894 618 }
seyhmus.cacina 0:ac4dea3e2894 619 }
seyhmus.cacina 0:ac4dea3e2894 620 }
seyhmus.cacina 0:ac4dea3e2894 621 }
seyhmus.cacina 0:ac4dea3e2894 622
seyhmus.cacina 0:ac4dea3e2894 623 #endif