Maxim Integrated / Mbed OS Host_Software_MAX32664GWEB_HR_EXTENDED

ME11B Sample Code in Maxim Integrated Team

Dependencies:   BMI160 max32630hsp3 MemoryLCD USBDevice

Fork of Host_Software_MAX32664GWEB_HR_EXTENDED by Seyhmus Cacina

Drivers/USBDevice/USBDevice/USBHAL_KL25Z.cpp@0:ac4dea3e2894, 2019-03-18 (annotated)

Committer:
seyhmus.cacina
Date:
Mon Mar 18 10:21:53 2019 +0300
Revision:
0:ac4dea3e2894
ME11B Sample Code First Commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
seyhmus.cacina 0:ac4dea3e2894 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
seyhmus.cacina 0:ac4dea3e2894 2 *
seyhmus.cacina 0:ac4dea3e2894 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
seyhmus.cacina 0:ac4dea3e2894 4 * and associated documentation files (the "Software"), to deal in the Software without
seyhmus.cacina 0:ac4dea3e2894 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
seyhmus.cacina 0:ac4dea3e2894 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
seyhmus.cacina 0:ac4dea3e2894 7 * Software is furnished to do so, subject to the following conditions:
seyhmus.cacina 0:ac4dea3e2894 8 *
seyhmus.cacina 0:ac4dea3e2894 9 * The above copyright notice and this permission notice shall be included in all copies or
seyhmus.cacina 0:ac4dea3e2894 10 * substantial portions of the Software.
seyhmus.cacina 0:ac4dea3e2894 11 *
seyhmus.cacina 0:ac4dea3e2894 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
seyhmus.cacina 0:ac4dea3e2894 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
seyhmus.cacina 0:ac4dea3e2894 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
seyhmus.cacina 0:ac4dea3e2894 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
seyhmus.cacina 0:ac4dea3e2894 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
seyhmus.cacina 0:ac4dea3e2894 17 */
seyhmus.cacina 0:ac4dea3e2894 18
seyhmus.cacina 0:ac4dea3e2894 19 #if defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D50M) | defined(TARGET_K64F) | defined(TARGET_K22F) | defined(TARGET_TEENSY3_1)
seyhmus.cacina 0:ac4dea3e2894 20
seyhmus.cacina 0:ac4dea3e2894 21 #include "USBHAL.h"
seyhmus.cacina 0:ac4dea3e2894 22
seyhmus.cacina 0:ac4dea3e2894 23 USBHAL * USBHAL::instance;
seyhmus.cacina 0:ac4dea3e2894 24
seyhmus.cacina 0:ac4dea3e2894 25 static volatile int epComplete = 0;
seyhmus.cacina 0:ac4dea3e2894 26
seyhmus.cacina 0:ac4dea3e2894 27 // Convert physical endpoint number to register bit
seyhmus.cacina 0:ac4dea3e2894 28 #define EP(endpoint) (1<<(endpoint))
seyhmus.cacina 0:ac4dea3e2894 29
seyhmus.cacina 0:ac4dea3e2894 30 // Convert physical to logical
seyhmus.cacina 0:ac4dea3e2894 31 #define PHY_TO_LOG(endpoint) ((endpoint)>>1)
seyhmus.cacina 0:ac4dea3e2894 32
seyhmus.cacina 0:ac4dea3e2894 33 // Get endpoint direction
seyhmus.cacina 0:ac4dea3e2894 34 #define IN_EP(endpoint) ((endpoint) & 1U ? true : false)
seyhmus.cacina 0:ac4dea3e2894 35 #define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
seyhmus.cacina 0:ac4dea3e2894 36
seyhmus.cacina 0:ac4dea3e2894 37 #define BD_OWN_MASK (1<<7)
seyhmus.cacina 0:ac4dea3e2894 38 #define BD_DATA01_MASK (1<<6)
seyhmus.cacina 0:ac4dea3e2894 39 #define BD_KEEP_MASK (1<<5)
seyhmus.cacina 0:ac4dea3e2894 40 #define BD_NINC_MASK (1<<4)
seyhmus.cacina 0:ac4dea3e2894 41 #define BD_DTS_MASK (1<<3)
seyhmus.cacina 0:ac4dea3e2894 42 #define BD_STALL_MASK (1<<2)
seyhmus.cacina 0:ac4dea3e2894 43
seyhmus.cacina 0:ac4dea3e2894 44 #define TX 1
seyhmus.cacina 0:ac4dea3e2894 45 #define RX 0
seyhmus.cacina 0:ac4dea3e2894 46 #define ODD 0
seyhmus.cacina 0:ac4dea3e2894 47 #define EVEN 1
seyhmus.cacina 0:ac4dea3e2894 48 // this macro waits a physical endpoint number
seyhmus.cacina 0:ac4dea3e2894 49 #define EP_BDT_IDX(ep, dir, odd) (((ep * 4) + (2 * dir) + (1 * odd)))
seyhmus.cacina 0:ac4dea3e2894 50
seyhmus.cacina 0:ac4dea3e2894 51 #define SETUP_TOKEN 0x0D
seyhmus.cacina 0:ac4dea3e2894 52 #define IN_TOKEN 0x09
seyhmus.cacina 0:ac4dea3e2894 53 #define OUT_TOKEN 0x01
seyhmus.cacina 0:ac4dea3e2894 54 #define TOK_PID(idx) ((bdt[idx].info >> 2) & 0x0F)
seyhmus.cacina 0:ac4dea3e2894 55
seyhmus.cacina 0:ac4dea3e2894 56 // for each endpt: 8 bytes
seyhmus.cacina 0:ac4dea3e2894 57 typedef struct BDT {
seyhmus.cacina 0:ac4dea3e2894 58 uint8_t info; // BD[0:7]
seyhmus.cacina 0:ac4dea3e2894 59 uint8_t dummy; // RSVD: BD[8:15]
seyhmus.cacina 0:ac4dea3e2894 60 uint16_t byte_count; // BD[16:32]
seyhmus.cacina 0:ac4dea3e2894 61 uint32_t address; // Addr
seyhmus.cacina 0:ac4dea3e2894 62 } BDT;
seyhmus.cacina 0:ac4dea3e2894 63
seyhmus.cacina 0:ac4dea3e2894 64
seyhmus.cacina 0:ac4dea3e2894 65 // there are:
seyhmus.cacina 0:ac4dea3e2894 66 // * 16 bidirectionnal endpt -> 32 physical endpt
seyhmus.cacina 0:ac4dea3e2894 67 // * as there are ODD and EVEN buffer -> 32*2 bdt
seyhmus.cacina 0:ac4dea3e2894 68 __attribute__((__aligned__(512))) BDT bdt[NUMBER_OF_PHYSICAL_ENDPOINTS * 2];
seyhmus.cacina 0:ac4dea3e2894 69 uint8_t * endpoint_buffer[(NUMBER_OF_PHYSICAL_ENDPOINTS - 2) * 2];
seyhmus.cacina 0:ac4dea3e2894 70 uint8_t * endpoint_buffer_iso[2*2];
seyhmus.cacina 0:ac4dea3e2894 71
seyhmus.cacina 0:ac4dea3e2894 72 static uint8_t set_addr = 0;
seyhmus.cacina 0:ac4dea3e2894 73 static uint8_t addr = 0;
seyhmus.cacina 0:ac4dea3e2894 74
seyhmus.cacina 0:ac4dea3e2894 75 static uint32_t Data1 = 0x55555555;
seyhmus.cacina 0:ac4dea3e2894 76
seyhmus.cacina 0:ac4dea3e2894 77 static uint32_t frameNumber() {
seyhmus.cacina 0:ac4dea3e2894 78 return((USB0->FRMNUML | (USB0->FRMNUMH << 8)) & 0x07FF);
seyhmus.cacina 0:ac4dea3e2894 79 }
seyhmus.cacina 0:ac4dea3e2894 80
seyhmus.cacina 0:ac4dea3e2894 81 uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
seyhmus.cacina 0:ac4dea3e2894 82 return 0;
seyhmus.cacina 0:ac4dea3e2894 83 }
seyhmus.cacina 0:ac4dea3e2894 84
seyhmus.cacina 0:ac4dea3e2894 85 USBHAL::USBHAL(void) {
seyhmus.cacina 0:ac4dea3e2894 86 // Disable IRQ
seyhmus.cacina 0:ac4dea3e2894 87 NVIC_DisableIRQ(USB0_IRQn);
seyhmus.cacina 0:ac4dea3e2894 88
seyhmus.cacina 0:ac4dea3e2894 89 #if defined(TARGET_K64F)
seyhmus.cacina 0:ac4dea3e2894 90 MPU->CESR=0;
seyhmus.cacina 0:ac4dea3e2894 91 #endif
seyhmus.cacina 0:ac4dea3e2894 92 // fill in callback array
seyhmus.cacina 0:ac4dea3e2894 93 epCallback[0] = &USBHAL::EP1_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 94 epCallback[1] = &USBHAL::EP1_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 95 epCallback[2] = &USBHAL::EP2_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 96 epCallback[3] = &USBHAL::EP2_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 97 epCallback[4] = &USBHAL::EP3_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 98 epCallback[5] = &USBHAL::EP3_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 99 epCallback[6] = &USBHAL::EP4_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 100 epCallback[7] = &USBHAL::EP4_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 101 epCallback[8] = &USBHAL::EP5_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 102 epCallback[9] = &USBHAL::EP5_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 103 epCallback[10] = &USBHAL::EP6_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 104 epCallback[11] = &USBHAL::EP6_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 105 epCallback[12] = &USBHAL::EP7_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 106 epCallback[13] = &USBHAL::EP7_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 107 epCallback[14] = &USBHAL::EP8_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 108 epCallback[15] = &USBHAL::EP8_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 109 epCallback[16] = &USBHAL::EP9_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 110 epCallback[17] = &USBHAL::EP9_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 111 epCallback[18] = &USBHAL::EP10_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 112 epCallback[19] = &USBHAL::EP10_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 113 epCallback[20] = &USBHAL::EP11_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 114 epCallback[21] = &USBHAL::EP11_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 115 epCallback[22] = &USBHAL::EP12_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 116 epCallback[23] = &USBHAL::EP12_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 117 epCallback[24] = &USBHAL::EP13_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 118 epCallback[25] = &USBHAL::EP13_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 119 epCallback[26] = &USBHAL::EP14_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 120 epCallback[27] = &USBHAL::EP14_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 121 epCallback[28] = &USBHAL::EP15_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 122 epCallback[29] = &USBHAL::EP15_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 123
seyhmus.cacina 0:ac4dea3e2894 124 #if defined(TARGET_KL43Z)
seyhmus.cacina 0:ac4dea3e2894 125 // enable USBFS clock
seyhmus.cacina 0:ac4dea3e2894 126 SIM->SCGC4 |= SIM_SCGC4_USBFS_MASK;
seyhmus.cacina 0:ac4dea3e2894 127
seyhmus.cacina 0:ac4dea3e2894 128 // enable the IRC48M clock
seyhmus.cacina 0:ac4dea3e2894 129 USB0->CLK_RECOVER_IRC_EN |= USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK;
seyhmus.cacina 0:ac4dea3e2894 130
seyhmus.cacina 0:ac4dea3e2894 131 // enable the USB clock recovery tuning
seyhmus.cacina 0:ac4dea3e2894 132 USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
seyhmus.cacina 0:ac4dea3e2894 133
seyhmus.cacina 0:ac4dea3e2894 134 // choose usb src clock
seyhmus.cacina 0:ac4dea3e2894 135 SIM->SOPT2 |= SIM_SOPT2_USBSRC_MASK;
seyhmus.cacina 0:ac4dea3e2894 136 #else
seyhmus.cacina 0:ac4dea3e2894 137 // choose usb src as PLL
seyhmus.cacina 0:ac4dea3e2894 138 SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK;
seyhmus.cacina 0:ac4dea3e2894 139 SIM->SOPT2 |= (SIM_SOPT2_USBSRC_MASK | (1 << SIM_SOPT2_PLLFLLSEL_SHIFT));
seyhmus.cacina 0:ac4dea3e2894 140
seyhmus.cacina 0:ac4dea3e2894 141 // enable OTG clock
seyhmus.cacina 0:ac4dea3e2894 142 SIM->SCGC4 |= SIM_SCGC4_USBOTG_MASK;
seyhmus.cacina 0:ac4dea3e2894 143 #endif
seyhmus.cacina 0:ac4dea3e2894 144
seyhmus.cacina 0:ac4dea3e2894 145 // Attach IRQ
seyhmus.cacina 0:ac4dea3e2894 146 instance = this;
seyhmus.cacina 0:ac4dea3e2894 147 NVIC_SetVector(USB0_IRQn, (uint32_t)&_usbisr);
seyhmus.cacina 0:ac4dea3e2894 148 NVIC_EnableIRQ(USB0_IRQn);
seyhmus.cacina 0:ac4dea3e2894 149
seyhmus.cacina 0:ac4dea3e2894 150 // USB Module Configuration
seyhmus.cacina 0:ac4dea3e2894 151 // Reset USB Module
seyhmus.cacina 0:ac4dea3e2894 152 USB0->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
seyhmus.cacina 0:ac4dea3e2894 153 while(USB0->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
seyhmus.cacina 0:ac4dea3e2894 154
seyhmus.cacina 0:ac4dea3e2894 155 // Set BDT Base Register
seyhmus.cacina 0:ac4dea3e2894 156 USB0->BDTPAGE1 = (uint8_t)((uint32_t)bdt>>8);
seyhmus.cacina 0:ac4dea3e2894 157 USB0->BDTPAGE2 = (uint8_t)((uint32_t)bdt>>16);
seyhmus.cacina 0:ac4dea3e2894 158 USB0->BDTPAGE3 = (uint8_t)((uint32_t)bdt>>24);
seyhmus.cacina 0:ac4dea3e2894 159
seyhmus.cacina 0:ac4dea3e2894 160 // Clear interrupt flag
seyhmus.cacina 0:ac4dea3e2894 161 USB0->ISTAT = 0xff;
seyhmus.cacina 0:ac4dea3e2894 162
seyhmus.cacina 0:ac4dea3e2894 163 // USB Interrupt Enablers
seyhmus.cacina 0:ac4dea3e2894 164 USB0->INTEN |= USB_INTEN_TOKDNEEN_MASK |
seyhmus.cacina 0:ac4dea3e2894 165 USB_INTEN_SOFTOKEN_MASK |
seyhmus.cacina 0:ac4dea3e2894 166 USB_INTEN_ERROREN_MASK |
seyhmus.cacina 0:ac4dea3e2894 167 USB_INTEN_USBRSTEN_MASK;
seyhmus.cacina 0:ac4dea3e2894 168
seyhmus.cacina 0:ac4dea3e2894 169 // Disable weak pull downs
seyhmus.cacina 0:ac4dea3e2894 170 USB0->USBCTRL &= ~(USB_USBCTRL_PDE_MASK | USB_USBCTRL_SUSP_MASK);
seyhmus.cacina 0:ac4dea3e2894 171
seyhmus.cacina 0:ac4dea3e2894 172 USB0->USBTRC0 |= 0x40;
seyhmus.cacina 0:ac4dea3e2894 173 }
seyhmus.cacina 0:ac4dea3e2894 174
seyhmus.cacina 0:ac4dea3e2894 175 USBHAL::~USBHAL(void) { }
seyhmus.cacina 0:ac4dea3e2894 176
seyhmus.cacina 0:ac4dea3e2894 177 void USBHAL::connect(void) {
seyhmus.cacina 0:ac4dea3e2894 178 // enable USB
seyhmus.cacina 0:ac4dea3e2894 179 USB0->CTL |= USB_CTL_USBENSOFEN_MASK;
seyhmus.cacina 0:ac4dea3e2894 180 // Pull up enable
seyhmus.cacina 0:ac4dea3e2894 181 USB0->CONTROL |= USB_CONTROL_DPPULLUPNONOTG_MASK;
seyhmus.cacina 0:ac4dea3e2894 182 }
seyhmus.cacina 0:ac4dea3e2894 183
seyhmus.cacina 0:ac4dea3e2894 184 void USBHAL::disconnect(void) {
seyhmus.cacina 0:ac4dea3e2894 185 // disable USB
seyhmus.cacina 0:ac4dea3e2894 186 USB0->CTL &= ~USB_CTL_USBENSOFEN_MASK;
seyhmus.cacina 0:ac4dea3e2894 187 // Pull up disable
seyhmus.cacina 0:ac4dea3e2894 188 USB0->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK;
seyhmus.cacina 0:ac4dea3e2894 189
seyhmus.cacina 0:ac4dea3e2894 190 //Free buffers if required:
seyhmus.cacina 0:ac4dea3e2894 191 for (int i = 0; i<(NUMBER_OF_PHYSICAL_ENDPOINTS - 2) * 2; i++) {
seyhmus.cacina 0:ac4dea3e2894 192 free(endpoint_buffer[i]);
seyhmus.cacina 0:ac4dea3e2894 193 endpoint_buffer[i] = NULL;
seyhmus.cacina 0:ac4dea3e2894 194 }
seyhmus.cacina 0:ac4dea3e2894 195 free(endpoint_buffer_iso[2]);
seyhmus.cacina 0:ac4dea3e2894 196 endpoint_buffer_iso[2] = NULL;
seyhmus.cacina 0:ac4dea3e2894 197 free(endpoint_buffer_iso[0]);
seyhmus.cacina 0:ac4dea3e2894 198 endpoint_buffer_iso[0] = NULL;
seyhmus.cacina 0:ac4dea3e2894 199 }
seyhmus.cacina 0:ac4dea3e2894 200
seyhmus.cacina 0:ac4dea3e2894 201 void USBHAL::configureDevice(void) {
seyhmus.cacina 0:ac4dea3e2894 202 // not needed
seyhmus.cacina 0:ac4dea3e2894 203 }
seyhmus.cacina 0:ac4dea3e2894 204
seyhmus.cacina 0:ac4dea3e2894 205 void USBHAL::unconfigureDevice(void) {
seyhmus.cacina 0:ac4dea3e2894 206 // not needed
seyhmus.cacina 0:ac4dea3e2894 207 }
seyhmus.cacina 0:ac4dea3e2894 208
seyhmus.cacina 0:ac4dea3e2894 209 void USBHAL::setAddress(uint8_t address) {
seyhmus.cacina 0:ac4dea3e2894 210 // we don't set the address now otherwise the usb controller does not ack
seyhmus.cacina 0:ac4dea3e2894 211 // we set a flag instead
seyhmus.cacina 0:ac4dea3e2894 212 // see usbisr when an IN token is received
seyhmus.cacina 0:ac4dea3e2894 213 set_addr = 1;
seyhmus.cacina 0:ac4dea3e2894 214 addr = address;
seyhmus.cacina 0:ac4dea3e2894 215 }
seyhmus.cacina 0:ac4dea3e2894 216
seyhmus.cacina 0:ac4dea3e2894 217 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) {
seyhmus.cacina 0:ac4dea3e2894 218 uint32_t handshake_flag = 0;
seyhmus.cacina 0:ac4dea3e2894 219 uint8_t * buf;
seyhmus.cacina 0:ac4dea3e2894 220
seyhmus.cacina 0:ac4dea3e2894 221 if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
seyhmus.cacina 0:ac4dea3e2894 222 return false;
seyhmus.cacina 0:ac4dea3e2894 223 }
seyhmus.cacina 0:ac4dea3e2894 224
seyhmus.cacina 0:ac4dea3e2894 225 uint32_t log_endpoint = PHY_TO_LOG(endpoint);
seyhmus.cacina 0:ac4dea3e2894 226
seyhmus.cacina 0:ac4dea3e2894 227 if ((flags & ISOCHRONOUS) == 0) {
seyhmus.cacina 0:ac4dea3e2894 228 handshake_flag = USB_ENDPT_EPHSHK_MASK;
seyhmus.cacina 0:ac4dea3e2894 229 if (IN_EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 230 if (endpoint_buffer[EP_BDT_IDX(log_endpoint, TX, ODD)] == NULL)
seyhmus.cacina 0:ac4dea3e2894 231 endpoint_buffer[EP_BDT_IDX(log_endpoint, TX, ODD)] = (uint8_t *) malloc (64);
seyhmus.cacina 0:ac4dea3e2894 232 buf = &endpoint_buffer[EP_BDT_IDX(log_endpoint, TX, ODD)][0];
seyhmus.cacina 0:ac4dea3e2894 233 } else {
seyhmus.cacina 0:ac4dea3e2894 234 if (endpoint_buffer[EP_BDT_IDX(log_endpoint, RX, ODD)] == NULL)
seyhmus.cacina 0:ac4dea3e2894 235 endpoint_buffer[EP_BDT_IDX(log_endpoint, RX, ODD)] = (uint8_t *) malloc (64);
seyhmus.cacina 0:ac4dea3e2894 236 buf = &endpoint_buffer[EP_BDT_IDX(log_endpoint, RX, ODD)][0];
seyhmus.cacina 0:ac4dea3e2894 237 }
seyhmus.cacina 0:ac4dea3e2894 238 } else {
seyhmus.cacina 0:ac4dea3e2894 239 if (IN_EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 240 if (endpoint_buffer_iso[2] == NULL)
seyhmus.cacina 0:ac4dea3e2894 241 endpoint_buffer_iso[2] = (uint8_t *) malloc (1023);
seyhmus.cacina 0:ac4dea3e2894 242 buf = &endpoint_buffer_iso[2][0];
seyhmus.cacina 0:ac4dea3e2894 243 } else {
seyhmus.cacina 0:ac4dea3e2894 244 if (endpoint_buffer_iso[0] == NULL)
seyhmus.cacina 0:ac4dea3e2894 245 endpoint_buffer_iso[0] = (uint8_t *) malloc (1023);
seyhmus.cacina 0:ac4dea3e2894 246 buf = &endpoint_buffer_iso[0][0];
seyhmus.cacina 0:ac4dea3e2894 247 }
seyhmus.cacina 0:ac4dea3e2894 248 }
seyhmus.cacina 0:ac4dea3e2894 249
seyhmus.cacina 0:ac4dea3e2894 250 // IN endpt -> device to host (TX)
seyhmus.cacina 0:ac4dea3e2894 251 if (IN_EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 252 USB0->ENDPOINT[log_endpoint].ENDPT |= handshake_flag | // ep handshaking (not if iso endpoint)
seyhmus.cacina 0:ac4dea3e2894 253 USB_ENDPT_EPTXEN_MASK; // en TX (IN) tran
seyhmus.cacina 0:ac4dea3e2894 254 bdt[EP_BDT_IDX(log_endpoint, TX, ODD )].address = (uint32_t) buf;
seyhmus.cacina 0:ac4dea3e2894 255 bdt[EP_BDT_IDX(log_endpoint, TX, EVEN)].address = 0;
seyhmus.cacina 0:ac4dea3e2894 256 }
seyhmus.cacina 0:ac4dea3e2894 257 // OUT endpt -> host to device (RX)
seyhmus.cacina 0:ac4dea3e2894 258 else {
seyhmus.cacina 0:ac4dea3e2894 259 USB0->ENDPOINT[log_endpoint].ENDPT |= handshake_flag | // ep handshaking (not if iso endpoint)
seyhmus.cacina 0:ac4dea3e2894 260 USB_ENDPT_EPRXEN_MASK; // en RX (OUT) tran.
seyhmus.cacina 0:ac4dea3e2894 261 bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].byte_count = maxPacket;
seyhmus.cacina 0:ac4dea3e2894 262 bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].address = (uint32_t) buf;
seyhmus.cacina 0:ac4dea3e2894 263 bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].info = BD_OWN_MASK | BD_DTS_MASK;
seyhmus.cacina 0:ac4dea3e2894 264 bdt[EP_BDT_IDX(log_endpoint, RX, EVEN)].info = 0;
seyhmus.cacina 0:ac4dea3e2894 265 }
seyhmus.cacina 0:ac4dea3e2894 266
seyhmus.cacina 0:ac4dea3e2894 267 Data1 |= (1 << endpoint);
seyhmus.cacina 0:ac4dea3e2894 268
seyhmus.cacina 0:ac4dea3e2894 269 return true;
seyhmus.cacina 0:ac4dea3e2894 270 }
seyhmus.cacina 0:ac4dea3e2894 271
seyhmus.cacina 0:ac4dea3e2894 272 // read setup packet
seyhmus.cacina 0:ac4dea3e2894 273 void USBHAL::EP0setup(uint8_t *buffer) {
seyhmus.cacina 0:ac4dea3e2894 274 uint32_t sz;
seyhmus.cacina 0:ac4dea3e2894 275 endpointReadResult(EP0OUT, buffer, &sz);
seyhmus.cacina 0:ac4dea3e2894 276 }
seyhmus.cacina 0:ac4dea3e2894 277
seyhmus.cacina 0:ac4dea3e2894 278 void USBHAL::EP0readStage(void) {
seyhmus.cacina 0:ac4dea3e2894 279 Data1 &= ~1UL; // set DATA0
seyhmus.cacina 0:ac4dea3e2894 280 bdt[0].info = (BD_DTS_MASK | BD_OWN_MASK);
seyhmus.cacina 0:ac4dea3e2894 281 }
seyhmus.cacina 0:ac4dea3e2894 282
seyhmus.cacina 0:ac4dea3e2894 283 void USBHAL::EP0read(void) {
seyhmus.cacina 0:ac4dea3e2894 284 uint32_t idx = EP_BDT_IDX(PHY_TO_LOG(EP0OUT), RX, 0);
seyhmus.cacina 0:ac4dea3e2894 285 bdt[idx].byte_count = MAX_PACKET_SIZE_EP0;
seyhmus.cacina 0:ac4dea3e2894 286 }
seyhmus.cacina 0:ac4dea3e2894 287
seyhmus.cacina 0:ac4dea3e2894 288 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
seyhmus.cacina 0:ac4dea3e2894 289 uint32_t sz;
seyhmus.cacina 0:ac4dea3e2894 290 endpointReadResult(EP0OUT, buffer, &sz);
seyhmus.cacina 0:ac4dea3e2894 291 return sz;
seyhmus.cacina 0:ac4dea3e2894 292 }
seyhmus.cacina 0:ac4dea3e2894 293
seyhmus.cacina 0:ac4dea3e2894 294 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
seyhmus.cacina 0:ac4dea3e2894 295 endpointWrite(EP0IN, buffer, size);
seyhmus.cacina 0:ac4dea3e2894 296 }
seyhmus.cacina 0:ac4dea3e2894 297
seyhmus.cacina 0:ac4dea3e2894 298 void USBHAL::EP0getWriteResult(void) {
seyhmus.cacina 0:ac4dea3e2894 299 }
seyhmus.cacina 0:ac4dea3e2894 300
seyhmus.cacina 0:ac4dea3e2894 301 void USBHAL::EP0stall(void) {
seyhmus.cacina 0:ac4dea3e2894 302 stallEndpoint(EP0OUT);
seyhmus.cacina 0:ac4dea3e2894 303 }
seyhmus.cacina 0:ac4dea3e2894 304
seyhmus.cacina 0:ac4dea3e2894 305 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
seyhmus.cacina 0:ac4dea3e2894 306 endpoint = PHY_TO_LOG(endpoint);
seyhmus.cacina 0:ac4dea3e2894 307 uint32_t idx = EP_BDT_IDX(endpoint, RX, 0);
seyhmus.cacina 0:ac4dea3e2894 308 bdt[idx].byte_count = maximumSize;
seyhmus.cacina 0:ac4dea3e2894 309 return EP_PENDING;
seyhmus.cacina 0:ac4dea3e2894 310 }
seyhmus.cacina 0:ac4dea3e2894 311
seyhmus.cacina 0:ac4dea3e2894 312 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
seyhmus.cacina 0:ac4dea3e2894 313 uint32_t n, sz, idx, setup = 0;
seyhmus.cacina 0:ac4dea3e2894 314 uint8_t not_iso;
seyhmus.cacina 0:ac4dea3e2894 315 uint8_t * ep_buf;
seyhmus.cacina 0:ac4dea3e2894 316
seyhmus.cacina 0:ac4dea3e2894 317 uint32_t log_endpoint = PHY_TO_LOG(endpoint);
seyhmus.cacina 0:ac4dea3e2894 318
seyhmus.cacina 0:ac4dea3e2894 319 if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
seyhmus.cacina 0:ac4dea3e2894 320 return EP_INVALID;
seyhmus.cacina 0:ac4dea3e2894 321 }
seyhmus.cacina 0:ac4dea3e2894 322
seyhmus.cacina 0:ac4dea3e2894 323 // if read on a IN endpoint -> error
seyhmus.cacina 0:ac4dea3e2894 324 if (IN_EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 325 return EP_INVALID;
seyhmus.cacina 0:ac4dea3e2894 326 }
seyhmus.cacina 0:ac4dea3e2894 327
seyhmus.cacina 0:ac4dea3e2894 328 idx = EP_BDT_IDX(log_endpoint, RX, 0);
seyhmus.cacina 0:ac4dea3e2894 329 sz = bdt[idx].byte_count;
seyhmus.cacina 0:ac4dea3e2894 330 not_iso = USB0->ENDPOINT[log_endpoint].ENDPT & USB_ENDPT_EPHSHK_MASK;
seyhmus.cacina 0:ac4dea3e2894 331
seyhmus.cacina 0:ac4dea3e2894 332 //for isochronous endpoint, we don't wait an interrupt
seyhmus.cacina 0:ac4dea3e2894 333 if ((log_endpoint != 0) && not_iso && !(epComplete & EP(endpoint))) {
seyhmus.cacina 0:ac4dea3e2894 334 return EP_PENDING;
seyhmus.cacina 0:ac4dea3e2894 335 }
seyhmus.cacina 0:ac4dea3e2894 336
seyhmus.cacina 0:ac4dea3e2894 337 if ((log_endpoint == 0) && (TOK_PID(idx) == SETUP_TOKEN)) {
seyhmus.cacina 0:ac4dea3e2894 338 setup = 1;
seyhmus.cacina 0:ac4dea3e2894 339 }
seyhmus.cacina 0:ac4dea3e2894 340
seyhmus.cacina 0:ac4dea3e2894 341 // non iso endpoint
seyhmus.cacina 0:ac4dea3e2894 342 if (not_iso) {
seyhmus.cacina 0:ac4dea3e2894 343 ep_buf = endpoint_buffer[idx];
seyhmus.cacina 0:ac4dea3e2894 344 } else {
seyhmus.cacina 0:ac4dea3e2894 345 ep_buf = endpoint_buffer_iso[0];
seyhmus.cacina 0:ac4dea3e2894 346 }
seyhmus.cacina 0:ac4dea3e2894 347
seyhmus.cacina 0:ac4dea3e2894 348 for (n = 0; n < sz; n++) {
seyhmus.cacina 0:ac4dea3e2894 349 buffer[n] = ep_buf[n];
seyhmus.cacina 0:ac4dea3e2894 350 }
seyhmus.cacina 0:ac4dea3e2894 351
seyhmus.cacina 0:ac4dea3e2894 352 if (((Data1 >> endpoint) & 1) == ((bdt[idx].info >> 6) & 1)) {
seyhmus.cacina 0:ac4dea3e2894 353 if (setup && (buffer[6] == 0)) // if no setup data stage,
seyhmus.cacina 0:ac4dea3e2894 354 Data1 &= ~1UL; // set DATA0
seyhmus.cacina 0:ac4dea3e2894 355 else
seyhmus.cacina 0:ac4dea3e2894 356 Data1 ^= (1 << endpoint);
seyhmus.cacina 0:ac4dea3e2894 357 }
seyhmus.cacina 0:ac4dea3e2894 358
seyhmus.cacina 0:ac4dea3e2894 359 if (((Data1 >> endpoint) & 1)) {
seyhmus.cacina 0:ac4dea3e2894 360 bdt[idx].info = BD_DTS_MASK | BD_DATA01_MASK | BD_OWN_MASK;
seyhmus.cacina 0:ac4dea3e2894 361 }
seyhmus.cacina 0:ac4dea3e2894 362 else {
seyhmus.cacina 0:ac4dea3e2894 363 bdt[idx].info = BD_DTS_MASK | BD_OWN_MASK;
seyhmus.cacina 0:ac4dea3e2894 364 }
seyhmus.cacina 0:ac4dea3e2894 365
seyhmus.cacina 0:ac4dea3e2894 366 USB0->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
seyhmus.cacina 0:ac4dea3e2894 367 *bytesRead = sz;
seyhmus.cacina 0:ac4dea3e2894 368
seyhmus.cacina 0:ac4dea3e2894 369 epComplete &= ~EP(endpoint);
seyhmus.cacina 0:ac4dea3e2894 370 return EP_COMPLETED;
seyhmus.cacina 0:ac4dea3e2894 371 }
seyhmus.cacina 0:ac4dea3e2894 372
seyhmus.cacina 0:ac4dea3e2894 373 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
seyhmus.cacina 0:ac4dea3e2894 374 uint32_t idx, n;
seyhmus.cacina 0:ac4dea3e2894 375 uint8_t * ep_buf;
seyhmus.cacina 0:ac4dea3e2894 376
seyhmus.cacina 0:ac4dea3e2894 377 if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
seyhmus.cacina 0:ac4dea3e2894 378 return EP_INVALID;
seyhmus.cacina 0:ac4dea3e2894 379 }
seyhmus.cacina 0:ac4dea3e2894 380
seyhmus.cacina 0:ac4dea3e2894 381 // if write on a OUT endpoint -> error
seyhmus.cacina 0:ac4dea3e2894 382 if (OUT_EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 383 return EP_INVALID;
seyhmus.cacina 0:ac4dea3e2894 384 }
seyhmus.cacina 0:ac4dea3e2894 385
seyhmus.cacina 0:ac4dea3e2894 386 idx = EP_BDT_IDX(PHY_TO_LOG(endpoint), TX, 0);
seyhmus.cacina 0:ac4dea3e2894 387 bdt[idx].byte_count = size;
seyhmus.cacina 0:ac4dea3e2894 388
seyhmus.cacina 0:ac4dea3e2894 389
seyhmus.cacina 0:ac4dea3e2894 390 // non iso endpoint
seyhmus.cacina 0:ac4dea3e2894 391 if (USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT & USB_ENDPT_EPHSHK_MASK) {
seyhmus.cacina 0:ac4dea3e2894 392 ep_buf = endpoint_buffer[idx];
seyhmus.cacina 0:ac4dea3e2894 393 } else {
seyhmus.cacina 0:ac4dea3e2894 394 ep_buf = endpoint_buffer_iso[2];
seyhmus.cacina 0:ac4dea3e2894 395 }
seyhmus.cacina 0:ac4dea3e2894 396
seyhmus.cacina 0:ac4dea3e2894 397 for (n = 0; n < size; n++) {
seyhmus.cacina 0:ac4dea3e2894 398 ep_buf[n] = data[n];
seyhmus.cacina 0:ac4dea3e2894 399 }
seyhmus.cacina 0:ac4dea3e2894 400
seyhmus.cacina 0:ac4dea3e2894 401 if ((Data1 >> endpoint) & 1) {
seyhmus.cacina 0:ac4dea3e2894 402 bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK;
seyhmus.cacina 0:ac4dea3e2894 403 } else {
seyhmus.cacina 0:ac4dea3e2894 404 bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK | BD_DATA01_MASK;
seyhmus.cacina 0:ac4dea3e2894 405 }
seyhmus.cacina 0:ac4dea3e2894 406
seyhmus.cacina 0:ac4dea3e2894 407 Data1 ^= (1 << endpoint);
seyhmus.cacina 0:ac4dea3e2894 408
seyhmus.cacina 0:ac4dea3e2894 409 return EP_PENDING;
seyhmus.cacina 0:ac4dea3e2894 410 }
seyhmus.cacina 0:ac4dea3e2894 411
seyhmus.cacina 0:ac4dea3e2894 412 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
seyhmus.cacina 0:ac4dea3e2894 413 if (epComplete & EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 414 epComplete &= ~EP(endpoint);
seyhmus.cacina 0:ac4dea3e2894 415 return EP_COMPLETED;
seyhmus.cacina 0:ac4dea3e2894 416 }
seyhmus.cacina 0:ac4dea3e2894 417
seyhmus.cacina 0:ac4dea3e2894 418 return EP_PENDING;
seyhmus.cacina 0:ac4dea3e2894 419 }
seyhmus.cacina 0:ac4dea3e2894 420
seyhmus.cacina 0:ac4dea3e2894 421 void USBHAL::stallEndpoint(uint8_t endpoint) {
seyhmus.cacina 0:ac4dea3e2894 422 USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT |= USB_ENDPT_EPSTALL_MASK;
seyhmus.cacina 0:ac4dea3e2894 423 }
seyhmus.cacina 0:ac4dea3e2894 424
seyhmus.cacina 0:ac4dea3e2894 425 void USBHAL::unstallEndpoint(uint8_t endpoint) {
seyhmus.cacina 0:ac4dea3e2894 426 USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT &= ~USB_ENDPT_EPSTALL_MASK;
seyhmus.cacina 0:ac4dea3e2894 427 }
seyhmus.cacina 0:ac4dea3e2894 428
seyhmus.cacina 0:ac4dea3e2894 429 bool USBHAL::getEndpointStallState(uint8_t endpoint) {
seyhmus.cacina 0:ac4dea3e2894 430 uint8_t stall = (USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT & USB_ENDPT_EPSTALL_MASK);
seyhmus.cacina 0:ac4dea3e2894 431 return (stall) ? true : false;
seyhmus.cacina 0:ac4dea3e2894 432 }
seyhmus.cacina 0:ac4dea3e2894 433
seyhmus.cacina 0:ac4dea3e2894 434 void USBHAL::remoteWakeup(void) {
seyhmus.cacina 0:ac4dea3e2894 435 // [TODO]
seyhmus.cacina 0:ac4dea3e2894 436 }
seyhmus.cacina 0:ac4dea3e2894 437
seyhmus.cacina 0:ac4dea3e2894 438
seyhmus.cacina 0:ac4dea3e2894 439 void USBHAL::_usbisr(void) {
seyhmus.cacina 0:ac4dea3e2894 440 instance->usbisr();
seyhmus.cacina 0:ac4dea3e2894 441 }
seyhmus.cacina 0:ac4dea3e2894 442
seyhmus.cacina 0:ac4dea3e2894 443
seyhmus.cacina 0:ac4dea3e2894 444 void USBHAL::usbisr(void) {
seyhmus.cacina 0:ac4dea3e2894 445 uint8_t i;
seyhmus.cacina 0:ac4dea3e2894 446 uint8_t istat = USB0->ISTAT;
seyhmus.cacina 0:ac4dea3e2894 447
seyhmus.cacina 0:ac4dea3e2894 448 // reset interrupt
seyhmus.cacina 0:ac4dea3e2894 449 if (istat & USB_ISTAT_USBRST_MASK) {
seyhmus.cacina 0:ac4dea3e2894 450 // disable all endpt
seyhmus.cacina 0:ac4dea3e2894 451 for(i = 0; i < 16; i++) {
seyhmus.cacina 0:ac4dea3e2894 452 USB0->ENDPOINT[i].ENDPT = 0x00;
seyhmus.cacina 0:ac4dea3e2894 453 }
seyhmus.cacina 0:ac4dea3e2894 454
seyhmus.cacina 0:ac4dea3e2894 455 // enable control endpoint
seyhmus.cacina 0:ac4dea3e2894 456 realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
seyhmus.cacina 0:ac4dea3e2894 457 realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
seyhmus.cacina 0:ac4dea3e2894 458
seyhmus.cacina 0:ac4dea3e2894 459 Data1 = 0x55555555;
seyhmus.cacina 0:ac4dea3e2894 460 USB0->CTL |= USB_CTL_ODDRST_MASK;
seyhmus.cacina 0:ac4dea3e2894 461
seyhmus.cacina 0:ac4dea3e2894 462 USB0->ISTAT = 0xFF; // clear all interrupt status flags
seyhmus.cacina 0:ac4dea3e2894 463 USB0->ERRSTAT = 0xFF; // clear all error flags
seyhmus.cacina 0:ac4dea3e2894 464 USB0->ERREN = 0xFF; // enable error interrupt sources
seyhmus.cacina 0:ac4dea3e2894 465 USB0->ADDR = 0x00; // set default address
seyhmus.cacina 0:ac4dea3e2894 466
seyhmus.cacina 0:ac4dea3e2894 467 return;
seyhmus.cacina 0:ac4dea3e2894 468 }
seyhmus.cacina 0:ac4dea3e2894 469
seyhmus.cacina 0:ac4dea3e2894 470 // resume interrupt
seyhmus.cacina 0:ac4dea3e2894 471 if (istat & USB_ISTAT_RESUME_MASK) {
seyhmus.cacina 0:ac4dea3e2894 472 USB0->ISTAT = USB_ISTAT_RESUME_MASK;
seyhmus.cacina 0:ac4dea3e2894 473 }
seyhmus.cacina 0:ac4dea3e2894 474
seyhmus.cacina 0:ac4dea3e2894 475 // SOF interrupt
seyhmus.cacina 0:ac4dea3e2894 476 if (istat & USB_ISTAT_SOFTOK_MASK) {
seyhmus.cacina 0:ac4dea3e2894 477 USB0->ISTAT = USB_ISTAT_SOFTOK_MASK;
seyhmus.cacina 0:ac4dea3e2894 478 // SOF event, read frame number
seyhmus.cacina 0:ac4dea3e2894 479 SOF(frameNumber());
seyhmus.cacina 0:ac4dea3e2894 480 }
seyhmus.cacina 0:ac4dea3e2894 481
seyhmus.cacina 0:ac4dea3e2894 482 // stall interrupt
seyhmus.cacina 0:ac4dea3e2894 483 if (istat & 1<<7) {
seyhmus.cacina 0:ac4dea3e2894 484 if (USB0->ENDPOINT[0].ENDPT & USB_ENDPT_EPSTALL_MASK)
seyhmus.cacina 0:ac4dea3e2894 485 USB0->ENDPOINT[0].ENDPT &= ~USB_ENDPT_EPSTALL_MASK;
seyhmus.cacina 0:ac4dea3e2894 486 USB0->ISTAT |= USB_ISTAT_STALL_MASK;
seyhmus.cacina 0:ac4dea3e2894 487 }
seyhmus.cacina 0:ac4dea3e2894 488
seyhmus.cacina 0:ac4dea3e2894 489 // token interrupt
seyhmus.cacina 0:ac4dea3e2894 490 if (istat & 1<<3) {
seyhmus.cacina 0:ac4dea3e2894 491 uint32_t num = (USB0->STAT >> 4) & 0x0F;
seyhmus.cacina 0:ac4dea3e2894 492 uint32_t dir = (USB0->STAT >> 3) & 0x01;
seyhmus.cacina 0:ac4dea3e2894 493 uint32_t ev_odd = (USB0->STAT >> 2) & 0x01;
seyhmus.cacina 0:ac4dea3e2894 494 int endpoint = (num << 1) | dir;
seyhmus.cacina 0:ac4dea3e2894 495
seyhmus.cacina 0:ac4dea3e2894 496 // setup packet
seyhmus.cacina 0:ac4dea3e2894 497 if ((num == 0) && (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == SETUP_TOKEN)) {
seyhmus.cacina 0:ac4dea3e2894 498 Data1 &= ~0x02;
seyhmus.cacina 0:ac4dea3e2894 499 bdt[EP_BDT_IDX(0, TX, EVEN)].info &= ~BD_OWN_MASK;
seyhmus.cacina 0:ac4dea3e2894 500 bdt[EP_BDT_IDX(0, TX, ODD)].info &= ~BD_OWN_MASK;
seyhmus.cacina 0:ac4dea3e2894 501
seyhmus.cacina 0:ac4dea3e2894 502 // EP0 SETUP event (SETUP data received)
seyhmus.cacina 0:ac4dea3e2894 503 EP0setupCallback();
seyhmus.cacina 0:ac4dea3e2894 504
seyhmus.cacina 0:ac4dea3e2894 505 } else {
seyhmus.cacina 0:ac4dea3e2894 506 // OUT packet
seyhmus.cacina 0:ac4dea3e2894 507 if (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == OUT_TOKEN) {
seyhmus.cacina 0:ac4dea3e2894 508 if (num == 0)
seyhmus.cacina 0:ac4dea3e2894 509 EP0out();
seyhmus.cacina 0:ac4dea3e2894 510 else {
seyhmus.cacina 0:ac4dea3e2894 511 epComplete |= EP(endpoint);
seyhmus.cacina 0:ac4dea3e2894 512 if ((instance->*(epCallback[endpoint - 2]))()) {
seyhmus.cacina 0:ac4dea3e2894 513 epComplete &= ~EP(endpoint);
seyhmus.cacina 0:ac4dea3e2894 514 }
seyhmus.cacina 0:ac4dea3e2894 515 }
seyhmus.cacina 0:ac4dea3e2894 516 }
seyhmus.cacina 0:ac4dea3e2894 517
seyhmus.cacina 0:ac4dea3e2894 518 // IN packet
seyhmus.cacina 0:ac4dea3e2894 519 if (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == IN_TOKEN) {
seyhmus.cacina 0:ac4dea3e2894 520 if (num == 0) {
seyhmus.cacina 0:ac4dea3e2894 521 EP0in();
seyhmus.cacina 0:ac4dea3e2894 522 if (set_addr == 1) {
seyhmus.cacina 0:ac4dea3e2894 523 USB0->ADDR = addr & 0x7F;
seyhmus.cacina 0:ac4dea3e2894 524 set_addr = 0;
seyhmus.cacina 0:ac4dea3e2894 525 }
seyhmus.cacina 0:ac4dea3e2894 526 }
seyhmus.cacina 0:ac4dea3e2894 527 else {
seyhmus.cacina 0:ac4dea3e2894 528 epComplete |= EP(endpoint);
seyhmus.cacina 0:ac4dea3e2894 529 if ((instance->*(epCallback[endpoint - 2]))()) {
seyhmus.cacina 0:ac4dea3e2894 530 epComplete &= ~EP(endpoint);
seyhmus.cacina 0:ac4dea3e2894 531 }
seyhmus.cacina 0:ac4dea3e2894 532 }
seyhmus.cacina 0:ac4dea3e2894 533 }
seyhmus.cacina 0:ac4dea3e2894 534 }
seyhmus.cacina 0:ac4dea3e2894 535
seyhmus.cacina 0:ac4dea3e2894 536 USB0->ISTAT = USB_ISTAT_TOKDNE_MASK;
seyhmus.cacina 0:ac4dea3e2894 537 }
seyhmus.cacina 0:ac4dea3e2894 538
seyhmus.cacina 0:ac4dea3e2894 539 // sleep interrupt
seyhmus.cacina 0:ac4dea3e2894 540 if (istat & 1<<4) {
seyhmus.cacina 0:ac4dea3e2894 541 USB0->ISTAT |= USB_ISTAT_SLEEP_MASK;
seyhmus.cacina 0:ac4dea3e2894 542 }
seyhmus.cacina 0:ac4dea3e2894 543
seyhmus.cacina 0:ac4dea3e2894 544 // error interrupt
seyhmus.cacina 0:ac4dea3e2894 545 if (istat & USB_ISTAT_ERROR_MASK) {
seyhmus.cacina 0:ac4dea3e2894 546 USB0->ERRSTAT = 0xFF;
seyhmus.cacina 0:ac4dea3e2894 547 USB0->ISTAT |= USB_ISTAT_ERROR_MASK;
seyhmus.cacina 0:ac4dea3e2894 548 }
seyhmus.cacina 0:ac4dea3e2894 549 }
seyhmus.cacina 0:ac4dea3e2894 550
seyhmus.cacina 0:ac4dea3e2894 551
seyhmus.cacina 0:ac4dea3e2894 552 #endif