library for MAX14661 16:2 mux
Dependents: ard2pmod MAX14661_Demo
max14661.cpp@4:45fa0192f66d, 2014-11-21 (annotated)
- Committer:
- j3
- Date:
- Fri Nov 21 04:31:05 2014 +0000
- Revision:
- 4:45fa0192f66d
- Parent:
- 2:88c168ddc145
- Child:
- 6:be4f2d7fc054
changed input args to write fx from an array to two 16 bit ints that represent switch states for each bank. Fixed C0PY_SHADOW to COPY_SHADOW
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
j3 | 0:c770ad7363c8 | 1 | /******************************************************************//** |
j3 | 0:c770ad7363c8 | 2 | * @file max14661.cpp |
j3 | 0:c770ad7363c8 | 3 | * |
j3 | 0:c770ad7363c8 | 4 | * @author Justin Jordan |
j3 | 0:c770ad7363c8 | 5 | * |
j3 | 0:c770ad7363c8 | 6 | * @version 0.0 |
j3 | 0:c770ad7363c8 | 7 | * |
j3 | 0:c770ad7363c8 | 8 | * Started: 11NOV14 |
j3 | 0:c770ad7363c8 | 9 | * |
j3 | 0:c770ad7363c8 | 10 | * Updated: |
j3 | 0:c770ad7363c8 | 11 | * |
j3 | 0:c770ad7363c8 | 12 | * @brief Source file for MAX14661 class |
j3 | 0:c770ad7363c8 | 13 | * |
j3 | 0:c770ad7363c8 | 14 | *********************************************************************** |
j3 | 0:c770ad7363c8 | 15 | * |
j3 | 0:c770ad7363c8 | 16 | * @copyright |
j3 | 0:c770ad7363c8 | 17 | * Copyright (C) 2013 Maxim Integrated Products, Inc., All Rights Reserved. |
j3 | 0:c770ad7363c8 | 18 | * |
j3 | 0:c770ad7363c8 | 19 | * Permission is hereby granted, free of charge, to any person obtaining a |
j3 | 0:c770ad7363c8 | 20 | * copy of this software and associated documentation files (the "Software"), |
j3 | 0:c770ad7363c8 | 21 | * to deal in the Software without restriction, including without limitation |
j3 | 0:c770ad7363c8 | 22 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
j3 | 0:c770ad7363c8 | 23 | * and/or sell copies of the Software, and to permit persons to whom the |
j3 | 0:c770ad7363c8 | 24 | * Software is furnished to do so, subject to the following conditions: |
j3 | 0:c770ad7363c8 | 25 | * |
j3 | 0:c770ad7363c8 | 26 | * The above copyright notice and this permission notice shall be included |
j3 | 0:c770ad7363c8 | 27 | * in all copies or substantial portions of the Software. |
j3 | 0:c770ad7363c8 | 28 | * |
j3 | 0:c770ad7363c8 | 29 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
j3 | 0:c770ad7363c8 | 30 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
j3 | 0:c770ad7363c8 | 31 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
j3 | 0:c770ad7363c8 | 32 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
j3 | 0:c770ad7363c8 | 33 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
j3 | 0:c770ad7363c8 | 34 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
j3 | 0:c770ad7363c8 | 35 | * OTHER DEALINGS IN THE SOFTWARE. |
j3 | 0:c770ad7363c8 | 36 | * |
j3 | 0:c770ad7363c8 | 37 | * Except as contained in this notice, the name of Maxim Integrated |
j3 | 0:c770ad7363c8 | 38 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
j3 | 0:c770ad7363c8 | 39 | * Products, Inc. Branding Policy. |
j3 | 0:c770ad7363c8 | 40 | * |
j3 | 0:c770ad7363c8 | 41 | * The mere transfer of this software does not imply any licenses |
j3 | 0:c770ad7363c8 | 42 | * of trade secrets, proprietary technology, copyrights, patents, |
j3 | 0:c770ad7363c8 | 43 | * trademarks, maskwork rights, or any other form of intellectual |
j3 | 0:c770ad7363c8 | 44 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
j3 | 0:c770ad7363c8 | 45 | * ownership rights. |
j3 | 0:c770ad7363c8 | 46 | **********************************************************************/ |
j3 | 0:c770ad7363c8 | 47 | |
j3 | 0:c770ad7363c8 | 48 | |
j3 | 0:c770ad7363c8 | 49 | #include "max14661.h" |
j3 | 0:c770ad7363c8 | 50 | |
j3 | 0:c770ad7363c8 | 51 | |
j3 | 2:88c168ddc145 | 52 | /**********************************************************//** |
j3 | 2:88c168ddc145 | 53 | * Constructor for Max14661 Class |
j3 | 0:c770ad7363c8 | 54 | * |
j3 | 0:c770ad7363c8 | 55 | * On Entry: |
j3 | 2:88c168ddc145 | 56 | * @param[in] sda - sda pin of I2C bus |
j3 | 2:88c168ddc145 | 57 | * @param[in] scl - scl pin of I2C bus |
j3 | 0:c770ad7363c8 | 58 | * @param[in] i2c_adrs - 7-bit slave address of MAX14661 |
j3 | 0:c770ad7363c8 | 59 | * |
j3 | 0:c770ad7363c8 | 60 | * On Exit: |
j3 | 0:c770ad7363c8 | 61 | * @return none |
j3 | 0:c770ad7363c8 | 62 | * |
j3 | 0:c770ad7363c8 | 63 | * Example: |
j3 | 0:c770ad7363c8 | 64 | * @code |
j3 | 0:c770ad7363c8 | 65 | * |
j3 | 2:88c168ddc145 | 66 | * //declare mux object |
j3 | 2:88c168ddc145 | 67 | * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0); |
j3 | 0:c770ad7363c8 | 68 | * |
j3 | 0:c770ad7363c8 | 69 | * @endcode |
j3 | 2:88c168ddc145 | 70 | **************************************************************/ |
j3 | 2:88c168ddc145 | 71 | Max14661::Max14661(PinName sda, PinName scl, max14661_i2c_adrs_t i2c_adrs) : |
j3 | 2:88c168ddc145 | 72 | I2C(sda, scl) |
j3 | 0:c770ad7363c8 | 73 | { |
j3 | 0:c770ad7363c8 | 74 | w_adrs = (i2c_adrs << 1); |
j3 | 0:c770ad7363c8 | 75 | r_adrs = (w_adrs | 0x01); |
j3 | 0:c770ad7363c8 | 76 | } |
j3 | 0:c770ad7363c8 | 77 | |
j3 | 0:c770ad7363c8 | 78 | |
j3 | 0:c770ad7363c8 | 79 | /******************************************************************//** |
j3 | 0:c770ad7363c8 | 80 | * Writes given commands to CMD_A and CMD_B |
j3 | 0:c770ad7363c8 | 81 | * |
j3 | 0:c770ad7363c8 | 82 | * On Entry: |
j3 | 0:c770ad7363c8 | 83 | * @param[in] cmdA - command for CMD_A |
j3 | 0:c770ad7363c8 | 84 | * @param[in] cmdB - command for CMD_B |
j3 | 0:c770ad7363c8 | 85 | * |
j3 | 0:c770ad7363c8 | 86 | * On Exit: |
j3 | 0:c770ad7363c8 | 87 | * @return return value = 0 on success, non-0 on failure |
j3 | 0:c770ad7363c8 | 88 | * |
j3 | 0:c770ad7363c8 | 89 | * Example: |
j3 | 0:c770ad7363c8 | 90 | * @code |
j3 | 0:c770ad7363c8 | 91 | * |
j3 | 2:88c168ddc145 | 92 | * //declare mux object |
j3 | 2:88c168ddc145 | 93 | * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0); |
j3 | 0:c770ad7363c8 | 94 | * |
j3 | 0:c770ad7363c8 | 95 | * uint16_t rtn_val; |
j3 | 0:c770ad7363c8 | 96 | * |
j3 | 0:c770ad7363c8 | 97 | * rtn_val = mux.wrt_cmd_registers(DISABLE_BANK, DISABLE_BANK); |
j3 | 0:c770ad7363c8 | 98 | * |
j3 | 0:c770ad7363c8 | 99 | * @endcode |
j3 | 0:c770ad7363c8 | 100 | **********************************************************************/ |
j3 | 0:c770ad7363c8 | 101 | uint16_t Max14661::wrt_cmd_registers(max14661_cmds_t cmdA, |
j3 | 0:c770ad7363c8 | 102 | max14661_cmds_t cmdB) |
j3 | 0:c770ad7363c8 | 103 | { |
j3 | 0:c770ad7363c8 | 104 | uint8_t data[3]; |
j3 | 0:c770ad7363c8 | 105 | uint8_t data_length = 0; |
j3 | 0:c770ad7363c8 | 106 | uint16_t rtn_val = 1; |
j3 | 0:c770ad7363c8 | 107 | |
j3 | 0:c770ad7363c8 | 108 | //build packet |
j3 | 0:c770ad7363c8 | 109 | data[data_length++] = CMD_A; |
j3 | 0:c770ad7363c8 | 110 | data[data_length++] = cmdA; |
j3 | 0:c770ad7363c8 | 111 | data[data_length++] = cmdB; |
j3 | 0:c770ad7363c8 | 112 | |
j3 | 2:88c168ddc145 | 113 | rtn_val = write(w_adrs,(const char*) data, data_length); |
j3 | 0:c770ad7363c8 | 114 | |
j3 | 0:c770ad7363c8 | 115 | return(rtn_val); |
j3 | 0:c770ad7363c8 | 116 | } |
j3 | 0:c770ad7363c8 | 117 | |
j3 | 0:c770ad7363c8 | 118 | |
j3 | 0:c770ad7363c8 | 119 | /******************************************************************//** |
j3 | 4:45fa0192f66d | 120 | * Writes bankA and bankB to coresponding shadow registers |
j3 | 0:c770ad7363c8 | 121 | * |
j3 | 0:c770ad7363c8 | 122 | * On Entry: |
j3 | 4:45fa0192f66d | 123 | * @param[in] bankA - binary representation of switch states |
j3 | 4:45fa0192f66d | 124 | * @param[in] bankB - binary representation of switch states |
j3 | 0:c770ad7363c8 | 125 | * |
j3 | 0:c770ad7363c8 | 126 | * On Exit: |
j3 | 0:c770ad7363c8 | 127 | * @return return value = 0 on success, non-0 on failure |
j3 | 0:c770ad7363c8 | 128 | * |
j3 | 0:c770ad7363c8 | 129 | * Example: |
j3 | 0:c770ad7363c8 | 130 | * @code |
j3 | 0:c770ad7363c8 | 131 | * |
j3 | 2:88c168ddc145 | 132 | * //declare mux object |
j3 | 2:88c168ddc145 | 133 | * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0); |
j3 | 0:c770ad7363c8 | 134 | * |
j3 | 4:45fa0192f66d | 135 | * uint16_t bankA = (SW12 | SW02); //example only |
j3 | 4:45fa0192f66d | 136 | * uint16_t bankB = (SW11 | SW01); |
j3 | 0:c770ad7363c8 | 137 | * uint16_t rtn_val; |
j3 | 0:c770ad7363c8 | 138 | * |
j3 | 0:c770ad7363c8 | 139 | * //wite shadow registers |
j3 | 4:45fa0192f66d | 140 | * rtn_val = mux.wrt_shadow_registers(bankA, bankB); |
j3 | 0:c770ad7363c8 | 141 | * |
j3 | 0:c770ad7363c8 | 142 | * @endcode |
j3 | 0:c770ad7363c8 | 143 | **********************************************************************/ |
j3 | 4:45fa0192f66d | 144 | uint16_t Max14661::wrt_shadow_registers(uint16_t bankA, uint16_t bankB) |
j3 | 0:c770ad7363c8 | 145 | { |
j3 | 4:45fa0192f66d | 146 | uint8_t data[5]; |
j3 | 0:c770ad7363c8 | 147 | uint8_t data_length = 0; |
j3 | 0:c770ad7363c8 | 148 | uint16_t rtn_val = 1; |
j3 | 0:c770ad7363c8 | 149 | |
j3 | 4:45fa0192f66d | 150 | data[data_length++] = SHDW0; |
j3 | 4:45fa0192f66d | 151 | data[data_length++] = (bankA & 0x00FF); |
j3 | 4:45fa0192f66d | 152 | data[data_length++] = ((bankA >> 8) & 0x00FF); |
j3 | 4:45fa0192f66d | 153 | data[data_length++] = (bankB & 0x00FF); |
j3 | 4:45fa0192f66d | 154 | data[data_length++] = ((bankB >> 8) & 0x00FF); |
j3 | 0:c770ad7363c8 | 155 | |
j3 | 4:45fa0192f66d | 156 | rtn_val = write(w_adrs,(const char*) data, data_length); |
j3 | 0:c770ad7363c8 | 157 | |
j3 | 0:c770ad7363c8 | 158 | return(rtn_val); |
j3 | 0:c770ad7363c8 | 159 | } |
j3 | 0:c770ad7363c8 | 160 | |
j3 | 0:c770ad7363c8 | 161 | |
j3 | 0:c770ad7363c8 | 162 | /******************************************************************//** |
j3 | 4:45fa0192f66d | 163 | * Writes bankA and bankB to coresponding direct access registers |
j3 | 0:c770ad7363c8 | 164 | * |
j3 | 0:c770ad7363c8 | 165 | * On Entry: |
j3 | 4:45fa0192f66d | 166 | * @param[in] bankA - binary representation of switch states |
j3 | 4:45fa0192f66d | 167 | * @param[in] bankB - binary representation of switch states |
j3 | 0:c770ad7363c8 | 168 | * |
j3 | 0:c770ad7363c8 | 169 | * On Exit: |
j3 | 0:c770ad7363c8 | 170 | * @return return value = 0 on success, non-0 on failure |
j3 | 0:c770ad7363c8 | 171 | * |
j3 | 0:c770ad7363c8 | 172 | * Example: |
j3 | 1:c1fdfe4c2354 | 173 | * @code |
j3 | 0:c770ad7363c8 | 174 | * |
j3 | 2:88c168ddc145 | 175 | * //declare mux object |
j3 | 2:88c168ddc145 | 176 | * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0); |
j3 | 0:c770ad7363c8 | 177 | * |
j3 | 4:45fa0192f66d | 178 | * uint16_t bankA = (SW12 | SW02); //example only |
j3 | 4:45fa0192f66d | 179 | * uint16_t bankB = (SW11 | SW01); |
j3 | 0:c770ad7363c8 | 180 | * uint16_t rtn_val; |
j3 | 0:c770ad7363c8 | 181 | * |
j3 | 0:c770ad7363c8 | 182 | * //wite shadow registers |
j3 | 4:45fa0192f66d | 183 | * rtn_val = mux.wrt_dir_registers(bankA, bankB); |
j3 | 0:c770ad7363c8 | 184 | * |
j3 | 0:c770ad7363c8 | 185 | * @endcode |
j3 | 0:c770ad7363c8 | 186 | **********************************************************************/ |
j3 | 4:45fa0192f66d | 187 | uint16_t Max14661::wrt_dir_registers(uint16_t bankA, uint16_t bankB) |
j3 | 0:c770ad7363c8 | 188 | { |
j3 | 4:45fa0192f66d | 189 | uint8_t data[5]; |
j3 | 0:c770ad7363c8 | 190 | uint8_t data_length = 0; |
j3 | 0:c770ad7363c8 | 191 | uint16_t rtn_val = 1; |
j3 | 0:c770ad7363c8 | 192 | |
j3 | 4:45fa0192f66d | 193 | data[data_length++] = DIR0; |
j3 | 4:45fa0192f66d | 194 | data[data_length++] = (bankA & 0x00FF); |
j3 | 4:45fa0192f66d | 195 | data[data_length++] = ((bankA >> 8) & 0x00FF); |
j3 | 4:45fa0192f66d | 196 | data[data_length++] = (bankB & 0x00FF); |
j3 | 4:45fa0192f66d | 197 | data[data_length++] = ((bankB >> 8) & 0x00FF); |
j3 | 4:45fa0192f66d | 198 | |
j3 | 4:45fa0192f66d | 199 | rtn_val = write(w_adrs,(const char*) data, data_length); |
j3 | 0:c770ad7363c8 | 200 | |
j3 | 4:45fa0192f66d | 201 | return(rtn_val); |
j3 | 4:45fa0192f66d | 202 | } |
j3 | 4:45fa0192f66d | 203 | |
j3 | 4:45fa0192f66d | 204 | |
j3 | 4:45fa0192f66d | 205 | /******************************************************************//** |
j3 | 4:45fa0192f66d | 206 | * Writes bankA and bankB to coresponding shadow register and then |
j3 | 4:45fa0192f66d | 207 | * issues copy command for both banks |
j3 | 4:45fa0192f66d | 208 | * |
j3 | 4:45fa0192f66d | 209 | * On Entry: |
j3 | 4:45fa0192f66d | 210 | * @param[in] bankA - binary representation of switch states |
j3 | 4:45fa0192f66d | 211 | * @param[in] bankB - binary representation of switch states |
j3 | 4:45fa0192f66d | 212 | * |
j3 | 4:45fa0192f66d | 213 | * On Exit: |
j3 | 4:45fa0192f66d | 214 | * @return return value = 0 on success, non-0 on failure |
j3 | 4:45fa0192f66d | 215 | * |
j3 | 4:45fa0192f66d | 216 | * Example: |
j3 | 4:45fa0192f66d | 217 | * @code |
j3 | 4:45fa0192f66d | 218 | * |
j3 | 4:45fa0192f66d | 219 | * //declare mux object |
j3 | 4:45fa0192f66d | 220 | * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0); |
j3 | 4:45fa0192f66d | 221 | * |
j3 | 4:45fa0192f66d | 222 | * uint16_t bankA = (SW12 | SW02); //example only |
j3 | 4:45fa0192f66d | 223 | * uint16_t bankB = (SW11 | SW01); |
j3 | 4:45fa0192f66d | 224 | * uint16_t rtn_val; |
j3 | 4:45fa0192f66d | 225 | * |
j3 | 4:45fa0192f66d | 226 | * //wite shadow registers |
j3 | 4:45fa0192f66d | 227 | * rtn_val = mux.set_switches(bankA, bankB); |
j3 | 4:45fa0192f66d | 228 | * |
j3 | 4:45fa0192f66d | 229 | * @endcode |
j3 | 4:45fa0192f66d | 230 | **********************************************************************/ |
j3 | 4:45fa0192f66d | 231 | uint16_t Max14661::set_switches(uint16_t bankA, uint16_t bankB) |
j3 | 4:45fa0192f66d | 232 | { |
j3 | 4:45fa0192f66d | 233 | uint8_t data[7]; |
j3 | 4:45fa0192f66d | 234 | uint8_t data_length = 0; |
j3 | 4:45fa0192f66d | 235 | uint16_t rtn_val = 1; |
j3 | 0:c770ad7363c8 | 236 | |
j3 | 4:45fa0192f66d | 237 | data[data_length++] = SHDW0; |
j3 | 4:45fa0192f66d | 238 | data[data_length++] = (bankA & 0x00FF); |
j3 | 4:45fa0192f66d | 239 | data[data_length++] = ((bankA >> 8) & 0x00FF); |
j3 | 4:45fa0192f66d | 240 | data[data_length++] = (bankB & 0x00FF); |
j3 | 4:45fa0192f66d | 241 | data[data_length++] = ((bankB >> 8) & 0x00FF); |
j3 | 4:45fa0192f66d | 242 | data[data_length++] = COPY_SHADOW; |
j3 | 4:45fa0192f66d | 243 | data[data_length++] = COPY_SHADOW; |
j3 | 4:45fa0192f66d | 244 | |
j3 | 4:45fa0192f66d | 245 | rtn_val = write(w_adrs,(const char*) data, data_length); |
j3 | 0:c770ad7363c8 | 246 | |
j3 | 0:c770ad7363c8 | 247 | return(rtn_val); |
j3 | 0:c770ad7363c8 | 248 | } |
j3 | 0:c770ad7363c8 | 249 | |
j3 | 0:c770ad7363c8 | 250 | |
j3 | 0:c770ad7363c8 | 251 | /**********************************************************//** |
j3 | 0:c770ad7363c8 | 252 | * Reads data from direct access registers starting at DIR0 and |
j3 | 0:c770ad7363c8 | 253 | * stores it in byte array pointed at by 'data' |
j3 | 0:c770ad7363c8 | 254 | * |
j3 | 0:c770ad7363c8 | 255 | * On Entry: |
j3 | 0:c770ad7363c8 | 256 | * @param[in] data - pointer to byte array for storing data |
j3 | 0:c770ad7363c8 | 257 | * |
j3 | 0:c770ad7363c8 | 258 | * On Exit: |
j3 | 0:c770ad7363c8 | 259 | * @param[out] data - data buffer now contains data read |
j3 | 0:c770ad7363c8 | 260 | * from dir registers |
j3 | 0:c770ad7363c8 | 261 | * @return return value = 0 on success, non-0 on failure |
j3 | 0:c770ad7363c8 | 262 | * |
j3 | 0:c770ad7363c8 | 263 | * Example: |
j3 | 0:c770ad7363c8 | 264 | * @code |
j3 | 0:c770ad7363c8 | 265 | * |
j3 | 2:88c168ddc145 | 266 | * //declare mux object |
j3 | 2:88c168ddc145 | 267 | * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0); |
j3 | 0:c770ad7363c8 | 268 | * |
j3 | 0:c770ad7363c8 | 269 | * uint16_t rtn_val; |
j3 | 0:c770ad7363c8 | 270 | * uint8_t data[4]; |
j3 | 0:c770ad7363c8 | 271 | * |
j3 | 0:c770ad7363c8 | 272 | * //read direct access registers |
j3 | 0:c770ad7363c8 | 273 | * rtn_val = mux.rd_dir_registers(data); |
j3 | 0:c770ad7363c8 | 274 | * |
j3 | 0:c770ad7363c8 | 275 | * @endcode |
j3 | 0:c770ad7363c8 | 276 | **********************************************************************/ |
j3 | 0:c770ad7363c8 | 277 | uint16_t Max14661::rd_dir_registers(uint8_t* data) |
j3 | 0:c770ad7363c8 | 278 | { |
j3 | 0:c770ad7363c8 | 279 | uint16_t rtn_val = 1; |
j3 | 0:c770ad7363c8 | 280 | uint8_t local_data = DIR0; |
j3 | 0:c770ad7363c8 | 281 | |
j3 | 2:88c168ddc145 | 282 | rtn_val = write(w_adrs,(const char*) local_data, 1); |
j3 | 0:c770ad7363c8 | 283 | |
j3 | 0:c770ad7363c8 | 284 | if(!rtn_val) |
j3 | 0:c770ad7363c8 | 285 | { |
j3 | 2:88c168ddc145 | 286 | rtn_val = read(r_adrs,(char*) data, 4); |
j3 | 0:c770ad7363c8 | 287 | } |
j3 | 0:c770ad7363c8 | 288 | |
j3 | 0:c770ad7363c8 | 289 | return(rtn_val); |
j3 | 0:c770ad7363c8 | 290 | } |
j3 | 0:c770ad7363c8 | 291 | |
j3 | 0:c770ad7363c8 | 292 | |
j3 | 0:c770ad7363c8 | 293 | /**********************************************************//** |
j3 | 0:c770ad7363c8 | 294 | * Reads data from shadow registers starting at SHDW0 and stores |
j3 | 0:c770ad7363c8 | 295 | * it in byte array pointed at by 'data' |
j3 | 0:c770ad7363c8 | 296 | * |
j3 | 0:c770ad7363c8 | 297 | * On Entry: |
j3 | 0:c770ad7363c8 | 298 | * @param[in] data - pointer to byte array for storing data |
j3 | 0:c770ad7363c8 | 299 | * |
j3 | 0:c770ad7363c8 | 300 | * On Exit: |
j3 | 0:c770ad7363c8 | 301 | * @param[out] data - data buffer now contains data read |
j3 | 0:c770ad7363c8 | 302 | * from shadow registers |
j3 | 0:c770ad7363c8 | 303 | * @return return value = 0 on success, non-0 on failure |
j3 | 0:c770ad7363c8 | 304 | * |
j3 | 0:c770ad7363c8 | 305 | * Example: |
j3 | 0:c770ad7363c8 | 306 | * @code |
j3 | 0:c770ad7363c8 | 307 | * |
j3 | 2:88c168ddc145 | 308 | * //declare mux object |
j3 | 2:88c168ddc145 | 309 | * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0); |
j3 | 0:c770ad7363c8 | 310 | * |
j3 | 0:c770ad7363c8 | 311 | * uint16_t rtn_val; |
j3 | 0:c770ad7363c8 | 312 | * uint8_t data[4]; |
j3 | 0:c770ad7363c8 | 313 | * |
j3 | 0:c770ad7363c8 | 314 | * //read shadow registers |
j3 | 0:c770ad7363c8 | 315 | * rtn_val = mux.rd_shadow_registers(data); |
j3 | 0:c770ad7363c8 | 316 | * |
j3 | 0:c770ad7363c8 | 317 | * @endcode |
j3 | 2:88c168ddc145 | 318 | **************************************************************/ |
j3 | 0:c770ad7363c8 | 319 | uint16_t Max14661::rd_shadow_registers(uint8_t* data) |
j3 | 0:c770ad7363c8 | 320 | { |
j3 | 0:c770ad7363c8 | 321 | uint16_t rtn_val = 1; |
j3 | 0:c770ad7363c8 | 322 | uint8_t local_data = SHDW0; |
j3 | 0:c770ad7363c8 | 323 | |
j3 | 2:88c168ddc145 | 324 | rtn_val = write(w_adrs,(const char*) local_data, 1); |
j3 | 0:c770ad7363c8 | 325 | |
j3 | 0:c770ad7363c8 | 326 | if(!rtn_val) |
j3 | 0:c770ad7363c8 | 327 | { |
j3 | 2:88c168ddc145 | 328 | rtn_val = read(r_adrs,(char*) data, 4); |
j3 | 0:c770ad7363c8 | 329 | } |
j3 | 0:c770ad7363c8 | 330 | |
j3 | 0:c770ad7363c8 | 331 | return(rtn_val); |
j3 | 0:c770ad7363c8 | 332 | } |