Maxim Integrated / USBDevice

USBDevice with MAX32620HSP platform support

Fork of USBDevice by mbed official

USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_function_dmacdrv.c@35:a8484e16c2f3, 2014-11-06 (annotated)

Committer:
mbed_official
Date:
Thu Nov 06 11:01:12 2014 +0000
Revision:
35:a8484e16c2f3
Synchronized with git revision 8724eb616b6e07a3bd111d3022652eb5bbefe9b7



Full URL: https://github.com/mbedmicro/mbed/commit/8724eb616b6e07a3bd111d3022652eb5bbefe9b7/



[RZ/A1H] mbed-RZ first release

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 35:a8484e16c2f3 1 /*******************************************************************************
mbed_official 35:a8484e16c2f3 2 * DISCLAIMER
mbed_official 35:a8484e16c2f3 3 * This software is supplied by Renesas Electronics Corporation and is only
mbed_official 35:a8484e16c2f3 4 * intended for use with Renesas products. No other uses are authorized. This
mbed_official 35:a8484e16c2f3 5 * software is owned by Renesas Electronics Corporation and is protected under
mbed_official 35:a8484e16c2f3 6 * all applicable laws, including copyright laws.
mbed_official 35:a8484e16c2f3 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
mbed_official 35:a8484e16c2f3 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
mbed_official 35:a8484e16c2f3 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
mbed_official 35:a8484e16c2f3 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
mbed_official 35:a8484e16c2f3 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
mbed_official 35:a8484e16c2f3 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
mbed_official 35:a8484e16c2f3 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
mbed_official 35:a8484e16c2f3 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
mbed_official 35:a8484e16c2f3 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
mbed_official 35:a8484e16c2f3 16 * Renesas reserves the right, without notice, to make changes to this software
mbed_official 35:a8484e16c2f3 17 * and to discontinue the availability of this software. By using this software,
mbed_official 35:a8484e16c2f3 18 * you agree to the additional terms and conditions found by accessing the
mbed_official 35:a8484e16c2f3 19 * following link:
mbed_official 35:a8484e16c2f3 20 * http://www.renesas.com/disclaimer
mbed_official 35:a8484e16c2f3 21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
mbed_official 35:a8484e16c2f3 22 *******************************************************************************/
mbed_official 35:a8484e16c2f3 23 /*******************************************************************************
mbed_official 35:a8484e16c2f3 24 * File Name : usb0_function_dmacdrv.c
mbed_official 35:a8484e16c2f3 25 * $Rev: 1116 $
mbed_official 35:a8484e16c2f3 26 * $Date:: 2014-07-09 16:29:19 +0900#$
mbed_official 35:a8484e16c2f3 27 * Device(s) : RZ/A1H
mbed_official 35:a8484e16c2f3 28 * Tool-Chain :
mbed_official 35:a8484e16c2f3 29 * OS : None
mbed_official 35:a8484e16c2f3 30 * H/W Platform :
mbed_official 35:a8484e16c2f3 31 * Description : RZ/A1H R7S72100 USB Sample Program
mbed_official 35:a8484e16c2f3 32 * Operation :
mbed_official 35:a8484e16c2f3 33 * Limitations :
mbed_official 35:a8484e16c2f3 34 *******************************************************************************/
mbed_official 35:a8484e16c2f3 35
mbed_official 35:a8484e16c2f3 36
mbed_official 35:a8484e16c2f3 37 /*******************************************************************************
mbed_official 35:a8484e16c2f3 38 Includes <System Includes> , "Project Includes"
mbed_official 35:a8484e16c2f3 39 *******************************************************************************/
mbed_official 35:a8484e16c2f3 40 #include <stdio.h>
mbed_official 35:a8484e16c2f3 41 #include "r_typedefs.h"
mbed_official 35:a8484e16c2f3 42 #include "iodefine.h"
mbed_official 35:a8484e16c2f3 43 #include "rza_io_regrw.h"
mbed_official 35:a8484e16c2f3 44 #include "usb0_function_dmacdrv.h"
mbed_official 35:a8484e16c2f3 45
mbed_official 35:a8484e16c2f3 46
mbed_official 35:a8484e16c2f3 47 /*******************************************************************************
mbed_official 35:a8484e16c2f3 48 Typedef definitions
mbed_official 35:a8484e16c2f3 49 *******************************************************************************/
mbed_official 35:a8484e16c2f3 50
mbed_official 35:a8484e16c2f3 51
mbed_official 35:a8484e16c2f3 52 /*******************************************************************************
mbed_official 35:a8484e16c2f3 53 Macro definitions
mbed_official 35:a8484e16c2f3 54 *******************************************************************************/
mbed_official 35:a8484e16c2f3 55 #define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */
mbed_official 35:a8484e16c2f3 56
mbed_official 35:a8484e16c2f3 57 /* ==== Request setting information for on-chip peripheral module ==== */
mbed_official 35:a8484e16c2f3 58 typedef enum dmac_peri_req_reg_type
mbed_official 35:a8484e16c2f3 59 {
mbed_official 35:a8484e16c2f3 60 DMAC_REQ_MID,
mbed_official 35:a8484e16c2f3 61 DMAC_REQ_RID,
mbed_official 35:a8484e16c2f3 62 DMAC_REQ_AM,
mbed_official 35:a8484e16c2f3 63 DMAC_REQ_LVL,
mbed_official 35:a8484e16c2f3 64 DMAC_REQ_REQD
mbed_official 35:a8484e16c2f3 65 } dmac_peri_req_reg_type_t;
mbed_official 35:a8484e16c2f3 66
mbed_official 35:a8484e16c2f3 67
mbed_official 35:a8484e16c2f3 68 /*******************************************************************************
mbed_official 35:a8484e16c2f3 69 Imported global variables and functions (from other files)
mbed_official 35:a8484e16c2f3 70 *******************************************************************************/
mbed_official 35:a8484e16c2f3 71
mbed_official 35:a8484e16c2f3 72
mbed_official 35:a8484e16c2f3 73 /*******************************************************************************
mbed_official 35:a8484e16c2f3 74 Exported global variables and functions (to be accessed by other files)
mbed_official 35:a8484e16c2f3 75 *******************************************************************************/
mbed_official 35:a8484e16c2f3 76
mbed_official 35:a8484e16c2f3 77
mbed_official 35:a8484e16c2f3 78 /*******************************************************************************
mbed_official 35:a8484e16c2f3 79 Private global variables and functions
mbed_official 35:a8484e16c2f3 80 *******************************************************************************/
mbed_official 35:a8484e16c2f3 81 /* ==== Prototype declaration ==== */
mbed_official 35:a8484e16c2f3 82
mbed_official 35:a8484e16c2f3 83 /* ==== Global variable ==== */
mbed_official 35:a8484e16c2f3 84 /* On-chip peripheral module request setting table */
mbed_official 35:a8484e16c2f3 85 static const uint8_t usb0_function_dmac_peri_req_init_table[8][5] =
mbed_official 35:a8484e16c2f3 86 {
mbed_official 35:a8484e16c2f3 87 /* MID,RID,AM,LVL,REQD */
mbed_official 35:a8484e16c2f3 88 {32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */
mbed_official 35:a8484e16c2f3 89 {32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */
mbed_official 35:a8484e16c2f3 90 {33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */
mbed_official 35:a8484e16c2f3 91 {33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */
mbed_official 35:a8484e16c2f3 92 {34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */
mbed_official 35:a8484e16c2f3 93 {34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */
mbed_official 35:a8484e16c2f3 94 {35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */
mbed_official 35:a8484e16c2f3 95 {35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */
mbed_official 35:a8484e16c2f3 96 };
mbed_official 35:a8484e16c2f3 97
mbed_official 35:a8484e16c2f3 98
mbed_official 35:a8484e16c2f3 99 /*******************************************************************************
mbed_official 35:a8484e16c2f3 100 * Function Name: usb0_function_DMAC1_PeriReqInit
mbed_official 35:a8484e16c2f3 101 * Description : Sets the register mode for DMA mode and the on-chip peripheral
mbed_official 35:a8484e16c2f3 102 * : module request for transfer request for DMAC channel 1.
mbed_official 35:a8484e16c2f3 103 * : Executes DMAC initial setting using the DMA information
mbed_official 35:a8484e16c2f3 104 * : specified by the argument *trans_info and the enabled/disabled
mbed_official 35:a8484e16c2f3 105 * : continuous transfer specified by the argument continuation.
mbed_official 35:a8484e16c2f3 106 * : Registers DMAC channel 1 interrupt handler function and sets
mbed_official 35:a8484e16c2f3 107 * : the interrupt priority level. Then enables transfer completion
mbed_official 35:a8484e16c2f3 108 * : interrupt.
mbed_official 35:a8484e16c2f3 109 * Arguments : dmac_transinfo_t *trans_info : Setting information to DMAC register
mbed_official 35:a8484e16c2f3 110 * : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
mbed_official 35:a8484e16c2f3 111 * : uint32_t continuation : Set continuous transfer to be valid
mbed_official 35:a8484e16c2f3 112 * : after DMA transfer has been completed
mbed_official 35:a8484e16c2f3 113 * : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
mbed_official 35:a8484e16c2f3 114 * : DMAC_SAMPLE_SINGLE : Do not execute continuous transfer
mbed_official 35:a8484e16c2f3 115 * : uint32_t request_factor : Factor for on-chip peripheral module request
mbed_official 35:a8484e16c2f3 116 * : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
mbed_official 35:a8484e16c2f3 117 * : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
mbed_official 35:a8484e16c2f3 118 * : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
mbed_official 35:a8484e16c2f3 119 * : :
mbed_official 35:a8484e16c2f3 120 * : uint32_t req_direction: Setting value of CHCFG_n register REQD bit
mbed_official 35:a8484e16c2f3 121 * Return Value : none
mbed_official 35:a8484e16c2f3 122 *******************************************************************************/
mbed_official 35:a8484e16c2f3 123 void usb0_function_DMAC1_PeriReqInit (const dmac_transinfo_t * trans_info,
mbed_official 35:a8484e16c2f3 124 uint32_t dmamode, uint32_t continuation,
mbed_official 35:a8484e16c2f3 125 uint32_t request_factor, uint32_t req_direction)
mbed_official 35:a8484e16c2f3 126 {
mbed_official 35:a8484e16c2f3 127 /* ==== Register mode ==== */
mbed_official 35:a8484e16c2f3 128 if (DMAC_MODE_REGISTER == dmamode)
mbed_official 35:a8484e16c2f3 129 {
mbed_official 35:a8484e16c2f3 130 /* ==== Next0 register set ==== */
mbed_official 35:a8484e16c2f3 131 DMAC1.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
mbed_official 35:a8484e16c2f3 132 DMAC1.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
mbed_official 35:a8484e16c2f3 133 DMAC1.N0TB_n = trans_info->count; /* Total transfer byte count */
mbed_official 35:a8484e16c2f3 134
mbed_official 35:a8484e16c2f3 135 /* DAD : Transfer destination address counting direction */
mbed_official 35:a8484e16c2f3 136 /* SAD : Transfer source address counting direction */
mbed_official 35:a8484e16c2f3 137 /* DDS : Transfer destination transfer size */
mbed_official 35:a8484e16c2f3 138 /* SDS : Transfer source transfer size */
mbed_official 35:a8484e16c2f3 139 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:a8484e16c2f3 140 trans_info->daddr_dir,
mbed_official 35:a8484e16c2f3 141 DMAC1_CHCFG_n_DAD_SHIFT,
mbed_official 35:a8484e16c2f3 142 DMAC1_CHCFG_n_DAD);
mbed_official 35:a8484e16c2f3 143 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:a8484e16c2f3 144 trans_info->saddr_dir,
mbed_official 35:a8484e16c2f3 145 DMAC1_CHCFG_n_SAD_SHIFT,
mbed_official 35:a8484e16c2f3 146 DMAC1_CHCFG_n_SAD);
mbed_official 35:a8484e16c2f3 147 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:a8484e16c2f3 148 trans_info->dst_size,
mbed_official 35:a8484e16c2f3 149 DMAC1_CHCFG_n_DDS_SHIFT,
mbed_official 35:a8484e16c2f3 150 DMAC1_CHCFG_n_DDS);
mbed_official 35:a8484e16c2f3 151 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:a8484e16c2f3 152 trans_info->src_size,
mbed_official 35:a8484e16c2f3 153 DMAC1_CHCFG_n_SDS_SHIFT,
mbed_official 35:a8484e16c2f3 154 DMAC1_CHCFG_n_SDS);
mbed_official 35:a8484e16c2f3 155
mbed_official 35:a8484e16c2f3 156 /* DMS : Register mode */
mbed_official 35:a8484e16c2f3 157 /* RSEL : Select Next0 register set */
mbed_official 35:a8484e16c2f3 158 /* SBE : No discharge of buffer data when aborted */
mbed_official 35:a8484e16c2f3 159 /* DEM : No DMA interrupt mask */
mbed_official 35:a8484e16c2f3 160 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:a8484e16c2f3 161 0,
mbed_official 35:a8484e16c2f3 162 DMAC1_CHCFG_n_DMS_SHIFT,
mbed_official 35:a8484e16c2f3 163 DMAC1_CHCFG_n_DMS);
mbed_official 35:a8484e16c2f3 164 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:a8484e16c2f3 165 0,
mbed_official 35:a8484e16c2f3 166 DMAC1_CHCFG_n_RSEL_SHIFT,
mbed_official 35:a8484e16c2f3 167 DMAC1_CHCFG_n_RSEL);
mbed_official 35:a8484e16c2f3 168 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:a8484e16c2f3 169 0,
mbed_official 35:a8484e16c2f3 170 DMAC1_CHCFG_n_SBE_SHIFT,
mbed_official 35:a8484e16c2f3 171 DMAC1_CHCFG_n_SBE);
mbed_official 35:a8484e16c2f3 172 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:a8484e16c2f3 173 0,
mbed_official 35:a8484e16c2f3 174 DMAC1_CHCFG_n_DEM_SHIFT,
mbed_official 35:a8484e16c2f3 175 DMAC1_CHCFG_n_DEM);
mbed_official 35:a8484e16c2f3 176
mbed_official 35:a8484e16c2f3 177 /* ---- Continuous transfer ---- */
mbed_official 35:a8484e16c2f3 178 if (DMAC_SAMPLE_CONTINUATION == continuation)
mbed_official 35:a8484e16c2f3 179 {
mbed_official 35:a8484e16c2f3 180 /* REN : Execute continuous transfer */
mbed_official 35:a8484e16c2f3 181 /* RSW : Change register set when DMA transfer is completed. */
mbed_official 35:a8484e16c2f3 182 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:a8484e16c2f3 183 1,
mbed_official 35:a8484e16c2f3 184 DMAC1_CHCFG_n_REN_SHIFT,
mbed_official 35:a8484e16c2f3 185 DMAC1_CHCFG_n_REN);
mbed_official 35:a8484e16c2f3 186 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:a8484e16c2f3 187 1,
mbed_official 35:a8484e16c2f3 188 DMAC1_CHCFG_n_RSW_SHIFT,
mbed_official 35:a8484e16c2f3 189 DMAC1_CHCFG_n_RSW);
mbed_official 35:a8484e16c2f3 190 }
mbed_official 35:a8484e16c2f3 191 /* ---- Single transfer ---- */
mbed_official 35:a8484e16c2f3 192 else
mbed_official 35:a8484e16c2f3 193 {
mbed_official 35:a8484e16c2f3 194 /* REN : Do not execute continuous transfer */
mbed_official 35:a8484e16c2f3 195 /* RSW : Do not change register set when DMA transfer is completed. */
mbed_official 35:a8484e16c2f3 196 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:a8484e16c2f3 197 0,
mbed_official 35:a8484e16c2f3 198 DMAC1_CHCFG_n_REN_SHIFT,
mbed_official 35:a8484e16c2f3 199 DMAC1_CHCFG_n_REN);
mbed_official 35:a8484e16c2f3 200 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:a8484e16c2f3 201 0,
mbed_official 35:a8484e16c2f3 202 DMAC1_CHCFG_n_RSW_SHIFT,
mbed_official 35:a8484e16c2f3 203 DMAC1_CHCFG_n_RSW);
mbed_official 35:a8484e16c2f3 204 }
mbed_official 35:a8484e16c2f3 205
mbed_official 35:a8484e16c2f3 206 /* TM : Single transfer */
mbed_official 35:a8484e16c2f3 207 /* SEL : Channel setting */
mbed_official 35:a8484e16c2f3 208 /* HIEN, LOEN : On-chip peripheral module request */
mbed_official 35:a8484e16c2f3 209 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:a8484e16c2f3 210 0,
mbed_official 35:a8484e16c2f3 211 DMAC1_CHCFG_n_TM_SHIFT,
mbed_official 35:a8484e16c2f3 212 DMAC1_CHCFG_n_TM);
mbed_official 35:a8484e16c2f3 213 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:a8484e16c2f3 214 1,
mbed_official 35:a8484e16c2f3 215 DMAC1_CHCFG_n_SEL_SHIFT,
mbed_official 35:a8484e16c2f3 216 DMAC1_CHCFG_n_SEL);
mbed_official 35:a8484e16c2f3 217 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:a8484e16c2f3 218 1,
mbed_official 35:a8484e16c2f3 219 DMAC1_CHCFG_n_HIEN_SHIFT,
mbed_official 35:a8484e16c2f3 220 DMAC1_CHCFG_n_HIEN);
mbed_official 35:a8484e16c2f3 221 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:a8484e16c2f3 222 0,
mbed_official 35:a8484e16c2f3 223 DMAC1_CHCFG_n_LOEN_SHIFT,
mbed_official 35:a8484e16c2f3 224 DMAC1_CHCFG_n_LOEN);
mbed_official 35:a8484e16c2f3 225
mbed_official 35:a8484e16c2f3 226 /* ---- Set factor by specified on-chip peripheral module request ---- */
mbed_official 35:a8484e16c2f3 227 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:a8484e16c2f3 228 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
mbed_official 35:a8484e16c2f3 229 DMAC1_CHCFG_n_AM_SHIFT,
mbed_official 35:a8484e16c2f3 230 DMAC1_CHCFG_n_AM);
mbed_official 35:a8484e16c2f3 231 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:a8484e16c2f3 232 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
mbed_official 35:a8484e16c2f3 233 DMAC1_CHCFG_n_LVL_SHIFT,
mbed_official 35:a8484e16c2f3 234 DMAC1_CHCFG_n_LVL);
mbed_official 35:a8484e16c2f3 235
mbed_official 35:a8484e16c2f3 236 if (usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
mbed_official 35:a8484e16c2f3 237 {
mbed_official 35:a8484e16c2f3 238 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:a8484e16c2f3 239 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
mbed_official 35:a8484e16c2f3 240 DMAC1_CHCFG_n_REQD_SHIFT,
mbed_official 35:a8484e16c2f3 241 DMAC1_CHCFG_n_REQD);
mbed_official 35:a8484e16c2f3 242 }
mbed_official 35:a8484e16c2f3 243 else
mbed_official 35:a8484e16c2f3 244 {
mbed_official 35:a8484e16c2f3 245 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:a8484e16c2f3 246 req_direction,
mbed_official 35:a8484e16c2f3 247 DMAC1_CHCFG_n_REQD_SHIFT,
mbed_official 35:a8484e16c2f3 248 DMAC1_CHCFG_n_REQD);
mbed_official 35:a8484e16c2f3 249 }
mbed_official 35:a8484e16c2f3 250
mbed_official 35:a8484e16c2f3 251 RZA_IO_RegWrite_32(&DMAC01.DMARS,
mbed_official 35:a8484e16c2f3 252 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
mbed_official 35:a8484e16c2f3 253 DMAC01_DMARS_CH1_RID_SHIFT,
mbed_official 35:a8484e16c2f3 254 DMAC01_DMARS_CH1_RID);
mbed_official 35:a8484e16c2f3 255 RZA_IO_RegWrite_32(&DMAC01.DMARS,
mbed_official 35:a8484e16c2f3 256 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
mbed_official 35:a8484e16c2f3 257 DMAC01_DMARS_CH1_MID_SHIFT,
mbed_official 35:a8484e16c2f3 258 DMAC01_DMARS_CH1_MID);
mbed_official 35:a8484e16c2f3 259
mbed_official 35:a8484e16c2f3 260 /* PR : Round robin mode */
mbed_official 35:a8484e16c2f3 261 RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
mbed_official 35:a8484e16c2f3 262 1,
mbed_official 35:a8484e16c2f3 263 DMAC07_DCTRL_0_7_PR_SHIFT,
mbed_official 35:a8484e16c2f3 264 DMAC07_DCTRL_0_7_PR);
mbed_official 35:a8484e16c2f3 265 }
mbed_official 35:a8484e16c2f3 266 }
mbed_official 35:a8484e16c2f3 267
mbed_official 35:a8484e16c2f3 268 /*******************************************************************************
mbed_official 35:a8484e16c2f3 269 * Function Name: usb0_function_DMAC1_Open
mbed_official 35:a8484e16c2f3 270 * Description : Enables DMAC channel 1 transfer.
mbed_official 35:a8484e16c2f3 271 * Arguments : uint32_t req : DMAC request mode
mbed_official 35:a8484e16c2f3 272 * Return Value : 0 : Succeeded in enabling DMA transfer
mbed_official 35:a8484e16c2f3 273 * : -1 : Failed to enable DMA transfer (due to DMA operation)
mbed_official 35:a8484e16c2f3 274 *******************************************************************************/
mbed_official 35:a8484e16c2f3 275 int32_t usb0_function_DMAC1_Open (uint32_t req)
mbed_official 35:a8484e16c2f3 276 {
mbed_official 35:a8484e16c2f3 277 int32_t ret;
mbed_official 35:a8484e16c2f3 278 volatile uint8_t dummy;
mbed_official 35:a8484e16c2f3 279
mbed_official 35:a8484e16c2f3 280 /* Transferable? */
mbed_official 35:a8484e16c2f3 281 if ((0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
mbed_official 35:a8484e16c2f3 282 DMAC1_CHSTAT_n_EN_SHIFT,
mbed_official 35:a8484e16c2f3 283 DMAC1_CHSTAT_n_EN)) &&
mbed_official 35:a8484e16c2f3 284 (0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
mbed_official 35:a8484e16c2f3 285 DMAC1_CHSTAT_n_TACT_SHIFT,
mbed_official 35:a8484e16c2f3 286 DMAC1_CHSTAT_n_TACT)))
mbed_official 35:a8484e16c2f3 287 {
mbed_official 35:a8484e16c2f3 288 /* Clear Channel Status Register */
mbed_official 35:a8484e16c2f3 289 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
mbed_official 35:a8484e16c2f3 290 1,
mbed_official 35:a8484e16c2f3 291 DMAC1_CHCTRL_n_SWRST_SHIFT,
mbed_official 35:a8484e16c2f3 292 DMAC1_CHCTRL_n_SWRST);
mbed_official 35:a8484e16c2f3 293 dummy = RZA_IO_RegRead_32(&DMAC1.CHCTRL_n,
mbed_official 35:a8484e16c2f3 294 DMAC1_CHCTRL_n_SWRST_SHIFT,
mbed_official 35:a8484e16c2f3 295 DMAC1_CHCTRL_n_SWRST);
mbed_official 35:a8484e16c2f3 296 /* Enable DMA transfer */
mbed_official 35:a8484e16c2f3 297 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
mbed_official 35:a8484e16c2f3 298 1,
mbed_official 35:a8484e16c2f3 299 DMAC1_CHCTRL_n_SETEN_SHIFT,
mbed_official 35:a8484e16c2f3 300 DMAC1_CHCTRL_n_SETEN);
mbed_official 35:a8484e16c2f3 301
mbed_official 35:a8484e16c2f3 302 /* ---- Request by software ---- */
mbed_official 35:a8484e16c2f3 303 if (DMAC_REQ_MODE_SOFT == req)
mbed_official 35:a8484e16c2f3 304 {
mbed_official 35:a8484e16c2f3 305 /* DMA transfer Request by software */
mbed_official 35:a8484e16c2f3 306 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
mbed_official 35:a8484e16c2f3 307 1,
mbed_official 35:a8484e16c2f3 308 DMAC1_CHCTRL_n_STG_SHIFT,
mbed_official 35:a8484e16c2f3 309 DMAC1_CHCTRL_n_STG);
mbed_official 35:a8484e16c2f3 310 }
mbed_official 35:a8484e16c2f3 311
mbed_official 35:a8484e16c2f3 312 ret = 0;
mbed_official 35:a8484e16c2f3 313 }
mbed_official 35:a8484e16c2f3 314 else
mbed_official 35:a8484e16c2f3 315 {
mbed_official 35:a8484e16c2f3 316 ret = -1;
mbed_official 35:a8484e16c2f3 317 }
mbed_official 35:a8484e16c2f3 318
mbed_official 35:a8484e16c2f3 319 return ret;
mbed_official 35:a8484e16c2f3 320 }
mbed_official 35:a8484e16c2f3 321
mbed_official 35:a8484e16c2f3 322 /*******************************************************************************
mbed_official 35:a8484e16c2f3 323 * Function Name: usb0_function_DMAC1_Close
mbed_official 35:a8484e16c2f3 324 * Description : Aborts DMAC channel 1 transfer. Returns the remaining transfer
mbed_official 35:a8484e16c2f3 325 * : byte count at the time of DMA transfer abort to the argument
mbed_official 35:a8484e16c2f3 326 * : *remain.
mbed_official 35:a8484e16c2f3 327 * Arguments : uint32_t * remain : Remaining transfer byte count when
mbed_official 35:a8484e16c2f3 328 * : : DMA transfer is aborted
mbed_official 35:a8484e16c2f3 329 * Return Value : none
mbed_official 35:a8484e16c2f3 330 *******************************************************************************/
mbed_official 35:a8484e16c2f3 331 void usb0_function_DMAC1_Close (uint32_t * remain)
mbed_official 35:a8484e16c2f3 332 {
mbed_official 35:a8484e16c2f3 333
mbed_official 35:a8484e16c2f3 334 /* ==== Abort transfer ==== */
mbed_official 35:a8484e16c2f3 335 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
mbed_official 35:a8484e16c2f3 336 1,
mbed_official 35:a8484e16c2f3 337 DMAC1_CHCTRL_n_CLREN_SHIFT,
mbed_official 35:a8484e16c2f3 338 DMAC1_CHCTRL_n_CLREN);
mbed_official 35:a8484e16c2f3 339
mbed_official 35:a8484e16c2f3 340 while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
mbed_official 35:a8484e16c2f3 341 DMAC1_CHSTAT_n_TACT_SHIFT,
mbed_official 35:a8484e16c2f3 342 DMAC1_CHSTAT_n_TACT))
mbed_official 35:a8484e16c2f3 343 {
mbed_official 35:a8484e16c2f3 344 /* Loop until transfer is aborted */
mbed_official 35:a8484e16c2f3 345 }
mbed_official 35:a8484e16c2f3 346
mbed_official 35:a8484e16c2f3 347 while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
mbed_official 35:a8484e16c2f3 348 DMAC1_CHSTAT_n_EN_SHIFT,
mbed_official 35:a8484e16c2f3 349 DMAC1_CHSTAT_n_EN))
mbed_official 35:a8484e16c2f3 350 {
mbed_official 35:a8484e16c2f3 351 /* Loop until 0 is set in EN before checking the remaining transfer byte count */
mbed_official 35:a8484e16c2f3 352 }
mbed_official 35:a8484e16c2f3 353 /* ==== Obtain remaining transfer byte count ==== */
mbed_official 35:a8484e16c2f3 354 *remain = DMAC1.CRTB_n;
mbed_official 35:a8484e16c2f3 355 }
mbed_official 35:a8484e16c2f3 356
mbed_official 35:a8484e16c2f3 357 /*******************************************************************************
mbed_official 35:a8484e16c2f3 358 * Function Name: usb0_function_DMAC1_Load_Set
mbed_official 35:a8484e16c2f3 359 * Description : Sets the transfer source address, transfer destination
mbed_official 35:a8484e16c2f3 360 * : address, and total transfer byte count respectively
mbed_official 35:a8484e16c2f3 361 * : specified by the argument src_addr, dst_addr, and count to
mbed_official 35:a8484e16c2f3 362 * : DMAC channel 1 as DMA transfer information.
mbed_official 35:a8484e16c2f3 363 * : Sets the register set selected by the CHCFG_n register
mbed_official 35:a8484e16c2f3 364 * : RSEL bit from the Next0 or Next1 register set.
mbed_official 35:a8484e16c2f3 365 * : This function should be called when DMA transfer of DMAC
mbed_official 35:a8484e16c2f3 366 * : channel 1 is aboted.
mbed_official 35:a8484e16c2f3 367 * Arguments : uint32_t src_addr : Transfer source address
mbed_official 35:a8484e16c2f3 368 * : uint32_t dst_addr : Transfer destination address
mbed_official 35:a8484e16c2f3 369 * : uint32_t count : Total transfer byte count
mbed_official 35:a8484e16c2f3 370 * Return Value : none
mbed_official 35:a8484e16c2f3 371 *******************************************************************************/
mbed_official 35:a8484e16c2f3 372 void usb0_function_DMAC1_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
mbed_official 35:a8484e16c2f3 373 {
mbed_official 35:a8484e16c2f3 374 uint8_t reg_set;
mbed_official 35:a8484e16c2f3 375
mbed_official 35:a8484e16c2f3 376 /* Obtain register set in use */
mbed_official 35:a8484e16c2f3 377 reg_set = RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
mbed_official 35:a8484e16c2f3 378 DMAC1_CHSTAT_n_SR_SHIFT,
mbed_official 35:a8484e16c2f3 379 DMAC1_CHSTAT_n_SR);
mbed_official 35:a8484e16c2f3 380
mbed_official 35:a8484e16c2f3 381 /* ==== Load ==== */
mbed_official 35:a8484e16c2f3 382 if (0 == reg_set)
mbed_official 35:a8484e16c2f3 383 {
mbed_official 35:a8484e16c2f3 384 /* ---- Next0 Register Set ---- */
mbed_official 35:a8484e16c2f3 385 DMAC1.N0SA_n = src_addr; /* Start address of transfer source */
mbed_official 35:a8484e16c2f3 386 DMAC1.N0DA_n = dst_addr; /* Start address of transfer destination */
mbed_official 35:a8484e16c2f3 387 DMAC1.N0TB_n = count; /* Total transfer byte count */
mbed_official 35:a8484e16c2f3 388 }
mbed_official 35:a8484e16c2f3 389 else
mbed_official 35:a8484e16c2f3 390 {
mbed_official 35:a8484e16c2f3 391 /* ---- Next1 Register Set ---- */
mbed_official 35:a8484e16c2f3 392 DMAC1.N1SA_n = src_addr; /* Start address of transfer source */
mbed_official 35:a8484e16c2f3 393 DMAC1.N1DA_n = dst_addr; /* Start address of transfer destination */
mbed_official 35:a8484e16c2f3 394 DMAC1.N1TB_n = count; /* Total transfer byte count */
mbed_official 35:a8484e16c2f3 395 }
mbed_official 35:a8484e16c2f3 396 }
mbed_official 35:a8484e16c2f3 397
mbed_official 35:a8484e16c2f3 398 /*******************************************************************************
mbed_official 35:a8484e16c2f3 399 * Function Name: usb0_function_DMAC2_PeriReqInit
mbed_official 35:a8484e16c2f3 400 * Description : Sets the register mode for DMA mode and the on-chip peripheral
mbed_official 35:a8484e16c2f3 401 * : module request for transfer request for DMAC channel 2.
mbed_official 35:a8484e16c2f3 402 * : Executes DMAC initial setting using the DMA information
mbed_official 35:a8484e16c2f3 403 * : specified by the argument *trans_info and the enabled/disabled
mbed_official 35:a8484e16c2f3 404 * : continuous transfer specified by the argument continuation.
mbed_official 35:a8484e16c2f3 405 * : Registers DMAC channel 2 interrupt handler function and sets
mbed_official 35:a8484e16c2f3 406 * : the interrupt priority level. Then enables transfer completion
mbed_official 35:a8484e16c2f3 407 * : interrupt.
mbed_official 35:a8484e16c2f3 408 * Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
mbed_official 35:a8484e16c2f3 409 * : : register
mbed_official 35:a8484e16c2f3 410 * : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
mbed_official 35:a8484e16c2f3 411 * : uint32_t continuation : Set continuous transfer to be valid
mbed_official 35:a8484e16c2f3 412 * : : after DMA transfer has been completed
mbed_official 35:a8484e16c2f3 413 * : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
mbed_official 35:a8484e16c2f3 414 * : DMAC_SAMPLE_SINGLE : Do not execute continuous
mbed_official 35:a8484e16c2f3 415 * : : transfer
mbed_official 35:a8484e16c2f3 416 * : uint32_t request_factor : Factor for on-chip peripheral module
mbed_official 35:a8484e16c2f3 417 * : : request
mbed_official 35:a8484e16c2f3 418 * : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
mbed_official 35:a8484e16c2f3 419 * : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
mbed_official 35:a8484e16c2f3 420 * : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
mbed_official 35:a8484e16c2f3 421 * : :
mbed_official 35:a8484e16c2f3 422 * : uint32_t req_direction : Setting value of CHCFG_n register
mbed_official 35:a8484e16c2f3 423 * : : REQD bit
mbed_official 35:a8484e16c2f3 424 *******************************************************************************/
mbed_official 35:a8484e16c2f3 425 void usb0_function_DMAC2_PeriReqInit (const dmac_transinfo_t * trans_info,
mbed_official 35:a8484e16c2f3 426 uint32_t dmamode, uint32_t continuation,
mbed_official 35:a8484e16c2f3 427 uint32_t request_factor, uint32_t req_direction)
mbed_official 35:a8484e16c2f3 428 {
mbed_official 35:a8484e16c2f3 429 /* ==== Register mode ==== */
mbed_official 35:a8484e16c2f3 430 if (DMAC_MODE_REGISTER == dmamode)
mbed_official 35:a8484e16c2f3 431 {
mbed_official 35:a8484e16c2f3 432 /* ==== Next0 register set ==== */
mbed_official 35:a8484e16c2f3 433 DMAC2.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
mbed_official 35:a8484e16c2f3 434 DMAC2.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
mbed_official 35:a8484e16c2f3 435 DMAC2.N0TB_n = trans_info->count; /* Total transfer byte count */
mbed_official 35:a8484e16c2f3 436
mbed_official 35:a8484e16c2f3 437 /* DAD : Transfer destination address counting direction */
mbed_official 35:a8484e16c2f3 438 /* SAD : Transfer source address counting direction */
mbed_official 35:a8484e16c2f3 439 /* DDS : Transfer destination transfer size */
mbed_official 35:a8484e16c2f3 440 /* SDS : Transfer source transfer size */
mbed_official 35:a8484e16c2f3 441 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:a8484e16c2f3 442 trans_info->daddr_dir,
mbed_official 35:a8484e16c2f3 443 DMAC2_CHCFG_n_DAD_SHIFT,
mbed_official 35:a8484e16c2f3 444 DMAC2_CHCFG_n_DAD);
mbed_official 35:a8484e16c2f3 445 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:a8484e16c2f3 446 trans_info->saddr_dir,
mbed_official 35:a8484e16c2f3 447 DMAC2_CHCFG_n_SAD_SHIFT,
mbed_official 35:a8484e16c2f3 448 DMAC2_CHCFG_n_SAD);
mbed_official 35:a8484e16c2f3 449 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:a8484e16c2f3 450 trans_info->dst_size,
mbed_official 35:a8484e16c2f3 451 DMAC2_CHCFG_n_DDS_SHIFT,
mbed_official 35:a8484e16c2f3 452 DMAC2_CHCFG_n_DDS);
mbed_official 35:a8484e16c2f3 453 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:a8484e16c2f3 454 trans_info->src_size,
mbed_official 35:a8484e16c2f3 455 DMAC2_CHCFG_n_SDS_SHIFT,
mbed_official 35:a8484e16c2f3 456 DMAC2_CHCFG_n_SDS);
mbed_official 35:a8484e16c2f3 457
mbed_official 35:a8484e16c2f3 458 /* DMS : Register mode */
mbed_official 35:a8484e16c2f3 459 /* RSEL : Select Next0 register set */
mbed_official 35:a8484e16c2f3 460 /* SBE : No discharge of buffer data when aborted */
mbed_official 35:a8484e16c2f3 461 /* DEM : No DMA interrupt mask */
mbed_official 35:a8484e16c2f3 462 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:a8484e16c2f3 463 0,
mbed_official 35:a8484e16c2f3 464 DMAC2_CHCFG_n_DMS_SHIFT,
mbed_official 35:a8484e16c2f3 465 DMAC2_CHCFG_n_DMS);
mbed_official 35:a8484e16c2f3 466 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:a8484e16c2f3 467 0,
mbed_official 35:a8484e16c2f3 468 DMAC2_CHCFG_n_RSEL_SHIFT,
mbed_official 35:a8484e16c2f3 469 DMAC2_CHCFG_n_RSEL);
mbed_official 35:a8484e16c2f3 470 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:a8484e16c2f3 471 0,
mbed_official 35:a8484e16c2f3 472 DMAC2_CHCFG_n_SBE_SHIFT,
mbed_official 35:a8484e16c2f3 473 DMAC2_CHCFG_n_SBE);
mbed_official 35:a8484e16c2f3 474 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:a8484e16c2f3 475 0,
mbed_official 35:a8484e16c2f3 476 DMAC2_CHCFG_n_DEM_SHIFT,
mbed_official 35:a8484e16c2f3 477 DMAC2_CHCFG_n_DEM);
mbed_official 35:a8484e16c2f3 478
mbed_official 35:a8484e16c2f3 479 /* ---- Continuous transfer ---- */
mbed_official 35:a8484e16c2f3 480 if (DMAC_SAMPLE_CONTINUATION == continuation)
mbed_official 35:a8484e16c2f3 481 {
mbed_official 35:a8484e16c2f3 482 /* REN : Execute continuous transfer */
mbed_official 35:a8484e16c2f3 483 /* RSW : Change register set when DMA transfer is completed. */
mbed_official 35:a8484e16c2f3 484 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:a8484e16c2f3 485 1,
mbed_official 35:a8484e16c2f3 486 DMAC2_CHCFG_n_REN_SHIFT,
mbed_official 35:a8484e16c2f3 487 DMAC2_CHCFG_n_REN);
mbed_official 35:a8484e16c2f3 488 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:a8484e16c2f3 489 1,
mbed_official 35:a8484e16c2f3 490 DMAC2_CHCFG_n_RSW_SHIFT,
mbed_official 35:a8484e16c2f3 491 DMAC2_CHCFG_n_RSW);
mbed_official 35:a8484e16c2f3 492 }
mbed_official 35:a8484e16c2f3 493 /* ---- Single transfer ---- */
mbed_official 35:a8484e16c2f3 494 else
mbed_official 35:a8484e16c2f3 495 {
mbed_official 35:a8484e16c2f3 496 /* REN : Do not execute continuous transfer */
mbed_official 35:a8484e16c2f3 497 /* RSW : Do not change register set when DMA transfer is completed. */
mbed_official 35:a8484e16c2f3 498 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:a8484e16c2f3 499 0,
mbed_official 35:a8484e16c2f3 500 DMAC2_CHCFG_n_REN_SHIFT,
mbed_official 35:a8484e16c2f3 501 DMAC2_CHCFG_n_REN);
mbed_official 35:a8484e16c2f3 502 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:a8484e16c2f3 503 0,
mbed_official 35:a8484e16c2f3 504 DMAC2_CHCFG_n_RSW_SHIFT,
mbed_official 35:a8484e16c2f3 505 DMAC2_CHCFG_n_RSW);
mbed_official 35:a8484e16c2f3 506 }
mbed_official 35:a8484e16c2f3 507
mbed_official 35:a8484e16c2f3 508 /* TM : Single transfer */
mbed_official 35:a8484e16c2f3 509 /* SEL : Channel setting */
mbed_official 35:a8484e16c2f3 510 /* HIEN, LOEN : On-chip peripheral module request */
mbed_official 35:a8484e16c2f3 511 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:a8484e16c2f3 512 0,
mbed_official 35:a8484e16c2f3 513 DMAC2_CHCFG_n_TM_SHIFT,
mbed_official 35:a8484e16c2f3 514 DMAC2_CHCFG_n_TM);
mbed_official 35:a8484e16c2f3 515 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:a8484e16c2f3 516 2,
mbed_official 35:a8484e16c2f3 517 DMAC2_CHCFG_n_SEL_SHIFT,
mbed_official 35:a8484e16c2f3 518 DMAC2_CHCFG_n_SEL);
mbed_official 35:a8484e16c2f3 519 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:a8484e16c2f3 520 1,
mbed_official 35:a8484e16c2f3 521 DMAC2_CHCFG_n_HIEN_SHIFT,
mbed_official 35:a8484e16c2f3 522 DMAC2_CHCFG_n_HIEN);
mbed_official 35:a8484e16c2f3 523 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:a8484e16c2f3 524 0,
mbed_official 35:a8484e16c2f3 525 DMAC2_CHCFG_n_LOEN_SHIFT,
mbed_official 35:a8484e16c2f3 526 DMAC2_CHCFG_n_LOEN);
mbed_official 35:a8484e16c2f3 527
mbed_official 35:a8484e16c2f3 528 /* ---- Set factor by specified on-chip peripheral module request ---- */
mbed_official 35:a8484e16c2f3 529 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:a8484e16c2f3 530 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
mbed_official 35:a8484e16c2f3 531 DMAC2_CHCFG_n_AM_SHIFT,
mbed_official 35:a8484e16c2f3 532 DMAC2_CHCFG_n_AM);
mbed_official 35:a8484e16c2f3 533 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:a8484e16c2f3 534 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
mbed_official 35:a8484e16c2f3 535 DMAC2_CHCFG_n_LVL_SHIFT,
mbed_official 35:a8484e16c2f3 536 DMAC2_CHCFG_n_LVL);
mbed_official 35:a8484e16c2f3 537 if (usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
mbed_official 35:a8484e16c2f3 538 {
mbed_official 35:a8484e16c2f3 539 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:a8484e16c2f3 540 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
mbed_official 35:a8484e16c2f3 541 DMAC2_CHCFG_n_REQD_SHIFT,
mbed_official 35:a8484e16c2f3 542 DMAC2_CHCFG_n_REQD);
mbed_official 35:a8484e16c2f3 543 }
mbed_official 35:a8484e16c2f3 544 else
mbed_official 35:a8484e16c2f3 545 {
mbed_official 35:a8484e16c2f3 546 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:a8484e16c2f3 547 req_direction,
mbed_official 35:a8484e16c2f3 548 DMAC2_CHCFG_n_REQD_SHIFT,
mbed_official 35:a8484e16c2f3 549 DMAC2_CHCFG_n_REQD);
mbed_official 35:a8484e16c2f3 550 }
mbed_official 35:a8484e16c2f3 551 RZA_IO_RegWrite_32(&DMAC23.DMARS,
mbed_official 35:a8484e16c2f3 552 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
mbed_official 35:a8484e16c2f3 553 DMAC23_DMARS_CH2_RID_SHIFT,
mbed_official 35:a8484e16c2f3 554 DMAC23_DMARS_CH2_RID);
mbed_official 35:a8484e16c2f3 555 RZA_IO_RegWrite_32(&DMAC23.DMARS,
mbed_official 35:a8484e16c2f3 556 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
mbed_official 35:a8484e16c2f3 557 DMAC23_DMARS_CH2_MID_SHIFT,
mbed_official 35:a8484e16c2f3 558 DMAC23_DMARS_CH2_MID);
mbed_official 35:a8484e16c2f3 559
mbed_official 35:a8484e16c2f3 560 /* PR : Round robin mode */
mbed_official 35:a8484e16c2f3 561 RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
mbed_official 35:a8484e16c2f3 562 1,
mbed_official 35:a8484e16c2f3 563 DMAC07_DCTRL_0_7_PR_SHIFT,
mbed_official 35:a8484e16c2f3 564 DMAC07_DCTRL_0_7_PR);
mbed_official 35:a8484e16c2f3 565 }
mbed_official 35:a8484e16c2f3 566 }
mbed_official 35:a8484e16c2f3 567
mbed_official 35:a8484e16c2f3 568 /*******************************************************************************
mbed_official 35:a8484e16c2f3 569 * Function Name: usb0_function_DMAC2_Open
mbed_official 35:a8484e16c2f3 570 * Description : Enables DMAC channel 2 transfer.
mbed_official 35:a8484e16c2f3 571 * Arguments : uint32_t req : DMAC request mode
mbed_official 35:a8484e16c2f3 572 * Return Value : 0 : Succeeded in enabling DMA transfer
mbed_official 35:a8484e16c2f3 573 * : -1 : Failed to enable DMA transfer (due to DMA operation)
mbed_official 35:a8484e16c2f3 574 *******************************************************************************/
mbed_official 35:a8484e16c2f3 575 int32_t usb0_function_DMAC2_Open (uint32_t req)
mbed_official 35:a8484e16c2f3 576 {
mbed_official 35:a8484e16c2f3 577 int32_t ret;
mbed_official 35:a8484e16c2f3 578 volatile uint8_t dummy;
mbed_official 35:a8484e16c2f3 579
mbed_official 35:a8484e16c2f3 580 /* Transferable? */
mbed_official 35:a8484e16c2f3 581 if ((0 == RZA_IO_RegRead_32(&DMAC.CHSTAT_2,
mbed_official 35:a8484e16c2f3 582 DMAC2_CHSTAT_n_EN_SHIFT,
mbed_official 35:a8484e16c2f3 583 DMAC2_CHSTAT_n_EN)) &&
mbed_official 35:a8484e16c2f3 584 (0 == RZA_IO_RegRead_32(&DMAC.CHSTAT_2,
mbed_official 35:a8484e16c2f3 585 DMAC2_CHSTAT_n_TACT_SHIFT,
mbed_official 35:a8484e16c2f3 586 DMAC2_CHSTAT_n_TACT)))
mbed_official 35:a8484e16c2f3 587 {
mbed_official 35:a8484e16c2f3 588 /* Clear Channel Status Register */
mbed_official 35:a8484e16c2f3 589 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
mbed_official 35:a8484e16c2f3 590 1,
mbed_official 35:a8484e16c2f3 591 DMAC2_CHCTRL_n_SWRST_SHIFT,
mbed_official 35:a8484e16c2f3 592 DMAC2_CHCTRL_n_SWRST);
mbed_official 35:a8484e16c2f3 593 dummy = RZA_IO_RegRead_32(&DMAC2.CHCTRL_n,
mbed_official 35:a8484e16c2f3 594 DMAC2_CHCTRL_n_SWRST_SHIFT,
mbed_official 35:a8484e16c2f3 595 DMAC2_CHCTRL_n_SWRST);
mbed_official 35:a8484e16c2f3 596 /* Enable DMA transfer */
mbed_official 35:a8484e16c2f3 597 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
mbed_official 35:a8484e16c2f3 598 1,
mbed_official 35:a8484e16c2f3 599 DMAC2_CHCTRL_n_SETEN_SHIFT,
mbed_official 35:a8484e16c2f3 600 DMAC2_CHCTRL_n_SETEN);
mbed_official 35:a8484e16c2f3 601
mbed_official 35:a8484e16c2f3 602 /* ---- Request by software ---- */
mbed_official 35:a8484e16c2f3 603 if (DMAC_REQ_MODE_SOFT == req)
mbed_official 35:a8484e16c2f3 604 {
mbed_official 35:a8484e16c2f3 605 /* DMA transfer Request by software */
mbed_official 35:a8484e16c2f3 606 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
mbed_official 35:a8484e16c2f3 607 1,
mbed_official 35:a8484e16c2f3 608 DMAC2_CHCTRL_n_STG_SHIFT,
mbed_official 35:a8484e16c2f3 609 DMAC2_CHCTRL_n_STG);
mbed_official 35:a8484e16c2f3 610 }
mbed_official 35:a8484e16c2f3 611
mbed_official 35:a8484e16c2f3 612 ret = 0;
mbed_official 35:a8484e16c2f3 613 }
mbed_official 35:a8484e16c2f3 614 else
mbed_official 35:a8484e16c2f3 615 {
mbed_official 35:a8484e16c2f3 616 ret = -1;
mbed_official 35:a8484e16c2f3 617 }
mbed_official 35:a8484e16c2f3 618
mbed_official 35:a8484e16c2f3 619 return ret;
mbed_official 35:a8484e16c2f3 620 }
mbed_official 35:a8484e16c2f3 621
mbed_official 35:a8484e16c2f3 622 /*******************************************************************************
mbed_official 35:a8484e16c2f3 623 * Function Name: usb0_function_DMAC2_Close
mbed_official 35:a8484e16c2f3 624 * Description : Aborts DMAC channel 2 transfer. Returns the remaining transfer
mbed_official 35:a8484e16c2f3 625 * : byte count at the time of DMA transfer abort to the argument
mbed_official 35:a8484e16c2f3 626 * : *remain.
mbed_official 35:a8484e16c2f3 627 * Arguments : uint32_t * remain : Remaining transfer byte count when
mbed_official 35:a8484e16c2f3 628 * : : DMA transfer is aborted
mbed_official 35:a8484e16c2f3 629 * Return Value : none
mbed_official 35:a8484e16c2f3 630 *******************************************************************************/
mbed_official 35:a8484e16c2f3 631 void usb0_function_DMAC2_Close (uint32_t * remain)
mbed_official 35:a8484e16c2f3 632 {
mbed_official 35:a8484e16c2f3 633
mbed_official 35:a8484e16c2f3 634 /* ==== Abort transfer ==== */
mbed_official 35:a8484e16c2f3 635 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
mbed_official 35:a8484e16c2f3 636 1,
mbed_official 35:a8484e16c2f3 637 DMAC2_CHCTRL_n_CLREN_SHIFT,
mbed_official 35:a8484e16c2f3 638 DMAC2_CHCTRL_n_CLREN);
mbed_official 35:a8484e16c2f3 639
mbed_official 35:a8484e16c2f3 640 while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
mbed_official 35:a8484e16c2f3 641 DMAC2_CHSTAT_n_TACT_SHIFT,
mbed_official 35:a8484e16c2f3 642 DMAC2_CHSTAT_n_TACT))
mbed_official 35:a8484e16c2f3 643 {
mbed_official 35:a8484e16c2f3 644 /* Loop until transfer is aborted */
mbed_official 35:a8484e16c2f3 645 }
mbed_official 35:a8484e16c2f3 646
mbed_official 35:a8484e16c2f3 647 while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
mbed_official 35:a8484e16c2f3 648 DMAC2_CHSTAT_n_EN_SHIFT,
mbed_official 35:a8484e16c2f3 649 DMAC2_CHSTAT_n_EN))
mbed_official 35:a8484e16c2f3 650 {
mbed_official 35:a8484e16c2f3 651 /* Loop until 0 is set in EN before checking the remaining transfer byte count */
mbed_official 35:a8484e16c2f3 652 }
mbed_official 35:a8484e16c2f3 653 /* ==== Obtain remaining transfer byte count ==== */
mbed_official 35:a8484e16c2f3 654 *remain = DMAC2.CRTB_n;
mbed_official 35:a8484e16c2f3 655 }
mbed_official 35:a8484e16c2f3 656
mbed_official 35:a8484e16c2f3 657 /*******************************************************************************
mbed_official 35:a8484e16c2f3 658 * Function Name: usb0_function_DMAC2_Load_Set
mbed_official 35:a8484e16c2f3 659 * Description : Sets the transfer source address, transfer destination
mbed_official 35:a8484e16c2f3 660 * : address, and total transfer byte count respectively
mbed_official 35:a8484e16c2f3 661 * : specified by the argument src_addr, dst_addr, and count to
mbed_official 35:a8484e16c2f3 662 * : DMAC channel 2 as DMA transfer information.
mbed_official 35:a8484e16c2f3 663 * : Sets the register set selected by the CHCFG_n register
mbed_official 35:a8484e16c2f3 664 * : RSEL bit from the Next0 or Next1 register set.
mbed_official 35:a8484e16c2f3 665 * : This function should be called when DMA transfer of DMAC
mbed_official 35:a8484e16c2f3 666 * : channel 2 is aboted.
mbed_official 35:a8484e16c2f3 667 * Arguments : uint32_t src_addr : Transfer source address
mbed_official 35:a8484e16c2f3 668 * : uint32_t dst_addr : Transfer destination address
mbed_official 35:a8484e16c2f3 669 * : uint32_t count : Total transfer byte count
mbed_official 35:a8484e16c2f3 670 * Return Value : none
mbed_official 35:a8484e16c2f3 671 *******************************************************************************/
mbed_official 35:a8484e16c2f3 672 void usb0_function_DMAC2_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
mbed_official 35:a8484e16c2f3 673 {
mbed_official 35:a8484e16c2f3 674 uint8_t reg_set;
mbed_official 35:a8484e16c2f3 675
mbed_official 35:a8484e16c2f3 676 /* Obtain register set in use */
mbed_official 35:a8484e16c2f3 677 reg_set = RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
mbed_official 35:a8484e16c2f3 678 DMAC2_CHSTAT_n_SR_SHIFT,
mbed_official 35:a8484e16c2f3 679 DMAC2_CHSTAT_n_SR);
mbed_official 35:a8484e16c2f3 680
mbed_official 35:a8484e16c2f3 681 /* ==== Load ==== */
mbed_official 35:a8484e16c2f3 682 if (0 == reg_set)
mbed_official 35:a8484e16c2f3 683 {
mbed_official 35:a8484e16c2f3 684 /* ---- Next0 Register Set ---- */
mbed_official 35:a8484e16c2f3 685 DMAC2.N0SA_n = src_addr; /* Start address of transfer source */
mbed_official 35:a8484e16c2f3 686 DMAC2.N0DA_n = dst_addr; /* Start address of transfer destination */
mbed_official 35:a8484e16c2f3 687 DMAC2.N0TB_n = count; /* Total transfer byte count */
mbed_official 35:a8484e16c2f3 688 }
mbed_official 35:a8484e16c2f3 689 else
mbed_official 35:a8484e16c2f3 690 {
mbed_official 35:a8484e16c2f3 691 /* ---- Next1 Register Set ---- */
mbed_official 35:a8484e16c2f3 692 DMAC2.N1SA_n = src_addr; /* Start address of transfer source */
mbed_official 35:a8484e16c2f3 693 DMAC2.N1DA_n = dst_addr; /* Start address of transfer destination */
mbed_official 35:a8484e16c2f3 694 DMAC2.N1TB_n = count; /* Total transfer byte count */
mbed_official 35:a8484e16c2f3 695 }
mbed_official 35:a8484e16c2f3 696 }
mbed_official 35:a8484e16c2f3 697
mbed_official 35:a8484e16c2f3 698 /* End of File */