Maxim Integrated / USBDevice

USBDevice with MAX32620HSP platform support

Fork of USBDevice by mbed official

USBDevice/USBHAL_STM32F4.cpp@64:71deba5aa9e9, 2016-10-07 (annotated)

Committer:
enginerd
Date:
Fri Oct 07 15:33:16 2016 +0000
Revision:
64:71deba5aa9e9
Parent:
53:5534733abe31 
[MAX32620HSP] Added support for new platform

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 16:4f6df64750bd 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
mbed_official 16:4f6df64750bd 2 *
mbed_official 16:4f6df64750bd 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
mbed_official 16:4f6df64750bd 4 * and associated documentation files (the "Software"), to deal in the Software without
mbed_official 16:4f6df64750bd 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
mbed_official 16:4f6df64750bd 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
mbed_official 16:4f6df64750bd 7 * Software is furnished to do so, subject to the following conditions:
mbed_official 16:4f6df64750bd 8 *
mbed_official 16:4f6df64750bd 9 * The above copyright notice and this permission notice shall be included in all copies or
mbed_official 16:4f6df64750bd 10 * substantial portions of the Software.
mbed_official 16:4f6df64750bd 11 *
mbed_official 16:4f6df64750bd 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
mbed_official 16:4f6df64750bd 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
mbed_official 16:4f6df64750bd 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
mbed_official 16:4f6df64750bd 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
mbed_official 16:4f6df64750bd 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
mbed_official 16:4f6df64750bd 17 */
mbed_official 16:4f6df64750bd 18
mbed_official 31:5bf05f9b3c7b 19 #if defined(TARGET_STM32F4)
mbed_official 16:4f6df64750bd 20
mbed_official 16:4f6df64750bd 21 #include "USBHAL.h"
mbed_official 16:4f6df64750bd 22 #include "USBRegs_STM32.h"
mbed_official 16:4f6df64750bd 23 #include "pinmap.h"
mbed_official 16:4f6df64750bd 24
mbed_official 16:4f6df64750bd 25 USBHAL * USBHAL::instance;
mbed_official 16:4f6df64750bd 26
mbed_official 16:4f6df64750bd 27 static volatile int epComplete = 0;
mbed_official 16:4f6df64750bd 28
mbed_official 16:4f6df64750bd 29 static uint32_t bufferEnd = 0;
mbed_official 16:4f6df64750bd 30 static const uint32_t rxFifoSize = 512;
mbed_official 16:4f6df64750bd 31 static uint32_t rxFifoCount = 0;
mbed_official 16:4f6df64750bd 32
mbed_official 16:4f6df64750bd 33 static uint32_t setupBuffer[MAX_PACKET_SIZE_EP0 >> 2];
mbed_official 16:4f6df64750bd 34
mbed_official 16:4f6df64750bd 35 uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
mbed_official 16:4f6df64750bd 36 return 0;
mbed_official 16:4f6df64750bd 37 }
mbed_official 16:4f6df64750bd 38
mbed_official 25:7c72828865f3 39 USBHAL::USBHAL(void) {
mbed_official 16:4f6df64750bd 40 NVIC_DisableIRQ(OTG_FS_IRQn);
mbed_official 16:4f6df64750bd 41 epCallback[0] = &USBHAL::EP1_OUT_callback;
mbed_official 16:4f6df64750bd 42 epCallback[1] = &USBHAL::EP1_IN_callback;
mbed_official 16:4f6df64750bd 43 epCallback[2] = &USBHAL::EP2_OUT_callback;
mbed_official 16:4f6df64750bd 44 epCallback[3] = &USBHAL::EP2_IN_callback;
mbed_official 16:4f6df64750bd 45 epCallback[4] = &USBHAL::EP3_OUT_callback;
mbed_official 16:4f6df64750bd 46 epCallback[5] = &USBHAL::EP3_IN_callback;
mbed_official 16:4f6df64750bd 47
mbed_official 16:4f6df64750bd 48 // Enable power and clocking
mbed_official 16:4f6df64750bd 49 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
mbed_official 16:4f6df64750bd 50
mbed_official 53:5534733abe31 51 #if defined(TARGET_STM32F407VG) || defined(TARGET_STM32F401RE) || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F429ZI)
mbed_official 31:5bf05f9b3c7b 52 pin_function(PA_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
mbed_official 31:5bf05f9b3c7b 53 pin_function(PA_9, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLDOWN, GPIO_AF10_OTG_FS));
mbed_official 31:5bf05f9b3c7b 54 pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS));
mbed_official 31:5bf05f9b3c7b 55 pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
mbed_official 31:5bf05f9b3c7b 56 pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
mbed_official 31:5bf05f9b3c7b 57 #else
mbed_official 16:4f6df64750bd 58 pin_function(PA_8, STM_PIN_DATA(2, 10));
mbed_official 16:4f6df64750bd 59 pin_function(PA_9, STM_PIN_DATA(0, 0));
mbed_official 16:4f6df64750bd 60 pin_function(PA_10, STM_PIN_DATA(2, 10));
mbed_official 16:4f6df64750bd 61 pin_function(PA_11, STM_PIN_DATA(2, 10));
mbed_official 16:4f6df64750bd 62 pin_function(PA_12, STM_PIN_DATA(2, 10));
mbed_official 16:4f6df64750bd 63
mbed_official 16:4f6df64750bd 64 // Set ID pin to open drain with pull-up resistor
mbed_official 16:4f6df64750bd 65 pin_mode(PA_10, OpenDrain);
mbed_official 16:4f6df64750bd 66 GPIOA->PUPDR &= ~(0x3 << 20);
mbed_official 16:4f6df64750bd 67 GPIOA->PUPDR |= 1 << 20;
mbed_official 16:4f6df64750bd 68
mbed_official 16:4f6df64750bd 69 // Set VBUS pin to open drain
mbed_official 16:4f6df64750bd 70 pin_mode(PA_9, OpenDrain);
mbed_official 31:5bf05f9b3c7b 71 #endif
mbed_official 16:4f6df64750bd 72
mbed_official 16:4f6df64750bd 73 RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
mbed_official 25:7c72828865f3 74
mbed_official 16:4f6df64750bd 75 // Enable interrupts
mbed_official 16:4f6df64750bd 76 OTG_FS->GREGS.GAHBCFG |= (1 << 0);
mbed_official 16:4f6df64750bd 77
mbed_official 16:4f6df64750bd 78 // Turnaround time to maximum value - too small causes packet loss
mbed_official 16:4f6df64750bd 79 OTG_FS->GREGS.GUSBCFG |= (0xF << 10);
mbed_official 16:4f6df64750bd 80
mbed_official 16:4f6df64750bd 81 // Unmask global interrupts
mbed_official 16:4f6df64750bd 82 OTG_FS->GREGS.GINTMSK |= (1 << 3) | // SOF
mbed_official 16:4f6df64750bd 83 (1 << 4) | // RX FIFO not empty
mbed_official 16:4f6df64750bd 84 (1 << 12); // USB reset
mbed_official 16:4f6df64750bd 85
mbed_official 16:4f6df64750bd 86 OTG_FS->DREGS.DCFG |= (0x3 << 0) | // Full speed
mbed_official 16:4f6df64750bd 87 (1 << 2); // Non-zero-length status OUT handshake
mbed_official 16:4f6df64750bd 88
mbed_official 16:4f6df64750bd 89 OTG_FS->GREGS.GCCFG |= (1 << 19) | // Enable VBUS sensing
mbed_official 16:4f6df64750bd 90 (1 << 16); // Power Up
mbed_official 16:4f6df64750bd 91
mbed_official 16:4f6df64750bd 92 instance = this;
mbed_official 16:4f6df64750bd 93 NVIC_SetVector(OTG_FS_IRQn, (uint32_t)&_usbisr);
mbed_official 16:4f6df64750bd 94 NVIC_SetPriority(OTG_FS_IRQn, 1);
mbed_official 16:4f6df64750bd 95 }
mbed_official 16:4f6df64750bd 96
mbed_official 16:4f6df64750bd 97 USBHAL::~USBHAL(void) {
mbed_official 16:4f6df64750bd 98 }
mbed_official 16:4f6df64750bd 99
mbed_official 16:4f6df64750bd 100 void USBHAL::connect(void) {
mbed_official 16:4f6df64750bd 101 NVIC_EnableIRQ(OTG_FS_IRQn);
mbed_official 16:4f6df64750bd 102 }
mbed_official 16:4f6df64750bd 103
mbed_official 16:4f6df64750bd 104 void USBHAL::disconnect(void) {
mbed_official 16:4f6df64750bd 105 NVIC_DisableIRQ(OTG_FS_IRQn);
mbed_official 16:4f6df64750bd 106 }
mbed_official 16:4f6df64750bd 107
mbed_official 16:4f6df64750bd 108 void USBHAL::configureDevice(void) {
mbed_official 16:4f6df64750bd 109 // Not needed
mbed_official 16:4f6df64750bd 110 }
mbed_official 16:4f6df64750bd 111
mbed_official 16:4f6df64750bd 112 void USBHAL::unconfigureDevice(void) {
mbed_official 16:4f6df64750bd 113 // Not needed
mbed_official 16:4f6df64750bd 114 }
mbed_official 16:4f6df64750bd 115
mbed_official 16:4f6df64750bd 116 void USBHAL::setAddress(uint8_t address) {
mbed_official 16:4f6df64750bd 117 OTG_FS->DREGS.DCFG |= (address << 4);
mbed_official 16:4f6df64750bd 118 EP0write(0, 0);
mbed_official 16:4f6df64750bd 119 }
mbed_official 16:4f6df64750bd 120
mbed_official 16:4f6df64750bd 121 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
mbed_official 16:4f6df64750bd 122 uint32_t flags) {
mbed_official 16:4f6df64750bd 123 uint32_t epIndex = endpoint >> 1;
mbed_official 16:4f6df64750bd 124
mbed_official 16:4f6df64750bd 125 uint32_t type;
mbed_official 16:4f6df64750bd 126 switch (endpoint) {
mbed_official 25:7c72828865f3 127 case EP0IN:
mbed_official 16:4f6df64750bd 128 case EP0OUT:
mbed_official 16:4f6df64750bd 129 type = 0;
mbed_official 25:7c72828865f3 130 break;
mbed_official 16:4f6df64750bd 131 case EPISO_IN:
mbed_official 16:4f6df64750bd 132 case EPISO_OUT:
mbed_official 25:7c72828865f3 133 type = 1;
mbed_official 16:4f6df64750bd 134 case EPBULK_IN:
mbed_official 16:4f6df64750bd 135 case EPBULK_OUT:
mbed_official 25:7c72828865f3 136 type = 2;
mbed_official 25:7c72828865f3 137 break;
mbed_official 16:4f6df64750bd 138 case EPINT_IN:
mbed_official 16:4f6df64750bd 139 case EPINT_OUT:
mbed_official 25:7c72828865f3 140 type = 3;
mbed_official 25:7c72828865f3 141 break;
mbed_official 16:4f6df64750bd 142 }
mbed_official 16:4f6df64750bd 143
mbed_official 16:4f6df64750bd 144 // Generic in or out EP controls
mbed_official 16:4f6df64750bd 145 uint32_t control = (maxPacket << 0) | // Packet size
mbed_official 16:4f6df64750bd 146 (1 << 15) | // Active endpoint
mbed_official 16:4f6df64750bd 147 (type << 18); // Endpoint type
mbed_official 16:4f6df64750bd 148
mbed_official 16:4f6df64750bd 149 if (endpoint & 0x1) { // In Endpoint
mbed_official 16:4f6df64750bd 150 // Set up the Tx FIFO
mbed_official 16:4f6df64750bd 151 if (endpoint == EP0IN) {
mbed_official 16:4f6df64750bd 152 OTG_FS->GREGS.DIEPTXF0_HNPTXFSIZ = ((maxPacket >> 2) << 16) |
mbed_official 16:4f6df64750bd 153 (bufferEnd << 0);
mbed_official 16:4f6df64750bd 154 }
mbed_official 16:4f6df64750bd 155 else {
mbed_official 16:4f6df64750bd 156 OTG_FS->GREGS.DIEPTXF[epIndex - 1] = ((maxPacket >> 2) << 16) |
mbed_official 16:4f6df64750bd 157 (bufferEnd << 0);
mbed_official 16:4f6df64750bd 158 }
mbed_official 16:4f6df64750bd 159 bufferEnd += maxPacket >> 2;
mbed_official 16:4f6df64750bd 160
mbed_official 16:4f6df64750bd 161 // Set the In EP specific control settings
mbed_official 16:4f6df64750bd 162 if (endpoint != EP0IN) {
mbed_official 16:4f6df64750bd 163 control |= (1 << 28); // SD0PID
mbed_official 16:4f6df64750bd 164 }
mbed_official 25:7c72828865f3 165
mbed_official 16:4f6df64750bd 166 control |= (epIndex << 22) | // TxFIFO index
mbed_official 16:4f6df64750bd 167 (1 << 27); // SNAK
mbed_official 16:4f6df64750bd 168 OTG_FS->INEP_REGS[epIndex].DIEPCTL = control;
mbed_official 16:4f6df64750bd 169
mbed_official 16:4f6df64750bd 170 // Unmask the interrupt
mbed_official 16:4f6df64750bd 171 OTG_FS->DREGS.DAINTMSK |= (1 << epIndex);
mbed_official 16:4f6df64750bd 172 }
mbed_official 16:4f6df64750bd 173 else { // Out endpoint
mbed_official 16:4f6df64750bd 174 // Set the out EP specific control settings
mbed_official 16:4f6df64750bd 175 control |= (1 << 26); // CNAK
mbed_official 16:4f6df64750bd 176 OTG_FS->OUTEP_REGS[epIndex].DOEPCTL = control;
mbed_official 25:7c72828865f3 177
mbed_official 16:4f6df64750bd 178 // Unmask the interrupt
mbed_official 16:4f6df64750bd 179 OTG_FS->DREGS.DAINTMSK |= (1 << (epIndex + 16));
mbed_official 16:4f6df64750bd 180 }
mbed_official 16:4f6df64750bd 181 return true;
mbed_official 16:4f6df64750bd 182 }
mbed_official 16:4f6df64750bd 183
mbed_official 16:4f6df64750bd 184 // read setup packet
mbed_official 16:4f6df64750bd 185 void USBHAL::EP0setup(uint8_t *buffer) {
mbed_official 16:4f6df64750bd 186 memcpy(buffer, setupBuffer, MAX_PACKET_SIZE_EP0);
mbed_official 16:4f6df64750bd 187 }
mbed_official 16:4f6df64750bd 188
mbed_official 16:4f6df64750bd 189 void USBHAL::EP0readStage(void) {
mbed_official 16:4f6df64750bd 190 }
mbed_official 16:4f6df64750bd 191
mbed_official 16:4f6df64750bd 192 void USBHAL::EP0read(void) {
mbed_official 16:4f6df64750bd 193 }
mbed_official 16:4f6df64750bd 194
mbed_official 16:4f6df64750bd 195 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
mbed_official 16:4f6df64750bd 196 uint32_t* buffer32 = (uint32_t *) buffer;
mbed_official 16:4f6df64750bd 197 uint32_t length = rxFifoCount;
mbed_official 16:4f6df64750bd 198 for (uint32_t i = 0; i < length; i += 4) {
mbed_official 16:4f6df64750bd 199 buffer32[i >> 2] = OTG_FS->FIFO[0][0];
mbed_official 16:4f6df64750bd 200 }
mbed_official 25:7c72828865f3 201
mbed_official 16:4f6df64750bd 202 rxFifoCount = 0;
mbed_official 16:4f6df64750bd 203 return length;
mbed_official 16:4f6df64750bd 204 }
mbed_official 16:4f6df64750bd 205
mbed_official 16:4f6df64750bd 206 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
mbed_official 16:4f6df64750bd 207 endpointWrite(0, buffer, size);
mbed_official 16:4f6df64750bd 208 }
mbed_official 16:4f6df64750bd 209
mbed_official 16:4f6df64750bd 210 void USBHAL::EP0getWriteResult(void) {
mbed_official 16:4f6df64750bd 211 }
mbed_official 16:4f6df64750bd 212
mbed_official 16:4f6df64750bd 213 void USBHAL::EP0stall(void) {
mbed_official 16:4f6df64750bd 214 // If we stall the out endpoint here then we have problems transferring
mbed_official 16:4f6df64750bd 215 // and setup requests after the (stalled) get device qualifier requests.
mbed_official 16:4f6df64750bd 216 // TODO: Find out if this is correct behavior, or whether we are doing
mbed_official 16:4f6df64750bd 217 // something else wrong
mbed_official 16:4f6df64750bd 218 stallEndpoint(EP0IN);
mbed_official 16:4f6df64750bd 219 // stallEndpoint(EP0OUT);
mbed_official 16:4f6df64750bd 220 }
mbed_official 16:4f6df64750bd 221
mbed_official 16:4f6df64750bd 222 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
mbed_official 16:4f6df64750bd 223 uint32_t epIndex = endpoint >> 1;
mbed_official 16:4f6df64750bd 224 uint32_t size = (1 << 19) | // 1 packet
mbed_official 16:4f6df64750bd 225 (maximumSize << 0); // Packet size
mbed_official 16:4f6df64750bd 226 // if (endpoint == EP0OUT) {
mbed_official 16:4f6df64750bd 227 size |= (1 << 29); // 1 setup packet
mbed_official 16:4f6df64750bd 228 // }
mbed_official 16:4f6df64750bd 229 OTG_FS->OUTEP_REGS[epIndex].DOEPTSIZ = size;
mbed_official 16:4f6df64750bd 230 OTG_FS->OUTEP_REGS[epIndex].DOEPCTL |= (1 << 31) | // Enable endpoint
mbed_official 16:4f6df64750bd 231 (1 << 26); // Clear NAK
mbed_official 16:4f6df64750bd 232
mbed_official 16:4f6df64750bd 233 epComplete &= ~(1 << endpoint);
mbed_official 16:4f6df64750bd 234 return EP_PENDING;
mbed_official 16:4f6df64750bd 235 }
mbed_official 16:4f6df64750bd 236
mbed_official 16:4f6df64750bd 237 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
mbed_official 16:4f6df64750bd 238 if (!(epComplete & (1 << endpoint))) {
mbed_official 16:4f6df64750bd 239 return EP_PENDING;
mbed_official 16:4f6df64750bd 240 }
mbed_official 16:4f6df64750bd 241
mbed_official 16:4f6df64750bd 242 uint32_t* buffer32 = (uint32_t *) buffer;
mbed_official 16:4f6df64750bd 243 uint32_t length = rxFifoCount;
mbed_official 16:4f6df64750bd 244 for (uint32_t i = 0; i < length; i += 4) {
mbed_official 16:4f6df64750bd 245 buffer32[i >> 2] = OTG_FS->FIFO[endpoint >> 1][0];
mbed_official 16:4f6df64750bd 246 }
mbed_official 16:4f6df64750bd 247 rxFifoCount = 0;
mbed_official 16:4f6df64750bd 248 *bytesRead = length;
mbed_official 16:4f6df64750bd 249 return EP_COMPLETED;
mbed_official 16:4f6df64750bd 250 }
mbed_official 16:4f6df64750bd 251
mbed_official 16:4f6df64750bd 252 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
mbed_official 16:4f6df64750bd 253 uint32_t epIndex = endpoint >> 1;
mbed_official 16:4f6df64750bd 254 OTG_FS->INEP_REGS[epIndex].DIEPTSIZ = (1 << 19) | // 1 packet
mbed_official 16:4f6df64750bd 255 (size << 0); // Size of packet
mbed_official 16:4f6df64750bd 256 OTG_FS->INEP_REGS[epIndex].DIEPCTL |= (1 << 31) | // Enable endpoint
mbed_official 16:4f6df64750bd 257 (1 << 26); // CNAK
mbed_official 16:4f6df64750bd 258 OTG_FS->DREGS.DIEPEMPMSK = (1 << epIndex);
mbed_official 16:4f6df64750bd 259
mbed_official 16:4f6df64750bd 260 while ((OTG_FS->INEP_REGS[epIndex].DTXFSTS & 0XFFFF) < ((size + 3) >> 2));
mbed_official 16:4f6df64750bd 261
mbed_official 16:4f6df64750bd 262 for (uint32_t i=0; i<(size + 3) >> 2; i++, data+=4) {
mbed_official 16:4f6df64750bd 263 OTG_FS->FIFO[epIndex][0] = *(uint32_t *)data;
mbed_official 16:4f6df64750bd 264 }
mbed_official 16:4f6df64750bd 265
mbed_official 16:4f6df64750bd 266 epComplete &= ~(1 << endpoint);
mbed_official 16:4f6df64750bd 267
mbed_official 16:4f6df64750bd 268 return EP_PENDING;
mbed_official 16:4f6df64750bd 269 }
mbed_official 16:4f6df64750bd 270
mbed_official 16:4f6df64750bd 271 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
mbed_official 16:4f6df64750bd 272 if (epComplete & (1 << endpoint)) {
mbed_official 16:4f6df64750bd 273 epComplete &= ~(1 << endpoint);
mbed_official 16:4f6df64750bd 274 return EP_COMPLETED;
mbed_official 16:4f6df64750bd 275 }
mbed_official 16:4f6df64750bd 276
mbed_official 25:7c72828865f3 277 return EP_PENDING;
mbed_official 16:4f6df64750bd 278 }
mbed_official 16:4f6df64750bd 279
mbed_official 16:4f6df64750bd 280 void USBHAL::stallEndpoint(uint8_t endpoint) {
mbed_official 16:4f6df64750bd 281 if (endpoint & 0x1) { // In EP
mbed_official 16:4f6df64750bd 282 OTG_FS->INEP_REGS[endpoint >> 1].DIEPCTL |= (1 << 30) | // Disable
mbed_official 16:4f6df64750bd 283 (1 << 21); // Stall
mbed_official 16:4f6df64750bd 284 }
mbed_official 16:4f6df64750bd 285 else { // Out EP
mbed_official 16:4f6df64750bd 286 OTG_FS->DREGS.DCTL |= (1 << 9); // Set global out NAK
mbed_official 16:4f6df64750bd 287 OTG_FS->OUTEP_REGS[endpoint >> 1].DOEPCTL |= (1 << 30) | // Disable
mbed_official 16:4f6df64750bd 288 (1 << 21); // Stall
mbed_official 16:4f6df64750bd 289 }
mbed_official 16:4f6df64750bd 290 }
mbed_official 16:4f6df64750bd 291
mbed_official 16:4f6df64750bd 292 void USBHAL::unstallEndpoint(uint8_t endpoint) {
mbed_official 25:7c72828865f3 293
mbed_official 16:4f6df64750bd 294 }
mbed_official 16:4f6df64750bd 295
mbed_official 16:4f6df64750bd 296 bool USBHAL::getEndpointStallState(uint8_t endpoint) {
mbed_official 16:4f6df64750bd 297 return false;
mbed_official 16:4f6df64750bd 298 }
mbed_official 16:4f6df64750bd 299
mbed_official 16:4f6df64750bd 300 void USBHAL::remoteWakeup(void) {
mbed_official 16:4f6df64750bd 301 }
mbed_official 16:4f6df64750bd 302
mbed_official 16:4f6df64750bd 303
mbed_official 16:4f6df64750bd 304 void USBHAL::_usbisr(void) {
mbed_official 16:4f6df64750bd 305 instance->usbisr();
mbed_official 16:4f6df64750bd 306 }
mbed_official 16:4f6df64750bd 307
mbed_official 16:4f6df64750bd 308
mbed_official 16:4f6df64750bd 309 void USBHAL::usbisr(void) {
mbed_official 52:fb344268a308 310 if (OTG_FS->GREGS.GINTSTS & (1 << 11)) { // USB Suspend
mbed_official 52:fb344268a308 311 suspendStateChanged(1);
mbed_official 52:fb344268a308 312 };
mbed_official 52:fb344268a308 313
mbed_official 16:4f6df64750bd 314 if (OTG_FS->GREGS.GINTSTS & (1 << 12)) { // USB Reset
mbed_official 52:fb344268a308 315 suspendStateChanged(0);
mbed_official 52:fb344268a308 316
mbed_official 16:4f6df64750bd 317 // Set SNAK bits
mbed_official 16:4f6df64750bd 318 OTG_FS->OUTEP_REGS[0].DOEPCTL |= (1 << 27);
mbed_official 16:4f6df64750bd 319 OTG_FS->OUTEP_REGS[1].DOEPCTL |= (1 << 27);
mbed_official 16:4f6df64750bd 320 OTG_FS->OUTEP_REGS[2].DOEPCTL |= (1 << 27);
mbed_official 16:4f6df64750bd 321 OTG_FS->OUTEP_REGS[3].DOEPCTL |= (1 << 27);
mbed_official 16:4f6df64750bd 322
mbed_official 16:4f6df64750bd 323 OTG_FS->DREGS.DIEPMSK = (1 << 0);
mbed_official 16:4f6df64750bd 324
mbed_official 16:4f6df64750bd 325 bufferEnd = 0;
mbed_official 16:4f6df64750bd 326
mbed_official 16:4f6df64750bd 327 // Set the receive FIFO size
mbed_official 16:4f6df64750bd 328 OTG_FS->GREGS.GRXFSIZ = rxFifoSize >> 2;
mbed_official 16:4f6df64750bd 329 bufferEnd += rxFifoSize >> 2;
mbed_official 16:4f6df64750bd 330
mbed_official 16:4f6df64750bd 331 // Create the endpoints, and wait for setup packets on out EP0
mbed_official 16:4f6df64750bd 332 realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
mbed_official 16:4f6df64750bd 333 realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
mbed_official 16:4f6df64750bd 334 endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
mbed_official 16:4f6df64750bd 335
mbed_official 16:4f6df64750bd 336 OTG_FS->GREGS.GINTSTS = (1 << 12);
mbed_official 16:4f6df64750bd 337 }
mbed_official 16:4f6df64750bd 338
mbed_official 16:4f6df64750bd 339 if (OTG_FS->GREGS.GINTSTS & (1 << 4)) { // RX FIFO not empty
mbed_official 16:4f6df64750bd 340 uint32_t status = OTG_FS->GREGS.GRXSTSP;
mbed_official 16:4f6df64750bd 341
mbed_official 16:4f6df64750bd 342 uint32_t endpoint = (status & 0xF) << 1;
mbed_official 16:4f6df64750bd 343 uint32_t length = (status >> 4) & 0x7FF;
mbed_official 16:4f6df64750bd 344 uint32_t type = (status >> 17) & 0xF;
mbed_official 16:4f6df64750bd 345
mbed_official 16:4f6df64750bd 346 rxFifoCount = length;
mbed_official 16:4f6df64750bd 347
mbed_official 16:4f6df64750bd 348 if (type == 0x6) {
mbed_official 16:4f6df64750bd 349 // Setup packet
mbed_official 16:4f6df64750bd 350 for (uint32_t i=0; i<length; i+=4) {
mbed_official 16:4f6df64750bd 351 setupBuffer[i >> 2] = OTG_FS->FIFO[0][i >> 2];
mbed_official 16:4f6df64750bd 352 }
mbed_official 16:4f6df64750bd 353 rxFifoCount = 0;
mbed_official 16:4f6df64750bd 354 }
mbed_official 16:4f6df64750bd 355
mbed_official 16:4f6df64750bd 356 if (type == 0x4) {
mbed_official 16:4f6df64750bd 357 // Setup complete
mbed_official 16:4f6df64750bd 358 EP0setupCallback();
mbed_official 16:4f6df64750bd 359 endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
mbed_official 16:4f6df64750bd 360 }
mbed_official 16:4f6df64750bd 361
mbed_official 16:4f6df64750bd 362 if (type == 0x2) {
mbed_official 16:4f6df64750bd 363 // Out packet
mbed_official 16:4f6df64750bd 364 if (endpoint == EP0OUT) {
mbed_official 16:4f6df64750bd 365 EP0out();
mbed_official 16:4f6df64750bd 366 }
mbed_official 16:4f6df64750bd 367 else {
mbed_official 16:4f6df64750bd 368 epComplete |= (1 << endpoint);
mbed_official 16:4f6df64750bd 369 if ((instance->*(epCallback[endpoint - 2]))()) {
mbed_official 16:4f6df64750bd 370 epComplete &= (1 << endpoint);
mbed_official 16:4f6df64750bd 371 }
mbed_official 16:4f6df64750bd 372 }
mbed_official 16:4f6df64750bd 373 }
mbed_official 16:4f6df64750bd 374
mbed_official 16:4f6df64750bd 375 for (uint32_t i=0; i<rxFifoCount; i+=4) {
mbed_official 16:4f6df64750bd 376 (void) OTG_FS->FIFO[0][0];
mbed_official 16:4f6df64750bd 377 }
mbed_official 16:4f6df64750bd 378 OTG_FS->GREGS.GINTSTS = (1 << 4);
mbed_official 16:4f6df64750bd 379 }
mbed_official 16:4f6df64750bd 380
mbed_official 16:4f6df64750bd 381 if (OTG_FS->GREGS.GINTSTS & (1 << 18)) { // In endpoint interrupt
mbed_official 16:4f6df64750bd 382 // Loop through the in endpoints
mbed_official 16:4f6df64750bd 383 for (uint32_t i=0; i<4; i++) {
mbed_official 16:4f6df64750bd 384 if (OTG_FS->DREGS.DAINT & (1 << i)) { // Interrupt is on endpoint
mbed_official 16:4f6df64750bd 385
mbed_official 16:4f6df64750bd 386 if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 7)) {// Tx FIFO empty
mbed_official 16:4f6df64750bd 387 // If the Tx FIFO is empty on EP0 we need to send a further
mbed_official 16:4f6df64750bd 388 // packet, so call EP0in()
mbed_official 16:4f6df64750bd 389 if (i == 0) {
mbed_official 16:4f6df64750bd 390 EP0in();
mbed_official 16:4f6df64750bd 391 }
mbed_official 16:4f6df64750bd 392 // Clear the interrupt
mbed_official 16:4f6df64750bd 393 OTG_FS->INEP_REGS[i].DIEPINT = (1 << 7);
mbed_official 16:4f6df64750bd 394 // Stop firing Tx empty interrupts
mbed_official 16:4f6df64750bd 395 // Will get turned on again if another write is called
mbed_official 16:4f6df64750bd 396 OTG_FS->DREGS.DIEPEMPMSK &= ~(1 << i);
mbed_official 16:4f6df64750bd 397 }
mbed_official 16:4f6df64750bd 398
mbed_official 16:4f6df64750bd 399 // If the transfer is complete
mbed_official 16:4f6df64750bd 400 if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 0)) { // Tx Complete
mbed_official 16:4f6df64750bd 401 epComplete |= (1 << (1 + (i << 1)));
mbed_official 16:4f6df64750bd 402 OTG_FS->INEP_REGS[i].DIEPINT = (1 << 0);
mbed_official 16:4f6df64750bd 403 }
mbed_official 16:4f6df64750bd 404 }
mbed_official 16:4f6df64750bd 405 }
mbed_official 16:4f6df64750bd 406 OTG_FS->GREGS.GINTSTS = (1 << 18);
mbed_official 16:4f6df64750bd 407 }
mbed_official 16:4f6df64750bd 408
mbed_official 16:4f6df64750bd 409 if (OTG_FS->GREGS.GINTSTS & (1 << 3)) { // Start of frame
mbed_official 16:4f6df64750bd 410 SOF((OTG_FS->GREGS.GRXSTSR >> 17) & 0xF);
mbed_official 16:4f6df64750bd 411 OTG_FS->GREGS.GINTSTS = (1 << 3);
mbed_official 16:4f6df64750bd 412 }
mbed_official 16:4f6df64750bd 413 }
mbed_official 16:4f6df64750bd 414
mbed_official 16:4f6df64750bd 415
mbed_official 16:4f6df64750bd 416 #endif