Maxim Integrated / MAX11300

Library for the MAX11300

Dependents:   MAXREFDES130_131_Demo MAXREFDES130_Demo MAX11300_test

MAX11300.cpp@1:90e0ff21a740, 2016-07-27 (annotated)

Committer:
j3
Date:
Wed Jul 27 01:41:08 2016 +0000
Revision:
1:90e0ff21a740
Parent:
0:bfae6930d2ff
Child:
2:4eecc9d5c972
Working init fx, few helper fxs for GPIO write/read, adc/dac read/write

Who changed what in which revision?

UserRevisionLine numberNew contents of line
j3 0:bfae6930d2ff 1 /**********************************************************************
j3 0:bfae6930d2ff 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
j3 0:bfae6930d2ff 3 *
j3 0:bfae6930d2ff 4 * Permission is hereby granted, free of charge, to any person obtaining a
j3 0:bfae6930d2ff 5 * copy of this software and associated documentation files (the "Software"),
j3 0:bfae6930d2ff 6 * to deal in the Software without restriction, including without limitation
j3 0:bfae6930d2ff 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
j3 0:bfae6930d2ff 8 * and/or sell copies of the Software, and to permit persons to whom the
j3 0:bfae6930d2ff 9 * Software is furnished to do so, subject to the following conditions:
j3 0:bfae6930d2ff 10 *
j3 0:bfae6930d2ff 11 * The above copyright notice and this permission notice shall be included
j3 0:bfae6930d2ff 12 * in all copies or substantial portions of the Software.
j3 0:bfae6930d2ff 13 *
j3 0:bfae6930d2ff 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
j3 0:bfae6930d2ff 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
j3 0:bfae6930d2ff 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
j3 0:bfae6930d2ff 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
j3 0:bfae6930d2ff 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
j3 0:bfae6930d2ff 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
j3 0:bfae6930d2ff 20 * OTHER DEALINGS IN THE SOFTWARE.
j3 0:bfae6930d2ff 21 *
j3 0:bfae6930d2ff 22 * Except as contained in this notice, the name of Maxim Integrated
j3 0:bfae6930d2ff 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
j3 0:bfae6930d2ff 24 * Products, Inc. Branding Policy.
j3 0:bfae6930d2ff 25 *
j3 0:bfae6930d2ff 26 * The mere transfer of this software does not imply any licenses
j3 0:bfae6930d2ff 27 * of trade secrets, proprietary technology, copyrights, patents,
j3 0:bfae6930d2ff 28 * trademarks, maskwork rights, or any other form of intellectual
j3 0:bfae6930d2ff 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
j3 0:bfae6930d2ff 30 * ownership rights.
j3 0:bfae6930d2ff 31 **********************************************************************/
j3 0:bfae6930d2ff 32
j3 0:bfae6930d2ff 33 #include "MAX11300.h"
j3 0:bfae6930d2ff 34
j3 0:bfae6930d2ff 35 static const uint16_t port_config_design_vals[20] = {
j3 0:bfae6930d2ff 36 port_cfg_00_DESIGNVALUE,
j3 0:bfae6930d2ff 37 port_cfg_01_DESIGNVALUE,
j3 0:bfae6930d2ff 38 port_cfg_02_DESIGNVALUE,
j3 0:bfae6930d2ff 39 port_cfg_03_DESIGNVALUE,
j3 0:bfae6930d2ff 40 port_cfg_04_DESIGNVALUE,
j3 0:bfae6930d2ff 41 port_cfg_05_DESIGNVALUE,
j3 0:bfae6930d2ff 42 port_cfg_06_DESIGNVALUE,
j3 0:bfae6930d2ff 43 port_cfg_07_DESIGNVALUE,
j3 0:bfae6930d2ff 44 port_cfg_08_DESIGNVALUE,
j3 0:bfae6930d2ff 45 port_cfg_09_DESIGNVALUE,
j3 0:bfae6930d2ff 46 port_cfg_10_DESIGNVALUE,
j3 0:bfae6930d2ff 47 port_cfg_11_DESIGNVALUE,
j3 0:bfae6930d2ff 48 port_cfg_12_DESIGNVALUE,
j3 0:bfae6930d2ff 49 port_cfg_13_DESIGNVALUE,
j3 0:bfae6930d2ff 50 port_cfg_14_DESIGNVALUE,
j3 0:bfae6930d2ff 51 port_cfg_15_DESIGNVALUE,
j3 0:bfae6930d2ff 52 port_cfg_16_DESIGNVALUE,
j3 0:bfae6930d2ff 53 port_cfg_17_DESIGNVALUE,
j3 0:bfae6930d2ff 54 port_cfg_18_DESIGNVALUE,
j3 0:bfae6930d2ff 55 port_cfg_19_DESIGNVALUE};
j3 0:bfae6930d2ff 56
j3 0:bfae6930d2ff 57 //*********************************************************************
j3 0:bfae6930d2ff 58 MAX11300::MAX11300(SPI & spi_bus, PinName cs, PinName interrupt, PinName cnvt):
j3 0:bfae6930d2ff 59 m_spi_bus(spi_bus), m_cs(cs, 1), m_int(interrupt), m_cnvt(cnvt)
j3 0:bfae6930d2ff 60 {
j3 0:bfae6930d2ff 61 init();
j3 0:bfae6930d2ff 62 }
j3 0:bfae6930d2ff 63
j3 0:bfae6930d2ff 64 //*********************************************************************
j3 0:bfae6930d2ff 65 MAX11300::~MAX11300()
j3 0:bfae6930d2ff 66 {
j3 0:bfae6930d2ff 67 }
j3 0:bfae6930d2ff 68
j3 0:bfae6930d2ff 69 //*********************************************************************
j3 0:bfae6930d2ff 70 void MAX11300::write_register(MAX11300RegAddress_t reg, uint16_t data)
j3 0:bfae6930d2ff 71 {
j3 0:bfae6930d2ff 72 m_cs = 0;
j3 0:bfae6930d2ff 73 m_spi_bus.write(MAX11300Addr_SPI_Write(reg));
j3 1:90e0ff21a740 74 m_spi_bus.write(((0xFF00 & data) >> 8));
j3 1:90e0ff21a740 75 m_spi_bus.write((0x00FF & data));
j3 0:bfae6930d2ff 76 m_cs = 1;
j3 0:bfae6930d2ff 77 }
j3 0:bfae6930d2ff 78
j3 0:bfae6930d2ff 79 //*********************************************************************
j3 0:bfae6930d2ff 80 uint16_t MAX11300::read_register(MAX11300RegAddress_t reg)
j3 0:bfae6930d2ff 81 {
j3 0:bfae6930d2ff 82 uint16_t rtn_val = 0;
j3 0:bfae6930d2ff 83
j3 0:bfae6930d2ff 84 m_cs = 0;
j3 0:bfae6930d2ff 85 m_spi_bus.write(MAX11300Addr_SPI_Read(reg));
j3 0:bfae6930d2ff 86 rtn_val |= (m_spi_bus.write(0xFF) << 8);
j3 0:bfae6930d2ff 87 rtn_val |= m_spi_bus.write(0xFF);
j3 0:bfae6930d2ff 88 m_cs = 1;
j3 0:bfae6930d2ff 89
j3 0:bfae6930d2ff 90 return rtn_val;
j3 0:bfae6930d2ff 91 }
j3 0:bfae6930d2ff 92
j3 1:90e0ff21a740 93 //*********************************************************************
j3 0:bfae6930d2ff 94 void MAX11300::block_write(MAX11300RegAddress_t reg, uint16_t * data, uint8_t num_bytes)
j3 0:bfae6930d2ff 95 {
j3 0:bfae6930d2ff 96 for(uint8_t idx = 0; idx < num_bytes; idx++)
j3 0:bfae6930d2ff 97 {
j3 0:bfae6930d2ff 98 write_register(static_cast<MAX11300RegAddress_t>(reg + idx), data[idx]);
j3 0:bfae6930d2ff 99 }
j3 0:bfae6930d2ff 100 }
j3 1:90e0ff21a740 101
j3 1:90e0ff21a740 102 //*********************************************************************
j3 0:bfae6930d2ff 103 void MAX11300::block_read(MAX11300RegAddress_t reg, uint16_t * data, uint8_t num_bytes)
j3 0:bfae6930d2ff 104 {
j3 0:bfae6930d2ff 105 for(uint8_t idx = 0; idx < num_bytes; idx++)
j3 0:bfae6930d2ff 106 {
j3 0:bfae6930d2ff 107 data[idx] = read_register(static_cast<MAX11300RegAddress_t>(reg + idx));
j3 0:bfae6930d2ff 108 }
j3 0:bfae6930d2ff 109 }
j3 0:bfae6930d2ff 110
j3 0:bfae6930d2ff 111 //*********************************************************************
j3 0:bfae6930d2ff 112 MAX11300::CmdResult MAX11300::gpio_write(MAX11300_Ports port, uint8_t state)
j3 0:bfae6930d2ff 113 {
j3 1:90e0ff21a740 114 MAX11300::CmdResult result = MAX11300::OpFailure;
j3 1:90e0ff21a740 115
j3 1:90e0ff21a740 116 if(((port_config_design_vals[port] & 0xF000) >> 12) == MAX11300::MODE_3)
j3 1:90e0ff21a740 117 {
j3 1:90e0ff21a740 118 if(port < MAX11300::PORT16)
j3 1:90e0ff21a740 119 {
j3 1:90e0ff21a740 120 write_register(gpo_data_15_to_0, ((state & 1) << port));
j3 1:90e0ff21a740 121 }
j3 1:90e0ff21a740 122 else
j3 1:90e0ff21a740 123 {
j3 1:90e0ff21a740 124 write_register(gpo_data_19_to_16, ((state & 1) << (port - MAX11300::PORT16)));
j3 1:90e0ff21a740 125 }
j3 1:90e0ff21a740 126
j3 1:90e0ff21a740 127 result = MAX11300::Success;
j3 1:90e0ff21a740 128 }
j3 1:90e0ff21a740 129
j3 1:90e0ff21a740 130 return result;
j3 0:bfae6930d2ff 131 }
j3 0:bfae6930d2ff 132
j3 0:bfae6930d2ff 133 //*********************************************************************
j3 0:bfae6930d2ff 134 MAX11300::CmdResult MAX11300::gpio_read(MAX11300_Ports port, uint8_t & state)
j3 0:bfae6930d2ff 135 {
j3 1:90e0ff21a740 136 MAX11300::CmdResult result = MAX11300::OpFailure;
j3 1:90e0ff21a740 137
j3 1:90e0ff21a740 138 if(((port_config_design_vals[port] & 0xF000) >> 12) == MAX11300::MODE_1)
j3 1:90e0ff21a740 139 {
j3 1:90e0ff21a740 140 if(port < MAX11300::PORT16)
j3 1:90e0ff21a740 141 {
j3 1:90e0ff21a740 142 state = (read_register(gpi_data_15_to_0) >> port);
j3 1:90e0ff21a740 143 }
j3 1:90e0ff21a740 144 else
j3 1:90e0ff21a740 145 {
j3 1:90e0ff21a740 146 state = (read_register(gpi_data_19_to_16) >> (port - MAX11300::PORT16));
j3 1:90e0ff21a740 147 }
j3 1:90e0ff21a740 148
j3 1:90e0ff21a740 149 result = MAX11300::Success;
j3 1:90e0ff21a740 150 }
j3 1:90e0ff21a740 151
j3 1:90e0ff21a740 152 return result;
j3 0:bfae6930d2ff 153 }
j3 0:bfae6930d2ff 154
j3 0:bfae6930d2ff 155 //*********************************************************************
j3 1:90e0ff21a740 156 MAX11300::CmdResult MAX11300::single_ended_adc_read(MAX11300_Ports port, uint16_t & data)
j3 0:bfae6930d2ff 157 {
j3 1:90e0ff21a740 158 MAX11300::CmdResult result = MAX11300::OpFailure;
j3 1:90e0ff21a740 159
j3 1:90e0ff21a740 160 if(((port_config_design_vals[port] & 0xF000) >> 12) == MAX11300::MODE_7)
j3 1:90e0ff21a740 161 {
j3 1:90e0ff21a740 162 data = read_register(static_cast<MAX11300RegAddress_t>(adc_data_port_00 + port));
j3 1:90e0ff21a740 163
j3 1:90e0ff21a740 164 result = MAX11300::Success;
j3 1:90e0ff21a740 165 }
j3 1:90e0ff21a740 166
j3 1:90e0ff21a740 167 return result;
j3 0:bfae6930d2ff 168 }
j3 0:bfae6930d2ff 169
j3 0:bfae6930d2ff 170 //*********************************************************************
j3 1:90e0ff21a740 171 MAX11300::CmdResult MAX11300::single_ended_dac_write(MAX11300_Ports port, uint16_t data)
j3 0:bfae6930d2ff 172 {
j3 1:90e0ff21a740 173 MAX11300::CmdResult result = MAX11300::OpFailure;
j3 1:90e0ff21a740 174
j3 1:90e0ff21a740 175 if(((port_config_design_vals[port] & 0xF000) >> 12) == MAX11300::MODE_5)
j3 1:90e0ff21a740 176 {
j3 1:90e0ff21a740 177 write_register(static_cast<MAX11300RegAddress_t>(dac_data_port_00 + port) , data);
j3 1:90e0ff21a740 178 result = MAX11300::Success;
j3 1:90e0ff21a740 179 }
j3 1:90e0ff21a740 180
j3 1:90e0ff21a740 181 return result;
j3 0:bfae6930d2ff 182 }
j3 0:bfae6930d2ff 183
j3 0:bfae6930d2ff 184 //*********************************************************************
j3 0:bfae6930d2ff 185 void MAX11300::init(void)
j3 0:bfae6930d2ff 186 {
j3 0:bfae6930d2ff 187 //see datasheet 19-7318; Rev 3; 4/16; page 49
j3 0:bfae6930d2ff 188 //https://datasheets.maximintegrated.com/en/ds/MAX11300.pdf
j3 0:bfae6930d2ff 189 //for description of configuration process
j3 0:bfae6930d2ff 190
j3 0:bfae6930d2ff 191 uint8_t idx;
j3 1:90e0ff21a740 192 uint8_t port_mode;
j3 0:bfae6930d2ff 193 uint16_t mode_bit_mask = 0;
j3 0:bfae6930d2ff 194
j3 0:bfae6930d2ff 195 //figure out port modes used
j3 0:bfae6930d2ff 196 for(idx = 0; idx < 20; idx++)
j3 0:bfae6930d2ff 197 {
j3 1:90e0ff21a740 198 port_mode = ((port_config_design_vals[idx] & 0xf000) >> 12);
j3 1:90e0ff21a740 199 if(port_mode > 0)
j3 1:90e0ff21a740 200 {
j3 1:90e0ff21a740 201 mode_bit_mask |= (1 << port_mode);
j3 1:90e0ff21a740 202 }
j3 0:bfae6930d2ff 203 }
j3 0:bfae6930d2ff 204
j3 0:bfae6930d2ff 205 //STEP 1: configure BRST, THSHDN, ADCCONV
j3 0:bfae6930d2ff 206 uint16_t device_control_local = (device_control_DESIGNVALUE & (device_control_BRST | device_control_THSHDN | device_control_ADCCONV));
j3 0:bfae6930d2ff 207 write_register(device_control, device_control_local);
j3 0:bfae6930d2ff 208
j3 0:bfae6930d2ff 209 //STEP 2: If any port is configured for modes 1,3,4,5,6, or 10
j3 1:90e0ff21a740 210 if(mode_bit_mask & MODE_BITMASK_PROCESS_1)
j3 0:bfae6930d2ff 211 {
j3 1:90e0ff21a740 212 config_process_1(device_control_local);
j3 0:bfae6930d2ff 213 }
j3 0:bfae6930d2ff 214
j3 0:bfae6930d2ff 215 //STEP 3: If any port is configured for modes 7,8, or 9
j3 1:90e0ff21a740 216 if(mode_bit_mask & MODE_BITMASK_PROCESS_2)
j3 0:bfae6930d2ff 217 {
j3 1:90e0ff21a740 218 config_process_2(device_control_local);
j3 0:bfae6930d2ff 219 }
j3 0:bfae6930d2ff 220
j3 0:bfae6930d2ff 221 //STEP 4: If any port is configured for modes 2,11, or 12
j3 1:90e0ff21a740 222 if(mode_bit_mask & MODE_BITMASK_PROCESS_3)
j3 0:bfae6930d2ff 223 {
j3 0:bfae6930d2ff 224 config_process_3();
j3 0:bfae6930d2ff 225 }
j3 0:bfae6930d2ff 226
j3 0:bfae6930d2ff 227 //STEP 5: Are Temperature sensors used?
j3 0:bfae6930d2ff 228 if(device_control_DESIGNVALUE & (device_control_TMPCTLEXT1 | device_control_TMPCTLEXT0 | device_control_TMPCTLINT))
j3 0:bfae6930d2ff 229 {
j3 1:90e0ff21a740 230 device_control_local |= (device_control_DESIGNVALUE & (device_control_TMPPER | device_control_RS_CANCEL));
j3 1:90e0ff21a740 231 write_register(device_control, device_control_local);
j3 1:90e0ff21a740 232
j3 1:90e0ff21a740 233 uint16_t temp_thresholds [6] = {
j3 1:90e0ff21a740 234 tmp_mon_int_hi_thresh_DESIGNVALUE,
j3 1:90e0ff21a740 235 tmp_mon_int_lo_thresh_DESIGNVALUE,
j3 1:90e0ff21a740 236 tmp_mon_ext1_hi_thresh_DESIGNVALUE,
j3 1:90e0ff21a740 237 tmp_mon_ext1_lo_thresh_DESIGNVALUE,
j3 1:90e0ff21a740 238 tmp_mon_ext2_hi_thresh_DESIGNVALUE,
j3 1:90e0ff21a740 239 tmp_mon_ext2_lo_thresh_DESIGNVALUE};
j3 1:90e0ff21a740 240 block_write(tmp_mon_int_hi_thresh, temp_thresholds, 6);
j3 1:90e0ff21a740 241
j3 1:90e0ff21a740 242 device_control_local |= (device_control_DESIGNVALUE & (device_control_TMPCTLEXT1 | device_control_TMPCTLEXT0 | device_control_TMPCTLINT));
j3 1:90e0ff21a740 243 write_register(device_control, device_control_local);
j3 0:bfae6930d2ff 244 }
j3 0:bfae6930d2ff 245
j3 1:90e0ff21a740 246 //STEP 6: Configure interrupt masks
j3 1:90e0ff21a740 247 write_register(interrupt_mask, interrupt_mask_DESIGNVALUE);
j3 0:bfae6930d2ff 248 }
j3 0:bfae6930d2ff 249
j3 0:bfae6930d2ff 250 //*********************************************************************
j3 1:90e0ff21a740 251 void MAX11300::config_process_1(uint16_t & device_control_local)
j3 0:bfae6930d2ff 252 {
j3 1:90e0ff21a740 253 uint8_t idx;
j3 1:90e0ff21a740 254 uint16_t port_mode;
j3 1:90e0ff21a740 255 uint16_t dac_data_array[20] = {
j3 1:90e0ff21a740 256 dac_data_port_00_DESIGNVALUE,
j3 1:90e0ff21a740 257 dac_data_port_01_DESIGNVALUE,
j3 1:90e0ff21a740 258 dac_data_port_02_DESIGNVALUE,
j3 1:90e0ff21a740 259 dac_data_port_03_DESIGNVALUE,
j3 1:90e0ff21a740 260 dac_data_port_04_DESIGNVALUE,
j3 1:90e0ff21a740 261 dac_data_port_05_DESIGNVALUE,
j3 1:90e0ff21a740 262 dac_data_port_06_DESIGNVALUE,
j3 1:90e0ff21a740 263 dac_data_port_07_DESIGNVALUE,
j3 1:90e0ff21a740 264 dac_data_port_08_DESIGNVALUE,
j3 1:90e0ff21a740 265 dac_data_port_09_DESIGNVALUE,
j3 1:90e0ff21a740 266 dac_data_port_10_DESIGNVALUE,
j3 1:90e0ff21a740 267 dac_data_port_11_DESIGNVALUE,
j3 1:90e0ff21a740 268 dac_data_port_12_DESIGNVALUE,
j3 1:90e0ff21a740 269 dac_data_port_13_DESIGNVALUE,
j3 1:90e0ff21a740 270 dac_data_port_14_DESIGNVALUE,
j3 1:90e0ff21a740 271 dac_data_port_15_DESIGNVALUE,
j3 1:90e0ff21a740 272 dac_data_port_16_DESIGNVALUE,
j3 1:90e0ff21a740 273 dac_data_port_17_DESIGNVALUE,
j3 1:90e0ff21a740 274 dac_data_port_18_DESIGNVALUE,
j3 1:90e0ff21a740 275 dac_data_port_19_DESIGNVALUE};
j3 1:90e0ff21a740 276
j3 1:90e0ff21a740 277 device_control_local |= (device_control_DESIGNVALUE & (device_control_DACREF | device_control_DACCTL));
j3 1:90e0ff21a740 278 write_register(device_control, device_control_local);
j3 1:90e0ff21a740 279
j3 1:90e0ff21a740 280 wait_us(200);
j3 1:90e0ff21a740 281
j3 1:90e0ff21a740 282 //Is DACCTL = 2 or 3
j3 1:90e0ff21a740 283 if(((device_control_DESIGNVALUE & device_control_DACCTL) == 2) || ((device_control_DESIGNVALUE & device_control_DACCTL) == 3))
j3 1:90e0ff21a740 284 {
j3 1:90e0ff21a740 285 //yes
j3 1:90e0ff21a740 286 write_register(dac_preset_data_1, dac_preset_data_1_DESIGNVALUE);
j3 1:90e0ff21a740 287 write_register(dac_preset_data_2, dac_preset_data_2_DESIGNVALUE);
j3 1:90e0ff21a740 288 }
j3 1:90e0ff21a740 289 else
j3 1:90e0ff21a740 290 {
j3 1:90e0ff21a740 291 //no
j3 1:90e0ff21a740 292 for(idx = 0; idx < 20; idx++)
j3 1:90e0ff21a740 293 {
j3 1:90e0ff21a740 294 port_mode = ((port_config_design_vals[idx] & 0xf000) >> 12);
j3 1:90e0ff21a740 295 if((port_mode == MAX11300::MODE_1) || (port_mode == MAX11300::MODE_3) ||
j3 1:90e0ff21a740 296 (port_mode == MAX11300::MODE_4) || (port_mode == MAX11300::MODE_5) ||
j3 1:90e0ff21a740 297 (port_mode == MAX11300::MODE_6) || (port_mode == MAX11300::MODE_10))
j3 1:90e0ff21a740 298 {
j3 1:90e0ff21a740 299 write_register(static_cast<MAX11300RegAddress_t>(dac_data_port_00 + idx), dac_data_array[idx]);
j3 1:90e0ff21a740 300 }
j3 1:90e0ff21a740 301 }
j3 1:90e0ff21a740 302 }
j3 1:90e0ff21a740 303
j3 1:90e0ff21a740 304 //Config FUNCID[i], FUNCPRM[i] for ports in mode 1
j3 1:90e0ff21a740 305 uint8_t num_ports_mode_1 = 0;
j3 1:90e0ff21a740 306 for(idx = 0; idx < 20; idx++)
j3 1:90e0ff21a740 307 {
j3 1:90e0ff21a740 308 port_mode = ((port_config_design_vals[idx] & 0xf000) >> 12);
j3 1:90e0ff21a740 309 if(port_mode == MAX11300::MODE_1)
j3 1:90e0ff21a740 310 {
j3 1:90e0ff21a740 311 write_register(static_cast<MAX11300RegAddress_t>(port_cfg_00 + idx), port_config_design_vals[idx]);
j3 1:90e0ff21a740 312 num_ports_mode_1++;
j3 1:90e0ff21a740 313 }
j3 1:90e0ff21a740 314 }
j3 1:90e0ff21a740 315
j3 1:90e0ff21a740 316 wait_us(200 * num_ports_mode_1);
j3 1:90e0ff21a740 317
j3 1:90e0ff21a740 318 //Config GPODAT[i] for ports in mode 3
j3 1:90e0ff21a740 319 write_register(gpo_data_15_to_0, gpo_data_15_to_0_DESIGNVALUE);
j3 1:90e0ff21a740 320 write_register(gpo_data_19_to_16, gpo_data_19_to_16_DESIGNVALUE);
j3 1:90e0ff21a740 321
j3 1:90e0ff21a740 322 //Config FUNCID[i], FUNCPRM[i] for ports in mode 3, 4, 5, 6, or 10
j3 1:90e0ff21a740 323 for(idx = 0; idx < 20; idx++)
j3 1:90e0ff21a740 324 {
j3 1:90e0ff21a740 325 port_mode = ((port_config_design_vals[idx] & 0xf000) >> 12);
j3 1:90e0ff21a740 326 if((port_mode == MAX11300::MODE_3) | (port_mode == MAX11300::MODE_4) |
j3 1:90e0ff21a740 327 (port_mode == MAX11300::MODE_5) | (port_mode == MAX11300::MODE_6) |
j3 1:90e0ff21a740 328 (port_mode == MAX11300::MODE_10))
j3 1:90e0ff21a740 329 {
j3 1:90e0ff21a740 330 write_register(static_cast<MAX11300RegAddress_t>(port_cfg_00 + idx), port_config_design_vals[idx]);
j3 1:90e0ff21a740 331 wait_ms(1);
j3 1:90e0ff21a740 332 }
j3 1:90e0ff21a740 333 }
j3 1:90e0ff21a740 334
j3 1:90e0ff21a740 335 //Config GPIMD[i] for ports in mode 1
j3 1:90e0ff21a740 336 write_register(gpi_irqmode_7_to_0, gpi_irqmode_7_to_0_DESIGNVALUE);
j3 1:90e0ff21a740 337 write_register(gpi_irqmode_15_to_8, gpi_irqmode_15_to_8_DESIGNVALUE);
j3 1:90e0ff21a740 338 write_register(gpi_irqmode_19_to_16, gpi_irqmode_19_to_16_DESIGNVALUE);
j3 0:bfae6930d2ff 339 }
j3 0:bfae6930d2ff 340
j3 0:bfae6930d2ff 341 //*********************************************************************
j3 1:90e0ff21a740 342 void MAX11300::config_process_2(uint16_t & device_control_local)
j3 0:bfae6930d2ff 343 {
j3 1:90e0ff21a740 344 uint8_t idx;
j3 1:90e0ff21a740 345 uint16_t port_mode;
j3 1:90e0ff21a740 346
j3 1:90e0ff21a740 347 for(idx = 0; idx < 20; idx++)
j3 1:90e0ff21a740 348 {
j3 1:90e0ff21a740 349 port_mode = ((port_config_design_vals[idx] & 0xf000) >> 12);
j3 1:90e0ff21a740 350 if(port_mode == MAX11300::MODE_9)
j3 1:90e0ff21a740 351 {
j3 1:90e0ff21a740 352 write_register(static_cast<MAX11300RegAddress_t>(port_cfg_00 + idx), port_config_design_vals[idx]);
j3 1:90e0ff21a740 353 wait_us(100);
j3 1:90e0ff21a740 354 }
j3 1:90e0ff21a740 355 }
j3 1:90e0ff21a740 356
j3 1:90e0ff21a740 357 for(idx = 0; idx < 20; idx++)
j3 1:90e0ff21a740 358 {
j3 1:90e0ff21a740 359 port_mode = ((port_config_design_vals[idx] & 0xf000) >> 12);
j3 1:90e0ff21a740 360 if((port_mode == MAX11300::MODE_7) || (port_mode == MAX11300::MODE_8))
j3 1:90e0ff21a740 361 {
j3 1:90e0ff21a740 362 write_register(static_cast<MAX11300RegAddress_t>(port_cfg_00 + idx), port_config_design_vals[idx]);
j3 1:90e0ff21a740 363 wait_us(100);
j3 1:90e0ff21a740 364 }
j3 1:90e0ff21a740 365 }
j3 1:90e0ff21a740 366
j3 1:90e0ff21a740 367 device_control_local |= (device_control_DESIGNVALUE & device_control_ADCCTL);
j3 1:90e0ff21a740 368 write_register(device_control, device_control_local);
j3 0:bfae6930d2ff 369 }
j3 0:bfae6930d2ff 370
j3 0:bfae6930d2ff 371 //*********************************************************************
j3 0:bfae6930d2ff 372 void MAX11300::config_process_3(void)
j3 0:bfae6930d2ff 373 {
j3 1:90e0ff21a740 374 uint8_t idx;
j3 1:90e0ff21a740 375 uint16_t port_mode;
j3 1:90e0ff21a740 376
j3 1:90e0ff21a740 377 for(idx = 0; idx < 20; idx++)
j3 1:90e0ff21a740 378 {
j3 1:90e0ff21a740 379 port_mode = ((port_config_design_vals[idx] & 0xf000) >> 12);
j3 1:90e0ff21a740 380 if((port_mode == MAX11300::MODE_2) || (port_mode == MAX11300::MODE_11) || (port_mode == MAX11300::MODE_12))
j3 1:90e0ff21a740 381 {
j3 1:90e0ff21a740 382 write_register(static_cast<MAX11300RegAddress_t>(port_cfg_00 + idx), port_config_design_vals[idx]);
j3 1:90e0ff21a740 383 }
j3 1:90e0ff21a740 384 }
j3 0:bfae6930d2ff 385 }
j3 0:bfae6930d2ff 386