MSS / MMA8451Q

Xtrinsic MMA8451Q 3-Axis, 14-bit/8-bit Digital Accelerometer

Dependents:   test_MMA8451Q afero_node_suntory_171018 testSensor Vytah ... more

MMA8451Q.cpp@0:5a09d01c6a2c, 2015-12-25 (annotated)

Committer:
Rhyme
Date:
Fri Dec 25 07:21:49 2015 +0000
Revision:
0:5a09d01c6a2c
First commit, only the minimum functions have been implemented.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Rhyme 0:5a09d01c6a2c 1 /**
Rhyme 0:5a09d01c6a2c 2 * MMA8451Q 3-Axis, 14-bit/8-bit Digital Accelerometer
Rhyme 0:5a09d01c6a2c 3 */
Rhyme 0:5a09d01c6a2c 4
Rhyme 0:5a09d01c6a2c 5 #include "mbed.h"
Rhyme 0:5a09d01c6a2c 6 #include "MMA8451Q.h"
Rhyme 0:5a09d01c6a2c 7
Rhyme 0:5a09d01c6a2c 8 #define REG_STATUS 0x00 // when F_MODE = 00
Rhyme 0:5a09d01c6a2c 9 #define REG_FIFO_STATUS 0x00 // when F_MODE > 0
Rhyme 0:5a09d01c6a2c 10 #define REG_XYZ_FIFO 0x01 // Root pointer to XYZ FIFO data
Rhyme 0:5a09d01c6a2c 11 #define REG_OUT_X_MSB 0x01 // 8 MSBs of 14-bit sample
Rhyme 0:5a09d01c6a2c 12 #define REG_OUT_X_LSB 0x02 // 6 LSBs of 14-bit sample
Rhyme 0:5a09d01c6a2c 13 #define REG_OUT_Y_MSB 0x03
Rhyme 0:5a09d01c6a2c 14 #define REG_OUT_Y_LSB 0x04
Rhyme 0:5a09d01c6a2c 15 #define REG_OUT_Z_MSB 0x05
Rhyme 0:5a09d01c6a2c 16 #define REG_OUT_Z_LSB 0x06
Rhyme 0:5a09d01c6a2c 17 #define REG_F_SETUP 0x09 // FIFO setup
Rhyme 0:5a09d01c6a2c 18 #define REG_TRIG_CFG 0x0A // Map of FIFO daa capture events
Rhyme 0:5a09d01c6a2c 19 #define REG_SYSMOD 0x0B // Current System Mode
Rhyme 0:5a09d01c6a2c 20 #define REG_INT_SOURCE 0x0C // Interrupt status
Rhyme 0:5a09d01c6a2c 21 #define REG_WHO_AM_I 0x0D // Device ID (0x1A)
Rhyme 0:5a09d01c6a2c 22 #define REG_XYZ_DATA_CFG 0x0E // Dynamic Range Settings
Rhyme 0:5a09d01c6a2c 23 #define REG_HP_FILTER_CUTOFF 0x0F // Cutoff freq is set to 16Hz@800Hz
Rhyme 0:5a09d01c6a2c 24 #define REG_PL_STATUS 0x10 // Landscape/Portrait orientation status
Rhyme 0:5a09d01c6a2c 25 #define REG_PL_CFG 0x11 // Landscape/Portrait configuration
Rhyme 0:5a09d01c6a2c 26 #define REG_PL_COUNT 0x12 // Landscape/Portrait debounce counter
Rhyme 0:5a09d01c6a2c 27 #define REG_PL_BF_ZCOMP 0x13 // Back/Front, Z-Lock Trip threshold
Rhyme 0:5a09d01c6a2c 28 #define REG_P_L_THS_REG 0x14 // Portrait to Landscape Trip Angle is 29 degree
Rhyme 0:5a09d01c6a2c 29 #define REG_FF_MT_CFG 0x15 // Freefall/Motion function block configuration
Rhyme 0:5a09d01c6a2c 30 #define REG_FF_MT_SRC 0x16 // Freefall/Motion event source register
Rhyme 0:5a09d01c6a2c 31 #define REG_FF_MT_THS 0x17 // Freefall/Motion threshold register
Rhyme 0:5a09d01c6a2c 32 #define REG_FF_MT_COUNT 0x18 // Freefall/Motion debounce counter
Rhyme 0:5a09d01c6a2c 33 // TRANSIENT
Rhyme 0:5a09d01c6a2c 34 #define REG_TRANSIENT_CFG 0x1D // Transient functional block configuration
Rhyme 0:5a09d01c6a2c 35 #define REG_TRANSIENT_SRC 0x1E // Transient event status register
Rhyme 0:5a09d01c6a2c 36 #define REG_TRANSIENT_THS 0x1F // Transient event threshold
Rhyme 0:5a09d01c6a2c 37 #define REG_TRANSIENT_COUNT 0x20 // Transient debounce counter
Rhyme 0:5a09d01c6a2c 38 // PULSE
Rhyme 0:5a09d01c6a2c 39 #define REG_PULSE_CFG 0x21 // ELE, Double_XYZ or Single_XYZ
Rhyme 0:5a09d01c6a2c 40 #define REG_PULSE_SRC 0x22 // EA, Double_XYZ or Single_XYZ
Rhyme 0:5a09d01c6a2c 41 #define REG_PULSE_THSX 0x23 // X pulse threshold
Rhyme 0:5a09d01c6a2c 42 #define REG_PULSE_THSY 0x24 // Y pulse threshold
Rhyme 0:5a09d01c6a2c 43 #define REG_PULSE_THSZ 0x25 // Z pulse threshold
Rhyme 0:5a09d01c6a2c 44 #define REG_PULSE_TMLT 0x26 // Time limit for pulse
Rhyme 0:5a09d01c6a2c 45 #define REG_PULSE_LTCY 0x27 // Latency time for 2nd pulse
Rhyme 0:5a09d01c6a2c 46 #define REG_PULSE_WIND 0x28 // Window time for 2nd pulse
Rhyme 0:5a09d01c6a2c 47 #define REG_ASLP_COUNT 0x29 // Counter setting for Auto-SLEEP
Rhyme 0:5a09d01c6a2c 48 // Control Registers
Rhyme 0:5a09d01c6a2c 49 #define REG_CTRL_REG1 0x2A // ODR = 800Hz, STANDBY Mode
Rhyme 0:5a09d01c6a2c 50 #define REG_CTRL_REG2 0x2B // Sleep Enable, OS Modes, RST, ST
Rhyme 0:5a09d01c6a2c 51 #define REG_CTRL_REG3 0x2C // Wake from Sleep, IPOL, PP_OD
Rhyme 0:5a09d01c6a2c 52 #define REG_CTRL_REG4 0x2D // Interrupt enable register
Rhyme 0:5a09d01c6a2c 53 #define REG_CTRL_REG5 0x2E // Interrupt pin (INT1/INT2) map
Rhyme 0:5a09d01c6a2c 54 // User Offset
Rhyme 0:5a09d01c6a2c 55 #define REG_OFF_X 0x2F // X-axis offset adjust
Rhyme 0:5a09d01c6a2c 56 #define REG_OFF_Y 0x30 // Y-axis offset adjust
Rhyme 0:5a09d01c6a2c 57 #define REG_OFF_Z 0x31 // Z-axis offset adjust
Rhyme 0:5a09d01c6a2c 58
Rhyme 0:5a09d01c6a2c 59 // Value definitions
Rhyme 0:5a09d01c6a2c 60 #define BIT_TRIG_TRANS 0x20 // Transient interrupt trigger bit
Rhyme 0:5a09d01c6a2c 61 #define BIT_TRIG_LNDPRT 0x10 // Landscape/Portrati Orientation
Rhyme 0:5a09d01c6a2c 62 #define BIT_TRIG_PULSE 0x08 // Pulse interrupt trigger bit
Rhyme 0:5a09d01c6a2c 63 #define BIT_TRIG_FF_MT 0x04 // Freefall/Motion trigger bit
Rhyme 0:5a09d01c6a2c 64
Rhyme 0:5a09d01c6a2c 65 MMA8451Q::MMA8451Q(PinName sda, PinName scl, int addr) : m_i2c(sda, scl), m_addr(addr<<1) {
Rhyme 0:5a09d01c6a2c 66 // activate the peripheral
Rhyme 0:5a09d01c6a2c 67 uint8_t data[2] = {REG_CTRL_REG1, 0x01};
Rhyme 0:5a09d01c6a2c 68 writeRegs(data, 2);
Rhyme 0:5a09d01c6a2c 69 }
Rhyme 0:5a09d01c6a2c 70
Rhyme 0:5a09d01c6a2c 71 MMA8451Q::~MMA8451Q() { }
Rhyme 0:5a09d01c6a2c 72
Rhyme 0:5a09d01c6a2c 73 void MMA8451Q::readRegs(int addr, uint8_t * data, int len)
Rhyme 0:5a09d01c6a2c 74 {
Rhyme 0:5a09d01c6a2c 75 char t[1] = {addr};
Rhyme 0:5a09d01c6a2c 76 m_i2c.write(m_addr, t, 1, true);
Rhyme 0:5a09d01c6a2c 77 m_i2c.read(m_addr, (char *)data, len);
Rhyme 0:5a09d01c6a2c 78 }
Rhyme 0:5a09d01c6a2c 79
Rhyme 0:5a09d01c6a2c 80 void MMA8451Q::writeRegs(uint8_t * data, int len)
Rhyme 0:5a09d01c6a2c 81 {
Rhyme 0:5a09d01c6a2c 82 m_i2c.write(m_addr, (char *)data, len);
Rhyme 0:5a09d01c6a2c 83 }
Rhyme 0:5a09d01c6a2c 84
Rhyme 0:5a09d01c6a2c 85 int16_t MMA8451Q::getRawData(uint8_t addr)
Rhyme 0:5a09d01c6a2c 86 {
Rhyme 0:5a09d01c6a2c 87 int16_t value ;
Rhyme 0:5a09d01c6a2c 88 uint8_t data[2] ;
Rhyme 0:5a09d01c6a2c 89 readRegs(addr, data, 2) ;
Rhyme 0:5a09d01c6a2c 90 value = ((int16_t)((data[0] << 8) | data[1])) >> 2 ;
Rhyme 0:5a09d01c6a2c 91 return( value ) ;
Rhyme 0:5a09d01c6a2c 92 }
Rhyme 0:5a09d01c6a2c 93
Rhyme 0:5a09d01c6a2c 94 int16_t MMA8451Q::getRawX(void)
Rhyme 0:5a09d01c6a2c 95 {
Rhyme 0:5a09d01c6a2c 96 int16_t value ;
Rhyme 0:5a09d01c6a2c 97 value = getRawData(REG_OUT_X_MSB) ;
Rhyme 0:5a09d01c6a2c 98 return( value ) ;
Rhyme 0:5a09d01c6a2c 99 }
Rhyme 0:5a09d01c6a2c 100
Rhyme 0:5a09d01c6a2c 101 int16_t MMA8451Q::getRawY(void)
Rhyme 0:5a09d01c6a2c 102 {
Rhyme 0:5a09d01c6a2c 103 int16_t value ;
Rhyme 0:5a09d01c6a2c 104 value = getRawData(REG_OUT_Y_MSB) ;
Rhyme 0:5a09d01c6a2c 105 return( value ) ;
Rhyme 0:5a09d01c6a2c 106 }
Rhyme 0:5a09d01c6a2c 107
Rhyme 0:5a09d01c6a2c 108 int16_t MMA8451Q::getRawZ(void)
Rhyme 0:5a09d01c6a2c 109 {
Rhyme 0:5a09d01c6a2c 110 int16_t value ;
Rhyme 0:5a09d01c6a2c 111 value = getRawData(REG_OUT_Z_MSB) ;
Rhyme 0:5a09d01c6a2c 112 return( value ) ;
Rhyme 0:5a09d01c6a2c 113 }
Rhyme 0:5a09d01c6a2c 114
Rhyme 0:5a09d01c6a2c 115 float MMA8451Q::getAccX(void)
Rhyme 0:5a09d01c6a2c 116 {
Rhyme 0:5a09d01c6a2c 117 return(((float)getRawX())/4096.0) ;
Rhyme 0:5a09d01c6a2c 118 }
Rhyme 0:5a09d01c6a2c 119
Rhyme 0:5a09d01c6a2c 120 float MMA8451Q::getAccY(void)
Rhyme 0:5a09d01c6a2c 121 {
Rhyme 0:5a09d01c6a2c 122 return(((float)getRawY())/4096.0) ;
Rhyme 0:5a09d01c6a2c 123 }
Rhyme 0:5a09d01c6a2c 124
Rhyme 0:5a09d01c6a2c 125 float MMA8451Q::getAccZ(void)
Rhyme 0:5a09d01c6a2c 126 {
Rhyme 0:5a09d01c6a2c 127 return(((float)getRawZ())/4096.0) ;
Rhyme 0:5a09d01c6a2c 128 }