Driver for the IO Expander/LED Driver
SX1509.h@2:0f4b9539feca, 2017-04-26 (annotated)
- Committer:
- mwilkens241
- Date:
- Wed Apr 26 18:04:24 2017 +0000
- Revision:
- 2:0f4b9539feca
- Parent:
- 1:0176ec93c3fe
nothing here changed lol
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mwilkens241 | 0:c36e6bab0c22 | 1 | #ifndef SX1509_H |
| mwilkens241 | 0:c36e6bab0c22 | 2 | #define SX1509_H |
| mwilkens241 | 0:c36e6bab0c22 | 3 | |
| mwilkens241 | 0:c36e6bab0c22 | 4 | #include "mbed.h" |
| mwilkens241 | 0:c36e6bab0c22 | 5 | |
| mwilkens241 | 0:c36e6bab0c22 | 6 | // DEFINES - SX1509 Configuration |
| mwilkens241 | 0:c36e6bab0c22 | 7 | // ==================================================== |
| mwilkens241 | 0:c36e6bab0c22 | 8 | #define SX1509_FREQUENCY 400000 |
| mwilkens241 | 0:c36e6bab0c22 | 9 | #define SX1509_ADDR (0x3E<<1) |
| mwilkens241 | 0:c36e6bab0c22 | 10 | |
| mwilkens241 | 0:c36e6bab0c22 | 11 | // DEFINES - Register Addresses |
| mwilkens241 | 0:c36e6bab0c22 | 12 | // ==================================================== |
| mwilkens241 | 0:c36e6bab0c22 | 13 | #define REGINPUTDISABLEB (0x00) |
| mwilkens241 | 0:c36e6bab0c22 | 14 | #define REGINPUTDISABLEA (0x01) |
| mwilkens241 | 0:c36e6bab0c22 | 15 | #define REGLONGSLEWB (0x02) |
| mwilkens241 | 0:c36e6bab0c22 | 16 | #define REGLONGSLEWA (0x03) |
| mwilkens241 | 0:c36e6bab0c22 | 17 | #define REGLOWDRIVEB (0x04) |
| mwilkens241 | 0:c36e6bab0c22 | 18 | #define REGLOWDRIVEA (0x05) |
| mwilkens241 | 0:c36e6bab0c22 | 19 | #define REGPULLUPB (0x06) |
| mwilkens241 | 0:c36e6bab0c22 | 20 | #define REGPULLUPA (0x07) |
| mwilkens241 | 0:c36e6bab0c22 | 21 | #define REGPULLDOWNB (0x08) |
| mwilkens241 | 0:c36e6bab0c22 | 22 | #define REGPULLDOWNA (0x09) |
| mwilkens241 | 0:c36e6bab0c22 | 23 | #define REGOPENDRAINB (0x0A) |
| mwilkens241 | 0:c36e6bab0c22 | 24 | #define REGOPENDRAINA (0x0B) |
| mwilkens241 | 0:c36e6bab0c22 | 25 | #define REGPOLARITYB (0x0C) |
| mwilkens241 | 0:c36e6bab0c22 | 26 | #define REGPOLARITYA (0x0D) |
| mwilkens241 | 0:c36e6bab0c22 | 27 | #define REGDIRB (0x0E) |
| mwilkens241 | 0:c36e6bab0c22 | 28 | #define REGDIRA (0x0F) |
| mwilkens241 | 0:c36e6bab0c22 | 29 | #define REGDATAB (0x10) |
| mwilkens241 | 0:c36e6bab0c22 | 30 | #define REGDATAA (0x11) |
| mwilkens241 | 0:c36e6bab0c22 | 31 | #define REGINTERRUPTMASKB (0x12) |
| mwilkens241 | 0:c36e6bab0c22 | 32 | #define REGINTERRUPTMASKA (0x13) |
| mwilkens241 | 0:c36e6bab0c22 | 33 | #define REGSENSEHIGHB (0x14) |
| mwilkens241 | 0:c36e6bab0c22 | 34 | #define REGSENSELOWB (0x15) |
| mwilkens241 | 0:c36e6bab0c22 | 35 | #define REGSENSEHIGHA (0x16) |
| mwilkens241 | 0:c36e6bab0c22 | 36 | #define REGSENSELOWA (0x17) |
| mwilkens241 | 0:c36e6bab0c22 | 37 | #define REGINTERRUPTSOURCEB (0x18) |
| mwilkens241 | 0:c36e6bab0c22 | 38 | #define REGINTERRUPTSOURCEA (0x19) |
| mwilkens241 | 0:c36e6bab0c22 | 39 | #define REGEVENTSTATUSB (0x1A) |
| mwilkens241 | 0:c36e6bab0c22 | 40 | #define REGEVENTSTATUSA (0x1B) |
| mwilkens241 | 0:c36e6bab0c22 | 41 | #define REGLEVELSHIFTER1 (0x1C) |
| mwilkens241 | 0:c36e6bab0c22 | 42 | #define REGLEVELSHIFTER2 (0x1D) |
| mwilkens241 | 0:c36e6bab0c22 | 43 | #define REGCLOCK (0x1E) |
| mwilkens241 | 0:c36e6bab0c22 | 44 | #define REGMISC (0x1F) |
| mwilkens241 | 0:c36e6bab0c22 | 45 | #define REGLEDDRIVERENABLEB (0x20) |
| mwilkens241 | 0:c36e6bab0c22 | 46 | #define REGLEDDRIVERENABLEA (0x21) |
| mwilkens241 | 0:c36e6bab0c22 | 47 | // Debounce |
| mwilkens241 | 0:c36e6bab0c22 | 48 | #define REGDEBOUNCECONFIG (0x22) |
| mwilkens241 | 0:c36e6bab0c22 | 49 | #define REGDEBOUNCEENABLEB (0x23) |
| mwilkens241 | 0:c36e6bab0c22 | 50 | #define REGDEBOUNCEENABLEA (0x24) |
| mwilkens241 | 0:c36e6bab0c22 | 51 | #define REGKEYCONFIG1 (0x25) |
| mwilkens241 | 0:c36e6bab0c22 | 52 | #define REGKEYCONFIG2 (0x26) |
| mwilkens241 | 0:c36e6bab0c22 | 53 | #define REGKEYDATA1 (0x27) |
| mwilkens241 | 0:c36e6bab0c22 | 54 | #define REGKEYDATA2 (0x28) |
| mwilkens241 | 0:c36e6bab0c22 | 55 | // LED Driver |
| mwilkens241 | 0:c36e6bab0c22 | 56 | #define REGTON0 (0x29) |
| mwilkens241 | 0:c36e6bab0c22 | 57 | #define REGION0 (0x2A) |
| mwilkens241 | 0:c36e6bab0c22 | 58 | #define REGOFF0 (0x2B) |
| mwilkens241 | 0:c36e6bab0c22 | 59 | #define REGTON1 (0x2C) |
| mwilkens241 | 0:c36e6bab0c22 | 60 | #define REGION1 (0x2D) |
| mwilkens241 | 0:c36e6bab0c22 | 61 | #define REGOFF1 (0x2E) |
| mwilkens241 | 0:c36e6bab0c22 | 62 | #define REGTON2 (0x2F) |
| mwilkens241 | 0:c36e6bab0c22 | 63 | #define REGION2 (0x30) |
| mwilkens241 | 0:c36e6bab0c22 | 64 | #define REGOFF2 (0x31) |
| mwilkens241 | 0:c36e6bab0c22 | 65 | #define REGTON3 (0x32) |
| mwilkens241 | 0:c36e6bab0c22 | 66 | #define REGION3 (0x33) |
| mwilkens241 | 0:c36e6bab0c22 | 67 | #define REGOFF3 (0x34) |
| mwilkens241 | 0:c36e6bab0c22 | 68 | #define REGTON4 (0x35) |
| mwilkens241 | 0:c36e6bab0c22 | 69 | #define REGION4 (0x36) |
| mwilkens241 | 0:c36e6bab0c22 | 70 | #define REGOFF4 (0x37) |
| mwilkens241 | 0:c36e6bab0c22 | 71 | #define REGTRISE4 (0x38) |
| mwilkens241 | 0:c36e6bab0c22 | 72 | #define REGTFALL4 (0x39) |
| mwilkens241 | 0:c36e6bab0c22 | 73 | #define REGTON5 (0x3A) |
| mwilkens241 | 0:c36e6bab0c22 | 74 | #define REGION5 (0x3B) |
| mwilkens241 | 0:c36e6bab0c22 | 75 | #define REGOFF5 (0x3C) |
| mwilkens241 | 0:c36e6bab0c22 | 76 | #define REGTRISE5 (0x3D) |
| mwilkens241 | 0:c36e6bab0c22 | 77 | #define REGTFALL5 (0x3E) |
| mwilkens241 | 0:c36e6bab0c22 | 78 | #define REGTON6 (0x3F) |
| mwilkens241 | 0:c36e6bab0c22 | 79 | #define REGION6 (0x40) |
| mwilkens241 | 0:c36e6bab0c22 | 80 | #define REGOFF6 (0x41) |
| mwilkens241 | 0:c36e6bab0c22 | 81 | #define REGTRISE6 (0x42) |
| mwilkens241 | 0:c36e6bab0c22 | 82 | #define REGTFALL6 (0x43) |
| mwilkens241 | 0:c36e6bab0c22 | 83 | #define REGTON7 (0x44) |
| mwilkens241 | 0:c36e6bab0c22 | 84 | #define REGION7 (0x45) |
| mwilkens241 | 0:c36e6bab0c22 | 85 | #define REGOFF7 (0x46) |
| mwilkens241 | 0:c36e6bab0c22 | 86 | #define REGTRISE7 (0x47) |
| mwilkens241 | 0:c36e6bab0c22 | 87 | #define REGTFALL7 (0x48) |
| mwilkens241 | 0:c36e6bab0c22 | 88 | #define REGTON8 (0x49) |
| mwilkens241 | 0:c36e6bab0c22 | 89 | #define REGION8 (0x4A) |
| mwilkens241 | 0:c36e6bab0c22 | 90 | #define REGOFF8 (0x4B) |
| mwilkens241 | 0:c36e6bab0c22 | 91 | #define REGTON9 (0x4C) |
| mwilkens241 | 0:c36e6bab0c22 | 92 | #define REGION9 (0x4D) |
| mwilkens241 | 0:c36e6bab0c22 | 93 | #define REGOFF9 (0x4E) |
| mwilkens241 | 0:c36e6bab0c22 | 94 | #define REGTON10 (0x4F) |
| mwilkens241 | 0:c36e6bab0c22 | 95 | #define REGION10 (0x50) |
| mwilkens241 | 0:c36e6bab0c22 | 96 | #define REGOFF10 (0x51) |
| mwilkens241 | 0:c36e6bab0c22 | 97 | #define REGTON11 (0x52) |
| mwilkens241 | 0:c36e6bab0c22 | 98 | #define REGION11 (0x53) |
| mwilkens241 | 0:c36e6bab0c22 | 99 | #define REGOFF11 (0x54) |
| mwilkens241 | 0:c36e6bab0c22 | 100 | #define REGTON12 (0x55) |
| mwilkens241 | 0:c36e6bab0c22 | 101 | #define REGION12 (0x56) |
| mwilkens241 | 0:c36e6bab0c22 | 102 | #define REGOFF12 (0x57) |
| mwilkens241 | 0:c36e6bab0c22 | 103 | #define REGTRISE12 (0x58) |
| mwilkens241 | 0:c36e6bab0c22 | 104 | #define REGTFALL12 (0x59) |
| mwilkens241 | 0:c36e6bab0c22 | 105 | #define REGTON13 (0x5A) |
| mwilkens241 | 0:c36e6bab0c22 | 106 | #define REGION13 (0x5B) |
| mwilkens241 | 0:c36e6bab0c22 | 107 | #define REGOFF13 (0x5C) |
| mwilkens241 | 0:c36e6bab0c22 | 108 | #define REGTRISE13 (0x5D) |
| mwilkens241 | 0:c36e6bab0c22 | 109 | #define REGTFALL13 (0x5E) |
| mwilkens241 | 0:c36e6bab0c22 | 110 | #define REGTON14 (0x5F) |
| mwilkens241 | 0:c36e6bab0c22 | 111 | #define REGION14 (0x60) |
| mwilkens241 | 0:c36e6bab0c22 | 112 | #define REGOFF14 (0x61) |
| mwilkens241 | 0:c36e6bab0c22 | 113 | #define REGTRISE14 (0x62) |
| mwilkens241 | 0:c36e6bab0c22 | 114 | #define REGTFALL14 (0x63) |
| mwilkens241 | 0:c36e6bab0c22 | 115 | #define REGTON15 (0x64) |
| mwilkens241 | 0:c36e6bab0c22 | 116 | #define REGION15 (0x65) |
| mwilkens241 | 0:c36e6bab0c22 | 117 | #define REGOFF15 (0x66) |
| mwilkens241 | 0:c36e6bab0c22 | 118 | #define REGTRISE15 (0x67) |
| mwilkens241 | 0:c36e6bab0c22 | 119 | #define REGTFALL15 (0x68) |
| mwilkens241 | 0:c36e6bab0c22 | 120 | // Misc |
| mwilkens241 | 0:c36e6bab0c22 | 121 | #define REGHIGHINPUTB (0x69) |
| mwilkens241 | 0:c36e6bab0c22 | 122 | #define REGHIGHINPUTA (0x6A) |
| mwilkens241 | 0:c36e6bab0c22 | 123 | // Software Reset |
| mwilkens241 | 0:c36e6bab0c22 | 124 | #define REGRESET (0x7D) |
| mwilkens241 | 0:c36e6bab0c22 | 125 | // Test Registers (do not write) |
| mwilkens241 | 0:c36e6bab0c22 | 126 | #define REGTEST1 (0x7E) |
| mwilkens241 | 0:c36e6bab0c22 | 127 | #define REGTEST2 (0x7F) |
| mwilkens241 | 0:c36e6bab0c22 | 128 | |
| mwilkens241 | 0:c36e6bab0c22 | 129 | #define LINEAR 0 |
| mwilkens241 | 0:c36e6bab0c22 | 130 | #define LOG 1 |
| mwilkens241 | 0:c36e6bab0c22 | 131 | |
| mwilkens241 | 0:c36e6bab0c22 | 132 | class SX1509{ |
| mwilkens241 | 0:c36e6bab0c22 | 133 | private: |
| mwilkens241 | 0:c36e6bab0c22 | 134 | I2C i2c; |
| mwilkens241 | 0:c36e6bab0c22 | 135 | uint8_t div_g; |
| mwilkens241 | 0:c36e6bab0c22 | 136 | |
| mwilkens241 | 0:c36e6bab0c22 | 137 | void i2cWrite8(char reg, char data); |
| mwilkens241 | 0:c36e6bab0c22 | 138 | uint8_t i2cRead8(char reg); |
| mwilkens241 | 0:c36e6bab0c22 | 139 | uint16_t i2cRead16(char reg); |
| mwilkens241 | 0:c36e6bab0c22 | 140 | |
| mwilkens241 | 0:c36e6bab0c22 | 141 | public: |
| mwilkens241 | 0:c36e6bab0c22 | 142 | SX1509(PinName sda, PinName scl); |
| mwilkens241 | 0:c36e6bab0c22 | 143 | |
| mwilkens241 | 0:c36e6bab0c22 | 144 | enum mode_t {INPUT, OUTPUT, LED}; |
| mwilkens241 | 0:c36e6bab0c22 | 145 | |
| mwilkens241 | 0:c36e6bab0c22 | 146 | bool init(); |
| mwilkens241 | 0:c36e6bab0c22 | 147 | void enableLEDDriver(); |
| mwilkens241 | 0:c36e6bab0c22 | 148 | void enableLEDDriver(uint8_t div, bool mode); |
| mwilkens241 | 0:c36e6bab0c22 | 149 | void setLEDMode(bool mode); |
| mwilkens241 | 0:c36e6bab0c22 | 150 | void setMode(uint8_t pin, mode_t mode); |
| mwilkens241 | 0:c36e6bab0c22 | 151 | void setBreath(uint8_t pin, uint8_t fadeIn, uint8_t fadeOut); |
| mwilkens241 | 0:c36e6bab0c22 | 152 | void setBlink(uint8_t pin, uint8_t tOn, uint8_t tOff, uint8_t iOff); |
| mwilkens241 | 0:c36e6bab0c22 | 153 | void writePin(uint8_t pin, uint8_t intensity); |
| mwilkens241 | 1:0176ec93c3fe | 154 | void setReset(); |
| mwilkens241 | 2:0f4b9539feca | 155 | void fullReset(); |
| mwilkens241 | 0:c36e6bab0c22 | 156 | }; |
| mwilkens241 | 0:c36e6bab0c22 | 157 | |
| mwilkens241 | 0:c36e6bab0c22 | 158 | |
| mwilkens241 | 0:c36e6bab0c22 | 159 | #endif |