LPS22HH pressure sensor library
Dependencies: X_NUCLEO_COMMON ST_INTERFACES
lps22hh_reg.c@1:978cae936ddb, 2019-07-24 (annotated)
- Committer:
- cparata
- Date:
- Wed Jul 24 14:19:09 2019 +0000
- Revision:
- 1:978cae936ddb
- Parent:
- 0:c761bc6186e8
Format with Astyle
Who changed what in which revision?
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cparata | 0:c761bc6186e8 | 1 | /* |
cparata | 0:c761bc6186e8 | 2 | ****************************************************************************** |
cparata | 0:c761bc6186e8 | 3 | * @file lps22hh_reg.c |
cparata | 0:c761bc6186e8 | 4 | * @author Sensors Software Solution Team |
cparata | 0:c761bc6186e8 | 5 | * @brief LPS22HH driver file |
cparata | 0:c761bc6186e8 | 6 | ****************************************************************************** |
cparata | 0:c761bc6186e8 | 7 | * @attention |
cparata | 0:c761bc6186e8 | 8 | * |
cparata | 0:c761bc6186e8 | 9 | * <h2><center>© COPYRIGHT(c) 2018 STMicroelectronics</center></h2> |
cparata | 0:c761bc6186e8 | 10 | * |
cparata | 0:c761bc6186e8 | 11 | * Redistribution and use in source and binary forms, with or without |
cparata | 0:c761bc6186e8 | 12 | * modification, are permitted provided that the following conditions |
cparata | 0:c761bc6186e8 | 13 | * are met: |
cparata | 0:c761bc6186e8 | 14 | * 1. Redistributions of source code must retain the above copyright notice, |
cparata | 0:c761bc6186e8 | 15 | * this list of conditions and the following disclaimer. |
cparata | 0:c761bc6186e8 | 16 | * 2. Redistributions in binary form must reproduce the above copyright |
cparata | 0:c761bc6186e8 | 17 | * notice, this list of conditions and the following disclaimer in the |
cparata | 0:c761bc6186e8 | 18 | * documentation and/or other materials provided with the distribution. |
cparata | 0:c761bc6186e8 | 19 | * 3. Neither the name of STMicroelectronics nor the names of its |
cparata | 0:c761bc6186e8 | 20 | * contributors may be used to endorse or promote products derived from |
cparata | 0:c761bc6186e8 | 21 | * this software without specific prior written permission. |
cparata | 0:c761bc6186e8 | 22 | * |
cparata | 0:c761bc6186e8 | 23 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
cparata | 0:c761bc6186e8 | 24 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
cparata | 0:c761bc6186e8 | 25 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
cparata | 0:c761bc6186e8 | 26 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
cparata | 0:c761bc6186e8 | 27 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
cparata | 0:c761bc6186e8 | 28 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
cparata | 0:c761bc6186e8 | 29 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
cparata | 0:c761bc6186e8 | 30 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
cparata | 0:c761bc6186e8 | 31 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
cparata | 0:c761bc6186e8 | 32 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
cparata | 0:c761bc6186e8 | 33 | * POSSIBILITY OF SUCH DAMAGE. |
cparata | 0:c761bc6186e8 | 34 | * |
cparata | 0:c761bc6186e8 | 35 | */ |
cparata | 0:c761bc6186e8 | 36 | |
cparata | 0:c761bc6186e8 | 37 | #include "lps22hh_reg.h" |
cparata | 0:c761bc6186e8 | 38 | |
cparata | 0:c761bc6186e8 | 39 | /** |
cparata | 0:c761bc6186e8 | 40 | * @defgroup LPS22HH |
cparata | 0:c761bc6186e8 | 41 | * @brief This file provides a set of functions needed to drive the |
cparata | 0:c761bc6186e8 | 42 | * lps22hh enhanced inertial module. |
cparata | 0:c761bc6186e8 | 43 | * @{ |
cparata | 0:c761bc6186e8 | 44 | * |
cparata | 0:c761bc6186e8 | 45 | */ |
cparata | 0:c761bc6186e8 | 46 | |
cparata | 0:c761bc6186e8 | 47 | /** |
cparata | 0:c761bc6186e8 | 48 | * @defgroup LPS22HH_Interfaces_Functions |
cparata | 0:c761bc6186e8 | 49 | * @brief This section provide a set of functions used to read and |
cparata | 0:c761bc6186e8 | 50 | * write a generic register of the device. |
cparata | 0:c761bc6186e8 | 51 | * MANDATORY: return 0 -> no Error. |
cparata | 0:c761bc6186e8 | 52 | * @{ |
cparata | 0:c761bc6186e8 | 53 | * |
cparata | 0:c761bc6186e8 | 54 | */ |
cparata | 0:c761bc6186e8 | 55 | |
cparata | 0:c761bc6186e8 | 56 | /** |
cparata | 0:c761bc6186e8 | 57 | * @brief Read generic device register |
cparata | 0:c761bc6186e8 | 58 | * |
cparata | 0:c761bc6186e8 | 59 | * @param ctx read / write interface definitions(ptr) |
cparata | 0:c761bc6186e8 | 60 | * @param reg register to read |
cparata | 0:c761bc6186e8 | 61 | * @param data pointer to buffer that store the data read(ptr) |
cparata | 0:c761bc6186e8 | 62 | * @param len number of consecutive register to read |
cparata | 0:c761bc6186e8 | 63 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 64 | * |
cparata | 0:c761bc6186e8 | 65 | */ |
cparata | 1:978cae936ddb | 66 | int32_t lps22hh_read_reg(lps22hh_ctx_t *ctx, uint8_t reg, uint8_t *data, |
cparata | 0:c761bc6186e8 | 67 | uint16_t len) |
cparata | 0:c761bc6186e8 | 68 | { |
cparata | 1:978cae936ddb | 69 | int32_t ret; |
cparata | 1:978cae936ddb | 70 | ret = ctx->read_reg(ctx->handle, reg, data, len); |
cparata | 1:978cae936ddb | 71 | return ret; |
cparata | 0:c761bc6186e8 | 72 | } |
cparata | 0:c761bc6186e8 | 73 | |
cparata | 0:c761bc6186e8 | 74 | /** |
cparata | 0:c761bc6186e8 | 75 | * @brief Write generic device register |
cparata | 0:c761bc6186e8 | 76 | * |
cparata | 0:c761bc6186e8 | 77 | * @param ctx read / write interface definitions(ptr) |
cparata | 0:c761bc6186e8 | 78 | * @param reg register to write |
cparata | 0:c761bc6186e8 | 79 | * @param data pointer to data to write in register reg(ptr) |
cparata | 0:c761bc6186e8 | 80 | * @param len number of consecutive register to write |
cparata | 0:c761bc6186e8 | 81 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 82 | * |
cparata | 0:c761bc6186e8 | 83 | */ |
cparata | 1:978cae936ddb | 84 | int32_t lps22hh_write_reg(lps22hh_ctx_t *ctx, uint8_t reg, uint8_t *data, |
cparata | 1:978cae936ddb | 85 | uint16_t len) |
cparata | 0:c761bc6186e8 | 86 | { |
cparata | 1:978cae936ddb | 87 | int32_t ret; |
cparata | 1:978cae936ddb | 88 | ret = ctx->write_reg(ctx->handle, reg, data, len); |
cparata | 1:978cae936ddb | 89 | return ret; |
cparata | 0:c761bc6186e8 | 90 | } |
cparata | 0:c761bc6186e8 | 91 | |
cparata | 0:c761bc6186e8 | 92 | /** |
cparata | 0:c761bc6186e8 | 93 | * @} |
cparata | 0:c761bc6186e8 | 94 | * |
cparata | 0:c761bc6186e8 | 95 | */ |
cparata | 0:c761bc6186e8 | 96 | |
cparata | 0:c761bc6186e8 | 97 | /** |
cparata | 0:c761bc6186e8 | 98 | * @defgroup LPS22HH_Sensitivity |
cparata | 0:c761bc6186e8 | 99 | * @brief These functions convert raw-data into engineering units. |
cparata | 0:c761bc6186e8 | 100 | * @{ |
cparata | 0:c761bc6186e8 | 101 | * |
cparata | 0:c761bc6186e8 | 102 | */ |
cparata | 0:c761bc6186e8 | 103 | float lps22hh_from_lsb_to_hpa(int16_t lsb) |
cparata | 0:c761bc6186e8 | 104 | { |
cparata | 1:978cae936ddb | 105 | return ((float) lsb / 4096.0f); |
cparata | 0:c761bc6186e8 | 106 | } |
cparata | 0:c761bc6186e8 | 107 | |
cparata | 0:c761bc6186e8 | 108 | float lps22hh_from_lsb_to_celsius(int16_t lsb) |
cparata | 0:c761bc6186e8 | 109 | { |
cparata | 1:978cae936ddb | 110 | return ((float) lsb / 100.0f); |
cparata | 0:c761bc6186e8 | 111 | } |
cparata | 0:c761bc6186e8 | 112 | |
cparata | 0:c761bc6186e8 | 113 | /** |
cparata | 0:c761bc6186e8 | 114 | * @} |
cparata | 0:c761bc6186e8 | 115 | * |
cparata | 0:c761bc6186e8 | 116 | */ |
cparata | 0:c761bc6186e8 | 117 | |
cparata | 0:c761bc6186e8 | 118 | /** |
cparata | 0:c761bc6186e8 | 119 | * @defgroup LPS22HH_Data_Generation |
cparata | 0:c761bc6186e8 | 120 | * @brief This section groups all the functions concerning |
cparata | 0:c761bc6186e8 | 121 | * data generation. |
cparata | 0:c761bc6186e8 | 122 | * @{ |
cparata | 0:c761bc6186e8 | 123 | * |
cparata | 0:c761bc6186e8 | 124 | */ |
cparata | 0:c761bc6186e8 | 125 | |
cparata | 0:c761bc6186e8 | 126 | /** |
cparata | 0:c761bc6186e8 | 127 | * @brief Reset Autozero function.[set] |
cparata | 0:c761bc6186e8 | 128 | * |
cparata | 0:c761bc6186e8 | 129 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 130 | * @param val change the values of reset_az in reg INTERRUPT_CFG |
cparata | 0:c761bc6186e8 | 131 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 132 | * |
cparata | 0:c761bc6186e8 | 133 | */ |
cparata | 0:c761bc6186e8 | 134 | int32_t lps22hh_autozero_rst_set(lps22hh_ctx_t *ctx, uint8_t val) |
cparata | 0:c761bc6186e8 | 135 | { |
cparata | 1:978cae936ddb | 136 | lps22hh_interrupt_cfg_t reg; |
cparata | 1:978cae936ddb | 137 | int32_t ret; |
cparata | 0:c761bc6186e8 | 138 | |
cparata | 1:978cae936ddb | 139 | ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 140 | if (ret == 0) { |
cparata | 1:978cae936ddb | 141 | reg.reset_az = val; |
cparata | 1:978cae936ddb | 142 | ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 143 | } |
cparata | 1:978cae936ddb | 144 | return ret; |
cparata | 0:c761bc6186e8 | 145 | } |
cparata | 0:c761bc6186e8 | 146 | |
cparata | 0:c761bc6186e8 | 147 | /** |
cparata | 0:c761bc6186e8 | 148 | * @brief Reset Autozero function.[get] |
cparata | 0:c761bc6186e8 | 149 | * |
cparata | 0:c761bc6186e8 | 150 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 151 | * @param val change the values of reset_az in reg INTERRUPT_CFG |
cparata | 0:c761bc6186e8 | 152 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 153 | * |
cparata | 0:c761bc6186e8 | 154 | */ |
cparata | 0:c761bc6186e8 | 155 | int32_t lps22hh_autozero_rst_get(lps22hh_ctx_t *ctx, uint8_t *val) |
cparata | 0:c761bc6186e8 | 156 | { |
cparata | 1:978cae936ddb | 157 | lps22hh_interrupt_cfg_t reg; |
cparata | 1:978cae936ddb | 158 | int32_t ret; |
cparata | 0:c761bc6186e8 | 159 | |
cparata | 1:978cae936ddb | 160 | ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 161 | *val = reg.reset_az; |
cparata | 0:c761bc6186e8 | 162 | |
cparata | 1:978cae936ddb | 163 | return ret; |
cparata | 0:c761bc6186e8 | 164 | } |
cparata | 0:c761bc6186e8 | 165 | |
cparata | 0:c761bc6186e8 | 166 | /** |
cparata | 0:c761bc6186e8 | 167 | * @brief Enable Autozero function.[set] |
cparata | 0:c761bc6186e8 | 168 | * |
cparata | 0:c761bc6186e8 | 169 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 170 | * @param val change the values of autozero in reg INTERRUPT_CFG |
cparata | 0:c761bc6186e8 | 171 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 172 | * |
cparata | 0:c761bc6186e8 | 173 | */ |
cparata | 0:c761bc6186e8 | 174 | int32_t lps22hh_autozero_set(lps22hh_ctx_t *ctx, uint8_t val) |
cparata | 0:c761bc6186e8 | 175 | { |
cparata | 1:978cae936ddb | 176 | lps22hh_interrupt_cfg_t reg; |
cparata | 1:978cae936ddb | 177 | int32_t ret; |
cparata | 0:c761bc6186e8 | 178 | |
cparata | 1:978cae936ddb | 179 | ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 180 | if (ret == 0) { |
cparata | 1:978cae936ddb | 181 | reg.autozero = val; |
cparata | 1:978cae936ddb | 182 | ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 183 | } |
cparata | 1:978cae936ddb | 184 | return ret; |
cparata | 0:c761bc6186e8 | 185 | } |
cparata | 0:c761bc6186e8 | 186 | |
cparata | 0:c761bc6186e8 | 187 | /** |
cparata | 0:c761bc6186e8 | 188 | * @brief Enable Autozero function.[get] |
cparata | 0:c761bc6186e8 | 189 | * |
cparata | 0:c761bc6186e8 | 190 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 191 | * @param val change the values of autozero in reg INTERRUPT_CFG |
cparata | 0:c761bc6186e8 | 192 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 193 | * |
cparata | 0:c761bc6186e8 | 194 | */ |
cparata | 0:c761bc6186e8 | 195 | int32_t lps22hh_autozero_get(lps22hh_ctx_t *ctx, uint8_t *val) |
cparata | 0:c761bc6186e8 | 196 | { |
cparata | 1:978cae936ddb | 197 | lps22hh_interrupt_cfg_t reg; |
cparata | 1:978cae936ddb | 198 | int32_t ret; |
cparata | 0:c761bc6186e8 | 199 | |
cparata | 1:978cae936ddb | 200 | ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 201 | *val = reg.autozero; |
cparata | 0:c761bc6186e8 | 202 | |
cparata | 1:978cae936ddb | 203 | return ret; |
cparata | 0:c761bc6186e8 | 204 | } |
cparata | 0:c761bc6186e8 | 205 | |
cparata | 0:c761bc6186e8 | 206 | /** |
cparata | 0:c761bc6186e8 | 207 | * @brief Reset AutoRifP function.[set] |
cparata | 0:c761bc6186e8 | 208 | * |
cparata | 0:c761bc6186e8 | 209 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 210 | * @param val change the values of reset_arp in reg INTERRUPT_CFG |
cparata | 0:c761bc6186e8 | 211 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 212 | * |
cparata | 0:c761bc6186e8 | 213 | */ |
cparata | 0:c761bc6186e8 | 214 | int32_t lps22hh_pressure_snap_rst_set(lps22hh_ctx_t *ctx, uint8_t val) |
cparata | 0:c761bc6186e8 | 215 | { |
cparata | 1:978cae936ddb | 216 | lps22hh_interrupt_cfg_t reg; |
cparata | 1:978cae936ddb | 217 | int32_t ret; |
cparata | 0:c761bc6186e8 | 218 | |
cparata | 1:978cae936ddb | 219 | ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 220 | if (ret == 0) { |
cparata | 1:978cae936ddb | 221 | reg.reset_arp = val; |
cparata | 1:978cae936ddb | 222 | ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 223 | } |
cparata | 1:978cae936ddb | 224 | return ret; |
cparata | 0:c761bc6186e8 | 225 | } |
cparata | 0:c761bc6186e8 | 226 | |
cparata | 0:c761bc6186e8 | 227 | /** |
cparata | 0:c761bc6186e8 | 228 | * @brief Reset AutoRifP function.[get] |
cparata | 0:c761bc6186e8 | 229 | * |
cparata | 0:c761bc6186e8 | 230 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 231 | * @param val change the values of reset_arp in reg INTERRUPT_CFG |
cparata | 0:c761bc6186e8 | 232 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 233 | * |
cparata | 0:c761bc6186e8 | 234 | */ |
cparata | 0:c761bc6186e8 | 235 | int32_t lps22hh_pressure_snap_rst_get(lps22hh_ctx_t *ctx, uint8_t *val) |
cparata | 0:c761bc6186e8 | 236 | { |
cparata | 1:978cae936ddb | 237 | lps22hh_interrupt_cfg_t reg; |
cparata | 1:978cae936ddb | 238 | int32_t ret; |
cparata | 0:c761bc6186e8 | 239 | |
cparata | 1:978cae936ddb | 240 | ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 241 | *val = reg.reset_arp; |
cparata | 0:c761bc6186e8 | 242 | |
cparata | 1:978cae936ddb | 243 | return ret; |
cparata | 0:c761bc6186e8 | 244 | } |
cparata | 0:c761bc6186e8 | 245 | |
cparata | 0:c761bc6186e8 | 246 | /** |
cparata | 0:c761bc6186e8 | 247 | * @brief Enable AutoRefP function.[set] |
cparata | 0:c761bc6186e8 | 248 | * |
cparata | 0:c761bc6186e8 | 249 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 250 | * @param val change the values of autorefp in reg INTERRUPT_CFG |
cparata | 0:c761bc6186e8 | 251 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 252 | * |
cparata | 0:c761bc6186e8 | 253 | */ |
cparata | 0:c761bc6186e8 | 254 | int32_t lps22hh_pressure_snap_set(lps22hh_ctx_t *ctx, uint8_t val) |
cparata | 0:c761bc6186e8 | 255 | { |
cparata | 1:978cae936ddb | 256 | lps22hh_interrupt_cfg_t reg; |
cparata | 1:978cae936ddb | 257 | int32_t ret; |
cparata | 0:c761bc6186e8 | 258 | |
cparata | 1:978cae936ddb | 259 | ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 260 | if (ret == 0) { |
cparata | 1:978cae936ddb | 261 | reg.autorefp = val; |
cparata | 1:978cae936ddb | 262 | ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 263 | } |
cparata | 1:978cae936ddb | 264 | return ret; |
cparata | 0:c761bc6186e8 | 265 | } |
cparata | 0:c761bc6186e8 | 266 | |
cparata | 0:c761bc6186e8 | 267 | /** |
cparata | 0:c761bc6186e8 | 268 | * @brief Enable AutoRefP function.[get] |
cparata | 0:c761bc6186e8 | 269 | * |
cparata | 0:c761bc6186e8 | 270 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 271 | * @param val change the values of autorefp in reg INTERRUPT_CFG |
cparata | 0:c761bc6186e8 | 272 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 273 | * |
cparata | 0:c761bc6186e8 | 274 | */ |
cparata | 0:c761bc6186e8 | 275 | int32_t lps22hh_pressure_snap_get(lps22hh_ctx_t *ctx, uint8_t *val) |
cparata | 0:c761bc6186e8 | 276 | { |
cparata | 1:978cae936ddb | 277 | lps22hh_interrupt_cfg_t reg; |
cparata | 1:978cae936ddb | 278 | int32_t ret; |
cparata | 0:c761bc6186e8 | 279 | |
cparata | 1:978cae936ddb | 280 | ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 281 | *val = reg.autorefp; |
cparata | 0:c761bc6186e8 | 282 | |
cparata | 1:978cae936ddb | 283 | return ret; |
cparata | 0:c761bc6186e8 | 284 | } |
cparata | 0:c761bc6186e8 | 285 | |
cparata | 0:c761bc6186e8 | 286 | /** |
cparata | 0:c761bc6186e8 | 287 | * @brief Block Data Update.[set] |
cparata | 0:c761bc6186e8 | 288 | * |
cparata | 0:c761bc6186e8 | 289 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 290 | * @param val change the values of bdu in reg CTRL_REG1 |
cparata | 0:c761bc6186e8 | 291 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 292 | * |
cparata | 0:c761bc6186e8 | 293 | */ |
cparata | 0:c761bc6186e8 | 294 | int32_t lps22hh_block_data_update_set(lps22hh_ctx_t *ctx, uint8_t val) |
cparata | 0:c761bc6186e8 | 295 | { |
cparata | 1:978cae936ddb | 296 | lps22hh_ctrl_reg1_t reg; |
cparata | 1:978cae936ddb | 297 | int32_t ret; |
cparata | 0:c761bc6186e8 | 298 | |
cparata | 1:978cae936ddb | 299 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 300 | if (ret == 0) { |
cparata | 1:978cae936ddb | 301 | reg.bdu = val; |
cparata | 1:978cae936ddb | 302 | ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 303 | } |
cparata | 1:978cae936ddb | 304 | return ret; |
cparata | 0:c761bc6186e8 | 305 | } |
cparata | 0:c761bc6186e8 | 306 | |
cparata | 0:c761bc6186e8 | 307 | /** |
cparata | 0:c761bc6186e8 | 308 | * @brief Block Data Update.[get] |
cparata | 0:c761bc6186e8 | 309 | * |
cparata | 0:c761bc6186e8 | 310 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 311 | * @param val change the values of bdu in reg CTRL_REG1 |
cparata | 0:c761bc6186e8 | 312 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 313 | * |
cparata | 0:c761bc6186e8 | 314 | */ |
cparata | 0:c761bc6186e8 | 315 | int32_t lps22hh_block_data_update_get(lps22hh_ctx_t *ctx, uint8_t *val) |
cparata | 0:c761bc6186e8 | 316 | { |
cparata | 1:978cae936ddb | 317 | lps22hh_ctrl_reg1_t reg; |
cparata | 1:978cae936ddb | 318 | int32_t ret; |
cparata | 0:c761bc6186e8 | 319 | |
cparata | 1:978cae936ddb | 320 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 321 | *val = reg.bdu; |
cparata | 0:c761bc6186e8 | 322 | |
cparata | 1:978cae936ddb | 323 | return ret; |
cparata | 0:c761bc6186e8 | 324 | } |
cparata | 0:c761bc6186e8 | 325 | |
cparata | 0:c761bc6186e8 | 326 | /** |
cparata | 0:c761bc6186e8 | 327 | * @brief Output data rate selection.[set] |
cparata | 0:c761bc6186e8 | 328 | * |
cparata | 0:c761bc6186e8 | 329 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 330 | * @param val change the values of odr in reg CTRL_REG1 |
cparata | 0:c761bc6186e8 | 331 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 332 | * |
cparata | 0:c761bc6186e8 | 333 | */ |
cparata | 0:c761bc6186e8 | 334 | int32_t lps22hh_data_rate_set(lps22hh_ctx_t *ctx, lps22hh_odr_t val) |
cparata | 0:c761bc6186e8 | 335 | { |
cparata | 1:978cae936ddb | 336 | lps22hh_ctrl_reg1_t ctrl_reg1; |
cparata | 1:978cae936ddb | 337 | lps22hh_ctrl_reg2_t ctrl_reg2; |
cparata | 1:978cae936ddb | 338 | int32_t ret; |
cparata | 0:c761bc6186e8 | 339 | |
cparata | 1:978cae936ddb | 340 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); |
cparata | 1:978cae936ddb | 341 | if (ret == 0) { |
cparata | 1:978cae936ddb | 342 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); |
cparata | 1:978cae936ddb | 343 | } |
cparata | 1:978cae936ddb | 344 | if (ret == 0) { |
cparata | 1:978cae936ddb | 345 | ctrl_reg1.odr = (uint8_t)val & 0x07U; |
cparata | 1:978cae936ddb | 346 | ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); |
cparata | 1:978cae936ddb | 347 | } |
cparata | 1:978cae936ddb | 348 | if (ret == 0) { |
cparata | 1:978cae936ddb | 349 | ctrl_reg2.low_noise_en = ((uint8_t)val & 0x10U) >> 4; |
cparata | 1:978cae936ddb | 350 | ctrl_reg2.one_shot = ((uint8_t)val & 0x08U) >> 3; |
cparata | 1:978cae936ddb | 351 | ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); |
cparata | 1:978cae936ddb | 352 | } |
cparata | 1:978cae936ddb | 353 | return ret; |
cparata | 0:c761bc6186e8 | 354 | } |
cparata | 0:c761bc6186e8 | 355 | |
cparata | 0:c761bc6186e8 | 356 | /** |
cparata | 0:c761bc6186e8 | 357 | * @brief Output data rate selection.[get] |
cparata | 0:c761bc6186e8 | 358 | * |
cparata | 0:c761bc6186e8 | 359 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 360 | * @param val Get the values of odr in reg CTRL_REG1 |
cparata | 0:c761bc6186e8 | 361 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 362 | * |
cparata | 0:c761bc6186e8 | 363 | */ |
cparata | 0:c761bc6186e8 | 364 | int32_t lps22hh_data_rate_get(lps22hh_ctx_t *ctx, lps22hh_odr_t *val) |
cparata | 0:c761bc6186e8 | 365 | { |
cparata | 1:978cae936ddb | 366 | lps22hh_ctrl_reg1_t ctrl_reg1; |
cparata | 1:978cae936ddb | 367 | lps22hh_ctrl_reg2_t ctrl_reg2; |
cparata | 1:978cae936ddb | 368 | int32_t ret; |
cparata | 0:c761bc6186e8 | 369 | |
cparata | 1:978cae936ddb | 370 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); |
cparata | 1:978cae936ddb | 371 | if (ret == 0) { |
cparata | 1:978cae936ddb | 372 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); |
cparata | 0:c761bc6186e8 | 373 | } |
cparata | 1:978cae936ddb | 374 | if (ret == 0) { |
cparata | 1:978cae936ddb | 375 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); |
cparata | 1:978cae936ddb | 376 | switch (((ctrl_reg2.low_noise_en << 4) + (ctrl_reg2.one_shot << 3) + |
cparata | 1:978cae936ddb | 377 | ctrl_reg1.odr)) { |
cparata | 1:978cae936ddb | 378 | case LPS22HH_POWER_DOWN: |
cparata | 1:978cae936ddb | 379 | *val = LPS22HH_POWER_DOWN; |
cparata | 1:978cae936ddb | 380 | break; |
cparata | 1:978cae936ddb | 381 | case LPS22HH_ONE_SHOOT: |
cparata | 1:978cae936ddb | 382 | *val = LPS22HH_ONE_SHOOT; |
cparata | 1:978cae936ddb | 383 | break; |
cparata | 1:978cae936ddb | 384 | case LPS22HH_1_Hz: |
cparata | 1:978cae936ddb | 385 | *val = LPS22HH_1_Hz; |
cparata | 1:978cae936ddb | 386 | break; |
cparata | 1:978cae936ddb | 387 | case LPS22HH_10_Hz: |
cparata | 1:978cae936ddb | 388 | *val = LPS22HH_10_Hz; |
cparata | 1:978cae936ddb | 389 | break; |
cparata | 1:978cae936ddb | 390 | case LPS22HH_25_Hz: |
cparata | 1:978cae936ddb | 391 | *val = LPS22HH_25_Hz; |
cparata | 1:978cae936ddb | 392 | break; |
cparata | 1:978cae936ddb | 393 | case LPS22HH_50_Hz: |
cparata | 1:978cae936ddb | 394 | *val = LPS22HH_50_Hz; |
cparata | 1:978cae936ddb | 395 | break; |
cparata | 1:978cae936ddb | 396 | case LPS22HH_75_Hz: |
cparata | 1:978cae936ddb | 397 | *val = LPS22HH_75_Hz; |
cparata | 1:978cae936ddb | 398 | break; |
cparata | 1:978cae936ddb | 399 | case LPS22HH_1_Hz_LOW_NOISE: |
cparata | 1:978cae936ddb | 400 | *val = LPS22HH_1_Hz_LOW_NOISE; |
cparata | 1:978cae936ddb | 401 | break; |
cparata | 1:978cae936ddb | 402 | case LPS22HH_10_Hz_LOW_NOISE: |
cparata | 1:978cae936ddb | 403 | *val = LPS22HH_10_Hz_LOW_NOISE; |
cparata | 1:978cae936ddb | 404 | break; |
cparata | 1:978cae936ddb | 405 | case LPS22HH_25_Hz_LOW_NOISE: |
cparata | 1:978cae936ddb | 406 | *val = LPS22HH_25_Hz_LOW_NOISE; |
cparata | 1:978cae936ddb | 407 | break; |
cparata | 1:978cae936ddb | 408 | case LPS22HH_50_Hz_LOW_NOISE: |
cparata | 1:978cae936ddb | 409 | *val = LPS22HH_50_Hz_LOW_NOISE; |
cparata | 1:978cae936ddb | 410 | break; |
cparata | 1:978cae936ddb | 411 | case LPS22HH_75_Hz_LOW_NOISE: |
cparata | 1:978cae936ddb | 412 | *val = LPS22HH_75_Hz_LOW_NOISE; |
cparata | 1:978cae936ddb | 413 | break; |
cparata | 1:978cae936ddb | 414 | case LPS22HH_100_Hz: |
cparata | 1:978cae936ddb | 415 | *val = LPS22HH_100_Hz; |
cparata | 1:978cae936ddb | 416 | break; |
cparata | 1:978cae936ddb | 417 | case LPS22HH_200_Hz: |
cparata | 1:978cae936ddb | 418 | *val = LPS22HH_200_Hz; |
cparata | 1:978cae936ddb | 419 | break; |
cparata | 1:978cae936ddb | 420 | default: |
cparata | 1:978cae936ddb | 421 | *val = LPS22HH_POWER_DOWN; |
cparata | 1:978cae936ddb | 422 | break; |
cparata | 1:978cae936ddb | 423 | } |
cparata | 1:978cae936ddb | 424 | } |
cparata | 1:978cae936ddb | 425 | return ret; |
cparata | 0:c761bc6186e8 | 426 | } |
cparata | 0:c761bc6186e8 | 427 | |
cparata | 0:c761bc6186e8 | 428 | /** |
cparata | 0:c761bc6186e8 | 429 | * @brief The Reference pressure value is a 16-bit data |
cparata | 0:c761bc6186e8 | 430 | * expressed as 2’s complement. The value is used |
cparata | 0:c761bc6186e8 | 431 | * when AUTOZERO or AUTORIFP function is enabled.[set] |
cparata | 0:c761bc6186e8 | 432 | * |
cparata | 0:c761bc6186e8 | 433 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 434 | * @param buff buffer that contains data to write |
cparata | 0:c761bc6186e8 | 435 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 436 | * |
cparata | 0:c761bc6186e8 | 437 | */ |
cparata | 0:c761bc6186e8 | 438 | int32_t lps22hh_pressure_ref_set(lps22hh_ctx_t *ctx, uint8_t *buff) |
cparata | 0:c761bc6186e8 | 439 | { |
cparata | 1:978cae936ddb | 440 | int32_t ret; |
cparata | 1:978cae936ddb | 441 | ret = lps22hh_write_reg(ctx, LPS22HH_REF_P_XL, buff, 2); |
cparata | 1:978cae936ddb | 442 | return ret; |
cparata | 0:c761bc6186e8 | 443 | } |
cparata | 0:c761bc6186e8 | 444 | |
cparata | 0:c761bc6186e8 | 445 | /** |
cparata | 0:c761bc6186e8 | 446 | * @brief The Reference pressure value is a 16-bit |
cparata | 0:c761bc6186e8 | 447 | * data expressed as 2’s complement. |
cparata | 0:c761bc6186e8 | 448 | * The value is used when AUTOZERO or AUTORIFP |
cparata | 0:c761bc6186e8 | 449 | * function is enabled.[get] |
cparata | 0:c761bc6186e8 | 450 | * |
cparata | 0:c761bc6186e8 | 451 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 452 | * @param buff buffer that stores data read |
cparata | 0:c761bc6186e8 | 453 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 454 | * |
cparata | 0:c761bc6186e8 | 455 | */ |
cparata | 0:c761bc6186e8 | 456 | int32_t lps22hh_pressure_ref_get(lps22hh_ctx_t *ctx, uint8_t *buff) |
cparata | 0:c761bc6186e8 | 457 | { |
cparata | 1:978cae936ddb | 458 | int32_t ret; |
cparata | 1:978cae936ddb | 459 | ret = lps22hh_read_reg(ctx, LPS22HH_REF_P_XL, buff, 2); |
cparata | 1:978cae936ddb | 460 | return ret; |
cparata | 0:c761bc6186e8 | 461 | } |
cparata | 0:c761bc6186e8 | 462 | |
cparata | 0:c761bc6186e8 | 463 | /** |
cparata | 0:c761bc6186e8 | 464 | * @brief The pressure offset value is 16-bit data |
cparata | 0:c761bc6186e8 | 465 | * that can be used to implement one-point |
cparata | 0:c761bc6186e8 | 466 | * calibration (OPC) after soldering.[set] |
cparata | 0:c761bc6186e8 | 467 | * |
cparata | 0:c761bc6186e8 | 468 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 469 | * @param buff buffer that contains data to write |
cparata | 0:c761bc6186e8 | 470 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 471 | * |
cparata | 0:c761bc6186e8 | 472 | */ |
cparata | 0:c761bc6186e8 | 473 | int32_t lps22hh_pressure_offset_set(lps22hh_ctx_t *ctx, uint8_t *buff) |
cparata | 0:c761bc6186e8 | 474 | { |
cparata | 1:978cae936ddb | 475 | int32_t ret; |
cparata | 1:978cae936ddb | 476 | ret = lps22hh_write_reg(ctx, LPS22HH_RPDS_L, buff, 2); |
cparata | 1:978cae936ddb | 477 | return ret; |
cparata | 0:c761bc6186e8 | 478 | } |
cparata | 0:c761bc6186e8 | 479 | |
cparata | 0:c761bc6186e8 | 480 | /** |
cparata | 0:c761bc6186e8 | 481 | * @brief The pressure offset value is 16-bit |
cparata | 0:c761bc6186e8 | 482 | * data that can be used to implement |
cparata | 0:c761bc6186e8 | 483 | * one-point calibration (OPC) after |
cparata | 0:c761bc6186e8 | 484 | * soldering.[get] |
cparata | 0:c761bc6186e8 | 485 | * |
cparata | 0:c761bc6186e8 | 486 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 487 | * @param buff buffer that stores data read |
cparata | 0:c761bc6186e8 | 488 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 489 | * |
cparata | 0:c761bc6186e8 | 490 | */ |
cparata | 0:c761bc6186e8 | 491 | int32_t lps22hh_pressure_offset_get(lps22hh_ctx_t *ctx, uint8_t *buff) |
cparata | 0:c761bc6186e8 | 492 | { |
cparata | 1:978cae936ddb | 493 | int32_t ret; |
cparata | 1:978cae936ddb | 494 | ret = lps22hh_read_reg(ctx, LPS22HH_RPDS_L, buff, 2); |
cparata | 1:978cae936ddb | 495 | return ret; |
cparata | 0:c761bc6186e8 | 496 | } |
cparata | 0:c761bc6186e8 | 497 | |
cparata | 0:c761bc6186e8 | 498 | /** |
cparata | 0:c761bc6186e8 | 499 | * @brief Read all the interrupt/status flag of the device.[get] |
cparata | 0:c761bc6186e8 | 500 | * |
cparata | 0:c761bc6186e8 | 501 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 502 | * @param val registers STATUS,FIFO_STATUS2,INT_SOURCE |
cparata | 0:c761bc6186e8 | 503 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 504 | * |
cparata | 0:c761bc6186e8 | 505 | */ |
cparata | 0:c761bc6186e8 | 506 | int32_t lps22hh_all_sources_get(lps22hh_ctx_t *ctx, lps22hh_all_sources_t *val) |
cparata | 0:c761bc6186e8 | 507 | { |
cparata | 1:978cae936ddb | 508 | int32_t ret; |
cparata | 0:c761bc6186e8 | 509 | |
cparata | 1:978cae936ddb | 510 | ret = lps22hh_read_reg(ctx, LPS22HH_INT_SOURCE, |
cparata | 1:978cae936ddb | 511 | (uint8_t *) & (val->int_source), 1); |
cparata | 1:978cae936ddb | 512 | if (ret == 0) { |
cparata | 1:978cae936ddb | 513 | ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, |
cparata | 1:978cae936ddb | 514 | (uint8_t *) & (val->fifo_status2), 1); |
cparata | 1:978cae936ddb | 515 | } |
cparata | 1:978cae936ddb | 516 | if (ret == 0) { |
cparata | 1:978cae936ddb | 517 | ret = lps22hh_read_reg(ctx, LPS22HH_STATUS, |
cparata | 1:978cae936ddb | 518 | (uint8_t *) & (val->status), 1); |
cparata | 1:978cae936ddb | 519 | } |
cparata | 1:978cae936ddb | 520 | return ret; |
cparata | 0:c761bc6186e8 | 521 | } |
cparata | 0:c761bc6186e8 | 522 | |
cparata | 0:c761bc6186e8 | 523 | /** |
cparata | 0:c761bc6186e8 | 524 | * @brief The STATUS_REG register is read by the primary interface.[get] |
cparata | 0:c761bc6186e8 | 525 | * |
cparata | 0:c761bc6186e8 | 526 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 527 | * @param val structure of registers from STATUS to STATUS_REG |
cparata | 0:c761bc6186e8 | 528 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 529 | * |
cparata | 0:c761bc6186e8 | 530 | */ |
cparata | 0:c761bc6186e8 | 531 | int32_t lps22hh_status_reg_get(lps22hh_ctx_t *ctx, lps22hh_status_t *val) |
cparata | 0:c761bc6186e8 | 532 | { |
cparata | 1:978cae936ddb | 533 | int32_t ret; |
cparata | 1:978cae936ddb | 534 | ret = lps22hh_read_reg(ctx, LPS22HH_STATUS, (uint8_t *) val, 1); |
cparata | 1:978cae936ddb | 535 | return ret; |
cparata | 0:c761bc6186e8 | 536 | } |
cparata | 0:c761bc6186e8 | 537 | |
cparata | 0:c761bc6186e8 | 538 | /** |
cparata | 0:c761bc6186e8 | 539 | * @brief Pressure new data available.[get] |
cparata | 0:c761bc6186e8 | 540 | * |
cparata | 0:c761bc6186e8 | 541 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 542 | * @param val change the values of p_da in reg STATUS |
cparata | 0:c761bc6186e8 | 543 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 544 | * |
cparata | 0:c761bc6186e8 | 545 | */ |
cparata | 0:c761bc6186e8 | 546 | int32_t lps22hh_press_flag_data_ready_get(lps22hh_ctx_t *ctx, uint8_t *val) |
cparata | 0:c761bc6186e8 | 547 | { |
cparata | 1:978cae936ddb | 548 | lps22hh_status_t reg; |
cparata | 1:978cae936ddb | 549 | int32_t ret; |
cparata | 0:c761bc6186e8 | 550 | |
cparata | 1:978cae936ddb | 551 | ret = lps22hh_read_reg(ctx, LPS22HH_STATUS, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 552 | *val = reg.p_da; |
cparata | 0:c761bc6186e8 | 553 | |
cparata | 1:978cae936ddb | 554 | return ret; |
cparata | 0:c761bc6186e8 | 555 | } |
cparata | 0:c761bc6186e8 | 556 | |
cparata | 0:c761bc6186e8 | 557 | /** |
cparata | 0:c761bc6186e8 | 558 | * @brief Temperature data available.[get] |
cparata | 0:c761bc6186e8 | 559 | * |
cparata | 0:c761bc6186e8 | 560 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 561 | * @param val change the values of t_da in reg STATUS |
cparata | 0:c761bc6186e8 | 562 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 563 | * |
cparata | 0:c761bc6186e8 | 564 | */ |
cparata | 0:c761bc6186e8 | 565 | int32_t lps22hh_temp_flag_data_ready_get(lps22hh_ctx_t *ctx, uint8_t *val) |
cparata | 0:c761bc6186e8 | 566 | { |
cparata | 1:978cae936ddb | 567 | lps22hh_status_t reg; |
cparata | 1:978cae936ddb | 568 | int32_t ret; |
cparata | 0:c761bc6186e8 | 569 | |
cparata | 1:978cae936ddb | 570 | ret = lps22hh_read_reg(ctx, LPS22HH_STATUS, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 571 | *val = reg.t_da; |
cparata | 0:c761bc6186e8 | 572 | |
cparata | 1:978cae936ddb | 573 | return ret; |
cparata | 0:c761bc6186e8 | 574 | } |
cparata | 0:c761bc6186e8 | 575 | |
cparata | 0:c761bc6186e8 | 576 | /** |
cparata | 0:c761bc6186e8 | 577 | * @} |
cparata | 0:c761bc6186e8 | 578 | * |
cparata | 0:c761bc6186e8 | 579 | */ |
cparata | 0:c761bc6186e8 | 580 | |
cparata | 0:c761bc6186e8 | 581 | /** |
cparata | 0:c761bc6186e8 | 582 | * @defgroup LPS22HH_Data_Output |
cparata | 0:c761bc6186e8 | 583 | * @brief This section groups all the data output functions. |
cparata | 0:c761bc6186e8 | 584 | * @{ |
cparata | 0:c761bc6186e8 | 585 | * |
cparata | 0:c761bc6186e8 | 586 | */ |
cparata | 0:c761bc6186e8 | 587 | |
cparata | 0:c761bc6186e8 | 588 | /** |
cparata | 0:c761bc6186e8 | 589 | * @brief Pressure output value.[get] |
cparata | 0:c761bc6186e8 | 590 | * |
cparata | 0:c761bc6186e8 | 591 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 592 | * @param buff buffer that stores data read |
cparata | 0:c761bc6186e8 | 593 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 594 | * |
cparata | 0:c761bc6186e8 | 595 | */ |
cparata | 0:c761bc6186e8 | 596 | int32_t lps22hh_pressure_raw_get(lps22hh_ctx_t *ctx, uint8_t *buff) |
cparata | 0:c761bc6186e8 | 597 | { |
cparata | 1:978cae936ddb | 598 | int32_t ret; |
cparata | 1:978cae936ddb | 599 | ret = lps22hh_read_reg(ctx, LPS22HH_PRESSURE_OUT_XL, buff, 3); |
cparata | 1:978cae936ddb | 600 | return ret; |
cparata | 0:c761bc6186e8 | 601 | } |
cparata | 0:c761bc6186e8 | 602 | |
cparata | 0:c761bc6186e8 | 603 | /** |
cparata | 0:c761bc6186e8 | 604 | * @brief Temperature output value.[get] |
cparata | 0:c761bc6186e8 | 605 | * |
cparata | 0:c761bc6186e8 | 606 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 607 | * @param buff buffer that stores data read |
cparata | 0:c761bc6186e8 | 608 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 609 | * |
cparata | 0:c761bc6186e8 | 610 | */ |
cparata | 0:c761bc6186e8 | 611 | int32_t lps22hh_temperature_raw_get(lps22hh_ctx_t *ctx, uint8_t *buff) |
cparata | 0:c761bc6186e8 | 612 | { |
cparata | 1:978cae936ddb | 613 | int32_t ret; |
cparata | 1:978cae936ddb | 614 | ret = lps22hh_read_reg(ctx, LPS22HH_TEMP_OUT_L, buff, 2); |
cparata | 1:978cae936ddb | 615 | return ret; |
cparata | 0:c761bc6186e8 | 616 | } |
cparata | 0:c761bc6186e8 | 617 | |
cparata | 0:c761bc6186e8 | 618 | /** |
cparata | 0:c761bc6186e8 | 619 | * @brief Pressure output from FIFO value.[get] |
cparata | 0:c761bc6186e8 | 620 | * |
cparata | 0:c761bc6186e8 | 621 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 622 | * @param buff buffer that stores data read |
cparata | 0:c761bc6186e8 | 623 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 624 | * |
cparata | 0:c761bc6186e8 | 625 | */ |
cparata | 0:c761bc6186e8 | 626 | int32_t lps22hh_fifo_pressure_raw_get(lps22hh_ctx_t *ctx, uint8_t *buff) |
cparata | 0:c761bc6186e8 | 627 | { |
cparata | 1:978cae936ddb | 628 | int32_t ret; |
cparata | 1:978cae936ddb | 629 | ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_DATA_OUT_PRESS_XL, buff, 3); |
cparata | 1:978cae936ddb | 630 | return ret; |
cparata | 0:c761bc6186e8 | 631 | } |
cparata | 0:c761bc6186e8 | 632 | |
cparata | 0:c761bc6186e8 | 633 | /** |
cparata | 0:c761bc6186e8 | 634 | * @brief Temperature output from FIFO value.[get] |
cparata | 0:c761bc6186e8 | 635 | * |
cparata | 0:c761bc6186e8 | 636 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 637 | * @param buff buffer that stores data read |
cparata | 0:c761bc6186e8 | 638 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 639 | * |
cparata | 0:c761bc6186e8 | 640 | */ |
cparata | 0:c761bc6186e8 | 641 | int32_t lps22hh_fifo_temperature_raw_get(lps22hh_ctx_t *ctx, uint8_t *buff) |
cparata | 0:c761bc6186e8 | 642 | { |
cparata | 1:978cae936ddb | 643 | int32_t ret; |
cparata | 1:978cae936ddb | 644 | ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_DATA_OUT_TEMP_L, buff, 2); |
cparata | 1:978cae936ddb | 645 | return ret; |
cparata | 0:c761bc6186e8 | 646 | } |
cparata | 0:c761bc6186e8 | 647 | |
cparata | 0:c761bc6186e8 | 648 | /** |
cparata | 0:c761bc6186e8 | 649 | * @} |
cparata | 0:c761bc6186e8 | 650 | * |
cparata | 0:c761bc6186e8 | 651 | */ |
cparata | 0:c761bc6186e8 | 652 | |
cparata | 0:c761bc6186e8 | 653 | /** |
cparata | 0:c761bc6186e8 | 654 | * @defgroup LPS22HH_Common |
cparata | 0:c761bc6186e8 | 655 | * @brief This section groups common useful functions. |
cparata | 0:c761bc6186e8 | 656 | * @{ |
cparata | 0:c761bc6186e8 | 657 | * |
cparata | 0:c761bc6186e8 | 658 | */ |
cparata | 0:c761bc6186e8 | 659 | |
cparata | 0:c761bc6186e8 | 660 | /** |
cparata | 0:c761bc6186e8 | 661 | * @brief DeviceWhoamI[get] |
cparata | 0:c761bc6186e8 | 662 | * |
cparata | 0:c761bc6186e8 | 663 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 664 | * @param buff buffer that stores data read |
cparata | 0:c761bc6186e8 | 665 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 666 | * |
cparata | 0:c761bc6186e8 | 667 | */ |
cparata | 0:c761bc6186e8 | 668 | int32_t lps22hh_device_id_get(lps22hh_ctx_t *ctx, uint8_t *buff) |
cparata | 0:c761bc6186e8 | 669 | { |
cparata | 1:978cae936ddb | 670 | int32_t ret; |
cparata | 1:978cae936ddb | 671 | ret = lps22hh_read_reg(ctx, LPS22HH_WHO_AM_I, buff, 1); |
cparata | 1:978cae936ddb | 672 | return ret; |
cparata | 0:c761bc6186e8 | 673 | } |
cparata | 0:c761bc6186e8 | 674 | |
cparata | 0:c761bc6186e8 | 675 | /** |
cparata | 0:c761bc6186e8 | 676 | * @brief Software reset. Restore the default values |
cparata | 0:c761bc6186e8 | 677 | * in user registers.[set] |
cparata | 0:c761bc6186e8 | 678 | * |
cparata | 0:c761bc6186e8 | 679 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 680 | * @param val change the values of swreset in reg CTRL_REG2 |
cparata | 0:c761bc6186e8 | 681 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 682 | * |
cparata | 0:c761bc6186e8 | 683 | */ |
cparata | 0:c761bc6186e8 | 684 | int32_t lps22hh_reset_set(lps22hh_ctx_t *ctx, uint8_t val) |
cparata | 0:c761bc6186e8 | 685 | { |
cparata | 1:978cae936ddb | 686 | lps22hh_ctrl_reg2_t reg; |
cparata | 1:978cae936ddb | 687 | int32_t ret; |
cparata | 0:c761bc6186e8 | 688 | |
cparata | 1:978cae936ddb | 689 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 690 | if (ret == 0) { |
cparata | 1:978cae936ddb | 691 | reg.swreset = val; |
cparata | 1:978cae936ddb | 692 | ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 693 | } |
cparata | 1:978cae936ddb | 694 | return ret; |
cparata | 0:c761bc6186e8 | 695 | } |
cparata | 0:c761bc6186e8 | 696 | |
cparata | 0:c761bc6186e8 | 697 | /** |
cparata | 0:c761bc6186e8 | 698 | * @brief Software reset. Restore the default values |
cparata | 0:c761bc6186e8 | 699 | * in user registers.[get] |
cparata | 0:c761bc6186e8 | 700 | * |
cparata | 0:c761bc6186e8 | 701 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 702 | * @param val change the values of swreset in reg CTRL_REG2 |
cparata | 0:c761bc6186e8 | 703 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 704 | * |
cparata | 0:c761bc6186e8 | 705 | */ |
cparata | 0:c761bc6186e8 | 706 | int32_t lps22hh_reset_get(lps22hh_ctx_t *ctx, uint8_t *val) |
cparata | 0:c761bc6186e8 | 707 | { |
cparata | 1:978cae936ddb | 708 | lps22hh_ctrl_reg2_t reg; |
cparata | 1:978cae936ddb | 709 | int32_t ret; |
cparata | 0:c761bc6186e8 | 710 | |
cparata | 1:978cae936ddb | 711 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 712 | *val = reg.swreset; |
cparata | 0:c761bc6186e8 | 713 | |
cparata | 1:978cae936ddb | 714 | return ret; |
cparata | 0:c761bc6186e8 | 715 | } |
cparata | 0:c761bc6186e8 | 716 | |
cparata | 0:c761bc6186e8 | 717 | /** |
cparata | 0:c761bc6186e8 | 718 | * @brief Register address automatically |
cparata | 0:c761bc6186e8 | 719 | * incremented during a multiple byte access |
cparata | 0:c761bc6186e8 | 720 | * with a serial interface.[set] |
cparata | 0:c761bc6186e8 | 721 | * |
cparata | 0:c761bc6186e8 | 722 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 723 | * @param val change the values of if_add_inc in reg CTRL_REG2 |
cparata | 0:c761bc6186e8 | 724 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 725 | * |
cparata | 0:c761bc6186e8 | 726 | */ |
cparata | 0:c761bc6186e8 | 727 | int32_t lps22hh_auto_increment_set(lps22hh_ctx_t *ctx, uint8_t val) |
cparata | 0:c761bc6186e8 | 728 | { |
cparata | 1:978cae936ddb | 729 | lps22hh_ctrl_reg2_t reg; |
cparata | 1:978cae936ddb | 730 | int32_t ret; |
cparata | 0:c761bc6186e8 | 731 | |
cparata | 1:978cae936ddb | 732 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 733 | if (ret == 0) { |
cparata | 1:978cae936ddb | 734 | reg.if_add_inc = val; |
cparata | 1:978cae936ddb | 735 | ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 736 | } |
cparata | 1:978cae936ddb | 737 | return ret; |
cparata | 0:c761bc6186e8 | 738 | } |
cparata | 0:c761bc6186e8 | 739 | |
cparata | 0:c761bc6186e8 | 740 | /** |
cparata | 0:c761bc6186e8 | 741 | * @brief Register address automatically |
cparata | 0:c761bc6186e8 | 742 | * incremented during a multiple byte |
cparata | 0:c761bc6186e8 | 743 | * access with a serial interface.[get] |
cparata | 0:c761bc6186e8 | 744 | * |
cparata | 0:c761bc6186e8 | 745 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 746 | * @param val change the values of if_add_inc in reg CTRL_REG2 |
cparata | 0:c761bc6186e8 | 747 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 748 | * |
cparata | 0:c761bc6186e8 | 749 | */ |
cparata | 0:c761bc6186e8 | 750 | int32_t lps22hh_auto_increment_get(lps22hh_ctx_t *ctx, uint8_t *val) |
cparata | 0:c761bc6186e8 | 751 | { |
cparata | 1:978cae936ddb | 752 | lps22hh_ctrl_reg2_t reg; |
cparata | 1:978cae936ddb | 753 | int32_t ret; |
cparata | 0:c761bc6186e8 | 754 | |
cparata | 1:978cae936ddb | 755 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 756 | *val = reg.if_add_inc; |
cparata | 0:c761bc6186e8 | 757 | |
cparata | 1:978cae936ddb | 758 | return ret; |
cparata | 0:c761bc6186e8 | 759 | } |
cparata | 0:c761bc6186e8 | 760 | |
cparata | 0:c761bc6186e8 | 761 | /** |
cparata | 0:c761bc6186e8 | 762 | * @brief Reboot memory content. Reload the calibration |
cparata | 0:c761bc6186e8 | 763 | * parameters.[set] |
cparata | 0:c761bc6186e8 | 764 | * |
cparata | 0:c761bc6186e8 | 765 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 766 | * @param val change the values of boot in reg CTRL_REG2 |
cparata | 0:c761bc6186e8 | 767 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 768 | * |
cparata | 0:c761bc6186e8 | 769 | */ |
cparata | 0:c761bc6186e8 | 770 | int32_t lps22hh_boot_set(lps22hh_ctx_t *ctx, uint8_t val) |
cparata | 0:c761bc6186e8 | 771 | { |
cparata | 1:978cae936ddb | 772 | lps22hh_ctrl_reg2_t reg; |
cparata | 1:978cae936ddb | 773 | int32_t ret; |
cparata | 0:c761bc6186e8 | 774 | |
cparata | 1:978cae936ddb | 775 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 776 | if (ret == 0) { |
cparata | 1:978cae936ddb | 777 | reg.boot = val; |
cparata | 1:978cae936ddb | 778 | ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 779 | } |
cparata | 1:978cae936ddb | 780 | return ret; |
cparata | 0:c761bc6186e8 | 781 | } |
cparata | 0:c761bc6186e8 | 782 | |
cparata | 0:c761bc6186e8 | 783 | /** |
cparata | 0:c761bc6186e8 | 784 | * @brief Reboot memory content. Reload the calibration |
cparata | 0:c761bc6186e8 | 785 | * parameters.[get] |
cparata | 0:c761bc6186e8 | 786 | * |
cparata | 0:c761bc6186e8 | 787 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 788 | * @param val change the values of boot in reg CTRL_REG2 |
cparata | 0:c761bc6186e8 | 789 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 790 | * |
cparata | 0:c761bc6186e8 | 791 | */ |
cparata | 0:c761bc6186e8 | 792 | int32_t lps22hh_boot_get(lps22hh_ctx_t *ctx, uint8_t *val) |
cparata | 0:c761bc6186e8 | 793 | { |
cparata | 1:978cae936ddb | 794 | lps22hh_ctrl_reg2_t reg; |
cparata | 1:978cae936ddb | 795 | int32_t ret; |
cparata | 0:c761bc6186e8 | 796 | |
cparata | 1:978cae936ddb | 797 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 798 | *val = reg.boot; |
cparata | 0:c761bc6186e8 | 799 | |
cparata | 1:978cae936ddb | 800 | return ret; |
cparata | 0:c761bc6186e8 | 801 | } |
cparata | 0:c761bc6186e8 | 802 | |
cparata | 0:c761bc6186e8 | 803 | /** |
cparata | 0:c761bc6186e8 | 804 | * @} |
cparata | 0:c761bc6186e8 | 805 | * |
cparata | 0:c761bc6186e8 | 806 | */ |
cparata | 0:c761bc6186e8 | 807 | |
cparata | 0:c761bc6186e8 | 808 | /** |
cparata | 0:c761bc6186e8 | 809 | * @defgroup LPS22HH_Filters |
cparata | 0:c761bc6186e8 | 810 | * @brief This section group all the functions concerning the |
cparata | 0:c761bc6186e8 | 811 | * filters configuration. |
cparata | 0:c761bc6186e8 | 812 | * @{ |
cparata | 0:c761bc6186e8 | 813 | * |
cparata | 0:c761bc6186e8 | 814 | */ |
cparata | 0:c761bc6186e8 | 815 | |
cparata | 0:c761bc6186e8 | 816 | /** |
cparata | 0:c761bc6186e8 | 817 | * @brief Low-pass bandwidth selection.[set] |
cparata | 0:c761bc6186e8 | 818 | * |
cparata | 0:c761bc6186e8 | 819 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 820 | * @param val change the values of lpfp_cfg in reg CTRL_REG1 |
cparata | 0:c761bc6186e8 | 821 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 822 | * |
cparata | 0:c761bc6186e8 | 823 | */ |
cparata | 0:c761bc6186e8 | 824 | int32_t lps22hh_lp_bandwidth_set(lps22hh_ctx_t *ctx, lps22hh_lpfp_cfg_t val) |
cparata | 0:c761bc6186e8 | 825 | { |
cparata | 1:978cae936ddb | 826 | lps22hh_ctrl_reg1_t reg; |
cparata | 1:978cae936ddb | 827 | int32_t ret; |
cparata | 0:c761bc6186e8 | 828 | |
cparata | 1:978cae936ddb | 829 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 830 | if (ret == 0) { |
cparata | 1:978cae936ddb | 831 | reg.lpfp_cfg = (uint8_t)val; |
cparata | 1:978cae936ddb | 832 | ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 833 | } |
cparata | 1:978cae936ddb | 834 | return ret; |
cparata | 0:c761bc6186e8 | 835 | } |
cparata | 0:c761bc6186e8 | 836 | |
cparata | 0:c761bc6186e8 | 837 | /** |
cparata | 0:c761bc6186e8 | 838 | * @brief Low-pass bandwidth selection.[get] |
cparata | 0:c761bc6186e8 | 839 | * |
cparata | 0:c761bc6186e8 | 840 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 841 | * @param val Get the values of lpfp_cfg in reg CTRL_REG1 |
cparata | 0:c761bc6186e8 | 842 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 843 | * |
cparata | 0:c761bc6186e8 | 844 | */ |
cparata | 0:c761bc6186e8 | 845 | int32_t lps22hh_lp_bandwidth_get(lps22hh_ctx_t *ctx, lps22hh_lpfp_cfg_t *val) |
cparata | 0:c761bc6186e8 | 846 | { |
cparata | 1:978cae936ddb | 847 | lps22hh_ctrl_reg1_t reg; |
cparata | 1:978cae936ddb | 848 | int32_t ret; |
cparata | 0:c761bc6186e8 | 849 | |
cparata | 1:978cae936ddb | 850 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 851 | switch (reg.lpfp_cfg) { |
cparata | 1:978cae936ddb | 852 | case LPS22HH_LPF_ODR_DIV_2: |
cparata | 1:978cae936ddb | 853 | *val = LPS22HH_LPF_ODR_DIV_2; |
cparata | 1:978cae936ddb | 854 | break; |
cparata | 1:978cae936ddb | 855 | case LPS22HH_LPF_ODR_DIV_9: |
cparata | 1:978cae936ddb | 856 | *val = LPS22HH_LPF_ODR_DIV_9; |
cparata | 1:978cae936ddb | 857 | break; |
cparata | 1:978cae936ddb | 858 | case LPS22HH_LPF_ODR_DIV_20: |
cparata | 1:978cae936ddb | 859 | *val = LPS22HH_LPF_ODR_DIV_20; |
cparata | 1:978cae936ddb | 860 | break; |
cparata | 1:978cae936ddb | 861 | default: |
cparata | 1:978cae936ddb | 862 | *val = LPS22HH_LPF_ODR_DIV_2; |
cparata | 1:978cae936ddb | 863 | break; |
cparata | 0:c761bc6186e8 | 864 | } |
cparata | 0:c761bc6186e8 | 865 | |
cparata | 1:978cae936ddb | 866 | return ret; |
cparata | 0:c761bc6186e8 | 867 | } |
cparata | 0:c761bc6186e8 | 868 | |
cparata | 0:c761bc6186e8 | 869 | /** |
cparata | 0:c761bc6186e8 | 870 | * @} |
cparata | 0:c761bc6186e8 | 871 | * |
cparata | 0:c761bc6186e8 | 872 | */ |
cparata | 0:c761bc6186e8 | 873 | |
cparata | 0:c761bc6186e8 | 874 | /** |
cparata | 0:c761bc6186e8 | 875 | * @defgroup LPS22HH_Serial_Interface |
cparata | 0:c761bc6186e8 | 876 | * @brief This section groups all the functions concerning serial |
cparata | 0:c761bc6186e8 | 877 | * interface management |
cparata | 0:c761bc6186e8 | 878 | * @{ |
cparata | 0:c761bc6186e8 | 879 | * |
cparata | 0:c761bc6186e8 | 880 | */ |
cparata | 0:c761bc6186e8 | 881 | |
cparata | 0:c761bc6186e8 | 882 | /** |
cparata | 0:c761bc6186e8 | 883 | * @brief Enable/Disable I2C interface.[set] |
cparata | 0:c761bc6186e8 | 884 | * |
cparata | 0:c761bc6186e8 | 885 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 886 | * @param val change the values of i2c_disable in reg IF_CTRL |
cparata | 0:c761bc6186e8 | 887 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 888 | * |
cparata | 0:c761bc6186e8 | 889 | */ |
cparata | 0:c761bc6186e8 | 890 | int32_t lps22hh_i2c_interface_set(lps22hh_ctx_t *ctx, |
cparata | 0:c761bc6186e8 | 891 | lps22hh_i2c_disable_t val) |
cparata | 0:c761bc6186e8 | 892 | { |
cparata | 1:978cae936ddb | 893 | lps22hh_if_ctrl_t reg; |
cparata | 1:978cae936ddb | 894 | int32_t ret; |
cparata | 0:c761bc6186e8 | 895 | |
cparata | 1:978cae936ddb | 896 | ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 897 | if (ret == 0) { |
cparata | 1:978cae936ddb | 898 | reg.i2c_disable = (uint8_t)val; |
cparata | 1:978cae936ddb | 899 | ret = lps22hh_write_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 900 | } |
cparata | 1:978cae936ddb | 901 | return ret; |
cparata | 0:c761bc6186e8 | 902 | } |
cparata | 0:c761bc6186e8 | 903 | |
cparata | 0:c761bc6186e8 | 904 | /** |
cparata | 0:c761bc6186e8 | 905 | * @brief Enable/Disable I2C interface.[get] |
cparata | 0:c761bc6186e8 | 906 | * |
cparata | 0:c761bc6186e8 | 907 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 908 | * @param val Get the values of i2c_disable in reg IF_CTRL |
cparata | 0:c761bc6186e8 | 909 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 910 | * |
cparata | 0:c761bc6186e8 | 911 | */ |
cparata | 0:c761bc6186e8 | 912 | int32_t lps22hh_i2c_interface_get(lps22hh_ctx_t *ctx, |
cparata | 0:c761bc6186e8 | 913 | lps22hh_i2c_disable_t *val) |
cparata | 0:c761bc6186e8 | 914 | { |
cparata | 1:978cae936ddb | 915 | lps22hh_if_ctrl_t reg; |
cparata | 1:978cae936ddb | 916 | int32_t ret; |
cparata | 0:c761bc6186e8 | 917 | |
cparata | 1:978cae936ddb | 918 | ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 919 | switch (reg.i2c_disable) { |
cparata | 1:978cae936ddb | 920 | case LPS22HH_I2C_ENABLE: |
cparata | 1:978cae936ddb | 921 | *val = LPS22HH_I2C_ENABLE; |
cparata | 1:978cae936ddb | 922 | break; |
cparata | 1:978cae936ddb | 923 | case LPS22HH_I2C_DISABLE: |
cparata | 1:978cae936ddb | 924 | *val = LPS22HH_I2C_DISABLE; |
cparata | 1:978cae936ddb | 925 | break; |
cparata | 1:978cae936ddb | 926 | default: |
cparata | 1:978cae936ddb | 927 | *val = LPS22HH_I2C_ENABLE; |
cparata | 1:978cae936ddb | 928 | break; |
cparata | 0:c761bc6186e8 | 929 | } |
cparata | 0:c761bc6186e8 | 930 | |
cparata | 1:978cae936ddb | 931 | return ret; |
cparata | 0:c761bc6186e8 | 932 | } |
cparata | 0:c761bc6186e8 | 933 | |
cparata | 0:c761bc6186e8 | 934 | /** |
cparata | 0:c761bc6186e8 | 935 | * @brief I3C Enable/Disable communication protocol.[set] |
cparata | 0:c761bc6186e8 | 936 | * |
cparata | 0:c761bc6186e8 | 937 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 938 | * @param val change the values of int_en_i3c in reg IF_CTRL |
cparata | 0:c761bc6186e8 | 939 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 940 | * |
cparata | 0:c761bc6186e8 | 941 | */ |
cparata | 0:c761bc6186e8 | 942 | int32_t lps22hh_i3c_interface_set(lps22hh_ctx_t *ctx, |
cparata | 0:c761bc6186e8 | 943 | lps22hh_i3c_disable_t val) |
cparata | 0:c761bc6186e8 | 944 | { |
cparata | 1:978cae936ddb | 945 | lps22hh_if_ctrl_t reg; |
cparata | 1:978cae936ddb | 946 | int32_t ret; |
cparata | 0:c761bc6186e8 | 947 | |
cparata | 1:978cae936ddb | 948 | ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 949 | if (ret == 0) { |
cparata | 1:978cae936ddb | 950 | reg.i3c_disable = ((uint8_t)val & 0x01u); |
cparata | 1:978cae936ddb | 951 | reg.int_en_i3c = ((uint8_t)val & 0x10U) >> 4; |
cparata | 1:978cae936ddb | 952 | ret = lps22hh_write_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 953 | } |
cparata | 1:978cae936ddb | 954 | return ret; |
cparata | 0:c761bc6186e8 | 955 | } |
cparata | 0:c761bc6186e8 | 956 | |
cparata | 0:c761bc6186e8 | 957 | /** |
cparata | 0:c761bc6186e8 | 958 | * @brief I3C Enable/Disable communication protocol.[get] |
cparata | 0:c761bc6186e8 | 959 | * |
cparata | 0:c761bc6186e8 | 960 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 961 | * @param val change the values of int_en_i3c in reg IF_CTRL |
cparata | 0:c761bc6186e8 | 962 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 963 | * |
cparata | 0:c761bc6186e8 | 964 | */ |
cparata | 0:c761bc6186e8 | 965 | int32_t lps22hh_i3c_interface_get(lps22hh_ctx_t *ctx, |
cparata | 0:c761bc6186e8 | 966 | lps22hh_i3c_disable_t *val) |
cparata | 0:c761bc6186e8 | 967 | { |
cparata | 1:978cae936ddb | 968 | lps22hh_if_ctrl_t reg; |
cparata | 1:978cae936ddb | 969 | int32_t ret; |
cparata | 0:c761bc6186e8 | 970 | |
cparata | 1:978cae936ddb | 971 | ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1); |
cparata | 0:c761bc6186e8 | 972 | |
cparata | 1:978cae936ddb | 973 | switch ((reg.int_en_i3c << 4) + reg.int_en_i3c) { |
cparata | 1:978cae936ddb | 974 | case LPS22HH_I3C_ENABLE: |
cparata | 1:978cae936ddb | 975 | *val = LPS22HH_I3C_ENABLE; |
cparata | 1:978cae936ddb | 976 | break; |
cparata | 1:978cae936ddb | 977 | case LPS22HH_I3C_ENABLE_INT_PIN_ENABLE: |
cparata | 1:978cae936ddb | 978 | *val = LPS22HH_I3C_ENABLE_INT_PIN_ENABLE; |
cparata | 1:978cae936ddb | 979 | break; |
cparata | 1:978cae936ddb | 980 | case LPS22HH_I3C_DISABLE: |
cparata | 1:978cae936ddb | 981 | *val = LPS22HH_I3C_DISABLE; |
cparata | 1:978cae936ddb | 982 | break; |
cparata | 1:978cae936ddb | 983 | default: |
cparata | 1:978cae936ddb | 984 | *val = LPS22HH_I3C_ENABLE; |
cparata | 1:978cae936ddb | 985 | break; |
cparata | 1:978cae936ddb | 986 | } |
cparata | 1:978cae936ddb | 987 | return ret; |
cparata | 0:c761bc6186e8 | 988 | } |
cparata | 0:c761bc6186e8 | 989 | |
cparata | 0:c761bc6186e8 | 990 | /** |
cparata | 0:c761bc6186e8 | 991 | * @brief Enable/Disable pull-up on SDO pin.[set] |
cparata | 0:c761bc6186e8 | 992 | * |
cparata | 0:c761bc6186e8 | 993 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 994 | * @param val change the values of sdo_pu_en in reg IF_CTRL |
cparata | 0:c761bc6186e8 | 995 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 996 | * |
cparata | 0:c761bc6186e8 | 997 | */ |
cparata | 0:c761bc6186e8 | 998 | int32_t lps22hh_sdo_sa0_mode_set(lps22hh_ctx_t *ctx, lps22hh_pu_en_t val) |
cparata | 0:c761bc6186e8 | 999 | { |
cparata | 1:978cae936ddb | 1000 | lps22hh_if_ctrl_t reg; |
cparata | 1:978cae936ddb | 1001 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1002 | |
cparata | 1:978cae936ddb | 1003 | ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1004 | if (ret == 0) { |
cparata | 1:978cae936ddb | 1005 | reg.sdo_pu_en = (uint8_t)val; |
cparata | 1:978cae936ddb | 1006 | ret = lps22hh_write_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1007 | } |
cparata | 1:978cae936ddb | 1008 | return ret; |
cparata | 0:c761bc6186e8 | 1009 | } |
cparata | 0:c761bc6186e8 | 1010 | |
cparata | 0:c761bc6186e8 | 1011 | /** |
cparata | 0:c761bc6186e8 | 1012 | * @brief Enable/Disable pull-up on SDO pin.[get] |
cparata | 0:c761bc6186e8 | 1013 | * |
cparata | 0:c761bc6186e8 | 1014 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1015 | * @param val Get the values of sdo_pu_en in reg IF_CTRL |
cparata | 0:c761bc6186e8 | 1016 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1017 | * |
cparata | 0:c761bc6186e8 | 1018 | */ |
cparata | 0:c761bc6186e8 | 1019 | int32_t lps22hh_sdo_sa0_mode_get(lps22hh_ctx_t *ctx, lps22hh_pu_en_t *val) |
cparata | 0:c761bc6186e8 | 1020 | { |
cparata | 1:978cae936ddb | 1021 | lps22hh_if_ctrl_t reg; |
cparata | 1:978cae936ddb | 1022 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1023 | |
cparata | 1:978cae936ddb | 1024 | ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1025 | switch (reg.sdo_pu_en) { |
cparata | 1:978cae936ddb | 1026 | case LPS22HH_PULL_UP_DISCONNECT: |
cparata | 1:978cae936ddb | 1027 | *val = LPS22HH_PULL_UP_DISCONNECT; |
cparata | 1:978cae936ddb | 1028 | break; |
cparata | 1:978cae936ddb | 1029 | case LPS22HH_PULL_UP_CONNECT: |
cparata | 1:978cae936ddb | 1030 | *val = LPS22HH_PULL_UP_CONNECT; |
cparata | 1:978cae936ddb | 1031 | break; |
cparata | 1:978cae936ddb | 1032 | default: |
cparata | 1:978cae936ddb | 1033 | *val = LPS22HH_PULL_UP_DISCONNECT; |
cparata | 1:978cae936ddb | 1034 | break; |
cparata | 1:978cae936ddb | 1035 | } |
cparata | 0:c761bc6186e8 | 1036 | |
cparata | 1:978cae936ddb | 1037 | return ret; |
cparata | 0:c761bc6186e8 | 1038 | } |
cparata | 0:c761bc6186e8 | 1039 | |
cparata | 0:c761bc6186e8 | 1040 | /** |
cparata | 0:c761bc6186e8 | 1041 | * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set] |
cparata | 0:c761bc6186e8 | 1042 | * |
cparata | 0:c761bc6186e8 | 1043 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1044 | * @param val change the values of sda_pu_en in reg IF_CTRL |
cparata | 0:c761bc6186e8 | 1045 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1046 | * |
cparata | 0:c761bc6186e8 | 1047 | */ |
cparata | 0:c761bc6186e8 | 1048 | int32_t lps22hh_sda_mode_set(lps22hh_ctx_t *ctx, lps22hh_pu_en_t val) |
cparata | 0:c761bc6186e8 | 1049 | { |
cparata | 1:978cae936ddb | 1050 | lps22hh_if_ctrl_t reg; |
cparata | 1:978cae936ddb | 1051 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1052 | |
cparata | 1:978cae936ddb | 1053 | ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1054 | if (ret == 0) { |
cparata | 1:978cae936ddb | 1055 | reg.sda_pu_en = (uint8_t)val; |
cparata | 1:978cae936ddb | 1056 | ret = lps22hh_write_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1057 | } |
cparata | 1:978cae936ddb | 1058 | return ret; |
cparata | 0:c761bc6186e8 | 1059 | } |
cparata | 0:c761bc6186e8 | 1060 | |
cparata | 0:c761bc6186e8 | 1061 | /** |
cparata | 0:c761bc6186e8 | 1062 | * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get] |
cparata | 0:c761bc6186e8 | 1063 | * |
cparata | 0:c761bc6186e8 | 1064 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1065 | * @param val Get the values of sda_pu_en in reg IF_CTRL |
cparata | 0:c761bc6186e8 | 1066 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1067 | * |
cparata | 0:c761bc6186e8 | 1068 | */ |
cparata | 0:c761bc6186e8 | 1069 | int32_t lps22hh_sda_mode_get(lps22hh_ctx_t *ctx, lps22hh_pu_en_t *val) |
cparata | 0:c761bc6186e8 | 1070 | { |
cparata | 1:978cae936ddb | 1071 | lps22hh_if_ctrl_t reg; |
cparata | 1:978cae936ddb | 1072 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1073 | |
cparata | 1:978cae936ddb | 1074 | ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1075 | switch (reg.sda_pu_en) { |
cparata | 1:978cae936ddb | 1076 | case LPS22HH_PULL_UP_DISCONNECT: |
cparata | 1:978cae936ddb | 1077 | *val = LPS22HH_PULL_UP_DISCONNECT; |
cparata | 1:978cae936ddb | 1078 | break; |
cparata | 1:978cae936ddb | 1079 | case LPS22HH_PULL_UP_CONNECT: |
cparata | 1:978cae936ddb | 1080 | *val = LPS22HH_PULL_UP_CONNECT; |
cparata | 1:978cae936ddb | 1081 | break; |
cparata | 1:978cae936ddb | 1082 | default: |
cparata | 1:978cae936ddb | 1083 | *val = LPS22HH_PULL_UP_DISCONNECT; |
cparata | 1:978cae936ddb | 1084 | break; |
cparata | 1:978cae936ddb | 1085 | } |
cparata | 1:978cae936ddb | 1086 | return ret; |
cparata | 0:c761bc6186e8 | 1087 | } |
cparata | 0:c761bc6186e8 | 1088 | |
cparata | 0:c761bc6186e8 | 1089 | /** |
cparata | 0:c761bc6186e8 | 1090 | * @brief SPI Serial Interface Mode selection.[set] |
cparata | 0:c761bc6186e8 | 1091 | * |
cparata | 0:c761bc6186e8 | 1092 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1093 | * @param val change the values of sim in reg CTRL_REG1 |
cparata | 0:c761bc6186e8 | 1094 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1095 | * |
cparata | 0:c761bc6186e8 | 1096 | */ |
cparata | 0:c761bc6186e8 | 1097 | int32_t lps22hh_spi_mode_set(lps22hh_ctx_t *ctx, lps22hh_sim_t val) |
cparata | 0:c761bc6186e8 | 1098 | { |
cparata | 1:978cae936ddb | 1099 | lps22hh_ctrl_reg1_t reg; |
cparata | 1:978cae936ddb | 1100 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1101 | |
cparata | 1:978cae936ddb | 1102 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1103 | if (ret == 0) { |
cparata | 1:978cae936ddb | 1104 | reg.sim = (uint8_t)val; |
cparata | 1:978cae936ddb | 1105 | ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1106 | } |
cparata | 1:978cae936ddb | 1107 | return ret; |
cparata | 0:c761bc6186e8 | 1108 | } |
cparata | 0:c761bc6186e8 | 1109 | |
cparata | 0:c761bc6186e8 | 1110 | /** |
cparata | 0:c761bc6186e8 | 1111 | * @brief SPI Serial Interface Mode selection.[get] |
cparata | 0:c761bc6186e8 | 1112 | * |
cparata | 0:c761bc6186e8 | 1113 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1114 | * @param val Get the values of sim in reg CTRL_REG1 |
cparata | 0:c761bc6186e8 | 1115 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1116 | * |
cparata | 0:c761bc6186e8 | 1117 | */ |
cparata | 0:c761bc6186e8 | 1118 | int32_t lps22hh_spi_mode_get(lps22hh_ctx_t *ctx, lps22hh_sim_t *val) |
cparata | 0:c761bc6186e8 | 1119 | { |
cparata | 1:978cae936ddb | 1120 | lps22hh_ctrl_reg1_t reg; |
cparata | 1:978cae936ddb | 1121 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1122 | |
cparata | 1:978cae936ddb | 1123 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1124 | switch (reg.sim) { |
cparata | 1:978cae936ddb | 1125 | case LPS22HH_SPI_4_WIRE: |
cparata | 1:978cae936ddb | 1126 | *val = LPS22HH_SPI_4_WIRE; |
cparata | 1:978cae936ddb | 1127 | break; |
cparata | 1:978cae936ddb | 1128 | case LPS22HH_SPI_3_WIRE: |
cparata | 1:978cae936ddb | 1129 | *val = LPS22HH_SPI_3_WIRE; |
cparata | 1:978cae936ddb | 1130 | break; |
cparata | 1:978cae936ddb | 1131 | default: |
cparata | 1:978cae936ddb | 1132 | *val = LPS22HH_SPI_4_WIRE; |
cparata | 1:978cae936ddb | 1133 | break; |
cparata | 1:978cae936ddb | 1134 | } |
cparata | 1:978cae936ddb | 1135 | return ret; |
cparata | 0:c761bc6186e8 | 1136 | } |
cparata | 0:c761bc6186e8 | 1137 | |
cparata | 0:c761bc6186e8 | 1138 | /** |
cparata | 0:c761bc6186e8 | 1139 | * @} |
cparata | 0:c761bc6186e8 | 1140 | * |
cparata | 0:c761bc6186e8 | 1141 | */ |
cparata | 0:c761bc6186e8 | 1142 | |
cparata | 0:c761bc6186e8 | 1143 | /** |
cparata | 0:c761bc6186e8 | 1144 | * @defgroup LPS22HH_Interrupt_Pins |
cparata | 0:c761bc6186e8 | 1145 | * @brief This section groups all the functions that manage |
cparata | 0:c761bc6186e8 | 1146 | * interrupt pins. |
cparata | 0:c761bc6186e8 | 1147 | * @{ |
cparata | 0:c761bc6186e8 | 1148 | * |
cparata | 0:c761bc6186e8 | 1149 | */ |
cparata | 0:c761bc6186e8 | 1150 | |
cparata | 0:c761bc6186e8 | 1151 | /** |
cparata | 0:c761bc6186e8 | 1152 | * @brief Latch interrupt request to the INT_SOURCE (24h) register.[set] |
cparata | 0:c761bc6186e8 | 1153 | * |
cparata | 0:c761bc6186e8 | 1154 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1155 | * @param val change the values of lir in reg INTERRUPT_CFG |
cparata | 0:c761bc6186e8 | 1156 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1157 | * |
cparata | 0:c761bc6186e8 | 1158 | */ |
cparata | 0:c761bc6186e8 | 1159 | int32_t lps22hh_int_notification_set(lps22hh_ctx_t *ctx, lps22hh_lir_t val) |
cparata | 0:c761bc6186e8 | 1160 | { |
cparata | 1:978cae936ddb | 1161 | lps22hh_interrupt_cfg_t reg; |
cparata | 1:978cae936ddb | 1162 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1163 | |
cparata | 1:978cae936ddb | 1164 | ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1165 | if (ret == 0) { |
cparata | 1:978cae936ddb | 1166 | reg.lir = (uint8_t)val; |
cparata | 1:978cae936ddb | 1167 | ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1168 | } |
cparata | 1:978cae936ddb | 1169 | return ret; |
cparata | 0:c761bc6186e8 | 1170 | } |
cparata | 0:c761bc6186e8 | 1171 | |
cparata | 0:c761bc6186e8 | 1172 | /** |
cparata | 0:c761bc6186e8 | 1173 | * @brief Latch interrupt request to the INT_SOURCE (24h) register.[get] |
cparata | 0:c761bc6186e8 | 1174 | * |
cparata | 0:c761bc6186e8 | 1175 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1176 | * @param val Get the values of lir in reg INTERRUPT_CFG |
cparata | 0:c761bc6186e8 | 1177 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1178 | * |
cparata | 0:c761bc6186e8 | 1179 | */ |
cparata | 0:c761bc6186e8 | 1180 | int32_t lps22hh_int_notification_get(lps22hh_ctx_t *ctx, lps22hh_lir_t *val) |
cparata | 0:c761bc6186e8 | 1181 | { |
cparata | 1:978cae936ddb | 1182 | lps22hh_interrupt_cfg_t reg; |
cparata | 1:978cae936ddb | 1183 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1184 | |
cparata | 1:978cae936ddb | 1185 | ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); |
cparata | 0:c761bc6186e8 | 1186 | |
cparata | 1:978cae936ddb | 1187 | switch (reg.lir) { |
cparata | 1:978cae936ddb | 1188 | case LPS22HH_INT_PULSED: |
cparata | 1:978cae936ddb | 1189 | *val = LPS22HH_INT_PULSED; |
cparata | 1:978cae936ddb | 1190 | break; |
cparata | 1:978cae936ddb | 1191 | case LPS22HH_INT_LATCHED: |
cparata | 1:978cae936ddb | 1192 | *val = LPS22HH_INT_LATCHED; |
cparata | 1:978cae936ddb | 1193 | break; |
cparata | 1:978cae936ddb | 1194 | default: |
cparata | 1:978cae936ddb | 1195 | *val = LPS22HH_INT_PULSED; |
cparata | 1:978cae936ddb | 1196 | break; |
cparata | 1:978cae936ddb | 1197 | } |
cparata | 1:978cae936ddb | 1198 | return ret; |
cparata | 0:c761bc6186e8 | 1199 | } |
cparata | 0:c761bc6186e8 | 1200 | |
cparata | 0:c761bc6186e8 | 1201 | /** |
cparata | 0:c761bc6186e8 | 1202 | * @brief Push-pull/open drain selection on interrupt pads.[set] |
cparata | 0:c761bc6186e8 | 1203 | * |
cparata | 0:c761bc6186e8 | 1204 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1205 | * @param val change the values of pp_od in reg CTRL_REG2 |
cparata | 0:c761bc6186e8 | 1206 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1207 | * |
cparata | 0:c761bc6186e8 | 1208 | */ |
cparata | 0:c761bc6186e8 | 1209 | int32_t lps22hh_pin_mode_set(lps22hh_ctx_t *ctx, lps22hh_pp_od_t val) |
cparata | 0:c761bc6186e8 | 1210 | { |
cparata | 1:978cae936ddb | 1211 | lps22hh_ctrl_reg2_t reg; |
cparata | 1:978cae936ddb | 1212 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1213 | |
cparata | 1:978cae936ddb | 1214 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1215 | if (ret == 0) { |
cparata | 1:978cae936ddb | 1216 | reg.pp_od = (uint8_t)val; |
cparata | 1:978cae936ddb | 1217 | ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1218 | } |
cparata | 0:c761bc6186e8 | 1219 | |
cparata | 1:978cae936ddb | 1220 | return ret; |
cparata | 0:c761bc6186e8 | 1221 | } |
cparata | 0:c761bc6186e8 | 1222 | |
cparata | 0:c761bc6186e8 | 1223 | /** |
cparata | 0:c761bc6186e8 | 1224 | * @brief Push-pull/open drain selection on interrupt pads.[get] |
cparata | 0:c761bc6186e8 | 1225 | * |
cparata | 0:c761bc6186e8 | 1226 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1227 | * @param val Get the values of pp_od in reg CTRL_REG2 |
cparata | 0:c761bc6186e8 | 1228 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1229 | * |
cparata | 0:c761bc6186e8 | 1230 | */ |
cparata | 0:c761bc6186e8 | 1231 | int32_t lps22hh_pin_mode_get(lps22hh_ctx_t *ctx, lps22hh_pp_od_t *val) |
cparata | 0:c761bc6186e8 | 1232 | { |
cparata | 1:978cae936ddb | 1233 | lps22hh_ctrl_reg2_t reg; |
cparata | 1:978cae936ddb | 1234 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1235 | |
cparata | 1:978cae936ddb | 1236 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1); |
cparata | 0:c761bc6186e8 | 1237 | |
cparata | 0:c761bc6186e8 | 1238 | |
cparata | 1:978cae936ddb | 1239 | switch (reg.pp_od) { |
cparata | 1:978cae936ddb | 1240 | case LPS22HH_PUSH_PULL: |
cparata | 1:978cae936ddb | 1241 | *val = LPS22HH_PUSH_PULL; |
cparata | 1:978cae936ddb | 1242 | break; |
cparata | 1:978cae936ddb | 1243 | case LPS22HH_OPEN_DRAIN: |
cparata | 1:978cae936ddb | 1244 | *val = LPS22HH_OPEN_DRAIN; |
cparata | 1:978cae936ddb | 1245 | break; |
cparata | 1:978cae936ddb | 1246 | default: |
cparata | 1:978cae936ddb | 1247 | *val = LPS22HH_PUSH_PULL; |
cparata | 1:978cae936ddb | 1248 | break; |
cparata | 1:978cae936ddb | 1249 | } |
cparata | 0:c761bc6186e8 | 1250 | |
cparata | 1:978cae936ddb | 1251 | return ret; |
cparata | 0:c761bc6186e8 | 1252 | } |
cparata | 0:c761bc6186e8 | 1253 | |
cparata | 0:c761bc6186e8 | 1254 | /** |
cparata | 0:c761bc6186e8 | 1255 | * @brief Interrupt active-high/low.[set] |
cparata | 0:c761bc6186e8 | 1256 | * |
cparata | 0:c761bc6186e8 | 1257 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1258 | * @param val change the values of int_h_l in reg CTRL_REG2 |
cparata | 0:c761bc6186e8 | 1259 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1260 | * |
cparata | 0:c761bc6186e8 | 1261 | */ |
cparata | 0:c761bc6186e8 | 1262 | int32_t lps22hh_pin_polarity_set(lps22hh_ctx_t *ctx, lps22hh_int_h_l_t val) |
cparata | 0:c761bc6186e8 | 1263 | { |
cparata | 1:978cae936ddb | 1264 | lps22hh_ctrl_reg2_t reg; |
cparata | 1:978cae936ddb | 1265 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1266 | |
cparata | 1:978cae936ddb | 1267 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1268 | if (ret == 0) { |
cparata | 1:978cae936ddb | 1269 | reg.int_h_l = (uint8_t)val; |
cparata | 1:978cae936ddb | 1270 | ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1271 | } |
cparata | 0:c761bc6186e8 | 1272 | |
cparata | 1:978cae936ddb | 1273 | return ret; |
cparata | 0:c761bc6186e8 | 1274 | } |
cparata | 0:c761bc6186e8 | 1275 | |
cparata | 0:c761bc6186e8 | 1276 | /** |
cparata | 0:c761bc6186e8 | 1277 | * @brief Interrupt active-high/low.[get] |
cparata | 0:c761bc6186e8 | 1278 | * |
cparata | 0:c761bc6186e8 | 1279 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1280 | * @param val Get the values of int_h_l in reg CTRL_REG2 |
cparata | 0:c761bc6186e8 | 1281 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1282 | * |
cparata | 0:c761bc6186e8 | 1283 | */ |
cparata | 0:c761bc6186e8 | 1284 | int32_t lps22hh_pin_polarity_get(lps22hh_ctx_t *ctx, lps22hh_int_h_l_t *val) |
cparata | 0:c761bc6186e8 | 1285 | { |
cparata | 1:978cae936ddb | 1286 | lps22hh_ctrl_reg2_t reg; |
cparata | 1:978cae936ddb | 1287 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1288 | |
cparata | 1:978cae936ddb | 1289 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1); |
cparata | 0:c761bc6186e8 | 1290 | |
cparata | 1:978cae936ddb | 1291 | switch (reg.int_h_l) { |
cparata | 1:978cae936ddb | 1292 | case LPS22HH_ACTIVE_HIGH: |
cparata | 1:978cae936ddb | 1293 | *val = LPS22HH_ACTIVE_HIGH; |
cparata | 1:978cae936ddb | 1294 | break; |
cparata | 1:978cae936ddb | 1295 | case LPS22HH_ACTIVE_LOW: |
cparata | 1:978cae936ddb | 1296 | *val = LPS22HH_ACTIVE_LOW; |
cparata | 1:978cae936ddb | 1297 | break; |
cparata | 1:978cae936ddb | 1298 | default: |
cparata | 1:978cae936ddb | 1299 | *val = LPS22HH_ACTIVE_HIGH; |
cparata | 1:978cae936ddb | 1300 | break; |
cparata | 1:978cae936ddb | 1301 | } |
cparata | 0:c761bc6186e8 | 1302 | |
cparata | 1:978cae936ddb | 1303 | return ret; |
cparata | 0:c761bc6186e8 | 1304 | } |
cparata | 0:c761bc6186e8 | 1305 | |
cparata | 0:c761bc6186e8 | 1306 | /** |
cparata | 0:c761bc6186e8 | 1307 | * @brief Select the signal that need to route on int pad.[set] |
cparata | 0:c761bc6186e8 | 1308 | * |
cparata | 0:c761bc6186e8 | 1309 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1310 | * @param val registers CTRL_REG3 |
cparata | 0:c761bc6186e8 | 1311 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1312 | * |
cparata | 0:c761bc6186e8 | 1313 | */ |
cparata | 0:c761bc6186e8 | 1314 | int32_t lps22hh_pin_int_route_set(lps22hh_ctx_t *ctx, |
cparata | 0:c761bc6186e8 | 1315 | lps22hh_ctrl_reg3_t *val) |
cparata | 0:c761bc6186e8 | 1316 | { |
cparata | 1:978cae936ddb | 1317 | int32_t ret; |
cparata | 1:978cae936ddb | 1318 | ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *) val, 1); |
cparata | 1:978cae936ddb | 1319 | return ret; |
cparata | 0:c761bc6186e8 | 1320 | } |
cparata | 0:c761bc6186e8 | 1321 | |
cparata | 0:c761bc6186e8 | 1322 | /** |
cparata | 0:c761bc6186e8 | 1323 | * @brief Select the signal that need to route on int pad.[get] |
cparata | 0:c761bc6186e8 | 1324 | * |
cparata | 0:c761bc6186e8 | 1325 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1326 | * @param val registers CTRL_REG3 |
cparata | 0:c761bc6186e8 | 1327 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1328 | * |
cparata | 0:c761bc6186e8 | 1329 | */ |
cparata | 0:c761bc6186e8 | 1330 | int32_t lps22hh_pin_int_route_get(lps22hh_ctx_t *ctx, |
cparata | 0:c761bc6186e8 | 1331 | lps22hh_ctrl_reg3_t *val) |
cparata | 0:c761bc6186e8 | 1332 | { |
cparata | 1:978cae936ddb | 1333 | int32_t ret; |
cparata | 1:978cae936ddb | 1334 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *) val, 1); |
cparata | 1:978cae936ddb | 1335 | return ret; |
cparata | 0:c761bc6186e8 | 1336 | } |
cparata | 0:c761bc6186e8 | 1337 | |
cparata | 0:c761bc6186e8 | 1338 | /** |
cparata | 0:c761bc6186e8 | 1339 | * @} |
cparata | 0:c761bc6186e8 | 1340 | * |
cparata | 0:c761bc6186e8 | 1341 | */ |
cparata | 0:c761bc6186e8 | 1342 | |
cparata | 0:c761bc6186e8 | 1343 | /** |
cparata | 0:c761bc6186e8 | 1344 | * @defgroup LPS22HH_Interrupt_on_Threshold |
cparata | 0:c761bc6186e8 | 1345 | * @brief This section groups all the functions that manage the |
cparata | 0:c761bc6186e8 | 1346 | * interrupt on threshold event generation. |
cparata | 0:c761bc6186e8 | 1347 | * @{ |
cparata | 0:c761bc6186e8 | 1348 | * |
cparata | 0:c761bc6186e8 | 1349 | */ |
cparata | 0:c761bc6186e8 | 1350 | |
cparata | 0:c761bc6186e8 | 1351 | /** |
cparata | 0:c761bc6186e8 | 1352 | * @brief Enable interrupt generation on pressure low/high event.[set] |
cparata | 0:c761bc6186e8 | 1353 | * |
cparata | 0:c761bc6186e8 | 1354 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1355 | * @param val change the values of pe in reg INTERRUPT_CFG |
cparata | 0:c761bc6186e8 | 1356 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1357 | * |
cparata | 0:c761bc6186e8 | 1358 | */ |
cparata | 0:c761bc6186e8 | 1359 | int32_t lps22hh_int_on_threshold_set(lps22hh_ctx_t *ctx, lps22hh_pe_t val) |
cparata | 0:c761bc6186e8 | 1360 | { |
cparata | 1:978cae936ddb | 1361 | lps22hh_interrupt_cfg_t reg; |
cparata | 1:978cae936ddb | 1362 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1363 | |
cparata | 1:978cae936ddb | 1364 | ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1365 | if (ret == 0) { |
cparata | 1:978cae936ddb | 1366 | reg.pe = (uint8_t)val; |
cparata | 0:c761bc6186e8 | 1367 | |
cparata | 1:978cae936ddb | 1368 | if (val == LPS22HH_NO_THRESHOLD) { |
cparata | 1:978cae936ddb | 1369 | reg.diff_en = PROPERTY_DISABLE; |
cparata | 1:978cae936ddb | 1370 | } else { |
cparata | 1:978cae936ddb | 1371 | reg.diff_en = PROPERTY_ENABLE; |
cparata | 1:978cae936ddb | 1372 | } |
cparata | 1:978cae936ddb | 1373 | ret = lps22hh_write_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); |
cparata | 0:c761bc6186e8 | 1374 | } |
cparata | 1:978cae936ddb | 1375 | return ret; |
cparata | 0:c761bc6186e8 | 1376 | } |
cparata | 0:c761bc6186e8 | 1377 | |
cparata | 0:c761bc6186e8 | 1378 | /** |
cparata | 0:c761bc6186e8 | 1379 | * @brief Enable interrupt generation on pressure low/high event.[get] |
cparata | 0:c761bc6186e8 | 1380 | * |
cparata | 0:c761bc6186e8 | 1381 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1382 | * @param val Get the values of pe in reg INTERRUPT_CFG |
cparata | 0:c761bc6186e8 | 1383 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1384 | * |
cparata | 0:c761bc6186e8 | 1385 | */ |
cparata | 0:c761bc6186e8 | 1386 | int32_t lps22hh_int_on_threshold_get(lps22hh_ctx_t *ctx, lps22hh_pe_t *val) |
cparata | 0:c761bc6186e8 | 1387 | { |
cparata | 1:978cae936ddb | 1388 | lps22hh_interrupt_cfg_t reg; |
cparata | 1:978cae936ddb | 1389 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1390 | |
cparata | 1:978cae936ddb | 1391 | ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); |
cparata | 0:c761bc6186e8 | 1392 | |
cparata | 1:978cae936ddb | 1393 | switch (reg.pe) { |
cparata | 1:978cae936ddb | 1394 | case LPS22HH_NO_THRESHOLD: |
cparata | 1:978cae936ddb | 1395 | *val = LPS22HH_NO_THRESHOLD; |
cparata | 1:978cae936ddb | 1396 | break; |
cparata | 1:978cae936ddb | 1397 | case LPS22HH_POSITIVE: |
cparata | 1:978cae936ddb | 1398 | *val = LPS22HH_POSITIVE; |
cparata | 1:978cae936ddb | 1399 | break; |
cparata | 1:978cae936ddb | 1400 | case LPS22HH_NEGATIVE: |
cparata | 1:978cae936ddb | 1401 | *val = LPS22HH_NEGATIVE; |
cparata | 1:978cae936ddb | 1402 | break; |
cparata | 1:978cae936ddb | 1403 | case LPS22HH_BOTH: |
cparata | 1:978cae936ddb | 1404 | *val = LPS22HH_BOTH; |
cparata | 1:978cae936ddb | 1405 | break; |
cparata | 1:978cae936ddb | 1406 | default: |
cparata | 1:978cae936ddb | 1407 | *val = LPS22HH_NO_THRESHOLD; |
cparata | 1:978cae936ddb | 1408 | break; |
cparata | 1:978cae936ddb | 1409 | } |
cparata | 0:c761bc6186e8 | 1410 | |
cparata | 1:978cae936ddb | 1411 | return ret; |
cparata | 0:c761bc6186e8 | 1412 | } |
cparata | 0:c761bc6186e8 | 1413 | |
cparata | 0:c761bc6186e8 | 1414 | /** |
cparata | 0:c761bc6186e8 | 1415 | * @brief User-defined threshold value for pressure interrupt event.[set] |
cparata | 0:c761bc6186e8 | 1416 | * |
cparata | 0:c761bc6186e8 | 1417 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1418 | * @param buff buffer that contains data to write |
cparata | 0:c761bc6186e8 | 1419 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1420 | * |
cparata | 0:c761bc6186e8 | 1421 | */ |
cparata | 0:c761bc6186e8 | 1422 | int32_t lps22hh_int_treshold_set(lps22hh_ctx_t *ctx, uint16_t buff) |
cparata | 0:c761bc6186e8 | 1423 | { |
cparata | 1:978cae936ddb | 1424 | int32_t ret; |
cparata | 1:978cae936ddb | 1425 | lps22hh_ths_p_l_t ths_p_l; |
cparata | 1:978cae936ddb | 1426 | lps22hh_ths_p_h_t ths_p_h; |
cparata | 1:978cae936ddb | 1427 | |
cparata | 1:978cae936ddb | 1428 | ths_p_l.ths = (uint8_t)(buff & 0x00FFU); |
cparata | 1:978cae936ddb | 1429 | ths_p_h.ths = (uint8_t)((buff & 0x7F00U) >> 8); |
cparata | 1:978cae936ddb | 1430 | |
cparata | 1:978cae936ddb | 1431 | ret = lps22hh_write_reg(ctx, LPS22HH_THS_P_L, |
cparata | 1:978cae936ddb | 1432 | (uint8_t *)&ths_p_l, 1); |
cparata | 1:978cae936ddb | 1433 | if (ret == 0) { |
cparata | 1:978cae936ddb | 1434 | ret = lps22hh_write_reg(ctx, LPS22HH_THS_P_H, |
cparata | 1:978cae936ddb | 1435 | (uint8_t *)&ths_p_h, 1); |
cparata | 1:978cae936ddb | 1436 | } |
cparata | 1:978cae936ddb | 1437 | return ret; |
cparata | 0:c761bc6186e8 | 1438 | } |
cparata | 0:c761bc6186e8 | 1439 | |
cparata | 0:c761bc6186e8 | 1440 | /** |
cparata | 0:c761bc6186e8 | 1441 | * @brief User-defined threshold value for pressure interrupt event.[get] |
cparata | 0:c761bc6186e8 | 1442 | * |
cparata | 0:c761bc6186e8 | 1443 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1444 | * @param buff buffer that stores data read |
cparata | 0:c761bc6186e8 | 1445 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1446 | * |
cparata | 0:c761bc6186e8 | 1447 | */ |
cparata | 0:c761bc6186e8 | 1448 | int32_t lps22hh_int_treshold_get(lps22hh_ctx_t *ctx, uint16_t *buff) |
cparata | 0:c761bc6186e8 | 1449 | { |
cparata | 1:978cae936ddb | 1450 | int32_t ret; |
cparata | 1:978cae936ddb | 1451 | lps22hh_ths_p_l_t ths_p_l; |
cparata | 1:978cae936ddb | 1452 | lps22hh_ths_p_h_t ths_p_h; |
cparata | 1:978cae936ddb | 1453 | |
cparata | 1:978cae936ddb | 1454 | ret = lps22hh_read_reg(ctx, LPS22HH_THS_P_L, |
cparata | 1:978cae936ddb | 1455 | (uint8_t *)&ths_p_l, 1); |
cparata | 1:978cae936ddb | 1456 | if (ret == 0) { |
cparata | 1:978cae936ddb | 1457 | ret = lps22hh_read_reg(ctx, LPS22HH_THS_P_H, |
cparata | 1:978cae936ddb | 1458 | (uint8_t *)&ths_p_h, 1); |
cparata | 1:978cae936ddb | 1459 | *buff = (uint16_t)ths_p_h.ths << 8; |
cparata | 1:978cae936ddb | 1460 | *buff |= (uint16_t)ths_p_l.ths; |
cparata | 1:978cae936ddb | 1461 | } |
cparata | 1:978cae936ddb | 1462 | return ret; |
cparata | 0:c761bc6186e8 | 1463 | } |
cparata | 0:c761bc6186e8 | 1464 | |
cparata | 0:c761bc6186e8 | 1465 | /** |
cparata | 0:c761bc6186e8 | 1466 | * @} |
cparata | 0:c761bc6186e8 | 1467 | * |
cparata | 0:c761bc6186e8 | 1468 | */ |
cparata | 0:c761bc6186e8 | 1469 | |
cparata | 0:c761bc6186e8 | 1470 | /** |
cparata | 0:c761bc6186e8 | 1471 | * @defgroup LPS22HH_Fifo |
cparata | 0:c761bc6186e8 | 1472 | * @brief This section group all the functions concerning the fifo usage. |
cparata | 0:c761bc6186e8 | 1473 | * @{ |
cparata | 0:c761bc6186e8 | 1474 | * |
cparata | 0:c761bc6186e8 | 1475 | */ |
cparata | 0:c761bc6186e8 | 1476 | |
cparata | 0:c761bc6186e8 | 1477 | /** |
cparata | 0:c761bc6186e8 | 1478 | * @brief Fifo Mode selection.[set] |
cparata | 0:c761bc6186e8 | 1479 | * |
cparata | 0:c761bc6186e8 | 1480 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1481 | * @param val change the values of f_mode in reg FIFO_CTRL |
cparata | 0:c761bc6186e8 | 1482 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1483 | * |
cparata | 0:c761bc6186e8 | 1484 | */ |
cparata | 0:c761bc6186e8 | 1485 | int32_t lps22hh_fifo_mode_set(lps22hh_ctx_t *ctx, lps22hh_f_mode_t val) |
cparata | 0:c761bc6186e8 | 1486 | { |
cparata | 1:978cae936ddb | 1487 | lps22hh_fifo_ctrl_t reg; |
cparata | 1:978cae936ddb | 1488 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1489 | |
cparata | 1:978cae936ddb | 1490 | ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1491 | if (ret == 0) { |
cparata | 1:978cae936ddb | 1492 | reg.f_mode = (uint8_t)val; |
cparata | 1:978cae936ddb | 1493 | ret = lps22hh_write_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1494 | } |
cparata | 1:978cae936ddb | 1495 | return ret; |
cparata | 0:c761bc6186e8 | 1496 | } |
cparata | 0:c761bc6186e8 | 1497 | |
cparata | 0:c761bc6186e8 | 1498 | /** |
cparata | 0:c761bc6186e8 | 1499 | * @brief Fifo Mode selection.[get] |
cparata | 0:c761bc6186e8 | 1500 | * |
cparata | 0:c761bc6186e8 | 1501 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1502 | * @param val Get the values of f_mode in reg FIFO_CTRL |
cparata | 0:c761bc6186e8 | 1503 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1504 | * |
cparata | 0:c761bc6186e8 | 1505 | */ |
cparata | 0:c761bc6186e8 | 1506 | int32_t lps22hh_fifo_mode_get(lps22hh_ctx_t *ctx, lps22hh_f_mode_t *val) |
cparata | 0:c761bc6186e8 | 1507 | { |
cparata | 1:978cae936ddb | 1508 | lps22hh_fifo_ctrl_t reg; |
cparata | 1:978cae936ddb | 1509 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1510 | |
cparata | 1:978cae936ddb | 1511 | ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t *) ®, 1); |
cparata | 0:c761bc6186e8 | 1512 | |
cparata | 1:978cae936ddb | 1513 | switch (reg.f_mode) { |
cparata | 1:978cae936ddb | 1514 | case LPS22HH_BYPASS_MODE: |
cparata | 1:978cae936ddb | 1515 | *val = LPS22HH_BYPASS_MODE; |
cparata | 1:978cae936ddb | 1516 | break; |
cparata | 1:978cae936ddb | 1517 | case LPS22HH_FIFO_MODE: |
cparata | 1:978cae936ddb | 1518 | *val = LPS22HH_FIFO_MODE; |
cparata | 1:978cae936ddb | 1519 | break; |
cparata | 1:978cae936ddb | 1520 | case LPS22HH_STREAM_MODE: |
cparata | 1:978cae936ddb | 1521 | *val = LPS22HH_STREAM_MODE; |
cparata | 1:978cae936ddb | 1522 | break; |
cparata | 1:978cae936ddb | 1523 | case LPS22HH_DYNAMIC_STREAM_MODE: |
cparata | 1:978cae936ddb | 1524 | *val = LPS22HH_DYNAMIC_STREAM_MODE; |
cparata | 1:978cae936ddb | 1525 | break; |
cparata | 1:978cae936ddb | 1526 | case LPS22HH_BYPASS_TO_FIFO_MODE: |
cparata | 1:978cae936ddb | 1527 | *val = LPS22HH_BYPASS_TO_FIFO_MODE; |
cparata | 1:978cae936ddb | 1528 | break; |
cparata | 1:978cae936ddb | 1529 | case LPS22HH_BYPASS_TO_STREAM_MODE: |
cparata | 1:978cae936ddb | 1530 | *val = LPS22HH_BYPASS_TO_STREAM_MODE; |
cparata | 1:978cae936ddb | 1531 | break; |
cparata | 1:978cae936ddb | 1532 | case LPS22HH_STREAM_TO_FIFO_MODE: |
cparata | 1:978cae936ddb | 1533 | *val = LPS22HH_STREAM_TO_FIFO_MODE; |
cparata | 1:978cae936ddb | 1534 | break; |
cparata | 1:978cae936ddb | 1535 | default: |
cparata | 1:978cae936ddb | 1536 | *val = LPS22HH_BYPASS_MODE; |
cparata | 1:978cae936ddb | 1537 | break; |
cparata | 1:978cae936ddb | 1538 | } |
cparata | 0:c761bc6186e8 | 1539 | |
cparata | 1:978cae936ddb | 1540 | return ret; |
cparata | 0:c761bc6186e8 | 1541 | } |
cparata | 0:c761bc6186e8 | 1542 | |
cparata | 0:c761bc6186e8 | 1543 | /** |
cparata | 0:c761bc6186e8 | 1544 | * @brief Sensing chain FIFO stop values memorization at |
cparata | 0:c761bc6186e8 | 1545 | * threshold level.[set] |
cparata | 0:c761bc6186e8 | 1546 | * |
cparata | 0:c761bc6186e8 | 1547 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1548 | * @param val change the values of stop_on_wtm in reg FIFO_CTRL |
cparata | 0:c761bc6186e8 | 1549 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1550 | * |
cparata | 0:c761bc6186e8 | 1551 | */ |
cparata | 0:c761bc6186e8 | 1552 | int32_t lps22hh_fifo_stop_on_wtm_set(lps22hh_ctx_t *ctx, uint8_t val) |
cparata | 0:c761bc6186e8 | 1553 | { |
cparata | 1:978cae936ddb | 1554 | lps22hh_fifo_ctrl_t reg; |
cparata | 1:978cae936ddb | 1555 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1556 | |
cparata | 1:978cae936ddb | 1557 | ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1558 | if (ret == 0) { |
cparata | 1:978cae936ddb | 1559 | reg.stop_on_wtm = val; |
cparata | 1:978cae936ddb | 1560 | ret = lps22hh_write_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1561 | } |
cparata | 1:978cae936ddb | 1562 | return ret; |
cparata | 0:c761bc6186e8 | 1563 | } |
cparata | 0:c761bc6186e8 | 1564 | |
cparata | 0:c761bc6186e8 | 1565 | /** |
cparata | 0:c761bc6186e8 | 1566 | * @brief Sensing chain FIFO stop values memorization at threshold |
cparata | 0:c761bc6186e8 | 1567 | * level.[get] |
cparata | 0:c761bc6186e8 | 1568 | * |
cparata | 0:c761bc6186e8 | 1569 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1570 | * @param val change the values of stop_on_wtm in reg FIFO_CTRL |
cparata | 0:c761bc6186e8 | 1571 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1572 | * |
cparata | 0:c761bc6186e8 | 1573 | */ |
cparata | 0:c761bc6186e8 | 1574 | int32_t lps22hh_fifo_stop_on_wtm_get(lps22hh_ctx_t *ctx, uint8_t *val) |
cparata | 0:c761bc6186e8 | 1575 | { |
cparata | 1:978cae936ddb | 1576 | lps22hh_fifo_ctrl_t reg; |
cparata | 1:978cae936ddb | 1577 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1578 | |
cparata | 1:978cae936ddb | 1579 | ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1580 | *val = reg.stop_on_wtm; |
cparata | 0:c761bc6186e8 | 1581 | |
cparata | 1:978cae936ddb | 1582 | return ret; |
cparata | 0:c761bc6186e8 | 1583 | } |
cparata | 0:c761bc6186e8 | 1584 | |
cparata | 0:c761bc6186e8 | 1585 | /** |
cparata | 0:c761bc6186e8 | 1586 | * @brief FIFO watermark level selection.[set] |
cparata | 0:c761bc6186e8 | 1587 | * |
cparata | 0:c761bc6186e8 | 1588 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1589 | * @param val change the values of wtm in reg FIFO_WTM |
cparata | 0:c761bc6186e8 | 1590 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1591 | * |
cparata | 0:c761bc6186e8 | 1592 | */ |
cparata | 0:c761bc6186e8 | 1593 | int32_t lps22hh_fifo_watermark_set(lps22hh_ctx_t *ctx, uint8_t val) |
cparata | 0:c761bc6186e8 | 1594 | { |
cparata | 1:978cae936ddb | 1595 | lps22hh_fifo_wtm_t reg; |
cparata | 1:978cae936ddb | 1596 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1597 | |
cparata | 1:978cae936ddb | 1598 | ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_WTM, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1599 | if (ret == 0) { |
cparata | 1:978cae936ddb | 1600 | reg.wtm = val; |
cparata | 1:978cae936ddb | 1601 | ret = lps22hh_write_reg(ctx, LPS22HH_FIFO_WTM, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1602 | } |
cparata | 1:978cae936ddb | 1603 | return ret; |
cparata | 0:c761bc6186e8 | 1604 | } |
cparata | 0:c761bc6186e8 | 1605 | |
cparata | 0:c761bc6186e8 | 1606 | /** |
cparata | 0:c761bc6186e8 | 1607 | * @brief FIFO watermark level selection.[get] |
cparata | 0:c761bc6186e8 | 1608 | * |
cparata | 0:c761bc6186e8 | 1609 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1610 | * @param val change the values of wtm in reg FIFO_WTM |
cparata | 0:c761bc6186e8 | 1611 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1612 | * |
cparata | 0:c761bc6186e8 | 1613 | */ |
cparata | 0:c761bc6186e8 | 1614 | int32_t lps22hh_fifo_watermark_get(lps22hh_ctx_t *ctx, uint8_t *val) |
cparata | 0:c761bc6186e8 | 1615 | { |
cparata | 1:978cae936ddb | 1616 | lps22hh_fifo_wtm_t reg; |
cparata | 1:978cae936ddb | 1617 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1618 | |
cparata | 1:978cae936ddb | 1619 | ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_WTM, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1620 | *val = reg.wtm; |
cparata | 0:c761bc6186e8 | 1621 | |
cparata | 1:978cae936ddb | 1622 | return ret; |
cparata | 0:c761bc6186e8 | 1623 | } |
cparata | 0:c761bc6186e8 | 1624 | |
cparata | 0:c761bc6186e8 | 1625 | /** |
cparata | 0:c761bc6186e8 | 1626 | * @brief FIFO stored data level.[get] |
cparata | 0:c761bc6186e8 | 1627 | * |
cparata | 0:c761bc6186e8 | 1628 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1629 | * @param buff buffer that stores data read |
cparata | 0:c761bc6186e8 | 1630 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1631 | * |
cparata | 0:c761bc6186e8 | 1632 | */ |
cparata | 0:c761bc6186e8 | 1633 | int32_t lps22hh_fifo_data_level_get(lps22hh_ctx_t *ctx, uint8_t *buff) |
cparata | 0:c761bc6186e8 | 1634 | { |
cparata | 1:978cae936ddb | 1635 | int32_t ret; |
cparata | 1:978cae936ddb | 1636 | ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS1, buff, 1); |
cparata | 1:978cae936ddb | 1637 | return ret; |
cparata | 0:c761bc6186e8 | 1638 | } |
cparata | 0:c761bc6186e8 | 1639 | |
cparata | 0:c761bc6186e8 | 1640 | /** |
cparata | 0:c761bc6186e8 | 1641 | * @brief Read all the FIFO status flag of the device.[get] |
cparata | 0:c761bc6186e8 | 1642 | * |
cparata | 0:c761bc6186e8 | 1643 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1644 | * @param val registers FIFO_STATUS2 |
cparata | 0:c761bc6186e8 | 1645 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1646 | * |
cparata | 0:c761bc6186e8 | 1647 | */ |
cparata | 0:c761bc6186e8 | 1648 | int32_t lps22hh_fifo_src_get(lps22hh_ctx_t *ctx, lps22hh_fifo_status2_t *val) |
cparata | 0:c761bc6186e8 | 1649 | { |
cparata | 1:978cae936ddb | 1650 | int32_t ret; |
cparata | 1:978cae936ddb | 1651 | ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t *) val, 1); |
cparata | 1:978cae936ddb | 1652 | return ret; |
cparata | 0:c761bc6186e8 | 1653 | } |
cparata | 0:c761bc6186e8 | 1654 | |
cparata | 0:c761bc6186e8 | 1655 | /** |
cparata | 0:c761bc6186e8 | 1656 | * @brief Smart FIFO full status.[get] |
cparata | 0:c761bc6186e8 | 1657 | * |
cparata | 0:c761bc6186e8 | 1658 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1659 | * @param val change the values of fifo_full_ia in reg FIFO_STATUS2 |
cparata | 0:c761bc6186e8 | 1660 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1661 | * |
cparata | 0:c761bc6186e8 | 1662 | */ |
cparata | 0:c761bc6186e8 | 1663 | int32_t lps22hh_fifo_full_flag_get(lps22hh_ctx_t *ctx, uint8_t *val) |
cparata | 0:c761bc6186e8 | 1664 | { |
cparata | 1:978cae936ddb | 1665 | lps22hh_fifo_status2_t reg; |
cparata | 1:978cae936ddb | 1666 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1667 | |
cparata | 1:978cae936ddb | 1668 | ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1669 | *val = reg.fifo_full_ia; |
cparata | 0:c761bc6186e8 | 1670 | |
cparata | 1:978cae936ddb | 1671 | return ret; |
cparata | 0:c761bc6186e8 | 1672 | } |
cparata | 0:c761bc6186e8 | 1673 | |
cparata | 0:c761bc6186e8 | 1674 | /** |
cparata | 0:c761bc6186e8 | 1675 | * @brief FIFO overrun status.[get] |
cparata | 0:c761bc6186e8 | 1676 | * |
cparata | 0:c761bc6186e8 | 1677 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1678 | * @param val change the values of fifo_ovr_ia in reg FIFO_STATUS2 |
cparata | 0:c761bc6186e8 | 1679 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1680 | * |
cparata | 0:c761bc6186e8 | 1681 | */ |
cparata | 0:c761bc6186e8 | 1682 | int32_t lps22hh_fifo_ovr_flag_get(lps22hh_ctx_t *ctx, uint8_t *val) |
cparata | 0:c761bc6186e8 | 1683 | { |
cparata | 1:978cae936ddb | 1684 | lps22hh_fifo_status2_t reg; |
cparata | 1:978cae936ddb | 1685 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1686 | |
cparata | 1:978cae936ddb | 1687 | ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1688 | *val = reg.fifo_ovr_ia; |
cparata | 0:c761bc6186e8 | 1689 | |
cparata | 1:978cae936ddb | 1690 | return ret; |
cparata | 0:c761bc6186e8 | 1691 | } |
cparata | 0:c761bc6186e8 | 1692 | |
cparata | 0:c761bc6186e8 | 1693 | /** |
cparata | 0:c761bc6186e8 | 1694 | * @brief FIFO watermark status.[get] |
cparata | 0:c761bc6186e8 | 1695 | * |
cparata | 0:c761bc6186e8 | 1696 | * @param ctx read / write interface definitions |
cparata | 0:c761bc6186e8 | 1697 | * @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2 |
cparata | 0:c761bc6186e8 | 1698 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:c761bc6186e8 | 1699 | * |
cparata | 0:c761bc6186e8 | 1700 | */ |
cparata | 0:c761bc6186e8 | 1701 | int32_t lps22hh_fifo_wtm_flag_get(lps22hh_ctx_t *ctx, uint8_t *val) |
cparata | 0:c761bc6186e8 | 1702 | { |
cparata | 1:978cae936ddb | 1703 | lps22hh_fifo_status2_t reg; |
cparata | 1:978cae936ddb | 1704 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1705 | |
cparata | 1:978cae936ddb | 1706 | ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t *) ®, 1); |
cparata | 1:978cae936ddb | 1707 | *val = reg.fifo_wtm_ia; |
cparata | 0:c761bc6186e8 | 1708 | |
cparata | 1:978cae936ddb | 1709 | return ret; |
cparata | 0:c761bc6186e8 | 1710 | } |
cparata | 0:c761bc6186e8 | 1711 | |
cparata | 0:c761bc6186e8 | 1712 | /** |
cparata | 0:c761bc6186e8 | 1713 | * @brief FIFO overrun interrupt on INT_DRDY pin.[set] |
cparata | 0:c761bc6186e8 | 1714 | * |
cparata | 0:c761bc6186e8 | 1715 | * @param lps22hh_ctx_t *ctx: read / write interface definitions |
cparata | 0:c761bc6186e8 | 1716 | * @param uint8_t val: change the values of f_ovr in reg CTRL_REG3 |
cparata | 0:c761bc6186e8 | 1717 | * |
cparata | 0:c761bc6186e8 | 1718 | */ |
cparata | 0:c761bc6186e8 | 1719 | int32_t lps22hh_fifo_ovr_on_int_set(lps22hh_ctx_t *ctx, uint8_t val) |
cparata | 0:c761bc6186e8 | 1720 | { |
cparata | 1:978cae936ddb | 1721 | lps22hh_reg_t reg; |
cparata | 1:978cae936ddb | 1722 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1723 | |
cparata | 1:978cae936ddb | 1724 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, &(reg.byte), 1); |
cparata | 1:978cae936ddb | 1725 | reg.ctrl_reg3.int_f_ovr = val; |
cparata | 1:978cae936ddb | 1726 | ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG3, &(reg.byte), 1); |
cparata | 0:c761bc6186e8 | 1727 | |
cparata | 1:978cae936ddb | 1728 | return ret; |
cparata | 0:c761bc6186e8 | 1729 | } |
cparata | 0:c761bc6186e8 | 1730 | |
cparata | 0:c761bc6186e8 | 1731 | /** |
cparata | 0:c761bc6186e8 | 1732 | * @brief FIFO overrun interrupt on INT_DRDY pin.[get] |
cparata | 0:c761bc6186e8 | 1733 | * |
cparata | 0:c761bc6186e8 | 1734 | * @param lps22hh_ctx_t *ctx: read / write interface definitions |
cparata | 0:c761bc6186e8 | 1735 | * @param uint8_t: change the values of f_ovr in reg CTRL_REG3 |
cparata | 0:c761bc6186e8 | 1736 | * |
cparata | 0:c761bc6186e8 | 1737 | */ |
cparata | 0:c761bc6186e8 | 1738 | int32_t lps22hh_fifo_ovr_on_int_get(lps22hh_ctx_t *ctx, uint8_t *val) |
cparata | 0:c761bc6186e8 | 1739 | { |
cparata | 1:978cae936ddb | 1740 | lps22hh_reg_t reg; |
cparata | 1:978cae936ddb | 1741 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1742 | |
cparata | 1:978cae936ddb | 1743 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, &(reg.byte), 1); |
cparata | 1:978cae936ddb | 1744 | *val = reg.ctrl_reg3.int_f_ovr; |
cparata | 0:c761bc6186e8 | 1745 | |
cparata | 1:978cae936ddb | 1746 | return ret; |
cparata | 0:c761bc6186e8 | 1747 | } |
cparata | 0:c761bc6186e8 | 1748 | |
cparata | 0:c761bc6186e8 | 1749 | /** |
cparata | 0:c761bc6186e8 | 1750 | * @brief FIFO watermark status on INT_DRDY pin.[set] |
cparata | 0:c761bc6186e8 | 1751 | * |
cparata | 0:c761bc6186e8 | 1752 | * @param lps22hh_ctx_t *ctx: read / write interface definitions |
cparata | 0:c761bc6186e8 | 1753 | * @param uint8_t val: change the values of f_fth in reg CTRL_REG3 |
cparata | 0:c761bc6186e8 | 1754 | * |
cparata | 0:c761bc6186e8 | 1755 | */ |
cparata | 0:c761bc6186e8 | 1756 | int32_t lps22hh_fifo_threshold_on_int_set(lps22hh_ctx_t *ctx, uint8_t val) |
cparata | 0:c761bc6186e8 | 1757 | { |
cparata | 1:978cae936ddb | 1758 | lps22hh_reg_t reg; |
cparata | 1:978cae936ddb | 1759 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1760 | |
cparata | 1:978cae936ddb | 1761 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, &(reg.byte), 1); |
cparata | 1:978cae936ddb | 1762 | reg.ctrl_reg3.int_f_wtm = val; |
cparata | 1:978cae936ddb | 1763 | ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG3, &(reg.byte), 1); |
cparata | 0:c761bc6186e8 | 1764 | |
cparata | 1:978cae936ddb | 1765 | return ret; |
cparata | 0:c761bc6186e8 | 1766 | } |
cparata | 0:c761bc6186e8 | 1767 | |
cparata | 0:c761bc6186e8 | 1768 | /** |
cparata | 0:c761bc6186e8 | 1769 | * @brief FIFO watermark status on INT_DRDY pin.[get] |
cparata | 0:c761bc6186e8 | 1770 | * |
cparata | 0:c761bc6186e8 | 1771 | * @param lps22hb_ctx_t *ctx: read / write interface definitions |
cparata | 0:c761bc6186e8 | 1772 | * @param uint8_t: change the values of f_fth in reg CTRL_REG3 |
cparata | 0:c761bc6186e8 | 1773 | * |
cparata | 0:c761bc6186e8 | 1774 | */ |
cparata | 0:c761bc6186e8 | 1775 | int32_t lps22hh_fifo_threshold_on_int_get(lps22hh_ctx_t *ctx, uint8_t *val) |
cparata | 0:c761bc6186e8 | 1776 | { |
cparata | 1:978cae936ddb | 1777 | lps22hh_reg_t reg; |
cparata | 1:978cae936ddb | 1778 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1779 | |
cparata | 1:978cae936ddb | 1780 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, &(reg.byte), 1); |
cparata | 1:978cae936ddb | 1781 | *val = reg.ctrl_reg3.int_f_wtm; |
cparata | 0:c761bc6186e8 | 1782 | |
cparata | 1:978cae936ddb | 1783 | return ret; |
cparata | 0:c761bc6186e8 | 1784 | } |
cparata | 0:c761bc6186e8 | 1785 | |
cparata | 0:c761bc6186e8 | 1786 | /** |
cparata | 0:c761bc6186e8 | 1787 | * @brief FIFO full flag on INT_DRDY pin.[set] |
cparata | 0:c761bc6186e8 | 1788 | * |
cparata | 0:c761bc6186e8 | 1789 | * @param lps22hh_ctx_t *ctx: read / write interface definitions |
cparata | 0:c761bc6186e8 | 1790 | * @param uint8_t val: change the values of f_fss5 in reg CTRL_REG3 |
cparata | 0:c761bc6186e8 | 1791 | * |
cparata | 0:c761bc6186e8 | 1792 | */ |
cparata | 0:c761bc6186e8 | 1793 | int32_t lps22hh_fifo_full_on_int_set(lps22hh_ctx_t *ctx, uint8_t val) |
cparata | 0:c761bc6186e8 | 1794 | { |
cparata | 1:978cae936ddb | 1795 | lps22hh_reg_t reg; |
cparata | 1:978cae936ddb | 1796 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1797 | |
cparata | 1:978cae936ddb | 1798 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, &(reg.byte), 1); |
cparata | 1:978cae936ddb | 1799 | reg.ctrl_reg3.int_f_full = val; |
cparata | 1:978cae936ddb | 1800 | ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG3, &(reg.byte), 1); |
cparata | 0:c761bc6186e8 | 1801 | |
cparata | 1:978cae936ddb | 1802 | return ret; |
cparata | 0:c761bc6186e8 | 1803 | } |
cparata | 0:c761bc6186e8 | 1804 | |
cparata | 0:c761bc6186e8 | 1805 | /** |
cparata | 0:c761bc6186e8 | 1806 | * @brief FIFO full flag on INT_DRDY pin.[get] |
cparata | 0:c761bc6186e8 | 1807 | * |
cparata | 0:c761bc6186e8 | 1808 | * @param lps22hh_ctx_t *ctx: read / write interface definitions |
cparata | 0:c761bc6186e8 | 1809 | * @param uint8_t: change the values of f_fss5 in reg CTRL_REG3 |
cparata | 0:c761bc6186e8 | 1810 | * |
cparata | 0:c761bc6186e8 | 1811 | */ |
cparata | 0:c761bc6186e8 | 1812 | int32_t lps22hh_fifo_full_on_int_get(lps22hh_ctx_t *ctx, uint8_t *val) |
cparata | 0:c761bc6186e8 | 1813 | { |
cparata | 1:978cae936ddb | 1814 | lps22hh_reg_t reg; |
cparata | 1:978cae936ddb | 1815 | int32_t ret; |
cparata | 0:c761bc6186e8 | 1816 | |
cparata | 1:978cae936ddb | 1817 | ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, &(reg.byte), 1); |
cparata | 1:978cae936ddb | 1818 | *val = reg.ctrl_reg3.int_f_full; |
cparata | 0:c761bc6186e8 | 1819 | |
cparata | 1:978cae936ddb | 1820 | return ret; |
cparata | 0:c761bc6186e8 | 1821 | } |
cparata | 0:c761bc6186e8 | 1822 | |
cparata | 0:c761bc6186e8 | 1823 | /** |
cparata | 0:c761bc6186e8 | 1824 | * @} |
cparata | 0:c761bc6186e8 | 1825 | * |
cparata | 0:c761bc6186e8 | 1826 | */ |
cparata | 0:c761bc6186e8 | 1827 | |
cparata | 0:c761bc6186e8 | 1828 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |