LIS2DW12 accelerometer sensor library
Dependencies: X_NUCLEO_COMMON ST_INTERFACES
lis2dw12_reg.c@5:b6ce53be44c2, 2019-09-17 (annotated)
- Committer:
- martlefebvre94
- Date:
- Tue Sep 17 08:40:17 2019 +0000
- Revision:
- 5:b6ce53be44c2
- Parent:
- 4:94c5d5546161
Addition of functions for the configuration of the accelerometer sensor
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
cparata | 3:111317ba9301 | 1 | /** |
cparata | 0:dff8803aace7 | 2 | ****************************************************************************** |
cparata | 0:dff8803aace7 | 3 | * @file lis2dw12_reg.c |
cparata | 2:a94816b14e3d | 4 | * @author Sensors Software Solution Team |
cparata | 0:dff8803aace7 | 5 | * @brief LIS2DW12 driver file |
cparata | 0:dff8803aace7 | 6 | ****************************************************************************** |
cparata | 0:dff8803aace7 | 7 | * @attention |
cparata | 0:dff8803aace7 | 8 | * |
cparata | 0:dff8803aace7 | 9 | * <h2><center>© COPYRIGHT(c) 2018 STMicroelectronics</center></h2> |
cparata | 0:dff8803aace7 | 10 | * |
cparata | 2:a94816b14e3d | 11 | * Redistribution and use in source and binary forms, with or without |
cparata | 2:a94816b14e3d | 12 | * modification, are permitted provided that the following conditions |
cparata | 2:a94816b14e3d | 13 | * are met: |
cparata | 0:dff8803aace7 | 14 | * 1. Redistributions of source code must retain the above copyright notice, |
cparata | 0:dff8803aace7 | 15 | * this list of conditions and the following disclaimer. |
cparata | 2:a94816b14e3d | 16 | * 2. Redistributions in binary form must reproduce the above copyright |
cparata | 2:a94816b14e3d | 17 | * notice, this list of conditions and the following disclaimer in the |
cparata | 2:a94816b14e3d | 18 | * documentation and/or other materials provided with the distribution. |
cparata | 2:a94816b14e3d | 19 | * 3. Neither the name of STMicroelectronics nor the names of its |
cparata | 2:a94816b14e3d | 20 | * contributors may be used to endorse or promote products derived from |
cparata | 2:a94816b14e3d | 21 | * this software without specific prior written permission. |
cparata | 0:dff8803aace7 | 22 | * |
cparata | 0:dff8803aace7 | 23 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
cparata | 0:dff8803aace7 | 24 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
cparata | 2:a94816b14e3d | 25 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
cparata | 2:a94816b14e3d | 26 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
cparata | 2:a94816b14e3d | 27 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
cparata | 2:a94816b14e3d | 28 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
cparata | 2:a94816b14e3d | 29 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
cparata | 2:a94816b14e3d | 30 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
cparata | 2:a94816b14e3d | 31 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
cparata | 2:a94816b14e3d | 32 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
cparata | 2:a94816b14e3d | 33 | * POSSIBILITY OF SUCH DAMAGE. |
cparata | 0:dff8803aace7 | 34 | * |
cparata | 3:111317ba9301 | 35 | ****************************************************************************** |
cparata | 0:dff8803aace7 | 36 | */ |
cparata | 0:dff8803aace7 | 37 | |
cparata | 0:dff8803aace7 | 38 | #include "lis2dw12_reg.h" |
cparata | 0:dff8803aace7 | 39 | |
cparata | 0:dff8803aace7 | 40 | /** |
cparata | 2:a94816b14e3d | 41 | * @defgroup LIS2DW12 |
cparata | 2:a94816b14e3d | 42 | * @brief This file provides a set of functions needed to drive the |
cparata | 2:a94816b14e3d | 43 | * lis2dw12 enhanced inertial module. |
cparata | 0:dff8803aace7 | 44 | * @{ |
cparata | 2:a94816b14e3d | 45 | * |
cparata | 0:dff8803aace7 | 46 | */ |
cparata | 0:dff8803aace7 | 47 | |
cparata | 2:a94816b14e3d | 48 | /** |
cparata | 2:a94816b14e3d | 49 | * @defgroup LIS2DW12_Interfaces_Functions |
cparata | 2:a94816b14e3d | 50 | * @brief This section provide a set of functions used to read and |
cparata | 2:a94816b14e3d | 51 | * write a generic register of the device. |
cparata | 2:a94816b14e3d | 52 | * MANDATORY: return 0 -> no Error. |
cparata | 0:dff8803aace7 | 53 | * @{ |
cparata | 2:a94816b14e3d | 54 | * |
cparata | 0:dff8803aace7 | 55 | */ |
cparata | 0:dff8803aace7 | 56 | |
cparata | 0:dff8803aace7 | 57 | /** |
cparata | 0:dff8803aace7 | 58 | * @brief Read generic device register |
cparata | 2:a94816b14e3d | 59 | * |
cparata | 2:a94816b14e3d | 60 | * @param ctx read / write interface definitions(ptr) |
cparata | 2:a94816b14e3d | 61 | * @param reg register to read |
cparata | 2:a94816b14e3d | 62 | * @param data pointer to buffer that store the data read(ptr) |
cparata | 2:a94816b14e3d | 63 | * @param len number of consecutive register to read |
cparata | 2:a94816b14e3d | 64 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 65 | * |
cparata | 0:dff8803aace7 | 66 | */ |
cparata | 4:94c5d5546161 | 67 | int32_t lis2dw12_read_reg(lis2dw12_ctx_t *ctx, uint8_t reg, uint8_t *data, |
cparata | 0:dff8803aace7 | 68 | uint16_t len) |
cparata | 0:dff8803aace7 | 69 | { |
cparata | 4:94c5d5546161 | 70 | int32_t ret; |
cparata | 4:94c5d5546161 | 71 | ret = ctx->read_reg(ctx->handle, reg, data, len); |
cparata | 4:94c5d5546161 | 72 | return ret; |
cparata | 0:dff8803aace7 | 73 | } |
cparata | 0:dff8803aace7 | 74 | |
cparata | 0:dff8803aace7 | 75 | /** |
cparata | 0:dff8803aace7 | 76 | * @brief Write generic device register |
cparata | 0:dff8803aace7 | 77 | * |
cparata | 2:a94816b14e3d | 78 | * @param ctx read / write interface definitions(ptr) |
cparata | 2:a94816b14e3d | 79 | * @param reg register to write |
cparata | 2:a94816b14e3d | 80 | * @param data pointer to data to write in register reg(ptr) |
cparata | 2:a94816b14e3d | 81 | * @param len number of consecutive register to write |
cparata | 2:a94816b14e3d | 82 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 2:a94816b14e3d | 83 | * |
cparata | 2:a94816b14e3d | 84 | */ |
cparata | 4:94c5d5546161 | 85 | int32_t lis2dw12_write_reg(lis2dw12_ctx_t *ctx, uint8_t reg, uint8_t *data, |
cparata | 0:dff8803aace7 | 86 | uint16_t len) |
cparata | 0:dff8803aace7 | 87 | { |
cparata | 4:94c5d5546161 | 88 | int32_t ret; |
cparata | 4:94c5d5546161 | 89 | ret = ctx->write_reg(ctx->handle, reg, data, len); |
cparata | 4:94c5d5546161 | 90 | return ret; |
cparata | 0:dff8803aace7 | 91 | } |
cparata | 0:dff8803aace7 | 92 | |
cparata | 0:dff8803aace7 | 93 | /** |
cparata | 0:dff8803aace7 | 94 | * @} |
cparata | 2:a94816b14e3d | 95 | * |
cparata | 2:a94816b14e3d | 96 | */ |
cparata | 4:94c5d5546161 | 97 | |
cparata | 2:a94816b14e3d | 98 | /** |
cparata | 2:a94816b14e3d | 99 | * @defgroup LIS2DW12_Sensitivity |
cparata | 2:a94816b14e3d | 100 | * @brief These functions convert raw-data into engineering units. |
cparata | 2:a94816b14e3d | 101 | * @{ |
cparata | 2:a94816b14e3d | 102 | * |
cparata | 2:a94816b14e3d | 103 | */ |
cparata | 2:a94816b14e3d | 104 | |
cparata | 2:a94816b14e3d | 105 | float lis2dw12_from_fs2_to_mg(int16_t lsb) |
cparata | 2:a94816b14e3d | 106 | { |
cparata | 4:94c5d5546161 | 107 | return ((float)lsb) * 0.061f; |
cparata | 2:a94816b14e3d | 108 | } |
cparata | 2:a94816b14e3d | 109 | |
cparata | 2:a94816b14e3d | 110 | float lis2dw12_from_fs4_to_mg(int16_t lsb) |
cparata | 2:a94816b14e3d | 111 | { |
cparata | 4:94c5d5546161 | 112 | return ((float)lsb) * 0.122f; |
cparata | 2:a94816b14e3d | 113 | } |
cparata | 2:a94816b14e3d | 114 | |
cparata | 2:a94816b14e3d | 115 | float lis2dw12_from_fs8_to_mg(int16_t lsb) |
cparata | 2:a94816b14e3d | 116 | { |
cparata | 4:94c5d5546161 | 117 | return ((float)lsb) * 0.244f; |
cparata | 2:a94816b14e3d | 118 | } |
cparata | 2:a94816b14e3d | 119 | |
cparata | 2:a94816b14e3d | 120 | float lis2dw12_from_fs16_to_mg(int16_t lsb) |
cparata | 2:a94816b14e3d | 121 | { |
cparata | 4:94c5d5546161 | 122 | return ((float)lsb) * 0.488f; |
cparata | 2:a94816b14e3d | 123 | } |
cparata | 2:a94816b14e3d | 124 | |
cparata | 2:a94816b14e3d | 125 | float lis2dw12_from_fs2_lp1_to_mg(int16_t lsb) |
cparata | 2:a94816b14e3d | 126 | { |
cparata | 4:94c5d5546161 | 127 | return ((float)lsb) * 0.061f; |
cparata | 2:a94816b14e3d | 128 | } |
cparata | 2:a94816b14e3d | 129 | |
cparata | 2:a94816b14e3d | 130 | float lis2dw12_from_fs4_lp1_to_mg(int16_t lsb) |
cparata | 2:a94816b14e3d | 131 | { |
cparata | 4:94c5d5546161 | 132 | return ((float)lsb) * 0.122f; |
cparata | 2:a94816b14e3d | 133 | } |
cparata | 2:a94816b14e3d | 134 | |
cparata | 2:a94816b14e3d | 135 | float lis2dw12_from_fs8_lp1_to_mg(int16_t lsb) |
cparata | 2:a94816b14e3d | 136 | { |
cparata | 4:94c5d5546161 | 137 | return ((float)lsb) * 0.244f; |
cparata | 2:a94816b14e3d | 138 | } |
cparata | 2:a94816b14e3d | 139 | |
cparata | 2:a94816b14e3d | 140 | float lis2dw12_from_fs16_lp1_to_mg(int16_t lsb) |
cparata | 2:a94816b14e3d | 141 | { |
cparata | 4:94c5d5546161 | 142 | return ((float)lsb) * 0.488f; |
cparata | 2:a94816b14e3d | 143 | } |
cparata | 2:a94816b14e3d | 144 | |
cparata | 2:a94816b14e3d | 145 | float lis2dw12_from_lsb_to_celsius(int16_t lsb) |
cparata | 2:a94816b14e3d | 146 | { |
cparata | 4:94c5d5546161 | 147 | return (((float)lsb / 16.0f) + 25.0f); |
cparata | 2:a94816b14e3d | 148 | } |
cparata | 2:a94816b14e3d | 149 | |
cparata | 2:a94816b14e3d | 150 | /** |
cparata | 2:a94816b14e3d | 151 | * @} |
cparata | 2:a94816b14e3d | 152 | * |
cparata | 0:dff8803aace7 | 153 | */ |
cparata | 0:dff8803aace7 | 154 | |
cparata | 0:dff8803aace7 | 155 | /** |
cparata | 2:a94816b14e3d | 156 | * @defgroup LIS2DW12_Data_Generation |
cparata | 4:94c5d5546161 | 157 | * @brief This section groups all the functions concerning |
cparata | 2:a94816b14e3d | 158 | * data generation |
cparata | 0:dff8803aace7 | 159 | * @{ |
cparata | 2:a94816b14e3d | 160 | * |
cparata | 0:dff8803aace7 | 161 | */ |
cparata | 0:dff8803aace7 | 162 | |
cparata | 0:dff8803aace7 | 163 | /** |
cparata | 2:a94816b14e3d | 164 | * @brief Select accelerometer operating modes.[set] |
cparata | 0:dff8803aace7 | 165 | * |
cparata | 2:a94816b14e3d | 166 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 167 | * @param val change the values of mode / lp_mode in reg CTRL1 |
cparata | 2:a94816b14e3d | 168 | * and low_noise in reg CTRL6 |
cparata | 2:a94816b14e3d | 169 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 170 | * |
cparata | 0:dff8803aace7 | 171 | */ |
cparata | 0:dff8803aace7 | 172 | int32_t lis2dw12_power_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_mode_t val) |
cparata | 0:dff8803aace7 | 173 | { |
cparata | 4:94c5d5546161 | 174 | lis2dw12_ctrl1_t ctrl1; |
cparata | 4:94c5d5546161 | 175 | lis2dw12_ctrl6_t ctrl6; |
cparata | 4:94c5d5546161 | 176 | int32_t ret; |
cparata | 0:dff8803aace7 | 177 | |
cparata | 4:94c5d5546161 | 178 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1); |
cparata | 4:94c5d5546161 | 179 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 180 | ctrl1.mode = ((uint8_t) val & 0x0CU) >> 2; |
cparata | 4:94c5d5546161 | 181 | ctrl1.lp_mode = (uint8_t) val & 0x03U ; |
cparata | 4:94c5d5546161 | 182 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1); |
cparata | 4:94c5d5546161 | 183 | } |
cparata | 4:94c5d5546161 | 184 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 185 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1); |
cparata | 4:94c5d5546161 | 186 | } |
cparata | 4:94c5d5546161 | 187 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 188 | ctrl6.low_noise = ((uint8_t) val & 0x10U) >> 4; |
cparata | 4:94c5d5546161 | 189 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1); |
cparata | 4:94c5d5546161 | 190 | } |
cparata | 4:94c5d5546161 | 191 | return ret; |
cparata | 0:dff8803aace7 | 192 | } |
cparata | 0:dff8803aace7 | 193 | |
cparata | 0:dff8803aace7 | 194 | /** |
cparata | 2:a94816b14e3d | 195 | * @brief Select accelerometer operating modes.[get] |
cparata | 0:dff8803aace7 | 196 | * |
cparata | 2:a94816b14e3d | 197 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 198 | * @param val change the values of mode / lp_mode in reg CTRL1 |
cparata | 2:a94816b14e3d | 199 | * and low_noise in reg CTRL6 |
cparata | 2:a94816b14e3d | 200 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 201 | * |
cparata | 0:dff8803aace7 | 202 | */ |
cparata | 0:dff8803aace7 | 203 | int32_t lis2dw12_power_mode_get(lis2dw12_ctx_t *ctx, lis2dw12_mode_t *val) |
cparata | 0:dff8803aace7 | 204 | { |
cparata | 4:94c5d5546161 | 205 | lis2dw12_ctrl1_t ctrl1; |
cparata | 4:94c5d5546161 | 206 | lis2dw12_ctrl6_t ctrl6; |
cparata | 4:94c5d5546161 | 207 | int32_t ret; |
cparata | 2:a94816b14e3d | 208 | |
cparata | 4:94c5d5546161 | 209 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1); |
cparata | 4:94c5d5546161 | 210 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 211 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1); |
cparata | 0:dff8803aace7 | 212 | |
cparata | 4:94c5d5546161 | 213 | switch (((ctrl6.low_noise << 4) + (ctrl1.mode << 2) + |
cparata | 4:94c5d5546161 | 214 | ctrl1.lp_mode)) { |
cparata | 4:94c5d5546161 | 215 | case LIS2DW12_HIGH_PERFORMANCE: |
cparata | 4:94c5d5546161 | 216 | *val = LIS2DW12_HIGH_PERFORMANCE; |
cparata | 4:94c5d5546161 | 217 | break; |
cparata | 4:94c5d5546161 | 218 | case LIS2DW12_CONT_LOW_PWR_4: |
cparata | 4:94c5d5546161 | 219 | *val = LIS2DW12_CONT_LOW_PWR_4; |
cparata | 4:94c5d5546161 | 220 | break; |
cparata | 4:94c5d5546161 | 221 | case LIS2DW12_CONT_LOW_PWR_3: |
cparata | 4:94c5d5546161 | 222 | *val = LIS2DW12_CONT_LOW_PWR_3; |
cparata | 4:94c5d5546161 | 223 | break; |
cparata | 4:94c5d5546161 | 224 | case LIS2DW12_CONT_LOW_PWR_2: |
cparata | 4:94c5d5546161 | 225 | *val = LIS2DW12_CONT_LOW_PWR_2; |
cparata | 4:94c5d5546161 | 226 | break; |
cparata | 4:94c5d5546161 | 227 | case LIS2DW12_CONT_LOW_PWR_12bit: |
cparata | 4:94c5d5546161 | 228 | *val = LIS2DW12_CONT_LOW_PWR_12bit; |
cparata | 4:94c5d5546161 | 229 | break; |
cparata | 4:94c5d5546161 | 230 | case LIS2DW12_SINGLE_LOW_PWR_4: |
cparata | 4:94c5d5546161 | 231 | *val = LIS2DW12_SINGLE_LOW_PWR_4; |
cparata | 4:94c5d5546161 | 232 | break; |
cparata | 4:94c5d5546161 | 233 | case LIS2DW12_SINGLE_LOW_PWR_3: |
cparata | 4:94c5d5546161 | 234 | *val = LIS2DW12_SINGLE_LOW_PWR_3; |
cparata | 4:94c5d5546161 | 235 | break; |
cparata | 4:94c5d5546161 | 236 | case LIS2DW12_SINGLE_LOW_PWR_2: |
cparata | 4:94c5d5546161 | 237 | *val = LIS2DW12_SINGLE_LOW_PWR_2; |
cparata | 4:94c5d5546161 | 238 | break; |
cparata | 4:94c5d5546161 | 239 | case LIS2DW12_SINGLE_LOW_PWR_12bit: |
cparata | 4:94c5d5546161 | 240 | *val = LIS2DW12_SINGLE_LOW_PWR_12bit; |
cparata | 4:94c5d5546161 | 241 | break; |
cparata | 4:94c5d5546161 | 242 | case LIS2DW12_HIGH_PERFORMANCE_LOW_NOISE: |
cparata | 4:94c5d5546161 | 243 | *val = LIS2DW12_HIGH_PERFORMANCE_LOW_NOISE; |
cparata | 4:94c5d5546161 | 244 | break; |
cparata | 4:94c5d5546161 | 245 | case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_4: |
cparata | 4:94c5d5546161 | 246 | *val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_4; |
cparata | 4:94c5d5546161 | 247 | break; |
cparata | 4:94c5d5546161 | 248 | case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_3: |
cparata | 4:94c5d5546161 | 249 | *val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_3; |
cparata | 4:94c5d5546161 | 250 | break; |
cparata | 4:94c5d5546161 | 251 | case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_2: |
cparata | 4:94c5d5546161 | 252 | *val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_2; |
cparata | 4:94c5d5546161 | 253 | break; |
cparata | 4:94c5d5546161 | 254 | case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_12bit: |
cparata | 4:94c5d5546161 | 255 | *val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_12bit; |
cparata | 4:94c5d5546161 | 256 | break; |
cparata | 4:94c5d5546161 | 257 | case LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_4: |
cparata | 4:94c5d5546161 | 258 | *val = LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_4; |
cparata | 4:94c5d5546161 | 259 | break; |
cparata | 4:94c5d5546161 | 260 | case LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_3: |
cparata | 4:94c5d5546161 | 261 | *val = LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_3; |
cparata | 4:94c5d5546161 | 262 | break; |
cparata | 4:94c5d5546161 | 263 | case LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_2: |
cparata | 4:94c5d5546161 | 264 | *val = LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_2; |
cparata | 4:94c5d5546161 | 265 | break; |
cparata | 4:94c5d5546161 | 266 | case LIS2DW12_SINGLE_LOW_LOW_NOISE_PWR_12bit: |
cparata | 4:94c5d5546161 | 267 | *val = LIS2DW12_SINGLE_LOW_LOW_NOISE_PWR_12bit; |
cparata | 4:94c5d5546161 | 268 | break; |
cparata | 4:94c5d5546161 | 269 | default: |
cparata | 4:94c5d5546161 | 270 | *val = LIS2DW12_HIGH_PERFORMANCE; |
cparata | 4:94c5d5546161 | 271 | break; |
cparata | 4:94c5d5546161 | 272 | } |
cparata | 2:a94816b14e3d | 273 | } |
cparata | 4:94c5d5546161 | 274 | return ret; |
cparata | 0:dff8803aace7 | 275 | } |
cparata | 0:dff8803aace7 | 276 | |
cparata | 0:dff8803aace7 | 277 | /** |
cparata | 2:a94816b14e3d | 278 | * @brief Accelerometer data rate selection.[set] |
cparata | 0:dff8803aace7 | 279 | * |
cparata | 2:a94816b14e3d | 280 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 281 | * @param val change the values of odr in reg CTRL1 |
cparata | 2:a94816b14e3d | 282 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 283 | * |
cparata | 0:dff8803aace7 | 284 | */ |
cparata | 0:dff8803aace7 | 285 | int32_t lis2dw12_data_rate_set(lis2dw12_ctx_t *ctx, lis2dw12_odr_t val) |
cparata | 0:dff8803aace7 | 286 | { |
cparata | 4:94c5d5546161 | 287 | lis2dw12_ctrl1_t ctrl1; |
cparata | 4:94c5d5546161 | 288 | lis2dw12_ctrl3_t ctrl3; |
cparata | 4:94c5d5546161 | 289 | int32_t ret; |
cparata | 0:dff8803aace7 | 290 | |
cparata | 4:94c5d5546161 | 291 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1); |
cparata | 4:94c5d5546161 | 292 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 293 | ctrl1.odr = (uint8_t) val; |
cparata | 4:94c5d5546161 | 294 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1); |
cparata | 4:94c5d5546161 | 295 | } |
cparata | 4:94c5d5546161 | 296 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 297 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &ctrl3, 1); |
cparata | 4:94c5d5546161 | 298 | } |
cparata | 4:94c5d5546161 | 299 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 300 | ctrl3.slp_mode = ((uint8_t) val & 0x30U) >> 4; |
cparata | 4:94c5d5546161 | 301 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &ctrl3, 1); |
cparata | 4:94c5d5546161 | 302 | } |
cparata | 4:94c5d5546161 | 303 | return ret; |
cparata | 0:dff8803aace7 | 304 | } |
cparata | 0:dff8803aace7 | 305 | |
cparata | 0:dff8803aace7 | 306 | /** |
cparata | 2:a94816b14e3d | 307 | * @brief Accelerometer data rate selection.[get] |
cparata | 0:dff8803aace7 | 308 | * |
cparata | 2:a94816b14e3d | 309 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 310 | * @param val Get the values of odr in reg CTRL1 |
cparata | 2:a94816b14e3d | 311 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 312 | * |
cparata | 0:dff8803aace7 | 313 | */ |
cparata | 0:dff8803aace7 | 314 | int32_t lis2dw12_data_rate_get(lis2dw12_ctx_t *ctx, lis2dw12_odr_t *val) |
cparata | 0:dff8803aace7 | 315 | { |
cparata | 4:94c5d5546161 | 316 | lis2dw12_ctrl1_t ctrl1; |
cparata | 4:94c5d5546161 | 317 | lis2dw12_ctrl3_t ctrl3; |
cparata | 4:94c5d5546161 | 318 | int32_t ret; |
cparata | 4:94c5d5546161 | 319 | |
cparata | 4:94c5d5546161 | 320 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1); |
cparata | 4:94c5d5546161 | 321 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 322 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &ctrl3, 1); |
cparata | 0:dff8803aace7 | 323 | |
cparata | 4:94c5d5546161 | 324 | switch ((ctrl3.slp_mode << 4) + ctrl1.odr) { |
cparata | 4:94c5d5546161 | 325 | case LIS2DW12_XL_ODR_OFF: |
cparata | 4:94c5d5546161 | 326 | *val = LIS2DW12_XL_ODR_OFF; |
cparata | 4:94c5d5546161 | 327 | break; |
cparata | 4:94c5d5546161 | 328 | case LIS2DW12_XL_ODR_1Hz6_LP_ONLY: |
cparata | 4:94c5d5546161 | 329 | *val = LIS2DW12_XL_ODR_1Hz6_LP_ONLY; |
cparata | 4:94c5d5546161 | 330 | break; |
cparata | 4:94c5d5546161 | 331 | case LIS2DW12_XL_ODR_12Hz5: |
cparata | 4:94c5d5546161 | 332 | *val = LIS2DW12_XL_ODR_12Hz5; |
cparata | 4:94c5d5546161 | 333 | break; |
cparata | 4:94c5d5546161 | 334 | case LIS2DW12_XL_ODR_25Hz: |
cparata | 4:94c5d5546161 | 335 | *val = LIS2DW12_XL_ODR_25Hz; |
cparata | 4:94c5d5546161 | 336 | break; |
cparata | 4:94c5d5546161 | 337 | case LIS2DW12_XL_ODR_50Hz: |
cparata | 4:94c5d5546161 | 338 | *val = LIS2DW12_XL_ODR_50Hz; |
cparata | 4:94c5d5546161 | 339 | break; |
cparata | 4:94c5d5546161 | 340 | case LIS2DW12_XL_ODR_100Hz: |
cparata | 4:94c5d5546161 | 341 | *val = LIS2DW12_XL_ODR_100Hz; |
cparata | 4:94c5d5546161 | 342 | break; |
cparata | 4:94c5d5546161 | 343 | case LIS2DW12_XL_ODR_200Hz: |
cparata | 4:94c5d5546161 | 344 | *val = LIS2DW12_XL_ODR_200Hz; |
cparata | 4:94c5d5546161 | 345 | break; |
cparata | 4:94c5d5546161 | 346 | case LIS2DW12_XL_ODR_400Hz: |
cparata | 4:94c5d5546161 | 347 | *val = LIS2DW12_XL_ODR_400Hz; |
cparata | 4:94c5d5546161 | 348 | break; |
cparata | 4:94c5d5546161 | 349 | case LIS2DW12_XL_ODR_800Hz: |
cparata | 4:94c5d5546161 | 350 | *val = LIS2DW12_XL_ODR_800Hz; |
cparata | 4:94c5d5546161 | 351 | break; |
cparata | 4:94c5d5546161 | 352 | case LIS2DW12_XL_ODR_1k6Hz: |
cparata | 4:94c5d5546161 | 353 | *val = LIS2DW12_XL_ODR_1k6Hz; |
cparata | 4:94c5d5546161 | 354 | break; |
cparata | 4:94c5d5546161 | 355 | case LIS2DW12_XL_SET_SW_TRIG: |
cparata | 4:94c5d5546161 | 356 | *val = LIS2DW12_XL_SET_SW_TRIG; |
cparata | 4:94c5d5546161 | 357 | break; |
cparata | 4:94c5d5546161 | 358 | case LIS2DW12_XL_SET_PIN_TRIG: |
cparata | 4:94c5d5546161 | 359 | *val = LIS2DW12_XL_SET_PIN_TRIG; |
cparata | 4:94c5d5546161 | 360 | break; |
cparata | 4:94c5d5546161 | 361 | default: |
cparata | 4:94c5d5546161 | 362 | *val = LIS2DW12_XL_ODR_OFF; |
cparata | 4:94c5d5546161 | 363 | break; |
cparata | 4:94c5d5546161 | 364 | } |
cparata | 2:a94816b14e3d | 365 | } |
cparata | 4:94c5d5546161 | 366 | return ret; |
cparata | 0:dff8803aace7 | 367 | } |
cparata | 0:dff8803aace7 | 368 | |
cparata | 0:dff8803aace7 | 369 | /** |
cparata | 4:94c5d5546161 | 370 | * @brief Block data update.[set] |
cparata | 0:dff8803aace7 | 371 | * |
cparata | 2:a94816b14e3d | 372 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 373 | * @param val change the values of bdu in reg CTRL2 |
cparata | 2:a94816b14e3d | 374 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 375 | * |
cparata | 0:dff8803aace7 | 376 | */ |
cparata | 0:dff8803aace7 | 377 | int32_t lis2dw12_block_data_update_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 378 | { |
cparata | 4:94c5d5546161 | 379 | lis2dw12_ctrl2_t reg; |
cparata | 4:94c5d5546161 | 380 | int32_t ret; |
cparata | 0:dff8803aace7 | 381 | |
cparata | 4:94c5d5546161 | 382 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 383 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 384 | reg.bdu = val; |
cparata | 4:94c5d5546161 | 385 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 386 | } |
cparata | 4:94c5d5546161 | 387 | return ret; |
cparata | 0:dff8803aace7 | 388 | } |
cparata | 0:dff8803aace7 | 389 | |
cparata | 0:dff8803aace7 | 390 | /** |
cparata | 2:a94816b14e3d | 391 | * @brief Block data update.[get] |
cparata | 0:dff8803aace7 | 392 | * |
cparata | 2:a94816b14e3d | 393 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 394 | * @param val change the values of bdu in reg CTRL2 |
cparata | 2:a94816b14e3d | 395 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 396 | * |
cparata | 0:dff8803aace7 | 397 | */ |
cparata | 0:dff8803aace7 | 398 | int32_t lis2dw12_block_data_update_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 399 | { |
cparata | 4:94c5d5546161 | 400 | lis2dw12_ctrl2_t reg; |
cparata | 4:94c5d5546161 | 401 | int32_t ret; |
cparata | 0:dff8803aace7 | 402 | |
cparata | 4:94c5d5546161 | 403 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 404 | *val = reg.bdu; |
cparata | 0:dff8803aace7 | 405 | |
cparata | 4:94c5d5546161 | 406 | return ret; |
cparata | 0:dff8803aace7 | 407 | } |
cparata | 0:dff8803aace7 | 408 | |
cparata | 0:dff8803aace7 | 409 | /** |
cparata | 2:a94816b14e3d | 410 | * @brief Accelerometer full-scale selection.[set] |
cparata | 0:dff8803aace7 | 411 | * |
cparata | 2:a94816b14e3d | 412 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 413 | * @param val change the values of fs in reg CTRL6 |
cparata | 2:a94816b14e3d | 414 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 415 | * |
cparata | 0:dff8803aace7 | 416 | */ |
cparata | 0:dff8803aace7 | 417 | int32_t lis2dw12_full_scale_set(lis2dw12_ctx_t *ctx, lis2dw12_fs_t val) |
cparata | 0:dff8803aace7 | 418 | { |
cparata | 4:94c5d5546161 | 419 | lis2dw12_ctrl6_t reg; |
cparata | 4:94c5d5546161 | 420 | int32_t ret; |
cparata | 0:dff8803aace7 | 421 | |
cparata | 4:94c5d5546161 | 422 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 423 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 424 | reg.fs = (uint8_t) val; |
cparata | 4:94c5d5546161 | 425 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 426 | } |
cparata | 4:94c5d5546161 | 427 | return ret; |
cparata | 0:dff8803aace7 | 428 | } |
cparata | 0:dff8803aace7 | 429 | |
cparata | 0:dff8803aace7 | 430 | /** |
cparata | 2:a94816b14e3d | 431 | * @brief Accelerometer full-scale selection.[get] |
cparata | 0:dff8803aace7 | 432 | * |
cparata | 2:a94816b14e3d | 433 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 434 | * @param val Get the values of fs in reg CTRL6 |
cparata | 2:a94816b14e3d | 435 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 436 | * |
cparata | 0:dff8803aace7 | 437 | */ |
cparata | 0:dff8803aace7 | 438 | int32_t lis2dw12_full_scale_get(lis2dw12_ctx_t *ctx, lis2dw12_fs_t *val) |
cparata | 0:dff8803aace7 | 439 | { |
cparata | 4:94c5d5546161 | 440 | lis2dw12_ctrl6_t reg; |
cparata | 4:94c5d5546161 | 441 | int32_t ret; |
cparata | 2:a94816b14e3d | 442 | |
cparata | 4:94c5d5546161 | 443 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) ®, 1); |
cparata | 0:dff8803aace7 | 444 | |
cparata | 4:94c5d5546161 | 445 | switch (reg.fs) { |
cparata | 4:94c5d5546161 | 446 | case LIS2DW12_2g: |
cparata | 4:94c5d5546161 | 447 | *val = LIS2DW12_2g; |
cparata | 4:94c5d5546161 | 448 | break; |
cparata | 4:94c5d5546161 | 449 | case LIS2DW12_4g: |
cparata | 4:94c5d5546161 | 450 | *val = LIS2DW12_4g; |
cparata | 4:94c5d5546161 | 451 | break; |
cparata | 4:94c5d5546161 | 452 | case LIS2DW12_8g: |
cparata | 4:94c5d5546161 | 453 | *val = LIS2DW12_8g; |
cparata | 4:94c5d5546161 | 454 | break; |
cparata | 4:94c5d5546161 | 455 | case LIS2DW12_16g: |
cparata | 4:94c5d5546161 | 456 | *val = LIS2DW12_16g; |
cparata | 4:94c5d5546161 | 457 | break; |
cparata | 4:94c5d5546161 | 458 | default: |
cparata | 4:94c5d5546161 | 459 | *val = LIS2DW12_2g; |
cparata | 4:94c5d5546161 | 460 | break; |
cparata | 4:94c5d5546161 | 461 | } |
cparata | 4:94c5d5546161 | 462 | return ret; |
cparata | 0:dff8803aace7 | 463 | } |
cparata | 0:dff8803aace7 | 464 | |
cparata | 0:dff8803aace7 | 465 | /** |
cparata | 2:a94816b14e3d | 466 | * @brief The STATUS_REG register of the device.[get] |
cparata | 0:dff8803aace7 | 467 | * |
cparata | 2:a94816b14e3d | 468 | * @param ctx read / write interface definitions |
cparata | 4:94c5d5546161 | 469 | * @param val union of registers from STATUS to |
cparata | 2:a94816b14e3d | 470 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 471 | * |
cparata | 0:dff8803aace7 | 472 | */ |
cparata | 0:dff8803aace7 | 473 | int32_t lis2dw12_status_reg_get(lis2dw12_ctx_t *ctx, lis2dw12_status_t *val) |
cparata | 0:dff8803aace7 | 474 | { |
cparata | 4:94c5d5546161 | 475 | int32_t ret; |
cparata | 4:94c5d5546161 | 476 | ret = lis2dw12_read_reg(ctx, LIS2DW12_STATUS, (uint8_t *) val, 1); |
cparata | 4:94c5d5546161 | 477 | return ret; |
cparata | 0:dff8803aace7 | 478 | } |
cparata | 2:a94816b14e3d | 479 | |
cparata | 0:dff8803aace7 | 480 | /** |
cparata | 2:a94816b14e3d | 481 | * @brief Accelerometer new data available.[get] |
cparata | 0:dff8803aace7 | 482 | * |
cparata | 2:a94816b14e3d | 483 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 484 | * @param val change the values of drdy in reg STATUS |
cparata | 2:a94816b14e3d | 485 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 486 | * |
cparata | 0:dff8803aace7 | 487 | */ |
cparata | 0:dff8803aace7 | 488 | int32_t lis2dw12_flag_data_ready_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 489 | { |
cparata | 4:94c5d5546161 | 490 | lis2dw12_status_t reg; |
cparata | 4:94c5d5546161 | 491 | int32_t ret; |
cparata | 0:dff8803aace7 | 492 | |
cparata | 4:94c5d5546161 | 493 | ret = lis2dw12_read_reg(ctx, LIS2DW12_STATUS, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 494 | *val = reg.drdy; |
cparata | 0:dff8803aace7 | 495 | |
cparata | 4:94c5d5546161 | 496 | return ret; |
cparata | 0:dff8803aace7 | 497 | } |
cparata | 0:dff8803aace7 | 498 | /** |
cparata | 2:a94816b14e3d | 499 | * @brief Read all the interrupt/status flag of the device.[get] |
cparata | 4:94c5d5546161 | 500 | * |
cparata | 2:a94816b14e3d | 501 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 502 | * @param val registers STATUS_DUP, WAKE_UP_SRC, |
cparata | 2:a94816b14e3d | 503 | * TAP_SRC, SIXD_SRC, ALL_INT_SRC |
cparata | 2:a94816b14e3d | 504 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 505 | * |
cparata | 0:dff8803aace7 | 506 | */ |
cparata | 0:dff8803aace7 | 507 | int32_t lis2dw12_all_sources_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 508 | lis2dw12_all_sources_t *val) |
cparata | 0:dff8803aace7 | 509 | { |
cparata | 4:94c5d5546161 | 510 | int32_t ret; |
cparata | 4:94c5d5546161 | 511 | ret = lis2dw12_read_reg(ctx, LIS2DW12_STATUS_DUP, (uint8_t *) val, 5); |
cparata | 4:94c5d5546161 | 512 | return ret; |
cparata | 0:dff8803aace7 | 513 | } |
cparata | 2:a94816b14e3d | 514 | |
cparata | 0:dff8803aace7 | 515 | /** |
cparata | 4:94c5d5546161 | 516 | * @brief Accelerometer X-axis user offset correction expressed in two’s |
cparata | 2:a94816b14e3d | 517 | * complement, weight depends on bit USR_OFF_W. The value must be |
cparata | 4:94c5d5546161 | 518 | * in the range [-127 127].[set] |
cparata | 0:dff8803aace7 | 519 | * |
cparata | 2:a94816b14e3d | 520 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 521 | * @param buff buffer that contains data to write |
cparata | 2:a94816b14e3d | 522 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 523 | * |
cparata | 0:dff8803aace7 | 524 | */ |
cparata | 0:dff8803aace7 | 525 | int32_t lis2dw12_usr_offset_x_set(lis2dw12_ctx_t *ctx, uint8_t *buff) |
cparata | 0:dff8803aace7 | 526 | { |
cparata | 4:94c5d5546161 | 527 | int32_t ret; |
cparata | 4:94c5d5546161 | 528 | ret = lis2dw12_write_reg(ctx, LIS2DW12_X_OFS_USR, buff, 1); |
cparata | 4:94c5d5546161 | 529 | return ret; |
cparata | 0:dff8803aace7 | 530 | } |
cparata | 0:dff8803aace7 | 531 | |
cparata | 0:dff8803aace7 | 532 | /** |
cparata | 4:94c5d5546161 | 533 | * @brief Accelerometer X-axis user offset correction expressed in two’s |
cparata | 2:a94816b14e3d | 534 | * complement, weight depends on bit USR_OFF_W. The value must be |
cparata | 4:94c5d5546161 | 535 | * in the range [-127 127].[get] |
cparata | 0:dff8803aace7 | 536 | * |
cparata | 2:a94816b14e3d | 537 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 538 | * @param buff buffer that stores data read |
cparata | 2:a94816b14e3d | 539 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 540 | * |
cparata | 0:dff8803aace7 | 541 | */ |
cparata | 0:dff8803aace7 | 542 | int32_t lis2dw12_usr_offset_x_get(lis2dw12_ctx_t *ctx, uint8_t *buff) |
cparata | 0:dff8803aace7 | 543 | { |
cparata | 4:94c5d5546161 | 544 | int32_t ret; |
cparata | 4:94c5d5546161 | 545 | ret = lis2dw12_read_reg(ctx, LIS2DW12_X_OFS_USR, buff, 1); |
cparata | 4:94c5d5546161 | 546 | return ret; |
cparata | 0:dff8803aace7 | 547 | } |
cparata | 2:a94816b14e3d | 548 | |
cparata | 0:dff8803aace7 | 549 | /** |
cparata | 4:94c5d5546161 | 550 | * @brief Accelerometer Y-axis user offset correction expressed in two’s |
cparata | 2:a94816b14e3d | 551 | * complement, weight depends on bit USR_OFF_W. The value must be |
cparata | 4:94c5d5546161 | 552 | * in the range [-127 127].[set] |
cparata | 0:dff8803aace7 | 553 | * |
cparata | 2:a94816b14e3d | 554 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 555 | * @param buff buffer that contains data to write |
cparata | 2:a94816b14e3d | 556 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 557 | * |
cparata | 0:dff8803aace7 | 558 | */ |
cparata | 0:dff8803aace7 | 559 | int32_t lis2dw12_usr_offset_y_set(lis2dw12_ctx_t *ctx, uint8_t *buff) |
cparata | 0:dff8803aace7 | 560 | { |
cparata | 4:94c5d5546161 | 561 | int32_t ret; |
cparata | 4:94c5d5546161 | 562 | ret = lis2dw12_write_reg(ctx, LIS2DW12_Y_OFS_USR, buff, 1); |
cparata | 4:94c5d5546161 | 563 | return ret; |
cparata | 0:dff8803aace7 | 564 | } |
cparata | 0:dff8803aace7 | 565 | |
cparata | 0:dff8803aace7 | 566 | /** |
cparata | 4:94c5d5546161 | 567 | * @brief Accelerometer Y-axis user offset correction expressed in two’s |
cparata | 2:a94816b14e3d | 568 | * complement, weight depends on bit USR_OFF_W. The value must be |
cparata | 4:94c5d5546161 | 569 | * in the range [-127 127].[get] |
cparata | 0:dff8803aace7 | 570 | * |
cparata | 2:a94816b14e3d | 571 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 572 | * @param buff buffer that stores data read |
cparata | 2:a94816b14e3d | 573 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 574 | * |
cparata | 0:dff8803aace7 | 575 | */ |
cparata | 0:dff8803aace7 | 576 | int32_t lis2dw12_usr_offset_y_get(lis2dw12_ctx_t *ctx, uint8_t *buff) |
cparata | 0:dff8803aace7 | 577 | { |
cparata | 4:94c5d5546161 | 578 | int32_t ret; |
cparata | 4:94c5d5546161 | 579 | ret = lis2dw12_read_reg(ctx, LIS2DW12_Y_OFS_USR, buff, 1); |
cparata | 4:94c5d5546161 | 580 | return ret; |
cparata | 0:dff8803aace7 | 581 | } |
cparata | 2:a94816b14e3d | 582 | |
cparata | 0:dff8803aace7 | 583 | /** |
cparata | 4:94c5d5546161 | 584 | * @brief Accelerometer Z-axis user offset correction expressed in two’s |
cparata | 2:a94816b14e3d | 585 | * complement, weight depends on bit USR_OFF_W. The value must be |
cparata | 4:94c5d5546161 | 586 | * in the range [-127 127].[set] |
cparata | 0:dff8803aace7 | 587 | * |
cparata | 2:a94816b14e3d | 588 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 589 | * @param buff buffer that contains data to write |
cparata | 2:a94816b14e3d | 590 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 591 | * |
cparata | 0:dff8803aace7 | 592 | */ |
cparata | 0:dff8803aace7 | 593 | int32_t lis2dw12_usr_offset_z_set(lis2dw12_ctx_t *ctx, uint8_t *buff) |
cparata | 0:dff8803aace7 | 594 | { |
cparata | 4:94c5d5546161 | 595 | int32_t ret; |
cparata | 4:94c5d5546161 | 596 | ret = lis2dw12_write_reg(ctx, LIS2DW12_Z_OFS_USR, buff, 1); |
cparata | 4:94c5d5546161 | 597 | return ret; |
cparata | 0:dff8803aace7 | 598 | } |
cparata | 0:dff8803aace7 | 599 | |
cparata | 0:dff8803aace7 | 600 | /** |
cparata | 4:94c5d5546161 | 601 | * @brief Accelerometer Z-axis user offset correction expressed in two’s |
cparata | 2:a94816b14e3d | 602 | * complement, weight depends on bit USR_OFF_W. The value must be |
cparata | 4:94c5d5546161 | 603 | * in the range [-127 127].[get] |
cparata | 0:dff8803aace7 | 604 | * |
cparata | 2:a94816b14e3d | 605 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 606 | * @param buff buffer that stores data read |
cparata | 2:a94816b14e3d | 607 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 608 | * |
cparata | 0:dff8803aace7 | 609 | */ |
cparata | 0:dff8803aace7 | 610 | int32_t lis2dw12_usr_offset_z_get(lis2dw12_ctx_t *ctx, uint8_t *buff) |
cparata | 0:dff8803aace7 | 611 | { |
cparata | 4:94c5d5546161 | 612 | int32_t ret; |
cparata | 4:94c5d5546161 | 613 | ret = lis2dw12_read_reg(ctx, LIS2DW12_Z_OFS_USR, buff, 1); |
cparata | 4:94c5d5546161 | 614 | return ret; |
cparata | 0:dff8803aace7 | 615 | } |
cparata | 2:a94816b14e3d | 616 | |
cparata | 0:dff8803aace7 | 617 | /** |
cparata | 4:94c5d5546161 | 618 | * @brief Weight of XL user offset bits of registers X_OFS_USR, |
cparata | 2:a94816b14e3d | 619 | * Y_OFS_USR, Z_OFS_USR.[set] |
cparata | 0:dff8803aace7 | 620 | * |
cparata | 2:a94816b14e3d | 621 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 622 | * @param val change the values of usr_off_w in |
cparata | 0:dff8803aace7 | 623 | * reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 624 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 625 | * |
cparata | 0:dff8803aace7 | 626 | */ |
cparata | 0:dff8803aace7 | 627 | int32_t lis2dw12_offset_weight_set(lis2dw12_ctx_t *ctx, |
cparata | 2:a94816b14e3d | 628 | lis2dw12_usr_off_w_t val) |
cparata | 0:dff8803aace7 | 629 | { |
cparata | 4:94c5d5546161 | 630 | lis2dw12_ctrl_reg7_t reg; |
cparata | 4:94c5d5546161 | 631 | int32_t ret; |
cparata | 0:dff8803aace7 | 632 | |
cparata | 4:94c5d5546161 | 633 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 634 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 635 | reg.usr_off_w = (uint8_t) val; |
cparata | 4:94c5d5546161 | 636 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 637 | } |
cparata | 4:94c5d5546161 | 638 | return ret; |
cparata | 0:dff8803aace7 | 639 | } |
cparata | 0:dff8803aace7 | 640 | |
cparata | 0:dff8803aace7 | 641 | /** |
cparata | 4:94c5d5546161 | 642 | * @brief Weight of XL user offset bits of registers X_OFS_USR, |
cparata | 2:a94816b14e3d | 643 | * Y_OFS_USR, Z_OFS_USR.[get] |
cparata | 0:dff8803aace7 | 644 | * |
cparata | 2:a94816b14e3d | 645 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 646 | * @param val Get the values of usr_off_w in reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 647 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 648 | * |
cparata | 0:dff8803aace7 | 649 | */ |
cparata | 0:dff8803aace7 | 650 | int32_t lis2dw12_offset_weight_get(lis2dw12_ctx_t *ctx, |
cparata | 2:a94816b14e3d | 651 | lis2dw12_usr_off_w_t *val) |
cparata | 0:dff8803aace7 | 652 | { |
cparata | 4:94c5d5546161 | 653 | lis2dw12_ctrl_reg7_t reg; |
cparata | 4:94c5d5546161 | 654 | int32_t ret; |
cparata | 0:dff8803aace7 | 655 | |
cparata | 4:94c5d5546161 | 656 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 657 | switch (reg.usr_off_w) { |
cparata | 4:94c5d5546161 | 658 | case LIS2DW12_LSb_977ug: |
cparata | 4:94c5d5546161 | 659 | *val = LIS2DW12_LSb_977ug; |
cparata | 4:94c5d5546161 | 660 | break; |
cparata | 4:94c5d5546161 | 661 | case LIS2DW12_LSb_15mg6: |
cparata | 4:94c5d5546161 | 662 | *val = LIS2DW12_LSb_15mg6; |
cparata | 4:94c5d5546161 | 663 | break; |
cparata | 4:94c5d5546161 | 664 | default: |
cparata | 4:94c5d5546161 | 665 | *val = LIS2DW12_LSb_977ug; |
cparata | 4:94c5d5546161 | 666 | break; |
cparata | 4:94c5d5546161 | 667 | } |
cparata | 4:94c5d5546161 | 668 | return ret; |
cparata | 0:dff8803aace7 | 669 | } |
cparata | 0:dff8803aace7 | 670 | |
cparata | 0:dff8803aace7 | 671 | /** |
cparata | 0:dff8803aace7 | 672 | * @} |
cparata | 2:a94816b14e3d | 673 | * |
cparata | 0:dff8803aace7 | 674 | */ |
cparata | 0:dff8803aace7 | 675 | |
cparata | 0:dff8803aace7 | 676 | /** |
cparata | 2:a94816b14e3d | 677 | * @defgroup LIS2DW12_Data_Output |
cparata | 2:a94816b14e3d | 678 | * @brief This section groups all the data output functions. |
cparata | 0:dff8803aace7 | 679 | * @{ |
cparata | 2:a94816b14e3d | 680 | * |
cparata | 0:dff8803aace7 | 681 | */ |
cparata | 0:dff8803aace7 | 682 | |
cparata | 0:dff8803aace7 | 683 | /** |
cparata | 4:94c5d5546161 | 684 | * @brief Temperature data output register (r). L and H registers |
cparata | 2:a94816b14e3d | 685 | * together express a 16-bit word in two’s complement.[get] |
cparata | 0:dff8803aace7 | 686 | * |
cparata | 2:a94816b14e3d | 687 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 688 | * @param buff buffer that stores data read |
cparata | 2:a94816b14e3d | 689 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 690 | * |
cparata | 0:dff8803aace7 | 691 | */ |
cparata | 0:dff8803aace7 | 692 | int32_t lis2dw12_temperature_raw_get(lis2dw12_ctx_t *ctx, uint8_t *buff) |
cparata | 0:dff8803aace7 | 693 | { |
cparata | 4:94c5d5546161 | 694 | int32_t ret; |
cparata | 4:94c5d5546161 | 695 | ret = lis2dw12_read_reg(ctx, LIS2DW12_OUT_T_L, buff, 2); |
cparata | 4:94c5d5546161 | 696 | return ret; |
cparata | 0:dff8803aace7 | 697 | } |
cparata | 0:dff8803aace7 | 698 | |
cparata | 0:dff8803aace7 | 699 | /** |
cparata | 4:94c5d5546161 | 700 | * @brief Linear acceleration output register. The value is expressed as |
cparata | 2:a94816b14e3d | 701 | * a 16-bit word in two’s complement.[get] |
cparata | 0:dff8803aace7 | 702 | * |
cparata | 2:a94816b14e3d | 703 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 704 | * @param buff buffer that stores data read |
cparata | 2:a94816b14e3d | 705 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 706 | * |
cparata | 0:dff8803aace7 | 707 | */ |
cparata | 0:dff8803aace7 | 708 | int32_t lis2dw12_acceleration_raw_get(lis2dw12_ctx_t *ctx, uint8_t *buff) |
cparata | 0:dff8803aace7 | 709 | { |
cparata | 4:94c5d5546161 | 710 | int32_t ret; |
cparata | 4:94c5d5546161 | 711 | ret = lis2dw12_read_reg(ctx, LIS2DW12_OUT_X_L, buff, 6); |
cparata | 4:94c5d5546161 | 712 | return ret; |
cparata | 0:dff8803aace7 | 713 | } |
cparata | 0:dff8803aace7 | 714 | |
cparata | 0:dff8803aace7 | 715 | /** |
cparata | 0:dff8803aace7 | 716 | * @} |
cparata | 2:a94816b14e3d | 717 | * |
cparata | 0:dff8803aace7 | 718 | */ |
cparata | 0:dff8803aace7 | 719 | |
cparata | 0:dff8803aace7 | 720 | /** |
cparata | 2:a94816b14e3d | 721 | * @defgroup LIS2DW12_Common |
cparata | 2:a94816b14e3d | 722 | * @brief This section groups common useful functions. |
cparata | 0:dff8803aace7 | 723 | * @{ |
cparata | 2:a94816b14e3d | 724 | * |
cparata | 0:dff8803aace7 | 725 | */ |
cparata | 0:dff8803aace7 | 726 | |
cparata | 0:dff8803aace7 | 727 | /** |
cparata | 2:a94816b14e3d | 728 | * @brief Device Who am I.[get] |
cparata | 0:dff8803aace7 | 729 | * |
cparata | 2:a94816b14e3d | 730 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 731 | * @param buff buffer that stores data read |
cparata | 2:a94816b14e3d | 732 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 733 | * |
cparata | 0:dff8803aace7 | 734 | */ |
cparata | 0:dff8803aace7 | 735 | int32_t lis2dw12_device_id_get(lis2dw12_ctx_t *ctx, uint8_t *buff) |
cparata | 0:dff8803aace7 | 736 | { |
cparata | 4:94c5d5546161 | 737 | int32_t ret; |
cparata | 4:94c5d5546161 | 738 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WHO_AM_I, buff, 1); |
cparata | 4:94c5d5546161 | 739 | return ret; |
cparata | 0:dff8803aace7 | 740 | } |
cparata | 0:dff8803aace7 | 741 | |
cparata | 0:dff8803aace7 | 742 | /** |
cparata | 4:94c5d5546161 | 743 | * @brief Register address automatically incremented during multiple byte |
cparata | 2:a94816b14e3d | 744 | * access with a serial interface.[set] |
cparata | 0:dff8803aace7 | 745 | * |
cparata | 2:a94816b14e3d | 746 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 747 | * @param val change the values of if_add_inc in reg CTRL2 |
cparata | 2:a94816b14e3d | 748 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 749 | * |
cparata | 0:dff8803aace7 | 750 | */ |
cparata | 0:dff8803aace7 | 751 | int32_t lis2dw12_auto_increment_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 752 | { |
cparata | 4:94c5d5546161 | 753 | lis2dw12_ctrl2_t reg; |
cparata | 4:94c5d5546161 | 754 | int32_t ret; |
cparata | 0:dff8803aace7 | 755 | |
cparata | 4:94c5d5546161 | 756 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 757 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 758 | reg.if_add_inc = val; |
cparata | 4:94c5d5546161 | 759 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 760 | } |
cparata | 4:94c5d5546161 | 761 | return ret; |
cparata | 0:dff8803aace7 | 762 | } |
cparata | 0:dff8803aace7 | 763 | |
cparata | 0:dff8803aace7 | 764 | /** |
cparata | 4:94c5d5546161 | 765 | * @brief Register address automatically incremented during multiple |
cparata | 2:a94816b14e3d | 766 | * byte access with a serial interface.[get] |
cparata | 0:dff8803aace7 | 767 | * |
cparata | 2:a94816b14e3d | 768 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 769 | * @param val change the values of if_add_inc in reg CTRL2 |
cparata | 2:a94816b14e3d | 770 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 771 | * |
cparata | 0:dff8803aace7 | 772 | */ |
cparata | 0:dff8803aace7 | 773 | int32_t lis2dw12_auto_increment_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 774 | { |
cparata | 4:94c5d5546161 | 775 | lis2dw12_ctrl2_t reg; |
cparata | 4:94c5d5546161 | 776 | int32_t ret; |
cparata | 0:dff8803aace7 | 777 | |
cparata | 4:94c5d5546161 | 778 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 779 | *val = reg.if_add_inc; |
cparata | 0:dff8803aace7 | 780 | |
cparata | 4:94c5d5546161 | 781 | return ret; |
cparata | 0:dff8803aace7 | 782 | } |
cparata | 0:dff8803aace7 | 783 | |
cparata | 0:dff8803aace7 | 784 | /** |
cparata | 2:a94816b14e3d | 785 | * @brief Software reset. Restore the default values in user registers.[set] |
cparata | 0:dff8803aace7 | 786 | * |
cparata | 2:a94816b14e3d | 787 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 788 | * @param val change the values of soft_reset in reg CTRL2 |
cparata | 2:a94816b14e3d | 789 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 790 | * |
cparata | 0:dff8803aace7 | 791 | */ |
cparata | 0:dff8803aace7 | 792 | int32_t lis2dw12_reset_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 793 | { |
cparata | 4:94c5d5546161 | 794 | lis2dw12_ctrl2_t reg; |
cparata | 4:94c5d5546161 | 795 | int32_t ret; |
cparata | 0:dff8803aace7 | 796 | |
cparata | 4:94c5d5546161 | 797 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 798 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 799 | reg.soft_reset = val; |
cparata | 4:94c5d5546161 | 800 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 801 | } |
cparata | 0:dff8803aace7 | 802 | |
cparata | 4:94c5d5546161 | 803 | return ret; |
cparata | 0:dff8803aace7 | 804 | } |
cparata | 0:dff8803aace7 | 805 | |
cparata | 0:dff8803aace7 | 806 | /** |
cparata | 2:a94816b14e3d | 807 | * @brief Software reset. Restore the default values in user registers.[get] |
cparata | 0:dff8803aace7 | 808 | * |
cparata | 2:a94816b14e3d | 809 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 810 | * @param val change the values of soft_reset in reg CTRL2 |
cparata | 2:a94816b14e3d | 811 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 812 | * |
cparata | 0:dff8803aace7 | 813 | */ |
cparata | 0:dff8803aace7 | 814 | int32_t lis2dw12_reset_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 815 | { |
cparata | 4:94c5d5546161 | 816 | lis2dw12_ctrl2_t reg; |
cparata | 4:94c5d5546161 | 817 | int32_t ret; |
cparata | 0:dff8803aace7 | 818 | |
cparata | 4:94c5d5546161 | 819 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 820 | *val = reg.soft_reset; |
cparata | 0:dff8803aace7 | 821 | |
cparata | 4:94c5d5546161 | 822 | return ret; |
cparata | 0:dff8803aace7 | 823 | } |
cparata | 0:dff8803aace7 | 824 | |
cparata | 0:dff8803aace7 | 825 | /** |
cparata | 2:a94816b14e3d | 826 | * @brief Reboot memory content. Reload the calibration parameters.[set] |
cparata | 0:dff8803aace7 | 827 | * |
cparata | 2:a94816b14e3d | 828 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 829 | * @param val change the values of boot in reg CTRL2 |
cparata | 2:a94816b14e3d | 830 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 831 | * |
cparata | 0:dff8803aace7 | 832 | */ |
cparata | 0:dff8803aace7 | 833 | int32_t lis2dw12_boot_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 834 | { |
cparata | 4:94c5d5546161 | 835 | lis2dw12_ctrl2_t reg; |
cparata | 4:94c5d5546161 | 836 | int32_t ret; |
cparata | 0:dff8803aace7 | 837 | |
cparata | 4:94c5d5546161 | 838 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 839 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 840 | reg.boot = val; |
cparata | 4:94c5d5546161 | 841 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 842 | } |
cparata | 4:94c5d5546161 | 843 | return ret; |
cparata | 0:dff8803aace7 | 844 | } |
cparata | 0:dff8803aace7 | 845 | |
cparata | 0:dff8803aace7 | 846 | /** |
cparata | 2:a94816b14e3d | 847 | * @brief Reboot memory content. Reload the calibration parameters.[get] |
cparata | 0:dff8803aace7 | 848 | * |
cparata | 2:a94816b14e3d | 849 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 850 | * @param val change the values of boot in reg CTRL2 |
cparata | 2:a94816b14e3d | 851 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 852 | * |
cparata | 0:dff8803aace7 | 853 | */ |
cparata | 0:dff8803aace7 | 854 | int32_t lis2dw12_boot_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 855 | { |
cparata | 4:94c5d5546161 | 856 | lis2dw12_ctrl2_t reg; |
cparata | 4:94c5d5546161 | 857 | int32_t ret; |
cparata | 0:dff8803aace7 | 858 | |
cparata | 4:94c5d5546161 | 859 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 860 | *val = reg.boot; |
cparata | 0:dff8803aace7 | 861 | |
cparata | 4:94c5d5546161 | 862 | return ret; |
cparata | 0:dff8803aace7 | 863 | } |
cparata | 0:dff8803aace7 | 864 | |
cparata | 0:dff8803aace7 | 865 | /** |
cparata | 4:94c5d5546161 | 866 | * @brief Sensor self-test enable.[set] |
cparata | 0:dff8803aace7 | 867 | * |
cparata | 2:a94816b14e3d | 868 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 869 | * @param val change the values of st in reg CTRL3 |
cparata | 2:a94816b14e3d | 870 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 871 | * |
cparata | 0:dff8803aace7 | 872 | */ |
cparata | 0:dff8803aace7 | 873 | int32_t lis2dw12_self_test_set(lis2dw12_ctx_t *ctx, lis2dw12_st_t val) |
cparata | 0:dff8803aace7 | 874 | { |
cparata | 4:94c5d5546161 | 875 | lis2dw12_ctrl3_t reg; |
cparata | 4:94c5d5546161 | 876 | int32_t ret; |
cparata | 0:dff8803aace7 | 877 | |
cparata | 4:94c5d5546161 | 878 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 879 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 880 | reg.st = (uint8_t) val; |
cparata | 4:94c5d5546161 | 881 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 882 | } |
cparata | 0:dff8803aace7 | 883 | |
cparata | 4:94c5d5546161 | 884 | return ret; |
cparata | 0:dff8803aace7 | 885 | } |
cparata | 0:dff8803aace7 | 886 | |
cparata | 0:dff8803aace7 | 887 | /** |
cparata | 2:a94816b14e3d | 888 | * @brief Sensor self-test enable.[get] |
cparata | 0:dff8803aace7 | 889 | * |
cparata | 2:a94816b14e3d | 890 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 891 | * @param val Get the values of st in reg CTRL3 |
cparata | 2:a94816b14e3d | 892 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 893 | * |
cparata | 0:dff8803aace7 | 894 | */ |
cparata | 0:dff8803aace7 | 895 | int32_t lis2dw12_self_test_get(lis2dw12_ctx_t *ctx, lis2dw12_st_t *val) |
cparata | 0:dff8803aace7 | 896 | { |
cparata | 4:94c5d5546161 | 897 | lis2dw12_ctrl3_t reg; |
cparata | 4:94c5d5546161 | 898 | int32_t ret; |
cparata | 2:a94816b14e3d | 899 | |
cparata | 4:94c5d5546161 | 900 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1); |
cparata | 0:dff8803aace7 | 901 | |
cparata | 4:94c5d5546161 | 902 | switch (reg.st) { |
cparata | 4:94c5d5546161 | 903 | case LIS2DW12_XL_ST_DISABLE: |
cparata | 4:94c5d5546161 | 904 | *val = LIS2DW12_XL_ST_DISABLE; |
cparata | 4:94c5d5546161 | 905 | break; |
cparata | 4:94c5d5546161 | 906 | case LIS2DW12_XL_ST_POSITIVE: |
cparata | 4:94c5d5546161 | 907 | *val = LIS2DW12_XL_ST_POSITIVE; |
cparata | 4:94c5d5546161 | 908 | break; |
cparata | 4:94c5d5546161 | 909 | case LIS2DW12_XL_ST_NEGATIVE: |
cparata | 4:94c5d5546161 | 910 | *val = LIS2DW12_XL_ST_NEGATIVE; |
cparata | 4:94c5d5546161 | 911 | break; |
cparata | 4:94c5d5546161 | 912 | default: |
cparata | 4:94c5d5546161 | 913 | *val = LIS2DW12_XL_ST_DISABLE; |
cparata | 4:94c5d5546161 | 914 | break; |
cparata | 4:94c5d5546161 | 915 | } |
cparata | 4:94c5d5546161 | 916 | return ret; |
cparata | 0:dff8803aace7 | 917 | } |
cparata | 0:dff8803aace7 | 918 | |
cparata | 0:dff8803aace7 | 919 | /** |
cparata | 2:a94816b14e3d | 920 | * @brief Data-ready pulsed / letched mode.[set] |
cparata | 0:dff8803aace7 | 921 | * |
cparata | 2:a94816b14e3d | 922 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 923 | * @param val change the values of drdy_pulsed in reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 924 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 925 | * |
cparata | 0:dff8803aace7 | 926 | */ |
cparata | 0:dff8803aace7 | 927 | int32_t lis2dw12_data_ready_mode_set(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 928 | lis2dw12_drdy_pulsed_t val) |
cparata | 0:dff8803aace7 | 929 | { |
cparata | 4:94c5d5546161 | 930 | lis2dw12_ctrl_reg7_t reg; |
cparata | 4:94c5d5546161 | 931 | int32_t ret; |
cparata | 0:dff8803aace7 | 932 | |
cparata | 4:94c5d5546161 | 933 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 934 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 935 | reg.drdy_pulsed = (uint8_t) val; |
cparata | 4:94c5d5546161 | 936 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 937 | } |
cparata | 0:dff8803aace7 | 938 | |
cparata | 4:94c5d5546161 | 939 | return ret; |
cparata | 0:dff8803aace7 | 940 | } |
cparata | 0:dff8803aace7 | 941 | |
cparata | 0:dff8803aace7 | 942 | /** |
cparata | 2:a94816b14e3d | 943 | * @brief Data-ready pulsed / letched mode.[get] |
cparata | 0:dff8803aace7 | 944 | * |
cparata | 2:a94816b14e3d | 945 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 946 | * @param val Get the values of drdy_pulsed in reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 947 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 948 | * |
cparata | 0:dff8803aace7 | 949 | */ |
cparata | 0:dff8803aace7 | 950 | int32_t lis2dw12_data_ready_mode_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 951 | lis2dw12_drdy_pulsed_t *val) |
cparata | 0:dff8803aace7 | 952 | { |
cparata | 4:94c5d5546161 | 953 | lis2dw12_ctrl_reg7_t reg; |
cparata | 4:94c5d5546161 | 954 | int32_t ret; |
cparata | 2:a94816b14e3d | 955 | |
cparata | 4:94c5d5546161 | 956 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); |
cparata | 0:dff8803aace7 | 957 | |
cparata | 4:94c5d5546161 | 958 | switch (reg.drdy_pulsed) { |
cparata | 4:94c5d5546161 | 959 | case LIS2DW12_DRDY_LATCHED: |
cparata | 4:94c5d5546161 | 960 | *val = LIS2DW12_DRDY_LATCHED; |
cparata | 4:94c5d5546161 | 961 | break; |
cparata | 4:94c5d5546161 | 962 | case LIS2DW12_DRDY_PULSED: |
cparata | 4:94c5d5546161 | 963 | *val = LIS2DW12_DRDY_PULSED; |
cparata | 4:94c5d5546161 | 964 | break; |
cparata | 4:94c5d5546161 | 965 | default: |
cparata | 4:94c5d5546161 | 966 | *val = LIS2DW12_DRDY_LATCHED; |
cparata | 4:94c5d5546161 | 967 | break; |
cparata | 4:94c5d5546161 | 968 | } |
cparata | 4:94c5d5546161 | 969 | return ret; |
cparata | 0:dff8803aace7 | 970 | } |
cparata | 0:dff8803aace7 | 971 | |
cparata | 0:dff8803aace7 | 972 | /** |
cparata | 0:dff8803aace7 | 973 | * @} |
cparata | 2:a94816b14e3d | 974 | * |
cparata | 0:dff8803aace7 | 975 | */ |
cparata | 0:dff8803aace7 | 976 | |
cparata | 0:dff8803aace7 | 977 | /** |
cparata | 2:a94816b14e3d | 978 | * @defgroup LIS2DW12_Filters |
cparata | 2:a94816b14e3d | 979 | * @brief This section group all the functions concerning the filters |
cparata | 2:a94816b14e3d | 980 | * configuration. |
cparata | 0:dff8803aace7 | 981 | * @{ |
cparata | 2:a94816b14e3d | 982 | * |
cparata | 0:dff8803aace7 | 983 | */ |
cparata | 0:dff8803aace7 | 984 | |
cparata | 0:dff8803aace7 | 985 | /** |
cparata | 2:a94816b14e3d | 986 | * @brief Accelerometer filtering path for outputs.[set] |
cparata | 0:dff8803aace7 | 987 | * |
cparata | 2:a94816b14e3d | 988 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 989 | * @param val change the values of fds in reg CTRL6 |
cparata | 2:a94816b14e3d | 990 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 991 | * |
cparata | 0:dff8803aace7 | 992 | */ |
cparata | 0:dff8803aace7 | 993 | int32_t lis2dw12_filter_path_set(lis2dw12_ctx_t *ctx, lis2dw12_fds_t val) |
cparata | 0:dff8803aace7 | 994 | { |
cparata | 4:94c5d5546161 | 995 | lis2dw12_ctrl6_t ctrl6; |
cparata | 4:94c5d5546161 | 996 | lis2dw12_ctrl_reg7_t ctrl_reg7; |
cparata | 4:94c5d5546161 | 997 | int32_t ret; |
cparata | 0:dff8803aace7 | 998 | |
cparata | 4:94c5d5546161 | 999 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1); |
cparata | 4:94c5d5546161 | 1000 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1001 | ctrl6.fds = ((uint8_t) val & 0x10U) >> 4; |
cparata | 4:94c5d5546161 | 1002 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1); |
cparata | 4:94c5d5546161 | 1003 | } |
cparata | 4:94c5d5546161 | 1004 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1005 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &ctrl_reg7, 1); |
cparata | 4:94c5d5546161 | 1006 | } |
cparata | 4:94c5d5546161 | 1007 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1008 | ctrl_reg7.usr_off_on_out = (uint8_t) val & 0x01U; |
cparata | 4:94c5d5546161 | 1009 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &ctrl_reg7, 1); |
cparata | 4:94c5d5546161 | 1010 | } |
cparata | 4:94c5d5546161 | 1011 | |
cparata | 4:94c5d5546161 | 1012 | return ret; |
cparata | 0:dff8803aace7 | 1013 | } |
cparata | 0:dff8803aace7 | 1014 | |
cparata | 0:dff8803aace7 | 1015 | /** |
cparata | 2:a94816b14e3d | 1016 | * @brief Accelerometer filtering path for outputs.[get] |
cparata | 0:dff8803aace7 | 1017 | * |
cparata | 2:a94816b14e3d | 1018 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1019 | * @param val Get the values of fds in reg CTRL6 |
cparata | 2:a94816b14e3d | 1020 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1021 | * |
cparata | 0:dff8803aace7 | 1022 | */ |
cparata | 0:dff8803aace7 | 1023 | int32_t lis2dw12_filter_path_get(lis2dw12_ctx_t *ctx, lis2dw12_fds_t *val) |
cparata | 0:dff8803aace7 | 1024 | { |
cparata | 4:94c5d5546161 | 1025 | lis2dw12_ctrl6_t ctrl6; |
cparata | 4:94c5d5546161 | 1026 | lis2dw12_ctrl_reg7_t ctrl_reg7; |
cparata | 4:94c5d5546161 | 1027 | int32_t ret; |
cparata | 4:94c5d5546161 | 1028 | |
cparata | 4:94c5d5546161 | 1029 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1); |
cparata | 4:94c5d5546161 | 1030 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1031 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &ctrl_reg7, 1); |
cparata | 0:dff8803aace7 | 1032 | |
cparata | 4:94c5d5546161 | 1033 | switch ((ctrl6.fds << 4) + ctrl_reg7.usr_off_on_out) { |
cparata | 4:94c5d5546161 | 1034 | case LIS2DW12_LPF_ON_OUT: |
cparata | 4:94c5d5546161 | 1035 | *val = LIS2DW12_LPF_ON_OUT; |
cparata | 4:94c5d5546161 | 1036 | break; |
cparata | 4:94c5d5546161 | 1037 | case LIS2DW12_USER_OFFSET_ON_OUT: |
cparata | 4:94c5d5546161 | 1038 | *val = LIS2DW12_USER_OFFSET_ON_OUT; |
cparata | 4:94c5d5546161 | 1039 | break; |
cparata | 4:94c5d5546161 | 1040 | case LIS2DW12_HIGH_PASS_ON_OUT: |
cparata | 4:94c5d5546161 | 1041 | *val = LIS2DW12_HIGH_PASS_ON_OUT; |
cparata | 4:94c5d5546161 | 1042 | break; |
cparata | 4:94c5d5546161 | 1043 | default: |
cparata | 4:94c5d5546161 | 1044 | *val = LIS2DW12_LPF_ON_OUT; |
cparata | 4:94c5d5546161 | 1045 | break; |
cparata | 4:94c5d5546161 | 1046 | } |
cparata | 2:a94816b14e3d | 1047 | } |
cparata | 4:94c5d5546161 | 1048 | return ret; |
cparata | 0:dff8803aace7 | 1049 | } |
cparata | 0:dff8803aace7 | 1050 | |
cparata | 0:dff8803aace7 | 1051 | /** |
cparata | 4:94c5d5546161 | 1052 | * @brief Accelerometer cutoff filter frequency. Valid for low and high |
cparata | 2:a94816b14e3d | 1053 | * pass filter.[set] |
cparata | 0:dff8803aace7 | 1054 | * |
cparata | 2:a94816b14e3d | 1055 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1056 | * @param val change the values of bw_filt in reg CTRL6 |
cparata | 2:a94816b14e3d | 1057 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1058 | * |
cparata | 0:dff8803aace7 | 1059 | */ |
cparata | 0:dff8803aace7 | 1060 | int32_t lis2dw12_filter_bandwidth_set(lis2dw12_ctx_t *ctx, |
cparata | 4:94c5d5546161 | 1061 | lis2dw12_bw_filt_t val) |
cparata | 0:dff8803aace7 | 1062 | { |
cparata | 4:94c5d5546161 | 1063 | lis2dw12_ctrl6_t reg; |
cparata | 4:94c5d5546161 | 1064 | int32_t ret; |
cparata | 0:dff8803aace7 | 1065 | |
cparata | 4:94c5d5546161 | 1066 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1067 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1068 | reg.bw_filt = (uint8_t) val; |
cparata | 4:94c5d5546161 | 1069 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1070 | } |
cparata | 0:dff8803aace7 | 1071 | |
cparata | 4:94c5d5546161 | 1072 | return ret; |
cparata | 0:dff8803aace7 | 1073 | } |
cparata | 0:dff8803aace7 | 1074 | |
cparata | 0:dff8803aace7 | 1075 | /** |
cparata | 4:94c5d5546161 | 1076 | * @brief Accelerometer cutoff filter frequency. Valid for low and |
cparata | 2:a94816b14e3d | 1077 | * high pass filter.[get] |
cparata | 0:dff8803aace7 | 1078 | * |
cparata | 2:a94816b14e3d | 1079 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1080 | * @param val Get the values of bw_filt in reg CTRL6 |
cparata | 2:a94816b14e3d | 1081 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1082 | * |
cparata | 0:dff8803aace7 | 1083 | */ |
cparata | 0:dff8803aace7 | 1084 | int32_t lis2dw12_filter_bandwidth_get(lis2dw12_ctx_t *ctx, |
cparata | 4:94c5d5546161 | 1085 | lis2dw12_bw_filt_t *val) |
cparata | 0:dff8803aace7 | 1086 | { |
cparata | 4:94c5d5546161 | 1087 | lis2dw12_ctrl6_t reg; |
cparata | 4:94c5d5546161 | 1088 | int32_t ret; |
cparata | 2:a94816b14e3d | 1089 | |
cparata | 4:94c5d5546161 | 1090 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) ®, 1); |
cparata | 0:dff8803aace7 | 1091 | |
cparata | 4:94c5d5546161 | 1092 | switch (reg.bw_filt) { |
cparata | 4:94c5d5546161 | 1093 | case LIS2DW12_ODR_DIV_2: |
cparata | 4:94c5d5546161 | 1094 | *val = LIS2DW12_ODR_DIV_2; |
cparata | 4:94c5d5546161 | 1095 | break; |
cparata | 4:94c5d5546161 | 1096 | case LIS2DW12_ODR_DIV_4: |
cparata | 4:94c5d5546161 | 1097 | *val = LIS2DW12_ODR_DIV_4; |
cparata | 4:94c5d5546161 | 1098 | break; |
cparata | 4:94c5d5546161 | 1099 | case LIS2DW12_ODR_DIV_10: |
cparata | 4:94c5d5546161 | 1100 | *val = LIS2DW12_ODR_DIV_10; |
cparata | 4:94c5d5546161 | 1101 | break; |
cparata | 4:94c5d5546161 | 1102 | case LIS2DW12_ODR_DIV_20: |
cparata | 4:94c5d5546161 | 1103 | *val = LIS2DW12_ODR_DIV_20; |
cparata | 4:94c5d5546161 | 1104 | break; |
cparata | 4:94c5d5546161 | 1105 | default: |
cparata | 4:94c5d5546161 | 1106 | *val = LIS2DW12_ODR_DIV_2; |
cparata | 4:94c5d5546161 | 1107 | break; |
cparata | 4:94c5d5546161 | 1108 | } |
cparata | 4:94c5d5546161 | 1109 | return ret; |
cparata | 0:dff8803aace7 | 1110 | } |
cparata | 0:dff8803aace7 | 1111 | |
cparata | 0:dff8803aace7 | 1112 | /** |
cparata | 2:a94816b14e3d | 1113 | * @brief Enable HP filter reference mode.[set] |
cparata | 0:dff8803aace7 | 1114 | * |
cparata | 2:a94816b14e3d | 1115 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1116 | * @param val change the values of hp_ref_mode in reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 1117 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1118 | * |
cparata | 0:dff8803aace7 | 1119 | */ |
cparata | 0:dff8803aace7 | 1120 | int32_t lis2dw12_reference_mode_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 1121 | { |
cparata | 4:94c5d5546161 | 1122 | lis2dw12_ctrl_reg7_t reg; |
cparata | 4:94c5d5546161 | 1123 | int32_t ret; |
cparata | 0:dff8803aace7 | 1124 | |
cparata | 4:94c5d5546161 | 1125 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1126 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1127 | reg.hp_ref_mode = val; |
cparata | 4:94c5d5546161 | 1128 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1129 | } |
cparata | 4:94c5d5546161 | 1130 | return ret; |
cparata | 0:dff8803aace7 | 1131 | } |
cparata | 0:dff8803aace7 | 1132 | |
cparata | 0:dff8803aace7 | 1133 | /** |
cparata | 2:a94816b14e3d | 1134 | * @brief Enable HP filter reference mode.[get] |
cparata | 0:dff8803aace7 | 1135 | * |
cparata | 2:a94816b14e3d | 1136 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1137 | * @param val change the values of hp_ref_mode in reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 1138 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1139 | * |
cparata | 0:dff8803aace7 | 1140 | */ |
cparata | 0:dff8803aace7 | 1141 | int32_t lis2dw12_reference_mode_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 1142 | { |
cparata | 4:94c5d5546161 | 1143 | lis2dw12_ctrl_reg7_t reg; |
cparata | 4:94c5d5546161 | 1144 | int32_t ret; |
cparata | 0:dff8803aace7 | 1145 | |
cparata | 4:94c5d5546161 | 1146 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1147 | *val = reg.hp_ref_mode; |
cparata | 0:dff8803aace7 | 1148 | |
cparata | 4:94c5d5546161 | 1149 | return ret; |
cparata | 0:dff8803aace7 | 1150 | } |
cparata | 0:dff8803aace7 | 1151 | |
cparata | 0:dff8803aace7 | 1152 | /** |
cparata | 0:dff8803aace7 | 1153 | * @} |
cparata | 2:a94816b14e3d | 1154 | * |
cparata | 0:dff8803aace7 | 1155 | */ |
cparata | 0:dff8803aace7 | 1156 | |
cparata | 0:dff8803aace7 | 1157 | /** |
cparata | 2:a94816b14e3d | 1158 | * @defgroup LIS2DW12_Serial_Interface |
cparata | 2:a94816b14e3d | 1159 | * @brief This section groups all the functions concerning main serial |
cparata | 2:a94816b14e3d | 1160 | * interface management (not auxiliary) |
cparata | 0:dff8803aace7 | 1161 | * @{ |
cparata | 2:a94816b14e3d | 1162 | * |
cparata | 0:dff8803aace7 | 1163 | */ |
cparata | 0:dff8803aace7 | 1164 | |
cparata | 0:dff8803aace7 | 1165 | /** |
cparata | 2:a94816b14e3d | 1166 | * @brief SPI Serial Interface Mode selection.[set] |
cparata | 0:dff8803aace7 | 1167 | * |
cparata | 2:a94816b14e3d | 1168 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1169 | * @param val change the values of sim in reg CTRL2 |
cparata | 2:a94816b14e3d | 1170 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1171 | * |
cparata | 0:dff8803aace7 | 1172 | */ |
cparata | 0:dff8803aace7 | 1173 | int32_t lis2dw12_spi_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_sim_t val) |
cparata | 0:dff8803aace7 | 1174 | { |
cparata | 4:94c5d5546161 | 1175 | lis2dw12_ctrl2_t reg; |
cparata | 4:94c5d5546161 | 1176 | int32_t ret; |
cparata | 0:dff8803aace7 | 1177 | |
cparata | 4:94c5d5546161 | 1178 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1179 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1180 | reg.sim = (uint8_t) val; |
cparata | 4:94c5d5546161 | 1181 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1182 | } |
cparata | 4:94c5d5546161 | 1183 | return ret; |
cparata | 0:dff8803aace7 | 1184 | } |
cparata | 0:dff8803aace7 | 1185 | |
cparata | 0:dff8803aace7 | 1186 | /** |
cparata | 4:94c5d5546161 | 1187 | * @brief SPI Serial Interface Mode selection.[get] |
cparata | 0:dff8803aace7 | 1188 | * |
cparata | 2:a94816b14e3d | 1189 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1190 | * @param val Get the values of sim in reg CTRL2 |
cparata | 2:a94816b14e3d | 1191 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1192 | * |
cparata | 0:dff8803aace7 | 1193 | */ |
cparata | 0:dff8803aace7 | 1194 | int32_t lis2dw12_spi_mode_get(lis2dw12_ctx_t *ctx, lis2dw12_sim_t *val) |
cparata | 0:dff8803aace7 | 1195 | { |
cparata | 4:94c5d5546161 | 1196 | lis2dw12_ctrl2_t reg; |
cparata | 4:94c5d5546161 | 1197 | int32_t ret; |
cparata | 2:a94816b14e3d | 1198 | |
cparata | 4:94c5d5546161 | 1199 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); |
cparata | 0:dff8803aace7 | 1200 | |
cparata | 4:94c5d5546161 | 1201 | switch (reg.sim) { |
cparata | 4:94c5d5546161 | 1202 | case LIS2DW12_SPI_4_WIRE: |
cparata | 4:94c5d5546161 | 1203 | *val = LIS2DW12_SPI_4_WIRE; |
cparata | 4:94c5d5546161 | 1204 | break; |
cparata | 4:94c5d5546161 | 1205 | case LIS2DW12_SPI_3_WIRE: |
cparata | 4:94c5d5546161 | 1206 | *val = LIS2DW12_SPI_3_WIRE; |
cparata | 4:94c5d5546161 | 1207 | break; |
cparata | 4:94c5d5546161 | 1208 | default: |
cparata | 4:94c5d5546161 | 1209 | *val = LIS2DW12_SPI_4_WIRE; |
cparata | 4:94c5d5546161 | 1210 | break; |
cparata | 4:94c5d5546161 | 1211 | } |
cparata | 4:94c5d5546161 | 1212 | return ret; |
cparata | 0:dff8803aace7 | 1213 | } |
cparata | 0:dff8803aace7 | 1214 | |
cparata | 0:dff8803aace7 | 1215 | /** |
cparata | 2:a94816b14e3d | 1216 | * @brief Disable / Enable I2C interface.[set] |
cparata | 0:dff8803aace7 | 1217 | * |
cparata | 2:a94816b14e3d | 1218 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1219 | * @param val change the values of i2c_disable in |
cparata | 0:dff8803aace7 | 1220 | * reg CTRL2 |
cparata | 2:a94816b14e3d | 1221 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1222 | * |
cparata | 0:dff8803aace7 | 1223 | */ |
cparata | 0:dff8803aace7 | 1224 | int32_t lis2dw12_i2c_interface_set(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1225 | lis2dw12_i2c_disable_t val) |
cparata | 0:dff8803aace7 | 1226 | { |
cparata | 4:94c5d5546161 | 1227 | lis2dw12_ctrl2_t reg; |
cparata | 4:94c5d5546161 | 1228 | int32_t ret; |
cparata | 0:dff8803aace7 | 1229 | |
cparata | 4:94c5d5546161 | 1230 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1231 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1232 | reg.i2c_disable = (uint8_t) val; |
cparata | 4:94c5d5546161 | 1233 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1234 | } |
cparata | 4:94c5d5546161 | 1235 | return ret; |
cparata | 0:dff8803aace7 | 1236 | } |
cparata | 0:dff8803aace7 | 1237 | |
cparata | 0:dff8803aace7 | 1238 | /** |
cparata | 4:94c5d5546161 | 1239 | * @brief Disable / Enable I2C interface.[get] |
cparata | 0:dff8803aace7 | 1240 | * |
cparata | 2:a94816b14e3d | 1241 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1242 | * @param val Get the values of i2c_disable in reg CTRL2 |
cparata | 2:a94816b14e3d | 1243 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1244 | * |
cparata | 0:dff8803aace7 | 1245 | */ |
cparata | 0:dff8803aace7 | 1246 | int32_t lis2dw12_i2c_interface_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1247 | lis2dw12_i2c_disable_t *val) |
cparata | 0:dff8803aace7 | 1248 | { |
cparata | 4:94c5d5546161 | 1249 | lis2dw12_ctrl2_t reg; |
cparata | 4:94c5d5546161 | 1250 | int32_t ret; |
cparata | 2:a94816b14e3d | 1251 | |
cparata | 4:94c5d5546161 | 1252 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); |
cparata | 0:dff8803aace7 | 1253 | |
cparata | 4:94c5d5546161 | 1254 | switch (reg.i2c_disable) { |
cparata | 4:94c5d5546161 | 1255 | case LIS2DW12_I2C_ENABLE: |
cparata | 4:94c5d5546161 | 1256 | *val = LIS2DW12_I2C_ENABLE; |
cparata | 4:94c5d5546161 | 1257 | break; |
cparata | 4:94c5d5546161 | 1258 | case LIS2DW12_I2C_DISABLE: |
cparata | 4:94c5d5546161 | 1259 | *val = LIS2DW12_I2C_DISABLE; |
cparata | 4:94c5d5546161 | 1260 | break; |
cparata | 4:94c5d5546161 | 1261 | default: |
cparata | 4:94c5d5546161 | 1262 | *val = LIS2DW12_I2C_ENABLE; |
cparata | 4:94c5d5546161 | 1263 | break; |
cparata | 4:94c5d5546161 | 1264 | } |
cparata | 4:94c5d5546161 | 1265 | return ret; |
cparata | 0:dff8803aace7 | 1266 | } |
cparata | 0:dff8803aace7 | 1267 | |
cparata | 0:dff8803aace7 | 1268 | /** |
cparata | 2:a94816b14e3d | 1269 | * @brief Disconnect CS pull-up.[set] |
cparata | 0:dff8803aace7 | 1270 | * |
cparata | 2:a94816b14e3d | 1271 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1272 | * @param val change the values of cs_pu_disc in reg CTRL2 |
cparata | 2:a94816b14e3d | 1273 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1274 | * |
cparata | 0:dff8803aace7 | 1275 | */ |
cparata | 0:dff8803aace7 | 1276 | int32_t lis2dw12_cs_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_cs_pu_disc_t val) |
cparata | 0:dff8803aace7 | 1277 | { |
cparata | 4:94c5d5546161 | 1278 | lis2dw12_ctrl2_t reg; |
cparata | 4:94c5d5546161 | 1279 | int32_t ret; |
cparata | 0:dff8803aace7 | 1280 | |
cparata | 4:94c5d5546161 | 1281 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1282 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1283 | reg.cs_pu_disc = (uint8_t) val; |
cparata | 4:94c5d5546161 | 1284 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1285 | } |
cparata | 4:94c5d5546161 | 1286 | return ret; |
cparata | 0:dff8803aace7 | 1287 | } |
cparata | 0:dff8803aace7 | 1288 | |
cparata | 0:dff8803aace7 | 1289 | /** |
cparata | 2:a94816b14e3d | 1290 | * @brief Disconnect CS pull-up.[get] |
cparata | 0:dff8803aace7 | 1291 | * |
cparata | 2:a94816b14e3d | 1292 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1293 | * @param val Get the values of cs_pu_disc in reg CTRL2 |
cparata | 2:a94816b14e3d | 1294 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1295 | * |
cparata | 0:dff8803aace7 | 1296 | */ |
cparata | 0:dff8803aace7 | 1297 | int32_t lis2dw12_cs_mode_get(lis2dw12_ctx_t *ctx, lis2dw12_cs_pu_disc_t *val) |
cparata | 0:dff8803aace7 | 1298 | { |
cparata | 4:94c5d5546161 | 1299 | lis2dw12_ctrl2_t reg; |
cparata | 4:94c5d5546161 | 1300 | int32_t ret; |
cparata | 2:a94816b14e3d | 1301 | |
cparata | 4:94c5d5546161 | 1302 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); |
cparata | 0:dff8803aace7 | 1303 | |
cparata | 4:94c5d5546161 | 1304 | switch (reg.cs_pu_disc) { |
cparata | 4:94c5d5546161 | 1305 | case LIS2DW12_PULL_UP_CONNECT: |
cparata | 4:94c5d5546161 | 1306 | *val = LIS2DW12_PULL_UP_CONNECT; |
cparata | 4:94c5d5546161 | 1307 | break; |
cparata | 4:94c5d5546161 | 1308 | case LIS2DW12_PULL_UP_DISCONNECT: |
cparata | 4:94c5d5546161 | 1309 | *val = LIS2DW12_PULL_UP_DISCONNECT; |
cparata | 4:94c5d5546161 | 1310 | break; |
cparata | 4:94c5d5546161 | 1311 | default: |
cparata | 4:94c5d5546161 | 1312 | *val = LIS2DW12_PULL_UP_CONNECT; |
cparata | 4:94c5d5546161 | 1313 | break; |
cparata | 4:94c5d5546161 | 1314 | } |
cparata | 4:94c5d5546161 | 1315 | return ret; |
cparata | 0:dff8803aace7 | 1316 | } |
cparata | 0:dff8803aace7 | 1317 | |
cparata | 0:dff8803aace7 | 1318 | /** |
cparata | 0:dff8803aace7 | 1319 | * @} |
cparata | 2:a94816b14e3d | 1320 | * |
cparata | 0:dff8803aace7 | 1321 | */ |
cparata | 0:dff8803aace7 | 1322 | |
cparata | 0:dff8803aace7 | 1323 | /** |
cparata | 2:a94816b14e3d | 1324 | * @defgroup LIS2DW12_Interrupt_Pins |
cparata | 2:a94816b14e3d | 1325 | * @brief This section groups all the functions that manage interrupt pins |
cparata | 0:dff8803aace7 | 1326 | * @{ |
cparata | 2:a94816b14e3d | 1327 | * |
cparata | 0:dff8803aace7 | 1328 | */ |
cparata | 0:dff8803aace7 | 1329 | |
cparata | 0:dff8803aace7 | 1330 | /** |
cparata | 2:a94816b14e3d | 1331 | * @brief Interrupt active-high/low.[set] |
cparata | 0:dff8803aace7 | 1332 | * |
cparata | 2:a94816b14e3d | 1333 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1334 | * @param val change the values of h_lactive in reg CTRL3 |
cparata | 2:a94816b14e3d | 1335 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1336 | * |
cparata | 0:dff8803aace7 | 1337 | */ |
cparata | 0:dff8803aace7 | 1338 | int32_t lis2dw12_pin_polarity_set(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1339 | lis2dw12_h_lactive_t val) |
cparata | 0:dff8803aace7 | 1340 | { |
cparata | 4:94c5d5546161 | 1341 | lis2dw12_ctrl3_t reg; |
cparata | 4:94c5d5546161 | 1342 | int32_t ret; |
cparata | 0:dff8803aace7 | 1343 | |
cparata | 4:94c5d5546161 | 1344 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1345 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1346 | reg.h_lactive = (uint8_t) val; |
cparata | 4:94c5d5546161 | 1347 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1348 | } |
cparata | 4:94c5d5546161 | 1349 | return ret; |
cparata | 0:dff8803aace7 | 1350 | } |
cparata | 0:dff8803aace7 | 1351 | |
cparata | 0:dff8803aace7 | 1352 | /** |
cparata | 2:a94816b14e3d | 1353 | * @brief Interrupt active-high/low.[get] |
cparata | 0:dff8803aace7 | 1354 | * |
cparata | 2:a94816b14e3d | 1355 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1356 | * @param val Get the values of h_lactive in reg CTRL3 |
cparata | 2:a94816b14e3d | 1357 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1358 | * |
cparata | 0:dff8803aace7 | 1359 | */ |
cparata | 0:dff8803aace7 | 1360 | int32_t lis2dw12_pin_polarity_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1361 | lis2dw12_h_lactive_t *val) |
cparata | 0:dff8803aace7 | 1362 | { |
cparata | 4:94c5d5546161 | 1363 | lis2dw12_ctrl3_t reg; |
cparata | 4:94c5d5546161 | 1364 | int32_t ret; |
cparata | 2:a94816b14e3d | 1365 | |
cparata | 4:94c5d5546161 | 1366 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1); |
cparata | 0:dff8803aace7 | 1367 | |
cparata | 4:94c5d5546161 | 1368 | switch (reg.h_lactive) { |
cparata | 4:94c5d5546161 | 1369 | case LIS2DW12_ACTIVE_HIGH: |
cparata | 4:94c5d5546161 | 1370 | *val = LIS2DW12_ACTIVE_HIGH; |
cparata | 4:94c5d5546161 | 1371 | break; |
cparata | 4:94c5d5546161 | 1372 | case LIS2DW12_ACTIVE_LOW: |
cparata | 4:94c5d5546161 | 1373 | *val = LIS2DW12_ACTIVE_LOW; |
cparata | 4:94c5d5546161 | 1374 | break; |
cparata | 4:94c5d5546161 | 1375 | default: |
cparata | 4:94c5d5546161 | 1376 | *val = LIS2DW12_ACTIVE_HIGH; |
cparata | 4:94c5d5546161 | 1377 | break; |
cparata | 4:94c5d5546161 | 1378 | } |
cparata | 4:94c5d5546161 | 1379 | return ret; |
cparata | 0:dff8803aace7 | 1380 | } |
cparata | 0:dff8803aace7 | 1381 | |
cparata | 0:dff8803aace7 | 1382 | /** |
cparata | 4:94c5d5546161 | 1383 | * @brief Latched/pulsed interrupt.[set] |
cparata | 0:dff8803aace7 | 1384 | * |
cparata | 2:a94816b14e3d | 1385 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1386 | * @param val change the values of lir in reg CTRL3 |
cparata | 2:a94816b14e3d | 1387 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1388 | * |
cparata | 0:dff8803aace7 | 1389 | */ |
cparata | 0:dff8803aace7 | 1390 | int32_t lis2dw12_int_notification_set(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1391 | lis2dw12_lir_t val) |
cparata | 0:dff8803aace7 | 1392 | { |
cparata | 4:94c5d5546161 | 1393 | lis2dw12_ctrl3_t reg; |
cparata | 4:94c5d5546161 | 1394 | int32_t ret; |
cparata | 0:dff8803aace7 | 1395 | |
cparata | 4:94c5d5546161 | 1396 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1397 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1398 | reg.lir = (uint8_t) val; |
cparata | 4:94c5d5546161 | 1399 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1400 | } |
cparata | 4:94c5d5546161 | 1401 | return ret; |
cparata | 0:dff8803aace7 | 1402 | } |
cparata | 0:dff8803aace7 | 1403 | |
cparata | 0:dff8803aace7 | 1404 | /** |
cparata | 2:a94816b14e3d | 1405 | * @brief Latched/pulsed interrupt.[get] |
cparata | 0:dff8803aace7 | 1406 | * |
cparata | 2:a94816b14e3d | 1407 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1408 | * @param val Get the values of lir in reg CTRL3 |
cparata | 2:a94816b14e3d | 1409 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1410 | * |
cparata | 0:dff8803aace7 | 1411 | */ |
cparata | 0:dff8803aace7 | 1412 | int32_t lis2dw12_int_notification_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1413 | lis2dw12_lir_t *val) |
cparata | 0:dff8803aace7 | 1414 | { |
cparata | 4:94c5d5546161 | 1415 | lis2dw12_ctrl3_t reg; |
cparata | 4:94c5d5546161 | 1416 | int32_t ret; |
cparata | 2:a94816b14e3d | 1417 | |
cparata | 4:94c5d5546161 | 1418 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1); |
cparata | 0:dff8803aace7 | 1419 | |
cparata | 4:94c5d5546161 | 1420 | switch (reg.lir) { |
cparata | 4:94c5d5546161 | 1421 | case LIS2DW12_INT_PULSED: |
cparata | 4:94c5d5546161 | 1422 | *val = LIS2DW12_INT_PULSED; |
cparata | 4:94c5d5546161 | 1423 | break; |
cparata | 4:94c5d5546161 | 1424 | case LIS2DW12_INT_LATCHED: |
cparata | 4:94c5d5546161 | 1425 | *val = LIS2DW12_INT_LATCHED; |
cparata | 4:94c5d5546161 | 1426 | break; |
cparata | 4:94c5d5546161 | 1427 | default: |
cparata | 4:94c5d5546161 | 1428 | *val = LIS2DW12_INT_PULSED; |
cparata | 4:94c5d5546161 | 1429 | break; |
cparata | 4:94c5d5546161 | 1430 | } |
cparata | 4:94c5d5546161 | 1431 | return ret; |
cparata | 0:dff8803aace7 | 1432 | } |
cparata | 0:dff8803aace7 | 1433 | |
cparata | 0:dff8803aace7 | 1434 | /** |
cparata | 2:a94816b14e3d | 1435 | * @brief Push-pull/open drain selection on interrupt pads.[set] |
cparata | 0:dff8803aace7 | 1436 | * |
cparata | 2:a94816b14e3d | 1437 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1438 | * @param val change the values of pp_od in reg CTRL3 |
cparata | 2:a94816b14e3d | 1439 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1440 | * |
cparata | 0:dff8803aace7 | 1441 | */ |
cparata | 0:dff8803aace7 | 1442 | int32_t lis2dw12_pin_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_pp_od_t val) |
cparata | 0:dff8803aace7 | 1443 | { |
cparata | 4:94c5d5546161 | 1444 | lis2dw12_ctrl3_t reg; |
cparata | 4:94c5d5546161 | 1445 | int32_t ret; |
cparata | 0:dff8803aace7 | 1446 | |
cparata | 4:94c5d5546161 | 1447 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1448 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1449 | reg.pp_od = (uint8_t) val; |
cparata | 4:94c5d5546161 | 1450 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1451 | } |
cparata | 4:94c5d5546161 | 1452 | return ret; |
cparata | 0:dff8803aace7 | 1453 | } |
cparata | 0:dff8803aace7 | 1454 | |
cparata | 0:dff8803aace7 | 1455 | /** |
cparata | 2:a94816b14e3d | 1456 | * @brief Push-pull/open drain selection on interrupt pads.[get] |
cparata | 0:dff8803aace7 | 1457 | * |
cparata | 2:a94816b14e3d | 1458 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1459 | * @param val Get the values of pp_od in reg CTRL3 |
cparata | 2:a94816b14e3d | 1460 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1461 | * |
cparata | 0:dff8803aace7 | 1462 | */ |
cparata | 0:dff8803aace7 | 1463 | int32_t lis2dw12_pin_mode_get(lis2dw12_ctx_t *ctx, lis2dw12_pp_od_t *val) |
cparata | 0:dff8803aace7 | 1464 | { |
cparata | 4:94c5d5546161 | 1465 | lis2dw12_ctrl3_t reg; |
cparata | 4:94c5d5546161 | 1466 | int32_t ret; |
cparata | 2:a94816b14e3d | 1467 | |
cparata | 4:94c5d5546161 | 1468 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1); |
cparata | 0:dff8803aace7 | 1469 | |
cparata | 4:94c5d5546161 | 1470 | switch (reg.pp_od) { |
cparata | 4:94c5d5546161 | 1471 | case LIS2DW12_PUSH_PULL: |
cparata | 4:94c5d5546161 | 1472 | *val = LIS2DW12_PUSH_PULL; |
cparata | 4:94c5d5546161 | 1473 | break; |
cparata | 4:94c5d5546161 | 1474 | case LIS2DW12_OPEN_DRAIN: |
cparata | 4:94c5d5546161 | 1475 | *val = LIS2DW12_OPEN_DRAIN; |
cparata | 4:94c5d5546161 | 1476 | break; |
cparata | 4:94c5d5546161 | 1477 | default: |
cparata | 4:94c5d5546161 | 1478 | *val = LIS2DW12_PUSH_PULL; |
cparata | 4:94c5d5546161 | 1479 | break; |
cparata | 4:94c5d5546161 | 1480 | } |
cparata | 4:94c5d5546161 | 1481 | return ret; |
cparata | 0:dff8803aace7 | 1482 | } |
cparata | 0:dff8803aace7 | 1483 | |
cparata | 0:dff8803aace7 | 1484 | /** |
cparata | 2:a94816b14e3d | 1485 | * @brief Select the signal that need to route on int1 pad.[set] |
cparata | 0:dff8803aace7 | 1486 | * |
cparata | 2:a94816b14e3d | 1487 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1488 | * @param val register CTRL4_INT1_PAD_CTRL. |
cparata | 2:a94816b14e3d | 1489 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1490 | * |
cparata | 0:dff8803aace7 | 1491 | */ |
cparata | 0:dff8803aace7 | 1492 | int32_t lis2dw12_pin_int1_route_set(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1493 | lis2dw12_ctrl4_int1_pad_ctrl_t *val) |
cparata | 0:dff8803aace7 | 1494 | { |
cparata | 4:94c5d5546161 | 1495 | lis2dw12_ctrl_reg7_t reg; |
cparata | 4:94c5d5546161 | 1496 | int32_t ret; |
cparata | 4:94c5d5546161 | 1497 | |
cparata | 4:94c5d5546161 | 1498 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1499 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1500 | if ((val->int1_tap | val->int1_ff | val->int1_wu | val->int1_single_tap | |
cparata | 4:94c5d5546161 | 1501 | val->int1_6d) != PROPERTY_DISABLE) { |
cparata | 4:94c5d5546161 | 1502 | reg.interrupts_enable = PROPERTY_ENABLE; |
cparata | 4:94c5d5546161 | 1503 | } else { |
cparata | 4:94c5d5546161 | 1504 | reg.interrupts_enable = PROPERTY_DISABLE; |
cparata | 4:94c5d5546161 | 1505 | } |
cparata | 4:94c5d5546161 | 1506 | |
cparata | 4:94c5d5546161 | 1507 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL4_INT1_PAD_CTRL, |
cparata | 4:94c5d5546161 | 1508 | (uint8_t *) val, 1); |
cparata | 2:a94816b14e3d | 1509 | } |
cparata | 4:94c5d5546161 | 1510 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1511 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1512 | } |
cparata | 4:94c5d5546161 | 1513 | return ret; |
cparata | 0:dff8803aace7 | 1514 | } |
cparata | 0:dff8803aace7 | 1515 | |
cparata | 0:dff8803aace7 | 1516 | /** |
cparata | 2:a94816b14e3d | 1517 | * @brief Select the signal that need to route on int1 pad.[get] |
cparata | 0:dff8803aace7 | 1518 | * |
cparata | 2:a94816b14e3d | 1519 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1520 | * @param val register CTRL4_INT1_PAD_CTRL. |
cparata | 2:a94816b14e3d | 1521 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1522 | * |
cparata | 0:dff8803aace7 | 1523 | */ |
cparata | 0:dff8803aace7 | 1524 | int32_t lis2dw12_pin_int1_route_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1525 | lis2dw12_ctrl4_int1_pad_ctrl_t *val) |
cparata | 0:dff8803aace7 | 1526 | { |
cparata | 4:94c5d5546161 | 1527 | int32_t ret; |
cparata | 4:94c5d5546161 | 1528 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL4_INT1_PAD_CTRL, |
cparata | 4:94c5d5546161 | 1529 | (uint8_t *) val, 1); |
cparata | 4:94c5d5546161 | 1530 | return ret; |
cparata | 0:dff8803aace7 | 1531 | } |
cparata | 2:a94816b14e3d | 1532 | |
cparata | 0:dff8803aace7 | 1533 | /** |
cparata | 4:94c5d5546161 | 1534 | * @brief Select the signal that need to route on int2 pad.[set] |
cparata | 0:dff8803aace7 | 1535 | * |
cparata | 2:a94816b14e3d | 1536 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1537 | * @param val register CTRL5_INT2_PAD_CTRL. |
cparata | 2:a94816b14e3d | 1538 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1539 | * |
cparata | 0:dff8803aace7 | 1540 | */ |
cparata | 0:dff8803aace7 | 1541 | int32_t lis2dw12_pin_int2_route_set(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1542 | lis2dw12_ctrl5_int2_pad_ctrl_t *val) |
cparata | 0:dff8803aace7 | 1543 | { |
cparata | 4:94c5d5546161 | 1544 | lis2dw12_ctrl_reg7_t reg; |
cparata | 4:94c5d5546161 | 1545 | int32_t ret; |
cparata | 4:94c5d5546161 | 1546 | |
cparata | 4:94c5d5546161 | 1547 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1548 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1549 | if ((val->int2_sleep_state | val->int2_sleep_chg) != PROPERTY_DISABLE) { |
cparata | 4:94c5d5546161 | 1550 | reg.interrupts_enable = PROPERTY_ENABLE; |
cparata | 4:94c5d5546161 | 1551 | } else { |
cparata | 4:94c5d5546161 | 1552 | reg.interrupts_enable = PROPERTY_DISABLE; |
cparata | 4:94c5d5546161 | 1553 | } |
cparata | 4:94c5d5546161 | 1554 | |
cparata | 4:94c5d5546161 | 1555 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL5_INT2_PAD_CTRL, |
cparata | 4:94c5d5546161 | 1556 | (uint8_t *) val, 1); |
cparata | 2:a94816b14e3d | 1557 | } |
cparata | 4:94c5d5546161 | 1558 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1559 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1560 | } |
cparata | 4:94c5d5546161 | 1561 | |
cparata | 4:94c5d5546161 | 1562 | return ret; |
cparata | 0:dff8803aace7 | 1563 | } |
cparata | 0:dff8803aace7 | 1564 | |
cparata | 0:dff8803aace7 | 1565 | /** |
cparata | 2:a94816b14e3d | 1566 | * @brief Select the signal that need to route on int2 pad.[get] |
cparata | 0:dff8803aace7 | 1567 | * |
cparata | 2:a94816b14e3d | 1568 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1569 | * @param val register CTRL5_INT2_PAD_CTRL |
cparata | 2:a94816b14e3d | 1570 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1571 | * |
cparata | 0:dff8803aace7 | 1572 | */ |
cparata | 0:dff8803aace7 | 1573 | int32_t lis2dw12_pin_int2_route_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1574 | lis2dw12_ctrl5_int2_pad_ctrl_t *val) |
cparata | 0:dff8803aace7 | 1575 | { |
cparata | 4:94c5d5546161 | 1576 | int32_t ret; |
cparata | 4:94c5d5546161 | 1577 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL5_INT2_PAD_CTRL, |
cparata | 4:94c5d5546161 | 1578 | (uint8_t *) val, 1); |
cparata | 4:94c5d5546161 | 1579 | return ret; |
cparata | 0:dff8803aace7 | 1580 | } |
cparata | 0:dff8803aace7 | 1581 | /** |
cparata | 4:94c5d5546161 | 1582 | * @brief All interrupt signals become available on INT1 pin.[set] |
cparata | 0:dff8803aace7 | 1583 | * |
cparata | 2:a94816b14e3d | 1584 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1585 | * @param val change the values of int2_on_int1 in reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 1586 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1587 | * |
cparata | 0:dff8803aace7 | 1588 | */ |
cparata | 0:dff8803aace7 | 1589 | int32_t lis2dw12_all_on_int1_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 1590 | { |
cparata | 4:94c5d5546161 | 1591 | lis2dw12_ctrl_reg7_t reg; |
cparata | 4:94c5d5546161 | 1592 | int32_t ret; |
cparata | 0:dff8803aace7 | 1593 | |
cparata | 4:94c5d5546161 | 1594 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1595 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1596 | reg.int2_on_int1 = val; |
cparata | 4:94c5d5546161 | 1597 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1598 | } |
cparata | 4:94c5d5546161 | 1599 | return ret; |
cparata | 0:dff8803aace7 | 1600 | } |
cparata | 0:dff8803aace7 | 1601 | |
cparata | 0:dff8803aace7 | 1602 | /** |
cparata | 2:a94816b14e3d | 1603 | * @brief All interrupt signals become available on INT1 pin.[get] |
cparata | 0:dff8803aace7 | 1604 | * |
cparata | 2:a94816b14e3d | 1605 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1606 | * @param val change the values of int2_on_int1 in reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 1607 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1608 | * |
cparata | 0:dff8803aace7 | 1609 | */ |
cparata | 0:dff8803aace7 | 1610 | int32_t lis2dw12_all_on_int1_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 1611 | { |
cparata | 4:94c5d5546161 | 1612 | lis2dw12_ctrl_reg7_t reg; |
cparata | 4:94c5d5546161 | 1613 | int32_t ret; |
cparata | 0:dff8803aace7 | 1614 | |
cparata | 4:94c5d5546161 | 1615 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1616 | *val = reg.int2_on_int1; |
cparata | 0:dff8803aace7 | 1617 | |
cparata | 4:94c5d5546161 | 1618 | return ret; |
cparata | 0:dff8803aace7 | 1619 | } |
cparata | 0:dff8803aace7 | 1620 | |
cparata | 0:dff8803aace7 | 1621 | /** |
cparata | 0:dff8803aace7 | 1622 | * @} |
cparata | 2:a94816b14e3d | 1623 | * |
cparata | 0:dff8803aace7 | 1624 | */ |
cparata | 0:dff8803aace7 | 1625 | |
cparata | 0:dff8803aace7 | 1626 | /** |
cparata | 2:a94816b14e3d | 1627 | * @defgroup LIS2DW12_Wake_Up_Event |
cparata | 2:a94816b14e3d | 1628 | * @brief This section groups all the functions that manage the Wake |
cparata | 2:a94816b14e3d | 1629 | * Up event generation. |
cparata | 0:dff8803aace7 | 1630 | * @{ |
cparata | 2:a94816b14e3d | 1631 | * |
cparata | 0:dff8803aace7 | 1632 | */ |
cparata | 0:dff8803aace7 | 1633 | |
cparata | 0:dff8803aace7 | 1634 | /** |
cparata | 2:a94816b14e3d | 1635 | * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[set] |
cparata | 0:dff8803aace7 | 1636 | * |
cparata | 2:a94816b14e3d | 1637 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1638 | * @param val change the values of wk_ths in reg WAKE_UP_THS |
cparata | 2:a94816b14e3d | 1639 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1640 | * |
cparata | 0:dff8803aace7 | 1641 | */ |
cparata | 0:dff8803aace7 | 1642 | int32_t lis2dw12_wkup_threshold_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 1643 | { |
cparata | 4:94c5d5546161 | 1644 | lis2dw12_wake_up_ths_t reg; |
cparata | 4:94c5d5546161 | 1645 | int32_t ret; |
cparata | 0:dff8803aace7 | 1646 | |
cparata | 4:94c5d5546161 | 1647 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1648 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1649 | reg.wk_ths = val; |
cparata | 4:94c5d5546161 | 1650 | ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1651 | } |
cparata | 4:94c5d5546161 | 1652 | return ret; |
cparata | 0:dff8803aace7 | 1653 | } |
cparata | 0:dff8803aace7 | 1654 | |
cparata | 0:dff8803aace7 | 1655 | /** |
cparata | 2:a94816b14e3d | 1656 | * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[get] |
cparata | 0:dff8803aace7 | 1657 | * |
cparata | 2:a94816b14e3d | 1658 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1659 | * @param val change the values of wk_ths in reg WAKE_UP_THS |
cparata | 2:a94816b14e3d | 1660 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1661 | * |
cparata | 0:dff8803aace7 | 1662 | */ |
cparata | 0:dff8803aace7 | 1663 | int32_t lis2dw12_wkup_threshold_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 1664 | { |
cparata | 4:94c5d5546161 | 1665 | lis2dw12_wake_up_ths_t reg; |
cparata | 4:94c5d5546161 | 1666 | int32_t ret; |
cparata | 0:dff8803aace7 | 1667 | |
cparata | 4:94c5d5546161 | 1668 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1669 | *val = reg.wk_ths; |
cparata | 0:dff8803aace7 | 1670 | |
cparata | 4:94c5d5546161 | 1671 | return ret; |
cparata | 0:dff8803aace7 | 1672 | } |
cparata | 0:dff8803aace7 | 1673 | |
cparata | 0:dff8803aace7 | 1674 | /** |
cparata | 2:a94816b14e3d | 1675 | * @brief Wake up duration event.1LSb = 1 / ODR.[set] |
cparata | 0:dff8803aace7 | 1676 | * |
cparata | 2:a94816b14e3d | 1677 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1678 | * @param val change the values of wake_dur in reg WAKE_UP_DUR |
cparata | 2:a94816b14e3d | 1679 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1680 | * |
cparata | 0:dff8803aace7 | 1681 | */ |
cparata | 0:dff8803aace7 | 1682 | int32_t lis2dw12_wkup_dur_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 1683 | { |
cparata | 4:94c5d5546161 | 1684 | lis2dw12_wake_up_dur_t reg; |
cparata | 4:94c5d5546161 | 1685 | int32_t ret; |
cparata | 0:dff8803aace7 | 1686 | |
cparata | 4:94c5d5546161 | 1687 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1688 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1689 | reg.wake_dur = val; |
cparata | 4:94c5d5546161 | 1690 | ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1691 | } |
cparata | 4:94c5d5546161 | 1692 | return ret; |
cparata | 0:dff8803aace7 | 1693 | } |
cparata | 0:dff8803aace7 | 1694 | |
cparata | 0:dff8803aace7 | 1695 | /** |
cparata | 2:a94816b14e3d | 1696 | * @brief Wake up duration event.1LSb = 1 / ODR.[get] |
cparata | 0:dff8803aace7 | 1697 | * |
cparata | 2:a94816b14e3d | 1698 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1699 | * @param val change the values of wake_dur in reg WAKE_UP_DUR |
cparata | 2:a94816b14e3d | 1700 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1701 | * |
cparata | 0:dff8803aace7 | 1702 | */ |
cparata | 0:dff8803aace7 | 1703 | int32_t lis2dw12_wkup_dur_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 1704 | { |
cparata | 4:94c5d5546161 | 1705 | lis2dw12_wake_up_dur_t reg; |
cparata | 4:94c5d5546161 | 1706 | int32_t ret; |
cparata | 0:dff8803aace7 | 1707 | |
cparata | 4:94c5d5546161 | 1708 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1709 | *val = reg.wake_dur; |
cparata | 0:dff8803aace7 | 1710 | |
cparata | 4:94c5d5546161 | 1711 | return ret; |
cparata | 0:dff8803aace7 | 1712 | } |
cparata | 0:dff8803aace7 | 1713 | |
cparata | 0:dff8803aace7 | 1714 | /** |
cparata | 2:a94816b14e3d | 1715 | * @brief Data sent to wake-up interrupt function.[set] |
cparata | 0:dff8803aace7 | 1716 | * |
cparata | 2:a94816b14e3d | 1717 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1718 | * @param val change the values of usr_off_on_wu in reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 1719 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1720 | * |
cparata | 0:dff8803aace7 | 1721 | */ |
cparata | 0:dff8803aace7 | 1722 | int32_t lis2dw12_wkup_feed_data_set(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1723 | lis2dw12_usr_off_on_wu_t val) |
cparata | 0:dff8803aace7 | 1724 | { |
cparata | 4:94c5d5546161 | 1725 | lis2dw12_ctrl_reg7_t reg; |
cparata | 4:94c5d5546161 | 1726 | int32_t ret; |
cparata | 0:dff8803aace7 | 1727 | |
cparata | 4:94c5d5546161 | 1728 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1729 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1730 | reg.usr_off_on_wu = (uint8_t) val; |
cparata | 4:94c5d5546161 | 1731 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1732 | } |
cparata | 4:94c5d5546161 | 1733 | return ret; |
cparata | 0:dff8803aace7 | 1734 | } |
cparata | 0:dff8803aace7 | 1735 | |
cparata | 0:dff8803aace7 | 1736 | /** |
cparata | 2:a94816b14e3d | 1737 | * @brief Data sent to wake-up interrupt function.[get] |
cparata | 0:dff8803aace7 | 1738 | * |
cparata | 2:a94816b14e3d | 1739 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1740 | * @param val Get the values of usr_off_on_wu in reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 1741 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1742 | * |
cparata | 0:dff8803aace7 | 1743 | */ |
cparata | 0:dff8803aace7 | 1744 | int32_t lis2dw12_wkup_feed_data_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1745 | lis2dw12_usr_off_on_wu_t *val) |
cparata | 0:dff8803aace7 | 1746 | { |
cparata | 4:94c5d5546161 | 1747 | lis2dw12_ctrl_reg7_t reg; |
cparata | 4:94c5d5546161 | 1748 | int32_t ret; |
cparata | 2:a94816b14e3d | 1749 | |
cparata | 4:94c5d5546161 | 1750 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); |
cparata | 0:dff8803aace7 | 1751 | |
cparata | 4:94c5d5546161 | 1752 | switch (reg.usr_off_on_wu) { |
cparata | 4:94c5d5546161 | 1753 | case LIS2DW12_HP_FEED: |
cparata | 4:94c5d5546161 | 1754 | *val = LIS2DW12_HP_FEED; |
cparata | 4:94c5d5546161 | 1755 | break; |
cparata | 4:94c5d5546161 | 1756 | case LIS2DW12_USER_OFFSET_FEED: |
cparata | 4:94c5d5546161 | 1757 | *val = LIS2DW12_USER_OFFSET_FEED; |
cparata | 4:94c5d5546161 | 1758 | break; |
cparata | 4:94c5d5546161 | 1759 | default: |
cparata | 4:94c5d5546161 | 1760 | *val = LIS2DW12_HP_FEED; |
cparata | 4:94c5d5546161 | 1761 | break; |
cparata | 4:94c5d5546161 | 1762 | } |
cparata | 4:94c5d5546161 | 1763 | return ret; |
cparata | 0:dff8803aace7 | 1764 | } |
cparata | 0:dff8803aace7 | 1765 | |
cparata | 0:dff8803aace7 | 1766 | /** |
cparata | 0:dff8803aace7 | 1767 | * @} |
cparata | 2:a94816b14e3d | 1768 | * |
cparata | 0:dff8803aace7 | 1769 | */ |
cparata | 0:dff8803aace7 | 1770 | |
cparata | 0:dff8803aace7 | 1771 | /** |
cparata | 2:a94816b14e3d | 1772 | * @defgroup LIS2DW12_Activity/Inactivity_Detection |
cparata | 2:a94816b14e3d | 1773 | * @brief This section groups all the functions concerning |
cparata | 2:a94816b14e3d | 1774 | * activity/inactivity detection. |
cparata | 0:dff8803aace7 | 1775 | * @{ |
cparata | 2:a94816b14e3d | 1776 | * |
cparata | 0:dff8803aace7 | 1777 | */ |
cparata | 0:dff8803aace7 | 1778 | |
cparata | 0:dff8803aace7 | 1779 | /** |
cparata | 4:94c5d5546161 | 1780 | * @brief Config activity / inactivity or |
cparata | 2:a94816b14e3d | 1781 | * stationary / motion detection.[set] |
cparata | 0:dff8803aace7 | 1782 | * |
cparata | 2:a94816b14e3d | 1783 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1784 | * @param val change the values of sleep_on / stationary in |
cparata | 2:a94816b14e3d | 1785 | * reg WAKE_UP_THS / WAKE_UP_DUR |
cparata | 2:a94816b14e3d | 1786 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1787 | * |
cparata | 0:dff8803aace7 | 1788 | */ |
cparata | 0:dff8803aace7 | 1789 | int32_t lis2dw12_act_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_sleep_on_t val) |
cparata | 0:dff8803aace7 | 1790 | { |
cparata | 4:94c5d5546161 | 1791 | lis2dw12_wake_up_ths_t wake_up_ths; |
cparata | 4:94c5d5546161 | 1792 | lis2dw12_wake_up_dur_t wake_up_dur; |
cparata | 4:94c5d5546161 | 1793 | int32_t ret; |
cparata | 4:94c5d5546161 | 1794 | |
cparata | 4:94c5d5546161 | 1795 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) &wake_up_ths, 1); |
cparata | 4:94c5d5546161 | 1796 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1797 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) &wake_up_dur, 1); |
cparata | 4:94c5d5546161 | 1798 | } |
cparata | 4:94c5d5546161 | 1799 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1800 | wake_up_ths.sleep_on = (uint8_t) val & 0x01U; |
cparata | 4:94c5d5546161 | 1801 | ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) &wake_up_ths, 1); |
cparata | 4:94c5d5546161 | 1802 | } |
cparata | 4:94c5d5546161 | 1803 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1804 | wake_up_dur.stationary = ((uint8_t)val & 0x02U) >> 1; |
cparata | 4:94c5d5546161 | 1805 | ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) &wake_up_dur, 1); |
cparata | 4:94c5d5546161 | 1806 | } |
cparata | 4:94c5d5546161 | 1807 | |
cparata | 4:94c5d5546161 | 1808 | return ret; |
cparata | 0:dff8803aace7 | 1809 | } |
cparata | 0:dff8803aace7 | 1810 | |
cparata | 0:dff8803aace7 | 1811 | /** |
cparata | 4:94c5d5546161 | 1812 | * @brief Config activity / inactivity or |
cparata | 2:a94816b14e3d | 1813 | * stationary / motion detection. [get] |
cparata | 0:dff8803aace7 | 1814 | * |
cparata | 2:a94816b14e3d | 1815 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1816 | * @param val Get the values of sleep_on in reg WAKE_UP_THS |
cparata | 2:a94816b14e3d | 1817 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1818 | * |
cparata | 0:dff8803aace7 | 1819 | */ |
cparata | 0:dff8803aace7 | 1820 | int32_t lis2dw12_act_mode_get(lis2dw12_ctx_t *ctx, lis2dw12_sleep_on_t *val) |
cparata | 0:dff8803aace7 | 1821 | { |
cparata | 4:94c5d5546161 | 1822 | lis2dw12_wake_up_ths_t wake_up_ths; |
cparata | 4:94c5d5546161 | 1823 | lis2dw12_wake_up_dur_t wake_up_dur;; |
cparata | 4:94c5d5546161 | 1824 | int32_t ret; |
cparata | 2:a94816b14e3d | 1825 | |
cparata | 4:94c5d5546161 | 1826 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) &wake_up_ths, 1); |
cparata | 4:94c5d5546161 | 1827 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1828 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) &wake_up_dur, 1); |
cparata | 0:dff8803aace7 | 1829 | |
cparata | 4:94c5d5546161 | 1830 | switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on) { |
cparata | 4:94c5d5546161 | 1831 | case LIS2DW12_NO_DETECTION: |
cparata | 4:94c5d5546161 | 1832 | *val = LIS2DW12_NO_DETECTION; |
cparata | 4:94c5d5546161 | 1833 | break; |
cparata | 4:94c5d5546161 | 1834 | case LIS2DW12_DETECT_ACT_INACT: |
cparata | 4:94c5d5546161 | 1835 | *val = LIS2DW12_DETECT_ACT_INACT; |
cparata | 4:94c5d5546161 | 1836 | break; |
cparata | 4:94c5d5546161 | 1837 | case LIS2DW12_DETECT_STAT_MOTION: |
cparata | 4:94c5d5546161 | 1838 | *val = LIS2DW12_DETECT_STAT_MOTION; |
cparata | 4:94c5d5546161 | 1839 | break; |
cparata | 4:94c5d5546161 | 1840 | default: |
cparata | 4:94c5d5546161 | 1841 | *val = LIS2DW12_NO_DETECTION; |
cparata | 4:94c5d5546161 | 1842 | break; |
cparata | 4:94c5d5546161 | 1843 | } |
cparata | 2:a94816b14e3d | 1844 | } |
cparata | 4:94c5d5546161 | 1845 | return ret; |
cparata | 0:dff8803aace7 | 1846 | } |
cparata | 0:dff8803aace7 | 1847 | |
cparata | 0:dff8803aace7 | 1848 | /** |
cparata | 2:a94816b14e3d | 1849 | * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set] |
cparata | 0:dff8803aace7 | 1850 | * |
cparata | 2:a94816b14e3d | 1851 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1852 | * @param val change the values of sleep_dur in reg WAKE_UP_DUR |
cparata | 2:a94816b14e3d | 1853 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1854 | * |
cparata | 0:dff8803aace7 | 1855 | */ |
cparata | 0:dff8803aace7 | 1856 | int32_t lis2dw12_act_sleep_dur_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 1857 | { |
cparata | 4:94c5d5546161 | 1858 | lis2dw12_wake_up_dur_t reg; |
cparata | 4:94c5d5546161 | 1859 | int32_t ret; |
cparata | 0:dff8803aace7 | 1860 | |
cparata | 4:94c5d5546161 | 1861 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1862 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1863 | reg.sleep_dur = val; |
cparata | 4:94c5d5546161 | 1864 | ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1865 | } |
cparata | 4:94c5d5546161 | 1866 | return ret; |
cparata | 0:dff8803aace7 | 1867 | } |
cparata | 0:dff8803aace7 | 1868 | |
cparata | 0:dff8803aace7 | 1869 | /** |
cparata | 2:a94816b14e3d | 1870 | * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[get] |
cparata | 0:dff8803aace7 | 1871 | * |
cparata | 2:a94816b14e3d | 1872 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1873 | * @param val change the values of sleep_dur in reg WAKE_UP_DUR |
cparata | 2:a94816b14e3d | 1874 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1875 | * |
cparata | 0:dff8803aace7 | 1876 | */ |
cparata | 0:dff8803aace7 | 1877 | int32_t lis2dw12_act_sleep_dur_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 1878 | { |
cparata | 4:94c5d5546161 | 1879 | lis2dw12_wake_up_dur_t reg; |
cparata | 4:94c5d5546161 | 1880 | int32_t ret; |
cparata | 0:dff8803aace7 | 1881 | |
cparata | 4:94c5d5546161 | 1882 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1883 | *val = reg.sleep_dur; |
cparata | 0:dff8803aace7 | 1884 | |
cparata | 4:94c5d5546161 | 1885 | return ret; |
cparata | 0:dff8803aace7 | 1886 | } |
cparata | 0:dff8803aace7 | 1887 | |
cparata | 0:dff8803aace7 | 1888 | /** |
cparata | 0:dff8803aace7 | 1889 | * @} |
cparata | 2:a94816b14e3d | 1890 | * |
cparata | 0:dff8803aace7 | 1891 | */ |
cparata | 0:dff8803aace7 | 1892 | |
cparata | 0:dff8803aace7 | 1893 | /** |
cparata | 2:a94816b14e3d | 1894 | * @defgroup LIS2DW12_Tap_Generator |
cparata | 2:a94816b14e3d | 1895 | * @brief This section groups all the functions that manage the tap |
cparata | 2:a94816b14e3d | 1896 | * and double tap event generation. |
cparata | 0:dff8803aace7 | 1897 | * @{ |
cparata | 2:a94816b14e3d | 1898 | * |
cparata | 0:dff8803aace7 | 1899 | */ |
cparata | 0:dff8803aace7 | 1900 | |
cparata | 0:dff8803aace7 | 1901 | /** |
cparata | 2:a94816b14e3d | 1902 | * @brief Threshold for tap recognition.[set] |
cparata | 0:dff8803aace7 | 1903 | * |
cparata | 2:a94816b14e3d | 1904 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1905 | * @param val change the values of tap_thsx in reg TAP_THS_X |
cparata | 2:a94816b14e3d | 1906 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1907 | * |
cparata | 0:dff8803aace7 | 1908 | */ |
cparata | 0:dff8803aace7 | 1909 | int32_t lis2dw12_tap_threshold_x_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 1910 | { |
cparata | 4:94c5d5546161 | 1911 | lis2dw12_tap_ths_x_t reg; |
cparata | 4:94c5d5546161 | 1912 | int32_t ret; |
cparata | 0:dff8803aace7 | 1913 | |
cparata | 4:94c5d5546161 | 1914 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1915 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1916 | reg.tap_thsx = val; |
cparata | 4:94c5d5546161 | 1917 | ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1918 | } |
cparata | 4:94c5d5546161 | 1919 | return ret; |
cparata | 0:dff8803aace7 | 1920 | } |
cparata | 0:dff8803aace7 | 1921 | |
cparata | 0:dff8803aace7 | 1922 | /** |
cparata | 2:a94816b14e3d | 1923 | * @brief Threshold for tap recognition.[get] |
cparata | 0:dff8803aace7 | 1924 | * |
cparata | 2:a94816b14e3d | 1925 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1926 | * @param val change the values of tap_thsx in reg TAP_THS_X |
cparata | 2:a94816b14e3d | 1927 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1928 | * |
cparata | 0:dff8803aace7 | 1929 | */ |
cparata | 0:dff8803aace7 | 1930 | int32_t lis2dw12_tap_threshold_x_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 1931 | { |
cparata | 4:94c5d5546161 | 1932 | lis2dw12_tap_ths_x_t reg; |
cparata | 4:94c5d5546161 | 1933 | int32_t ret; |
cparata | 0:dff8803aace7 | 1934 | |
cparata | 4:94c5d5546161 | 1935 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1936 | *val = reg.tap_thsx; |
cparata | 0:dff8803aace7 | 1937 | |
cparata | 4:94c5d5546161 | 1938 | return ret; |
cparata | 0:dff8803aace7 | 1939 | } |
cparata | 0:dff8803aace7 | 1940 | |
cparata | 0:dff8803aace7 | 1941 | /** |
cparata | 2:a94816b14e3d | 1942 | * @brief Threshold for tap recognition.[set] |
cparata | 0:dff8803aace7 | 1943 | * |
cparata | 2:a94816b14e3d | 1944 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1945 | * @param val change the values of tap_thsy in reg TAP_THS_Y |
cparata | 2:a94816b14e3d | 1946 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1947 | * |
cparata | 0:dff8803aace7 | 1948 | */ |
cparata | 0:dff8803aace7 | 1949 | int32_t lis2dw12_tap_threshold_y_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 1950 | { |
cparata | 4:94c5d5546161 | 1951 | lis2dw12_tap_ths_y_t reg; |
cparata | 4:94c5d5546161 | 1952 | int32_t ret; |
cparata | 0:dff8803aace7 | 1953 | |
cparata | 4:94c5d5546161 | 1954 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1955 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1956 | reg.tap_thsy = val; |
cparata | 4:94c5d5546161 | 1957 | ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1958 | } |
cparata | 4:94c5d5546161 | 1959 | return ret; |
cparata | 0:dff8803aace7 | 1960 | } |
cparata | 0:dff8803aace7 | 1961 | |
cparata | 0:dff8803aace7 | 1962 | /** |
cparata | 2:a94816b14e3d | 1963 | * @brief Threshold for tap recognition.[get] |
cparata | 0:dff8803aace7 | 1964 | * |
cparata | 2:a94816b14e3d | 1965 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1966 | * @param val change the values of tap_thsy in reg TAP_THS_Y |
cparata | 2:a94816b14e3d | 1967 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1968 | * |
cparata | 0:dff8803aace7 | 1969 | */ |
cparata | 0:dff8803aace7 | 1970 | int32_t lis2dw12_tap_threshold_y_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 1971 | { |
cparata | 4:94c5d5546161 | 1972 | lis2dw12_tap_ths_y_t reg; |
cparata | 4:94c5d5546161 | 1973 | int32_t ret; |
cparata | 0:dff8803aace7 | 1974 | |
cparata | 4:94c5d5546161 | 1975 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1976 | *val = reg.tap_thsy; |
cparata | 0:dff8803aace7 | 1977 | |
cparata | 4:94c5d5546161 | 1978 | return ret; |
cparata | 0:dff8803aace7 | 1979 | } |
cparata | 0:dff8803aace7 | 1980 | |
cparata | 0:dff8803aace7 | 1981 | /** |
cparata | 2:a94816b14e3d | 1982 | * @brief Selection of axis priority for TAP detection.[set] |
cparata | 0:dff8803aace7 | 1983 | * |
cparata | 2:a94816b14e3d | 1984 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1985 | * @param val change the values of tap_prior in reg TAP_THS_Y |
cparata | 2:a94816b14e3d | 1986 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1987 | * |
cparata | 0:dff8803aace7 | 1988 | */ |
cparata | 0:dff8803aace7 | 1989 | int32_t lis2dw12_tap_axis_priority_set(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1990 | lis2dw12_tap_prior_t val) |
cparata | 0:dff8803aace7 | 1991 | { |
cparata | 4:94c5d5546161 | 1992 | lis2dw12_tap_ths_y_t reg; |
cparata | 4:94c5d5546161 | 1993 | int32_t ret; |
cparata | 0:dff8803aace7 | 1994 | |
cparata | 4:94c5d5546161 | 1995 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1996 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 1997 | reg.tap_prior = (uint8_t) val; |
cparata | 4:94c5d5546161 | 1998 | ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 1999 | } |
cparata | 4:94c5d5546161 | 2000 | return ret; |
cparata | 0:dff8803aace7 | 2001 | } |
cparata | 0:dff8803aace7 | 2002 | |
cparata | 0:dff8803aace7 | 2003 | /** |
cparata | 2:a94816b14e3d | 2004 | * @brief Selection of axis priority for TAP detection.[get] |
cparata | 0:dff8803aace7 | 2005 | * |
cparata | 2:a94816b14e3d | 2006 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2007 | * @param val Get the values of tap_prior in reg TAP_THS_Y |
cparata | 2:a94816b14e3d | 2008 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2009 | * |
cparata | 0:dff8803aace7 | 2010 | */ |
cparata | 0:dff8803aace7 | 2011 | int32_t lis2dw12_tap_axis_priority_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 2012 | lis2dw12_tap_prior_t *val) |
cparata | 0:dff8803aace7 | 2013 | { |
cparata | 4:94c5d5546161 | 2014 | lis2dw12_tap_ths_y_t reg; |
cparata | 4:94c5d5546161 | 2015 | int32_t ret; |
cparata | 2:a94816b14e3d | 2016 | |
cparata | 4:94c5d5546161 | 2017 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) ®, 1); |
cparata | 0:dff8803aace7 | 2018 | |
cparata | 4:94c5d5546161 | 2019 | switch (reg.tap_prior) { |
cparata | 4:94c5d5546161 | 2020 | case LIS2DW12_XYZ: |
cparata | 4:94c5d5546161 | 2021 | *val = LIS2DW12_XYZ; |
cparata | 4:94c5d5546161 | 2022 | break; |
cparata | 4:94c5d5546161 | 2023 | case LIS2DW12_YXZ: |
cparata | 4:94c5d5546161 | 2024 | *val = LIS2DW12_YXZ; |
cparata | 4:94c5d5546161 | 2025 | break; |
cparata | 4:94c5d5546161 | 2026 | case LIS2DW12_XZY: |
cparata | 4:94c5d5546161 | 2027 | *val = LIS2DW12_XZY; |
cparata | 4:94c5d5546161 | 2028 | break; |
cparata | 4:94c5d5546161 | 2029 | case LIS2DW12_ZYX: |
cparata | 4:94c5d5546161 | 2030 | *val = LIS2DW12_ZYX; |
cparata | 4:94c5d5546161 | 2031 | break; |
cparata | 4:94c5d5546161 | 2032 | case LIS2DW12_YZX: |
cparata | 4:94c5d5546161 | 2033 | *val = LIS2DW12_YZX; |
cparata | 4:94c5d5546161 | 2034 | break; |
cparata | 4:94c5d5546161 | 2035 | case LIS2DW12_ZXY: |
cparata | 4:94c5d5546161 | 2036 | *val = LIS2DW12_ZXY; |
cparata | 4:94c5d5546161 | 2037 | break; |
cparata | 4:94c5d5546161 | 2038 | default: |
cparata | 4:94c5d5546161 | 2039 | *val = LIS2DW12_XYZ; |
cparata | 4:94c5d5546161 | 2040 | break; |
cparata | 4:94c5d5546161 | 2041 | } |
cparata | 4:94c5d5546161 | 2042 | return ret; |
cparata | 0:dff8803aace7 | 2043 | } |
cparata | 0:dff8803aace7 | 2044 | |
cparata | 0:dff8803aace7 | 2045 | /** |
cparata | 2:a94816b14e3d | 2046 | * @brief Threshold for tap recognition.[set] |
cparata | 0:dff8803aace7 | 2047 | * |
cparata | 2:a94816b14e3d | 2048 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2049 | * @param val change the values of tap_thsz in reg TAP_THS_Z |
cparata | 2:a94816b14e3d | 2050 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2051 | * |
cparata | 0:dff8803aace7 | 2052 | */ |
cparata | 0:dff8803aace7 | 2053 | int32_t lis2dw12_tap_threshold_z_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 2054 | { |
cparata | 4:94c5d5546161 | 2055 | lis2dw12_tap_ths_z_t reg; |
cparata | 4:94c5d5546161 | 2056 | int32_t ret; |
cparata | 0:dff8803aace7 | 2057 | |
cparata | 4:94c5d5546161 | 2058 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2059 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 2060 | reg.tap_thsz = val; |
cparata | 4:94c5d5546161 | 2061 | ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2062 | } |
cparata | 0:dff8803aace7 | 2063 | |
cparata | 4:94c5d5546161 | 2064 | return ret; |
cparata | 0:dff8803aace7 | 2065 | } |
cparata | 0:dff8803aace7 | 2066 | |
cparata | 0:dff8803aace7 | 2067 | /** |
cparata | 2:a94816b14e3d | 2068 | * @brief Threshold for tap recognition.[get] |
cparata | 0:dff8803aace7 | 2069 | * |
cparata | 2:a94816b14e3d | 2070 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2071 | * @param val change the values of tap_thsz in reg TAP_THS_Z |
cparata | 2:a94816b14e3d | 2072 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2073 | * |
cparata | 0:dff8803aace7 | 2074 | */ |
cparata | 0:dff8803aace7 | 2075 | int32_t lis2dw12_tap_threshold_z_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2076 | { |
cparata | 4:94c5d5546161 | 2077 | lis2dw12_tap_ths_z_t reg; |
cparata | 4:94c5d5546161 | 2078 | int32_t ret; |
cparata | 0:dff8803aace7 | 2079 | |
cparata | 4:94c5d5546161 | 2080 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2081 | *val = reg.tap_thsz; |
cparata | 0:dff8803aace7 | 2082 | |
cparata | 4:94c5d5546161 | 2083 | return ret; |
cparata | 0:dff8803aace7 | 2084 | } |
cparata | 0:dff8803aace7 | 2085 | |
cparata | 0:dff8803aace7 | 2086 | /** |
cparata | 2:a94816b14e3d | 2087 | * @brief Enable Z direction in tap recognition.[set] |
cparata | 0:dff8803aace7 | 2088 | * |
cparata | 2:a94816b14e3d | 2089 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2090 | * @param val change the values of tap_z_en in reg TAP_THS_Z |
cparata | 2:a94816b14e3d | 2091 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2092 | * |
cparata | 0:dff8803aace7 | 2093 | */ |
cparata | 0:dff8803aace7 | 2094 | int32_t lis2dw12_tap_detection_on_z_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 2095 | { |
cparata | 4:94c5d5546161 | 2096 | lis2dw12_tap_ths_z_t reg; |
cparata | 4:94c5d5546161 | 2097 | int32_t ret; |
cparata | 0:dff8803aace7 | 2098 | |
cparata | 4:94c5d5546161 | 2099 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2100 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 2101 | reg.tap_z_en = val; |
cparata | 4:94c5d5546161 | 2102 | ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2103 | } |
cparata | 4:94c5d5546161 | 2104 | return ret; |
cparata | 0:dff8803aace7 | 2105 | } |
cparata | 0:dff8803aace7 | 2106 | |
cparata | 0:dff8803aace7 | 2107 | /** |
cparata | 2:a94816b14e3d | 2108 | * @brief Enable Z direction in tap recognition.[get] |
cparata | 0:dff8803aace7 | 2109 | * |
cparata | 2:a94816b14e3d | 2110 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2111 | * @param val change the values of tap_z_en in reg TAP_THS_Z |
cparata | 2:a94816b14e3d | 2112 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2113 | * |
cparata | 0:dff8803aace7 | 2114 | */ |
cparata | 0:dff8803aace7 | 2115 | int32_t lis2dw12_tap_detection_on_z_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2116 | { |
cparata | 4:94c5d5546161 | 2117 | lis2dw12_tap_ths_z_t reg; |
cparata | 4:94c5d5546161 | 2118 | int32_t ret; |
cparata | 0:dff8803aace7 | 2119 | |
cparata | 4:94c5d5546161 | 2120 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2121 | *val = reg.tap_z_en; |
cparata | 0:dff8803aace7 | 2122 | |
cparata | 4:94c5d5546161 | 2123 | return ret; |
cparata | 0:dff8803aace7 | 2124 | } |
cparata | 0:dff8803aace7 | 2125 | |
cparata | 0:dff8803aace7 | 2126 | /** |
cparata | 2:a94816b14e3d | 2127 | * @brief Enable Y direction in tap recognition.[set] |
cparata | 0:dff8803aace7 | 2128 | * |
cparata | 2:a94816b14e3d | 2129 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2130 | * @param val change the values of tap_y_en in reg TAP_THS_Z |
cparata | 2:a94816b14e3d | 2131 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2132 | * |
cparata | 0:dff8803aace7 | 2133 | */ |
cparata | 0:dff8803aace7 | 2134 | int32_t lis2dw12_tap_detection_on_y_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 2135 | { |
cparata | 4:94c5d5546161 | 2136 | lis2dw12_tap_ths_z_t reg; |
cparata | 4:94c5d5546161 | 2137 | int32_t ret; |
cparata | 0:dff8803aace7 | 2138 | |
cparata | 4:94c5d5546161 | 2139 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2140 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 2141 | reg.tap_y_en = val; |
cparata | 4:94c5d5546161 | 2142 | ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2143 | } |
cparata | 4:94c5d5546161 | 2144 | return ret; |
cparata | 0:dff8803aace7 | 2145 | } |
cparata | 0:dff8803aace7 | 2146 | |
cparata | 0:dff8803aace7 | 2147 | /** |
cparata | 2:a94816b14e3d | 2148 | * @brief Enable Y direction in tap recognition.[get] |
cparata | 0:dff8803aace7 | 2149 | * |
cparata | 2:a94816b14e3d | 2150 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2151 | * @param val change the values of tap_y_en in reg TAP_THS_Z |
cparata | 2:a94816b14e3d | 2152 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2153 | * |
cparata | 0:dff8803aace7 | 2154 | */ |
cparata | 0:dff8803aace7 | 2155 | int32_t lis2dw12_tap_detection_on_y_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2156 | { |
cparata | 4:94c5d5546161 | 2157 | lis2dw12_tap_ths_z_t reg; |
cparata | 4:94c5d5546161 | 2158 | int32_t ret; |
cparata | 0:dff8803aace7 | 2159 | |
cparata | 4:94c5d5546161 | 2160 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2161 | *val = reg.tap_y_en; |
cparata | 0:dff8803aace7 | 2162 | |
cparata | 4:94c5d5546161 | 2163 | return ret; |
cparata | 0:dff8803aace7 | 2164 | } |
cparata | 0:dff8803aace7 | 2165 | |
cparata | 0:dff8803aace7 | 2166 | /** |
cparata | 2:a94816b14e3d | 2167 | * @brief Enable X direction in tap recognition.[set] |
cparata | 0:dff8803aace7 | 2168 | * |
cparata | 2:a94816b14e3d | 2169 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2170 | * @param val change the values of tap_x_en in reg TAP_THS_Z |
cparata | 2:a94816b14e3d | 2171 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2172 | * |
cparata | 0:dff8803aace7 | 2173 | */ |
cparata | 0:dff8803aace7 | 2174 | int32_t lis2dw12_tap_detection_on_x_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 2175 | { |
cparata | 4:94c5d5546161 | 2176 | lis2dw12_tap_ths_z_t reg; |
cparata | 4:94c5d5546161 | 2177 | int32_t ret; |
cparata | 0:dff8803aace7 | 2178 | |
cparata | 4:94c5d5546161 | 2179 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2180 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 2181 | reg.tap_x_en = val; |
cparata | 4:94c5d5546161 | 2182 | ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2183 | } |
cparata | 4:94c5d5546161 | 2184 | return ret; |
cparata | 0:dff8803aace7 | 2185 | } |
cparata | 0:dff8803aace7 | 2186 | |
cparata | 0:dff8803aace7 | 2187 | /** |
cparata | 2:a94816b14e3d | 2188 | * @brief Enable X direction in tap recognition.[get] |
cparata | 0:dff8803aace7 | 2189 | * |
cparata | 2:a94816b14e3d | 2190 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2191 | * @param val change the values of tap_x_en in reg TAP_THS_Z |
cparata | 2:a94816b14e3d | 2192 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2193 | * |
cparata | 0:dff8803aace7 | 2194 | */ |
cparata | 0:dff8803aace7 | 2195 | int32_t lis2dw12_tap_detection_on_x_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2196 | { |
cparata | 4:94c5d5546161 | 2197 | lis2dw12_tap_ths_z_t reg; |
cparata | 4:94c5d5546161 | 2198 | int32_t ret; |
cparata | 0:dff8803aace7 | 2199 | |
cparata | 4:94c5d5546161 | 2200 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2201 | *val = reg.tap_x_en; |
cparata | 0:dff8803aace7 | 2202 | |
cparata | 4:94c5d5546161 | 2203 | return ret; |
cparata | 0:dff8803aace7 | 2204 | } |
cparata | 0:dff8803aace7 | 2205 | |
cparata | 0:dff8803aace7 | 2206 | /** |
cparata | 2:a94816b14e3d | 2207 | * @brief Maximum duration is the maximum time of an overthreshold signal |
cparata | 2:a94816b14e3d | 2208 | * detection to be recognized as a tap event. The default value |
cparata | 2:a94816b14e3d | 2209 | * of these bits is 00b which corresponds to 4*ODR_XL time. |
cparata | 2:a94816b14e3d | 2210 | * If the SHOCK[1:0] bits are set to a different value, 1LSB |
cparata | 2:a94816b14e3d | 2211 | * corresponds to 8*ODR_XL time.[set] |
cparata | 0:dff8803aace7 | 2212 | * |
cparata | 2:a94816b14e3d | 2213 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2214 | * @param val change the values of shock in reg INT_DUR |
cparata | 2:a94816b14e3d | 2215 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2216 | * |
cparata | 0:dff8803aace7 | 2217 | */ |
cparata | 0:dff8803aace7 | 2218 | int32_t lis2dw12_tap_shock_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 2219 | { |
cparata | 4:94c5d5546161 | 2220 | lis2dw12_int_dur_t reg; |
cparata | 4:94c5d5546161 | 2221 | int32_t ret; |
cparata | 0:dff8803aace7 | 2222 | |
cparata | 4:94c5d5546161 | 2223 | ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2224 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 2225 | reg.shock = val; |
cparata | 4:94c5d5546161 | 2226 | ret = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2227 | } |
cparata | 0:dff8803aace7 | 2228 | |
cparata | 4:94c5d5546161 | 2229 | return ret; |
cparata | 0:dff8803aace7 | 2230 | } |
cparata | 0:dff8803aace7 | 2231 | |
cparata | 0:dff8803aace7 | 2232 | /** |
cparata | 2:a94816b14e3d | 2233 | * @brief Maximum duration is the maximum time of an overthreshold signal |
cparata | 2:a94816b14e3d | 2234 | * detection to be recognized as a tap event. The default value |
cparata | 2:a94816b14e3d | 2235 | * of these bits is 00b which corresponds to 4*ODR_XL time. |
cparata | 2:a94816b14e3d | 2236 | * If the SHOCK[1:0] bits are set to a different value, 1LSB |
cparata | 2:a94816b14e3d | 2237 | * corresponds to 8*ODR_XL time.[get] |
cparata | 0:dff8803aace7 | 2238 | * |
cparata | 2:a94816b14e3d | 2239 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2240 | * @param val change the values of shock in reg INT_DUR |
cparata | 2:a94816b14e3d | 2241 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2242 | * |
cparata | 0:dff8803aace7 | 2243 | */ |
cparata | 0:dff8803aace7 | 2244 | int32_t lis2dw12_tap_shock_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2245 | { |
cparata | 4:94c5d5546161 | 2246 | lis2dw12_int_dur_t reg; |
cparata | 4:94c5d5546161 | 2247 | int32_t ret; |
cparata | 0:dff8803aace7 | 2248 | |
cparata | 4:94c5d5546161 | 2249 | ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2250 | *val = reg.shock; |
cparata | 0:dff8803aace7 | 2251 | |
cparata | 4:94c5d5546161 | 2252 | return ret; |
cparata | 0:dff8803aace7 | 2253 | } |
cparata | 0:dff8803aace7 | 2254 | |
cparata | 0:dff8803aace7 | 2255 | /** |
cparata | 4:94c5d5546161 | 2256 | * @brief Quiet time is the time after the first detected tap in which |
cparata | 2:a94816b14e3d | 2257 | * there must not be any overthreshold event. |
cparata | 4:94c5d5546161 | 2258 | * The default value of these bits is 00b which corresponds |
cparata | 2:a94816b14e3d | 2259 | * to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different |
cparata | 2:a94816b14e3d | 2260 | * value, 1LSB corresponds to 4*ODR_XL time.[set] |
cparata | 0:dff8803aace7 | 2261 | * |
cparata | 2:a94816b14e3d | 2262 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2263 | * @param val change the values of quiet in reg INT_DUR |
cparata | 2:a94816b14e3d | 2264 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2265 | * |
cparata | 0:dff8803aace7 | 2266 | */ |
cparata | 0:dff8803aace7 | 2267 | int32_t lis2dw12_tap_quiet_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 2268 | { |
cparata | 4:94c5d5546161 | 2269 | lis2dw12_int_dur_t reg; |
cparata | 4:94c5d5546161 | 2270 | int32_t ret; |
cparata | 0:dff8803aace7 | 2271 | |
cparata | 4:94c5d5546161 | 2272 | ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2273 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 2274 | reg.quiet = val; |
cparata | 4:94c5d5546161 | 2275 | ret = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2276 | } |
cparata | 4:94c5d5546161 | 2277 | return ret; |
cparata | 0:dff8803aace7 | 2278 | } |
cparata | 0:dff8803aace7 | 2279 | |
cparata | 0:dff8803aace7 | 2280 | /** |
cparata | 4:94c5d5546161 | 2281 | * @brief Quiet time is the time after the first detected tap in which |
cparata | 2:a94816b14e3d | 2282 | * there must not be any overthreshold event. |
cparata | 4:94c5d5546161 | 2283 | * The default value of these bits is 00b which corresponds |
cparata | 2:a94816b14e3d | 2284 | * to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different |
cparata | 2:a94816b14e3d | 2285 | * value, 1LSB corresponds to 4*ODR_XL time.[get] |
cparata | 0:dff8803aace7 | 2286 | * |
cparata | 2:a94816b14e3d | 2287 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2288 | * @param val change the values of quiet in reg INT_DUR |
cparata | 2:a94816b14e3d | 2289 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2290 | * |
cparata | 0:dff8803aace7 | 2291 | */ |
cparata | 0:dff8803aace7 | 2292 | int32_t lis2dw12_tap_quiet_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2293 | { |
cparata | 4:94c5d5546161 | 2294 | lis2dw12_int_dur_t reg; |
cparata | 4:94c5d5546161 | 2295 | int32_t ret; |
cparata | 0:dff8803aace7 | 2296 | |
cparata | 4:94c5d5546161 | 2297 | ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2298 | *val = reg.quiet; |
cparata | 0:dff8803aace7 | 2299 | |
cparata | 4:94c5d5546161 | 2300 | return ret; |
cparata | 0:dff8803aace7 | 2301 | } |
cparata | 0:dff8803aace7 | 2302 | |
cparata | 0:dff8803aace7 | 2303 | /** |
cparata | 4:94c5d5546161 | 2304 | * @brief When double tap recognition is enabled, this register expresses |
cparata | 4:94c5d5546161 | 2305 | * the maximum time between two consecutive detected taps to |
cparata | 2:a94816b14e3d | 2306 | * determine a double tap event. |
cparata | 4:94c5d5546161 | 2307 | * The default value of these bits is 0000b which corresponds |
cparata | 4:94c5d5546161 | 2308 | * to 16*ODR_XL time. If the DUR[3:0] bits are set to a different |
cparata | 2:a94816b14e3d | 2309 | * value, 1LSB corresponds to 32*ODR_XL time.[set] |
cparata | 0:dff8803aace7 | 2310 | * |
cparata | 2:a94816b14e3d | 2311 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2312 | * @param val change the values of latency in reg INT_DUR |
cparata | 2:a94816b14e3d | 2313 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2314 | * |
cparata | 0:dff8803aace7 | 2315 | */ |
cparata | 0:dff8803aace7 | 2316 | int32_t lis2dw12_tap_dur_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 2317 | { |
cparata | 4:94c5d5546161 | 2318 | lis2dw12_int_dur_t reg; |
cparata | 4:94c5d5546161 | 2319 | int32_t ret; |
cparata | 0:dff8803aace7 | 2320 | |
cparata | 4:94c5d5546161 | 2321 | ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2322 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 2323 | reg.latency = val; |
cparata | 4:94c5d5546161 | 2324 | ret = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2325 | } |
cparata | 4:94c5d5546161 | 2326 | return ret; |
cparata | 0:dff8803aace7 | 2327 | } |
cparata | 0:dff8803aace7 | 2328 | |
cparata | 0:dff8803aace7 | 2329 | /** |
cparata | 4:94c5d5546161 | 2330 | * @brief When double tap recognition is enabled, this register expresses |
cparata | 4:94c5d5546161 | 2331 | * the maximum time between two consecutive detected taps to |
cparata | 2:a94816b14e3d | 2332 | * determine a double tap event. |
cparata | 4:94c5d5546161 | 2333 | * The default value of these bits is 0000b which corresponds |
cparata | 4:94c5d5546161 | 2334 | * to 16*ODR_XL time. If the DUR[3:0] bits are set to a different |
cparata | 2:a94816b14e3d | 2335 | * value, 1LSB corresponds to 32*ODR_XL time.[get] |
cparata | 0:dff8803aace7 | 2336 | * |
cparata | 2:a94816b14e3d | 2337 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2338 | * @param val change the values of latency in reg INT_DUR |
cparata | 2:a94816b14e3d | 2339 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2340 | * |
cparata | 0:dff8803aace7 | 2341 | */ |
cparata | 0:dff8803aace7 | 2342 | int32_t lis2dw12_tap_dur_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2343 | { |
cparata | 4:94c5d5546161 | 2344 | lis2dw12_int_dur_t reg; |
cparata | 4:94c5d5546161 | 2345 | int32_t ret; |
cparata | 0:dff8803aace7 | 2346 | |
cparata | 4:94c5d5546161 | 2347 | ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2348 | *val = reg.latency; |
cparata | 0:dff8803aace7 | 2349 | |
cparata | 4:94c5d5546161 | 2350 | return ret; |
cparata | 0:dff8803aace7 | 2351 | } |
cparata | 0:dff8803aace7 | 2352 | |
cparata | 0:dff8803aace7 | 2353 | /** |
cparata | 2:a94816b14e3d | 2354 | * @brief Single/double-tap event enable.[set] |
cparata | 0:dff8803aace7 | 2355 | * |
cparata | 2:a94816b14e3d | 2356 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2357 | * @param val change the values of single_double_tap in reg WAKE_UP_THS |
cparata | 2:a94816b14e3d | 2358 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2359 | * |
cparata | 0:dff8803aace7 | 2360 | */ |
cparata | 0:dff8803aace7 | 2361 | int32_t lis2dw12_tap_mode_set(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 2362 | lis2dw12_single_double_tap_t val) |
cparata | 0:dff8803aace7 | 2363 | { |
cparata | 4:94c5d5546161 | 2364 | lis2dw12_wake_up_ths_t reg; |
cparata | 4:94c5d5546161 | 2365 | int32_t ret; |
cparata | 0:dff8803aace7 | 2366 | |
cparata | 4:94c5d5546161 | 2367 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2368 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 2369 | reg.single_double_tap = (uint8_t) val; |
cparata | 4:94c5d5546161 | 2370 | ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2371 | } |
cparata | 4:94c5d5546161 | 2372 | return ret; |
cparata | 0:dff8803aace7 | 2373 | } |
cparata | 0:dff8803aace7 | 2374 | |
cparata | 0:dff8803aace7 | 2375 | /** |
cparata | 2:a94816b14e3d | 2376 | * @brief Single/double-tap event enable.[get] |
cparata | 0:dff8803aace7 | 2377 | * |
cparata | 2:a94816b14e3d | 2378 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2379 | * @param val Get the values of single_double_tap in reg WAKE_UP_THS |
cparata | 2:a94816b14e3d | 2380 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2381 | * |
cparata | 0:dff8803aace7 | 2382 | */ |
cparata | 0:dff8803aace7 | 2383 | int32_t lis2dw12_tap_mode_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 2384 | lis2dw12_single_double_tap_t *val) |
cparata | 0:dff8803aace7 | 2385 | { |
cparata | 4:94c5d5546161 | 2386 | lis2dw12_wake_up_ths_t reg; |
cparata | 4:94c5d5546161 | 2387 | int32_t ret; |
cparata | 2:a94816b14e3d | 2388 | |
cparata | 4:94c5d5546161 | 2389 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1); |
cparata | 0:dff8803aace7 | 2390 | |
cparata | 4:94c5d5546161 | 2391 | switch (reg.single_double_tap) { |
cparata | 4:94c5d5546161 | 2392 | case LIS2DW12_ONLY_SINGLE: |
cparata | 4:94c5d5546161 | 2393 | *val = LIS2DW12_ONLY_SINGLE; |
cparata | 4:94c5d5546161 | 2394 | break; |
cparata | 4:94c5d5546161 | 2395 | case LIS2DW12_BOTH_SINGLE_DOUBLE: |
cparata | 4:94c5d5546161 | 2396 | *val = LIS2DW12_BOTH_SINGLE_DOUBLE; |
cparata | 4:94c5d5546161 | 2397 | break; |
cparata | 4:94c5d5546161 | 2398 | default: |
cparata | 4:94c5d5546161 | 2399 | *val = LIS2DW12_ONLY_SINGLE; |
cparata | 4:94c5d5546161 | 2400 | break; |
cparata | 4:94c5d5546161 | 2401 | } |
cparata | 0:dff8803aace7 | 2402 | |
cparata | 4:94c5d5546161 | 2403 | return ret; |
cparata | 0:dff8803aace7 | 2404 | } |
cparata | 0:dff8803aace7 | 2405 | |
cparata | 0:dff8803aace7 | 2406 | /** |
cparata | 2:a94816b14e3d | 2407 | * @brief Read the tap / double tap source register.[get] |
cparata | 0:dff8803aace7 | 2408 | * |
cparata | 2:a94816b14e3d | 2409 | * @param ctx read / write interface definitions |
cparata | 4:94c5d5546161 | 2410 | * @param lis2dw12_tap_src: union of registers from TAP_SRC to |
cparata | 2:a94816b14e3d | 2411 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2412 | * |
cparata | 0:dff8803aace7 | 2413 | */ |
cparata | 0:dff8803aace7 | 2414 | int32_t lis2dw12_tap_src_get(lis2dw12_ctx_t *ctx, lis2dw12_tap_src_t *val) |
cparata | 0:dff8803aace7 | 2415 | { |
cparata | 4:94c5d5546161 | 2416 | int32_t ret; |
cparata | 4:94c5d5546161 | 2417 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_SRC, (uint8_t *) val, 1); |
cparata | 4:94c5d5546161 | 2418 | return ret; |
cparata | 0:dff8803aace7 | 2419 | } |
cparata | 2:a94816b14e3d | 2420 | |
cparata | 0:dff8803aace7 | 2421 | /** |
cparata | 0:dff8803aace7 | 2422 | * @} |
cparata | 2:a94816b14e3d | 2423 | * |
cparata | 0:dff8803aace7 | 2424 | */ |
cparata | 0:dff8803aace7 | 2425 | |
cparata | 0:dff8803aace7 | 2426 | /** |
cparata | 2:a94816b14e3d | 2427 | * @defgroup LIS2DW12_Six_Position_Detection(6D/4D) |
cparata | 2:a94816b14e3d | 2428 | * @brief This section groups all the functions concerning six |
cparata | 2:a94816b14e3d | 2429 | * position detection (6D). |
cparata | 0:dff8803aace7 | 2430 | * @{ |
cparata | 2:a94816b14e3d | 2431 | * |
cparata | 0:dff8803aace7 | 2432 | */ |
cparata | 0:dff8803aace7 | 2433 | |
cparata | 0:dff8803aace7 | 2434 | /** |
cparata | 4:94c5d5546161 | 2435 | * @brief Threshold for 4D/6D function.[set] |
cparata | 0:dff8803aace7 | 2436 | * |
cparata | 2:a94816b14e3d | 2437 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2438 | * @param val change the values of 6d_ths in reg TAP_THS_X |
cparata | 2:a94816b14e3d | 2439 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2440 | * |
cparata | 0:dff8803aace7 | 2441 | */ |
cparata | 0:dff8803aace7 | 2442 | int32_t lis2dw12_6d_threshold_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 2443 | { |
cparata | 4:94c5d5546161 | 2444 | lis2dw12_tap_ths_x_t reg; |
cparata | 4:94c5d5546161 | 2445 | int32_t ret; |
cparata | 0:dff8803aace7 | 2446 | |
cparata | 4:94c5d5546161 | 2447 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2448 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 2449 | reg._6d_ths = val; |
cparata | 4:94c5d5546161 | 2450 | ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2451 | } |
cparata | 4:94c5d5546161 | 2452 | return ret; |
cparata | 0:dff8803aace7 | 2453 | } |
cparata | 0:dff8803aace7 | 2454 | |
cparata | 0:dff8803aace7 | 2455 | /** |
cparata | 2:a94816b14e3d | 2456 | * @brief Threshold for 4D/6D function.[get] |
cparata | 0:dff8803aace7 | 2457 | * |
cparata | 2:a94816b14e3d | 2458 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2459 | * @param val change the values of 6d_ths in reg TAP_THS_X |
cparata | 2:a94816b14e3d | 2460 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2461 | * |
cparata | 0:dff8803aace7 | 2462 | */ |
cparata | 0:dff8803aace7 | 2463 | int32_t lis2dw12_6d_threshold_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2464 | { |
cparata | 4:94c5d5546161 | 2465 | lis2dw12_tap_ths_x_t reg; |
cparata | 4:94c5d5546161 | 2466 | int32_t ret; |
cparata | 0:dff8803aace7 | 2467 | |
cparata | 4:94c5d5546161 | 2468 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2469 | *val = reg._6d_ths; |
cparata | 0:dff8803aace7 | 2470 | |
cparata | 4:94c5d5546161 | 2471 | return ret; |
cparata | 0:dff8803aace7 | 2472 | } |
cparata | 0:dff8803aace7 | 2473 | |
cparata | 0:dff8803aace7 | 2474 | /** |
cparata | 2:a94816b14e3d | 2475 | * @brief 4D orientation detection enable.[set] |
cparata | 0:dff8803aace7 | 2476 | * |
cparata | 2:a94816b14e3d | 2477 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2478 | * @param val change the values of 4d_en in reg TAP_THS_X |
cparata | 2:a94816b14e3d | 2479 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2480 | * |
cparata | 0:dff8803aace7 | 2481 | */ |
cparata | 0:dff8803aace7 | 2482 | int32_t lis2dw12_4d_mode_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 2483 | { |
cparata | 4:94c5d5546161 | 2484 | lis2dw12_tap_ths_x_t reg; |
cparata | 4:94c5d5546161 | 2485 | int32_t ret; |
cparata | 0:dff8803aace7 | 2486 | |
cparata | 4:94c5d5546161 | 2487 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2488 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 2489 | reg._4d_en = val; |
cparata | 4:94c5d5546161 | 2490 | ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2491 | } |
cparata | 0:dff8803aace7 | 2492 | |
cparata | 4:94c5d5546161 | 2493 | return ret; |
cparata | 0:dff8803aace7 | 2494 | } |
cparata | 0:dff8803aace7 | 2495 | |
cparata | 0:dff8803aace7 | 2496 | /** |
cparata | 2:a94816b14e3d | 2497 | * @brief 4D orientation detection enable.[get] |
cparata | 0:dff8803aace7 | 2498 | * |
cparata | 2:a94816b14e3d | 2499 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2500 | * @param val change the values of 4d_en in reg TAP_THS_X |
cparata | 2:a94816b14e3d | 2501 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2502 | * |
cparata | 0:dff8803aace7 | 2503 | */ |
cparata | 0:dff8803aace7 | 2504 | int32_t lis2dw12_4d_mode_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2505 | { |
cparata | 4:94c5d5546161 | 2506 | lis2dw12_tap_ths_x_t reg; |
cparata | 4:94c5d5546161 | 2507 | int32_t ret; |
cparata | 0:dff8803aace7 | 2508 | |
cparata | 4:94c5d5546161 | 2509 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2510 | *val = reg._4d_en; |
cparata | 0:dff8803aace7 | 2511 | |
cparata | 4:94c5d5546161 | 2512 | return ret; |
cparata | 0:dff8803aace7 | 2513 | } |
cparata | 0:dff8803aace7 | 2514 | |
cparata | 0:dff8803aace7 | 2515 | /** |
cparata | 2:a94816b14e3d | 2516 | * @brief Read the 6D tap source register.[get] |
cparata | 0:dff8803aace7 | 2517 | * |
cparata | 2:a94816b14e3d | 2518 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2519 | * @param val union of registers from SIXD_SRC |
cparata | 2:a94816b14e3d | 2520 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2521 | * |
cparata | 0:dff8803aace7 | 2522 | */ |
cparata | 0:dff8803aace7 | 2523 | int32_t lis2dw12_6d_src_get(lis2dw12_ctx_t *ctx, lis2dw12_sixd_src_t *val) |
cparata | 0:dff8803aace7 | 2524 | { |
cparata | 4:94c5d5546161 | 2525 | int32_t ret; |
cparata | 4:94c5d5546161 | 2526 | ret = lis2dw12_read_reg(ctx, LIS2DW12_SIXD_SRC, (uint8_t *) val, 1); |
cparata | 4:94c5d5546161 | 2527 | return ret; |
cparata | 0:dff8803aace7 | 2528 | } |
cparata | 0:dff8803aace7 | 2529 | /** |
cparata | 2:a94816b14e3d | 2530 | * @brief Data sent to 6D interrupt function.[set] |
cparata | 0:dff8803aace7 | 2531 | * |
cparata | 2:a94816b14e3d | 2532 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2533 | * @param val change the values of lpass_on6d in reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 2534 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2535 | * |
cparata | 0:dff8803aace7 | 2536 | */ |
cparata | 0:dff8803aace7 | 2537 | int32_t lis2dw12_6d_feed_data_set(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 2538 | lis2dw12_lpass_on6d_t val) |
cparata | 0:dff8803aace7 | 2539 | { |
cparata | 4:94c5d5546161 | 2540 | lis2dw12_ctrl_reg7_t reg; |
cparata | 4:94c5d5546161 | 2541 | int32_t ret; |
cparata | 0:dff8803aace7 | 2542 | |
cparata | 4:94c5d5546161 | 2543 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2544 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 2545 | reg.lpass_on6d = (uint8_t) val; |
cparata | 4:94c5d5546161 | 2546 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2547 | } |
cparata | 4:94c5d5546161 | 2548 | return ret; |
cparata | 0:dff8803aace7 | 2549 | } |
cparata | 0:dff8803aace7 | 2550 | |
cparata | 0:dff8803aace7 | 2551 | /** |
cparata | 2:a94816b14e3d | 2552 | * @brief Data sent to 6D interrupt function.[get] |
cparata | 0:dff8803aace7 | 2553 | * |
cparata | 2:a94816b14e3d | 2554 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2555 | * @param val Get the values of lpass_on6d in reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 2556 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2557 | * |
cparata | 0:dff8803aace7 | 2558 | */ |
cparata | 0:dff8803aace7 | 2559 | int32_t lis2dw12_6d_feed_data_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 2560 | lis2dw12_lpass_on6d_t *val) |
cparata | 0:dff8803aace7 | 2561 | { |
cparata | 4:94c5d5546161 | 2562 | lis2dw12_ctrl_reg7_t reg; |
cparata | 4:94c5d5546161 | 2563 | int32_t ret; |
cparata | 2:a94816b14e3d | 2564 | |
cparata | 4:94c5d5546161 | 2565 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); |
cparata | 0:dff8803aace7 | 2566 | |
cparata | 4:94c5d5546161 | 2567 | switch (reg.lpass_on6d) { |
cparata | 4:94c5d5546161 | 2568 | case LIS2DW12_ODR_DIV_2_FEED: |
cparata | 4:94c5d5546161 | 2569 | *val = LIS2DW12_ODR_DIV_2_FEED; |
cparata | 4:94c5d5546161 | 2570 | break; |
cparata | 4:94c5d5546161 | 2571 | case LIS2DW12_LPF2_FEED: |
cparata | 4:94c5d5546161 | 2572 | *val = LIS2DW12_LPF2_FEED; |
cparata | 4:94c5d5546161 | 2573 | break; |
cparata | 4:94c5d5546161 | 2574 | default: |
cparata | 4:94c5d5546161 | 2575 | *val = LIS2DW12_ODR_DIV_2_FEED; |
cparata | 4:94c5d5546161 | 2576 | break; |
cparata | 4:94c5d5546161 | 2577 | } |
cparata | 4:94c5d5546161 | 2578 | return ret; |
cparata | 0:dff8803aace7 | 2579 | } |
cparata | 0:dff8803aace7 | 2580 | |
cparata | 0:dff8803aace7 | 2581 | /** |
cparata | 0:dff8803aace7 | 2582 | * @} |
cparata | 2:a94816b14e3d | 2583 | * |
cparata | 0:dff8803aace7 | 2584 | */ |
cparata | 0:dff8803aace7 | 2585 | |
cparata | 0:dff8803aace7 | 2586 | /** |
cparata | 2:a94816b14e3d | 2587 | * @defgroup LIS2DW12_Free_Fall |
cparata | 2:a94816b14e3d | 2588 | * @brief This section group all the functions concerning |
cparata | 2:a94816b14e3d | 2589 | * the free fall detection. |
cparata | 0:dff8803aace7 | 2590 | * @{ |
cparata | 2:a94816b14e3d | 2591 | * |
cparata | 0:dff8803aace7 | 2592 | */ |
cparata | 0:dff8803aace7 | 2593 | |
cparata | 0:dff8803aace7 | 2594 | /** |
cparata | 2:a94816b14e3d | 2595 | * @brief Wake up duration event(1LSb = 1 / ODR).[set] |
cparata | 0:dff8803aace7 | 2596 | * |
cparata | 2:a94816b14e3d | 2597 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2598 | * @param val change the values of ff_dur in reg |
cparata | 2:a94816b14e3d | 2599 | * WAKE_UP_DUR /F REE_FALL |
cparata | 2:a94816b14e3d | 2600 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2601 | * |
cparata | 0:dff8803aace7 | 2602 | */ |
cparata | 0:dff8803aace7 | 2603 | int32_t lis2dw12_ff_dur_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 2604 | { |
cparata | 4:94c5d5546161 | 2605 | lis2dw12_wake_up_dur_t wake_up_dur; |
cparata | 4:94c5d5546161 | 2606 | lis2dw12_free_fall_t free_fall; |
cparata | 4:94c5d5546161 | 2607 | int32_t ret; |
cparata | 0:dff8803aace7 | 2608 | |
cparata | 4:94c5d5546161 | 2609 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) &wake_up_dur, 1); |
cparata | 4:94c5d5546161 | 2610 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 2611 | ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL, (uint8_t *) &free_fall, 1); |
cparata | 4:94c5d5546161 | 2612 | } |
cparata | 4:94c5d5546161 | 2613 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 2614 | wake_up_dur.ff_dur = ((uint8_t) val & 0x20U) >> 5; |
cparata | 4:94c5d5546161 | 2615 | free_fall.ff_dur = (uint8_t) val & 0x1FU; |
cparata | 4:94c5d5546161 | 2616 | ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) &wake_up_dur, 1); |
cparata | 4:94c5d5546161 | 2617 | } |
cparata | 4:94c5d5546161 | 2618 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 2619 | ret = lis2dw12_write_reg(ctx, LIS2DW12_FREE_FALL, (uint8_t *) &free_fall, 1); |
cparata | 4:94c5d5546161 | 2620 | } |
cparata | 4:94c5d5546161 | 2621 | |
cparata | 4:94c5d5546161 | 2622 | return ret; |
cparata | 0:dff8803aace7 | 2623 | } |
cparata | 0:dff8803aace7 | 2624 | |
cparata | 0:dff8803aace7 | 2625 | /** |
cparata | 2:a94816b14e3d | 2626 | * @brief Wake up duration event(1LSb = 1 / ODR).[get] |
cparata | 0:dff8803aace7 | 2627 | * |
cparata | 2:a94816b14e3d | 2628 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2629 | * @param val change the values of ff_dur in |
cparata | 4:94c5d5546161 | 2630 | * reg WAKE_UP_DUR /F REE_FALL |
cparata | 2:a94816b14e3d | 2631 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2632 | * |
cparata | 0:dff8803aace7 | 2633 | */ |
cparata | 0:dff8803aace7 | 2634 | int32_t lis2dw12_ff_dur_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2635 | { |
cparata | 4:94c5d5546161 | 2636 | lis2dw12_wake_up_dur_t wake_up_dur; |
cparata | 4:94c5d5546161 | 2637 | lis2dw12_free_fall_t free_fall; |
cparata | 4:94c5d5546161 | 2638 | int32_t ret; |
cparata | 4:94c5d5546161 | 2639 | |
cparata | 4:94c5d5546161 | 2640 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) &wake_up_dur, 1); |
cparata | 4:94c5d5546161 | 2641 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 2642 | ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL, (uint8_t *) &free_fall, 1); |
cparata | 4:94c5d5546161 | 2643 | *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; |
cparata | 4:94c5d5546161 | 2644 | } |
cparata | 4:94c5d5546161 | 2645 | return ret; |
cparata | 0:dff8803aace7 | 2646 | } |
cparata | 0:dff8803aace7 | 2647 | |
cparata | 0:dff8803aace7 | 2648 | /** |
cparata | 2:a94816b14e3d | 2649 | * @brief Free fall threshold setting.[set] |
cparata | 0:dff8803aace7 | 2650 | * |
cparata | 2:a94816b14e3d | 2651 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2652 | * @param val change the values of ff_ths in reg FREE_FALL |
cparata | 2:a94816b14e3d | 2653 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2654 | * |
cparata | 0:dff8803aace7 | 2655 | */ |
cparata | 0:dff8803aace7 | 2656 | int32_t lis2dw12_ff_threshold_set(lis2dw12_ctx_t *ctx, lis2dw12_ff_ths_t val) |
cparata | 0:dff8803aace7 | 2657 | { |
cparata | 4:94c5d5546161 | 2658 | lis2dw12_free_fall_t reg; |
cparata | 4:94c5d5546161 | 2659 | int32_t ret; |
cparata | 0:dff8803aace7 | 2660 | |
cparata | 4:94c5d5546161 | 2661 | ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2662 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 2663 | reg.ff_ths = (uint8_t) val; |
cparata | 4:94c5d5546161 | 2664 | ret = lis2dw12_write_reg(ctx, LIS2DW12_FREE_FALL, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2665 | } |
cparata | 0:dff8803aace7 | 2666 | |
cparata | 4:94c5d5546161 | 2667 | return ret; |
cparata | 0:dff8803aace7 | 2668 | } |
cparata | 0:dff8803aace7 | 2669 | |
cparata | 0:dff8803aace7 | 2670 | /** |
cparata | 2:a94816b14e3d | 2671 | * @brief Free fall threshold setting.[get] |
cparata | 0:dff8803aace7 | 2672 | * |
cparata | 2:a94816b14e3d | 2673 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2674 | * @param val Get the values of ff_ths in reg FREE_FALL |
cparata | 2:a94816b14e3d | 2675 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2676 | * |
cparata | 0:dff8803aace7 | 2677 | */ |
cparata | 0:dff8803aace7 | 2678 | int32_t lis2dw12_ff_threshold_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 2679 | lis2dw12_ff_ths_t *val) |
cparata | 0:dff8803aace7 | 2680 | { |
cparata | 4:94c5d5546161 | 2681 | lis2dw12_free_fall_t reg; |
cparata | 4:94c5d5546161 | 2682 | int32_t ret; |
cparata | 2:a94816b14e3d | 2683 | |
cparata | 4:94c5d5546161 | 2684 | ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL, (uint8_t *) ®, 1); |
cparata | 0:dff8803aace7 | 2685 | |
cparata | 4:94c5d5546161 | 2686 | switch (reg.ff_ths) { |
cparata | 4:94c5d5546161 | 2687 | case LIS2DW12_FF_TSH_5LSb_FS2g: |
cparata | 4:94c5d5546161 | 2688 | *val = LIS2DW12_FF_TSH_5LSb_FS2g; |
cparata | 4:94c5d5546161 | 2689 | break; |
cparata | 4:94c5d5546161 | 2690 | case LIS2DW12_FF_TSH_7LSb_FS2g: |
cparata | 4:94c5d5546161 | 2691 | *val = LIS2DW12_FF_TSH_7LSb_FS2g; |
cparata | 4:94c5d5546161 | 2692 | break; |
cparata | 4:94c5d5546161 | 2693 | case LIS2DW12_FF_TSH_8LSb_FS2g: |
cparata | 4:94c5d5546161 | 2694 | *val = LIS2DW12_FF_TSH_8LSb_FS2g; |
cparata | 4:94c5d5546161 | 2695 | break; |
cparata | 4:94c5d5546161 | 2696 | case LIS2DW12_FF_TSH_10LSb_FS2g: |
cparata | 4:94c5d5546161 | 2697 | *val = LIS2DW12_FF_TSH_10LSb_FS2g; |
cparata | 4:94c5d5546161 | 2698 | break; |
cparata | 4:94c5d5546161 | 2699 | case LIS2DW12_FF_TSH_11LSb_FS2g: |
cparata | 4:94c5d5546161 | 2700 | *val = LIS2DW12_FF_TSH_11LSb_FS2g; |
cparata | 4:94c5d5546161 | 2701 | break; |
cparata | 4:94c5d5546161 | 2702 | case LIS2DW12_FF_TSH_13LSb_FS2g: |
cparata | 4:94c5d5546161 | 2703 | *val = LIS2DW12_FF_TSH_13LSb_FS2g; |
cparata | 4:94c5d5546161 | 2704 | break; |
cparata | 4:94c5d5546161 | 2705 | case LIS2DW12_FF_TSH_15LSb_FS2g: |
cparata | 4:94c5d5546161 | 2706 | *val = LIS2DW12_FF_TSH_15LSb_FS2g; |
cparata | 4:94c5d5546161 | 2707 | break; |
cparata | 4:94c5d5546161 | 2708 | case LIS2DW12_FF_TSH_16LSb_FS2g: |
cparata | 4:94c5d5546161 | 2709 | *val = LIS2DW12_FF_TSH_16LSb_FS2g; |
cparata | 4:94c5d5546161 | 2710 | break; |
cparata | 4:94c5d5546161 | 2711 | default: |
cparata | 4:94c5d5546161 | 2712 | *val = LIS2DW12_FF_TSH_5LSb_FS2g; |
cparata | 4:94c5d5546161 | 2713 | break; |
cparata | 4:94c5d5546161 | 2714 | } |
cparata | 4:94c5d5546161 | 2715 | return ret; |
cparata | 0:dff8803aace7 | 2716 | } |
cparata | 0:dff8803aace7 | 2717 | |
cparata | 0:dff8803aace7 | 2718 | /** |
cparata | 0:dff8803aace7 | 2719 | * @} |
cparata | 2:a94816b14e3d | 2720 | * |
cparata | 0:dff8803aace7 | 2721 | */ |
cparata | 0:dff8803aace7 | 2722 | |
cparata | 0:dff8803aace7 | 2723 | /** |
cparata | 2:a94816b14e3d | 2724 | * @defgroup LIS2DW12_Fifo |
cparata | 2:a94816b14e3d | 2725 | * @brief This section group all the functions concerning the fifo usage |
cparata | 0:dff8803aace7 | 2726 | * @{ |
cparata | 2:a94816b14e3d | 2727 | * |
cparata | 0:dff8803aace7 | 2728 | */ |
cparata | 0:dff8803aace7 | 2729 | |
cparata | 0:dff8803aace7 | 2730 | /** |
cparata | 2:a94816b14e3d | 2731 | * @brief FIFO watermark level selection.[set] |
cparata | 0:dff8803aace7 | 2732 | * |
cparata | 2:a94816b14e3d | 2733 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2734 | * @param val change the values of fth in reg FIFO_CTRL |
cparata | 2:a94816b14e3d | 2735 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2736 | * |
cparata | 0:dff8803aace7 | 2737 | */ |
cparata | 0:dff8803aace7 | 2738 | int32_t lis2dw12_fifo_watermark_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 2739 | { |
cparata | 4:94c5d5546161 | 2740 | lis2dw12_fifo_ctrl_t reg; |
cparata | 4:94c5d5546161 | 2741 | int32_t ret; |
cparata | 0:dff8803aace7 | 2742 | |
cparata | 4:94c5d5546161 | 2743 | ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2744 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 2745 | reg.fth = val; |
cparata | 4:94c5d5546161 | 2746 | ret = lis2dw12_write_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2747 | } |
cparata | 0:dff8803aace7 | 2748 | |
cparata | 4:94c5d5546161 | 2749 | return ret; |
cparata | 0:dff8803aace7 | 2750 | } |
cparata | 0:dff8803aace7 | 2751 | |
cparata | 0:dff8803aace7 | 2752 | /** |
cparata | 4:94c5d5546161 | 2753 | * @brief FIFO watermark level selection.[get] |
cparata | 0:dff8803aace7 | 2754 | * |
cparata | 2:a94816b14e3d | 2755 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2756 | * @param val change the values of fth in reg FIFO_CTRL |
cparata | 2:a94816b14e3d | 2757 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2758 | * |
cparata | 0:dff8803aace7 | 2759 | */ |
cparata | 0:dff8803aace7 | 2760 | int32_t lis2dw12_fifo_watermark_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2761 | { |
cparata | 4:94c5d5546161 | 2762 | lis2dw12_fifo_ctrl_t reg; |
cparata | 4:94c5d5546161 | 2763 | int32_t ret; |
cparata | 0:dff8803aace7 | 2764 | |
cparata | 4:94c5d5546161 | 2765 | ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2766 | *val = reg.fth; |
cparata | 0:dff8803aace7 | 2767 | |
cparata | 4:94c5d5546161 | 2768 | return ret; |
cparata | 0:dff8803aace7 | 2769 | } |
cparata | 0:dff8803aace7 | 2770 | |
cparata | 0:dff8803aace7 | 2771 | /** |
cparata | 2:a94816b14e3d | 2772 | * @brief FIFO mode selection.[set] |
cparata | 0:dff8803aace7 | 2773 | * |
cparata | 2:a94816b14e3d | 2774 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2775 | * @param val change the values of fmode in reg FIFO_CTRL |
cparata | 2:a94816b14e3d | 2776 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2777 | * |
cparata | 0:dff8803aace7 | 2778 | */ |
cparata | 0:dff8803aace7 | 2779 | int32_t lis2dw12_fifo_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_fmode_t val) |
cparata | 0:dff8803aace7 | 2780 | { |
cparata | 4:94c5d5546161 | 2781 | lis2dw12_fifo_ctrl_t reg; |
cparata | 4:94c5d5546161 | 2782 | int32_t ret; |
cparata | 0:dff8803aace7 | 2783 | |
cparata | 4:94c5d5546161 | 2784 | ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2785 | if (ret == 0) { |
cparata | 4:94c5d5546161 | 2786 | reg.fmode = (uint8_t) val; |
cparata | 4:94c5d5546161 | 2787 | ret = lis2dw12_write_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2788 | } |
cparata | 4:94c5d5546161 | 2789 | return ret; |
cparata | 0:dff8803aace7 | 2790 | } |
cparata | 0:dff8803aace7 | 2791 | |
cparata | 0:dff8803aace7 | 2792 | /** |
cparata | 2:a94816b14e3d | 2793 | * @brief FIFO mode selection.[get] |
cparata | 0:dff8803aace7 | 2794 | * |
cparata | 2:a94816b14e3d | 2795 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2796 | * @param val Get the values of fmode in reg FIFO_CTRL |
cparata | 2:a94816b14e3d | 2797 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2798 | * |
cparata | 0:dff8803aace7 | 2799 | */ |
cparata | 0:dff8803aace7 | 2800 | int32_t lis2dw12_fifo_mode_get(lis2dw12_ctx_t *ctx, lis2dw12_fmode_t *val) |
cparata | 0:dff8803aace7 | 2801 | { |
cparata | 4:94c5d5546161 | 2802 | lis2dw12_fifo_ctrl_t reg; |
cparata | 4:94c5d5546161 | 2803 | int32_t ret; |
cparata | 2:a94816b14e3d | 2804 | |
cparata | 4:94c5d5546161 | 2805 | ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1); |
cparata | 0:dff8803aace7 | 2806 | |
cparata | 4:94c5d5546161 | 2807 | switch (reg.fmode) { |
cparata | 4:94c5d5546161 | 2808 | case LIS2DW12_BYPASS_MODE: |
cparata | 4:94c5d5546161 | 2809 | *val = LIS2DW12_BYPASS_MODE; |
cparata | 4:94c5d5546161 | 2810 | break; |
cparata | 4:94c5d5546161 | 2811 | case LIS2DW12_FIFO_MODE: |
cparata | 4:94c5d5546161 | 2812 | *val = LIS2DW12_FIFO_MODE; |
cparata | 4:94c5d5546161 | 2813 | break; |
cparata | 4:94c5d5546161 | 2814 | case LIS2DW12_STREAM_TO_FIFO_MODE: |
cparata | 4:94c5d5546161 | 2815 | *val = LIS2DW12_STREAM_TO_FIFO_MODE; |
cparata | 4:94c5d5546161 | 2816 | break; |
cparata | 4:94c5d5546161 | 2817 | case LIS2DW12_BYPASS_TO_STREAM_MODE: |
cparata | 4:94c5d5546161 | 2818 | *val = LIS2DW12_BYPASS_TO_STREAM_MODE; |
cparata | 4:94c5d5546161 | 2819 | break; |
cparata | 4:94c5d5546161 | 2820 | case LIS2DW12_STREAM_MODE: |
cparata | 4:94c5d5546161 | 2821 | *val = LIS2DW12_STREAM_MODE; |
cparata | 4:94c5d5546161 | 2822 | break; |
cparata | 4:94c5d5546161 | 2823 | default: |
cparata | 4:94c5d5546161 | 2824 | *val = LIS2DW12_BYPASS_MODE; |
cparata | 4:94c5d5546161 | 2825 | break; |
cparata | 4:94c5d5546161 | 2826 | } |
cparata | 4:94c5d5546161 | 2827 | return ret; |
cparata | 0:dff8803aace7 | 2828 | } |
cparata | 0:dff8803aace7 | 2829 | |
cparata | 0:dff8803aace7 | 2830 | /** |
cparata | 2:a94816b14e3d | 2831 | * @brief Number of unread samples stored in FIFO.[get] |
cparata | 0:dff8803aace7 | 2832 | * |
cparata | 2:a94816b14e3d | 2833 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2834 | * @param val change the values of diff in reg FIFO_SAMPLES |
cparata | 2:a94816b14e3d | 2835 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2836 | * |
cparata | 0:dff8803aace7 | 2837 | */ |
cparata | 0:dff8803aace7 | 2838 | int32_t lis2dw12_fifo_data_level_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2839 | { |
cparata | 4:94c5d5546161 | 2840 | lis2dw12_fifo_samples_t reg; |
cparata | 4:94c5d5546161 | 2841 | int32_t ret; |
cparata | 0:dff8803aace7 | 2842 | |
cparata | 4:94c5d5546161 | 2843 | ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2844 | *val = reg.diff; |
cparata | 0:dff8803aace7 | 2845 | |
cparata | 4:94c5d5546161 | 2846 | return ret; |
cparata | 0:dff8803aace7 | 2847 | } |
cparata | 0:dff8803aace7 | 2848 | /** |
cparata | 2:a94816b14e3d | 2849 | * @brief FIFO overrun status.[get] |
cparata | 0:dff8803aace7 | 2850 | * |
cparata | 2:a94816b14e3d | 2851 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2852 | * @param val change the values of fifo_ovr in reg FIFO_SAMPLES |
cparata | 2:a94816b14e3d | 2853 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2854 | * |
cparata | 0:dff8803aace7 | 2855 | */ |
cparata | 0:dff8803aace7 | 2856 | int32_t lis2dw12_fifo_ovr_flag_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2857 | { |
cparata | 4:94c5d5546161 | 2858 | lis2dw12_fifo_samples_t reg; |
cparata | 4:94c5d5546161 | 2859 | int32_t ret; |
cparata | 0:dff8803aace7 | 2860 | |
cparata | 4:94c5d5546161 | 2861 | ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2862 | *val = reg.fifo_ovr; |
cparata | 0:dff8803aace7 | 2863 | |
cparata | 4:94c5d5546161 | 2864 | return ret; |
cparata | 0:dff8803aace7 | 2865 | } |
cparata | 0:dff8803aace7 | 2866 | /** |
cparata | 2:a94816b14e3d | 2867 | * @brief FIFO threshold status flag.[get] |
cparata | 0:dff8803aace7 | 2868 | * |
cparata | 2:a94816b14e3d | 2869 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2870 | * @param val change the values of fifo_fth in reg FIFO_SAMPLES |
cparata | 2:a94816b14e3d | 2871 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2872 | * |
cparata | 0:dff8803aace7 | 2873 | */ |
cparata | 0:dff8803aace7 | 2874 | int32_t lis2dw12_fifo_wtm_flag_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2875 | { |
cparata | 4:94c5d5546161 | 2876 | lis2dw12_fifo_samples_t reg; |
cparata | 4:94c5d5546161 | 2877 | int32_t ret; |
cparata | 0:dff8803aace7 | 2878 | |
cparata | 4:94c5d5546161 | 2879 | ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES, (uint8_t *) ®, 1); |
cparata | 4:94c5d5546161 | 2880 | *val = reg.fifo_fth; |
cparata | 0:dff8803aace7 | 2881 | |
cparata | 4:94c5d5546161 | 2882 | return ret; |
cparata | 0:dff8803aace7 | 2883 | } |
cparata | 0:dff8803aace7 | 2884 | /** |
cparata | 0:dff8803aace7 | 2885 | * @} |
cparata | 4:94c5d5546161 | 2886 | * |
cparata | 0:dff8803aace7 | 2887 | */ |
cparata | 0:dff8803aace7 | 2888 | |
cparata | 0:dff8803aace7 | 2889 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |