LIS2DW12 - LIS2DW12 accelerometer sensor library

LELEC2811 - I&S » Code » LIS2DW12

LIS2DW12 accelerometer sensor library

Dependencies: X_NUCLEO_COMMON ST_INTERFACES

lis2dw12_reg.c@3:111317ba9301, 2018-11-21 (annotated)

Committer:: cparata
Date:: Wed Nov 21 15:43:22 2018 +0000
Revision:: 3:111317ba9301
Parent:: 2:a94816b14e3d
Child:: 4:94c5d5546161

Update header in reg files

Who changed what in which revision?

User	Revision	Line number	New contents of line
cparata	3:111317ba9301	1	/**
cparata	0:dff8803aace7	2	******************************************************************************
cparata	0:dff8803aace7	3	* @file lis2dw12_reg.c
cparata	2:a94816b14e3d	4	* @author Sensors Software Solution Team
cparata	0:dff8803aace7	5	* @brief LIS2DW12 driver file
cparata	0:dff8803aace7	6	******************************************************************************
cparata	0:dff8803aace7	7	* @attention
cparata	0:dff8803aace7	8	*
cparata	0:dff8803aace7	9	* <h2><center>© COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
cparata	0:dff8803aace7	10	*
cparata	2:a94816b14e3d	11	* Redistribution and use in source and binary forms, with or without
cparata	2:a94816b14e3d	12	* modification, are permitted provided that the following conditions
cparata	2:a94816b14e3d	13	* are met:
cparata	0:dff8803aace7	14	* 1. Redistributions of source code must retain the above copyright notice,
cparata	0:dff8803aace7	15	* this list of conditions and the following disclaimer.
cparata	2:a94816b14e3d	16	* 2. Redistributions in binary form must reproduce the above copyright
cparata	2:a94816b14e3d	17	* notice, this list of conditions and the following disclaimer in the
cparata	2:a94816b14e3d	18	* documentation and/or other materials provided with the distribution.
cparata	2:a94816b14e3d	19	* 3. Neither the name of STMicroelectronics nor the names of its
cparata	2:a94816b14e3d	20	* contributors may be used to endorse or promote products derived from
cparata	2:a94816b14e3d	21	* this software without specific prior written permission.
cparata	0:dff8803aace7	22	*
cparata	0:dff8803aace7	23	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
cparata	0:dff8803aace7	24	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
cparata	2:a94816b14e3d	25	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
cparata	2:a94816b14e3d	26	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
cparata	2:a94816b14e3d	27	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
cparata	2:a94816b14e3d	28	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
cparata	2:a94816b14e3d	29	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
cparata	2:a94816b14e3d	30	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
cparata	2:a94816b14e3d	31	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
cparata	2:a94816b14e3d	32	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
cparata	2:a94816b14e3d	33	* POSSIBILITY OF SUCH DAMAGE.
cparata	0:dff8803aace7	34	*
cparata	3:111317ba9301	35	******************************************************************************
cparata	0:dff8803aace7	36	*/
cparata	0:dff8803aace7	37
cparata	0:dff8803aace7	38	#include "lis2dw12_reg.h"
cparata	0:dff8803aace7	39
cparata	0:dff8803aace7	40	/**
cparata	2:a94816b14e3d	41	* @defgroup LIS2DW12
cparata	2:a94816b14e3d	42	* @brief This file provides a set of functions needed to drive the
cparata	2:a94816b14e3d	43	* lis2dw12 enhanced inertial module.
cparata	0:dff8803aace7	44	* @{
cparata	2:a94816b14e3d	45	*
cparata	0:dff8803aace7	46	*/
cparata	0:dff8803aace7	47
cparata	2:a94816b14e3d	48	/**
cparata	2:a94816b14e3d	49	* @defgroup LIS2DW12_Interfaces_Functions
cparata	2:a94816b14e3d	50	* @brief This section provide a set of functions used to read and
cparata	2:a94816b14e3d	51	* write a generic register of the device.
cparata	2:a94816b14e3d	52	* MANDATORY: return 0 -> no Error.
cparata	0:dff8803aace7	53	* @{
cparata	2:a94816b14e3d	54	*
cparata	0:dff8803aace7	55	*/
cparata	0:dff8803aace7	56
cparata	0:dff8803aace7	57	/**
cparata	0:dff8803aace7	58	* @brief Read generic device register
cparata	2:a94816b14e3d	59	*
cparata	2:a94816b14e3d	60	* @param ctx read / write interface definitions(ptr)
cparata	2:a94816b14e3d	61	* @param reg register to read
cparata	2:a94816b14e3d	62	* @param data pointer to buffer that store the data read(ptr)
cparata	2:a94816b14e3d	63	* @param len number of consecutive register to read
cparata	2:a94816b14e3d	64	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	65	*
cparata	0:dff8803aace7	66	*/
cparata	0:dff8803aace7	67	int32_t lis2dw12_read_reg(lis2dw12_ctx_t* ctx, uint8_t reg, uint8_t* data,
cparata	0:dff8803aace7	68	uint16_t len)
cparata	0:dff8803aace7	69	{
cparata	2:a94816b14e3d	70	int32_t ret;
cparata	2:a94816b14e3d	71	ret = ctx->read_reg(ctx->handle, reg, data, len);
cparata	2:a94816b14e3d	72	return ret;
cparata	0:dff8803aace7	73	}
cparata	0:dff8803aace7	74
cparata	0:dff8803aace7	75	/**
cparata	0:dff8803aace7	76	* @brief Write generic device register
cparata	0:dff8803aace7	77	*
cparata	2:a94816b14e3d	78	* @param ctx read / write interface definitions(ptr)
cparata	2:a94816b14e3d	79	* @param reg register to write
cparata	2:a94816b14e3d	80	* @param data pointer to data to write in register reg(ptr)
cparata	2:a94816b14e3d	81	* @param len number of consecutive register to write
cparata	2:a94816b14e3d	82	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	2:a94816b14e3d	83	*
cparata	2:a94816b14e3d	84	*/
cparata	0:dff8803aace7	85	int32_t lis2dw12_write_reg(lis2dw12_ctx_t* ctx, uint8_t reg, uint8_t* data,
cparata	0:dff8803aace7	86	uint16_t len)
cparata	0:dff8803aace7	87	{
cparata	2:a94816b14e3d	88	int32_t ret;
cparata	2:a94816b14e3d	89	ret = ctx->write_reg(ctx->handle, reg, data, len);
cparata	2:a94816b14e3d	90	return ret;
cparata	0:dff8803aace7	91	}
cparata	0:dff8803aace7	92
cparata	0:dff8803aace7	93	/**
cparata	0:dff8803aace7	94	* @}
cparata	2:a94816b14e3d	95	*
cparata	2:a94816b14e3d	96	*/
cparata	2:a94816b14e3d	97
cparata	2:a94816b14e3d	98	/**
cparata	2:a94816b14e3d	99	* @defgroup LIS2DW12_Sensitivity
cparata	2:a94816b14e3d	100	* @brief These functions convert raw-data into engineering units.
cparata	2:a94816b14e3d	101	* @{
cparata	2:a94816b14e3d	102	*
cparata	2:a94816b14e3d	103	*/
cparata	2:a94816b14e3d	104
cparata	2:a94816b14e3d	105	float lis2dw12_from_fs2_to_mg(int16_t lsb)
cparata	2:a94816b14e3d	106	{
cparata	2:a94816b14e3d	107	return ((float)lsb) * 0.061f;
cparata	2:a94816b14e3d	108	}
cparata	2:a94816b14e3d	109
cparata	2:a94816b14e3d	110	float lis2dw12_from_fs4_to_mg(int16_t lsb)
cparata	2:a94816b14e3d	111	{
cparata	2:a94816b14e3d	112	return ((float)lsb) * 0.122f;
cparata	2:a94816b14e3d	113	}
cparata	2:a94816b14e3d	114
cparata	2:a94816b14e3d	115	float lis2dw12_from_fs8_to_mg(int16_t lsb)
cparata	2:a94816b14e3d	116	{
cparata	2:a94816b14e3d	117	return ((float)lsb) * 0.244f;
cparata	2:a94816b14e3d	118	}
cparata	2:a94816b14e3d	119
cparata	2:a94816b14e3d	120	float lis2dw12_from_fs16_to_mg(int16_t lsb)
cparata	2:a94816b14e3d	121	{
cparata	2:a94816b14e3d	122	return ((float)lsb) *0.488f;
cparata	2:a94816b14e3d	123	}
cparata	2:a94816b14e3d	124
cparata	2:a94816b14e3d	125	float lis2dw12_from_fs2_lp1_to_mg(int16_t lsb)
cparata	2:a94816b14e3d	126	{
cparata	2:a94816b14e3d	127	return ((float)lsb) * 0.061f;
cparata	2:a94816b14e3d	128	}
cparata	2:a94816b14e3d	129
cparata	2:a94816b14e3d	130	float lis2dw12_from_fs4_lp1_to_mg(int16_t lsb)
cparata	2:a94816b14e3d	131	{
cparata	2:a94816b14e3d	132	return ((float)lsb) * 0.122f;
cparata	2:a94816b14e3d	133	}
cparata	2:a94816b14e3d	134
cparata	2:a94816b14e3d	135	float lis2dw12_from_fs8_lp1_to_mg(int16_t lsb)
cparata	2:a94816b14e3d	136	{
cparata	2:a94816b14e3d	137	return ((float)lsb) * 0.244f;
cparata	2:a94816b14e3d	138	}
cparata	2:a94816b14e3d	139
cparata	2:a94816b14e3d	140	float lis2dw12_from_fs16_lp1_to_mg(int16_t lsb)
cparata	2:a94816b14e3d	141	{
cparata	2:a94816b14e3d	142	return ((float)lsb) * 0.488f;
cparata	2:a94816b14e3d	143	}
cparata	2:a94816b14e3d	144
cparata	2:a94816b14e3d	145	float lis2dw12_from_lsb_to_celsius(int16_t lsb)
cparata	2:a94816b14e3d	146	{
cparata	2:a94816b14e3d	147	return (((float)lsb / 16.0f) + 25.0f);
cparata	2:a94816b14e3d	148	}
cparata	2:a94816b14e3d	149
cparata	2:a94816b14e3d	150	/**
cparata	2:a94816b14e3d	151	* @}
cparata	2:a94816b14e3d	152	*
cparata	0:dff8803aace7	153	*/
cparata	0:dff8803aace7	154
cparata	0:dff8803aace7	155	/**
cparata	2:a94816b14e3d	156	* @defgroup LIS2DW12_Data_Generation
cparata	2:a94816b14e3d	157	* @brief This section groups all the functions concerning
cparata	2:a94816b14e3d	158	* data generation
cparata	0:dff8803aace7	159	* @{
cparata	2:a94816b14e3d	160	*
cparata	0:dff8803aace7	161	*/
cparata	0:dff8803aace7	162
cparata	0:dff8803aace7	163	/**
cparata	2:a94816b14e3d	164	* @brief Select accelerometer operating modes.[set]
cparata	0:dff8803aace7	165	*
cparata	2:a94816b14e3d	166	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	167	* @param val change the values of mode / lp_mode in reg CTRL1
cparata	2:a94816b14e3d	168	* and low_noise in reg CTRL6
cparata	2:a94816b14e3d	169	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	170	*
cparata	0:dff8803aace7	171	*/
cparata	0:dff8803aace7	172	int32_t lis2dw12_power_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_mode_t val)
cparata	0:dff8803aace7	173	{
cparata	2:a94816b14e3d	174	lis2dw12_ctrl1_t ctrl1;
cparata	2:a94816b14e3d	175	lis2dw12_ctrl6_t ctrl6;
cparata	2:a94816b14e3d	176	int32_t ret;
cparata	0:dff8803aace7	177
cparata	2:a94816b14e3d	178	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1);
cparata	2:a94816b14e3d	179	if (ret == 0) {
cparata	2:a94816b14e3d	180	ctrl1.mode = ( (uint8_t) val & 0x0CU ) >> 2;
cparata	2:a94816b14e3d	181	ctrl1.lp_mode = (uint8_t) val & 0x03U ;
cparata	2:a94816b14e3d	182	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1);
cparata	2:a94816b14e3d	183	}
cparata	2:a94816b14e3d	184	if (ret == 0) {
cparata	2:a94816b14e3d	185	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &ctrl6, 1);
cparata	2:a94816b14e3d	186	}
cparata	2:a94816b14e3d	187	if (ret == 0) {
cparata	2:a94816b14e3d	188	ctrl6.low_noise = ( (uint8_t) val & 0x10U ) >> 4;
cparata	2:a94816b14e3d	189	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &ctrl6, 1);
cparata	2:a94816b14e3d	190	}
cparata	2:a94816b14e3d	191	return ret;
cparata	0:dff8803aace7	192	}
cparata	0:dff8803aace7	193
cparata	0:dff8803aace7	194	/**
cparata	2:a94816b14e3d	195	* @brief Select accelerometer operating modes.[get]
cparata	0:dff8803aace7	196	*
cparata	2:a94816b14e3d	197	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	198	* @param val change the values of mode / lp_mode in reg CTRL1
cparata	2:a94816b14e3d	199	* and low_noise in reg CTRL6
cparata	2:a94816b14e3d	200	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	201	*
cparata	0:dff8803aace7	202	*/
cparata	0:dff8803aace7	203	int32_t lis2dw12_power_mode_get(lis2dw12_ctx_t ctx, lis2dw12_mode_t val)
cparata	0:dff8803aace7	204	{
cparata	2:a94816b14e3d	205	lis2dw12_ctrl1_t ctrl1;
cparata	2:a94816b14e3d	206	lis2dw12_ctrl6_t ctrl6;
cparata	2:a94816b14e3d	207	int32_t ret;
cparata	2:a94816b14e3d	208
cparata	2:a94816b14e3d	209	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1);
cparata	2:a94816b14e3d	210	if (ret == 0) {
cparata	2:a94816b14e3d	211	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &ctrl6, 1);
cparata	0:dff8803aace7	212
cparata	2:a94816b14e3d	213	switch (((ctrl6.low_noise << 4) + (ctrl1.mode << 2) +
cparata	2:a94816b14e3d	214	ctrl1.lp_mode)) {
cparata	2:a94816b14e3d	215	case LIS2DW12_HIGH_PERFORMANCE:
cparata	2:a94816b14e3d	216	*val = LIS2DW12_HIGH_PERFORMANCE;
cparata	2:a94816b14e3d	217	break;
cparata	2:a94816b14e3d	218	case LIS2DW12_CONT_LOW_PWR_4:
cparata	2:a94816b14e3d	219	*val = LIS2DW12_CONT_LOW_PWR_4;
cparata	2:a94816b14e3d	220	break;
cparata	2:a94816b14e3d	221	case LIS2DW12_CONT_LOW_PWR_3:
cparata	2:a94816b14e3d	222	*val = LIS2DW12_CONT_LOW_PWR_3;
cparata	2:a94816b14e3d	223	break;
cparata	2:a94816b14e3d	224	case LIS2DW12_CONT_LOW_PWR_2:
cparata	2:a94816b14e3d	225	*val = LIS2DW12_CONT_LOW_PWR_2;
cparata	2:a94816b14e3d	226	break;
cparata	2:a94816b14e3d	227	case LIS2DW12_CONT_LOW_PWR_12bit:
cparata	2:a94816b14e3d	228	*val = LIS2DW12_CONT_LOW_PWR_12bit;
cparata	2:a94816b14e3d	229	break;
cparata	2:a94816b14e3d	230	case LIS2DW12_SINGLE_LOW_PWR_4:
cparata	2:a94816b14e3d	231	*val = LIS2DW12_SINGLE_LOW_PWR_4;
cparata	2:a94816b14e3d	232	break;
cparata	2:a94816b14e3d	233	case LIS2DW12_SINGLE_LOW_PWR_3:
cparata	2:a94816b14e3d	234	*val = LIS2DW12_SINGLE_LOW_PWR_3;
cparata	2:a94816b14e3d	235	break;
cparata	2:a94816b14e3d	236	case LIS2DW12_SINGLE_LOW_PWR_2:
cparata	2:a94816b14e3d	237	*val = LIS2DW12_SINGLE_LOW_PWR_2;
cparata	2:a94816b14e3d	238	break;
cparata	2:a94816b14e3d	239	case LIS2DW12_SINGLE_LOW_PWR_12bit:
cparata	2:a94816b14e3d	240	*val = LIS2DW12_SINGLE_LOW_PWR_12bit;
cparata	2:a94816b14e3d	241	break;
cparata	2:a94816b14e3d	242	case LIS2DW12_HIGH_PERFORMANCE_LOW_NOISE:
cparata	2:a94816b14e3d	243	*val = LIS2DW12_HIGH_PERFORMANCE_LOW_NOISE;
cparata	2:a94816b14e3d	244	break;
cparata	2:a94816b14e3d	245	case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_4:
cparata	2:a94816b14e3d	246	*val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_4;
cparata	2:a94816b14e3d	247	break;
cparata	2:a94816b14e3d	248	case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_3:
cparata	2:a94816b14e3d	249	*val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_3;
cparata	2:a94816b14e3d	250	break;
cparata	2:a94816b14e3d	251	case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_2:
cparata	2:a94816b14e3d	252	*val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_2;
cparata	2:a94816b14e3d	253	break;
cparata	2:a94816b14e3d	254	case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_12bit:
cparata	2:a94816b14e3d	255	*val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_12bit;
cparata	2:a94816b14e3d	256	break;
cparata	2:a94816b14e3d	257	case LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_4:
cparata	2:a94816b14e3d	258	*val = LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_4;
cparata	2:a94816b14e3d	259	break;
cparata	2:a94816b14e3d	260	case LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_3:
cparata	2:a94816b14e3d	261	*val = LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_3;
cparata	2:a94816b14e3d	262	break;
cparata	2:a94816b14e3d	263	case LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_2:
cparata	2:a94816b14e3d	264	*val = LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_2;
cparata	2:a94816b14e3d	265	break;
cparata	2:a94816b14e3d	266	case LIS2DW12_SINGLE_LOW_LOW_NOISE_PWR_12bit:
cparata	2:a94816b14e3d	267	*val = LIS2DW12_SINGLE_LOW_LOW_NOISE_PWR_12bit;
cparata	2:a94816b14e3d	268	break;
cparata	2:a94816b14e3d	269	default:
cparata	2:a94816b14e3d	270	*val = LIS2DW12_HIGH_PERFORMANCE;
cparata	2:a94816b14e3d	271	break;
cparata	2:a94816b14e3d	272	}
cparata	2:a94816b14e3d	273	}
cparata	2:a94816b14e3d	274	return ret;
cparata	0:dff8803aace7	275	}
cparata	0:dff8803aace7	276
cparata	0:dff8803aace7	277	/**
cparata	2:a94816b14e3d	278	* @brief Accelerometer data rate selection.[set]
cparata	0:dff8803aace7	279	*
cparata	2:a94816b14e3d	280	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	281	* @param val change the values of odr in reg CTRL1
cparata	2:a94816b14e3d	282	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	283	*
cparata	0:dff8803aace7	284	*/
cparata	0:dff8803aace7	285	int32_t lis2dw12_data_rate_set(lis2dw12_ctx_t *ctx, lis2dw12_odr_t val)
cparata	0:dff8803aace7	286	{
cparata	2:a94816b14e3d	287	lis2dw12_ctrl1_t ctrl1;
cparata	2:a94816b14e3d	288	lis2dw12_ctrl3_t ctrl3;
cparata	2:a94816b14e3d	289	int32_t ret;
cparata	0:dff8803aace7	290
cparata	2:a94816b14e3d	291	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1);
cparata	2:a94816b14e3d	292	if (ret == 0) {
cparata	2:a94816b14e3d	293	ctrl1.odr = (uint8_t) val;
cparata	2:a94816b14e3d	294	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1);
cparata	2:a94816b14e3d	295	}
cparata	2:a94816b14e3d	296	if (ret == 0) {
cparata	2:a94816b14e3d	297	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) &ctrl3, 1);
cparata	2:a94816b14e3d	298	}
cparata	2:a94816b14e3d	299	if (ret == 0) {
cparata	2:a94816b14e3d	300	ctrl3.slp_mode = ( (uint8_t) val & 0x30U ) >> 4;
cparata	2:a94816b14e3d	301	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) &ctrl3, 1);
cparata	2:a94816b14e3d	302	}
cparata	2:a94816b14e3d	303	return ret;
cparata	0:dff8803aace7	304	}
cparata	0:dff8803aace7	305
cparata	0:dff8803aace7	306	/**
cparata	2:a94816b14e3d	307	* @brief Accelerometer data rate selection.[get]
cparata	0:dff8803aace7	308	*
cparata	2:a94816b14e3d	309	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	310	* @param val Get the values of odr in reg CTRL1
cparata	2:a94816b14e3d	311	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	312	*
cparata	0:dff8803aace7	313	*/
cparata	0:dff8803aace7	314	int32_t lis2dw12_data_rate_get(lis2dw12_ctx_t ctx, lis2dw12_odr_t val)
cparata	0:dff8803aace7	315	{
cparata	2:a94816b14e3d	316	lis2dw12_ctrl1_t ctrl1;
cparata	2:a94816b14e3d	317	lis2dw12_ctrl3_t ctrl3;
cparata	2:a94816b14e3d	318	int32_t ret;
cparata	0:dff8803aace7	319
cparata	2:a94816b14e3d	320	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1);
cparata	2:a94816b14e3d	321	if (ret == 0) {
cparata	2:a94816b14e3d	322	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) &ctrl3, 1);
cparata	2:a94816b14e3d	323
cparata	2:a94816b14e3d	324	switch ((ctrl3.slp_mode << 4) + ctrl1.odr) {
cparata	2:a94816b14e3d	325	case LIS2DW12_XL_ODR_OFF:
cparata	2:a94816b14e3d	326	*val = LIS2DW12_XL_ODR_OFF;
cparata	2:a94816b14e3d	327	break;
cparata	2:a94816b14e3d	328	case LIS2DW12_XL_ODR_1Hz6_LP_ONLY:
cparata	2:a94816b14e3d	329	*val = LIS2DW12_XL_ODR_1Hz6_LP_ONLY;
cparata	2:a94816b14e3d	330	break;
cparata	2:a94816b14e3d	331	case LIS2DW12_XL_ODR_12Hz5:
cparata	2:a94816b14e3d	332	*val = LIS2DW12_XL_ODR_12Hz5;
cparata	2:a94816b14e3d	333	break;
cparata	2:a94816b14e3d	334	case LIS2DW12_XL_ODR_25Hz:
cparata	2:a94816b14e3d	335	*val = LIS2DW12_XL_ODR_25Hz;
cparata	2:a94816b14e3d	336	break;
cparata	2:a94816b14e3d	337	case LIS2DW12_XL_ODR_50Hz:
cparata	2:a94816b14e3d	338	*val = LIS2DW12_XL_ODR_50Hz;
cparata	2:a94816b14e3d	339	break;
cparata	2:a94816b14e3d	340	case LIS2DW12_XL_ODR_100Hz:
cparata	2:a94816b14e3d	341	*val = LIS2DW12_XL_ODR_100Hz;
cparata	2:a94816b14e3d	342	break;
cparata	2:a94816b14e3d	343	case LIS2DW12_XL_ODR_200Hz:
cparata	2:a94816b14e3d	344	*val = LIS2DW12_XL_ODR_200Hz;
cparata	2:a94816b14e3d	345	break;
cparata	2:a94816b14e3d	346	case LIS2DW12_XL_ODR_400Hz:
cparata	2:a94816b14e3d	347	*val = LIS2DW12_XL_ODR_400Hz;
cparata	2:a94816b14e3d	348	break;
cparata	2:a94816b14e3d	349	case LIS2DW12_XL_ODR_800Hz:
cparata	2:a94816b14e3d	350	*val = LIS2DW12_XL_ODR_800Hz;
cparata	2:a94816b14e3d	351	break;
cparata	2:a94816b14e3d	352	case LIS2DW12_XL_ODR_1k6Hz:
cparata	2:a94816b14e3d	353	*val = LIS2DW12_XL_ODR_1k6Hz;
cparata	2:a94816b14e3d	354	break;
cparata	2:a94816b14e3d	355	case LIS2DW12_XL_SET_SW_TRIG:
cparata	2:a94816b14e3d	356	*val = LIS2DW12_XL_SET_SW_TRIG;
cparata	2:a94816b14e3d	357	break;
cparata	2:a94816b14e3d	358	case LIS2DW12_XL_SET_PIN_TRIG:
cparata	2:a94816b14e3d	359	*val = LIS2DW12_XL_SET_PIN_TRIG;
cparata	2:a94816b14e3d	360	break;
cparata	2:a94816b14e3d	361	default:
cparata	2:a94816b14e3d	362	*val = LIS2DW12_XL_ODR_OFF;
cparata	2:a94816b14e3d	363	break;
cparata	2:a94816b14e3d	364	}
cparata	2:a94816b14e3d	365	}
cparata	2:a94816b14e3d	366	return ret;
cparata	0:dff8803aace7	367	}
cparata	0:dff8803aace7	368
cparata	0:dff8803aace7	369	/**
cparata	2:a94816b14e3d	370	* @brief Block data update.[set]
cparata	0:dff8803aace7	371	*
cparata	2:a94816b14e3d	372	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	373	* @param val change the values of bdu in reg CTRL2
cparata	2:a94816b14e3d	374	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	375	*
cparata	0:dff8803aace7	376	*/
cparata	0:dff8803aace7	377	int32_t lis2dw12_block_data_update_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	378	{
cparata	2:a94816b14e3d	379	lis2dw12_ctrl2_t reg;
cparata	2:a94816b14e3d	380	int32_t ret;
cparata	0:dff8803aace7	381
cparata	2:a94816b14e3d	382	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	383	if (ret == 0) {
cparata	2:a94816b14e3d	384	reg.bdu = val;
cparata	2:a94816b14e3d	385	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	386	}
cparata	2:a94816b14e3d	387	return ret;
cparata	0:dff8803aace7	388	}
cparata	0:dff8803aace7	389
cparata	0:dff8803aace7	390	/**
cparata	2:a94816b14e3d	391	* @brief Block data update.[get]
cparata	0:dff8803aace7	392	*
cparata	2:a94816b14e3d	393	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	394	* @param val change the values of bdu in reg CTRL2
cparata	2:a94816b14e3d	395	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	396	*
cparata	0:dff8803aace7	397	*/
cparata	0:dff8803aace7	398	int32_t lis2dw12_block_data_update_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	399	{
cparata	2:a94816b14e3d	400	lis2dw12_ctrl2_t reg;
cparata	2:a94816b14e3d	401	int32_t ret;
cparata	0:dff8803aace7	402
cparata	2:a94816b14e3d	403	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	404	*val = reg.bdu;
cparata	0:dff8803aace7	405
cparata	2:a94816b14e3d	406	return ret;
cparata	0:dff8803aace7	407	}
cparata	0:dff8803aace7	408
cparata	0:dff8803aace7	409	/**
cparata	2:a94816b14e3d	410	* @brief Accelerometer full-scale selection.[set]
cparata	0:dff8803aace7	411	*
cparata	2:a94816b14e3d	412	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	413	* @param val change the values of fs in reg CTRL6
cparata	2:a94816b14e3d	414	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	415	*
cparata	0:dff8803aace7	416	*/
cparata	0:dff8803aace7	417	int32_t lis2dw12_full_scale_set(lis2dw12_ctx_t *ctx, lis2dw12_fs_t val)
cparata	0:dff8803aace7	418	{
cparata	2:a94816b14e3d	419	lis2dw12_ctrl6_t reg;
cparata	2:a94816b14e3d	420	int32_t ret;
cparata	0:dff8803aace7	421
cparata	2:a94816b14e3d	422	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	423	if (ret == 0) {
cparata	2:a94816b14e3d	424	reg.fs = (uint8_t) val;
cparata	2:a94816b14e3d	425	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	426	}
cparata	2:a94816b14e3d	427	return ret;
cparata	0:dff8803aace7	428	}
cparata	0:dff8803aace7	429
cparata	0:dff8803aace7	430	/**
cparata	2:a94816b14e3d	431	* @brief Accelerometer full-scale selection.[get]
cparata	0:dff8803aace7	432	*
cparata	2:a94816b14e3d	433	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	434	* @param val Get the values of fs in reg CTRL6
cparata	2:a94816b14e3d	435	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	436	*
cparata	0:dff8803aace7	437	*/
cparata	0:dff8803aace7	438	int32_t lis2dw12_full_scale_get(lis2dw12_ctx_t ctx, lis2dw12_fs_t val)
cparata	0:dff8803aace7	439	{
cparata	2:a94816b14e3d	440	lis2dw12_ctrl6_t reg;
cparata	2:a94816b14e3d	441	int32_t ret;
cparata	2:a94816b14e3d	442
cparata	2:a94816b14e3d	443	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &reg, 1);
cparata	0:dff8803aace7	444
cparata	2:a94816b14e3d	445	switch (reg.fs) {
cparata	2:a94816b14e3d	446	case LIS2DW12_2g:
cparata	2:a94816b14e3d	447	*val = LIS2DW12_2g;
cparata	2:a94816b14e3d	448	break;
cparata	2:a94816b14e3d	449	case LIS2DW12_4g:
cparata	2:a94816b14e3d	450	*val = LIS2DW12_4g;
cparata	2:a94816b14e3d	451	break;
cparata	2:a94816b14e3d	452	case LIS2DW12_8g:
cparata	2:a94816b14e3d	453	*val = LIS2DW12_8g;
cparata	2:a94816b14e3d	454	break;
cparata	2:a94816b14e3d	455	case LIS2DW12_16g:
cparata	2:a94816b14e3d	456	*val = LIS2DW12_16g;
cparata	2:a94816b14e3d	457	break;
cparata	2:a94816b14e3d	458	default:
cparata	2:a94816b14e3d	459	*val = LIS2DW12_2g;
cparata	2:a94816b14e3d	460	break;
cparata	2:a94816b14e3d	461	}
cparata	2:a94816b14e3d	462	return ret;
cparata	0:dff8803aace7	463	}
cparata	0:dff8803aace7	464
cparata	0:dff8803aace7	465	/**
cparata	2:a94816b14e3d	466	* @brief The STATUS_REG register of the device.[get]
cparata	0:dff8803aace7	467	*
cparata	2:a94816b14e3d	468	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	469	* @param val union of registers from STATUS to
cparata	2:a94816b14e3d	470	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	471	*
cparata	0:dff8803aace7	472	*/
cparata	0:dff8803aace7	473	int32_t lis2dw12_status_reg_get(lis2dw12_ctx_t ctx, lis2dw12_status_t val)
cparata	0:dff8803aace7	474	{
cparata	2:a94816b14e3d	475	int32_t ret;
cparata	2:a94816b14e3d	476	ret = lis2dw12_read_reg(ctx, LIS2DW12_STATUS, (uint8_t*) val, 1);
cparata	2:a94816b14e3d	477	return ret;
cparata	0:dff8803aace7	478	}
cparata	2:a94816b14e3d	479
cparata	0:dff8803aace7	480	/**
cparata	2:a94816b14e3d	481	* @brief Accelerometer new data available.[get]
cparata	0:dff8803aace7	482	*
cparata	2:a94816b14e3d	483	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	484	* @param val change the values of drdy in reg STATUS
cparata	2:a94816b14e3d	485	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	486	*
cparata	0:dff8803aace7	487	*/
cparata	0:dff8803aace7	488	int32_t lis2dw12_flag_data_ready_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	489	{
cparata	2:a94816b14e3d	490	lis2dw12_status_t reg;
cparata	2:a94816b14e3d	491	int32_t ret;
cparata	0:dff8803aace7	492
cparata	2:a94816b14e3d	493	ret = lis2dw12_read_reg(ctx, LIS2DW12_STATUS,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	494	*val = reg.drdy;
cparata	0:dff8803aace7	495
cparata	2:a94816b14e3d	496	return ret;
cparata	0:dff8803aace7	497	}
cparata	0:dff8803aace7	498	/**
cparata	2:a94816b14e3d	499	* @brief Read all the interrupt/status flag of the device.[get]
cparata	2:a94816b14e3d	500	*
cparata	2:a94816b14e3d	501	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	502	* @param val registers STATUS_DUP, WAKE_UP_SRC,
cparata	2:a94816b14e3d	503	* TAP_SRC, SIXD_SRC, ALL_INT_SRC
cparata	2:a94816b14e3d	504	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	505	*
cparata	0:dff8803aace7	506	*/
cparata	0:dff8803aace7	507	int32_t lis2dw12_all_sources_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	508	lis2dw12_all_sources_t *val)
cparata	0:dff8803aace7	509	{
cparata	2:a94816b14e3d	510	int32_t ret;
cparata	2:a94816b14e3d	511	ret = lis2dw12_read_reg(ctx, LIS2DW12_STATUS_DUP, (uint8_t*) val, 5);
cparata	2:a94816b14e3d	512	return ret;
cparata	0:dff8803aace7	513	}
cparata	2:a94816b14e3d	514
cparata	0:dff8803aace7	515	/**
cparata	2:a94816b14e3d	516	* @brief Accelerometer X-axis user offset correction expressed in two’s
cparata	2:a94816b14e3d	517	* complement, weight depends on bit USR_OFF_W. The value must be
cparata	2:a94816b14e3d	518	* in the range [-127 127].[set]
cparata	0:dff8803aace7	519	*
cparata	2:a94816b14e3d	520	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	521	* @param buff buffer that contains data to write
cparata	2:a94816b14e3d	522	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	523	*
cparata	0:dff8803aace7	524	*/
cparata	0:dff8803aace7	525	int32_t lis2dw12_usr_offset_x_set(lis2dw12_ctx_t ctx, uint8_t buff)
cparata	0:dff8803aace7	526	{
cparata	2:a94816b14e3d	527	int32_t ret;
cparata	2:a94816b14e3d	528	ret = lis2dw12_write_reg(ctx, LIS2DW12_X_OFS_USR, buff, 1);
cparata	2:a94816b14e3d	529	return ret;
cparata	0:dff8803aace7	530	}
cparata	0:dff8803aace7	531
cparata	0:dff8803aace7	532	/**
cparata	2:a94816b14e3d	533	* @brief Accelerometer X-axis user offset correction expressed in two’s
cparata	2:a94816b14e3d	534	* complement, weight depends on bit USR_OFF_W. The value must be
cparata	2:a94816b14e3d	535	* in the range [-127 127].[get]
cparata	0:dff8803aace7	536	*
cparata	2:a94816b14e3d	537	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	538	* @param buff buffer that stores data read
cparata	2:a94816b14e3d	539	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	540	*
cparata	0:dff8803aace7	541	*/
cparata	0:dff8803aace7	542	int32_t lis2dw12_usr_offset_x_get(lis2dw12_ctx_t ctx, uint8_t buff)
cparata	0:dff8803aace7	543	{
cparata	2:a94816b14e3d	544	int32_t ret;
cparata	2:a94816b14e3d	545	ret = lis2dw12_read_reg(ctx, LIS2DW12_X_OFS_USR, buff, 1);
cparata	2:a94816b14e3d	546	return ret;
cparata	0:dff8803aace7	547	}
cparata	2:a94816b14e3d	548
cparata	0:dff8803aace7	549	/**
cparata	2:a94816b14e3d	550	* @brief Accelerometer Y-axis user offset correction expressed in two’s
cparata	2:a94816b14e3d	551	* complement, weight depends on bit USR_OFF_W. The value must be
cparata	2:a94816b14e3d	552	* in the range [-127 127].[set]
cparata	0:dff8803aace7	553	*
cparata	2:a94816b14e3d	554	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	555	* @param buff buffer that contains data to write
cparata	2:a94816b14e3d	556	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	557	*
cparata	0:dff8803aace7	558	*/
cparata	0:dff8803aace7	559	int32_t lis2dw12_usr_offset_y_set(lis2dw12_ctx_t ctx, uint8_t buff)
cparata	0:dff8803aace7	560	{
cparata	2:a94816b14e3d	561	int32_t ret;
cparata	2:a94816b14e3d	562	ret = lis2dw12_write_reg(ctx, LIS2DW12_Y_OFS_USR, buff, 1);
cparata	2:a94816b14e3d	563	return ret;
cparata	0:dff8803aace7	564	}
cparata	0:dff8803aace7	565
cparata	0:dff8803aace7	566	/**
cparata	2:a94816b14e3d	567	* @brief Accelerometer Y-axis user offset correction expressed in two’s
cparata	2:a94816b14e3d	568	* complement, weight depends on bit USR_OFF_W. The value must be
cparata	2:a94816b14e3d	569	* in the range [-127 127].[get]
cparata	0:dff8803aace7	570	*
cparata	2:a94816b14e3d	571	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	572	* @param buff buffer that stores data read
cparata	2:a94816b14e3d	573	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	574	*
cparata	0:dff8803aace7	575	*/
cparata	0:dff8803aace7	576	int32_t lis2dw12_usr_offset_y_get(lis2dw12_ctx_t ctx, uint8_t buff)
cparata	0:dff8803aace7	577	{
cparata	2:a94816b14e3d	578	int32_t ret;
cparata	2:a94816b14e3d	579	ret = lis2dw12_read_reg(ctx, LIS2DW12_Y_OFS_USR, buff, 1);
cparata	2:a94816b14e3d	580	return ret;
cparata	0:dff8803aace7	581	}
cparata	2:a94816b14e3d	582
cparata	0:dff8803aace7	583	/**
cparata	2:a94816b14e3d	584	* @brief Accelerometer Z-axis user offset correction expressed in two’s
cparata	2:a94816b14e3d	585	* complement, weight depends on bit USR_OFF_W. The value must be
cparata	2:a94816b14e3d	586	* in the range [-127 127].[set]
cparata	0:dff8803aace7	587	*
cparata	2:a94816b14e3d	588	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	589	* @param buff buffer that contains data to write
cparata	2:a94816b14e3d	590	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	591	*
cparata	0:dff8803aace7	592	*/
cparata	0:dff8803aace7	593	int32_t lis2dw12_usr_offset_z_set(lis2dw12_ctx_t ctx, uint8_t buff)
cparata	0:dff8803aace7	594	{
cparata	2:a94816b14e3d	595	int32_t ret;
cparata	2:a94816b14e3d	596	ret = lis2dw12_write_reg(ctx, LIS2DW12_Z_OFS_USR, buff, 1);
cparata	2:a94816b14e3d	597	return ret;
cparata	0:dff8803aace7	598	}
cparata	0:dff8803aace7	599
cparata	0:dff8803aace7	600	/**
cparata	2:a94816b14e3d	601	* @brief Accelerometer Z-axis user offset correction expressed in two’s
cparata	2:a94816b14e3d	602	* complement, weight depends on bit USR_OFF_W. The value must be
cparata	2:a94816b14e3d	603	* in the range [-127 127].[get]
cparata	0:dff8803aace7	604	*
cparata	2:a94816b14e3d	605	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	606	* @param buff buffer that stores data read
cparata	2:a94816b14e3d	607	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	608	*
cparata	0:dff8803aace7	609	*/
cparata	0:dff8803aace7	610	int32_t lis2dw12_usr_offset_z_get(lis2dw12_ctx_t ctx, uint8_t buff)
cparata	0:dff8803aace7	611	{
cparata	2:a94816b14e3d	612	int32_t ret;
cparata	2:a94816b14e3d	613	ret = lis2dw12_read_reg(ctx, LIS2DW12_Z_OFS_USR, buff, 1);
cparata	2:a94816b14e3d	614	return ret;
cparata	0:dff8803aace7	615	}
cparata	2:a94816b14e3d	616
cparata	0:dff8803aace7	617	/**
cparata	2:a94816b14e3d	618	* @brief Weight of XL user offset bits of registers X_OFS_USR,
cparata	2:a94816b14e3d	619	* Y_OFS_USR, Z_OFS_USR.[set]
cparata	0:dff8803aace7	620	*
cparata	2:a94816b14e3d	621	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	622	* @param val change the values of usr_off_w in
cparata	0:dff8803aace7	623	* reg CTRL_REG7
cparata	2:a94816b14e3d	624	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	625	*
cparata	0:dff8803aace7	626	*/
cparata	0:dff8803aace7	627	int32_t lis2dw12_offset_weight_set(lis2dw12_ctx_t *ctx,
cparata	2:a94816b14e3d	628	lis2dw12_usr_off_w_t val)
cparata	0:dff8803aace7	629	{
cparata	2:a94816b14e3d	630	lis2dw12_ctrl_reg7_t reg;
cparata	2:a94816b14e3d	631	int32_t ret;
cparata	0:dff8803aace7	632
cparata	2:a94816b14e3d	633	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	634	if (ret == 0) {
cparata	2:a94816b14e3d	635	reg.usr_off_w = (uint8_t) val;
cparata	2:a94816b14e3d	636	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	637	}
cparata	2:a94816b14e3d	638	return ret;
cparata	0:dff8803aace7	639	}
cparata	0:dff8803aace7	640
cparata	0:dff8803aace7	641	/**
cparata	2:a94816b14e3d	642	* @brief Weight of XL user offset bits of registers X_OFS_USR,
cparata	2:a94816b14e3d	643	* Y_OFS_USR, Z_OFS_USR.[get]
cparata	0:dff8803aace7	644	*
cparata	2:a94816b14e3d	645	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	646	* @param val Get the values of usr_off_w in reg CTRL_REG7
cparata	2:a94816b14e3d	647	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	648	*
cparata	0:dff8803aace7	649	*/
cparata	0:dff8803aace7	650	int32_t lis2dw12_offset_weight_get(lis2dw12_ctx_t *ctx,
cparata	2:a94816b14e3d	651	lis2dw12_usr_off_w_t *val)
cparata	0:dff8803aace7	652	{
cparata	2:a94816b14e3d	653	lis2dw12_ctrl_reg7_t reg;
cparata	2:a94816b14e3d	654	int32_t ret;
cparata	0:dff8803aace7	655
cparata	2:a94816b14e3d	656	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	657	switch (reg.usr_off_w) {
cparata	2:a94816b14e3d	658	case LIS2DW12_LSb_977ug:
cparata	2:a94816b14e3d	659	*val = LIS2DW12_LSb_977ug;
cparata	2:a94816b14e3d	660	break;
cparata	2:a94816b14e3d	661	case LIS2DW12_LSb_15mg6:
cparata	2:a94816b14e3d	662	*val = LIS2DW12_LSb_15mg6;
cparata	2:a94816b14e3d	663	break;
cparata	2:a94816b14e3d	664	default:
cparata	2:a94816b14e3d	665	*val = LIS2DW12_LSb_977ug;
cparata	2:a94816b14e3d	666	break;
cparata	2:a94816b14e3d	667	}
cparata	2:a94816b14e3d	668	return ret;
cparata	0:dff8803aace7	669	}
cparata	0:dff8803aace7	670
cparata	0:dff8803aace7	671	/**
cparata	0:dff8803aace7	672	* @}
cparata	2:a94816b14e3d	673	*
cparata	0:dff8803aace7	674	*/
cparata	0:dff8803aace7	675
cparata	0:dff8803aace7	676	/**
cparata	2:a94816b14e3d	677	* @defgroup LIS2DW12_Data_Output
cparata	2:a94816b14e3d	678	* @brief This section groups all the data output functions.
cparata	0:dff8803aace7	679	* @{
cparata	2:a94816b14e3d	680	*
cparata	0:dff8803aace7	681	*/
cparata	0:dff8803aace7	682
cparata	0:dff8803aace7	683	/**
cparata	2:a94816b14e3d	684	* @brief Temperature data output register (r). L and H registers
cparata	2:a94816b14e3d	685	* together express a 16-bit word in two’s complement.[get]
cparata	0:dff8803aace7	686	*
cparata	2:a94816b14e3d	687	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	688	* @param buff buffer that stores data read
cparata	2:a94816b14e3d	689	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	690	*
cparata	0:dff8803aace7	691	*/
cparata	0:dff8803aace7	692	int32_t lis2dw12_temperature_raw_get(lis2dw12_ctx_t ctx, uint8_t buff)
cparata	0:dff8803aace7	693	{
cparata	2:a94816b14e3d	694	int32_t ret;
cparata	2:a94816b14e3d	695	ret = lis2dw12_read_reg(ctx, LIS2DW12_OUT_T_L, buff, 2);
cparata	2:a94816b14e3d	696	return ret;
cparata	0:dff8803aace7	697	}
cparata	0:dff8803aace7	698
cparata	0:dff8803aace7	699	/**
cparata	2:a94816b14e3d	700	* @brief Linear acceleration output register. The value is expressed as
cparata	2:a94816b14e3d	701	* a 16-bit word in two’s complement.[get]
cparata	0:dff8803aace7	702	*
cparata	2:a94816b14e3d	703	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	704	* @param buff buffer that stores data read
cparata	2:a94816b14e3d	705	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	706	*
cparata	0:dff8803aace7	707	*/
cparata	0:dff8803aace7	708	int32_t lis2dw12_acceleration_raw_get(lis2dw12_ctx_t ctx, uint8_t buff)
cparata	0:dff8803aace7	709	{
cparata	2:a94816b14e3d	710	int32_t ret;
cparata	2:a94816b14e3d	711	ret = lis2dw12_read_reg(ctx, LIS2DW12_OUT_X_L, buff, 6);
cparata	2:a94816b14e3d	712	return ret;
cparata	0:dff8803aace7	713	}
cparata	0:dff8803aace7	714
cparata	0:dff8803aace7	715	/**
cparata	0:dff8803aace7	716	* @}
cparata	2:a94816b14e3d	717	*
cparata	0:dff8803aace7	718	*/
cparata	0:dff8803aace7	719
cparata	0:dff8803aace7	720	/**
cparata	2:a94816b14e3d	721	* @defgroup LIS2DW12_Common
cparata	2:a94816b14e3d	722	* @brief This section groups common useful functions.
cparata	0:dff8803aace7	723	* @{
cparata	2:a94816b14e3d	724	*
cparata	0:dff8803aace7	725	*/
cparata	0:dff8803aace7	726
cparata	0:dff8803aace7	727	/**
cparata	2:a94816b14e3d	728	* @brief Device Who am I.[get]
cparata	0:dff8803aace7	729	*
cparata	2:a94816b14e3d	730	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	731	* @param buff buffer that stores data read
cparata	2:a94816b14e3d	732	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	733	*
cparata	0:dff8803aace7	734	*/
cparata	0:dff8803aace7	735	int32_t lis2dw12_device_id_get(lis2dw12_ctx_t ctx, uint8_t buff)
cparata	0:dff8803aace7	736	{
cparata	2:a94816b14e3d	737	int32_t ret;
cparata	2:a94816b14e3d	738	ret = lis2dw12_read_reg(ctx, LIS2DW12_WHO_AM_I, buff, 1);
cparata	2:a94816b14e3d	739	return ret;
cparata	0:dff8803aace7	740	}
cparata	0:dff8803aace7	741
cparata	0:dff8803aace7	742	/**
cparata	2:a94816b14e3d	743	* @brief Register address automatically incremented during multiple byte
cparata	2:a94816b14e3d	744	* access with a serial interface.[set]
cparata	0:dff8803aace7	745	*
cparata	2:a94816b14e3d	746	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	747	* @param val change the values of if_add_inc in reg CTRL2
cparata	2:a94816b14e3d	748	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	749	*
cparata	0:dff8803aace7	750	*/
cparata	0:dff8803aace7	751	int32_t lis2dw12_auto_increment_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	752	{
cparata	2:a94816b14e3d	753	lis2dw12_ctrl2_t reg;
cparata	2:a94816b14e3d	754	int32_t ret;
cparata	0:dff8803aace7	755
cparata	2:a94816b14e3d	756	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	757	if (ret == 0) {
cparata	2:a94816b14e3d	758	reg.if_add_inc = val;
cparata	2:a94816b14e3d	759	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	760	}
cparata	2:a94816b14e3d	761	return ret;
cparata	0:dff8803aace7	762	}
cparata	0:dff8803aace7	763
cparata	0:dff8803aace7	764	/**
cparata	2:a94816b14e3d	765	* @brief Register address automatically incremented during multiple
cparata	2:a94816b14e3d	766	* byte access with a serial interface.[get]
cparata	0:dff8803aace7	767	*
cparata	2:a94816b14e3d	768	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	769	* @param val change the values of if_add_inc in reg CTRL2
cparata	2:a94816b14e3d	770	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	771	*
cparata	0:dff8803aace7	772	*/
cparata	0:dff8803aace7	773	int32_t lis2dw12_auto_increment_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	774	{
cparata	2:a94816b14e3d	775	lis2dw12_ctrl2_t reg;
cparata	2:a94816b14e3d	776	int32_t ret;
cparata	0:dff8803aace7	777
cparata	2:a94816b14e3d	778	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	779	*val = reg.if_add_inc;
cparata	0:dff8803aace7	780
cparata	2:a94816b14e3d	781	return ret;
cparata	0:dff8803aace7	782	}
cparata	0:dff8803aace7	783
cparata	0:dff8803aace7	784	/**
cparata	2:a94816b14e3d	785	* @brief Software reset. Restore the default values in user registers.[set]
cparata	0:dff8803aace7	786	*
cparata	2:a94816b14e3d	787	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	788	* @param val change the values of soft_reset in reg CTRL2
cparata	2:a94816b14e3d	789	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	790	*
cparata	0:dff8803aace7	791	*/
cparata	0:dff8803aace7	792	int32_t lis2dw12_reset_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	793	{
cparata	2:a94816b14e3d	794	lis2dw12_ctrl2_t reg;
cparata	2:a94816b14e3d	795	int32_t ret;
cparata	0:dff8803aace7	796
cparata	2:a94816b14e3d	797	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	798	if (ret == 0) {
cparata	2:a94816b14e3d	799	reg.soft_reset = val;
cparata	2:a94816b14e3d	800	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	801	}
cparata	0:dff8803aace7	802
cparata	2:a94816b14e3d	803	return ret;
cparata	0:dff8803aace7	804	}
cparata	0:dff8803aace7	805
cparata	0:dff8803aace7	806	/**
cparata	2:a94816b14e3d	807	* @brief Software reset. Restore the default values in user registers.[get]
cparata	0:dff8803aace7	808	*
cparata	2:a94816b14e3d	809	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	810	* @param val change the values of soft_reset in reg CTRL2
cparata	2:a94816b14e3d	811	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	812	*
cparata	0:dff8803aace7	813	*/
cparata	0:dff8803aace7	814	int32_t lis2dw12_reset_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	815	{
cparata	2:a94816b14e3d	816	lis2dw12_ctrl2_t reg;
cparata	2:a94816b14e3d	817	int32_t ret;
cparata	0:dff8803aace7	818
cparata	2:a94816b14e3d	819	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	820	*val = reg.soft_reset;
cparata	0:dff8803aace7	821
cparata	2:a94816b14e3d	822	return ret;
cparata	0:dff8803aace7	823	}
cparata	0:dff8803aace7	824
cparata	0:dff8803aace7	825	/**
cparata	2:a94816b14e3d	826	* @brief Reboot memory content. Reload the calibration parameters.[set]
cparata	0:dff8803aace7	827	*
cparata	2:a94816b14e3d	828	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	829	* @param val change the values of boot in reg CTRL2
cparata	2:a94816b14e3d	830	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	831	*
cparata	0:dff8803aace7	832	*/
cparata	0:dff8803aace7	833	int32_t lis2dw12_boot_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	834	{
cparata	2:a94816b14e3d	835	lis2dw12_ctrl2_t reg;
cparata	2:a94816b14e3d	836	int32_t ret;
cparata	0:dff8803aace7	837
cparata	2:a94816b14e3d	838	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	839	if (ret == 0) {
cparata	2:a94816b14e3d	840	reg.boot = val;
cparata	2:a94816b14e3d	841	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	842	}
cparata	2:a94816b14e3d	843	return ret;
cparata	0:dff8803aace7	844	}
cparata	0:dff8803aace7	845
cparata	0:dff8803aace7	846	/**
cparata	2:a94816b14e3d	847	* @brief Reboot memory content. Reload the calibration parameters.[get]
cparata	0:dff8803aace7	848	*
cparata	2:a94816b14e3d	849	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	850	* @param val change the values of boot in reg CTRL2
cparata	2:a94816b14e3d	851	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	852	*
cparata	0:dff8803aace7	853	*/
cparata	0:dff8803aace7	854	int32_t lis2dw12_boot_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	855	{
cparata	2:a94816b14e3d	856	lis2dw12_ctrl2_t reg;
cparata	2:a94816b14e3d	857	int32_t ret;
cparata	0:dff8803aace7	858
cparata	2:a94816b14e3d	859	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	860	*val = reg.boot;
cparata	0:dff8803aace7	861
cparata	2:a94816b14e3d	862	return ret;
cparata	0:dff8803aace7	863	}
cparata	0:dff8803aace7	864
cparata	0:dff8803aace7	865	/**
cparata	2:a94816b14e3d	866	* @brief Sensor self-test enable.[set]
cparata	0:dff8803aace7	867	*
cparata	2:a94816b14e3d	868	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	869	* @param val change the values of st in reg CTRL3
cparata	2:a94816b14e3d	870	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	871	*
cparata	0:dff8803aace7	872	*/
cparata	0:dff8803aace7	873	int32_t lis2dw12_self_test_set(lis2dw12_ctx_t *ctx, lis2dw12_st_t val)
cparata	0:dff8803aace7	874	{
cparata	2:a94816b14e3d	875	lis2dw12_ctrl3_t reg;
cparata	2:a94816b14e3d	876	int32_t ret;
cparata	0:dff8803aace7	877
cparata	2:a94816b14e3d	878	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	879	if (ret == 0) {
cparata	2:a94816b14e3d	880	reg.st = (uint8_t) val;
cparata	2:a94816b14e3d	881	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	882	}
cparata	0:dff8803aace7	883
cparata	2:a94816b14e3d	884	return ret;
cparata	0:dff8803aace7	885	}
cparata	0:dff8803aace7	886
cparata	0:dff8803aace7	887	/**
cparata	2:a94816b14e3d	888	* @brief Sensor self-test enable.[get]
cparata	0:dff8803aace7	889	*
cparata	2:a94816b14e3d	890	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	891	* @param val Get the values of st in reg CTRL3
cparata	2:a94816b14e3d	892	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	893	*
cparata	0:dff8803aace7	894	*/
cparata	0:dff8803aace7	895	int32_t lis2dw12_self_test_get(lis2dw12_ctx_t ctx, lis2dw12_st_t val)
cparata	0:dff8803aace7	896	{
cparata	2:a94816b14e3d	897	lis2dw12_ctrl3_t reg;
cparata	2:a94816b14e3d	898	int32_t ret;
cparata	2:a94816b14e3d	899
cparata	2:a94816b14e3d	900	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) &reg, 1);
cparata	0:dff8803aace7	901
cparata	2:a94816b14e3d	902	switch (reg.st) {
cparata	2:a94816b14e3d	903	case LIS2DW12_XL_ST_DISABLE:
cparata	2:a94816b14e3d	904	*val = LIS2DW12_XL_ST_DISABLE;
cparata	2:a94816b14e3d	905	break;
cparata	2:a94816b14e3d	906	case LIS2DW12_XL_ST_POSITIVE:
cparata	2:a94816b14e3d	907	*val = LIS2DW12_XL_ST_POSITIVE;
cparata	2:a94816b14e3d	908	break;
cparata	2:a94816b14e3d	909	case LIS2DW12_XL_ST_NEGATIVE:
cparata	2:a94816b14e3d	910	*val = LIS2DW12_XL_ST_NEGATIVE;
cparata	2:a94816b14e3d	911	break;
cparata	2:a94816b14e3d	912	default:
cparata	2:a94816b14e3d	913	*val = LIS2DW12_XL_ST_DISABLE;
cparata	2:a94816b14e3d	914	break;
cparata	2:a94816b14e3d	915	}
cparata	2:a94816b14e3d	916	return ret;
cparata	0:dff8803aace7	917	}
cparata	0:dff8803aace7	918
cparata	0:dff8803aace7	919	/**
cparata	2:a94816b14e3d	920	* @brief Data-ready pulsed / letched mode.[set]
cparata	0:dff8803aace7	921	*
cparata	2:a94816b14e3d	922	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	923	* @param val change the values of drdy_pulsed in reg CTRL_REG7
cparata	2:a94816b14e3d	924	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	925	*
cparata	0:dff8803aace7	926	*/
cparata	0:dff8803aace7	927	int32_t lis2dw12_data_ready_mode_set(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	928	lis2dw12_drdy_pulsed_t val)
cparata	0:dff8803aace7	929	{
cparata	2:a94816b14e3d	930	lis2dw12_ctrl_reg7_t reg;
cparata	2:a94816b14e3d	931	int32_t ret;
cparata	0:dff8803aace7	932
cparata	2:a94816b14e3d	933	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	934	if (ret == 0) {
cparata	2:a94816b14e3d	935	reg.drdy_pulsed = (uint8_t) val;
cparata	2:a94816b14e3d	936	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	937	}
cparata	0:dff8803aace7	938
cparata	2:a94816b14e3d	939	return ret;
cparata	0:dff8803aace7	940	}
cparata	0:dff8803aace7	941
cparata	0:dff8803aace7	942	/**
cparata	2:a94816b14e3d	943	* @brief Data-ready pulsed / letched mode.[get]
cparata	0:dff8803aace7	944	*
cparata	2:a94816b14e3d	945	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	946	* @param val Get the values of drdy_pulsed in reg CTRL_REG7
cparata	2:a94816b14e3d	947	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	948	*
cparata	0:dff8803aace7	949	*/
cparata	0:dff8803aace7	950	int32_t lis2dw12_data_ready_mode_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	951	lis2dw12_drdy_pulsed_t *val)
cparata	0:dff8803aace7	952	{
cparata	2:a94816b14e3d	953	lis2dw12_ctrl_reg7_t reg;
cparata	2:a94816b14e3d	954	int32_t ret;
cparata	2:a94816b14e3d	955
cparata	2:a94816b14e3d	956	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:dff8803aace7	957
cparata	2:a94816b14e3d	958	switch (reg.drdy_pulsed) {
cparata	2:a94816b14e3d	959	case LIS2DW12_DRDY_LATCHED:
cparata	2:a94816b14e3d	960	*val = LIS2DW12_DRDY_LATCHED;
cparata	2:a94816b14e3d	961	break;
cparata	2:a94816b14e3d	962	case LIS2DW12_DRDY_PULSED:
cparata	2:a94816b14e3d	963	*val = LIS2DW12_DRDY_PULSED;
cparata	2:a94816b14e3d	964	break;
cparata	2:a94816b14e3d	965	default:
cparata	2:a94816b14e3d	966	*val = LIS2DW12_DRDY_LATCHED;
cparata	2:a94816b14e3d	967	break;
cparata	2:a94816b14e3d	968	}
cparata	2:a94816b14e3d	969	return ret;
cparata	0:dff8803aace7	970	}
cparata	0:dff8803aace7	971
cparata	0:dff8803aace7	972	/**
cparata	0:dff8803aace7	973	* @}
cparata	2:a94816b14e3d	974	*
cparata	0:dff8803aace7	975	*/
cparata	0:dff8803aace7	976
cparata	0:dff8803aace7	977	/**
cparata	2:a94816b14e3d	978	* @defgroup LIS2DW12_Filters
cparata	2:a94816b14e3d	979	* @brief This section group all the functions concerning the filters
cparata	2:a94816b14e3d	980	* configuration.
cparata	0:dff8803aace7	981	* @{
cparata	2:a94816b14e3d	982	*
cparata	0:dff8803aace7	983	*/
cparata	0:dff8803aace7	984
cparata	0:dff8803aace7	985	/**
cparata	2:a94816b14e3d	986	* @brief Accelerometer filtering path for outputs.[set]
cparata	0:dff8803aace7	987	*
cparata	2:a94816b14e3d	988	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	989	* @param val change the values of fds in reg CTRL6
cparata	2:a94816b14e3d	990	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	991	*
cparata	0:dff8803aace7	992	*/
cparata	0:dff8803aace7	993	int32_t lis2dw12_filter_path_set(lis2dw12_ctx_t *ctx, lis2dw12_fds_t val)
cparata	0:dff8803aace7	994	{
cparata	2:a94816b14e3d	995	lis2dw12_ctrl6_t ctrl6;
cparata	2:a94816b14e3d	996	lis2dw12_ctrl_reg7_t ctrl_reg7;
cparata	2:a94816b14e3d	997	int32_t ret;
cparata	0:dff8803aace7	998
cparata	2:a94816b14e3d	999	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &ctrl6, 1);
cparata	2:a94816b14e3d	1000	if (ret == 0) {
cparata	2:a94816b14e3d	1001	ctrl6.fds = ( (uint8_t) val & 0x10U ) >> 4;
cparata	2:a94816b14e3d	1002	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &ctrl6, 1);
cparata	2:a94816b14e3d	1003	}
cparata	2:a94816b14e3d	1004	if (ret == 0) {
cparata	2:a94816b14e3d	1005	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &ctrl_reg7, 1);
cparata	2:a94816b14e3d	1006	}
cparata	2:a94816b14e3d	1007	if (ret == 0) {
cparata	2:a94816b14e3d	1008	ctrl_reg7.usr_off_on_out = (uint8_t) val & 0x01U;
cparata	2:a94816b14e3d	1009	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &ctrl_reg7, 1);
cparata	2:a94816b14e3d	1010	}
cparata	0:dff8803aace7	1011
cparata	2:a94816b14e3d	1012	return ret;
cparata	0:dff8803aace7	1013	}
cparata	0:dff8803aace7	1014
cparata	0:dff8803aace7	1015	/**
cparata	2:a94816b14e3d	1016	* @brief Accelerometer filtering path for outputs.[get]
cparata	0:dff8803aace7	1017	*
cparata	2:a94816b14e3d	1018	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1019	* @param val Get the values of fds in reg CTRL6
cparata	2:a94816b14e3d	1020	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1021	*
cparata	0:dff8803aace7	1022	*/
cparata	0:dff8803aace7	1023	int32_t lis2dw12_filter_path_get(lis2dw12_ctx_t ctx, lis2dw12_fds_t val)
cparata	0:dff8803aace7	1024	{
cparata	2:a94816b14e3d	1025	lis2dw12_ctrl6_t ctrl6;
cparata	2:a94816b14e3d	1026	lis2dw12_ctrl_reg7_t ctrl_reg7;
cparata	2:a94816b14e3d	1027	int32_t ret;
cparata	0:dff8803aace7	1028
cparata	2:a94816b14e3d	1029	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &ctrl6, 1);
cparata	2:a94816b14e3d	1030	if (ret == 0) {
cparata	2:a94816b14e3d	1031	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &ctrl_reg7, 1);
cparata	0:dff8803aace7	1032
cparata	2:a94816b14e3d	1033	switch ((ctrl6.fds << 4 ) + ctrl_reg7.usr_off_on_out) {
cparata	2:a94816b14e3d	1034	case LIS2DW12_LPF_ON_OUT:
cparata	2:a94816b14e3d	1035	*val = LIS2DW12_LPF_ON_OUT;
cparata	2:a94816b14e3d	1036	break;
cparata	2:a94816b14e3d	1037	case LIS2DW12_USER_OFFSET_ON_OUT:
cparata	2:a94816b14e3d	1038	*val = LIS2DW12_USER_OFFSET_ON_OUT;
cparata	2:a94816b14e3d	1039	break;
cparata	2:a94816b14e3d	1040	case LIS2DW12_HIGH_PASS_ON_OUT:
cparata	2:a94816b14e3d	1041	*val = LIS2DW12_HIGH_PASS_ON_OUT;
cparata	2:a94816b14e3d	1042	break;
cparata	2:a94816b14e3d	1043	default:
cparata	2:a94816b14e3d	1044	*val = LIS2DW12_LPF_ON_OUT;
cparata	2:a94816b14e3d	1045	break;
cparata	2:a94816b14e3d	1046	}
cparata	2:a94816b14e3d	1047	}
cparata	2:a94816b14e3d	1048	return ret;
cparata	0:dff8803aace7	1049	}
cparata	0:dff8803aace7	1050
cparata	0:dff8803aace7	1051	/**
cparata	2:a94816b14e3d	1052	* @brief Accelerometer cutoff filter frequency. Valid for low and high
cparata	2:a94816b14e3d	1053	* pass filter.[set]
cparata	0:dff8803aace7	1054	*
cparata	2:a94816b14e3d	1055	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1056	* @param val change the values of bw_filt in reg CTRL6
cparata	2:a94816b14e3d	1057	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1058	*
cparata	0:dff8803aace7	1059	*/
cparata	0:dff8803aace7	1060	int32_t lis2dw12_filter_bandwidth_set(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1061	lis2dw12_bw_filt_t val)
cparata	0:dff8803aace7	1062	{
cparata	2:a94816b14e3d	1063	lis2dw12_ctrl6_t reg;
cparata	2:a94816b14e3d	1064	int32_t ret;
cparata	0:dff8803aace7	1065
cparata	2:a94816b14e3d	1066	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1067	if (ret == 0) {
cparata	2:a94816b14e3d	1068	reg.bw_filt = (uint8_t) val;
cparata	2:a94816b14e3d	1069	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1070	}
cparata	0:dff8803aace7	1071
cparata	2:a94816b14e3d	1072	return ret;
cparata	0:dff8803aace7	1073	}
cparata	0:dff8803aace7	1074
cparata	0:dff8803aace7	1075	/**
cparata	2:a94816b14e3d	1076	* @brief Accelerometer cutoff filter frequency. Valid for low and
cparata	2:a94816b14e3d	1077	* high pass filter.[get]
cparata	0:dff8803aace7	1078	*
cparata	2:a94816b14e3d	1079	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1080	* @param val Get the values of bw_filt in reg CTRL6
cparata	2:a94816b14e3d	1081	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1082	*
cparata	0:dff8803aace7	1083	*/
cparata	0:dff8803aace7	1084	int32_t lis2dw12_filter_bandwidth_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1085	lis2dw12_bw_filt_t *val)
cparata	0:dff8803aace7	1086	{
cparata	2:a94816b14e3d	1087	lis2dw12_ctrl6_t reg;
cparata	2:a94816b14e3d	1088	int32_t ret;
cparata	2:a94816b14e3d	1089
cparata	2:a94816b14e3d	1090	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &reg, 1);
cparata	0:dff8803aace7	1091
cparata	2:a94816b14e3d	1092	switch (reg.bw_filt) {
cparata	2:a94816b14e3d	1093	case LIS2DW12_ODR_DIV_2:
cparata	2:a94816b14e3d	1094	*val = LIS2DW12_ODR_DIV_2;
cparata	2:a94816b14e3d	1095	break;
cparata	2:a94816b14e3d	1096	case LIS2DW12_ODR_DIV_4:
cparata	2:a94816b14e3d	1097	*val = LIS2DW12_ODR_DIV_4;
cparata	2:a94816b14e3d	1098	break;
cparata	2:a94816b14e3d	1099	case LIS2DW12_ODR_DIV_10:
cparata	2:a94816b14e3d	1100	*val = LIS2DW12_ODR_DIV_10;
cparata	2:a94816b14e3d	1101	break;
cparata	2:a94816b14e3d	1102	case LIS2DW12_ODR_DIV_20:
cparata	2:a94816b14e3d	1103	*val = LIS2DW12_ODR_DIV_20;
cparata	2:a94816b14e3d	1104	break;
cparata	2:a94816b14e3d	1105	default:
cparata	2:a94816b14e3d	1106	*val = LIS2DW12_ODR_DIV_2;
cparata	2:a94816b14e3d	1107	break;
cparata	2:a94816b14e3d	1108	}
cparata	2:a94816b14e3d	1109	return ret;
cparata	0:dff8803aace7	1110	}
cparata	0:dff8803aace7	1111
cparata	0:dff8803aace7	1112	/**
cparata	2:a94816b14e3d	1113	* @brief Enable HP filter reference mode.[set]
cparata	0:dff8803aace7	1114	*
cparata	2:a94816b14e3d	1115	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1116	* @param val change the values of hp_ref_mode in reg CTRL_REG7
cparata	2:a94816b14e3d	1117	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1118	*
cparata	0:dff8803aace7	1119	*/
cparata	0:dff8803aace7	1120	int32_t lis2dw12_reference_mode_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	1121	{
cparata	2:a94816b14e3d	1122	lis2dw12_ctrl_reg7_t reg;
cparata	2:a94816b14e3d	1123	int32_t ret;
cparata	0:dff8803aace7	1124
cparata	2:a94816b14e3d	1125	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1126	if (ret == 0) {
cparata	2:a94816b14e3d	1127	reg.hp_ref_mode = val;
cparata	2:a94816b14e3d	1128	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1129	}
cparata	2:a94816b14e3d	1130	return ret;
cparata	0:dff8803aace7	1131	}
cparata	0:dff8803aace7	1132
cparata	0:dff8803aace7	1133	/**
cparata	2:a94816b14e3d	1134	* @brief Enable HP filter reference mode.[get]
cparata	0:dff8803aace7	1135	*
cparata	2:a94816b14e3d	1136	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1137	* @param val change the values of hp_ref_mode in reg CTRL_REG7
cparata	2:a94816b14e3d	1138	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1139	*
cparata	0:dff8803aace7	1140	*/
cparata	0:dff8803aace7	1141	int32_t lis2dw12_reference_mode_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	1142	{
cparata	2:a94816b14e3d	1143	lis2dw12_ctrl_reg7_t reg;
cparata	2:a94816b14e3d	1144	int32_t ret;
cparata	0:dff8803aace7	1145
cparata	2:a94816b14e3d	1146	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1147	*val = reg.hp_ref_mode;
cparata	0:dff8803aace7	1148
cparata	2:a94816b14e3d	1149	return ret;
cparata	0:dff8803aace7	1150	}
cparata	0:dff8803aace7	1151
cparata	0:dff8803aace7	1152	/**
cparata	0:dff8803aace7	1153	* @}
cparata	2:a94816b14e3d	1154	*
cparata	0:dff8803aace7	1155	*/
cparata	0:dff8803aace7	1156
cparata	0:dff8803aace7	1157	/**
cparata	2:a94816b14e3d	1158	* @defgroup LIS2DW12_Serial_Interface
cparata	2:a94816b14e3d	1159	* @brief This section groups all the functions concerning main serial
cparata	2:a94816b14e3d	1160	* interface management (not auxiliary)
cparata	0:dff8803aace7	1161	* @{
cparata	2:a94816b14e3d	1162	*
cparata	0:dff8803aace7	1163	*/
cparata	0:dff8803aace7	1164
cparata	0:dff8803aace7	1165	/**
cparata	2:a94816b14e3d	1166	* @brief SPI Serial Interface Mode selection.[set]
cparata	0:dff8803aace7	1167	*
cparata	2:a94816b14e3d	1168	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1169	* @param val change the values of sim in reg CTRL2
cparata	2:a94816b14e3d	1170	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1171	*
cparata	0:dff8803aace7	1172	*/
cparata	0:dff8803aace7	1173	int32_t lis2dw12_spi_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_sim_t val)
cparata	0:dff8803aace7	1174	{
cparata	2:a94816b14e3d	1175	lis2dw12_ctrl2_t reg;
cparata	2:a94816b14e3d	1176	int32_t ret;
cparata	0:dff8803aace7	1177
cparata	2:a94816b14e3d	1178	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1179	if (ret == 0) {
cparata	2:a94816b14e3d	1180	reg.sim = (uint8_t) val;
cparata	2:a94816b14e3d	1181	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1182	}
cparata	2:a94816b14e3d	1183	return ret;
cparata	0:dff8803aace7	1184	}
cparata	0:dff8803aace7	1185
cparata	0:dff8803aace7	1186	/**
cparata	2:a94816b14e3d	1187	* @brief SPI Serial Interface Mode selection.[get]
cparata	0:dff8803aace7	1188	*
cparata	2:a94816b14e3d	1189	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1190	* @param val Get the values of sim in reg CTRL2
cparata	2:a94816b14e3d	1191	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1192	*
cparata	0:dff8803aace7	1193	*/
cparata	0:dff8803aace7	1194	int32_t lis2dw12_spi_mode_get(lis2dw12_ctx_t ctx, lis2dw12_sim_t val)
cparata	0:dff8803aace7	1195	{
cparata	2:a94816b14e3d	1196	lis2dw12_ctrl2_t reg;
cparata	2:a94816b14e3d	1197	int32_t ret;
cparata	2:a94816b14e3d	1198
cparata	2:a94816b14e3d	1199	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) &reg, 1);
cparata	0:dff8803aace7	1200
cparata	2:a94816b14e3d	1201	switch (reg.sim) {
cparata	2:a94816b14e3d	1202	case LIS2DW12_SPI_4_WIRE:
cparata	2:a94816b14e3d	1203	*val = LIS2DW12_SPI_4_WIRE;
cparata	2:a94816b14e3d	1204	break;
cparata	2:a94816b14e3d	1205	case LIS2DW12_SPI_3_WIRE:
cparata	2:a94816b14e3d	1206	*val = LIS2DW12_SPI_3_WIRE;
cparata	2:a94816b14e3d	1207	break;
cparata	2:a94816b14e3d	1208	default:
cparata	2:a94816b14e3d	1209	*val = LIS2DW12_SPI_4_WIRE;
cparata	2:a94816b14e3d	1210	break;
cparata	2:a94816b14e3d	1211	}
cparata	2:a94816b14e3d	1212	return ret;
cparata	0:dff8803aace7	1213	}
cparata	0:dff8803aace7	1214
cparata	0:dff8803aace7	1215	/**
cparata	2:a94816b14e3d	1216	* @brief Disable / Enable I2C interface.[set]
cparata	0:dff8803aace7	1217	*
cparata	2:a94816b14e3d	1218	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1219	* @param val change the values of i2c_disable in
cparata	0:dff8803aace7	1220	* reg CTRL2
cparata	2:a94816b14e3d	1221	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1222	*
cparata	0:dff8803aace7	1223	*/
cparata	0:dff8803aace7	1224	int32_t lis2dw12_i2c_interface_set(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1225	lis2dw12_i2c_disable_t val)
cparata	0:dff8803aace7	1226	{
cparata	2:a94816b14e3d	1227	lis2dw12_ctrl2_t reg;
cparata	2:a94816b14e3d	1228	int32_t ret;
cparata	0:dff8803aace7	1229
cparata	2:a94816b14e3d	1230	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1231	if (ret == 0) {
cparata	2:a94816b14e3d	1232	reg.i2c_disable = (uint8_t) val;
cparata	2:a94816b14e3d	1233	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1234	}
cparata	2:a94816b14e3d	1235	return ret;
cparata	0:dff8803aace7	1236	}
cparata	0:dff8803aace7	1237
cparata	0:dff8803aace7	1238	/**
cparata	2:a94816b14e3d	1239	* @brief Disable / Enable I2C interface.[get]
cparata	0:dff8803aace7	1240	*
cparata	2:a94816b14e3d	1241	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1242	* @param val Get the values of i2c_disable in reg CTRL2
cparata	2:a94816b14e3d	1243	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1244	*
cparata	0:dff8803aace7	1245	*/
cparata	0:dff8803aace7	1246	int32_t lis2dw12_i2c_interface_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1247	lis2dw12_i2c_disable_t *val)
cparata	0:dff8803aace7	1248	{
cparata	2:a94816b14e3d	1249	lis2dw12_ctrl2_t reg;
cparata	2:a94816b14e3d	1250	int32_t ret;
cparata	2:a94816b14e3d	1251
cparata	2:a94816b14e3d	1252	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) &reg, 1);
cparata	0:dff8803aace7	1253
cparata	2:a94816b14e3d	1254	switch (reg.i2c_disable) {
cparata	2:a94816b14e3d	1255	case LIS2DW12_I2C_ENABLE:
cparata	2:a94816b14e3d	1256	*val = LIS2DW12_I2C_ENABLE;
cparata	2:a94816b14e3d	1257	break;
cparata	2:a94816b14e3d	1258	case LIS2DW12_I2C_DISABLE:
cparata	2:a94816b14e3d	1259	*val = LIS2DW12_I2C_DISABLE;
cparata	2:a94816b14e3d	1260	break;
cparata	2:a94816b14e3d	1261	default:
cparata	2:a94816b14e3d	1262	*val = LIS2DW12_I2C_ENABLE;
cparata	2:a94816b14e3d	1263	break;
cparata	2:a94816b14e3d	1264	}
cparata	2:a94816b14e3d	1265	return ret;
cparata	0:dff8803aace7	1266	}
cparata	0:dff8803aace7	1267
cparata	0:dff8803aace7	1268	/**
cparata	2:a94816b14e3d	1269	* @brief Disconnect CS pull-up.[set]
cparata	0:dff8803aace7	1270	*
cparata	2:a94816b14e3d	1271	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1272	* @param val change the values of cs_pu_disc in reg CTRL2
cparata	2:a94816b14e3d	1273	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1274	*
cparata	0:dff8803aace7	1275	*/
cparata	0:dff8803aace7	1276	int32_t lis2dw12_cs_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_cs_pu_disc_t val)
cparata	0:dff8803aace7	1277	{
cparata	2:a94816b14e3d	1278	lis2dw12_ctrl2_t reg;
cparata	2:a94816b14e3d	1279	int32_t ret;
cparata	0:dff8803aace7	1280
cparata	2:a94816b14e3d	1281	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1282	if (ret == 0) {
cparata	2:a94816b14e3d	1283	reg.cs_pu_disc = (uint8_t) val;
cparata	2:a94816b14e3d	1284	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1285	}
cparata	2:a94816b14e3d	1286	return ret;
cparata	0:dff8803aace7	1287	}
cparata	0:dff8803aace7	1288
cparata	0:dff8803aace7	1289	/**
cparata	2:a94816b14e3d	1290	* @brief Disconnect CS pull-up.[get]
cparata	0:dff8803aace7	1291	*
cparata	2:a94816b14e3d	1292	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1293	* @param val Get the values of cs_pu_disc in reg CTRL2
cparata	2:a94816b14e3d	1294	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1295	*
cparata	0:dff8803aace7	1296	*/
cparata	0:dff8803aace7	1297	int32_t lis2dw12_cs_mode_get(lis2dw12_ctx_t ctx, lis2dw12_cs_pu_disc_t val)
cparata	0:dff8803aace7	1298	{
cparata	2:a94816b14e3d	1299	lis2dw12_ctrl2_t reg;
cparata	2:a94816b14e3d	1300	int32_t ret;
cparata	2:a94816b14e3d	1301
cparata	2:a94816b14e3d	1302	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) &reg, 1);
cparata	0:dff8803aace7	1303
cparata	2:a94816b14e3d	1304	switch (reg.cs_pu_disc) {
cparata	2:a94816b14e3d	1305	case LIS2DW12_PULL_UP_CONNECT:
cparata	2:a94816b14e3d	1306	*val = LIS2DW12_PULL_UP_CONNECT;
cparata	2:a94816b14e3d	1307	break;
cparata	2:a94816b14e3d	1308	case LIS2DW12_PULL_UP_DISCONNECT:
cparata	2:a94816b14e3d	1309	*val = LIS2DW12_PULL_UP_DISCONNECT;
cparata	2:a94816b14e3d	1310	break;
cparata	2:a94816b14e3d	1311	default:
cparata	2:a94816b14e3d	1312	*val = LIS2DW12_PULL_UP_CONNECT;
cparata	2:a94816b14e3d	1313	break;
cparata	2:a94816b14e3d	1314	}
cparata	2:a94816b14e3d	1315	return ret;
cparata	0:dff8803aace7	1316	}
cparata	0:dff8803aace7	1317
cparata	0:dff8803aace7	1318	/**
cparata	0:dff8803aace7	1319	* @}
cparata	2:a94816b14e3d	1320	*
cparata	0:dff8803aace7	1321	*/
cparata	0:dff8803aace7	1322
cparata	0:dff8803aace7	1323	/**
cparata	2:a94816b14e3d	1324	* @defgroup LIS2DW12_Interrupt_Pins
cparata	2:a94816b14e3d	1325	* @brief This section groups all the functions that manage interrupt pins
cparata	0:dff8803aace7	1326	* @{
cparata	2:a94816b14e3d	1327	*
cparata	0:dff8803aace7	1328	*/
cparata	0:dff8803aace7	1329
cparata	0:dff8803aace7	1330	/**
cparata	2:a94816b14e3d	1331	* @brief Interrupt active-high/low.[set]
cparata	0:dff8803aace7	1332	*
cparata	2:a94816b14e3d	1333	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1334	* @param val change the values of h_lactive in reg CTRL3
cparata	2:a94816b14e3d	1335	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1336	*
cparata	0:dff8803aace7	1337	*/
cparata	0:dff8803aace7	1338	int32_t lis2dw12_pin_polarity_set(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1339	lis2dw12_h_lactive_t val)
cparata	0:dff8803aace7	1340	{
cparata	2:a94816b14e3d	1341	lis2dw12_ctrl3_t reg;
cparata	2:a94816b14e3d	1342	int32_t ret;
cparata	0:dff8803aace7	1343
cparata	2:a94816b14e3d	1344	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1345	if (ret == 0) {
cparata	2:a94816b14e3d	1346	reg.h_lactive = (uint8_t) val;
cparata	2:a94816b14e3d	1347	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1348	}
cparata	2:a94816b14e3d	1349	return ret;
cparata	0:dff8803aace7	1350	}
cparata	0:dff8803aace7	1351
cparata	0:dff8803aace7	1352	/**
cparata	2:a94816b14e3d	1353	* @brief Interrupt active-high/low.[get]
cparata	0:dff8803aace7	1354	*
cparata	2:a94816b14e3d	1355	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1356	* @param val Get the values of h_lactive in reg CTRL3
cparata	2:a94816b14e3d	1357	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1358	*
cparata	0:dff8803aace7	1359	*/
cparata	0:dff8803aace7	1360	int32_t lis2dw12_pin_polarity_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1361	lis2dw12_h_lactive_t *val)
cparata	0:dff8803aace7	1362	{
cparata	2:a94816b14e3d	1363	lis2dw12_ctrl3_t reg;
cparata	2:a94816b14e3d	1364	int32_t ret;
cparata	2:a94816b14e3d	1365
cparata	2:a94816b14e3d	1366	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) &reg, 1);
cparata	0:dff8803aace7	1367
cparata	2:a94816b14e3d	1368	switch (reg.h_lactive) {
cparata	2:a94816b14e3d	1369	case LIS2DW12_ACTIVE_HIGH:
cparata	2:a94816b14e3d	1370	*val = LIS2DW12_ACTIVE_HIGH;
cparata	2:a94816b14e3d	1371	break;
cparata	2:a94816b14e3d	1372	case LIS2DW12_ACTIVE_LOW:
cparata	2:a94816b14e3d	1373	*val = LIS2DW12_ACTIVE_LOW;
cparata	2:a94816b14e3d	1374	break;
cparata	2:a94816b14e3d	1375	default:
cparata	2:a94816b14e3d	1376	*val = LIS2DW12_ACTIVE_HIGH;
cparata	2:a94816b14e3d	1377	break;
cparata	2:a94816b14e3d	1378	}
cparata	2:a94816b14e3d	1379	return ret;
cparata	0:dff8803aace7	1380	}
cparata	0:dff8803aace7	1381
cparata	0:dff8803aace7	1382	/**
cparata	2:a94816b14e3d	1383	* @brief Latched/pulsed interrupt.[set]
cparata	0:dff8803aace7	1384	*
cparata	2:a94816b14e3d	1385	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1386	* @param val change the values of lir in reg CTRL3
cparata	2:a94816b14e3d	1387	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1388	*
cparata	0:dff8803aace7	1389	*/
cparata	0:dff8803aace7	1390	int32_t lis2dw12_int_notification_set(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1391	lis2dw12_lir_t val)
cparata	0:dff8803aace7	1392	{
cparata	2:a94816b14e3d	1393	lis2dw12_ctrl3_t reg;
cparata	2:a94816b14e3d	1394	int32_t ret;
cparata	0:dff8803aace7	1395
cparata	2:a94816b14e3d	1396	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1397	if (ret == 0) {
cparata	2:a94816b14e3d	1398	reg.lir = (uint8_t) val;
cparata	2:a94816b14e3d	1399	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1400	}
cparata	2:a94816b14e3d	1401	return ret;
cparata	0:dff8803aace7	1402	}
cparata	0:dff8803aace7	1403
cparata	0:dff8803aace7	1404	/**
cparata	2:a94816b14e3d	1405	* @brief Latched/pulsed interrupt.[get]
cparata	0:dff8803aace7	1406	*
cparata	2:a94816b14e3d	1407	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1408	* @param val Get the values of lir in reg CTRL3
cparata	2:a94816b14e3d	1409	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1410	*
cparata	0:dff8803aace7	1411	*/
cparata	0:dff8803aace7	1412	int32_t lis2dw12_int_notification_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1413	lis2dw12_lir_t *val)
cparata	0:dff8803aace7	1414	{
cparata	2:a94816b14e3d	1415	lis2dw12_ctrl3_t reg;
cparata	2:a94816b14e3d	1416	int32_t ret;
cparata	2:a94816b14e3d	1417
cparata	2:a94816b14e3d	1418	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) &reg, 1);
cparata	0:dff8803aace7	1419
cparata	2:a94816b14e3d	1420	switch (reg.lir) {
cparata	2:a94816b14e3d	1421	case LIS2DW12_INT_PULSED:
cparata	2:a94816b14e3d	1422	*val = LIS2DW12_INT_PULSED;
cparata	2:a94816b14e3d	1423	break;
cparata	2:a94816b14e3d	1424	case LIS2DW12_INT_LATCHED:
cparata	2:a94816b14e3d	1425	*val = LIS2DW12_INT_LATCHED;
cparata	2:a94816b14e3d	1426	break;
cparata	2:a94816b14e3d	1427	default:
cparata	2:a94816b14e3d	1428	*val = LIS2DW12_INT_PULSED;
cparata	2:a94816b14e3d	1429	break;
cparata	2:a94816b14e3d	1430	}
cparata	2:a94816b14e3d	1431	return ret;
cparata	0:dff8803aace7	1432	}
cparata	0:dff8803aace7	1433
cparata	0:dff8803aace7	1434	/**
cparata	2:a94816b14e3d	1435	* @brief Push-pull/open drain selection on interrupt pads.[set]
cparata	0:dff8803aace7	1436	*
cparata	2:a94816b14e3d	1437	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1438	* @param val change the values of pp_od in reg CTRL3
cparata	2:a94816b14e3d	1439	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1440	*
cparata	0:dff8803aace7	1441	*/
cparata	0:dff8803aace7	1442	int32_t lis2dw12_pin_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_pp_od_t val)
cparata	0:dff8803aace7	1443	{
cparata	2:a94816b14e3d	1444	lis2dw12_ctrl3_t reg;
cparata	2:a94816b14e3d	1445	int32_t ret;
cparata	0:dff8803aace7	1446
cparata	2:a94816b14e3d	1447	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1448	if (ret == 0) {
cparata	2:a94816b14e3d	1449	reg.pp_od = (uint8_t) val;
cparata	2:a94816b14e3d	1450	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1451	}
cparata	2:a94816b14e3d	1452	return ret;
cparata	0:dff8803aace7	1453	}
cparata	0:dff8803aace7	1454
cparata	0:dff8803aace7	1455	/**
cparata	2:a94816b14e3d	1456	* @brief Push-pull/open drain selection on interrupt pads.[get]
cparata	0:dff8803aace7	1457	*
cparata	2:a94816b14e3d	1458	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1459	* @param val Get the values of pp_od in reg CTRL3
cparata	2:a94816b14e3d	1460	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1461	*
cparata	0:dff8803aace7	1462	*/
cparata	0:dff8803aace7	1463	int32_t lis2dw12_pin_mode_get(lis2dw12_ctx_t ctx, lis2dw12_pp_od_t val)
cparata	0:dff8803aace7	1464	{
cparata	2:a94816b14e3d	1465	lis2dw12_ctrl3_t reg;
cparata	2:a94816b14e3d	1466	int32_t ret;
cparata	2:a94816b14e3d	1467
cparata	2:a94816b14e3d	1468	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) &reg, 1);
cparata	0:dff8803aace7	1469
cparata	2:a94816b14e3d	1470	switch (reg.pp_od) {
cparata	2:a94816b14e3d	1471	case LIS2DW12_PUSH_PULL:
cparata	2:a94816b14e3d	1472	*val = LIS2DW12_PUSH_PULL;
cparata	2:a94816b14e3d	1473	break;
cparata	2:a94816b14e3d	1474	case LIS2DW12_OPEN_DRAIN:
cparata	2:a94816b14e3d	1475	*val = LIS2DW12_OPEN_DRAIN;
cparata	2:a94816b14e3d	1476	break;
cparata	2:a94816b14e3d	1477	default:
cparata	2:a94816b14e3d	1478	*val = LIS2DW12_PUSH_PULL;
cparata	2:a94816b14e3d	1479	break;
cparata	2:a94816b14e3d	1480	}
cparata	2:a94816b14e3d	1481	return ret;
cparata	0:dff8803aace7	1482	}
cparata	0:dff8803aace7	1483
cparata	0:dff8803aace7	1484	/**
cparata	2:a94816b14e3d	1485	* @brief Select the signal that need to route on int1 pad.[set]
cparata	0:dff8803aace7	1486	*
cparata	2:a94816b14e3d	1487	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1488	* @param val register CTRL4_INT1_PAD_CTRL.
cparata	2:a94816b14e3d	1489	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1490	*
cparata	0:dff8803aace7	1491	*/
cparata	0:dff8803aace7	1492	int32_t lis2dw12_pin_int1_route_set(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1493	lis2dw12_ctrl4_int1_pad_ctrl_t *val)
cparata	0:dff8803aace7	1494	{
cparata	2:a94816b14e3d	1495	lis2dw12_ctrl_reg7_t reg;
cparata	2:a94816b14e3d	1496	int32_t ret;
cparata	0:dff8803aace7	1497
cparata	2:a94816b14e3d	1498	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1499	if (ret == 0) {
cparata	2:a94816b14e3d	1500	if ((val->int1_tap \| val->int1_ff \| val->int1_wu \| val->int1_single_tap \|
cparata	2:a94816b14e3d	1501	val->int1_6d) != PROPERTY_DISABLE){
cparata	2:a94816b14e3d	1502	reg.interrupts_enable = PROPERTY_ENABLE;
cparata	2:a94816b14e3d	1503	}
cparata	2:a94816b14e3d	1504	else{
cparata	2:a94816b14e3d	1505	reg.interrupts_enable = PROPERTY_DISABLE;
cparata	2:a94816b14e3d	1506	}
cparata	2:a94816b14e3d	1507
cparata	2:a94816b14e3d	1508	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL4_INT1_PAD_CTRL,
cparata	0:dff8803aace7	1509	(uint8_t*) val, 1);
cparata	2:a94816b14e3d	1510	} if (ret == 0) {
cparata	2:a94816b14e3d	1511	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1512	}
cparata	2:a94816b14e3d	1513	return ret;
cparata	0:dff8803aace7	1514	}
cparata	0:dff8803aace7	1515
cparata	0:dff8803aace7	1516	/**
cparata	2:a94816b14e3d	1517	* @brief Select the signal that need to route on int1 pad.[get]
cparata	0:dff8803aace7	1518	*
cparata	2:a94816b14e3d	1519	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1520	* @param val register CTRL4_INT1_PAD_CTRL.
cparata	2:a94816b14e3d	1521	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1522	*
cparata	0:dff8803aace7	1523	*/
cparata	0:dff8803aace7	1524	int32_t lis2dw12_pin_int1_route_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1525	lis2dw12_ctrl4_int1_pad_ctrl_t *val)
cparata	0:dff8803aace7	1526	{
cparata	2:a94816b14e3d	1527	int32_t ret;
cparata	2:a94816b14e3d	1528	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL4_INT1_PAD_CTRL,
cparata	2:a94816b14e3d	1529	(uint8_t*) val, 1);
cparata	2:a94816b14e3d	1530	return ret;
cparata	0:dff8803aace7	1531	}
cparata	2:a94816b14e3d	1532
cparata	0:dff8803aace7	1533	/**
cparata	2:a94816b14e3d	1534	* @brief Select the signal that need to route on int2 pad.[set]
cparata	0:dff8803aace7	1535	*
cparata	2:a94816b14e3d	1536	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1537	* @param val register CTRL5_INT2_PAD_CTRL.
cparata	2:a94816b14e3d	1538	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1539	*
cparata	0:dff8803aace7	1540	*/
cparata	0:dff8803aace7	1541	int32_t lis2dw12_pin_int2_route_set(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1542	lis2dw12_ctrl5_int2_pad_ctrl_t *val)
cparata	0:dff8803aace7	1543	{
cparata	2:a94816b14e3d	1544	lis2dw12_ctrl_reg7_t reg;
cparata	2:a94816b14e3d	1545	int32_t ret;
cparata	0:dff8803aace7	1546
cparata	2:a94816b14e3d	1547	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1548	if (ret == 0) {
cparata	2:a94816b14e3d	1549	if ((val->int2_sleep_state \| val->int2_sleep_chg ) != PROPERTY_DISABLE) {
cparata	2:a94816b14e3d	1550	reg.interrupts_enable = PROPERTY_ENABLE;
cparata	2:a94816b14e3d	1551	}
cparata	2:a94816b14e3d	1552	else{
cparata	2:a94816b14e3d	1553	reg.interrupts_enable = PROPERTY_DISABLE;
cparata	2:a94816b14e3d	1554	}
cparata	2:a94816b14e3d	1555
cparata	2:a94816b14e3d	1556	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL5_INT2_PAD_CTRL,
cparata	2:a94816b14e3d	1557	(uint8_t*) val, 1);
cparata	0:dff8803aace7	1558	}
cparata	2:a94816b14e3d	1559	if (ret == 0) {
cparata	2:a94816b14e3d	1560	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1561	}
cparata	2:a94816b14e3d	1562
cparata	2:a94816b14e3d	1563	return ret;
cparata	0:dff8803aace7	1564	}
cparata	0:dff8803aace7	1565
cparata	0:dff8803aace7	1566	/**
cparata	2:a94816b14e3d	1567	* @brief Select the signal that need to route on int2 pad.[get]
cparata	0:dff8803aace7	1568	*
cparata	2:a94816b14e3d	1569	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1570	* @param val register CTRL5_INT2_PAD_CTRL
cparata	2:a94816b14e3d	1571	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1572	*
cparata	0:dff8803aace7	1573	*/
cparata	0:dff8803aace7	1574	int32_t lis2dw12_pin_int2_route_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1575	lis2dw12_ctrl5_int2_pad_ctrl_t *val)
cparata	0:dff8803aace7	1576	{
cparata	2:a94816b14e3d	1577	int32_t ret;
cparata	2:a94816b14e3d	1578	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL5_INT2_PAD_CTRL,
cparata	2:a94816b14e3d	1579	(uint8_t*) val, 1);
cparata	2:a94816b14e3d	1580	return ret;
cparata	0:dff8803aace7	1581	}
cparata	0:dff8803aace7	1582	/**
cparata	2:a94816b14e3d	1583	* @brief All interrupt signals become available on INT1 pin.[set]
cparata	0:dff8803aace7	1584	*
cparata	2:a94816b14e3d	1585	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1586	* @param val change the values of int2_on_int1 in reg CTRL_REG7
cparata	2:a94816b14e3d	1587	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1588	*
cparata	0:dff8803aace7	1589	*/
cparata	0:dff8803aace7	1590	int32_t lis2dw12_all_on_int1_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	1591	{
cparata	2:a94816b14e3d	1592	lis2dw12_ctrl_reg7_t reg;
cparata	2:a94816b14e3d	1593	int32_t ret;
cparata	0:dff8803aace7	1594
cparata	2:a94816b14e3d	1595	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1596	if (ret == 0) {
cparata	2:a94816b14e3d	1597	reg.int2_on_int1 = val;
cparata	2:a94816b14e3d	1598	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1599	}
cparata	2:a94816b14e3d	1600	return ret;
cparata	0:dff8803aace7	1601	}
cparata	0:dff8803aace7	1602
cparata	0:dff8803aace7	1603	/**
cparata	2:a94816b14e3d	1604	* @brief All interrupt signals become available on INT1 pin.[get]
cparata	0:dff8803aace7	1605	*
cparata	2:a94816b14e3d	1606	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1607	* @param val change the values of int2_on_int1 in reg CTRL_REG7
cparata	2:a94816b14e3d	1608	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1609	*
cparata	0:dff8803aace7	1610	*/
cparata	0:dff8803aace7	1611	int32_t lis2dw12_all_on_int1_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	1612	{
cparata	2:a94816b14e3d	1613	lis2dw12_ctrl_reg7_t reg;
cparata	2:a94816b14e3d	1614	int32_t ret;
cparata	0:dff8803aace7	1615
cparata	2:a94816b14e3d	1616	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1617	*val = reg.int2_on_int1;
cparata	0:dff8803aace7	1618
cparata	2:a94816b14e3d	1619	return ret;
cparata	0:dff8803aace7	1620	}
cparata	0:dff8803aace7	1621
cparata	0:dff8803aace7	1622	/**
cparata	0:dff8803aace7	1623	* @}
cparata	2:a94816b14e3d	1624	*
cparata	0:dff8803aace7	1625	*/
cparata	0:dff8803aace7	1626
cparata	0:dff8803aace7	1627	/**
cparata	2:a94816b14e3d	1628	* @defgroup LIS2DW12_Wake_Up_Event
cparata	2:a94816b14e3d	1629	* @brief This section groups all the functions that manage the Wake
cparata	2:a94816b14e3d	1630	* Up event generation.
cparata	0:dff8803aace7	1631	* @{
cparata	2:a94816b14e3d	1632	*
cparata	0:dff8803aace7	1633	*/
cparata	0:dff8803aace7	1634
cparata	0:dff8803aace7	1635	/**
cparata	2:a94816b14e3d	1636	* @brief Threshold for wakeup.1 LSB = FS_XL / 64.[set]
cparata	0:dff8803aace7	1637	*
cparata	2:a94816b14e3d	1638	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1639	* @param val change the values of wk_ths in reg WAKE_UP_THS
cparata	2:a94816b14e3d	1640	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1641	*
cparata	0:dff8803aace7	1642	*/
cparata	0:dff8803aace7	1643	int32_t lis2dw12_wkup_threshold_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	1644	{
cparata	2:a94816b14e3d	1645	lis2dw12_wake_up_ths_t reg;
cparata	2:a94816b14e3d	1646	int32_t ret;
cparata	0:dff8803aace7	1647
cparata	2:a94816b14e3d	1648	ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1649	if (ret == 0) {
cparata	2:a94816b14e3d	1650	reg.wk_ths = val;
cparata	2:a94816b14e3d	1651	ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1652	}
cparata	2:a94816b14e3d	1653	return ret;
cparata	0:dff8803aace7	1654	}
cparata	0:dff8803aace7	1655
cparata	0:dff8803aace7	1656	/**
cparata	2:a94816b14e3d	1657	* @brief Threshold for wakeup.1 LSB = FS_XL / 64.[get]
cparata	0:dff8803aace7	1658	*
cparata	2:a94816b14e3d	1659	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1660	* @param val change the values of wk_ths in reg WAKE_UP_THS
cparata	2:a94816b14e3d	1661	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1662	*
cparata	0:dff8803aace7	1663	*/
cparata	0:dff8803aace7	1664	int32_t lis2dw12_wkup_threshold_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	1665	{
cparata	2:a94816b14e3d	1666	lis2dw12_wake_up_ths_t reg;
cparata	2:a94816b14e3d	1667	int32_t ret;
cparata	0:dff8803aace7	1668
cparata	2:a94816b14e3d	1669	ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1670	*val = reg.wk_ths;
cparata	0:dff8803aace7	1671
cparata	2:a94816b14e3d	1672	return ret;
cparata	0:dff8803aace7	1673	}
cparata	0:dff8803aace7	1674
cparata	0:dff8803aace7	1675	/**
cparata	2:a94816b14e3d	1676	* @brief Wake up duration event.1LSb = 1 / ODR.[set]
cparata	0:dff8803aace7	1677	*
cparata	2:a94816b14e3d	1678	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1679	* @param val change the values of wake_dur in reg WAKE_UP_DUR
cparata	2:a94816b14e3d	1680	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1681	*
cparata	0:dff8803aace7	1682	*/
cparata	0:dff8803aace7	1683	int32_t lis2dw12_wkup_dur_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	1684	{
cparata	2:a94816b14e3d	1685	lis2dw12_wake_up_dur_t reg;
cparata	2:a94816b14e3d	1686	int32_t ret;
cparata	0:dff8803aace7	1687
cparata	2:a94816b14e3d	1688	ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1689	if (ret == 0) {
cparata	2:a94816b14e3d	1690	reg.wake_dur = val;
cparata	2:a94816b14e3d	1691	ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1692	}
cparata	2:a94816b14e3d	1693	return ret;
cparata	0:dff8803aace7	1694	}
cparata	0:dff8803aace7	1695
cparata	0:dff8803aace7	1696	/**
cparata	2:a94816b14e3d	1697	* @brief Wake up duration event.1LSb = 1 / ODR.[get]
cparata	0:dff8803aace7	1698	*
cparata	2:a94816b14e3d	1699	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1700	* @param val change the values of wake_dur in reg WAKE_UP_DUR
cparata	2:a94816b14e3d	1701	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1702	*
cparata	0:dff8803aace7	1703	*/
cparata	0:dff8803aace7	1704	int32_t lis2dw12_wkup_dur_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	1705	{
cparata	2:a94816b14e3d	1706	lis2dw12_wake_up_dur_t reg;
cparata	2:a94816b14e3d	1707	int32_t ret;
cparata	0:dff8803aace7	1708
cparata	2:a94816b14e3d	1709	ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1710	*val = reg.wake_dur;
cparata	0:dff8803aace7	1711
cparata	2:a94816b14e3d	1712	return ret;
cparata	0:dff8803aace7	1713	}
cparata	0:dff8803aace7	1714
cparata	0:dff8803aace7	1715	/**
cparata	2:a94816b14e3d	1716	* @brief Data sent to wake-up interrupt function.[set]
cparata	0:dff8803aace7	1717	*
cparata	2:a94816b14e3d	1718	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1719	* @param val change the values of usr_off_on_wu in reg CTRL_REG7
cparata	2:a94816b14e3d	1720	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1721	*
cparata	0:dff8803aace7	1722	*/
cparata	0:dff8803aace7	1723	int32_t lis2dw12_wkup_feed_data_set(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1724	lis2dw12_usr_off_on_wu_t val)
cparata	0:dff8803aace7	1725	{
cparata	2:a94816b14e3d	1726	lis2dw12_ctrl_reg7_t reg;
cparata	2:a94816b14e3d	1727	int32_t ret;
cparata	0:dff8803aace7	1728
cparata	2:a94816b14e3d	1729	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1730	if (ret == 0) {
cparata	2:a94816b14e3d	1731	reg.usr_off_on_wu = (uint8_t) val;
cparata	2:a94816b14e3d	1732	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1733	}
cparata	2:a94816b14e3d	1734	return ret;
cparata	0:dff8803aace7	1735	}
cparata	0:dff8803aace7	1736
cparata	0:dff8803aace7	1737	/**
cparata	2:a94816b14e3d	1738	* @brief Data sent to wake-up interrupt function.[get]
cparata	0:dff8803aace7	1739	*
cparata	2:a94816b14e3d	1740	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1741	* @param val Get the values of usr_off_on_wu in reg CTRL_REG7
cparata	2:a94816b14e3d	1742	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1743	*
cparata	0:dff8803aace7	1744	*/
cparata	0:dff8803aace7	1745	int32_t lis2dw12_wkup_feed_data_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1746	lis2dw12_usr_off_on_wu_t *val)
cparata	0:dff8803aace7	1747	{
cparata	2:a94816b14e3d	1748	lis2dw12_ctrl_reg7_t reg;
cparata	2:a94816b14e3d	1749	int32_t ret;
cparata	2:a94816b14e3d	1750
cparata	2:a94816b14e3d	1751	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:dff8803aace7	1752
cparata	2:a94816b14e3d	1753	switch (reg.usr_off_on_wu) {
cparata	2:a94816b14e3d	1754	case LIS2DW12_HP_FEED:
cparata	2:a94816b14e3d	1755	*val = LIS2DW12_HP_FEED;
cparata	2:a94816b14e3d	1756	break;
cparata	2:a94816b14e3d	1757	case LIS2DW12_USER_OFFSET_FEED:
cparata	2:a94816b14e3d	1758	*val = LIS2DW12_USER_OFFSET_FEED;
cparata	2:a94816b14e3d	1759	break;
cparata	2:a94816b14e3d	1760	default:
cparata	2:a94816b14e3d	1761	*val = LIS2DW12_HP_FEED;
cparata	2:a94816b14e3d	1762	break;
cparata	2:a94816b14e3d	1763	}
cparata	2:a94816b14e3d	1764	return ret;
cparata	0:dff8803aace7	1765	}
cparata	0:dff8803aace7	1766
cparata	0:dff8803aace7	1767	/**
cparata	0:dff8803aace7	1768	* @}
cparata	2:a94816b14e3d	1769	*
cparata	0:dff8803aace7	1770	*/
cparata	0:dff8803aace7	1771
cparata	0:dff8803aace7	1772	/**
cparata	2:a94816b14e3d	1773	* @defgroup LIS2DW12_Activity/Inactivity_Detection
cparata	2:a94816b14e3d	1774	* @brief This section groups all the functions concerning
cparata	2:a94816b14e3d	1775	* activity/inactivity detection.
cparata	0:dff8803aace7	1776	* @{
cparata	2:a94816b14e3d	1777	*
cparata	0:dff8803aace7	1778	*/
cparata	0:dff8803aace7	1779
cparata	0:dff8803aace7	1780	/**
cparata	2:a94816b14e3d	1781	* @brief Config activity / inactivity or
cparata	2:a94816b14e3d	1782	* stationary / motion detection.[set]
cparata	0:dff8803aace7	1783	*
cparata	2:a94816b14e3d	1784	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1785	* @param val change the values of sleep_on / stationary in
cparata	2:a94816b14e3d	1786	* reg WAKE_UP_THS / WAKE_UP_DUR
cparata	2:a94816b14e3d	1787	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1788	*
cparata	0:dff8803aace7	1789	*/
cparata	0:dff8803aace7	1790	int32_t lis2dw12_act_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_sleep_on_t val)
cparata	0:dff8803aace7	1791	{
cparata	2:a94816b14e3d	1792	lis2dw12_wake_up_ths_t wake_up_ths;
cparata	2:a94816b14e3d	1793	lis2dw12_wake_up_dur_t wake_up_dur;
cparata	2:a94816b14e3d	1794	int32_t ret;
cparata	2:a94816b14e3d	1795
cparata	2:a94816b14e3d	1796	ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 1);
cparata	2:a94816b14e3d	1797	if (ret == 0) {
cparata	2:a94816b14e3d	1798	ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
cparata	2:a94816b14e3d	1799	}
cparata	2:a94816b14e3d	1800	if (ret == 0) {
cparata	2:a94816b14e3d	1801	wake_up_ths.sleep_on = (uint8_t) val & 0x01U;
cparata	2:a94816b14e3d	1802	ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 1);
cparata	2:a94816b14e3d	1803	}
cparata	2:a94816b14e3d	1804	if (ret == 0) {
cparata	2:a94816b14e3d	1805	wake_up_dur.stationary = ((uint8_t)val & 0x02U) >> 1;
cparata	2:a94816b14e3d	1806	ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
cparata	2:a94816b14e3d	1807	}
cparata	2:a94816b14e3d	1808
cparata	2:a94816b14e3d	1809	return ret;
cparata	0:dff8803aace7	1810	}
cparata	0:dff8803aace7	1811
cparata	0:dff8803aace7	1812	/**
cparata	2:a94816b14e3d	1813	* @brief Config activity / inactivity or
cparata	2:a94816b14e3d	1814	* stationary / motion detection. [get]
cparata	0:dff8803aace7	1815	*
cparata	2:a94816b14e3d	1816	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1817	* @param val Get the values of sleep_on in reg WAKE_UP_THS
cparata	2:a94816b14e3d	1818	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1819	*
cparata	0:dff8803aace7	1820	*/
cparata	0:dff8803aace7	1821	int32_t lis2dw12_act_mode_get(lis2dw12_ctx_t ctx, lis2dw12_sleep_on_t val)
cparata	0:dff8803aace7	1822	{
cparata	2:a94816b14e3d	1823	lis2dw12_wake_up_ths_t wake_up_ths;
cparata	2:a94816b14e3d	1824	lis2dw12_wake_up_dur_t wake_up_dur;;
cparata	2:a94816b14e3d	1825	int32_t ret;
cparata	2:a94816b14e3d	1826
cparata	2:a94816b14e3d	1827	ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 1);
cparata	2:a94816b14e3d	1828	if (ret == 0) {
cparata	2:a94816b14e3d	1829	ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
cparata	0:dff8803aace7	1830
cparata	2:a94816b14e3d	1831	switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on){
cparata	2:a94816b14e3d	1832	case LIS2DW12_NO_DETECTION:
cparata	2:a94816b14e3d	1833	*val = LIS2DW12_NO_DETECTION;
cparata	2:a94816b14e3d	1834	break;
cparata	2:a94816b14e3d	1835	case LIS2DW12_DETECT_ACT_INACT:
cparata	2:a94816b14e3d	1836	*val = LIS2DW12_DETECT_ACT_INACT;
cparata	2:a94816b14e3d	1837	break;
cparata	2:a94816b14e3d	1838	case LIS2DW12_DETECT_STAT_MOTION:
cparata	2:a94816b14e3d	1839	*val = LIS2DW12_DETECT_STAT_MOTION;
cparata	2:a94816b14e3d	1840	break;
cparata	2:a94816b14e3d	1841	default:
cparata	2:a94816b14e3d	1842	*val = LIS2DW12_NO_DETECTION;
cparata	2:a94816b14e3d	1843	break;
cparata	2:a94816b14e3d	1844	}
cparata	2:a94816b14e3d	1845	}
cparata	2:a94816b14e3d	1846	return ret;
cparata	0:dff8803aace7	1847	}
cparata	0:dff8803aace7	1848
cparata	0:dff8803aace7	1849	/**
cparata	2:a94816b14e3d	1850	* @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set]
cparata	0:dff8803aace7	1851	*
cparata	2:a94816b14e3d	1852	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1853	* @param val change the values of sleep_dur in reg WAKE_UP_DUR
cparata	2:a94816b14e3d	1854	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1855	*
cparata	0:dff8803aace7	1856	*/
cparata	0:dff8803aace7	1857	int32_t lis2dw12_act_sleep_dur_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	1858	{
cparata	2:a94816b14e3d	1859	lis2dw12_wake_up_dur_t reg;
cparata	2:a94816b14e3d	1860	int32_t ret;
cparata	0:dff8803aace7	1861
cparata	2:a94816b14e3d	1862	ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1863	if (ret == 0) {
cparata	2:a94816b14e3d	1864	reg.sleep_dur = val;
cparata	2:a94816b14e3d	1865	ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1866	}
cparata	2:a94816b14e3d	1867	return ret;
cparata	0:dff8803aace7	1868	}
cparata	0:dff8803aace7	1869
cparata	0:dff8803aace7	1870	/**
cparata	2:a94816b14e3d	1871	* @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[get]
cparata	0:dff8803aace7	1872	*
cparata	2:a94816b14e3d	1873	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1874	* @param val change the values of sleep_dur in reg WAKE_UP_DUR
cparata	2:a94816b14e3d	1875	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1876	*
cparata	0:dff8803aace7	1877	*/
cparata	0:dff8803aace7	1878	int32_t lis2dw12_act_sleep_dur_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	1879	{
cparata	2:a94816b14e3d	1880	lis2dw12_wake_up_dur_t reg;
cparata	2:a94816b14e3d	1881	int32_t ret;
cparata	0:dff8803aace7	1882
cparata	2:a94816b14e3d	1883	ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1884	*val = reg.sleep_dur;
cparata	0:dff8803aace7	1885
cparata	2:a94816b14e3d	1886	return ret;
cparata	0:dff8803aace7	1887	}
cparata	0:dff8803aace7	1888
cparata	0:dff8803aace7	1889	/**
cparata	0:dff8803aace7	1890	* @}
cparata	2:a94816b14e3d	1891	*
cparata	0:dff8803aace7	1892	*/
cparata	0:dff8803aace7	1893
cparata	0:dff8803aace7	1894	/**
cparata	2:a94816b14e3d	1895	* @defgroup LIS2DW12_Tap_Generator
cparata	2:a94816b14e3d	1896	* @brief This section groups all the functions that manage the tap
cparata	2:a94816b14e3d	1897	* and double tap event generation.
cparata	0:dff8803aace7	1898	* @{
cparata	2:a94816b14e3d	1899	*
cparata	0:dff8803aace7	1900	*/
cparata	0:dff8803aace7	1901
cparata	0:dff8803aace7	1902	/**
cparata	2:a94816b14e3d	1903	* @brief Threshold for tap recognition.[set]
cparata	0:dff8803aace7	1904	*
cparata	2:a94816b14e3d	1905	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1906	* @param val change the values of tap_thsx in reg TAP_THS_X
cparata	2:a94816b14e3d	1907	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1908	*
cparata	0:dff8803aace7	1909	*/
cparata	0:dff8803aace7	1910	int32_t lis2dw12_tap_threshold_x_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	1911	{
cparata	2:a94816b14e3d	1912	lis2dw12_tap_ths_x_t reg;
cparata	2:a94816b14e3d	1913	int32_t ret;
cparata	0:dff8803aace7	1914
cparata	2:a94816b14e3d	1915	ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1916	if (ret == 0) {
cparata	2:a94816b14e3d	1917	reg.tap_thsx = val;
cparata	2:a94816b14e3d	1918	ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1919	}
cparata	2:a94816b14e3d	1920	return ret;
cparata	0:dff8803aace7	1921	}
cparata	0:dff8803aace7	1922
cparata	0:dff8803aace7	1923	/**
cparata	2:a94816b14e3d	1924	* @brief Threshold for tap recognition.[get]
cparata	0:dff8803aace7	1925	*
cparata	2:a94816b14e3d	1926	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1927	* @param val change the values of tap_thsx in reg TAP_THS_X
cparata	2:a94816b14e3d	1928	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1929	*
cparata	0:dff8803aace7	1930	*/
cparata	0:dff8803aace7	1931	int32_t lis2dw12_tap_threshold_x_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	1932	{
cparata	2:a94816b14e3d	1933	lis2dw12_tap_ths_x_t reg;
cparata	2:a94816b14e3d	1934	int32_t ret;
cparata	0:dff8803aace7	1935
cparata	2:a94816b14e3d	1936	ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1937	*val = reg.tap_thsx;
cparata	0:dff8803aace7	1938
cparata	2:a94816b14e3d	1939	return ret;
cparata	0:dff8803aace7	1940	}
cparata	0:dff8803aace7	1941
cparata	0:dff8803aace7	1942	/**
cparata	2:a94816b14e3d	1943	* @brief Threshold for tap recognition.[set]
cparata	0:dff8803aace7	1944	*
cparata	2:a94816b14e3d	1945	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1946	* @param val change the values of tap_thsy in reg TAP_THS_Y
cparata	2:a94816b14e3d	1947	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1948	*
cparata	0:dff8803aace7	1949	*/
cparata	0:dff8803aace7	1950	int32_t lis2dw12_tap_threshold_y_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	1951	{
cparata	2:a94816b14e3d	1952	lis2dw12_tap_ths_y_t reg;
cparata	2:a94816b14e3d	1953	int32_t ret;
cparata	0:dff8803aace7	1954
cparata	2:a94816b14e3d	1955	ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1956	if (ret == 0) {
cparata	2:a94816b14e3d	1957	reg.tap_thsy = val;
cparata	2:a94816b14e3d	1958	ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Y,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1959	}
cparata	2:a94816b14e3d	1960	return ret;
cparata	0:dff8803aace7	1961	}
cparata	0:dff8803aace7	1962
cparata	0:dff8803aace7	1963	/**
cparata	2:a94816b14e3d	1964	* @brief Threshold for tap recognition.[get]
cparata	0:dff8803aace7	1965	*
cparata	2:a94816b14e3d	1966	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1967	* @param val change the values of tap_thsy in reg TAP_THS_Y
cparata	2:a94816b14e3d	1968	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1969	*
cparata	0:dff8803aace7	1970	*/
cparata	0:dff8803aace7	1971	int32_t lis2dw12_tap_threshold_y_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	1972	{
cparata	2:a94816b14e3d	1973	lis2dw12_tap_ths_y_t reg;
cparata	2:a94816b14e3d	1974	int32_t ret;
cparata	0:dff8803aace7	1975
cparata	2:a94816b14e3d	1976	ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1977	*val = reg.tap_thsy;
cparata	0:dff8803aace7	1978
cparata	2:a94816b14e3d	1979	return ret;
cparata	0:dff8803aace7	1980	}
cparata	0:dff8803aace7	1981
cparata	0:dff8803aace7	1982	/**
cparata	2:a94816b14e3d	1983	* @brief Selection of axis priority for TAP detection.[set]
cparata	0:dff8803aace7	1984	*
cparata	2:a94816b14e3d	1985	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	1986	* @param val change the values of tap_prior in reg TAP_THS_Y
cparata	2:a94816b14e3d	1987	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	1988	*
cparata	0:dff8803aace7	1989	*/
cparata	0:dff8803aace7	1990	int32_t lis2dw12_tap_axis_priority_set(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1991	lis2dw12_tap_prior_t val)
cparata	0:dff8803aace7	1992	{
cparata	2:a94816b14e3d	1993	lis2dw12_tap_ths_y_t reg;
cparata	2:a94816b14e3d	1994	int32_t ret;
cparata	0:dff8803aace7	1995
cparata	2:a94816b14e3d	1996	ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	1997	if (ret == 0) {
cparata	2:a94816b14e3d	1998	reg.tap_prior = (uint8_t) val;
cparata	2:a94816b14e3d	1999	ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Y,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2000	}
cparata	2:a94816b14e3d	2001	return ret;
cparata	0:dff8803aace7	2002	}
cparata	0:dff8803aace7	2003
cparata	0:dff8803aace7	2004	/**
cparata	2:a94816b14e3d	2005	* @brief Selection of axis priority for TAP detection.[get]
cparata	0:dff8803aace7	2006	*
cparata	2:a94816b14e3d	2007	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2008	* @param val Get the values of tap_prior in reg TAP_THS_Y
cparata	2:a94816b14e3d	2009	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2010	*
cparata	0:dff8803aace7	2011	*/
cparata	0:dff8803aace7	2012	int32_t lis2dw12_tap_axis_priority_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	2013	lis2dw12_tap_prior_t *val)
cparata	0:dff8803aace7	2014	{
cparata	2:a94816b14e3d	2015	lis2dw12_tap_ths_y_t reg;
cparata	2:a94816b14e3d	2016	int32_t ret;
cparata	2:a94816b14e3d	2017
cparata	2:a94816b14e3d	2018	ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y,(uint8_t*) &reg, 1);
cparata	0:dff8803aace7	2019
cparata	2:a94816b14e3d	2020	switch (reg.tap_prior) {
cparata	2:a94816b14e3d	2021	case LIS2DW12_XYZ:
cparata	2:a94816b14e3d	2022	*val = LIS2DW12_XYZ;
cparata	2:a94816b14e3d	2023	break;
cparata	2:a94816b14e3d	2024	case LIS2DW12_YXZ:
cparata	2:a94816b14e3d	2025	*val = LIS2DW12_YXZ;
cparata	2:a94816b14e3d	2026	break;
cparata	2:a94816b14e3d	2027	case LIS2DW12_XZY:
cparata	2:a94816b14e3d	2028	*val = LIS2DW12_XZY;
cparata	2:a94816b14e3d	2029	break;
cparata	2:a94816b14e3d	2030	case LIS2DW12_ZYX:
cparata	2:a94816b14e3d	2031	*val = LIS2DW12_ZYX;
cparata	2:a94816b14e3d	2032	break;
cparata	2:a94816b14e3d	2033	case LIS2DW12_YZX:
cparata	2:a94816b14e3d	2034	*val = LIS2DW12_YZX;
cparata	2:a94816b14e3d	2035	break;
cparata	2:a94816b14e3d	2036	case LIS2DW12_ZXY:
cparata	2:a94816b14e3d	2037	*val = LIS2DW12_ZXY;
cparata	2:a94816b14e3d	2038	break;
cparata	2:a94816b14e3d	2039	default:
cparata	2:a94816b14e3d	2040	*val = LIS2DW12_XYZ;
cparata	2:a94816b14e3d	2041	break;
cparata	2:a94816b14e3d	2042	}
cparata	2:a94816b14e3d	2043	return ret;
cparata	0:dff8803aace7	2044	}
cparata	0:dff8803aace7	2045
cparata	0:dff8803aace7	2046	/**
cparata	2:a94816b14e3d	2047	* @brief Threshold for tap recognition.[set]
cparata	0:dff8803aace7	2048	*
cparata	2:a94816b14e3d	2049	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2050	* @param val change the values of tap_thsz in reg TAP_THS_Z
cparata	2:a94816b14e3d	2051	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2052	*
cparata	0:dff8803aace7	2053	*/
cparata	0:dff8803aace7	2054	int32_t lis2dw12_tap_threshold_z_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	2055	{
cparata	2:a94816b14e3d	2056	lis2dw12_tap_ths_z_t reg;
cparata	2:a94816b14e3d	2057	int32_t ret;
cparata	0:dff8803aace7	2058
cparata	2:a94816b14e3d	2059	ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2060	if (ret == 0) {
cparata	2:a94816b14e3d	2061	reg.tap_thsz = val;
cparata	2:a94816b14e3d	2062	ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2063	}
cparata	0:dff8803aace7	2064
cparata	2:a94816b14e3d	2065	return ret;
cparata	0:dff8803aace7	2066	}
cparata	0:dff8803aace7	2067
cparata	0:dff8803aace7	2068	/**
cparata	2:a94816b14e3d	2069	* @brief Threshold for tap recognition.[get]
cparata	0:dff8803aace7	2070	*
cparata	2:a94816b14e3d	2071	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2072	* @param val change the values of tap_thsz in reg TAP_THS_Z
cparata	2:a94816b14e3d	2073	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2074	*
cparata	0:dff8803aace7	2075	*/
cparata	0:dff8803aace7	2076	int32_t lis2dw12_tap_threshold_z_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	2077	{
cparata	2:a94816b14e3d	2078	lis2dw12_tap_ths_z_t reg;
cparata	2:a94816b14e3d	2079	int32_t ret;
cparata	0:dff8803aace7	2080
cparata	2:a94816b14e3d	2081	ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2082	*val = reg.tap_thsz;
cparata	0:dff8803aace7	2083
cparata	2:a94816b14e3d	2084	return ret;
cparata	0:dff8803aace7	2085	}
cparata	0:dff8803aace7	2086
cparata	0:dff8803aace7	2087	/**
cparata	2:a94816b14e3d	2088	* @brief Enable Z direction in tap recognition.[set]
cparata	0:dff8803aace7	2089	*
cparata	2:a94816b14e3d	2090	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2091	* @param val change the values of tap_z_en in reg TAP_THS_Z
cparata	2:a94816b14e3d	2092	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2093	*
cparata	0:dff8803aace7	2094	*/
cparata	0:dff8803aace7	2095	int32_t lis2dw12_tap_detection_on_z_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	2096	{
cparata	2:a94816b14e3d	2097	lis2dw12_tap_ths_z_t reg;
cparata	2:a94816b14e3d	2098	int32_t ret;
cparata	0:dff8803aace7	2099
cparata	2:a94816b14e3d	2100	ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2101	if (ret == 0) {
cparata	2:a94816b14e3d	2102	reg.tap_z_en = val;
cparata	2:a94816b14e3d	2103	ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2104	}
cparata	2:a94816b14e3d	2105	return ret;
cparata	0:dff8803aace7	2106	}
cparata	0:dff8803aace7	2107
cparata	0:dff8803aace7	2108	/**
cparata	2:a94816b14e3d	2109	* @brief Enable Z direction in tap recognition.[get]
cparata	0:dff8803aace7	2110	*
cparata	2:a94816b14e3d	2111	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2112	* @param val change the values of tap_z_en in reg TAP_THS_Z
cparata	2:a94816b14e3d	2113	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2114	*
cparata	0:dff8803aace7	2115	*/
cparata	0:dff8803aace7	2116	int32_t lis2dw12_tap_detection_on_z_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	2117	{
cparata	2:a94816b14e3d	2118	lis2dw12_tap_ths_z_t reg;
cparata	2:a94816b14e3d	2119	int32_t ret;
cparata	0:dff8803aace7	2120
cparata	2:a94816b14e3d	2121	ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2122	*val = reg.tap_z_en;
cparata	0:dff8803aace7	2123
cparata	2:a94816b14e3d	2124	return ret;
cparata	0:dff8803aace7	2125	}
cparata	0:dff8803aace7	2126
cparata	0:dff8803aace7	2127	/**
cparata	2:a94816b14e3d	2128	* @brief Enable Y direction in tap recognition.[set]
cparata	0:dff8803aace7	2129	*
cparata	2:a94816b14e3d	2130	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2131	* @param val change the values of tap_y_en in reg TAP_THS_Z
cparata	2:a94816b14e3d	2132	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2133	*
cparata	0:dff8803aace7	2134	*/
cparata	0:dff8803aace7	2135	int32_t lis2dw12_tap_detection_on_y_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	2136	{
cparata	2:a94816b14e3d	2137	lis2dw12_tap_ths_z_t reg;
cparata	2:a94816b14e3d	2138	int32_t ret;
cparata	0:dff8803aace7	2139
cparata	2:a94816b14e3d	2140	ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2141	if (ret == 0) {
cparata	2:a94816b14e3d	2142	reg.tap_y_en = val;
cparata	2:a94816b14e3d	2143	ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2144	}
cparata	2:a94816b14e3d	2145	return ret;
cparata	0:dff8803aace7	2146	}
cparata	0:dff8803aace7	2147
cparata	0:dff8803aace7	2148	/**
cparata	2:a94816b14e3d	2149	* @brief Enable Y direction in tap recognition.[get]
cparata	0:dff8803aace7	2150	*
cparata	2:a94816b14e3d	2151	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2152	* @param val change the values of tap_y_en in reg TAP_THS_Z
cparata	2:a94816b14e3d	2153	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2154	*
cparata	0:dff8803aace7	2155	*/
cparata	0:dff8803aace7	2156	int32_t lis2dw12_tap_detection_on_y_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	2157	{
cparata	2:a94816b14e3d	2158	lis2dw12_tap_ths_z_t reg;
cparata	2:a94816b14e3d	2159	int32_t ret;
cparata	0:dff8803aace7	2160
cparata	2:a94816b14e3d	2161	ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2162	*val = reg.tap_y_en;
cparata	0:dff8803aace7	2163
cparata	2:a94816b14e3d	2164	return ret;
cparata	0:dff8803aace7	2165	}
cparata	0:dff8803aace7	2166
cparata	0:dff8803aace7	2167	/**
cparata	2:a94816b14e3d	2168	* @brief Enable X direction in tap recognition.[set]
cparata	0:dff8803aace7	2169	*
cparata	2:a94816b14e3d	2170	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2171	* @param val change the values of tap_x_en in reg TAP_THS_Z
cparata	2:a94816b14e3d	2172	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2173	*
cparata	0:dff8803aace7	2174	*/
cparata	0:dff8803aace7	2175	int32_t lis2dw12_tap_detection_on_x_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	2176	{
cparata	2:a94816b14e3d	2177	lis2dw12_tap_ths_z_t reg;
cparata	2:a94816b14e3d	2178	int32_t ret;
cparata	0:dff8803aace7	2179
cparata	2:a94816b14e3d	2180	ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2181	if (ret == 0) {
cparata	2:a94816b14e3d	2182	reg.tap_x_en = val;
cparata	2:a94816b14e3d	2183	ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2184	}
cparata	2:a94816b14e3d	2185	return ret;
cparata	0:dff8803aace7	2186	}
cparata	0:dff8803aace7	2187
cparata	0:dff8803aace7	2188	/**
cparata	2:a94816b14e3d	2189	* @brief Enable X direction in tap recognition.[get]
cparata	0:dff8803aace7	2190	*
cparata	2:a94816b14e3d	2191	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2192	* @param val change the values of tap_x_en in reg TAP_THS_Z
cparata	2:a94816b14e3d	2193	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2194	*
cparata	0:dff8803aace7	2195	*/
cparata	0:dff8803aace7	2196	int32_t lis2dw12_tap_detection_on_x_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	2197	{
cparata	2:a94816b14e3d	2198	lis2dw12_tap_ths_z_t reg;
cparata	2:a94816b14e3d	2199	int32_t ret;
cparata	0:dff8803aace7	2200
cparata	2:a94816b14e3d	2201	ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2202	*val = reg.tap_x_en;
cparata	0:dff8803aace7	2203
cparata	2:a94816b14e3d	2204	return ret;
cparata	0:dff8803aace7	2205	}
cparata	0:dff8803aace7	2206
cparata	0:dff8803aace7	2207	/**
cparata	2:a94816b14e3d	2208	* @brief Maximum duration is the maximum time of an overthreshold signal
cparata	2:a94816b14e3d	2209	* detection to be recognized as a tap event. The default value
cparata	2:a94816b14e3d	2210	* of these bits is 00b which corresponds to 4*ODR_XL time.
cparata	2:a94816b14e3d	2211	* If the SHOCK[1:0] bits are set to a different value, 1LSB
cparata	2:a94816b14e3d	2212	* corresponds to 8*ODR_XL time.[set]
cparata	0:dff8803aace7	2213	*
cparata	2:a94816b14e3d	2214	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2215	* @param val change the values of shock in reg INT_DUR
cparata	2:a94816b14e3d	2216	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2217	*
cparata	0:dff8803aace7	2218	*/
cparata	0:dff8803aace7	2219	int32_t lis2dw12_tap_shock_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	2220	{
cparata	2:a94816b14e3d	2221	lis2dw12_int_dur_t reg;
cparata	2:a94816b14e3d	2222	int32_t ret;
cparata	0:dff8803aace7	2223
cparata	2:a94816b14e3d	2224	ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2225	if (ret == 0) {
cparata	2:a94816b14e3d	2226	reg.shock = val;
cparata	2:a94816b14e3d	2227	ret = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2228	}
cparata	0:dff8803aace7	2229
cparata	2:a94816b14e3d	2230	return ret;
cparata	0:dff8803aace7	2231	}
cparata	0:dff8803aace7	2232
cparata	0:dff8803aace7	2233	/**
cparata	2:a94816b14e3d	2234	* @brief Maximum duration is the maximum time of an overthreshold signal
cparata	2:a94816b14e3d	2235	* detection to be recognized as a tap event. The default value
cparata	2:a94816b14e3d	2236	* of these bits is 00b which corresponds to 4*ODR_XL time.
cparata	2:a94816b14e3d	2237	* If the SHOCK[1:0] bits are set to a different value, 1LSB
cparata	2:a94816b14e3d	2238	* corresponds to 8*ODR_XL time.[get]
cparata	0:dff8803aace7	2239	*
cparata	2:a94816b14e3d	2240	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2241	* @param val change the values of shock in reg INT_DUR
cparata	2:a94816b14e3d	2242	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2243	*
cparata	0:dff8803aace7	2244	*/
cparata	0:dff8803aace7	2245	int32_t lis2dw12_tap_shock_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	2246	{
cparata	2:a94816b14e3d	2247	lis2dw12_int_dur_t reg;
cparata	2:a94816b14e3d	2248	int32_t ret;
cparata	0:dff8803aace7	2249
cparata	2:a94816b14e3d	2250	ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2251	*val = reg.shock;
cparata	0:dff8803aace7	2252
cparata	2:a94816b14e3d	2253	return ret;
cparata	0:dff8803aace7	2254	}
cparata	0:dff8803aace7	2255
cparata	0:dff8803aace7	2256	/**
cparata	2:a94816b14e3d	2257	* @brief Quiet time is the time after the first detected tap in which
cparata	2:a94816b14e3d	2258	* there must not be any overthreshold event.
cparata	2:a94816b14e3d	2259	* The default value of these bits is 00b which corresponds
cparata	2:a94816b14e3d	2260	* to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
cparata	2:a94816b14e3d	2261	* value, 1LSB corresponds to 4*ODR_XL time.[set]
cparata	0:dff8803aace7	2262	*
cparata	2:a94816b14e3d	2263	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2264	* @param val change the values of quiet in reg INT_DUR
cparata	2:a94816b14e3d	2265	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2266	*
cparata	0:dff8803aace7	2267	*/
cparata	0:dff8803aace7	2268	int32_t lis2dw12_tap_quiet_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	2269	{
cparata	2:a94816b14e3d	2270	lis2dw12_int_dur_t reg;
cparata	2:a94816b14e3d	2271	int32_t ret;
cparata	0:dff8803aace7	2272
cparata	2:a94816b14e3d	2273	ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2274	if (ret == 0) {
cparata	2:a94816b14e3d	2275	reg.quiet = val;
cparata	2:a94816b14e3d	2276	ret = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2277	}
cparata	2:a94816b14e3d	2278	return ret;
cparata	0:dff8803aace7	2279	}
cparata	0:dff8803aace7	2280
cparata	0:dff8803aace7	2281	/**
cparata	2:a94816b14e3d	2282	* @brief Quiet time is the time after the first detected tap in which
cparata	2:a94816b14e3d	2283	* there must not be any overthreshold event.
cparata	2:a94816b14e3d	2284	* The default value of these bits is 00b which corresponds
cparata	2:a94816b14e3d	2285	* to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
cparata	2:a94816b14e3d	2286	* value, 1LSB corresponds to 4*ODR_XL time.[get]
cparata	0:dff8803aace7	2287	*
cparata	2:a94816b14e3d	2288	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2289	* @param val change the values of quiet in reg INT_DUR
cparata	2:a94816b14e3d	2290	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2291	*
cparata	0:dff8803aace7	2292	*/
cparata	0:dff8803aace7	2293	int32_t lis2dw12_tap_quiet_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	2294	{
cparata	2:a94816b14e3d	2295	lis2dw12_int_dur_t reg;
cparata	2:a94816b14e3d	2296	int32_t ret;
cparata	0:dff8803aace7	2297
cparata	2:a94816b14e3d	2298	ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2299	*val = reg.quiet;
cparata	0:dff8803aace7	2300
cparata	2:a94816b14e3d	2301	return ret;
cparata	0:dff8803aace7	2302	}
cparata	0:dff8803aace7	2303
cparata	0:dff8803aace7	2304	/**
cparata	2:a94816b14e3d	2305	* @brief When double tap recognition is enabled, this register expresses
cparata	2:a94816b14e3d	2306	* the maximum time between two consecutive detected taps to
cparata	2:a94816b14e3d	2307	* determine a double tap event.
cparata	2:a94816b14e3d	2308	* The default value of these bits is 0000b which corresponds
cparata	2:a94816b14e3d	2309	* to 16*ODR_XL time. If the DUR[3:0] bits are set to a different
cparata	2:a94816b14e3d	2310	* value, 1LSB corresponds to 32*ODR_XL time.[set]
cparata	0:dff8803aace7	2311	*
cparata	2:a94816b14e3d	2312	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2313	* @param val change the values of latency in reg INT_DUR
cparata	2:a94816b14e3d	2314	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2315	*
cparata	0:dff8803aace7	2316	*/
cparata	0:dff8803aace7	2317	int32_t lis2dw12_tap_dur_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	2318	{
cparata	2:a94816b14e3d	2319	lis2dw12_int_dur_t reg;
cparata	2:a94816b14e3d	2320	int32_t ret;
cparata	0:dff8803aace7	2321
cparata	2:a94816b14e3d	2322	ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2323	if (ret == 0) {
cparata	2:a94816b14e3d	2324	reg.latency = val;
cparata	2:a94816b14e3d	2325	ret = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2326	}
cparata	2:a94816b14e3d	2327	return ret;
cparata	0:dff8803aace7	2328	}
cparata	0:dff8803aace7	2329
cparata	0:dff8803aace7	2330	/**
cparata	2:a94816b14e3d	2331	* @brief When double tap recognition is enabled, this register expresses
cparata	2:a94816b14e3d	2332	* the maximum time between two consecutive detected taps to
cparata	2:a94816b14e3d	2333	* determine a double tap event.
cparata	2:a94816b14e3d	2334	* The default value of these bits is 0000b which corresponds
cparata	2:a94816b14e3d	2335	* to 16*ODR_XL time. If the DUR[3:0] bits are set to a different
cparata	2:a94816b14e3d	2336	* value, 1LSB corresponds to 32*ODR_XL time.[get]
cparata	0:dff8803aace7	2337	*
cparata	2:a94816b14e3d	2338	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2339	* @param val change the values of latency in reg INT_DUR
cparata	2:a94816b14e3d	2340	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2341	*
cparata	0:dff8803aace7	2342	*/
cparata	0:dff8803aace7	2343	int32_t lis2dw12_tap_dur_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	2344	{
cparata	2:a94816b14e3d	2345	lis2dw12_int_dur_t reg;
cparata	2:a94816b14e3d	2346	int32_t ret;
cparata	0:dff8803aace7	2347
cparata	2:a94816b14e3d	2348	ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2349	*val = reg.latency;
cparata	0:dff8803aace7	2350
cparata	2:a94816b14e3d	2351	return ret;
cparata	0:dff8803aace7	2352	}
cparata	0:dff8803aace7	2353
cparata	0:dff8803aace7	2354	/**
cparata	2:a94816b14e3d	2355	* @brief Single/double-tap event enable.[set]
cparata	0:dff8803aace7	2356	*
cparata	2:a94816b14e3d	2357	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2358	* @param val change the values of single_double_tap in reg WAKE_UP_THS
cparata	2:a94816b14e3d	2359	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2360	*
cparata	0:dff8803aace7	2361	*/
cparata	0:dff8803aace7	2362	int32_t lis2dw12_tap_mode_set(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	2363	lis2dw12_single_double_tap_t val)
cparata	0:dff8803aace7	2364	{
cparata	2:a94816b14e3d	2365	lis2dw12_wake_up_ths_t reg;
cparata	2:a94816b14e3d	2366	int32_t ret;
cparata	0:dff8803aace7	2367
cparata	2:a94816b14e3d	2368	ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2369	if (ret == 0) {
cparata	2:a94816b14e3d	2370	reg.single_double_tap = (uint8_t) val;
cparata	2:a94816b14e3d	2371	ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2372	}
cparata	2:a94816b14e3d	2373	return ret;
cparata	0:dff8803aace7	2374	}
cparata	0:dff8803aace7	2375
cparata	0:dff8803aace7	2376	/**
cparata	2:a94816b14e3d	2377	* @brief Single/double-tap event enable.[get]
cparata	0:dff8803aace7	2378	*
cparata	2:a94816b14e3d	2379	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2380	* @param val Get the values of single_double_tap in reg WAKE_UP_THS
cparata	2:a94816b14e3d	2381	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2382	*
cparata	0:dff8803aace7	2383	*/
cparata	0:dff8803aace7	2384	int32_t lis2dw12_tap_mode_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	2385	lis2dw12_single_double_tap_t *val)
cparata	0:dff8803aace7	2386	{
cparata	2:a94816b14e3d	2387	lis2dw12_wake_up_ths_t reg;
cparata	2:a94816b14e3d	2388	int32_t ret;
cparata	2:a94816b14e3d	2389
cparata	2:a94816b14e3d	2390	ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) &reg, 1);
cparata	0:dff8803aace7	2391
cparata	2:a94816b14e3d	2392	switch (reg.single_double_tap) {
cparata	2:a94816b14e3d	2393	case LIS2DW12_ONLY_SINGLE:
cparata	2:a94816b14e3d	2394	*val = LIS2DW12_ONLY_SINGLE;
cparata	2:a94816b14e3d	2395	break;
cparata	2:a94816b14e3d	2396	case LIS2DW12_BOTH_SINGLE_DOUBLE:
cparata	2:a94816b14e3d	2397	*val = LIS2DW12_BOTH_SINGLE_DOUBLE;
cparata	2:a94816b14e3d	2398	break;
cparata	2:a94816b14e3d	2399	default:
cparata	2:a94816b14e3d	2400	*val = LIS2DW12_ONLY_SINGLE;
cparata	2:a94816b14e3d	2401	break;
cparata	2:a94816b14e3d	2402	}
cparata	0:dff8803aace7	2403
cparata	2:a94816b14e3d	2404	return ret;
cparata	0:dff8803aace7	2405	}
cparata	0:dff8803aace7	2406
cparata	0:dff8803aace7	2407	/**
cparata	2:a94816b14e3d	2408	* @brief Read the tap / double tap source register.[get]
cparata	0:dff8803aace7	2409	*
cparata	2:a94816b14e3d	2410	* @param ctx read / write interface definitions
cparata	0:dff8803aace7	2411	* @param lis2dw12_tap_src: union of registers from TAP_SRC to
cparata	2:a94816b14e3d	2412	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2413	*
cparata	0:dff8803aace7	2414	*/
cparata	0:dff8803aace7	2415	int32_t lis2dw12_tap_src_get(lis2dw12_ctx_t ctx, lis2dw12_tap_src_t val)
cparata	0:dff8803aace7	2416	{
cparata	2:a94816b14e3d	2417	int32_t ret;
cparata	2:a94816b14e3d	2418	ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_SRC, (uint8_t*) val, 1);
cparata	2:a94816b14e3d	2419	return ret;
cparata	0:dff8803aace7	2420	}
cparata	2:a94816b14e3d	2421
cparata	0:dff8803aace7	2422	/**
cparata	0:dff8803aace7	2423	* @}
cparata	2:a94816b14e3d	2424	*
cparata	0:dff8803aace7	2425	*/
cparata	0:dff8803aace7	2426
cparata	0:dff8803aace7	2427	/**
cparata	2:a94816b14e3d	2428	* @defgroup LIS2DW12_Six_Position_Detection(6D/4D)
cparata	2:a94816b14e3d	2429	* @brief This section groups all the functions concerning six
cparata	2:a94816b14e3d	2430	* position detection (6D).
cparata	0:dff8803aace7	2431	* @{
cparata	2:a94816b14e3d	2432	*
cparata	0:dff8803aace7	2433	*/
cparata	0:dff8803aace7	2434
cparata	0:dff8803aace7	2435	/**
cparata	2:a94816b14e3d	2436	* @brief Threshold for 4D/6D function.[set]
cparata	0:dff8803aace7	2437	*
cparata	2:a94816b14e3d	2438	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2439	* @param val change the values of 6d_ths in reg TAP_THS_X
cparata	2:a94816b14e3d	2440	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2441	*
cparata	0:dff8803aace7	2442	*/
cparata	0:dff8803aace7	2443	int32_t lis2dw12_6d_threshold_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	2444	{
cparata	2:a94816b14e3d	2445	lis2dw12_tap_ths_x_t reg;
cparata	2:a94816b14e3d	2446	int32_t ret;
cparata	0:dff8803aace7	2447
cparata	2:a94816b14e3d	2448	ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2449	if (ret == 0) {
cparata	2:a94816b14e3d	2450	reg._6d_ths = val;
cparata	2:a94816b14e3d	2451	ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2452	}
cparata	2:a94816b14e3d	2453	return ret;
cparata	0:dff8803aace7	2454	}
cparata	0:dff8803aace7	2455
cparata	0:dff8803aace7	2456	/**
cparata	2:a94816b14e3d	2457	* @brief Threshold for 4D/6D function.[get]
cparata	0:dff8803aace7	2458	*
cparata	2:a94816b14e3d	2459	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2460	* @param val change the values of 6d_ths in reg TAP_THS_X
cparata	2:a94816b14e3d	2461	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2462	*
cparata	0:dff8803aace7	2463	*/
cparata	0:dff8803aace7	2464	int32_t lis2dw12_6d_threshold_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	2465	{
cparata	2:a94816b14e3d	2466	lis2dw12_tap_ths_x_t reg;
cparata	2:a94816b14e3d	2467	int32_t ret;
cparata	0:dff8803aace7	2468
cparata	2:a94816b14e3d	2469	ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2470	*val = reg._6d_ths;
cparata	0:dff8803aace7	2471
cparata	2:a94816b14e3d	2472	return ret;
cparata	0:dff8803aace7	2473	}
cparata	0:dff8803aace7	2474
cparata	0:dff8803aace7	2475	/**
cparata	2:a94816b14e3d	2476	* @brief 4D orientation detection enable.[set]
cparata	0:dff8803aace7	2477	*
cparata	2:a94816b14e3d	2478	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2479	* @param val change the values of 4d_en in reg TAP_THS_X
cparata	2:a94816b14e3d	2480	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2481	*
cparata	0:dff8803aace7	2482	*/
cparata	0:dff8803aace7	2483	int32_t lis2dw12_4d_mode_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	2484	{
cparata	2:a94816b14e3d	2485	lis2dw12_tap_ths_x_t reg;
cparata	2:a94816b14e3d	2486	int32_t ret;
cparata	0:dff8803aace7	2487
cparata	2:a94816b14e3d	2488	ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2489	if (ret == 0) {
cparata	2:a94816b14e3d	2490	reg._4d_en = val;
cparata	2:a94816b14e3d	2491	ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2492	}
cparata	0:dff8803aace7	2493
cparata	2:a94816b14e3d	2494	return ret;
cparata	0:dff8803aace7	2495	}
cparata	0:dff8803aace7	2496
cparata	0:dff8803aace7	2497	/**
cparata	2:a94816b14e3d	2498	* @brief 4D orientation detection enable.[get]
cparata	0:dff8803aace7	2499	*
cparata	2:a94816b14e3d	2500	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2501	* @param val change the values of 4d_en in reg TAP_THS_X
cparata	2:a94816b14e3d	2502	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2503	*
cparata	0:dff8803aace7	2504	*/
cparata	0:dff8803aace7	2505	int32_t lis2dw12_4d_mode_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	2506	{
cparata	2:a94816b14e3d	2507	lis2dw12_tap_ths_x_t reg;
cparata	2:a94816b14e3d	2508	int32_t ret;
cparata	0:dff8803aace7	2509
cparata	2:a94816b14e3d	2510	ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2511	*val = reg._4d_en;
cparata	0:dff8803aace7	2512
cparata	2:a94816b14e3d	2513	return ret;
cparata	0:dff8803aace7	2514	}
cparata	0:dff8803aace7	2515
cparata	0:dff8803aace7	2516	/**
cparata	2:a94816b14e3d	2517	* @brief Read the 6D tap source register.[get]
cparata	0:dff8803aace7	2518	*
cparata	2:a94816b14e3d	2519	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2520	* @param val union of registers from SIXD_SRC
cparata	2:a94816b14e3d	2521	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2522	*
cparata	0:dff8803aace7	2523	*/
cparata	0:dff8803aace7	2524	int32_t lis2dw12_6d_src_get(lis2dw12_ctx_t ctx, lis2dw12_sixd_src_t val)
cparata	0:dff8803aace7	2525	{
cparata	2:a94816b14e3d	2526	int32_t ret;
cparata	2:a94816b14e3d	2527	ret = lis2dw12_read_reg(ctx, LIS2DW12_SIXD_SRC, (uint8_t*) val, 1);
cparata	2:a94816b14e3d	2528	return ret;
cparata	0:dff8803aace7	2529	}
cparata	0:dff8803aace7	2530	/**
cparata	2:a94816b14e3d	2531	* @brief Data sent to 6D interrupt function.[set]
cparata	0:dff8803aace7	2532	*
cparata	2:a94816b14e3d	2533	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2534	* @param val change the values of lpass_on6d in reg CTRL_REG7
cparata	2:a94816b14e3d	2535	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2536	*
cparata	0:dff8803aace7	2537	*/
cparata	0:dff8803aace7	2538	int32_t lis2dw12_6d_feed_data_set(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	2539	lis2dw12_lpass_on6d_t val)
cparata	0:dff8803aace7	2540	{
cparata	2:a94816b14e3d	2541	lis2dw12_ctrl_reg7_t reg;
cparata	2:a94816b14e3d	2542	int32_t ret;
cparata	0:dff8803aace7	2543
cparata	2:a94816b14e3d	2544	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2545	if (ret == 0) {
cparata	2:a94816b14e3d	2546	reg.lpass_on6d = (uint8_t) val;
cparata	2:a94816b14e3d	2547	ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2548	}
cparata	2:a94816b14e3d	2549	return ret;
cparata	0:dff8803aace7	2550	}
cparata	0:dff8803aace7	2551
cparata	0:dff8803aace7	2552	/**
cparata	2:a94816b14e3d	2553	* @brief Data sent to 6D interrupt function.[get]
cparata	0:dff8803aace7	2554	*
cparata	2:a94816b14e3d	2555	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2556	* @param val Get the values of lpass_on6d in reg CTRL_REG7
cparata	2:a94816b14e3d	2557	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2558	*
cparata	0:dff8803aace7	2559	*/
cparata	0:dff8803aace7	2560	int32_t lis2dw12_6d_feed_data_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	2561	lis2dw12_lpass_on6d_t *val)
cparata	0:dff8803aace7	2562	{
cparata	2:a94816b14e3d	2563	lis2dw12_ctrl_reg7_t reg;
cparata	2:a94816b14e3d	2564	int32_t ret;
cparata	2:a94816b14e3d	2565
cparata	2:a94816b14e3d	2566	ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:dff8803aace7	2567
cparata	2:a94816b14e3d	2568	switch (reg.lpass_on6d) {
cparata	2:a94816b14e3d	2569	case LIS2DW12_ODR_DIV_2_FEED:
cparata	2:a94816b14e3d	2570	*val = LIS2DW12_ODR_DIV_2_FEED;
cparata	2:a94816b14e3d	2571	break;
cparata	2:a94816b14e3d	2572	case LIS2DW12_LPF2_FEED:
cparata	2:a94816b14e3d	2573	*val = LIS2DW12_LPF2_FEED;
cparata	2:a94816b14e3d	2574	break;
cparata	2:a94816b14e3d	2575	default:
cparata	2:a94816b14e3d	2576	*val = LIS2DW12_ODR_DIV_2_FEED;
cparata	2:a94816b14e3d	2577	break;
cparata	2:a94816b14e3d	2578	}
cparata	2:a94816b14e3d	2579	return ret;
cparata	0:dff8803aace7	2580	}
cparata	0:dff8803aace7	2581
cparata	0:dff8803aace7	2582	/**
cparata	0:dff8803aace7	2583	* @}
cparata	2:a94816b14e3d	2584	*
cparata	0:dff8803aace7	2585	*/
cparata	0:dff8803aace7	2586
cparata	0:dff8803aace7	2587	/**
cparata	2:a94816b14e3d	2588	* @defgroup LIS2DW12_Free_Fall
cparata	2:a94816b14e3d	2589	* @brief This section group all the functions concerning
cparata	2:a94816b14e3d	2590	* the free fall detection.
cparata	0:dff8803aace7	2591	* @{
cparata	2:a94816b14e3d	2592	*
cparata	0:dff8803aace7	2593	*/
cparata	0:dff8803aace7	2594
cparata	0:dff8803aace7	2595	/**
cparata	2:a94816b14e3d	2596	* @brief Wake up duration event(1LSb = 1 / ODR).[set]
cparata	0:dff8803aace7	2597	*
cparata	2:a94816b14e3d	2598	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2599	* @param val change the values of ff_dur in reg
cparata	2:a94816b14e3d	2600	* WAKE_UP_DUR /F REE_FALL
cparata	2:a94816b14e3d	2601	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2602	*
cparata	0:dff8803aace7	2603	*/
cparata	0:dff8803aace7	2604	int32_t lis2dw12_ff_dur_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	2605	{
cparata	2:a94816b14e3d	2606	lis2dw12_wake_up_dur_t wake_up_dur;
cparata	2:a94816b14e3d	2607	lis2dw12_free_fall_t free_fall;
cparata	2:a94816b14e3d	2608	int32_t ret;
cparata	0:dff8803aace7	2609
cparata	2:a94816b14e3d	2610	ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
cparata	2:a94816b14e3d	2611	if (ret == 0) {
cparata	2:a94816b14e3d	2612	ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL,(uint8_t*) &free_fall, 1);
cparata	2:a94816b14e3d	2613	}
cparata	2:a94816b14e3d	2614	if(ret == 0) {
cparata	2:a94816b14e3d	2615	wake_up_dur.ff_dur = ( (uint8_t) val & 0x20U) >> 5;
cparata	2:a94816b14e3d	2616	free_fall.ff_dur = (uint8_t) val & 0x1FU;
cparata	2:a94816b14e3d	2617	ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
cparata	2:a94816b14e3d	2618	}
cparata	2:a94816b14e3d	2619	if(ret == 0) {
cparata	2:a94816b14e3d	2620	ret = lis2dw12_write_reg(ctx, LIS2DW12_FREE_FALL,(uint8_t*) &free_fall, 1);
cparata	2:a94816b14e3d	2621	}
cparata	2:a94816b14e3d	2622
cparata	2:a94816b14e3d	2623	return ret;
cparata	0:dff8803aace7	2624	}
cparata	0:dff8803aace7	2625
cparata	0:dff8803aace7	2626	/**
cparata	2:a94816b14e3d	2627	* @brief Wake up duration event(1LSb = 1 / ODR).[get]
cparata	0:dff8803aace7	2628	*
cparata	2:a94816b14e3d	2629	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2630	* @param val change the values of ff_dur in
cparata	0:dff8803aace7	2631	* reg WAKE_UP_DUR /F REE_FALL
cparata	2:a94816b14e3d	2632	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2633	*
cparata	0:dff8803aace7	2634	*/
cparata	0:dff8803aace7	2635	int32_t lis2dw12_ff_dur_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	2636	{
cparata	2:a94816b14e3d	2637	lis2dw12_wake_up_dur_t wake_up_dur;
cparata	2:a94816b14e3d	2638	lis2dw12_free_fall_t free_fall;
cparata	2:a94816b14e3d	2639	int32_t ret;
cparata	2:a94816b14e3d	2640
cparata	2:a94816b14e3d	2641	ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
cparata	2:a94816b14e3d	2642	if (ret == 0) {
cparata	2:a94816b14e3d	2643	ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL,(uint8_t*) &free_fall, 1);
cparata	2:a94816b14e3d	2644	*val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
cparata	2:a94816b14e3d	2645	}
cparata	2:a94816b14e3d	2646	return ret;
cparata	0:dff8803aace7	2647	}
cparata	0:dff8803aace7	2648
cparata	0:dff8803aace7	2649	/**
cparata	2:a94816b14e3d	2650	* @brief Free fall threshold setting.[set]
cparata	0:dff8803aace7	2651	*
cparata	2:a94816b14e3d	2652	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2653	* @param val change the values of ff_ths in reg FREE_FALL
cparata	2:a94816b14e3d	2654	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2655	*
cparata	0:dff8803aace7	2656	*/
cparata	0:dff8803aace7	2657	int32_t lis2dw12_ff_threshold_set(lis2dw12_ctx_t *ctx, lis2dw12_ff_ths_t val)
cparata	0:dff8803aace7	2658	{
cparata	2:a94816b14e3d	2659	lis2dw12_free_fall_t reg;
cparata	2:a94816b14e3d	2660	int32_t ret;
cparata	0:dff8803aace7	2661
cparata	2:a94816b14e3d	2662	ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2663	if (ret == 0) {
cparata	2:a94816b14e3d	2664	reg.ff_ths = (uint8_t) val;
cparata	2:a94816b14e3d	2665	ret = lis2dw12_write_reg(ctx, LIS2DW12_FREE_FALL,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2666	}
cparata	0:dff8803aace7	2667
cparata	2:a94816b14e3d	2668	return ret;
cparata	0:dff8803aace7	2669	}
cparata	0:dff8803aace7	2670
cparata	0:dff8803aace7	2671	/**
cparata	2:a94816b14e3d	2672	* @brief Free fall threshold setting.[get]
cparata	0:dff8803aace7	2673	*
cparata	2:a94816b14e3d	2674	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2675	* @param val Get the values of ff_ths in reg FREE_FALL
cparata	2:a94816b14e3d	2676	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2677	*
cparata	0:dff8803aace7	2678	*/
cparata	0:dff8803aace7	2679	int32_t lis2dw12_ff_threshold_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	2680	lis2dw12_ff_ths_t *val)
cparata	0:dff8803aace7	2681	{
cparata	2:a94816b14e3d	2682	lis2dw12_free_fall_t reg;
cparata	2:a94816b14e3d	2683	int32_t ret;
cparata	2:a94816b14e3d	2684
cparata	2:a94816b14e3d	2685	ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL,(uint8_t*) &reg, 1);
cparata	0:dff8803aace7	2686
cparata	2:a94816b14e3d	2687	switch (reg.ff_ths) {
cparata	2:a94816b14e3d	2688	case LIS2DW12_FF_TSH_5LSb_FS2g:
cparata	2:a94816b14e3d	2689	*val = LIS2DW12_FF_TSH_5LSb_FS2g;
cparata	2:a94816b14e3d	2690	break;
cparata	2:a94816b14e3d	2691	case LIS2DW12_FF_TSH_7LSb_FS2g:
cparata	2:a94816b14e3d	2692	*val = LIS2DW12_FF_TSH_7LSb_FS2g;
cparata	2:a94816b14e3d	2693	break;
cparata	2:a94816b14e3d	2694	case LIS2DW12_FF_TSH_8LSb_FS2g:
cparata	2:a94816b14e3d	2695	*val = LIS2DW12_FF_TSH_8LSb_FS2g;
cparata	2:a94816b14e3d	2696	break;
cparata	2:a94816b14e3d	2697	case LIS2DW12_FF_TSH_10LSb_FS2g:
cparata	2:a94816b14e3d	2698	*val = LIS2DW12_FF_TSH_10LSb_FS2g;
cparata	2:a94816b14e3d	2699	break;
cparata	2:a94816b14e3d	2700	case LIS2DW12_FF_TSH_11LSb_FS2g:
cparata	2:a94816b14e3d	2701	*val = LIS2DW12_FF_TSH_11LSb_FS2g;
cparata	2:a94816b14e3d	2702	break;
cparata	2:a94816b14e3d	2703	case LIS2DW12_FF_TSH_13LSb_FS2g:
cparata	2:a94816b14e3d	2704	*val = LIS2DW12_FF_TSH_13LSb_FS2g;
cparata	2:a94816b14e3d	2705	break;
cparata	2:a94816b14e3d	2706	case LIS2DW12_FF_TSH_15LSb_FS2g:
cparata	2:a94816b14e3d	2707	*val = LIS2DW12_FF_TSH_15LSb_FS2g;
cparata	2:a94816b14e3d	2708	break;
cparata	2:a94816b14e3d	2709	case LIS2DW12_FF_TSH_16LSb_FS2g:
cparata	2:a94816b14e3d	2710	*val = LIS2DW12_FF_TSH_16LSb_FS2g;
cparata	2:a94816b14e3d	2711	break;
cparata	2:a94816b14e3d	2712	default:
cparata	2:a94816b14e3d	2713	*val = LIS2DW12_FF_TSH_5LSb_FS2g;
cparata	2:a94816b14e3d	2714	break;
cparata	2:a94816b14e3d	2715	}
cparata	2:a94816b14e3d	2716	return ret;
cparata	0:dff8803aace7	2717	}
cparata	0:dff8803aace7	2718
cparata	0:dff8803aace7	2719	/**
cparata	0:dff8803aace7	2720	* @}
cparata	2:a94816b14e3d	2721	*
cparata	0:dff8803aace7	2722	*/
cparata	0:dff8803aace7	2723
cparata	0:dff8803aace7	2724	/**
cparata	2:a94816b14e3d	2725	* @defgroup LIS2DW12_Fifo
cparata	2:a94816b14e3d	2726	* @brief This section group all the functions concerning the fifo usage
cparata	0:dff8803aace7	2727	* @{
cparata	2:a94816b14e3d	2728	*
cparata	0:dff8803aace7	2729	*/
cparata	0:dff8803aace7	2730
cparata	0:dff8803aace7	2731	/**
cparata	2:a94816b14e3d	2732	* @brief FIFO watermark level selection.[set]
cparata	0:dff8803aace7	2733	*
cparata	2:a94816b14e3d	2734	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2735	* @param val change the values of fth in reg FIFO_CTRL
cparata	2:a94816b14e3d	2736	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2737	*
cparata	0:dff8803aace7	2738	*/
cparata	0:dff8803aace7	2739	int32_t lis2dw12_fifo_watermark_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	2740	{
cparata	2:a94816b14e3d	2741	lis2dw12_fifo_ctrl_t reg;
cparata	2:a94816b14e3d	2742	int32_t ret;
cparata	0:dff8803aace7	2743
cparata	2:a94816b14e3d	2744	ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2745	if (ret == 0) {
cparata	2:a94816b14e3d	2746	reg.fth = val;
cparata	2:a94816b14e3d	2747	ret = lis2dw12_write_reg(ctx, LIS2DW12_FIFO_CTRL,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2748	}
cparata	0:dff8803aace7	2749
cparata	2:a94816b14e3d	2750	return ret;
cparata	0:dff8803aace7	2751	}
cparata	0:dff8803aace7	2752
cparata	0:dff8803aace7	2753	/**
cparata	2:a94816b14e3d	2754	* @brief FIFO watermark level selection.[get]
cparata	0:dff8803aace7	2755	*
cparata	2:a94816b14e3d	2756	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2757	* @param val change the values of fth in reg FIFO_CTRL
cparata	2:a94816b14e3d	2758	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2759	*
cparata	0:dff8803aace7	2760	*/
cparata	0:dff8803aace7	2761	int32_t lis2dw12_fifo_watermark_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	2762	{
cparata	2:a94816b14e3d	2763	lis2dw12_fifo_ctrl_t reg;
cparata	2:a94816b14e3d	2764	int32_t ret;
cparata	0:dff8803aace7	2765
cparata	2:a94816b14e3d	2766	ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2767	*val = reg.fth;
cparata	0:dff8803aace7	2768
cparata	2:a94816b14e3d	2769	return ret;
cparata	0:dff8803aace7	2770	}
cparata	0:dff8803aace7	2771
cparata	0:dff8803aace7	2772	/**
cparata	2:a94816b14e3d	2773	* @brief FIFO mode selection.[set]
cparata	0:dff8803aace7	2774	*
cparata	2:a94816b14e3d	2775	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2776	* @param val change the values of fmode in reg FIFO_CTRL
cparata	2:a94816b14e3d	2777	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2778	*
cparata	0:dff8803aace7	2779	*/
cparata	0:dff8803aace7	2780	int32_t lis2dw12_fifo_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_fmode_t val)
cparata	0:dff8803aace7	2781	{
cparata	2:a94816b14e3d	2782	lis2dw12_fifo_ctrl_t reg;
cparata	2:a94816b14e3d	2783	int32_t ret;
cparata	0:dff8803aace7	2784
cparata	2:a94816b14e3d	2785	ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2786	if (ret == 0) {
cparata	2:a94816b14e3d	2787	reg.fmode = (uint8_t) val;
cparata	2:a94816b14e3d	2788	ret = lis2dw12_write_reg(ctx, LIS2DW12_FIFO_CTRL,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2789	}
cparata	2:a94816b14e3d	2790	return ret;
cparata	0:dff8803aace7	2791	}
cparata	0:dff8803aace7	2792
cparata	0:dff8803aace7	2793	/**
cparata	2:a94816b14e3d	2794	* @brief FIFO mode selection.[get]
cparata	0:dff8803aace7	2795	*
cparata	2:a94816b14e3d	2796	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2797	* @param val Get the values of fmode in reg FIFO_CTRL
cparata	2:a94816b14e3d	2798	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2799	*
cparata	0:dff8803aace7	2800	*/
cparata	0:dff8803aace7	2801	int32_t lis2dw12_fifo_mode_get(lis2dw12_ctx_t ctx, lis2dw12_fmode_t val)
cparata	0:dff8803aace7	2802	{
cparata	2:a94816b14e3d	2803	lis2dw12_fifo_ctrl_t reg;
cparata	2:a94816b14e3d	2804	int32_t ret;
cparata	2:a94816b14e3d	2805
cparata	2:a94816b14e3d	2806	ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL,(uint8_t*) &reg, 1);
cparata	0:dff8803aace7	2807
cparata	2:a94816b14e3d	2808	switch (reg.fmode) {
cparata	2:a94816b14e3d	2809	case LIS2DW12_BYPASS_MODE:
cparata	2:a94816b14e3d	2810	*val = LIS2DW12_BYPASS_MODE;
cparata	2:a94816b14e3d	2811	break;
cparata	2:a94816b14e3d	2812	case LIS2DW12_FIFO_MODE:
cparata	2:a94816b14e3d	2813	*val = LIS2DW12_FIFO_MODE;
cparata	2:a94816b14e3d	2814	break;
cparata	2:a94816b14e3d	2815	case LIS2DW12_STREAM_TO_FIFO_MODE:
cparata	2:a94816b14e3d	2816	*val = LIS2DW12_STREAM_TO_FIFO_MODE;
cparata	2:a94816b14e3d	2817	break;
cparata	2:a94816b14e3d	2818	case LIS2DW12_BYPASS_TO_STREAM_MODE:
cparata	2:a94816b14e3d	2819	*val = LIS2DW12_BYPASS_TO_STREAM_MODE;
cparata	2:a94816b14e3d	2820	break;
cparata	2:a94816b14e3d	2821	case LIS2DW12_STREAM_MODE:
cparata	2:a94816b14e3d	2822	*val = LIS2DW12_STREAM_MODE;
cparata	2:a94816b14e3d	2823	break;
cparata	2:a94816b14e3d	2824	default:
cparata	2:a94816b14e3d	2825	*val = LIS2DW12_BYPASS_MODE;
cparata	2:a94816b14e3d	2826	break;
cparata	2:a94816b14e3d	2827	}
cparata	2:a94816b14e3d	2828	return ret;
cparata	0:dff8803aace7	2829	}
cparata	0:dff8803aace7	2830
cparata	0:dff8803aace7	2831	/**
cparata	2:a94816b14e3d	2832	* @brief Number of unread samples stored in FIFO.[get]
cparata	0:dff8803aace7	2833	*
cparata	2:a94816b14e3d	2834	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2835	* @param val change the values of diff in reg FIFO_SAMPLES
cparata	2:a94816b14e3d	2836	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2837	*
cparata	0:dff8803aace7	2838	*/
cparata	0:dff8803aace7	2839	int32_t lis2dw12_fifo_data_level_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	2840	{
cparata	2:a94816b14e3d	2841	lis2dw12_fifo_samples_t reg;
cparata	2:a94816b14e3d	2842	int32_t ret;
cparata	0:dff8803aace7	2843
cparata	2:a94816b14e3d	2844	ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2845	*val = reg.diff;
cparata	0:dff8803aace7	2846
cparata	2:a94816b14e3d	2847	return ret;
cparata	0:dff8803aace7	2848	}
cparata	0:dff8803aace7	2849	/**
cparata	2:a94816b14e3d	2850	* @brief FIFO overrun status.[get]
cparata	0:dff8803aace7	2851	*
cparata	2:a94816b14e3d	2852	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2853	* @param val change the values of fifo_ovr in reg FIFO_SAMPLES
cparata	2:a94816b14e3d	2854	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2855	*
cparata	0:dff8803aace7	2856	*/
cparata	0:dff8803aace7	2857	int32_t lis2dw12_fifo_ovr_flag_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	2858	{
cparata	2:a94816b14e3d	2859	lis2dw12_fifo_samples_t reg;
cparata	2:a94816b14e3d	2860	int32_t ret;
cparata	0:dff8803aace7	2861
cparata	2:a94816b14e3d	2862	ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2863	*val = reg.fifo_ovr;
cparata	0:dff8803aace7	2864
cparata	2:a94816b14e3d	2865	return ret;
cparata	0:dff8803aace7	2866	}
cparata	0:dff8803aace7	2867	/**
cparata	2:a94816b14e3d	2868	* @brief FIFO threshold status flag.[get]
cparata	0:dff8803aace7	2869	*
cparata	2:a94816b14e3d	2870	* @param ctx read / write interface definitions
cparata	2:a94816b14e3d	2871	* @param val change the values of fifo_fth in reg FIFO_SAMPLES
cparata	2:a94816b14e3d	2872	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:dff8803aace7	2873	*
cparata	0:dff8803aace7	2874	*/
cparata	0:dff8803aace7	2875	int32_t lis2dw12_fifo_wtm_flag_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	2876	{
cparata	2:a94816b14e3d	2877	lis2dw12_fifo_samples_t reg;
cparata	2:a94816b14e3d	2878	int32_t ret;
cparata	0:dff8803aace7	2879
cparata	2:a94816b14e3d	2880	ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES,(uint8_t*) &reg, 1);
cparata	2:a94816b14e3d	2881	*val = reg.fifo_fth;
cparata	0:dff8803aace7	2882
cparata	2:a94816b14e3d	2883	return ret;
cparata	0:dff8803aace7	2884	}
cparata	0:dff8803aace7	2885	/**
cparata	0:dff8803aace7	2886	* @}
cparata	2:a94816b14e3d	2887	*
cparata	0:dff8803aace7	2888	*/
cparata	0:dff8803aace7	2889
cparata	0:dff8803aace7	2890	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	17 Sep 2019
Imports:	6
Forks:	0
Commits:	6
Dependents:	1
Dependencies:	2
Followers:	35

lis2dw12_reg.c@3:111317ba9301, 2018-11-21 (annotated)

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