Pin usage: MOSI(D4), MISO(D5), SCK(D3), CS(D6), format(8, 3) Test OK.
Fork of LSM6DS3 by
LSM6DS3_Types.h
00001 #ifndef __LSM6DS3_Types_H__ 00002 #define __LSM6DS3_Types_H__ 00003 00004 /******************************************************************************* 00005 * Register : TEST_PAGE 00006 * Address : 0X00 00007 * Bit Group Name: FLASH_PAGE 00008 * Permission : RW 00009 *******************************************************************************/ 00010 #define FLASH_PAGE 0x40 00011 00012 /******************************************************************************* 00013 * Register : RAM_ACCESS 00014 * Address : 0X01 00015 * Bit Group Name: PROG_RAM1 00016 * Permission : RW 00017 *******************************************************************************/ 00018 typedef enum { 00019 LSM6DS3_ACC_GYRO_PROG_RAM1_DISABLED = 0x00, 00020 LSM6DS3_ACC_GYRO_PROG_RAM1_ENABLED = 0x01, 00021 } LSM6DS3_ACC_GYRO_PROG_RAM1_t; 00022 00023 /******************************************************************************* 00024 * Register : RAM_ACCESS 00025 * Address : 0X01 00026 * Bit Group Name: CUSTOMROM1 00027 * Permission : RW 00028 *******************************************************************************/ 00029 typedef enum { 00030 LSM6DS3_ACC_GYRO_CUSTOMROM1_DISABLED = 0x00, 00031 LSM6DS3_ACC_GYRO_CUSTOMROM1_ENABLED = 0x04, 00032 } LSM6DS3_ACC_GYRO_CUSTOMROM1_t; 00033 00034 /******************************************************************************* 00035 * Register : RAM_ACCESS 00036 * Address : 0X01 00037 * Bit Group Name: RAM_PAGE 00038 * Permission : RW 00039 *******************************************************************************/ 00040 typedef enum { 00041 LSM6DS3_ACC_GYRO_RAM_PAGE_DISABLED = 0x00, 00042 LSM6DS3_ACC_GYRO_RAM_PAGE_ENABLED = 0x80, 00043 } LSM6DS3_ACC_GYRO_RAM_PAGE_t; 00044 00045 /******************************************************************************* 00046 * Register : SENSOR_SYNC_TIME 00047 * Address : 0X04 00048 * Bit Group Name: TPH 00049 * Permission : RW 00050 *******************************************************************************/ 00051 #define LSM6DS3_ACC_GYRO_TPH_MASK 0xFF 00052 #define LSM6DS3_ACC_GYRO_TPH_POSITION 0 00053 00054 /******************************************************************************* 00055 * Register : SENSOR_SYNC_EN 00056 * Address : 0X05 00057 * Bit Group Name: SYNC_EN 00058 * Permission : RW 00059 *******************************************************************************/ 00060 typedef enum { 00061 LSM6DS3_ACC_GYRO_SYNC_EN_DISABLED = 0x00, 00062 LSM6DS3_ACC_GYRO_SYNC_EN_ENABLED = 0x01, 00063 } LSM6DS3_ACC_GYRO_SYNC_EN_t; 00064 00065 /******************************************************************************* 00066 * Register : SENSOR_SYNC_EN 00067 * Address : 0X05 00068 * Bit Group Name: HP_RST 00069 * Permission : RW 00070 *******************************************************************************/ 00071 typedef enum { 00072 LSM6DS3_ACC_GYRO_HP_RST_RST_OFF = 0x00, 00073 LSM6DS3_ACC_GYRO_HP_RST_RST_ON = 0x02, 00074 } LSM6DS3_ACC_GYRO_HP_RST_t; 00075 00076 /******************************************************************************* 00077 * Register : FIFO_CTRL1 00078 * Address : 0X06 00079 * Bit Group Name: WTM_FIFO 00080 * Permission : RW 00081 *******************************************************************************/ 00082 #define LSM6DS3_ACC_GYRO_WTM_FIFO_CTRL1_MASK 0xFF 00083 #define LSM6DS3_ACC_GYRO_WTM_FIFO_CTRL1_POSITION 0 00084 #define LSM6DS3_ACC_GYRO_WTM_FIFO_CTRL2_MASK 0x0F 00085 #define LSM6DS3_ACC_GYRO_WTM_FIFO_CTRL2_POSITION 0 00086 00087 /******************************************************************************* 00088 * Register : FIFO_CTRL2 00089 * Address : 0X07 00090 * Bit Group Name: TIM_PEDO_FIFO_DRDY 00091 * Permission : RW 00092 *******************************************************************************/ 00093 typedef enum { 00094 LSM6DS3_ACC_GYRO_TIM_PEDO_FIFO_DRDY_DISABLED = 0x00, 00095 LSM6DS3_ACC_GYRO_TIM_PEDO_FIFO_DRDY_ENABLED = 0x40, 00096 } LSM6DS3_ACC_GYRO_TIM_PEDO_FIFO_DRDY_t; 00097 00098 /******************************************************************************* 00099 * Register : FIFO_CTRL2 00100 * Address : 0X07 00101 * Bit Group Name: TIM_PEDO_FIFO_EN 00102 * Permission : RW 00103 *******************************************************************************/ 00104 typedef enum { 00105 LSM6DS3_ACC_GYRO_TIM_PEDO_FIFO_EN_DISABLED = 0x00, 00106 LSM6DS3_ACC_GYRO_TIM_PEDO_FIFO_EN_ENABLED = 0x80, 00107 } LSM6DS3_ACC_GYRO_TIM_PEDO_FIFO_EN_t; 00108 00109 /******************************************************************************* 00110 * Register : FIFO_CTRL3 00111 * Address : 0X08 00112 * Bit Group Name: DEC_FIFO_XL 00113 * Permission : RW 00114 *******************************************************************************/ 00115 typedef enum { 00116 LSM6DS3_ACC_GYRO_DEC_FIFO_XL_DATA_NOT_IN_FIFO = 0x00, 00117 LSM6DS3_ACC_GYRO_DEC_FIFO_XL_NO_DECIMATION = 0x01, 00118 LSM6DS3_ACC_GYRO_DEC_FIFO_XL_DECIMATION_BY_2 = 0x02, 00119 LSM6DS3_ACC_GYRO_DEC_FIFO_XL_DECIMATION_BY_3 = 0x03, 00120 LSM6DS3_ACC_GYRO_DEC_FIFO_XL_DECIMATION_BY_4 = 0x04, 00121 LSM6DS3_ACC_GYRO_DEC_FIFO_XL_DECIMATION_BY_8 = 0x05, 00122 LSM6DS3_ACC_GYRO_DEC_FIFO_XL_DECIMATION_BY_16 = 0x06, 00123 LSM6DS3_ACC_GYRO_DEC_FIFO_XL_DECIMATION_BY_32 = 0x07, 00124 } LSM6DS3_ACC_GYRO_DEC_FIFO_XL_t; 00125 00126 /******************************************************************************* 00127 * Register : FIFO_CTRL3 00128 * Address : 0X08 00129 * Bit Group Name: DEC_FIFO_G 00130 * Permission : RW 00131 *******************************************************************************/ 00132 typedef enum { 00133 LSM6DS3_ACC_GYRO_DEC_FIFO_G_DATA_NOT_IN_FIFO = 0x00, 00134 LSM6DS3_ACC_GYRO_DEC_FIFO_G_NO_DECIMATION = 0x08, 00135 LSM6DS3_ACC_GYRO_DEC_FIFO_G_DECIMATION_BY_2 = 0x10, 00136 LSM6DS3_ACC_GYRO_DEC_FIFO_G_DECIMATION_BY_3 = 0x18, 00137 LSM6DS3_ACC_GYRO_DEC_FIFO_G_DECIMATION_BY_4 = 0x20, 00138 LSM6DS3_ACC_GYRO_DEC_FIFO_G_DECIMATION_BY_8 = 0x28, 00139 LSM6DS3_ACC_GYRO_DEC_FIFO_G_DECIMATION_BY_16 = 0x30, 00140 LSM6DS3_ACC_GYRO_DEC_FIFO_G_DECIMATION_BY_32 = 0x38, 00141 } LSM6DS3_ACC_GYRO_DEC_FIFO_G_t; 00142 00143 /******************************************************************************* 00144 * Register : FIFO_CTRL4 00145 * Address : 0X09 00146 * Bit Group Name: DEC_FIFO_SLV0 00147 * Permission : RW 00148 *******************************************************************************/ 00149 typedef enum { 00150 LSM6DS3_ACC_GYRO_DEC_FIFO_SLV0_DATA_NOT_IN_FIFO = 0x00, 00151 LSM6DS3_ACC_GYRO_DEC_FIFO_SLV0_NO_DECIMATION = 0x01, 00152 LSM6DS3_ACC_GYRO_DEC_FIFO_SLV0_DECIMATION_BY_2 = 0x02, 00153 LSM6DS3_ACC_GYRO_DEC_FIFO_SLV0_DECIMATION_BY_3 = 0x03, 00154 LSM6DS3_ACC_GYRO_DEC_FIFO_SLV0_DECIMATION_BY_4 = 0x04, 00155 LSM6DS3_ACC_GYRO_DEC_FIFO_SLV0_DECIMATION_BY_8 = 0x05, 00156 LSM6DS3_ACC_GYRO_DEC_FIFO_SLV0_DECIMATION_BY_16 = 0x06, 00157 LSM6DS3_ACC_GYRO_DEC_FIFO_SLV0_DECIMATION_BY_32 = 0x07, 00158 } LSM6DS3_ACC_GYRO_DEC_FIFO_SLV0_t; 00159 00160 /******************************************************************************* 00161 * Register : FIFO_CTRL4 00162 * Address : 0X09 00163 * Bit Group Name: DEC_FIFO_SLV1 00164 * Permission : RW 00165 *******************************************************************************/ 00166 typedef enum { 00167 LSM6DS3_ACC_GYRO_DEC_FIFO_SLV1_DATA_NOT_IN_FIFO = 0x00, 00168 LSM6DS3_ACC_GYRO_DEC_FIFO_SLV1_NO_DECIMATION = 0x08, 00169 LSM6DS3_ACC_GYRO_DEC_FIFO_SLV1_DECIMATION_BY_2 = 0x10, 00170 LSM6DS3_ACC_GYRO_DEC_FIFO_SLV1_DECIMATION_BY_3 = 0x18, 00171 LSM6DS3_ACC_GYRO_DEC_FIFO_SLV1_DECIMATION_BY_4 = 0x20, 00172 LSM6DS3_ACC_GYRO_DEC_FIFO_SLV1_DECIMATION_BY_8 = 0x28, 00173 LSM6DS3_ACC_GYRO_DEC_FIFO_SLV1_DECIMATION_BY_16 = 0x30, 00174 LSM6DS3_ACC_GYRO_DEC_FIFO_SLV1_DECIMATION_BY_32 = 0x38, 00175 } LSM6DS3_ACC_GYRO_DEC_FIFO_SLV1_t; 00176 00177 /******************************************************************************* 00178 * Register : FIFO_CTRL4 00179 * Address : 0X09 00180 * Bit Group Name: HI_DATA_ONLY 00181 * Permission : RW 00182 *******************************************************************************/ 00183 typedef enum { 00184 LSM6DS3_ACC_GYRO_HI_DATA_ONLY_DISABLED = 0x00, 00185 LSM6DS3_ACC_GYRO_HI_DATA_ONLY_ENABLED = 0x40, 00186 } LSM6DS3_ACC_GYRO_HI_DATA_ONLY_t; 00187 00188 /******************************************************************************* 00189 * Register : FIFO_CTRL5 00190 * Address : 0X0A 00191 * Bit Group Name: FIFO_MODE 00192 * Permission : RW 00193 *******************************************************************************/ 00194 typedef enum { 00195 LSM6DS3_ACC_GYRO_FIFO_MODE_BYPASS = 0x00, 00196 LSM6DS3_ACC_GYRO_FIFO_MODE_FIFO = 0x01, 00197 LSM6DS3_ACC_GYRO_FIFO_MODE_STREAM = 0x02, 00198 LSM6DS3_ACC_GYRO_FIFO_MODE_STF = 0x03, 00199 LSM6DS3_ACC_GYRO_FIFO_MODE_BTS = 0x04, 00200 LSM6DS3_ACC_GYRO_FIFO_MODE_DYN_STREAM = 0x05, 00201 LSM6DS3_ACC_GYRO_FIFO_MODE_DYN_STREAM_2 = 0x06, 00202 LSM6DS3_ACC_GYRO_FIFO_MODE_BTF = 0x07, 00203 } LSM6DS3_ACC_GYRO_FIFO_MODE_t; 00204 00205 /******************************************************************************* 00206 * Register : FIFO_CTRL5 00207 * Address : 0X0A 00208 * Bit Group Name: ODR_FIFO 00209 * Permission : RW 00210 *******************************************************************************/ 00211 typedef enum { 00212 LSM6DS3_ACC_GYRO_ODR_FIFO_10Hz = 0x08, 00213 LSM6DS3_ACC_GYRO_ODR_FIFO_25Hz = 0x10, 00214 LSM6DS3_ACC_GYRO_ODR_FIFO_50Hz = 0x18, 00215 LSM6DS3_ACC_GYRO_ODR_FIFO_100Hz = 0x20, 00216 LSM6DS3_ACC_GYRO_ODR_FIFO_200Hz = 0x28, 00217 LSM6DS3_ACC_GYRO_ODR_FIFO_400Hz = 0x30, 00218 LSM6DS3_ACC_GYRO_ODR_FIFO_800Hz = 0x38, 00219 LSM6DS3_ACC_GYRO_ODR_FIFO_1600Hz = 0x40, 00220 LSM6DS3_ACC_GYRO_ODR_FIFO_3300Hz = 0x48, 00221 LSM6DS3_ACC_GYRO_ODR_FIFO_6600Hz = 0x50, 00222 LSM6DS3_ACC_GYRO_ODR_FIFO_13300Hz = 0x58, 00223 } LSM6DS3_ACC_GYRO_ODR_FIFO_t; 00224 00225 /******************************************************************************* 00226 * Register : ORIENT_CFG_G 00227 * Address : 0X0B 00228 * Bit Group Name: ORIENT 00229 * Permission : RW 00230 *******************************************************************************/ 00231 typedef enum { 00232 LSM6DS3_ACC_GYRO_ORIENT_XYZ = 0x00, 00233 LSM6DS3_ACC_GYRO_ORIENT_XZY = 0x01, 00234 LSM6DS3_ACC_GYRO_ORIENT_YXZ = 0x02, 00235 LSM6DS3_ACC_GYRO_ORIENT_YZX = 0x03, 00236 LSM6DS3_ACC_GYRO_ORIENT_ZXY = 0x04, 00237 LSM6DS3_ACC_GYRO_ORIENT_ZYX = 0x05, 00238 } LSM6DS3_ACC_GYRO_ORIENT_t; 00239 00240 /******************************************************************************* 00241 * Register : ORIENT_CFG_G 00242 * Address : 0X0B 00243 * Bit Group Name: SIGN_Z_G 00244 * Permission : RW 00245 *******************************************************************************/ 00246 typedef enum { 00247 LSM6DS3_ACC_GYRO_SIGN_Z_G_POSITIVE = 0x00, 00248 LSM6DS3_ACC_GYRO_SIGN_Z_G_NEGATIVE = 0x08, 00249 } LSM6DS3_ACC_GYRO_SIGN_Z_G_t; 00250 00251 /******************************************************************************* 00252 * Register : ORIENT_CFG_G 00253 * Address : 0X0B 00254 * Bit Group Name: SIGN_Y_G 00255 * Permission : RW 00256 *******************************************************************************/ 00257 typedef enum { 00258 LSM6DS3_ACC_GYRO_SIGN_Y_G_POSITIVE = 0x00, 00259 LSM6DS3_ACC_GYRO_SIGN_Y_G_NEGATIVE = 0x10, 00260 } LSM6DS3_ACC_GYRO_SIGN_Y_G_t; 00261 00262 /******************************************************************************* 00263 * Register : ORIENT_CFG_G 00264 * Address : 0X0B 00265 * Bit Group Name: SIGN_X_G 00266 * Permission : RW 00267 *******************************************************************************/ 00268 typedef enum { 00269 LSM6DS3_ACC_GYRO_SIGN_X_G_POSITIVE = 0x00, 00270 LSM6DS3_ACC_GYRO_SIGN_X_G_NEGATIVE = 0x20, 00271 } LSM6DS3_ACC_GYRO_SIGN_X_G_t; 00272 00273 /******************************************************************************* 00274 * Register : REFERENCE_G 00275 * Address : 0X0C 00276 * Bit Group Name: REF_G 00277 * Permission : RW 00278 *******************************************************************************/ 00279 #define LSM6DS3_ACC_GYRO_REF_G_MASK 0xFF 00280 #define LSM6DS3_ACC_GYRO_REF_G_POSITION 0 00281 00282 /******************************************************************************* 00283 * Register : INT1_CTRL 00284 * Address : 0X0D 00285 * Bit Group Name: INT1_DRDY_XL 00286 * Permission : RW 00287 *******************************************************************************/ 00288 typedef enum { 00289 LSM6DS3_ACC_GYRO_INT1_DRDY_XL_DISABLED = 0x00, 00290 LSM6DS3_ACC_GYRO_INT1_DRDY_XL_ENABLED = 0x01, 00291 } LSM6DS3_ACC_GYRO_INT1_DRDY_XL_t; 00292 00293 /******************************************************************************* 00294 * Register : INT1_CTRL 00295 * Address : 0X0D 00296 * Bit Group Name: INT1_DRDY_G 00297 * Permission : RW 00298 *******************************************************************************/ 00299 typedef enum { 00300 LSM6DS3_ACC_GYRO_INT1_DRDY_G_DISABLED = 0x00, 00301 LSM6DS3_ACC_GYRO_INT1_DRDY_G_ENABLED = 0x02, 00302 } LSM6DS3_ACC_GYRO_INT1_DRDY_G_t; 00303 00304 /******************************************************************************* 00305 * Register : INT1_CTRL 00306 * Address : 0X0D 00307 * Bit Group Name: INT1_BOOT 00308 * Permission : RW 00309 *******************************************************************************/ 00310 typedef enum { 00311 LSM6DS3_ACC_GYRO_INT1_BOOT_DISABLED = 0x00, 00312 LSM6DS3_ACC_GYRO_INT1_BOOT_ENABLED = 0x04, 00313 } LSM6DS3_ACC_GYRO_INT1_BOOT_t; 00314 00315 /******************************************************************************* 00316 * Register : INT1_CTRL 00317 * Address : 0X0D 00318 * Bit Group Name: INT1_FTH 00319 * Permission : RW 00320 *******************************************************************************/ 00321 typedef enum { 00322 LSM6DS3_ACC_GYRO_INT1_FTH_DISABLED = 0x00, 00323 LSM6DS3_ACC_GYRO_INT1_FTH_ENABLED = 0x08, 00324 } LSM6DS3_ACC_GYRO_INT1_FTH_t; 00325 00326 /******************************************************************************* 00327 * Register : INT1_CTRL 00328 * Address : 0X0D 00329 * Bit Group Name: INT1_OVR 00330 * Permission : RW 00331 *******************************************************************************/ 00332 typedef enum { 00333 LSM6DS3_ACC_GYRO_INT1_OVR_DISABLED = 0x00, 00334 LSM6DS3_ACC_GYRO_INT1_OVR_ENABLED = 0x10, 00335 } LSM6DS3_ACC_GYRO_INT1_OVR_t; 00336 00337 /******************************************************************************* 00338 * Register : INT1_CTRL 00339 * Address : 0X0D 00340 * Bit Group Name: INT1_FSS5 00341 * Permission : RW 00342 *******************************************************************************/ 00343 typedef enum { 00344 LSM6DS3_ACC_GYRO_INT1_FSS5_DISABLED = 0x00, 00345 LSM6DS3_ACC_GYRO_INT1_FSS5_ENABLED = 0x20, 00346 } LSM6DS3_ACC_GYRO_INT1_FSS5_t; 00347 00348 /******************************************************************************* 00349 * Register : INT1_CTRL 00350 * Address : 0X0D 00351 * Bit Group Name: INT1_SIGN_MOT 00352 * Permission : RW 00353 *******************************************************************************/ 00354 typedef enum { 00355 LSM6DS3_ACC_GYRO_INT1_SIGN_MOT_DISABLED = 0x00, 00356 LSM6DS3_ACC_GYRO_INT1_SIGN_MOT_ENABLED = 0x40, 00357 } LSM6DS3_ACC_GYRO_INT1_SIGN_MOT_t; 00358 00359 /******************************************************************************* 00360 * Register : INT1_CTRL 00361 * Address : 0X0D 00362 * Bit Group Name: INT1_PEDO 00363 * Permission : RW 00364 *******************************************************************************/ 00365 typedef enum { 00366 LSM6DS3_ACC_GYRO_INT1_PEDO_DISABLED = 0x00, 00367 LSM6DS3_ACC_GYRO_INT1_PEDO_ENABLED = 0x80, 00368 } LSM6DS3_ACC_GYRO_INT1_PEDO_t; 00369 00370 /******************************************************************************* 00371 * Register : INT2_CTRL 00372 * Address : 0X0E 00373 * Bit Group Name: INT2_DRDY_XL 00374 * Permission : RW 00375 *******************************************************************************/ 00376 typedef enum { 00377 LSM6DS3_ACC_GYRO_INT2_DRDY_XL_DISABLED = 0x00, 00378 LSM6DS3_ACC_GYRO_INT2_DRDY_XL_ENABLED = 0x01, 00379 } LSM6DS3_ACC_GYRO_INT2_DRDY_XL_t; 00380 00381 /******************************************************************************* 00382 * Register : INT2_CTRL 00383 * Address : 0X0E 00384 * Bit Group Name: INT2_DRDY_G 00385 * Permission : RW 00386 *******************************************************************************/ 00387 typedef enum { 00388 LSM6DS3_ACC_GYRO_INT2_DRDY_G_DISABLED = 0x00, 00389 LSM6DS3_ACC_GYRO_INT2_DRDY_G_ENABLED = 0x02, 00390 } LSM6DS3_ACC_GYRO_INT2_DRDY_G_t; 00391 00392 /******************************************************************************* 00393 * Register : INT2_CTRL 00394 * Address : 0X0E 00395 * Bit Group Name: INT2_FTH 00396 * Permission : RW 00397 *******************************************************************************/ 00398 typedef enum { 00399 LSM6DS3_ACC_GYRO_INT2_FTH_DISABLED = 0x00, 00400 LSM6DS3_ACC_GYRO_INT2_FTH_ENABLED = 0x08, 00401 } LSM6DS3_ACC_GYRO_INT2_FTH_t; 00402 00403 /******************************************************************************* 00404 * Register : INT2_CTRL 00405 * Address : 0X0E 00406 * Bit Group Name: INT2_OVR 00407 * Permission : RW 00408 *******************************************************************************/ 00409 typedef enum { 00410 LSM6DS3_ACC_GYRO_INT2_OVR_DISABLED = 0x00, 00411 LSM6DS3_ACC_GYRO_INT2_OVR_ENABLED = 0x10, 00412 } LSM6DS3_ACC_GYRO_INT2_OVR_t; 00413 00414 /******************************************************************************* 00415 * Register : INT2_CTRL 00416 * Address : 0X0E 00417 * Bit Group Name: INT2_FSS5 00418 * Permission : RW 00419 *******************************************************************************/ 00420 typedef enum { 00421 LSM6DS3_ACC_GYRO_INT2_FSS5_DISABLED = 0x00, 00422 LSM6DS3_ACC_GYRO_INT2_FSS5_ENABLED = 0x20, 00423 } LSM6DS3_ACC_GYRO_INT2_FSS5_t; 00424 00425 /******************************************************************************* 00426 * Register : INT2_CTRL 00427 * Address : 0X0E 00428 * Bit Group Name: INT2_SIGN_MOT 00429 * Permission : RW 00430 *******************************************************************************/ 00431 typedef enum { 00432 LSM6DS3_ACC_GYRO_INT2_SIGN_MOT_DISABLED = 0x00, 00433 LSM6DS3_ACC_GYRO_INT2_SIGN_MOT_ENABLED = 0x40, 00434 } LSM6DS3_ACC_GYRO_INT2_SIGN_MOT_t; 00435 00436 /******************************************************************************* 00437 * Register : INT2_CTRL 00438 * Address : 0X0E 00439 * Bit Group Name: INT2_PEDO 00440 * Permission : RW 00441 *******************************************************************************/ 00442 typedef enum { 00443 LSM6DS3_ACC_GYRO_INT2_PEDO_DISABLED = 0x00, 00444 LSM6DS3_ACC_GYRO_INT2_PEDO_ENABLED = 0x80, 00445 } LSM6DS3_ACC_GYRO_INT2_PEDO_t; 00446 00447 /******************************************************************************* 00448 * Register : WHO_AM_I 00449 * Address : 0X0F 00450 * Bit Group Name: WHO_AM_I_BIT 00451 * Permission : RO 00452 *******************************************************************************/ 00453 #define LSM6DS3_ACC_GYRO_WHO_AM_I_BIT_MASK 0xFF 00454 #define LSM6DS3_ACC_GYRO_WHO_AM_I_BIT_POSITION 0 00455 00456 /******************************************************************************* 00457 * Register : CTRL1_XL 00458 * Address : 0X10 00459 * Bit Group Name: BW_XL 00460 * Permission : RW 00461 *******************************************************************************/ 00462 typedef enum { 00463 LSM6DS3_ACC_GYRO_BW_XL_400Hz = 0x00, 00464 LSM6DS3_ACC_GYRO_BW_XL_200Hz = 0x01, 00465 LSM6DS3_ACC_GYRO_BW_XL_100Hz = 0x02, 00466 LSM6DS3_ACC_GYRO_BW_XL_50Hz = 0x03, 00467 } LSM6DS3_ACC_GYRO_BW_XL_t; 00468 00469 /******************************************************************************* 00470 * Register : CTRL1_XL 00471 * Address : 0X10 00472 * Bit Group Name: FS_XL 00473 * Permission : RW 00474 *******************************************************************************/ 00475 typedef enum { 00476 LSM6DS3_ACC_GYRO_FS_XL_2g = 0x00, 00477 LSM6DS3_ACC_GYRO_FS_XL_16g = 0x04, 00478 LSM6DS3_ACC_GYRO_FS_XL_4g = 0x08, 00479 LSM6DS3_ACC_GYRO_FS_XL_8g = 0x0C, 00480 } LSM6DS3_ACC_GYRO_FS_XL_t; 00481 00482 /******************************************************************************* 00483 * Register : CTRL1_XL 00484 * Address : 0X10 00485 * Bit Group Name: ODR_XL 00486 * Permission : RW 00487 *******************************************************************************/ 00488 typedef enum { 00489 LSM6DS3_ACC_GYRO_ODR_XL_POWER_DOWN = 0x00, 00490 LSM6DS3_ACC_GYRO_ODR_XL_13Hz = 0x10, 00491 LSM6DS3_ACC_GYRO_ODR_XL_26Hz = 0x20, 00492 LSM6DS3_ACC_GYRO_ODR_XL_52Hz = 0x30, 00493 LSM6DS3_ACC_GYRO_ODR_XL_104Hz = 0x40, 00494 LSM6DS3_ACC_GYRO_ODR_XL_208Hz = 0x50, 00495 LSM6DS3_ACC_GYRO_ODR_XL_416Hz = 0x60, 00496 LSM6DS3_ACC_GYRO_ODR_XL_833Hz = 0x70, 00497 LSM6DS3_ACC_GYRO_ODR_XL_1660Hz = 0x80, 00498 LSM6DS3_ACC_GYRO_ODR_XL_3330Hz = 0x90, 00499 LSM6DS3_ACC_GYRO_ODR_XL_6660Hz = 0xA0, 00500 LSM6DS3_ACC_GYRO_ODR_XL_13330Hz = 0xB0, 00501 } LSM6DS3_ACC_GYRO_ODR_XL_t; 00502 00503 /******************************************************************************* 00504 * Register : CTRL2_G 00505 * Address : 0X11 00506 * Bit Group Name: FS_125 00507 * Permission : RW 00508 *******************************************************************************/ 00509 typedef enum { 00510 LSM6DS3_ACC_GYRO_FS_125_DISABLED = 0x00, 00511 LSM6DS3_ACC_GYRO_FS_125_ENABLED = 0x02, 00512 } LSM6DS3_ACC_GYRO_FS_125_t; 00513 00514 /******************************************************************************* 00515 * Register : CTRL2_G 00516 * Address : 0X11 00517 * Bit Group Name: FS_G 00518 * Permission : RW 00519 *******************************************************************************/ 00520 typedef enum { 00521 LSM6DS3_ACC_GYRO_FS_G_245dps = 0x00, 00522 LSM6DS3_ACC_GYRO_FS_G_500dps = 0x04, 00523 LSM6DS3_ACC_GYRO_FS_G_1000dps = 0x08, 00524 LSM6DS3_ACC_GYRO_FS_G_2000dps = 0x0C, 00525 } LSM6DS3_ACC_GYRO_FS_G_t; 00526 00527 /******************************************************************************* 00528 * Register : CTRL2_G 00529 * Address : 0X11 00530 * Bit Group Name: ODR_G 00531 * Permission : RW 00532 *******************************************************************************/ 00533 typedef enum { 00534 LSM6DS3_ACC_GYRO_ODR_G_POWER_DOWN = 0x00, 00535 LSM6DS3_ACC_GYRO_ODR_G_13Hz = 0x10, 00536 LSM6DS3_ACC_GYRO_ODR_G_26Hz = 0x20, 00537 LSM6DS3_ACC_GYRO_ODR_G_52Hz = 0x30, 00538 LSM6DS3_ACC_GYRO_ODR_G_104Hz = 0x40, 00539 LSM6DS3_ACC_GYRO_ODR_G_208Hz = 0x50, 00540 LSM6DS3_ACC_GYRO_ODR_G_416Hz = 0x60, 00541 LSM6DS3_ACC_GYRO_ODR_G_833Hz = 0x70, 00542 LSM6DS3_ACC_GYRO_ODR_G_1660Hz = 0x80, 00543 } LSM6DS3_ACC_GYRO_ODR_G_t; 00544 00545 /******************************************************************************* 00546 * Register : CTRL3_C 00547 * Address : 0X12 00548 * Bit Group Name: SW_RESET 00549 * Permission : RW 00550 *******************************************************************************/ 00551 typedef enum { 00552 LSM6DS3_ACC_GYRO_SW_RESET_NORMAL_MODE = 0x00, 00553 LSM6DS3_ACC_GYRO_SW_RESET_RESET_DEVICE = 0x01, 00554 } LSM6DS3_ACC_GYRO_SW_RESET_t; 00555 00556 /******************************************************************************* 00557 * Register : CTRL3_C 00558 * Address : 0X12 00559 * Bit Group Name: BLE 00560 * Permission : RW 00561 *******************************************************************************/ 00562 typedef enum { 00563 LSM6DS3_ACC_GYRO_BLE_LSB = 0x00, 00564 LSM6DS3_ACC_GYRO_BLE_MSB = 0x02, 00565 } LSM6DS3_ACC_GYRO_BLE_t; 00566 00567 /******************************************************************************* 00568 * Register : CTRL3_C 00569 * Address : 0X12 00570 * Bit Group Name: IF_INC 00571 * Permission : RW 00572 *******************************************************************************/ 00573 typedef enum { 00574 LSM6DS3_ACC_GYRO_IF_INC_DISABLED = 0x00, 00575 LSM6DS3_ACC_GYRO_IF_INC_ENABLED = 0x04, 00576 } LSM6DS3_ACC_GYRO_IF_INC_t; 00577 00578 /******************************************************************************* 00579 * Register : CTRL3_C 00580 * Address : 0X12 00581 * Bit Group Name: SIM 00582 * Permission : RW 00583 *******************************************************************************/ 00584 typedef enum { 00585 LSM6DS3_ACC_GYRO_SIM_4_WIRE = 0x00, 00586 LSM6DS3_ACC_GYRO_SIM_3_WIRE = 0x08, 00587 } LSM6DS3_ACC_GYRO_SIM_t; 00588 00589 /******************************************************************************* 00590 * Register : CTRL3_C 00591 * Address : 0X12 00592 * Bit Group Name: PP_OD 00593 * Permission : RW 00594 *******************************************************************************/ 00595 typedef enum { 00596 LSM6DS3_ACC_GYRO_PP_OD_PUSH_PULL = 0x00, 00597 LSM6DS3_ACC_GYRO_PP_OD_OPEN_DRAIN = 0x10, 00598 } LSM6DS3_ACC_GYRO_PP_OD_t; 00599 00600 /******************************************************************************* 00601 * Register : CTRL3_C 00602 * Address : 0X12 00603 * Bit Group Name: INT_ACT_LEVEL 00604 * Permission : RW 00605 *******************************************************************************/ 00606 typedef enum { 00607 LSM6DS3_ACC_GYRO_INT_ACT_LEVEL_ACTIVE_HI = 0x00, 00608 LSM6DS3_ACC_GYRO_INT_ACT_LEVEL_ACTIVE_LO = 0x20, 00609 } LSM6DS3_ACC_GYRO_INT_ACT_LEVEL_t; 00610 00611 /******************************************************************************* 00612 * Register : CTRL3_C 00613 * Address : 0X12 00614 * Bit Group Name: BDU 00615 * Permission : RW 00616 *******************************************************************************/ 00617 typedef enum { 00618 LSM6DS3_ACC_GYRO_BDU_CONTINUOS = 0x00, 00619 LSM6DS3_ACC_GYRO_BDU_BLOCK_UPDATE = 0x40, 00620 } LSM6DS3_ACC_GYRO_BDU_t; 00621 00622 /******************************************************************************* 00623 * Register : CTRL3_C 00624 * Address : 0X12 00625 * Bit Group Name: BOOT 00626 * Permission : RW 00627 *******************************************************************************/ 00628 typedef enum { 00629 LSM6DS3_ACC_GYRO_BOOT_NORMAL_MODE = 0x00, 00630 LSM6DS3_ACC_GYRO_BOOT_REBOOT_MODE = 0x80, 00631 } LSM6DS3_ACC_GYRO_BOOT_t; 00632 00633 /******************************************************************************* 00634 * Register : CTRL4_C 00635 * Address : 0X13 00636 * Bit Group Name: STOP_ON_FTH 00637 * Permission : RW 00638 *******************************************************************************/ 00639 typedef enum { 00640 LSM6DS3_ACC_GYRO_STOP_ON_FTH_DISABLED = 0x00, 00641 LSM6DS3_ACC_GYRO_STOP_ON_FTH_ENABLED = 0x01, 00642 } LSM6DS3_ACC_GYRO_STOP_ON_FTH_t; 00643 00644 /******************************************************************************* 00645 * Register : CTRL4_C 00646 * Address : 0X13 00647 * Bit Group Name: MODE3_EN 00648 * Permission : RW 00649 *******************************************************************************/ 00650 typedef enum { 00651 LSM6DS3_ACC_GYRO_MODE3_EN_DISABLED = 0x00, 00652 LSM6DS3_ACC_GYRO_MODE3_EN_ENABLED = 0x02, 00653 } LSM6DS3_ACC_GYRO_MODE3_EN_t; 00654 00655 /******************************************************************************* 00656 * Register : CTRL4_C 00657 * Address : 0X13 00658 * Bit Group Name: I2C_DISABLE 00659 * Permission : RW 00660 *******************************************************************************/ 00661 typedef enum { 00662 LSM6DS3_ACC_GYRO_I2C_DISABLE_I2C_AND_SPI = 0x00, 00663 LSM6DS3_ACC_GYRO_I2C_DISABLE_SPI_ONLY = 0x04, 00664 } LSM6DS3_ACC_GYRO_I2C_DISABLE_t; 00665 00666 /******************************************************************************* 00667 * Register : CTRL4_C 00668 * Address : 0X13 00669 * Bit Group Name: DRDY_MSK 00670 * Permission : RW 00671 *******************************************************************************/ 00672 typedef enum { 00673 LSM6DS3_ACC_GYRO_DRDY_MSK_DISABLED = 0x00, 00674 LSM6DS3_ACC_GYRO_DRDY_MSK_ENABLED = 0x08, 00675 } LSM6DS3_ACC_GYRO_DRDY_MSK_t; 00676 00677 /******************************************************************************* 00678 * Register : CTRL4_C 00679 * Address : 0X13 00680 * Bit Group Name: FIFO_TEMP_EN 00681 * Permission : RW 00682 *******************************************************************************/ 00683 typedef enum { 00684 LSM6DS3_ACC_GYRO_FIFO_TEMP_EN_DISABLED = 0x00, 00685 LSM6DS3_ACC_GYRO_FIFO_TEMP_EN_ENABLED = 0x10, 00686 } LSM6DS3_ACC_GYRO_FIFO_TEMP_EN_t; 00687 00688 /******************************************************************************* 00689 * Register : CTRL4_C 00690 * Address : 0X13 00691 * Bit Group Name: INT2_ON_INT1 00692 * Permission : RW 00693 *******************************************************************************/ 00694 typedef enum { 00695 LSM6DS3_ACC_GYRO_INT2_ON_INT1_DISABLED = 0x00, 00696 LSM6DS3_ACC_GYRO_INT2_ON_INT1_ENABLED = 0x20, 00697 } LSM6DS3_ACC_GYRO_INT2_ON_INT1_t; 00698 00699 /******************************************************************************* 00700 * Register : CTRL4_C 00701 * Address : 0X13 00702 * Bit Group Name: SLEEP_G 00703 * Permission : RW 00704 *******************************************************************************/ 00705 typedef enum { 00706 LSM6DS3_ACC_GYRO_SLEEP_G_DISABLED = 0x00, 00707 LSM6DS3_ACC_GYRO_SLEEP_G_ENABLED = 0x40, 00708 } LSM6DS3_ACC_GYRO_SLEEP_G_t; 00709 00710 /******************************************************************************* 00711 * Register : CTRL4_C 00712 * Address : 0X13 00713 * Bit Group Name: BW_SCAL_ODR 00714 * Permission : RW 00715 *******************************************************************************/ 00716 typedef enum { 00717 LSM6DS3_ACC_GYRO_BW_SCAL_ODR_DISABLED = 0x00, 00718 LSM6DS3_ACC_GYRO_BW_SCAL_ODR_ENABLED = 0x80, 00719 } LSM6DS3_ACC_GYRO_BW_SCAL_ODR_t; 00720 00721 /******************************************************************************* 00722 * Register : CTRL5_C 00723 * Address : 0X14 00724 * Bit Group Name: ST_XL 00725 * Permission : RW 00726 *******************************************************************************/ 00727 typedef enum { 00728 LSM6DS3_ACC_GYRO_ST_XL_NORMAL_MODE = 0x00, 00729 LSM6DS3_ACC_GYRO_ST_XL_POS_SIGN_TEST = 0x01, 00730 LSM6DS3_ACC_GYRO_ST_XL_NEG_SIGN_TEST = 0x02, 00731 LSM6DS3_ACC_GYRO_ST_XL_NA = 0x03, 00732 } LSM6DS3_ACC_GYRO_ST_XL_t; 00733 00734 /******************************************************************************* 00735 * Register : CTRL5_C 00736 * Address : 0X14 00737 * Bit Group Name: ST_G 00738 * Permission : RW 00739 *******************************************************************************/ 00740 typedef enum { 00741 LSM6DS3_ACC_GYRO_ST_G_NORMAL_MODE = 0x00, 00742 LSM6DS3_ACC_GYRO_ST_G_POS_SIGN_TEST = 0x04, 00743 LSM6DS3_ACC_GYRO_ST_G_NA = 0x08, 00744 LSM6DS3_ACC_GYRO_ST_G_NEG_SIGN_TEST = 0x0C, 00745 } LSM6DS3_ACC_GYRO_ST_G_t; 00746 00747 /******************************************************************************* 00748 * Register : CTRL6_G 00749 * Address : 0X15 00750 * Bit Group Name: LP_XL 00751 * Permission : RW 00752 *******************************************************************************/ 00753 typedef enum { 00754 LSM6DS3_ACC_GYRO_LP_XL_DISABLED = 0x00, 00755 LSM6DS3_ACC_GYRO_LP_XL_ENABLED = 0x10, 00756 } LSM6DS3_ACC_GYRO_LP_XL_t; 00757 00758 /******************************************************************************* 00759 * Register : CTRL6_G 00760 * Address : 0X15 00761 * Bit Group Name: DEN_LVL2_EN 00762 * Permission : RW 00763 *******************************************************************************/ 00764 typedef enum { 00765 LSM6DS3_ACC_GYRO_DEN_LVL2_EN_DISABLED = 0x00, 00766 LSM6DS3_ACC_GYRO_DEN_LVL2_EN_ENABLED = 0x20, 00767 } LSM6DS3_ACC_GYRO_DEN_LVL2_EN_t; 00768 00769 /******************************************************************************* 00770 * Register : CTRL6_G 00771 * Address : 0X15 00772 * Bit Group Name: DEN_LVL_EN 00773 * Permission : RW 00774 *******************************************************************************/ 00775 typedef enum { 00776 LSM6DS3_ACC_GYRO_DEN_LVL_EN_DISABLED = 0x00, 00777 LSM6DS3_ACC_GYRO_DEN_LVL_EN_ENABLED = 0x40, 00778 } LSM6DS3_ACC_GYRO_DEN_LVL_EN_t; 00779 00780 /******************************************************************************* 00781 * Register : CTRL6_G 00782 * Address : 0X15 00783 * Bit Group Name: DEN_EDGE_EN 00784 * Permission : RW 00785 *******************************************************************************/ 00786 typedef enum { 00787 LSM6DS3_ACC_GYRO_DEN_EDGE_EN_DISABLED = 0x00, 00788 LSM6DS3_ACC_GYRO_DEN_EDGE_EN_ENABLED = 0x80, 00789 } LSM6DS3_ACC_GYRO_DEN_EDGE_EN_t; 00790 00791 /******************************************************************************* 00792 * Register : CTRL7_G 00793 * Address : 0X16 00794 * Bit Group Name: HPM_G 00795 * Permission : RW 00796 *******************************************************************************/ 00797 typedef enum { 00798 LSM6DS3_ACC_GYRO_HPM_G_NORMAL_MODE = 0x00, 00799 LSM6DS3_ACC_GYRO_HPM_G_REF_SIGNAL = 0x10, 00800 LSM6DS3_ACC_GYRO_HPM_G_NORMAL_MODE_2 = 0x20, 00801 LSM6DS3_ACC_GYRO_HPM_G_AUTO_RESET_ON_INT = 0x30, 00802 } LSM6DS3_ACC_GYRO_HPM_G_t; 00803 00804 /******************************************************************************* 00805 * Register : CTRL7_G 00806 * Address : 0X16 00807 * Bit Group Name: HP_EN 00808 * Permission : RW 00809 *******************************************************************************/ 00810 typedef enum { 00811 LSM6DS3_ACC_GYRO_HP_EN_DISABLED = 0x00, 00812 LSM6DS3_ACC_GYRO_HP_EN_ENABLED = 0x40, 00813 } LSM6DS3_ACC_GYRO_HP_EN_t; 00814 00815 /******************************************************************************* 00816 * Register : CTRL7_G 00817 * Address : 0X16 00818 * Bit Group Name: LP_EN 00819 * Permission : RW 00820 *******************************************************************************/ 00821 typedef enum { 00822 LSM6DS3_ACC_GYRO_LP_EN_DISABLED = 0x00, 00823 LSM6DS3_ACC_GYRO_LP_EN_ENABLED = 0x80, 00824 } LSM6DS3_ACC_GYRO_LP_EN_t; 00825 00826 /******************************************************************************* 00827 * Register : CTRL8_XL 00828 * Address : 0X17 00829 * Bit Group Name: FDS 00830 * Permission : RW 00831 *******************************************************************************/ 00832 typedef enum { 00833 LSM6DS3_ACC_GYRO_FDS_FILTER_OFF = 0x00, 00834 LSM6DS3_ACC_GYRO_FDS_FILTER_ON = 0x04, 00835 } LSM6DS3_ACC_GYRO_FDS_t; 00836 00837 /******************************************************************************* 00838 * Register : CTRL9_XL 00839 * Address : 0X18 00840 * Bit Group Name: XEN_XL 00841 * Permission : RW 00842 *******************************************************************************/ 00843 typedef enum { 00844 LSM6DS3_ACC_GYRO_XEN_XL_DISABLED = 0x00, 00845 LSM6DS3_ACC_GYRO_XEN_XL_ENABLED = 0x08, 00846 } LSM6DS3_ACC_GYRO_XEN_XL_t; 00847 00848 /******************************************************************************* 00849 * Register : CTRL9_XL 00850 * Address : 0X18 00851 * Bit Group Name: YEN_XL 00852 * Permission : RW 00853 *******************************************************************************/ 00854 typedef enum { 00855 LSM6DS3_ACC_GYRO_YEN_XL_DISABLED = 0x00, 00856 LSM6DS3_ACC_GYRO_YEN_XL_ENABLED = 0x10, 00857 } LSM6DS3_ACC_GYRO_YEN_XL_t; 00858 00859 /******************************************************************************* 00860 * Register : CTRL9_XL 00861 * Address : 0X18 00862 * Bit Group Name: ZEN_XL 00863 * Permission : RW 00864 *******************************************************************************/ 00865 typedef enum { 00866 LSM6DS3_ACC_GYRO_ZEN_XL_DISABLED = 0x00, 00867 LSM6DS3_ACC_GYRO_ZEN_XL_ENABLED = 0x20, 00868 } LSM6DS3_ACC_GYRO_ZEN_XL_t; 00869 00870 /******************************************************************************* 00871 * Register : CTRL10_C 00872 * Address : 0X19 00873 * Bit Group Name: SIGN_MOTION_EN 00874 * Permission : RW 00875 *******************************************************************************/ 00876 typedef enum { 00877 LSM6DS3_ACC_GYRO_SIGN_MOTION_EN_DISABLED = 0x00, 00878 LSM6DS3_ACC_GYRO_SIGN_MOTION_EN_ENABLED = 0x01, 00879 } LSM6DS3_ACC_GYRO_SIGN_MOTION_EN_t; 00880 00881 /******************************************************************************* 00882 * Register : CTRL10_C 00883 * Address : 0X19 00884 * Bit Group Name: PEDO_RST_STEP 00885 * Permission : RW 00886 *******************************************************************************/ 00887 typedef enum { 00888 LSM6DS3_ACC_GYRO_PEDO_RST_STEP_DISABLED = 0x00, 00889 LSM6DS3_ACC_GYRO_PEDO_RST_STEP_ENABLED = 0x02, 00890 } LSM6DS3_ACC_GYRO_PEDO_RST_STEP_t; 00891 00892 /******************************************************************************* 00893 * Register : CTRL10_C 00894 * Address : 0X19 00895 * Bit Group Name: XEN_G 00896 * Permission : RW 00897 *******************************************************************************/ 00898 typedef enum { 00899 LSM6DS3_ACC_GYRO_XEN_G_DISABLED = 0x00, 00900 LSM6DS3_ACC_GYRO_XEN_G_ENABLED = 0x08, 00901 } LSM6DS3_ACC_GYRO_XEN_G_t; 00902 00903 /******************************************************************************* 00904 * Register : CTRL10_C 00905 * Address : 0X19 00906 * Bit Group Name: YEN_G 00907 * Permission : RW 00908 *******************************************************************************/ 00909 typedef enum { 00910 LSM6DS3_ACC_GYRO_YEN_G_DISABLED = 0x00, 00911 LSM6DS3_ACC_GYRO_YEN_G_ENABLED = 0x10, 00912 } LSM6DS3_ACC_GYRO_YEN_G_t; 00913 00914 /******************************************************************************* 00915 * Register : CTRL10_C 00916 * Address : 0X19 00917 * Bit Group Name: ZEN_G 00918 * Permission : RW 00919 *******************************************************************************/ 00920 typedef enum { 00921 LSM6DS3_ACC_GYRO_ZEN_G_DISABLED = 0x00, 00922 LSM6DS3_ACC_GYRO_ZEN_G_ENABLED = 0x20, 00923 } LSM6DS3_ACC_GYRO_ZEN_G_t; 00924 00925 /******************************************************************************* 00926 * Register : CTRL10_C 00927 * Address : 0X19 00928 * Bit Group Name: FUNC_EN 00929 * Permission : RW 00930 *******************************************************************************/ 00931 typedef enum { 00932 LSM6DS3_ACC_GYRO_FUNC_EN_DISABLED = 0x00, 00933 LSM6DS3_ACC_GYRO_FUNC_EN_ENABLED = 0x04, 00934 } LSM6DS3_ACC_GYRO_FUNC_EN_t; 00935 00936 /******************************************************************************* 00937 * Register : MASTER_CONFIG 00938 * Address : 0X1A 00939 * Bit Group Name: MASTER_ON 00940 * Permission : RW 00941 *******************************************************************************/ 00942 typedef enum { 00943 LSM6DS3_ACC_GYRO_MASTER_ON_DISABLED = 0x00, 00944 LSM6DS3_ACC_GYRO_MASTER_ON_ENABLED = 0x01, 00945 } LSM6DS3_ACC_GYRO_MASTER_ON_t; 00946 00947 /******************************************************************************* 00948 * Register : MASTER_CONFIG 00949 * Address : 0X1A 00950 * Bit Group Name: IRON_EN 00951 * Permission : RW 00952 *******************************************************************************/ 00953 typedef enum { 00954 LSM6DS3_ACC_GYRO_IRON_EN_DISABLED = 0x00, 00955 LSM6DS3_ACC_GYRO_IRON_EN_ENABLED = 0x02, 00956 } LSM6DS3_ACC_GYRO_IRON_EN_t; 00957 00958 /******************************************************************************* 00959 * Register : MASTER_CONFIG 00960 * Address : 0X1A 00961 * Bit Group Name: PASS_THRU_MODE 00962 * Permission : RW 00963 *******************************************************************************/ 00964 typedef enum { 00965 LSM6DS3_ACC_GYRO_PASS_THRU_MODE_DISABLED = 0x00, 00966 LSM6DS3_ACC_GYRO_PASS_THRU_MODE_ENABLED = 0x04, 00967 } LSM6DS3_ACC_GYRO_PASS_THRU_MODE_t; 00968 00969 /******************************************************************************* 00970 * Register : MASTER_CONFIG 00971 * Address : 0X1A 00972 * Bit Group Name: PULL_UP_EN 00973 * Permission : RW 00974 *******************************************************************************/ 00975 typedef enum { 00976 LSM6DS3_ACC_GYRO_PULL_UP_EN_DISABLED = 0x00, 00977 LSM6DS3_ACC_GYRO_PULL_UP_EN_ENABLED = 0x08, 00978 } LSM6DS3_ACC_GYRO_PULL_UP_EN_t; 00979 00980 /******************************************************************************* 00981 * Register : MASTER_CONFIG 00982 * Address : 0X1A 00983 * Bit Group Name: START_CONFIG 00984 * Permission : RW 00985 *******************************************************************************/ 00986 typedef enum { 00987 LSM6DS3_ACC_GYRO_START_CONFIG_XL_G_DRDY = 0x00, 00988 LSM6DS3_ACC_GYRO_START_CONFIG_EXT_INT2 = 0x10, 00989 } LSM6DS3_ACC_GYRO_START_CONFIG_t; 00990 00991 /******************************************************************************* 00992 * Register : MASTER_CONFIG 00993 * Address : 0X1A 00994 * Bit Group Name: DATA_VAL_SEL_FIFO 00995 * Permission : RW 00996 *******************************************************************************/ 00997 typedef enum { 00998 LSM6DS3_ACC_GYRO_DATA_VAL_SEL_FIFO_XL_G_DRDY = 0x00, 00999 LSM6DS3_ACC_GYRO_DATA_VAL_SEL_FIFO_SHUB_DRDY = 0x40, 01000 } LSM6DS3_ACC_GYRO_DATA_VAL_SEL_FIFO_t; 01001 01002 /******************************************************************************* 01003 * Register : MASTER_CONFIG 01004 * Address : 0X1A 01005 * Bit Group Name: DRDY_ON_INT1 01006 * Permission : RW 01007 *******************************************************************************/ 01008 typedef enum { 01009 LSM6DS3_ACC_GYRO_DRDY_ON_INT1_DISABLED = 0x00, 01010 LSM6DS3_ACC_GYRO_DRDY_ON_INT1_ENABLED = 0x80, 01011 } LSM6DS3_ACC_GYRO_DRDY_ON_INT1_t; 01012 01013 /******************************************************************************* 01014 * Register : WAKE_UP_SRC 01015 * Address : 0X1B 01016 * Bit Group Name: Z_WU 01017 * Permission : RO 01018 *******************************************************************************/ 01019 typedef enum { 01020 LSM6DS3_ACC_GYRO_Z_WU_NOT_DETECTED = 0x00, 01021 LSM6DS3_ACC_GYRO_Z_WU_DETECTED = 0x01, 01022 } LSM6DS3_ACC_GYRO_Z_WU_t; 01023 01024 /******************************************************************************* 01025 * Register : WAKE_UP_SRC 01026 * Address : 0X1B 01027 * Bit Group Name: Y_WU 01028 * Permission : RO 01029 *******************************************************************************/ 01030 typedef enum { 01031 LSM6DS3_ACC_GYRO_Y_WU_NOT_DETECTED = 0x00, 01032 LSM6DS3_ACC_GYRO_Y_WU_DETECTED = 0x02, 01033 } LSM6DS3_ACC_GYRO_Y_WU_t; 01034 01035 /******************************************************************************* 01036 * Register : WAKE_UP_SRC 01037 * Address : 0X1B 01038 * Bit Group Name: X_WU 01039 * Permission : RO 01040 *******************************************************************************/ 01041 typedef enum { 01042 LSM6DS3_ACC_GYRO_X_WU_NOT_DETECTED = 0x00, 01043 LSM6DS3_ACC_GYRO_X_WU_DETECTED = 0x04, 01044 } LSM6DS3_ACC_GYRO_X_WU_t; 01045 01046 /******************************************************************************* 01047 * Register : WAKE_UP_SRC 01048 * Address : 0X1B 01049 * Bit Group Name: WU_EV_STATUS 01050 * Permission : RO 01051 *******************************************************************************/ 01052 typedef enum { 01053 LSM6DS3_ACC_GYRO_WU_EV_STATUS_NOT_DETECTED = 0x00, 01054 LSM6DS3_ACC_GYRO_WU_EV_STATUS_DETECTED = 0x08, 01055 } LSM6DS3_ACC_GYRO_WU_EV_STATUS_t; 01056 01057 /******************************************************************************* 01058 * Register : WAKE_UP_SRC 01059 * Address : 0X1B 01060 * Bit Group Name: SLEEP_EV_STATUS 01061 * Permission : RO 01062 *******************************************************************************/ 01063 typedef enum { 01064 LSM6DS3_ACC_GYRO_SLEEP_EV_STATUS_NOT_DETECTED = 0x00, 01065 LSM6DS3_ACC_GYRO_SLEEP_EV_STATUS_DETECTED = 0x10, 01066 } LSM6DS3_ACC_GYRO_SLEEP_EV_STATUS_t; 01067 01068 /******************************************************************************* 01069 * Register : WAKE_UP_SRC 01070 * Address : 0X1B 01071 * Bit Group Name: FF_EV_STATUS 01072 * Permission : RO 01073 *******************************************************************************/ 01074 typedef enum { 01075 LSM6DS3_ACC_GYRO_FF_EV_STATUS_NOT_DETECTED = 0x00, 01076 LSM6DS3_ACC_GYRO_FF_EV_STATUS_DETECTED = 0x20, 01077 } LSM6DS3_ACC_GYRO_FF_EV_STATUS_t; 01078 01079 /******************************************************************************* 01080 * Register : TAP_SRC 01081 * Address : 0X1C 01082 * Bit Group Name: Z_TAP 01083 * Permission : RO 01084 *******************************************************************************/ 01085 typedef enum { 01086 LSM6DS3_ACC_GYRO_Z_TAP_NOT_DETECTED = 0x00, 01087 LSM6DS3_ACC_GYRO_Z_TAP_DETECTED = 0x01, 01088 } LSM6DS3_ACC_GYRO_Z_TAP_t; 01089 01090 /******************************************************************************* 01091 * Register : TAP_SRC 01092 * Address : 0X1C 01093 * Bit Group Name: Y_TAP 01094 * Permission : RO 01095 *******************************************************************************/ 01096 typedef enum { 01097 LSM6DS3_ACC_GYRO_Y_TAP_NOT_DETECTED = 0x00, 01098 LSM6DS3_ACC_GYRO_Y_TAP_DETECTED = 0x02, 01099 } LSM6DS3_ACC_GYRO_Y_TAP_t; 01100 01101 /******************************************************************************* 01102 * Register : TAP_SRC 01103 * Address : 0X1C 01104 * Bit Group Name: X_TAP 01105 * Permission : RO 01106 *******************************************************************************/ 01107 typedef enum { 01108 LSM6DS3_ACC_GYRO_X_TAP_NOT_DETECTED = 0x00, 01109 LSM6DS3_ACC_GYRO_X_TAP_DETECTED = 0x04, 01110 } LSM6DS3_ACC_GYRO_X_TAP_t; 01111 01112 /******************************************************************************* 01113 * Register : TAP_SRC 01114 * Address : 0X1C 01115 * Bit Group Name: TAP_SIGN 01116 * Permission : RO 01117 *******************************************************************************/ 01118 typedef enum { 01119 LSM6DS3_ACC_GYRO_TAP_SIGN_POS_SIGN = 0x00, 01120 LSM6DS3_ACC_GYRO_TAP_SIGN_NEG_SIGN = 0x08, 01121 } LSM6DS3_ACC_GYRO_TAP_SIGN_t; 01122 01123 /******************************************************************************* 01124 * Register : TAP_SRC 01125 * Address : 0X1C 01126 * Bit Group Name: DOUBLE_TAP_EV_STATUS 01127 * Permission : RO 01128 *******************************************************************************/ 01129 typedef enum { 01130 LSM6DS3_ACC_GYRO_DOUBLE_TAP_EV_STATUS_NOT_DETECTED = 0x00, 01131 LSM6DS3_ACC_GYRO_DOUBLE_TAP_EV_STATUS_DETECTED = 0x10, 01132 } LSM6DS3_ACC_GYRO_DOUBLE_TAP_EV_STATUS_t; 01133 01134 /******************************************************************************* 01135 * Register : TAP_SRC 01136 * Address : 0X1C 01137 * Bit Group Name: SINGLE_TAP_EV_STATUS 01138 * Permission : RO 01139 *******************************************************************************/ 01140 typedef enum { 01141 LSM6DS3_ACC_GYRO_SINGLE_TAP_EV_STATUS_NOT_DETECTED = 0x00, 01142 LSM6DS3_ACC_GYRO_SINGLE_TAP_EV_STATUS_DETECTED = 0x20, 01143 } LSM6DS3_ACC_GYRO_SINGLE_TAP_EV_STATUS_t; 01144 01145 /******************************************************************************* 01146 * Register : TAP_SRC 01147 * Address : 0X1C 01148 * Bit Group Name: TAP_EV_STATUS 01149 * Permission : RO 01150 *******************************************************************************/ 01151 typedef enum { 01152 LSM6DS3_ACC_GYRO_TAP_EV_STATUS_NOT_DETECTED = 0x00, 01153 LSM6DS3_ACC_GYRO_TAP_EV_STATUS_DETECTED = 0x40, 01154 } LSM6DS3_ACC_GYRO_TAP_EV_STATUS_t; 01155 01156 /******************************************************************************* 01157 * Register : D6D_SRC 01158 * Address : 0X1D 01159 * Bit Group Name: DSD_XL 01160 * Permission : RO 01161 *******************************************************************************/ 01162 typedef enum { 01163 LSM6DS3_ACC_GYRO_DSD_XL_NOT_DETECTED = 0x00, 01164 LSM6DS3_ACC_GYRO_DSD_XL_DETECTED = 0x01, 01165 } LSM6DS3_ACC_GYRO_DSD_XL_t; 01166 01167 /******************************************************************************* 01168 * Register : D6D_SRC 01169 * Address : 0X1D 01170 * Bit Group Name: DSD_XH 01171 * Permission : RO 01172 *******************************************************************************/ 01173 typedef enum { 01174 LSM6DS3_ACC_GYRO_DSD_XH_NOT_DETECTED = 0x00, 01175 LSM6DS3_ACC_GYRO_DSD_XH_DETECTED = 0x02, 01176 } LSM6DS3_ACC_GYRO_DSD_XH_t; 01177 01178 /******************************************************************************* 01179 * Register : D6D_SRC 01180 * Address : 0X1D 01181 * Bit Group Name: DSD_YL 01182 * Permission : RO 01183 *******************************************************************************/ 01184 typedef enum { 01185 LSM6DS3_ACC_GYRO_DSD_YL_NOT_DETECTED = 0x00, 01186 LSM6DS3_ACC_GYRO_DSD_YL_DETECTED = 0x04, 01187 } LSM6DS3_ACC_GYRO_DSD_YL_t; 01188 01189 /******************************************************************************* 01190 * Register : D6D_SRC 01191 * Address : 0X1D 01192 * Bit Group Name: DSD_YH 01193 * Permission : RO 01194 *******************************************************************************/ 01195 typedef enum { 01196 LSM6DS3_ACC_GYRO_DSD_YH_NOT_DETECTED = 0x00, 01197 LSM6DS3_ACC_GYRO_DSD_YH_DETECTED = 0x08, 01198 } LSM6DS3_ACC_GYRO_DSD_YH_t; 01199 01200 /******************************************************************************* 01201 * Register : D6D_SRC 01202 * Address : 0X1D 01203 * Bit Group Name: DSD_ZL 01204 * Permission : RO 01205 *******************************************************************************/ 01206 typedef enum { 01207 LSM6DS3_ACC_GYRO_DSD_ZL_NOT_DETECTED = 0x00, 01208 LSM6DS3_ACC_GYRO_DSD_ZL_DETECTED = 0x10, 01209 } LSM6DS3_ACC_GYRO_DSD_ZL_t; 01210 01211 /******************************************************************************* 01212 * Register : D6D_SRC 01213 * Address : 0X1D 01214 * Bit Group Name: DSD_ZH 01215 * Permission : RO 01216 *******************************************************************************/ 01217 typedef enum { 01218 LSM6DS3_ACC_GYRO_DSD_ZH_NOT_DETECTED = 0x00, 01219 LSM6DS3_ACC_GYRO_DSD_ZH_DETECTED = 0x20, 01220 } LSM6DS3_ACC_GYRO_DSD_ZH_t; 01221 01222 /******************************************************************************* 01223 * Register : D6D_SRC 01224 * Address : 0X1D 01225 * Bit Group Name: D6D_EV_STATUS 01226 * Permission : RO 01227 *******************************************************************************/ 01228 typedef enum { 01229 LSM6DS3_ACC_GYRO_D6D_EV_STATUS_NOT_DETECTED = 0x00, 01230 LSM6DS3_ACC_GYRO_D6D_EV_STATUS_DETECTED = 0x40, 01231 } LSM6DS3_ACC_GYRO_D6D_EV_STATUS_t; 01232 01233 /******************************************************************************* 01234 * Register : STATUS_REG 01235 * Address : 0X1E 01236 * Bit Group Name: XLDA 01237 * Permission : RO 01238 *******************************************************************************/ 01239 typedef enum { 01240 LSM6DS3_ACC_GYRO_XLDA_NO_DATA_AVAIL = 0x00, 01241 LSM6DS3_ACC_GYRO_XLDA_DATA_AVAIL = 0x01, 01242 } LSM6DS3_ACC_GYRO_XLDA_t; 01243 01244 /******************************************************************************* 01245 * Register : STATUS_REG 01246 * Address : 0X1E 01247 * Bit Group Name: GDA 01248 * Permission : RO 01249 *******************************************************************************/ 01250 typedef enum { 01251 LSM6DS3_ACC_GYRO_GDA_NO_DATA_AVAIL = 0x00, 01252 LSM6DS3_ACC_GYRO_GDA_DATA_AVAIL = 0x02, 01253 } LSM6DS3_ACC_GYRO_GDA_t; 01254 01255 /******************************************************************************* 01256 * Register : STATUS_REG 01257 * Address : 0X1E 01258 * Bit Group Name: EV_BOOT 01259 * Permission : RO 01260 *******************************************************************************/ 01261 typedef enum { 01262 LSM6DS3_ACC_GYRO_EV_BOOT_NO_BOOT_RUNNING = 0x00, 01263 LSM6DS3_ACC_GYRO_EV_BOOT_BOOT_IS_RUNNING = 0x08, 01264 } LSM6DS3_ACC_GYRO_EV_BOOT_t; 01265 01266 /******************************************************************************* 01267 * Register : FIFO_STATUS1 01268 * Address : 0X3A 01269 * Bit Group Name: DIFF_FIFO 01270 * Permission : RO 01271 *******************************************************************************/ 01272 #define LSM6DS3_ACC_GYRO_DIFF_FIFO_STATUS1_MASK 0xFF 01273 #define LSM6DS3_ACC_GYRO_DIFF_FIFO_STATUS1_POSITION 0 01274 #define LSM6DS3_ACC_GYRO_DIFF_FIFO_STATUS2_MASK 0xF 01275 #define LSM6DS3_ACC_GYRO_DIFF_FIFO_STATUS2_POSITION 0 01276 01277 /******************************************************************************* 01278 * Register : FIFO_STATUS2 01279 * Address : 0X3B 01280 * Bit Group Name: FIFO_EMPTY 01281 * Permission : RO 01282 *******************************************************************************/ 01283 typedef enum { 01284 LSM6DS3_ACC_GYRO_FIFO_EMPTY_FIFO_NOT_EMPTY = 0x00, 01285 LSM6DS3_ACC_GYRO_FIFO_EMPTY_FIFO_EMPTY = 0x10, 01286 } LSM6DS3_ACC_GYRO_FIFO_EMPTY_t; 01287 01288 /******************************************************************************* 01289 * Register : FIFO_STATUS2 01290 * Address : 0X3B 01291 * Bit Group Name: FIFO_FULL 01292 * Permission : RO 01293 *******************************************************************************/ 01294 typedef enum { 01295 LSM6DS3_ACC_GYRO_FIFO_FULL_FIFO_NOT_FULL = 0x00, 01296 LSM6DS3_ACC_GYRO_FIFO_FULL_FIFO_FULL = 0x20, 01297 } LSM6DS3_ACC_GYRO_FIFO_FULL_t; 01298 01299 /******************************************************************************* 01300 * Register : FIFO_STATUS2 01301 * Address : 0X3B 01302 * Bit Group Name: OVERRUN 01303 * Permission : RO 01304 *******************************************************************************/ 01305 typedef enum { 01306 LSM6DS3_ACC_GYRO_OVERRUN_NO_OVERRUN = 0x00, 01307 LSM6DS3_ACC_GYRO_OVERRUN_OVERRUN = 0x40, 01308 } LSM6DS3_ACC_GYRO_OVERRUN_t; 01309 01310 /******************************************************************************* 01311 * Register : FIFO_STATUS2 01312 * Address : 0X3B 01313 * Bit Group Name: WTM 01314 * Permission : RO 01315 *******************************************************************************/ 01316 typedef enum { 01317 LSM6DS3_ACC_GYRO_WTM_BELOW_WTM = 0x00, 01318 LSM6DS3_ACC_GYRO_WTM_ABOVE_OR_EQUAL_WTM = 0x80, 01319 } LSM6DS3_ACC_GYRO_WTM_t; 01320 01321 /******************************************************************************* 01322 * Register : FIFO_STATUS3 01323 * Address : 0X3C 01324 * Bit Group Name: FIFO_PATTERN 01325 * Permission : RO 01326 *******************************************************************************/ 01327 #define LSM6DS3_ACC_GYRO_FIFO_STATUS3_PATTERN_MASK 0xFF 01328 #define LSM6DS3_ACC_GYRO_FIFO_STATUS3_PATTERN_POSITION 0 01329 #define LSM6DS3_ACC_GYRO_FIFO_STATUS4_PATTERN_MASK 0x03 01330 #define LSM6DS3_ACC_GYRO_FIFO_STATUS4_PATTERN_POSITION 0 01331 01332 /******************************************************************************* 01333 * Register : FUNC_SRC 01334 * Address : 0X53 01335 * Bit Group Name: SENS_HUB_END 01336 * Permission : RO 01337 *******************************************************************************/ 01338 typedef enum { 01339 LSM6DS3_ACC_GYRO_SENS_HUB_END_STILL_ONGOING = 0x00, 01340 LSM6DS3_ACC_GYRO_SENS_HUB_END_OP_COMPLETED = 0x01, 01341 } LSM6DS3_ACC_GYRO_SENS_HUB_END_t; 01342 01343 /******************************************************************************* 01344 * Register : FUNC_SRC 01345 * Address : 0X53 01346 * Bit Group Name: SOFT_IRON_END 01347 * Permission : RO 01348 *******************************************************************************/ 01349 typedef enum { 01350 LSM6DS3_ACC_GYRO_SOFT_IRON_END_NOT_COMPLETED = 0x00, 01351 LSM6DS3_ACC_GYRO_SOFT_IRON_END_COMPLETED = 0x02, 01352 } LSM6DS3_ACC_GYRO_SOFT_IRON_END_t; 01353 01354 /******************************************************************************* 01355 * Register : FUNC_SRC 01356 * Address : 0X53 01357 * Bit Group Name: PEDO_EV_STATUS 01358 * Permission : RO 01359 *******************************************************************************/ 01360 typedef enum { 01361 LSM6DS3_ACC_GYRO_PEDO_EV_STATUS_NOT_DETECTED = 0x00, 01362 LSM6DS3_ACC_GYRO_PEDO_EV_STATUS_DETECTED = 0x10, 01363 } LSM6DS3_ACC_GYRO_PEDO_EV_STATUS_t; 01364 01365 /******************************************************************************* 01366 * Register : FUNC_SRC 01367 * Address : 0X53 01368 * Bit Group Name: TILT_EV_STATUS 01369 * Permission : RO 01370 *******************************************************************************/ 01371 typedef enum { 01372 LSM6DS3_ACC_GYRO_TILT_EV_STATUS_NOT_DETECTED = 0x00, 01373 LSM6DS3_ACC_GYRO_TILT_EV_STATUS_DETECTED = 0x20, 01374 } LSM6DS3_ACC_GYRO_TILT_EV_STATUS_t; 01375 01376 /******************************************************************************* 01377 * Register : FUNC_SRC 01378 * Address : 0X53 01379 * Bit Group Name: SIGN_MOT_EV_STATUS 01380 * Permission : RO 01381 *******************************************************************************/ 01382 typedef enum { 01383 LSM6DS3_ACC_GYRO_SIGN_MOT_EV_STATUS_NOT_DETECTED = 0x00, 01384 LSM6DS3_ACC_GYRO_SIGN_MOT_EV_STATUS_DETECTED = 0x40, 01385 } LSM6DS3_ACC_GYRO_SIGN_MOT_EV_STATUS_t; 01386 01387 /******************************************************************************* 01388 * Register : TAP_CFG1 01389 * Address : 0X58 01390 * Bit Group Name: LIR 01391 * Permission : RW 01392 *******************************************************************************/ 01393 typedef enum { 01394 LSM6DS3_ACC_GYRO_LIR_DISABLED = 0x00, 01395 LSM6DS3_ACC_GYRO_LIR_ENABLED = 0x01, 01396 } LSM6DS3_ACC_GYRO_LIR_t; 01397 01398 /******************************************************************************* 01399 * Register : TAP_CFG1 01400 * Address : 0X58 01401 * Bit Group Name: TAP_Z_EN 01402 * Permission : RW 01403 *******************************************************************************/ 01404 typedef enum { 01405 LSM6DS3_ACC_GYRO_TAP_Z_EN_DISABLED = 0x00, 01406 LSM6DS3_ACC_GYRO_TAP_Z_EN_ENABLED = 0x02, 01407 } LSM6DS3_ACC_GYRO_TAP_Z_EN_t; 01408 01409 /******************************************************************************* 01410 * Register : TAP_CFG1 01411 * Address : 0X58 01412 * Bit Group Name: TAP_Y_EN 01413 * Permission : RW 01414 *******************************************************************************/ 01415 typedef enum { 01416 LSM6DS3_ACC_GYRO_TAP_Y_EN_DISABLED = 0x00, 01417 LSM6DS3_ACC_GYRO_TAP_Y_EN_ENABLED = 0x04, 01418 } LSM6DS3_ACC_GYRO_TAP_Y_EN_t; 01419 01420 /******************************************************************************* 01421 * Register : TAP_CFG1 01422 * Address : 0X58 01423 * Bit Group Name: TAP_X_EN 01424 * Permission : RW 01425 *******************************************************************************/ 01426 typedef enum { 01427 LSM6DS3_ACC_GYRO_TAP_X_EN_DISABLED = 0x00, 01428 LSM6DS3_ACC_GYRO_TAP_X_EN_ENABLED = 0x08, 01429 } LSM6DS3_ACC_GYRO_TAP_X_EN_t; 01430 01431 /******************************************************************************* 01432 * Register : TAP_CFG1 01433 * Address : 0X58 01434 * Bit Group Name: TILT_EN 01435 * Permission : RW 01436 *******************************************************************************/ 01437 typedef enum { 01438 LSM6DS3_ACC_GYRO_TILT_EN_DISABLED = 0x00, 01439 LSM6DS3_ACC_GYRO_TILT_EN_ENABLED = 0x20, 01440 } LSM6DS3_ACC_GYRO_TILT_EN_t; 01441 01442 /******************************************************************************* 01443 * Register : TAP_CFG1 01444 * Address : 0X58 01445 * Bit Group Name: PEDO_EN 01446 * Permission : RW 01447 *******************************************************************************/ 01448 typedef enum { 01449 LSM6DS3_ACC_GYRO_PEDO_EN_DISABLED = 0x00, 01450 LSM6DS3_ACC_GYRO_PEDO_EN_ENABLED = 0x40, 01451 } LSM6DS3_ACC_GYRO_PEDO_EN_t; 01452 01453 /******************************************************************************* 01454 * Register : TAP_CFG1 01455 * Address : 0X58 01456 * Bit Group Name: TIMER_EN 01457 * Permission : RW 01458 *******************************************************************************/ 01459 typedef enum { 01460 LSM6DS3_ACC_GYRO_TIMER_EN_DISABLED = 0x00, 01461 LSM6DS3_ACC_GYRO_TIMER_EN_ENABLED = 0x80, 01462 } LSM6DS3_ACC_GYRO_TIMER_EN_t; 01463 01464 /******************************************************************************* 01465 * Register : TAP_THS_6D 01466 * Address : 0X59 01467 * Bit Group Name: TAP_THS 01468 * Permission : RW 01469 *******************************************************************************/ 01470 #define LSM6DS3_ACC_GYRO_TAP_THS_MASK 0x1F 01471 #define LSM6DS3_ACC_GYRO_TAP_THS_POSITION 0 01472 01473 /******************************************************************************* 01474 * Register : TAP_THS_6D 01475 * Address : 0X59 01476 * Bit Group Name: SIXD_THS 01477 * Permission : RW 01478 *******************************************************************************/ 01479 typedef enum { 01480 LSM6DS3_ACC_GYRO_SIXD_THS_80_degree = 0x00, 01481 LSM6DS3_ACC_GYRO_SIXD_THS_70_degree = 0x20, 01482 LSM6DS3_ACC_GYRO_SIXD_THS_60_degree = 0x40, 01483 LSM6DS3_ACC_GYRO_SIXD_THS_50_degree = 0x60, 01484 } LSM6DS3_ACC_GYRO_SIXD_THS_t; 01485 01486 /******************************************************************************* 01487 * Register : INT_DUR2 01488 * Address : 0X5A 01489 * Bit Group Name: SHOCK 01490 * Permission : RW 01491 *******************************************************************************/ 01492 #define LSM6DS3_ACC_GYRO_SHOCK_MASK 0x03 01493 #define LSM6DS3_ACC_GYRO_SHOCK_POSITION 0 01494 01495 /******************************************************************************* 01496 * Register : INT_DUR2 01497 * Address : 0X5A 01498 * Bit Group Name: QUIET 01499 * Permission : RW 01500 *******************************************************************************/ 01501 #define LSM6DS3_ACC_GYRO_QUIET_MASK 0x0C 01502 #define LSM6DS3_ACC_GYRO_QUIET_POSITION 2 01503 01504 /******************************************************************************* 01505 * Register : INT_DUR2 01506 * Address : 0X5A 01507 * Bit Group Name: DUR 01508 * Permission : RW 01509 *******************************************************************************/ 01510 #define LSM6DS3_ACC_GYRO_DUR_MASK 0xF0 01511 #define LSM6DS3_ACC_GYRO_DUR_POSITION 4 01512 01513 /******************************************************************************* 01514 * Register : WAKE_UP_THS 01515 * Address : 0X5B 01516 * Bit Group Name: WK_THS 01517 * Permission : RW 01518 *******************************************************************************/ 01519 #define LSM6DS3_ACC_GYRO_WK_THS_MASK 0x3F 01520 #define LSM6DS3_ACC_GYRO_WK_THS_POSITION 0 01521 01522 /******************************************************************************* 01523 * Register : WAKE_UP_THS 01524 * Address : 0X5B 01525 * Bit Group Name: INACTIVITY_ON 01526 * Permission : RW 01527 *******************************************************************************/ 01528 typedef enum { 01529 LSM6DS3_ACC_GYRO_INACTIVITY_ON_DISABLED = 0x00, 01530 LSM6DS3_ACC_GYRO_INACTIVITY_ON_ENABLED = 0x40, 01531 } LSM6DS3_ACC_GYRO_INACTIVITY_ON_t; 01532 01533 /******************************************************************************* 01534 * Register : WAKE_UP_THS 01535 * Address : 0X5B 01536 * Bit Group Name: SINGLE_DOUBLE_TAP 01537 * Permission : RW 01538 *******************************************************************************/ 01539 typedef enum { 01540 LSM6DS3_ACC_GYRO_SINGLE_DOUBLE_TAP_DOUBLE_TAP = 0x00, 01541 LSM6DS3_ACC_GYRO_SINGLE_DOUBLE_TAP_SINGLE_TAP = 0x80, 01542 } LSM6DS3_ACC_GYRO_SINGLE_DOUBLE_TAP_t; 01543 01544 /******************************************************************************* 01545 * Register : WAKE_UP_DUR 01546 * Address : 0X5C 01547 * Bit Group Name: SLEEP_DUR 01548 * Permission : RW 01549 *******************************************************************************/ 01550 #define LSM6DS3_ACC_GYRO_SLEEP_DUR_MASK 0x0F 01551 #define LSM6DS3_ACC_GYRO_SLEEP_DUR_POSITION 0 01552 01553 /******************************************************************************* 01554 * Register : WAKE_UP_DUR 01555 * Address : 0X5C 01556 * Bit Group Name: TIMER_HR 01557 * Permission : RW 01558 *******************************************************************************/ 01559 typedef enum { 01560 LSM6DS3_ACC_GYRO_TIMER_HR_6_4ms = 0x00, 01561 LSM6DS3_ACC_GYRO_TIMER_HR_25us = 0x10, 01562 } LSM6DS3_ACC_GYRO_TIMER_HR_t; 01563 01564 /******************************************************************************* 01565 * Register : WAKE_UP_DUR 01566 * Address : 0X5C 01567 * Bit Group Name: WAKE_DUR 01568 * Permission : RW 01569 *******************************************************************************/ 01570 #define LSM6DS3_ACC_GYRO_WAKE_DUR_MASK 0x60 01571 #define LSM6DS3_ACC_GYRO_WAKE_DUR_POSITION 5 01572 01573 /******************************************************************************* 01574 * Register : FREE_FALL 01575 * Address : 0X5D 01576 * Bit Group Name: FF_DUR 01577 * Permission : RW 01578 *******************************************************************************/ 01579 #define LSM6DS3_ACC_GYRO_FF_FREE_FALL_DUR_MASK 0xF8 01580 #define LSM6DS3_ACC_GYRO_FF_FREE_FALL_DUR_POSITION 3 01581 #define LSM6DS3_ACC_GYRO_FF_WAKE_UP_DUR_MASK 0x80 01582 #define LSM6DS3_ACC_GYRO_FF_WAKE_UP_DUR_POSITION 7 01583 01584 01585 /******************************************************************************* 01586 * Register : FREE_FALL 01587 * Address : 0X5D 01588 * Bit Group Name: FF_THS 01589 * Permission : RW 01590 *******************************************************************************/ 01591 typedef enum { 01592 LSM6DS3_ACC_GYRO_FF_THS_5 = 0x00, 01593 LSM6DS3_ACC_GYRO_FF_THS_7 = 0x01, 01594 LSM6DS3_ACC_GYRO_FF_THS_8 = 0x02, 01595 LSM6DS3_ACC_GYRO_FF_THS_10 = 0x03, 01596 LSM6DS3_ACC_GYRO_FF_THS_11 = 0x04, 01597 LSM6DS3_ACC_GYRO_FF_THS_13 = 0x05, 01598 LSM6DS3_ACC_GYRO_FF_THS_15 = 0x06, 01599 LSM6DS3_ACC_GYRO_FF_THS_16 = 0x07, 01600 } LSM6DS3_ACC_GYRO_FF_THS_t; 01601 01602 /******************************************************************************* 01603 * Register : MD1_CFG 01604 * Address : 0X5E 01605 * Bit Group Name: INT1_TIMER 01606 * Permission : RW 01607 *******************************************************************************/ 01608 typedef enum { 01609 LSM6DS3_ACC_GYRO_INT1_TIMER_DISABLED = 0x00, 01610 LSM6DS3_ACC_GYRO_INT1_TIMER_ENABLED = 0x01, 01611 } LSM6DS3_ACC_GYRO_INT1_TIMER_t; 01612 01613 /******************************************************************************* 01614 * Register : MD1_CFG 01615 * Address : 0X5E 01616 * Bit Group Name: INT1_TILT 01617 * Permission : RW 01618 *******************************************************************************/ 01619 typedef enum { 01620 LSM6DS3_ACC_GYRO_INT1_TILT_DISABLED = 0x00, 01621 LSM6DS3_ACC_GYRO_INT1_TILT_ENABLED = 0x02, 01622 } LSM6DS3_ACC_GYRO_INT1_TILT_t; 01623 01624 /******************************************************************************* 01625 * Register : MD1_CFG 01626 * Address : 0X5E 01627 * Bit Group Name: INT1_6D 01628 * Permission : RW 01629 *******************************************************************************/ 01630 typedef enum { 01631 LSM6DS3_ACC_GYRO_INT1_6D_DISABLED = 0x00, 01632 LSM6DS3_ACC_GYRO_INT1_6D_ENABLED = 0x04, 01633 } LSM6DS3_ACC_GYRO_INT1_6D_t; 01634 01635 /******************************************************************************* 01636 * Register : MD1_CFG 01637 * Address : 0X5E 01638 * Bit Group Name: INT1_TAP 01639 * Permission : RW 01640 *******************************************************************************/ 01641 typedef enum { 01642 LSM6DS3_ACC_GYRO_INT1_TAP_DISABLED = 0x00, 01643 LSM6DS3_ACC_GYRO_INT1_TAP_ENABLED = 0x08, 01644 } LSM6DS3_ACC_GYRO_INT1_TAP_t; 01645 01646 /******************************************************************************* 01647 * Register : MD1_CFG 01648 * Address : 0X5E 01649 * Bit Group Name: INT1_FF 01650 * Permission : RW 01651 *******************************************************************************/ 01652 typedef enum { 01653 LSM6DS3_ACC_GYRO_INT1_FF_DISABLED = 0x00, 01654 LSM6DS3_ACC_GYRO_INT1_FF_ENABLED = 0x10, 01655 } LSM6DS3_ACC_GYRO_INT1_FF_t; 01656 01657 /******************************************************************************* 01658 * Register : MD1_CFG 01659 * Address : 0X5E 01660 * Bit Group Name: INT1_WU 01661 * Permission : RW 01662 *******************************************************************************/ 01663 typedef enum { 01664 LSM6DS3_ACC_GYRO_INT1_WU_DISABLED = 0x00, 01665 LSM6DS3_ACC_GYRO_INT1_WU_ENABLED = 0x20, 01666 } LSM6DS3_ACC_GYRO_INT1_WU_t; 01667 01668 /******************************************************************************* 01669 * Register : MD1_CFG 01670 * Address : 0X5E 01671 * Bit Group Name: INT1_SINGLE_TAP 01672 * Permission : RW 01673 *******************************************************************************/ 01674 typedef enum { 01675 LSM6DS3_ACC_GYRO_INT1_SINGLE_TAP_DISABLED = 0x00, 01676 LSM6DS3_ACC_GYRO_INT1_SINGLE_TAP_ENABLED = 0x40, 01677 } LSM6DS3_ACC_GYRO_INT1_SINGLE_TAP_t; 01678 01679 /******************************************************************************* 01680 * Register : MD1_CFG 01681 * Address : 0X5E 01682 * Bit Group Name: INT1_SLEEP 01683 * Permission : RW 01684 *******************************************************************************/ 01685 typedef enum { 01686 LSM6DS3_ACC_GYRO_INT1_SLEEP_DISABLED = 0x00, 01687 LSM6DS3_ACC_GYRO_INT1_SLEEP_ENABLED = 0x80, 01688 } LSM6DS3_ACC_GYRO_INT1_SLEEP_t; 01689 01690 /******************************************************************************* 01691 * Register : MD2_CFG 01692 * Address : 0X5F 01693 * Bit Group Name: INT2_TIMER 01694 * Permission : RW 01695 *******************************************************************************/ 01696 typedef enum { 01697 LSM6DS3_ACC_GYRO_INT2_TIMER_DISABLED = 0x00, 01698 LSM6DS3_ACC_GYRO_INT2_TIMER_ENABLED = 0x01, 01699 } LSM6DS3_ACC_GYRO_INT2_TIMER_t; 01700 01701 /******************************************************************************* 01702 * Register : MD2_CFG 01703 * Address : 0X5F 01704 * Bit Group Name: INT2_TILT 01705 * Permission : RW 01706 *******************************************************************************/ 01707 typedef enum { 01708 LSM6DS3_ACC_GYRO_INT2_TILT_DISABLED = 0x00, 01709 LSM6DS3_ACC_GYRO_INT2_TILT_ENABLED = 0x02, 01710 } LSM6DS3_ACC_GYRO_INT2_TILT_t; 01711 01712 /******************************************************************************* 01713 * Register : MD2_CFG 01714 * Address : 0X5F 01715 * Bit Group Name: INT2_6D 01716 * Permission : RW 01717 *******************************************************************************/ 01718 typedef enum { 01719 LSM6DS3_ACC_GYRO_INT2_6D_DISABLED = 0x00, 01720 LSM6DS3_ACC_GYRO_INT2_6D_ENABLED = 0x04, 01721 } LSM6DS3_ACC_GYRO_INT2_6D_t; 01722 01723 /******************************************************************************* 01724 * Register : MD2_CFG 01725 * Address : 0X5F 01726 * Bit Group Name: INT2_TAP 01727 * Permission : RW 01728 *******************************************************************************/ 01729 typedef enum { 01730 LSM6DS3_ACC_GYRO_INT2_TAP_DISABLED = 0x00, 01731 LSM6DS3_ACC_GYRO_INT2_TAP_ENABLED = 0x08, 01732 } LSM6DS3_ACC_GYRO_INT2_TAP_t; 01733 01734 /******************************************************************************* 01735 * Register : MD2_CFG 01736 * Address : 0X5F 01737 * Bit Group Name: INT2_FF 01738 * Permission : RW 01739 *******************************************************************************/ 01740 typedef enum { 01741 LSM6DS3_ACC_GYRO_INT2_FF_DISABLED = 0x00, 01742 LSM6DS3_ACC_GYRO_INT2_FF_ENABLED = 0x10, 01743 } LSM6DS3_ACC_GYRO_INT2_FF_t; 01744 01745 /******************************************************************************* 01746 * Register : MD2_CFG 01747 * Address : 0X5F 01748 * Bit Group Name: INT2_WU 01749 * Permission : RW 01750 *******************************************************************************/ 01751 typedef enum { 01752 LSM6DS3_ACC_GYRO_INT2_WU_DISABLED = 0x00, 01753 LSM6DS3_ACC_GYRO_INT2_WU_ENABLED = 0x20, 01754 } LSM6DS3_ACC_GYRO_INT2_WU_t; 01755 01756 /******************************************************************************* 01757 * Register : MD2_CFG 01758 * Address : 0X5F 01759 * Bit Group Name: INT2_SINGLE_TAP 01760 * Permission : RW 01761 *******************************************************************************/ 01762 typedef enum { 01763 LSM6DS3_ACC_GYRO_INT2_SINGLE_TAP_DISABLED = 0x00, 01764 LSM6DS3_ACC_GYRO_INT2_SINGLE_TAP_ENABLED = 0x40, 01765 } LSM6DS3_ACC_GYRO_INT2_SINGLE_TAP_t; 01766 01767 /******************************************************************************* 01768 * Register : MD2_CFG 01769 * Address : 0X5F 01770 * Bit Group Name: INT2_SLEEP 01771 * Permission : RW 01772 *******************************************************************************/ 01773 typedef enum { 01774 LSM6DS3_ACC_GYRO_INT2_SLEEP_DISABLED = 0x00, 01775 LSM6DS3_ACC_GYRO_INT2_SLEEP_ENABLED = 0x80, 01776 } LSM6DS3_ACC_GYRO_INT2_SLEEP_t; 01777 01778 #endif
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