HAN Solarboat / Mbed 2 deprecated SolarOnFoils_MainModule_20150518

version 1.0

Dependencies:   CMSIS_DSP_401 GPS MPU9150_DMP PID QuaternionMath Servo mbed

Fork of SolarOnFoils_MainModule_20150518 by Dannis Brugman

MCP23017.h@2:f6d058931b17, 2015-08-11 (annotated)

Committer:
Dannis_mbed
Date:
Tue Aug 11 08:38:55 2015 +0000
Revision:
2:f6d058931b17
Parent:
0:81b21910454e 
Test version mainmodule

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Dannis_mbed 0:81b21910454e 1 /* MCP23017 - drive the Microchip MCP23017 16-bit Port Extender using I2C
Dannis_mbed 0:81b21910454e 2 * Copyright (c) 2010 Wim Huiskamp, Romilly Cocking (original version for SPI)
Dannis_mbed 0:81b21910454e 3 *
Dannis_mbed 0:81b21910454e 4 * Released under the MIT License: http://mbed.org/license/mit
Dannis_mbed 0:81b21910454e 5 *
Dannis_mbed 0:81b21910454e 6 * version 0.2 Initial Release
Dannis_mbed 0:81b21910454e 7 * version 0.3 Cleaned up
Dannis_mbed 0:81b21910454e 8 * version 0.4 Fixed problem with _read method
Dannis_mbed 0:81b21910454e 9 * version 0.5 Added support for 'Banked' access to registers
Dannis_mbed 0:81b21910454e 10 */
Dannis_mbed 0:81b21910454e 11 #include "mbed.h"
Dannis_mbed 0:81b21910454e 12
Dannis_mbed 0:81b21910454e 13 #ifndef MCP23017_H
Dannis_mbed 0:81b21910454e 14 #define MCP23017_H
Dannis_mbed 0:81b21910454e 15
Dannis_mbed 0:81b21910454e 16 // All register addresses assume IOCON.BANK = 0 (POR default)
Dannis_mbed 0:81b21910454e 17 #define IODIRA 0x00
Dannis_mbed 0:81b21910454e 18 #define IODIRB 0x01
Dannis_mbed 0:81b21910454e 19 #define IPOLA 0x02
Dannis_mbed 0:81b21910454e 20 #define IPOLB 0x03
Dannis_mbed 0:81b21910454e 21 #define GPINTENA 0x04
Dannis_mbed 0:81b21910454e 22 #define GPINTENB 0x05
Dannis_mbed 0:81b21910454e 23 #define DEFVALA 0x06
Dannis_mbed 0:81b21910454e 24 #define DEFVALB 0x07
Dannis_mbed 0:81b21910454e 25 #define INTCONA 0x08
Dannis_mbed 0:81b21910454e 26 #define INTCONB 0x09
Dannis_mbed 0:81b21910454e 27 #define IOCONA 0x0A
Dannis_mbed 0:81b21910454e 28 #define IOCONB 0x0B
Dannis_mbed 0:81b21910454e 29 #define GPPUA 0x0C
Dannis_mbed 0:81b21910454e 30 #define GPPUB 0x0D
Dannis_mbed 0:81b21910454e 31 #define INTFA 0x0E
Dannis_mbed 0:81b21910454e 32 #define INTFB 0x0F
Dannis_mbed 0:81b21910454e 33 #define INTCAPA 0x10
Dannis_mbed 0:81b21910454e 34 #define INTCAPB 0x11
Dannis_mbed 0:81b21910454e 35 #define GPIOA 0x12
Dannis_mbed 0:81b21910454e 36 #define GPIOB 0x13
Dannis_mbed 0:81b21910454e 37 #define OLATA 0x14
Dannis_mbed 0:81b21910454e 38 #define OLATB 0x15
Dannis_mbed 0:81b21910454e 39
Dannis_mbed 0:81b21910454e 40 // The following register addresses assume IOCON.BANK = 1
Dannis_mbed 0:81b21910454e 41 #define IODIRA_BNK 0x00
Dannis_mbed 0:81b21910454e 42 #define IPOLA_BNK 0x01
Dannis_mbed 0:81b21910454e 43 #define GPINTENA_BNK 0x02
Dannis_mbed 0:81b21910454e 44 #define DEFVALA_BNK 0x03
Dannis_mbed 0:81b21910454e 45 #define INTCONA_BNK 0x04
Dannis_mbed 0:81b21910454e 46 #define IOCONA_BNK 0x05
Dannis_mbed 0:81b21910454e 47 #define GPPUA_BNK 0x06
Dannis_mbed 0:81b21910454e 48 #define INTFA_BNK 0x07
Dannis_mbed 0:81b21910454e 49 #define INTCAPA_BNK 0x08
Dannis_mbed 0:81b21910454e 50 #define GPIOA_BNK 0x09
Dannis_mbed 0:81b21910454e 51 #define OLATA_BNK 0x0A
Dannis_mbed 0:81b21910454e 52
Dannis_mbed 0:81b21910454e 53 #define IODIRB_BNK 0x10
Dannis_mbed 0:81b21910454e 54 #define IPOLB_BNK 0x11
Dannis_mbed 0:81b21910454e 55 #define GPINTENB_BNK 0x12
Dannis_mbed 0:81b21910454e 56 #define DEFVALB_BNK 0x13
Dannis_mbed 0:81b21910454e 57 #define INTCONB_BNK 0x14
Dannis_mbed 0:81b21910454e 58 #define IOCONB_BNK 0x15
Dannis_mbed 0:81b21910454e 59 #define GPPUB_BNK 0x16
Dannis_mbed 0:81b21910454e 60 #define INTFB_BNK 0x17
Dannis_mbed 0:81b21910454e 61 #define INTCAPB_BNK 0x18
Dannis_mbed 0:81b21910454e 62 #define GPIOB_BNK 0x19
Dannis_mbed 0:81b21910454e 63 #define OLATB_BNK 0x1A
Dannis_mbed 0:81b21910454e 64
Dannis_mbed 0:81b21910454e 65 // This array allows structured access to Port_A and Port_B registers for both bankModes
Dannis_mbed 0:81b21910454e 66 const int IODIR_AB[2][2] = {{IODIRA, IODIRB}, {IODIRA_BNK, IODIRB_BNK}};
Dannis_mbed 0:81b21910454e 67 const int IPOL_AB[2][2] = {{IPOLA, IPOLB}, {IPOLA_BNK, IPOLB_BNK}};
Dannis_mbed 0:81b21910454e 68 const int GPINTEN_AB[2][2] = {{GPINTENA, GPINTENB}, {GPINTENA_BNK, GPINTENB_BNK}};
Dannis_mbed 0:81b21910454e 69 const int DEFVAL_AB[2][2] = {{DEFVALA, DEFVALB}, {DEFVALA_BNK, DEFVALB_BNK}};
Dannis_mbed 0:81b21910454e 70 const int INTCON_AB[2][2] = {{INTCONA, INTCONB}, {INTCONA_BNK, INTCONB_BNK}};
Dannis_mbed 0:81b21910454e 71 const int IOCON_AB[2][2] = {{IOCONA, IOCONB}, {IOCONA_BNK, IOCONB_BNK}};
Dannis_mbed 0:81b21910454e 72 const int GPPU_AB[2][2] = {{GPPUA, GPPUB}, {GPPUA_BNK, GPPUB_BNK}};
Dannis_mbed 0:81b21910454e 73 const int INTF_AB[2][2] = {{INTFA, INTFB}, {INTFA_BNK, INTFB_BNK}};
Dannis_mbed 0:81b21910454e 74 const int INTCAP_AB[2][2] = {{INTCAPA, INTCAPB}, {INTCAPA_BNK, INTCAPB_BNK}};
Dannis_mbed 0:81b21910454e 75 const int GPIO_AB[2][2] = {{GPIOA, GPIOB}, {GPIOA_BNK, GPIOB_BNK}};
Dannis_mbed 0:81b21910454e 76 const int OLAT_AB[2][2] = {{OLATA, OLATB}, {OLATA_BNK, OLATB_BNK}};
Dannis_mbed 0:81b21910454e 77
Dannis_mbed 0:81b21910454e 78
Dannis_mbed 0:81b21910454e 79 // Control settings
Dannis_mbed 0:81b21910454e 80 #define IOCON_BANK 0x80 // Banked registers for Port A and B
Dannis_mbed 0:81b21910454e 81 #define IOCON_BYTE_MODE 0x20 // Disables sequential operation, Address Ptr does not increment
Dannis_mbed 0:81b21910454e 82 // If Disabled and Bank = 0, operations toggle between Port A and B registers
Dannis_mbed 0:81b21910454e 83 // If Disabled and Bank = 1, operations do not increment registeraddress
Dannis_mbed 0:81b21910454e 84 #define IOCON_HAEN 0x08 // Hardware address enable
Dannis_mbed 0:81b21910454e 85
Dannis_mbed 0:81b21910454e 86 #define INTERRUPT_POLARITY_BIT 0x02
Dannis_mbed 0:81b21910454e 87 #define INTERRUPT_MIRROR_BIT 0x40
Dannis_mbed 0:81b21910454e 88
Dannis_mbed 0:81b21910454e 89 #define PORT_DIR_OUT 0x00
Dannis_mbed 0:81b21910454e 90 #define PORT_DIR_IN 0xFF
Dannis_mbed 0:81b21910454e 91
Dannis_mbed 0:81b21910454e 92 enum Polarity { ACTIVE_LOW , ACTIVE_HIGH };
Dannis_mbed 0:81b21910454e 93 enum Port { PORT_A=0, PORT_B=1 };
Dannis_mbed 0:81b21910454e 94 enum Bank { NOT_BNK=0, BNK=1 };
Dannis_mbed 0:81b21910454e 95
Dannis_mbed 0:81b21910454e 96 class MCP23017 {
Dannis_mbed 0:81b21910454e 97 public:
Dannis_mbed 0:81b21910454e 98 /** Create an MCP23017 object connected to the specified I2C object and using the specified deviceAddress
Dannis_mbed 0:81b21910454e 99 *
Dannis_mbed 0:81b21910454e 100 * @param I2C &i2c the I2C port to connect to
Dannis_mbed 0:81b21910454e 101 * @param char deviceAddress the address of the MCP23017
Dannis_mbed 0:81b21910454e 102 */
Dannis_mbed 0:81b21910454e 103 MCP23017(I2C &i2c, char deviceAddress);
Dannis_mbed 0:81b21910454e 104
Dannis_mbed 0:81b21910454e 105 /** Set I/O direction of specified MCP23017 Port
Dannis_mbed 0:81b21910454e 106 *
Dannis_mbed 0:81b21910454e 107 * @param Port Port address (Port_A or Port_B)
Dannis_mbed 0:81b21910454e 108 * @param char direction pin direction (0 = output, 1 = input)
Dannis_mbed 0:81b21910454e 109 */
Dannis_mbed 0:81b21910454e 110 void direction(Port port, char direction);
Dannis_mbed 0:81b21910454e 111
Dannis_mbed 0:81b21910454e 112 /** Set Pull-Up Resistors on specified MCP23017 Port
Dannis_mbed 0:81b21910454e 113 *
Dannis_mbed 0:81b21910454e 114 * @param Port Port address (Port_A or Port_B)
Dannis_mbed 0:81b21910454e 115 * @param char offOrOn per pin (0 = off, 1 = on)
Dannis_mbed 0:81b21910454e 116 */
Dannis_mbed 0:81b21910454e 117 void configurePullUps(Port port, char offOrOn);
Dannis_mbed 0:81b21910454e 118
Dannis_mbed 0:81b21910454e 119 void configureBanked(Bank bankmode);
Dannis_mbed 0:81b21910454e 120 void interruptEnable(Port port, char interruptsEnabledMask);
Dannis_mbed 0:81b21910454e 121 void interruptPolarity(Polarity polarity);
Dannis_mbed 0:81b21910454e 122 void mirrorInterrupts(bool mirror);
Dannis_mbed 0:81b21910454e 123 void defaultValue(Port port, char valuesToCompare);
Dannis_mbed 0:81b21910454e 124 void interruptControl(Port port, char interruptControlBits);
Dannis_mbed 0:81b21910454e 125
Dannis_mbed 0:81b21910454e 126 /** Read from specified MCP23017 Port
Dannis_mbed 0:81b21910454e 127 *
Dannis_mbed 0:81b21910454e 128 * @param Port Port address (Port_A or Port_B)
Dannis_mbed 0:81b21910454e 129 * @returns data from Port
Dannis_mbed 0:81b21910454e 130 */
Dannis_mbed 0:81b21910454e 131 char read(Port port);
Dannis_mbed 0:81b21910454e 132
Dannis_mbed 0:81b21910454e 133 /** Write to specified MCP23017 Port
Dannis_mbed 0:81b21910454e 134 *
Dannis_mbed 0:81b21910454e 135 * @param Port Port address (Port_A or Port_B)
Dannis_mbed 0:81b21910454e 136 * @param char byte data to write
Dannis_mbed 0:81b21910454e 137 */
Dannis_mbed 0:81b21910454e 138 void write(Port port, char byte);
Dannis_mbed 0:81b21910454e 139
Dannis_mbed 0:81b21910454e 140 protected:
Dannis_mbed 0:81b21910454e 141 I2C &_i2c;
Dannis_mbed 0:81b21910454e 142 char _readOpcode;
Dannis_mbed 0:81b21910454e 143 char _writeOpcode;
Dannis_mbed 0:81b21910454e 144 Bank _bankMode;
Dannis_mbed 0:81b21910454e 145
Dannis_mbed 0:81b21910454e 146 /** Init MCP23017
Dannis_mbed 0:81b21910454e 147 *
Dannis_mbed 0:81b21910454e 148 * @param
Dannis_mbed 0:81b21910454e 149 * @returns
Dannis_mbed 0:81b21910454e 150 */
Dannis_mbed 0:81b21910454e 151 void _init();
Dannis_mbed 0:81b21910454e 152
Dannis_mbed 0:81b21910454e 153 /** Write to specified MCP23017 register
Dannis_mbed 0:81b21910454e 154 *
Dannis_mbed 0:81b21910454e 155 * @param char address the internal registeraddress of the MCP23017
Dannis_mbed 0:81b21910454e 156 */
Dannis_mbed 0:81b21910454e 157 void _write(char address, char byte);
Dannis_mbed 0:81b21910454e 158
Dannis_mbed 0:81b21910454e 159 /** Read from specified MCP23017 register
Dannis_mbed 0:81b21910454e 160 *
Dannis_mbed 0:81b21910454e 161 * @param char address the internal registeraddress of the MCP23017
Dannis_mbed 0:81b21910454e 162 * @returns data from register
Dannis_mbed 0:81b21910454e 163 */
Dannis_mbed 0:81b21910454e 164 char _read(char address);
Dannis_mbed 0:81b21910454e 165 };
Dannis_mbed 0:81b21910454e 166
Dannis_mbed 0:81b21910454e 167 #endif