Gymtrack / RFIDTestNFC

interrupt handling

Dependencies:  

interruptStuff.cpp@12:336524cf63de, 2015-04-10 (annotated)

Committer:
soumi_ghsoh
Date:
Fri Apr 10 23:16:44 2015 +0000
Revision:
12:336524cf63de
Parent:
6:3c510c297e2f 
PollNFC(), FindNFC(), tagFound

Who changed what in which revision?

UserRevisionLine numberNew contents of line
soumi_ghsoh 6:3c510c297e2f 1 ///* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
soumi_ghsoh 6:3c510c297e2f 2 // Filename: interruptHandler.cpp
soumi_ghsoh 6:3c510c297e2f 3 // Description: Handles interrupt from TRF7970
soumi_ghsoh 6:3c510c297e2f 4 // Copyright (C) 2015 Gymtrack, Inc.
soumi_ghsoh 6:3c510c297e2f 5 // Author: Ron Clough
soumi_ghsoh 6:3c510c297e2f 6 // Date: 2015-03-03
soumi_ghsoh 6:3c510c297e2f 7 //
soumi_ghsoh 6:3c510c297e2f 8 // Changes:
soumi_ghsoh 6:3c510c297e2f 9 // Rev Date Who Details
soumi_ghsoh 6:3c510c297e2f 10 // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
soumi_ghsoh 6:3c510c297e2f 11 // 0.0 2015-03-03 RWC Original version.
soumi_ghsoh 6:3c510c297e2f 12 //
soumi_ghsoh 6:3c510c297e2f 13 //* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
soumi_ghsoh 6:3c510c297e2f 14 //
soumi_ghsoh 6:3c510c297e2f 15 //#include "mbed.h"
soumi_ghsoh 6:3c510c297e2f 16 ////#include "main.h"
soumi_ghsoh 6:3c510c297e2f 17 //#include "interruptStuff.h"
soumi_ghsoh 6:3c510c297e2f 18 //#include "readerComm.h"
soumi_ghsoh 6:3c510c297e2f 19 //
soumi_ghsoh 6:3c510c297e2f 20 //InterruptIn readerInt(p7); // Interrupt from TRF7970
soumi_ghsoh 6:3c510c297e2f 21 ////DigitalIn irqPin(p7, PullDown);
soumi_ghsoh 6:3c510c297e2f 22 //extern DigitalOut debug1LED; // "Debug" LED
soumi_ghsoh 6:3c510c297e2f 23 //extern DigitalOut debug2LED;
soumi_ghsoh 6:3c510c297e2f 24 //extern DigitalOut heartbeatLED;
soumi_ghsoh 6:3c510c297e2f 25 //extern DigitalOut testPin;
soumi_ghsoh 6:3c510c297e2f 26 //extern Serial pc; // main.cpp
soumi_ghsoh 6:3c510c297e2f 27 //extern DigitalOut ISO15693LED;
soumi_ghsoh 6:3c510c297e2f 28 //extern uint8_t irqRegister; // Interrupt register (main.cpp)
soumi_ghsoh 6:3c510c297e2f 29 //extern uint8_t buf[300];
soumi_ghsoh 6:3c510c297e2f 30 //extern int16_t nfc_state;
soumi_ghsoh 6:3c510c297e2f 31 //extern uint8_t nfc_protocol;
soumi_ghsoh 6:3c510c297e2f 32 //extern uint8_t active;
soumi_ghsoh 6:3c510c297e2f 33 //extern int8_t rxtxState;
soumi_ghsoh 6:3c510c297e2f 34 //extern uint8_t rxErrorFlag;
soumi_ghsoh 6:3c510c297e2f 35 //extern uint8_t tagFlag;
soumi_ghsoh 6:3c510c297e2f 36 //volatile extern uint8_t irqFlag;
soumi_ghsoh 6:3c510c297e2f 37 //extern uint8_t irqCount;
soumi_ghsoh 6:3c510c297e2f 38 //
soumi_ghsoh 6:3c510c297e2f 39 //extern uint8_t buffer;
soumi_ghsoh 6:3c510c297e2f 40 //
soumi_ghsoh 6:3c510c297e2f 41 //extern uint8_t debugBuffer[1000]; // Capture data for analysis
soumi_ghsoh 6:3c510c297e2f 42 //extern uint8_t bufIdx;
soumi_ghsoh 6:3c510c297e2f 43 //
soumi_ghsoh 6:3c510c297e2f 44 //void trf797xSetupIrq(void)
soumi_ghsoh 6:3c510c297e2f 45 //// * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
soumi_ghsoh 6:3c510c297e2f 46 //// trf797xSetupIrq()
soumi_ghsoh 6:3c510c297e2f 47 //// Description: Interrupt from TRF7970 appears at pin 7 of
soumi_ghsoh 6:3c510c297e2f 48 //// on nRF51-DK eval board. trf7970IrqHandler() is called
soumi_ghsoh 6:3c510c297e2f 49 //// when a rising edge is detected.
soumi_ghsoh 6:3c510c297e2f 50 //// * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
soumi_ghsoh 6:3c510c297e2f 51 //{
soumi_ghsoh 6:3c510c297e2f 52 // readerInt.rise(&trf797xIrqHandler); // Interrupt on rising edge, call trf7970IrqHandler()
soumi_ghsoh 6:3c510c297e2f 53 // readerInt.disable_irq();
soumi_ghsoh 6:3c510c297e2f 54 //} // End of trf797xSetupIrq()
soumi_ghsoh 6:3c510c297e2f 55 //
soumi_ghsoh 6:3c510c297e2f 56 //void trf797xReadIrqStatus(uint8_t *buffer)
soumi_ghsoh 6:3c510c297e2f 57 //// * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
soumi_ghsoh 6:3c510c297e2f 58 //// trf797xReadIrqStatus()
soumi_ghsoh 6:3c510c297e2f 59 //// * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
soumi_ghsoh 6:3c510c297e2f 60 //{
soumi_ghsoh 6:3c510c297e2f 61 // *buffer = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 62 // *(buffer + 1) = IRQ_MASK;
soumi_ghsoh 6:3c510c297e2f 63 // trf797xReadContinuous(buffer, 2);
soumi_ghsoh 6:3c510c297e2f 64 //} // End of trf797xReadIrqStatus()
soumi_ghsoh 6:3c510c297e2f 65 //
soumi_ghsoh 6:3c510c297e2f 66 //void trf797xResetIrqStatus(void)
soumi_ghsoh 6:3c510c297e2f 67 //// * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
soumi_ghsoh 6:3c510c297e2f 68 //// trf797xResetIrqStatus()
soumi_ghsoh 6:3c510c297e2f 69 //// * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
soumi_ghsoh 6:3c510c297e2f 70 //{
soumi_ghsoh 6:3c510c297e2f 71 // uint8_t irq_status[4];
soumi_ghsoh 6:3c510c297e2f 72 //
soumi_ghsoh 6:3c510c297e2f 73 // irq_status[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 74 // irq_status[1] = IRQ_MASK;
soumi_ghsoh 6:3c510c297e2f 75 // trf797xReadContinuous(irq_status, 2); // Read second register as dummy read
soumi_ghsoh 6:3c510c297e2f 76 //} // End of trf797xResetIrqStatus()
soumi_ghsoh 6:3c510c297e2f 77 //
soumi_ghsoh 6:3c510c297e2f 78 //
soumi_ghsoh 6:3c510c297e2f 79 //
soumi_ghsoh 6:3c510c297e2f 80 ///*======================================nfc mode SG
soumi_ghsoh 6:3c510c297e2f 81 //void trf797xNfcModeIsr(uint8_t *Register)
soumi_ghsoh 6:3c510c297e2f 82 //// * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
soumi_ghsoh 6:3c510c297e2f 83 //// trf797xNfcModeIsr()
soumi_ghsoh 6:3c510c297e2f 84 //// bit0 - RF collision avoidance error
soumi_ghsoh 6:3c510c297e2f 85 //// bit1 - RF collision avoidance OK
soumi_ghsoh 6:3c510c297e2f 86 //// bit2 - Change in RF field level
soumi_ghsoh 6:3c510c297e2f 87 //// bit3 - SDD OK
soumi_ghsoh 6:3c510c297e2f 88 //// bit4 - Communication error
soumi_ghsoh 6:3c510c297e2f 89 //// bit5 - FIFO high/low
soumi_ghsoh 6:3c510c297e2f 90 //// bit6 - RX
soumi_ghsoh 6:3c510c297e2f 91 //// bit7 - TX
soumi_ghsoh 6:3c510c297e2f 92 ////
soumi_ghsoh 6:3c510c297e2f 93 //// irqRegister is used for signaling to the protocol functions
soumi_ghsoh 6:3c510c297e2f 94 //// irqRegister = 0x00 - OK
soumi_ghsoh 6:3c510c297e2f 95 //// irqRegister = 0x01 - progress
soumi_ghsoh 6:3c510c297e2f 96 //// irqRegister = 0x02 - error
soumi_ghsoh 6:3c510c297e2f 97 //// irqRegister = 0xFF - end of RX
soumi_ghsoh 6:3c510c297e2f 98 //// * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
soumi_ghsoh 6:3c510c297e2f 99 //{
soumi_ghsoh 6:3c510c297e2f 100 // if (*Register == BIT0) {
soumi_ghsoh 6:3c510c297e2f 101 // irqRegister = 0x02;
soumi_ghsoh 6:3c510c297e2f 102 // }
soumi_ghsoh 6:3c510c297e2f 103 // else if (*Register == BIT1) {
soumi_ghsoh 6:3c510c297e2f 104 // irqRegister = 0x00;
soumi_ghsoh 6:3c510c297e2f 105 // }
soumi_ghsoh 6:3c510c297e2f 106 // else if (*Register == BIT3) {
soumi_ghsoh 6:3c510c297e2f 107 // irqRegister = 0x00;
soumi_ghsoh 6:3c510c297e2f 108 // }
soumi_ghsoh 6:3c510c297e2f 109 // else if ((*Register & BIT4) == BIT4) {
soumi_ghsoh 6:3c510c297e2f 110 // *Register = RX_SPECIAL_SETTINGS; // Check filter and gain
soumi_ghsoh 6:3c510c297e2f 111 // trf797xReadSingle(Register, 1);
soumi_ghsoh 6:3c510c297e2f 112 // trf797xStopDecoders();
soumi_ghsoh 6:3c510c297e2f 113 // irqRegister = 0x02;
soumi_ghsoh 6:3c510c297e2f 114 // }
soumi_ghsoh 6:3c510c297e2f 115 // else if (*Register == BIT7) { // TX complete
soumi_ghsoh 6:3c510c297e2f 116 // irqRegister = 0x00;
soumi_ghsoh 6:3c510c297e2f 117 // trf797xReset();
soumi_ghsoh 6:3c510c297e2f 118 // }
soumi_ghsoh 6:3c510c297e2f 119 // else if (*Register == 0x40 || *Register == 0x44) { // RX flag means that EOF has been received and
soumi_ghsoh 6:3c510c297e2f 120 // // the number of unread bytes is in FIFOstatus register
soumi_ghsoh 6:3c510c297e2f 121 // *Register = RX_SPECIAL_SETTINGS; // Check filter and gain
soumi_ghsoh 6:3c510c297e2f 122 // trf797xReadSingle(Register, 1);
soumi_ghsoh 6:3c510c297e2f 123 // *Register = FIFO_CONTROL;
soumi_ghsoh 6:3c510c297e2f 124 // trf797xReadSingle(Register, 1);
soumi_ghsoh 6:3c510c297e2f 125 // *Register = 0x7F & *Register;
soumi_ghsoh 6:3c510c297e2f 126 // buf[nfc_state] = FIFO; // Write the received bytes to the correct place in the buffer
soumi_ghsoh 6:3c510c297e2f 127 // trf797xReadContinuous(&buf[nfc_state], *Register);
soumi_ghsoh 6:3c510c297e2f 128 // nfc_state = nfc_state + *Register;
soumi_ghsoh 6:3c510c297e2f 129 // trf797xReset(); // Reset the FIFO after last byte has been read out
soumi_ghsoh 6:3c510c297e2f 130 // irqRegister = 0xFF; // Signal to the receive function that these are the last bytes
soumi_ghsoh 6:3c510c297e2f 131 // trf797xResetIrqStatus();
soumi_ghsoh 6:3c510c297e2f 132 // }
soumi_ghsoh 6:3c510c297e2f 133 // else if ((*Register == 0x60) || (*Register == 0x64)) { // RX and FIFO interrupt
soumi_ghsoh 6:3c510c297e2f 134 // irqRegister = 0x01;
soumi_ghsoh 6:3c510c297e2f 135 // }
soumi_ghsoh 6:3c510c297e2f 136 // else if (*Register == 0x48) { // SDD complete
soumi_ghsoh 6:3c510c297e2f 137 // irqRegister = 0x00;
soumi_ghsoh 6:3c510c297e2f 138 // }
soumi_ghsoh 6:3c510c297e2f 139 //} // End of trf797xNfcModeIsr()
soumi_ghsoh 6:3c510c297e2f 140 //*/
rwclough 2:bd5afc5aa139 141 //
soumi_ghsoh 6:3c510c297e2f 142 ///*==============================================================================target SG
soumi_ghsoh 6:3c510c297e2f 143 //void trf797xTargetIsr(uint8_t *Register)
soumi_ghsoh 6:3c510c297e2f 144 //// * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
soumi_ghsoh 6:3c510c297e2f 145 //// trf797xTargetIsr()
soumi_ghsoh 6:3c510c297e2f 146 //// * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
soumi_ghsoh 6:3c510c297e2f 147 //{
soumi_ghsoh 6:3c510c297e2f 148 // uint8_t command, i;
soumi_ghsoh 6:3c510c297e2f 149 //
soumi_ghsoh 6:3c510c297e2f 150 // if (*Register == 0x48) {
soumi_ghsoh 6:3c510c297e2f 151 // TargetProtocol:
soumi_ghsoh 6:3c510c297e2f 152 // // Determine the NFC target protocol
soumi_ghsoh 6:3c510c297e2f 153 // command = NFC_TARGET_PROTOCOL;
soumi_ghsoh 6:3c510c297e2f 154 // trf797xReadSingle(&command, 1); //read the NFCtargetprotocol register
soumi_ghsoh 6:3c510c297e2f 155 // command &= 0x3F;
soumi_ghsoh 6:3c510c297e2f 156 // buf[50] = ISO_CONTROL;
soumi_ghsoh 6:3c510c297e2f 157 // if (command == 0x09) {
soumi_ghsoh 6:3c510c297e2f 158 // nfc_protocol = 0x01;
soumi_ghsoh 6:3c510c297e2f 159 // *Register = FIFO_CONTROL;
soumi_ghsoh 6:3c510c297e2f 160 // trf797xReadSingle(Register, 1); // Determine the number of bytes left in FIFO
soumi_ghsoh 6:3c510c297e2f 161 // *Register = 0x7F & *Register;
soumi_ghsoh 6:3c510c297e2f 162 // buf[nfc_state] = FIFO; // Write the received bytes to the correct place in the buffer
soumi_ghsoh 6:3c510c297e2f 163 // trf797xReadContinuous(&buf[nfc_state], *Register);
soumi_ghsoh 6:3c510c297e2f 164 // nfc_state = nfc_state + *Register;
soumi_ghsoh 6:3c510c297e2f 165 // irqRegister = 0xFF;
soumi_ghsoh 6:3c510c297e2f 166 // }
soumi_ghsoh 6:3c510c297e2f 167 // else {
soumi_ghsoh 6:3c510c297e2f 168 // *Register = FIFO_CONTROL;
soumi_ghsoh 6:3c510c297e2f 169 // trf797xReadSingle(Register, 1); // Determine the number of bytes left in FIFO
soumi_ghsoh 6:3c510c297e2f 170 // *Register = 0x7F & *Register;
soumi_ghsoh 6:3c510c297e2f 171 // buf[nfc_state] = FIFO; // Write the received bytes to the correct place in the buffer
soumi_ghsoh 6:3c510c297e2f 172 // trf797xReadContinuous(&buf[nfc_state], *Register);
soumi_ghsoh 6:3c510c297e2f 173 // nfc_state = nfc_state + *Register;
soumi_ghsoh 6:3c510c297e2f 174 // irqRegister = 0xFF;
soumi_ghsoh 6:3c510c297e2f 175 // if ((command == 0x01)) { // 14443A - active
soumi_ghsoh 6:3c510c297e2f 176 // buf[51] = NFC106AC;
soumi_ghsoh 6:3c510c297e2f 177 // trf797xWriteSingle(&buf[50], 2);
soumi_ghsoh 6:3c510c297e2f 178 // nfc_protocol = 0x02;
soumi_ghsoh 6:3c510c297e2f 179 // active = 0xFF;
soumi_ghsoh 6:3c510c297e2f 180 // }
soumi_ghsoh 6:3c510c297e2f 181 // else if (command == 0x05) { // 14443B - tag emulation
soumi_ghsoh 6:3c510c297e2f 182 // buf[51] = TAG14443B;
soumi_ghsoh 6:3c510c297e2f 183 // trf797xWriteSingle(&buf[50], 2);
soumi_ghsoh 6:3c510c297e2f 184 // nfc_protocol = 0x07;
soumi_ghsoh 6:3c510c297e2f 185 // active = 0x00;
soumi_ghsoh 6:3c510c297e2f 186 // }
soumi_ghsoh 6:3c510c297e2f 187 // else if (command == 0x12) {
soumi_ghsoh 6:3c510c297e2f 188 // if(buf[1] == 0x06) { // Felica 212 - passive
soumi_ghsoh 6:3c510c297e2f 189 // buf[51] = NFC212PA;
soumi_ghsoh 6:3c510c297e2f 190 // trf797xWriteSingle(&buf[50], 2);
soumi_ghsoh 6:3c510c297e2f 191 // nfc_protocol = 0x03;
soumi_ghsoh 6:3c510c297e2f 192 // active = 0x00;
soumi_ghsoh 6:3c510c297e2f 193 // }
soumi_ghsoh 6:3c510c297e2f 194 // else { // Felica 212 - active
soumi_ghsoh 6:3c510c297e2f 195 // buf[51] = NFC212AC;
soumi_ghsoh 6:3c510c297e2f 196 // trf797xWriteSingle(&buf[50], 2);
soumi_ghsoh 6:3c510c297e2f 197 // nfc_protocol = 0x04;
soumi_ghsoh 6:3c510c297e2f 198 // active = 0xFF;
soumi_ghsoh 6:3c510c297e2f 199 // }
soumi_ghsoh 6:3c510c297e2f 200 // } // if (command == 0x12)
soumi_ghsoh 6:3c510c297e2f 201 // else if (command == 0x13) {
soumi_ghsoh 6:3c510c297e2f 202 // if(buf[1] == 0x06) { //Felica 424 - passive
soumi_ghsoh 6:3c510c297e2f 203 // buf[51] = NFC424PA;
soumi_ghsoh 6:3c510c297e2f 204 // trf797xWriteSingle(&buf[50], 2);
soumi_ghsoh 6:3c510c297e2f 205 // nfc_protocol = 0x05;
soumi_ghsoh 6:3c510c297e2f 206 // active = 0x00;
soumi_ghsoh 6:3c510c297e2f 207 // }
soumi_ghsoh 6:3c510c297e2f 208 // else { // Felica 424 - active
soumi_ghsoh 6:3c510c297e2f 209 // buf[51] = NFC424AC;
soumi_ghsoh 6:3c510c297e2f 210 // trf797xWriteSingle(&buf[50], 2);
soumi_ghsoh 6:3c510c297e2f 211 // nfc_protocol = 0x06;
soumi_ghsoh 6:3c510c297e2f 212 // active = 0xFF;
soumi_ghsoh 6:3c510c297e2f 213 // } // if (buf[1] == 0x06)
soumi_ghsoh 6:3c510c297e2f 214 // } // if (command == 0x13)
soumi_ghsoh 6:3c510c297e2f 215 // } // if (command == 0x09)
soumi_ghsoh 6:3c510c297e2f 216 // } // if (*Register == 0x48)
soumi_ghsoh 6:3c510c297e2f 217 // else if (*Register == 0x60) {
soumi_ghsoh 6:3c510c297e2f 218 // irqRegister = 0x01;
soumi_ghsoh 6:3c510c297e2f 219 // buf[nfc_state] = FIFO;
soumi_ghsoh 6:3c510c297e2f 220 // trf797xReadContinuous(&buf[nfc_state], FIFO_MORE); // Read FIFO_MORE bytes from FIFO
soumi_ghsoh 6:3c510c297e2f 221 // nfc_state = nfc_state + FIFO_MORE;
soumi_ghsoh 6:3c510c297e2f 222 // trf797xResetIrqStatus();
soumi_ghsoh 6:3c510c297e2f 223 // }
soumi_ghsoh 6:3c510c297e2f 224 // else if ((*Register & BIT3) == BIT3) { // SDD finished
soumi_ghsoh 6:3c510c297e2f 225 // irqRegister = 0xFF;
soumi_ghsoh 6:3c510c297e2f 226 // for(i = 0; i < 255; i++);
soumi_ghsoh 6:3c510c297e2f 227 // nfc_protocol = 0x01;
soumi_ghsoh 6:3c510c297e2f 228 // trf797xReset();
soumi_ghsoh 6:3c510c297e2f 229 // trf797xStopDecoders();
soumi_ghsoh 6:3c510c297e2f 230 // trf797xRunDecoders();
soumi_ghsoh 6:3c510c297e2f 231 // }
soumi_ghsoh 6:3c510c297e2f 232 // else if (*Register == 0x44) {
soumi_ghsoh 6:3c510c297e2f 233 // trf797xReadIrqStatus(Register);
soumi_ghsoh 6:3c510c297e2f 234 // if (*Register == 0x40) {
soumi_ghsoh 6:3c510c297e2f 235 // goto TargetProtocol;
soumi_ghsoh 6:3c510c297e2f 236 // }
soumi_ghsoh 6:3c510c297e2f 237 // else if (*Register == 0x00) {
soumi_ghsoh 6:3c510c297e2f 238 // goto RFfieldChange;
soumi_ghsoh 6:3c510c297e2f 239 // }
soumi_ghsoh 6:3c510c297e2f 240 // }
soumi_ghsoh 6:3c510c297e2f 241 // else if (*Register == BIT2) { // RF field change
soumi_ghsoh 6:3c510c297e2f 242 // RFfieldChange:
soumi_ghsoh 6:3c510c297e2f 243 // trf797xReset();
soumi_ghsoh 6:3c510c297e2f 244 // trf797xStopDecoders();
soumi_ghsoh 6:3c510c297e2f 245 // trf797xRunDecoders();
soumi_ghsoh 6:3c510c297e2f 246 // }
soumi_ghsoh 6:3c510c297e2f 247 // trf797xResetIrqStatus();
soumi_ghsoh 6:3c510c297e2f 248 //} // End of trf797xTargetIsr()
soumi_ghsoh 6:3c510c297e2f 249 //*/
soumi_ghsoh 6:3c510c297e2f 250 //void trf797xISR(uint8_t *irq_status)
soumi_ghsoh 6:3c510c297e2f 251 //// * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
soumi_ghsoh 6:3c510c297e2f 252 //// trf797xISR()
soumi_ghsoh 6:3c510c297e2f 253 //// Description: The Interrupt Handler determines how the IRQ should
soumi_ghsoh 6:3c510c297e2f 254 //// be handled. The Trf797x IRQ status register is read
soumi_ghsoh 6:3c510c297e2f 255 //// to determine the cause of the IRQ.
soumi_ghsoh 6:3c510c297e2f 256 //// Conditions are checked and appropriate actions taken.
soumi_ghsoh 6:3c510c297e2f 257 //// * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
soumi_ghsoh 6:3c510c297e2f 258 //{
soumi_ghsoh 6:3c510c297e2f 259 //
soumi_ghsoh 6:3c510c297e2f 260 //debug2LED = LED_ON;
soumi_ghsoh 6:3c510c297e2f 261 //printf(" IRQ_STATUS %d \r\n",irq_status[0]);
soumi_ghsoh 6:3c510c297e2f 262 // printf(" IRQ_MASK %d \r\n",irq_status[1]);
soumi_ghsoh 6:3c510c297e2f 263 // if (*irq_status == 0xA0) { printf( "BIT5 and BIT7, TX active and only 3 bytes left in FIFO \r\n"); // BIT5 and BIT7, TX active and only 3 bytes left in FIFO
soumi_ghsoh 6:3c510c297e2f 264 // irqRegister = 0x00;
soumi_ghsoh 6:3c510c297e2f 265 // }
soumi_ghsoh 6:3c510c297e2f 266 // else if (*irq_status == BIT7) { printf( " TX complete \r\n"); // TX complete // always comes here SG
soumi_ghsoh 6:3c510c297e2f 267 //
soumi_ghsoh 6:3c510c297e2f 268 // irqRegister = 0x00;
soumi_ghsoh 6:3c510c297e2f 269 // trf797xReset(); // Reset the FIFO after TX
soumi_ghsoh 6:3c510c297e2f 270 // }
soumi_ghsoh 6:3c510c297e2f 271 // else if ((*irq_status & BIT1) == BIT1) {printf( "Collision error \r\n"); // Collision error // comes here when tag is detected SG
soumi_ghsoh 6:3c510c297e2f 272 //
soumi_ghsoh 6:3c510c297e2f 273 // irqRegister = 0x02; // RX complete
soumi_ghsoh 6:3c510c297e2f 274 // trf797xStopDecoders();
soumi_ghsoh 6:3c510c297e2f 275 // trf797xReset();
soumi_ghsoh 6:3c510c297e2f 276 // trf797xResetIrqStatus();
soumi_ghsoh 6:3c510c297e2f 277 //// // IRQ_CLR;
soumi_ghsoh 6:3c510c297e2f 278 // }
soumi_ghsoh 6:3c510c297e2f 279 // else if (*irq_status == BIT6) { printf( "BIT6 INTERRUPT \r\n"); // RX flag means that EOF has been received // does not come here 3G
soumi_ghsoh 6:3c510c297e2f 280 // // and the number of unread bytes is in FIFOstatus register
soumi_ghsoh 5:93c612f43ec2 281 //
soumi_ghsoh 6:3c510c297e2f 282 // if (rxErrorFlag == 0x02) {
soumi_ghsoh 6:3c510c297e2f 283 // irqRegister = 0x02;
soumi_ghsoh 6:3c510c297e2f 284 // return;
soumi_ghsoh 6:3c510c297e2f 285 // }
soumi_ghsoh 6:3c510c297e2f 286 // *irq_status = FIFO_CONTROL;
soumi_ghsoh 6:3c510c297e2f 287 // trf797xReadSingle(irq_status, 1); // Determine the number of bytes left in FIFO
soumi_ghsoh 6:3c510c297e2f 288 // *irq_status = 0x7F & *irq_status;
soumi_ghsoh 6:3c510c297e2f 289 // buf[rxtxState] = FIFO; // Write the received bytes to the correct place in the buffer
soumi_ghsoh 6:3c510c297e2f 290 // trf797xReadContinuous(&buf[rxtxState], *irq_status);
soumi_ghsoh 6:3c510c297e2f 291 // rxtxState = rxtxState + *irq_status;
soumi_ghsoh 6:3c510c297e2f 292 // trf797xReset(); // Reset the FIFO after last byte has been read out
soumi_ghsoh 6:3c510c297e2f 293 // irqRegister = 0xFF; // Signal to the receive funnction that these are the last bytes
soumi_ghsoh 6:3c510c297e2f 294 // }
soumi_ghsoh 6:3c510c297e2f 295 // else if (*irq_status == 0x60) { printf( "RX active and 9 bytes already in FIFO \r\n"); // RX active and 9 bytes already in FIFO
soumi_ghsoh 5:93c612f43ec2 296 //
soumi_ghsoh 6:3c510c297e2f 297 // irqRegister = 0x01;
soumi_ghsoh 6:3c510c297e2f 298 // buf[rxtxState] = FIFO;
soumi_ghsoh 6:3c510c297e2f 299 // trf797xReadContinuous(&buf[rxtxState], 86); // Read 86 bytes from FIFO
soumi_ghsoh 6:3c510c297e2f 300 // rxtxState = rxtxState + 86;
soumi_ghsoh 6:3c510c297e2f 301 // if (readerInt) { //ISO15693LED = LED_ON; // If IRQ pin high // chnaged irqpin to readerInt
soumi_ghsoh 6:3c510c297e2f 302 // trf797xReadIrqStatus(irq_status);
soumi_ghsoh 6:3c510c297e2f 303 //// // IRQ_CLR
soumi_ghsoh 6:3c510c297e2f 304 // if (*irq_status == 0x40) { // End of recieve
soumi_ghsoh 6:3c510c297e2f 305 // *irq_status = FIFO_CONTROL;
soumi_ghsoh 6:3c510c297e2f 306 // trf797xReadSingle(irq_status, 1); // Determine the number of bytes left in FIFO
soumi_ghsoh 6:3c510c297e2f 307 // *irq_status = 0x7F & *irq_status;
soumi_ghsoh 6:3c510c297e2f 308 // buf[rxtxState] = FIFO; // Write the received bytes to the correct place in the buffer
soumi_ghsoh 6:3c510c297e2f 309 // trf797xReadContinuous(&buf[rxtxState], *irq_status);
soumi_ghsoh 6:3c510c297e2f 310 // rxtxState = rxtxState + *irq_status;
soumi_ghsoh 6:3c510c297e2f 311 // irqRegister = 0xFF; // Signal to the receive funnction that these are the last bytes
soumi_ghsoh 6:3c510c297e2f 312 // trf797xReset(); // Reset the FIFO after last byte has been read out
soumi_ghsoh 5:93c612f43ec2 313 // }
soumi_ghsoh 6:3c510c297e2f 314 // else if(*irq_status == 0x50) { printf( "End of receive and error \r\n"); // End of receive and error
soumi_ghsoh 6:3c510c297e2f 315 // irqRegister = 0x02;
soumi_ghsoh 5:93c612f43ec2 316 // }
soumi_ghsoh 5:93c612f43ec2 317 // }
soumi_ghsoh 6:3c510c297e2f 318 // else {
soumi_ghsoh 6:3c510c297e2f 319 // trf797xReadIrqStatus(irq_status);
soumi_ghsoh 6:3c510c297e2f 320 // if(irq_status[0] == 0x00) {
soumi_ghsoh 6:3c510c297e2f 321 // irqRegister = 0xFF;
soumi_ghsoh 6:3c510c297e2f 322 // }
soumi_ghsoh 6:3c510c297e2f 323 // }
soumi_ghsoh 6:3c510c297e2f 324 // }
soumi_ghsoh 6:3c510c297e2f 325 // else if ((*irq_status & BIT4) == BIT4) { printf( "BIT4 INTERRUPT \r\n"); // CRC error
soumi_ghsoh 6:3c510c297e2f 326 // if ((*irq_status & BIT5) == BIT5) { printf( "BIT5 INTERRUPT \r\n");
soumi_ghsoh 6:3c510c297e2f 327 // irqRegister = 0x01; // RX active
soumi_ghsoh 6:3c510c297e2f 328 // rxErrorFlag = 0x02;
soumi_ghsoh 6:3c510c297e2f 329 // }
soumi_ghsoh 6:3c510c297e2f 330 // if ((*irq_status & BIT6) == BIT6) { printf( "BIT4/BIT 6 INTERRUPT \r\n"); // 4 Bit receive
soumi_ghsoh 6:3c510c297e2f 331 // buf[200] = FIFO; // Write the received bytes to the correct place in the buffer
soumi_ghsoh 6:3c510c297e2f 332 // trf797xReadContinuous(&buf[200], 1);
soumi_ghsoh 6:3c510c297e2f 333 // trf797xReset();
soumi_ghsoh 6:3c510c297e2f 334 // irqRegister = 0x02; // End of RX
soumi_ghsoh 6:3c510c297e2f 335 // rxErrorFlag = 0x02;
soumi_ghsoh 6:3c510c297e2f 336 // }
soumi_ghsoh 6:3c510c297e2f 337 // else
soumi_ghsoh 6:3c510c297e2f 338 // {
soumi_ghsoh 6:3c510c297e2f 339 // irqRegister = 0x02; // End of RX
soumi_ghsoh 6:3c510c297e2f 340 // }
soumi_ghsoh 6:3c510c297e2f 341 // }
soumi_ghsoh 6:3c510c297e2f 342 // else if ((*irq_status & BIT2) == BIT2) { printf( "BIT2 INTERRUPT \r\n"); // Byte framing error
soumi_ghsoh 6:3c510c297e2f 343 // if ((*irq_status & BIT5) == BIT5) {
soumi_ghsoh 6:3c510c297e2f 344 // irqRegister = 0x01; // RX active
soumi_ghsoh 6:3c510c297e2f 345 // rxErrorFlag = 0x02;
soumi_ghsoh 6:3c510c297e2f 346 // }
soumi_ghsoh 6:3c510c297e2f 347 // else
soumi_ghsoh 6:3c510c297e2f 348 // irqRegister = 0x02; // End of RX
soumi_ghsoh 6:3c510c297e2f 349 // }
soumi_ghsoh 6:3c510c297e2f 350 // else if ((*irq_status == BIT0)) {printf( "No response interrupt \r\n"); // No response interrupt
soumi_ghsoh 6:3c510c297e2f 351 // irqRegister = 0x00;
soumi_ghsoh 6:3c510c297e2f 352 // }
soumi_ghsoh 6:3c510c297e2f 353 // else { // Interrupt register not properly set
soumi_ghsoh 6:3c510c297e2f 354 // printf ("Interrupt Error\r\n");
soumi_ghsoh 6:3c510c297e2f 355 //
soumi_ghsoh 6:3c510c297e2f 356 // irqRegister = 0x02;
soumi_ghsoh 6:3c510c297e2f 357 // trf797xStopDecoders(); // Reset the FIFO after TX
soumi_ghsoh 6:3c510c297e2f 358 // trf797xReset();
soumi_ghsoh 6:3c510c297e2f 359 // trf797xResetIrqStatus();
soumi_ghsoh 6:3c510c297e2f 360 // // Original code clears the IRQ flag here.
soumi_ghsoh 6:3c510c297e2f 361 // }
soumi_ghsoh 6:3c510c297e2f 362 // // wait_ms(10);
soumi_ghsoh 6:3c510c297e2f 363 ////debug2LED = LED_OFF;
soumi_ghsoh 6:3c510c297e2f 364 ////=================================================================================
soumi_ghsoh 6:3c510c297e2f 365 //} // End of trf797xISR()
soumi_ghsoh 6:3c510c297e2f 366 //
soumi_ghsoh 6:3c510c297e2f 367 //
soumi_ghsoh 6:3c510c297e2f 368 ////============================interrupt call back test
soumi_ghsoh 6:3c510c297e2f 369 //void trf797xIrqHandlerCallback(void)
soumi_ghsoh 6:3c510c297e2f 370 // { wait_ms(10);
soumi_ghsoh 6:3c510c297e2f 371 // debug1LED = LED_OFF;
soumi_ghsoh 6:3c510c297e2f 372 //
soumi_ghsoh 6:3c510c297e2f 373 // }
soumi_ghsoh 6:3c510c297e2f 374 ////==============================SG
soumi_ghsoh 6:3c510c297e2f 375 //
soumi_ghsoh 6:3c510c297e2f 376 //
soumi_ghsoh 6:3c510c297e2f 377 //
soumi_ghsoh 6:3c510c297e2f 378 //
soumi_ghsoh 6:3c510c297e2f 379 //
soumi_ghsoh 6:3c510c297e2f 380 //void trf797xIrqHandler(void)
soumi_ghsoh 6:3c510c297e2f 381 //// * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
soumi_ghsoh 6:3c510c297e2f 382 //// trf7970IrqHandler()
soumi_ghsoh 6:3c510c297e2f 383 //// __interrupt void Trf797xPortB(void) in original source file trf797x.c
soumi_ghsoh 6:3c510c297e2f 384 //// * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
soumi_ghsoh 6:3c510c297e2f 385 //{ //======================works $SG
soumi_ghsoh 6:3c510c297e2f 386 // debug1LED = LED_ON;
soumi_ghsoh 6:3c510c297e2f 387 // // uint8_t irqStatus[2], iso_control;
soumi_ghsoh 6:3c510c297e2f 388 // irqFlag = 0x02;
soumi_ghsoh 6:3c510c297e2f 389 // // trf797xIrqHandlerCallback();
soumi_ghsoh 6:3c510c297e2f 390 // //=====================================================================================
soumi_ghsoh 6:3c510c297e2f 391 // // do {
soumi_ghsoh 6:3c510c297e2f 392 ////
soumi_ghsoh 6:3c510c297e2f 393 //// iso_control = ISO_CONTROL;
soumi_ghsoh 6:3c510c297e2f 394 //// trf797xReadSingle(&iso_control, 1);
soumi_ghsoh 6:3c510c297e2f 395 //// trf797xReadIrqStatus(irqStatus); //reads IRQ_STATUS register SG
soumi_ghsoh 6:3c510c297e2f 396 ////
soumi_ghsoh 6:3c510c297e2f 397 //// if (*irqStatus == 0xA0) { // TX active and only 3 bytes left in FIFO
soumi_ghsoh 6:3c510c297e2f 398 //// break;
soumi_ghsoh 6:3c510c297e2f 399 //// }
soumi_ghsoh 6:3c510c297e2f 400 ////
soumi_ghsoh 6:3c510c297e2f 401 //// if ((iso_control & BIT5) != BIT5) { // RFID mode
soumi_ghsoh 6:3c510c297e2f 402 ////
soumi_ghsoh 6:3c510c297e2f 403 //// trf797xISR(irqStatus);}
soumi_ghsoh 6:3c510c297e2f 404 //
soumi_ghsoh 6:3c510c297e2f 405 // //==========================================================================
soumi_ghsoh 6:3c510c297e2f 406 // // }
soumi_ghsoh 6:3c510c297e2f 407 //// else { // NFC mode
soumi_ghsoh 6:3c510c297e2f 408 //// if ((iso_control & BIT2) == BIT2) {
soumi_ghsoh 6:3c510c297e2f 409 //// // Tag emulation
soumi_ghsoh 6:3c510c297e2f 410 //// tagFlag = 1;
soumi_ghsoh 6:3c510c297e2f 411 //// trf797xNfcModeIsr(irqStatus);
soumi_ghsoh 6:3c510c297e2f 412 ////
soumi_ghsoh 6:3c510c297e2f 413 //// }
soumi_ghsoh 6:3c510c297e2f 414 //// else {
soumi_ghsoh 6:3c510c297e2f 415 //// if ((iso_control & BIT4) == BIT4) { // Active mode
soumi_ghsoh 6:3c510c297e2f 416 ////
soumi_ghsoh 6:3c510c297e2f 417 //// trf797xNfcModeIsr(irqStatus);
soumi_ghsoh 6:3c510c297e2f 418 ////
soumi_ghsoh 6:3c510c297e2f 419 //// }
soumi_ghsoh 6:3c510c297e2f 420 //// else { // Passive mode
soumi_ghsoh 6:3c510c297e2f 421 //// trf797xTargetIsr(irqStatus);
soumi_ghsoh 6:3c510c297e2f 422 ////
soumi_ghsoh 6:3c510c297e2f 423 //// }
soumi_ghsoh 6:3c510c297e2f 424 //// }
soumi_ghsoh 6:3c510c297e2f 425 //// }
soumi_ghsoh 6:3c510c297e2f 426 // // } while(readerInt); // While IRQ pin is high ********** chnaged irq to readerInt
soumi_ghsoh 6:3c510c297e2f 427 //
soumi_ghsoh 6:3c510c297e2f 428 // // wait_ms(10);
soumi_ghsoh 6:3c510c297e2f 429 // debug1LED = LED_OFF;
soumi_ghsoh 6:3c510c297e2f 430 //
soumi_ghsoh 6:3c510c297e2f 431 //}
soumi_ghsoh 6:3c510c297e2f 432 //
soumi_ghsoh 6:3c510c297e2f 433 //
soumi_ghsoh 6:3c510c297e2f 434 //
soumi_ghsoh 6:3c510c297e2f 435 //
soumi_ghsoh 6:3c510c297e2f 436 //