FRA221:A / Mbed 2 deprecated RC522_LF

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Dependencies:   mbed

MFRC522.cpp@0:3d4bd1fdeb2e, 2015-10-23 (annotated)

Committer:
mustwillza
Date:
Fri Oct 23 11:01:44 2015 +0000
Revision:
0:3d4bd1fdeb2e
Worked

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mustwillza 0:3d4bd1fdeb2e 1 /*
mustwillza 0:3d4bd1fdeb2e 2 * MFRC522.cpp - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
mustwillza 0:3d4bd1fdeb2e 3 * _Please_ see the comments in MFRC522.h - they give useful hints and background.
mustwillza 0:3d4bd1fdeb2e 4 * Released into the public domain.
mustwillza 0:3d4bd1fdeb2e 5 */
mustwillza 0:3d4bd1fdeb2e 6
mustwillza 0:3d4bd1fdeb2e 7 #include "MFRC522.h"
mustwillza 0:3d4bd1fdeb2e 8
mustwillza 0:3d4bd1fdeb2e 9 static const char* const _TypeNamePICC[] =
mustwillza 0:3d4bd1fdeb2e 10 {
mustwillza 0:3d4bd1fdeb2e 11 "Unknown type",
mustwillza 0:3d4bd1fdeb2e 12 "PICC compliant with ISO/IEC 14443-4",
mustwillza 0:3d4bd1fdeb2e 13 "PICC compliant with ISO/IEC 18092 (NFC)",
mustwillza 0:3d4bd1fdeb2e 14 "MIFARE Mini, 320 bytes",
mustwillza 0:3d4bd1fdeb2e 15 "MIFARE 1KB",
mustwillza 0:3d4bd1fdeb2e 16 "MIFARE 4KB",
mustwillza 0:3d4bd1fdeb2e 17 "MIFARE Ultralight or Ultralight C",
mustwillza 0:3d4bd1fdeb2e 18 "MIFARE Plus",
mustwillza 0:3d4bd1fdeb2e 19 "MIFARE TNP3XXX",
mustwillza 0:3d4bd1fdeb2e 20
mustwillza 0:3d4bd1fdeb2e 21 /* not complete UID */
mustwillza 0:3d4bd1fdeb2e 22 "SAK indicates UID is not complete"
mustwillza 0:3d4bd1fdeb2e 23 };
mustwillza 0:3d4bd1fdeb2e 24
mustwillza 0:3d4bd1fdeb2e 25 static const char* const _ErrorMessage[] =
mustwillza 0:3d4bd1fdeb2e 26 {
mustwillza 0:3d4bd1fdeb2e 27 "Unknown error",
mustwillza 0:3d4bd1fdeb2e 28 "Success",
mustwillza 0:3d4bd1fdeb2e 29 "Error in communication",
mustwillza 0:3d4bd1fdeb2e 30 "Collision detected",
mustwillza 0:3d4bd1fdeb2e 31 "Timeout in communication",
mustwillza 0:3d4bd1fdeb2e 32 "A buffer is not big enough",
mustwillza 0:3d4bd1fdeb2e 33 "Internal error in the code, should not happen",
mustwillza 0:3d4bd1fdeb2e 34 "Invalid argument",
mustwillza 0:3d4bd1fdeb2e 35 "The CRC_A does not match",
mustwillza 0:3d4bd1fdeb2e 36 "A MIFARE PICC responded with NAK"
mustwillza 0:3d4bd1fdeb2e 37 };
mustwillza 0:3d4bd1fdeb2e 38
mustwillza 0:3d4bd1fdeb2e 39 #define MFRC522_MaxPICCs (sizeof(_TypeNamePICC)/sizeof(_TypeNamePICC[0]))
mustwillza 0:3d4bd1fdeb2e 40 #define MFRC522_MaxError (sizeof(_ErrorMessage)/sizeof(_ErrorMessage[0]))
mustwillza 0:3d4bd1fdeb2e 41
mustwillza 0:3d4bd1fdeb2e 42 /////////////////////////////////////////////////////////////////////////////////////
mustwillza 0:3d4bd1fdeb2e 43 // Functions for setting up the driver
mustwillza 0:3d4bd1fdeb2e 44 /////////////////////////////////////////////////////////////////////////////////////
mustwillza 0:3d4bd1fdeb2e 45
mustwillza 0:3d4bd1fdeb2e 46 /**
mustwillza 0:3d4bd1fdeb2e 47 * Constructor.
mustwillza 0:3d4bd1fdeb2e 48 * Prepares the output pins.
mustwillza 0:3d4bd1fdeb2e 49 */
mustwillza 0:3d4bd1fdeb2e 50 MFRC522::MFRC522(PinName mosi,
mustwillza 0:3d4bd1fdeb2e 51 PinName miso,
mustwillza 0:3d4bd1fdeb2e 52 PinName sclk,
mustwillza 0:3d4bd1fdeb2e 53 PinName cs,
mustwillza 0:3d4bd1fdeb2e 54 PinName reset) : m_SPI(mosi, miso, sclk), m_CS(cs), m_RESET(reset)
mustwillza 0:3d4bd1fdeb2e 55 {
mustwillza 0:3d4bd1fdeb2e 56 /* Configure SPI bus */
mustwillza 0:3d4bd1fdeb2e 57 m_SPI.format(8, 0);
mustwillza 0:3d4bd1fdeb2e 58 m_SPI.frequency(8000000);
mustwillza 0:3d4bd1fdeb2e 59
mustwillza 0:3d4bd1fdeb2e 60 /* Release SPI-CS pin */
mustwillza 0:3d4bd1fdeb2e 61 m_CS = 1;
mustwillza 0:3d4bd1fdeb2e 62
mustwillza 0:3d4bd1fdeb2e 63 /* Release RESET pin */
mustwillza 0:3d4bd1fdeb2e 64 m_RESET = 1;
mustwillza 0:3d4bd1fdeb2e 65 } // End constructor
mustwillza 0:3d4bd1fdeb2e 66
mustwillza 0:3d4bd1fdeb2e 67
mustwillza 0:3d4bd1fdeb2e 68 /**
mustwillza 0:3d4bd1fdeb2e 69 * Destructor.
mustwillza 0:3d4bd1fdeb2e 70 */
mustwillza 0:3d4bd1fdeb2e 71 MFRC522::~MFRC522()
mustwillza 0:3d4bd1fdeb2e 72 {
mustwillza 0:3d4bd1fdeb2e 73
mustwillza 0:3d4bd1fdeb2e 74 }
mustwillza 0:3d4bd1fdeb2e 75
mustwillza 0:3d4bd1fdeb2e 76
mustwillza 0:3d4bd1fdeb2e 77 /////////////////////////////////////////////////////////////////////////////////////
mustwillza 0:3d4bd1fdeb2e 78 // Basic interface functions for communicating with the MFRC522
mustwillza 0:3d4bd1fdeb2e 79 /////////////////////////////////////////////////////////////////////////////////////
mustwillza 0:3d4bd1fdeb2e 80
mustwillza 0:3d4bd1fdeb2e 81 /**
mustwillza 0:3d4bd1fdeb2e 82 * Writes a byte to the specified register in the MFRC522 chip.
mustwillza 0:3d4bd1fdeb2e 83 * The interface is described in the datasheet section 8.1.2.
mustwillza 0:3d4bd1fdeb2e 84 */
mustwillza 0:3d4bd1fdeb2e 85 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t value)
mustwillza 0:3d4bd1fdeb2e 86 {
mustwillza 0:3d4bd1fdeb2e 87 m_CS = 0; /* Select SPI Chip MFRC522 */
mustwillza 0:3d4bd1fdeb2e 88
mustwillza 0:3d4bd1fdeb2e 89 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
mustwillza 0:3d4bd1fdeb2e 90 (void) m_SPI.write(reg & 0x7E);
mustwillza 0:3d4bd1fdeb2e 91 (void) m_SPI.write(value);
mustwillza 0:3d4bd1fdeb2e 92
mustwillza 0:3d4bd1fdeb2e 93 m_CS = 1; /* Release SPI Chip MFRC522 */
mustwillza 0:3d4bd1fdeb2e 94 } // End PCD_WriteRegister()
mustwillza 0:3d4bd1fdeb2e 95
mustwillza 0:3d4bd1fdeb2e 96 /**
mustwillza 0:3d4bd1fdeb2e 97 * Writes a number of bytes to the specified register in the MFRC522 chip.
mustwillza 0:3d4bd1fdeb2e 98 * The interface is described in the datasheet section 8.1.2.
mustwillza 0:3d4bd1fdeb2e 99 */
mustwillza 0:3d4bd1fdeb2e 100 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t count, uint8_t *values)
mustwillza 0:3d4bd1fdeb2e 101 {
mustwillza 0:3d4bd1fdeb2e 102 m_CS = 0; /* Select SPI Chip MFRC522 */
mustwillza 0:3d4bd1fdeb2e 103
mustwillza 0:3d4bd1fdeb2e 104 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
mustwillza 0:3d4bd1fdeb2e 105 (void) m_SPI.write(reg & 0x7E);
mustwillza 0:3d4bd1fdeb2e 106 for (uint8_t index = 0; index < count; index++)
mustwillza 0:3d4bd1fdeb2e 107 {
mustwillza 0:3d4bd1fdeb2e 108 (void) m_SPI.write(values[index]);
mustwillza 0:3d4bd1fdeb2e 109 }
mustwillza 0:3d4bd1fdeb2e 110
mustwillza 0:3d4bd1fdeb2e 111 m_CS = 1; /* Release SPI Chip MFRC522 */
mustwillza 0:3d4bd1fdeb2e 112 } // End PCD_WriteRegister()
mustwillza 0:3d4bd1fdeb2e 113
mustwillza 0:3d4bd1fdeb2e 114 /**
mustwillza 0:3d4bd1fdeb2e 115 * Reads a byte from the specified register in the MFRC522 chip.
mustwillza 0:3d4bd1fdeb2e 116 * The interface is described in the datasheet section 8.1.2.
mustwillza 0:3d4bd1fdeb2e 117 */
mustwillza 0:3d4bd1fdeb2e 118 uint8_t MFRC522::PCD_ReadRegister(uint8_t reg)
mustwillza 0:3d4bd1fdeb2e 119 {
mustwillza 0:3d4bd1fdeb2e 120 uint8_t value;
mustwillza 0:3d4bd1fdeb2e 121 m_CS = 0; /* Select SPI Chip MFRC522 */
mustwillza 0:3d4bd1fdeb2e 122
mustwillza 0:3d4bd1fdeb2e 123 // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
mustwillza 0:3d4bd1fdeb2e 124 (void) m_SPI.write(0x80 | reg);
mustwillza 0:3d4bd1fdeb2e 125
mustwillza 0:3d4bd1fdeb2e 126 // Read the value back. Send 0 to stop reading.
mustwillza 0:3d4bd1fdeb2e 127 value = m_SPI.write(0);
mustwillza 0:3d4bd1fdeb2e 128
mustwillza 0:3d4bd1fdeb2e 129 m_CS = 1; /* Release SPI Chip MFRC522 */
mustwillza 0:3d4bd1fdeb2e 130
mustwillza 0:3d4bd1fdeb2e 131 return value;
mustwillza 0:3d4bd1fdeb2e 132 } // End PCD_ReadRegister()
mustwillza 0:3d4bd1fdeb2e 133
mustwillza 0:3d4bd1fdeb2e 134 /**
mustwillza 0:3d4bd1fdeb2e 135 * Reads a number of bytes from the specified register in the MFRC522 chip.
mustwillza 0:3d4bd1fdeb2e 136 * The interface is described in the datasheet section 8.1.2.
mustwillza 0:3d4bd1fdeb2e 137 */
mustwillza 0:3d4bd1fdeb2e 138 void MFRC522::PCD_ReadRegister(uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign)
mustwillza 0:3d4bd1fdeb2e 139 {
mustwillza 0:3d4bd1fdeb2e 140 if (count == 0) { return; }
mustwillza 0:3d4bd1fdeb2e 141
mustwillza 0:3d4bd1fdeb2e 142 uint8_t address = 0x80 | reg; // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
mustwillza 0:3d4bd1fdeb2e 143 uint8_t index = 0; // Index in values array.
mustwillza 0:3d4bd1fdeb2e 144
mustwillza 0:3d4bd1fdeb2e 145 m_CS = 0; /* Select SPI Chip MFRC522 */
mustwillza 0:3d4bd1fdeb2e 146 count--; // One read is performed outside of the loop
mustwillza 0:3d4bd1fdeb2e 147 (void) m_SPI.write(address); // Tell MFRC522 which address we want to read
mustwillza 0:3d4bd1fdeb2e 148
mustwillza 0:3d4bd1fdeb2e 149 while (index < count)
mustwillza 0:3d4bd1fdeb2e 150 {
mustwillza 0:3d4bd1fdeb2e 151 if ((index == 0) && rxAlign) // Only update bit positions rxAlign..7 in values[0]
mustwillza 0:3d4bd1fdeb2e 152 {
mustwillza 0:3d4bd1fdeb2e 153 // Create bit mask for bit positions rxAlign..7
mustwillza 0:3d4bd1fdeb2e 154 uint8_t mask = 0;
mustwillza 0:3d4bd1fdeb2e 155 for (uint8_t i = rxAlign; i <= 7; i++)
mustwillza 0:3d4bd1fdeb2e 156 {
mustwillza 0:3d4bd1fdeb2e 157 mask |= (1 << i);
mustwillza 0:3d4bd1fdeb2e 158 }
mustwillza 0:3d4bd1fdeb2e 159
mustwillza 0:3d4bd1fdeb2e 160 // Read value and tell that we want to read the same address again.
mustwillza 0:3d4bd1fdeb2e 161 uint8_t value = m_SPI.write(address);
mustwillza 0:3d4bd1fdeb2e 162
mustwillza 0:3d4bd1fdeb2e 163 // Apply mask to both current value of values[0] and the new data in value.
mustwillza 0:3d4bd1fdeb2e 164 values[0] = (values[index] & ~mask) | (value & mask);
mustwillza 0:3d4bd1fdeb2e 165 }
mustwillza 0:3d4bd1fdeb2e 166 else
mustwillza 0:3d4bd1fdeb2e 167 {
mustwillza 0:3d4bd1fdeb2e 168 // Read value and tell that we want to read the same address again.
mustwillza 0:3d4bd1fdeb2e 169 values[index] = m_SPI.write(address);
mustwillza 0:3d4bd1fdeb2e 170 }
mustwillza 0:3d4bd1fdeb2e 171
mustwillza 0:3d4bd1fdeb2e 172 index++;
mustwillza 0:3d4bd1fdeb2e 173 }
mustwillza 0:3d4bd1fdeb2e 174
mustwillza 0:3d4bd1fdeb2e 175 values[index] = m_SPI.write(0); // Read the final byte. Send 0 to stop reading.
mustwillza 0:3d4bd1fdeb2e 176
mustwillza 0:3d4bd1fdeb2e 177 m_CS = 1; /* Release SPI Chip MFRC522 */
mustwillza 0:3d4bd1fdeb2e 178 } // End PCD_ReadRegister()
mustwillza 0:3d4bd1fdeb2e 179
mustwillza 0:3d4bd1fdeb2e 180 /**
mustwillza 0:3d4bd1fdeb2e 181 * Sets the bits given in mask in register reg.
mustwillza 0:3d4bd1fdeb2e 182 */
mustwillza 0:3d4bd1fdeb2e 183 void MFRC522::PCD_SetRegisterBits(uint8_t reg, uint8_t mask)
mustwillza 0:3d4bd1fdeb2e 184 {
mustwillza 0:3d4bd1fdeb2e 185 uint8_t tmp = PCD_ReadRegister(reg);
mustwillza 0:3d4bd1fdeb2e 186 PCD_WriteRegister(reg, tmp | mask); // set bit mask
mustwillza 0:3d4bd1fdeb2e 187 } // End PCD_SetRegisterBitMask()
mustwillza 0:3d4bd1fdeb2e 188
mustwillza 0:3d4bd1fdeb2e 189 /**
mustwillza 0:3d4bd1fdeb2e 190 * Clears the bits given in mask from register reg.
mustwillza 0:3d4bd1fdeb2e 191 */
mustwillza 0:3d4bd1fdeb2e 192 void MFRC522::PCD_ClrRegisterBits(uint8_t reg, uint8_t mask)
mustwillza 0:3d4bd1fdeb2e 193 {
mustwillza 0:3d4bd1fdeb2e 194 uint8_t tmp = PCD_ReadRegister(reg);
mustwillza 0:3d4bd1fdeb2e 195 PCD_WriteRegister(reg, tmp & (~mask)); // clear bit mask
mustwillza 0:3d4bd1fdeb2e 196 } // End PCD_ClearRegisterBitMask()
mustwillza 0:3d4bd1fdeb2e 197
mustwillza 0:3d4bd1fdeb2e 198
mustwillza 0:3d4bd1fdeb2e 199 /**
mustwillza 0:3d4bd1fdeb2e 200 * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
mustwillza 0:3d4bd1fdeb2e 201 */
mustwillza 0:3d4bd1fdeb2e 202 uint8_t MFRC522::PCD_CalculateCRC(uint8_t *data, uint8_t length, uint8_t *result)
mustwillza 0:3d4bd1fdeb2e 203 {
mustwillza 0:3d4bd1fdeb2e 204 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
mustwillza 0:3d4bd1fdeb2e 205 PCD_WriteRegister(DivIrqReg, 0x04); // Clear the CRCIRq interrupt request bit
mustwillza 0:3d4bd1fdeb2e 206 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
mustwillza 0:3d4bd1fdeb2e 207 PCD_WriteRegister(FIFODataReg, length, data); // Write data to the FIFO
mustwillza 0:3d4bd1fdeb2e 208 PCD_WriteRegister(CommandReg, PCD_CalcCRC); // Start the calculation
mustwillza 0:3d4bd1fdeb2e 209
mustwillza 0:3d4bd1fdeb2e 210 // Wait for the CRC calculation to complete. Each iteration of the while-loop takes 17.73us.
mustwillza 0:3d4bd1fdeb2e 211 uint16_t i = 5000;
mustwillza 0:3d4bd1fdeb2e 212 uint8_t n;
mustwillza 0:3d4bd1fdeb2e 213 while (1)
mustwillza 0:3d4bd1fdeb2e 214 {
mustwillza 0:3d4bd1fdeb2e 215 n = PCD_ReadRegister(DivIrqReg); // DivIrqReg[7..0] bits are: Set2 reserved reserved MfinActIRq reserved CRCIRq reserved reserved
mustwillza 0:3d4bd1fdeb2e 216 if (n & 0x04)
mustwillza 0:3d4bd1fdeb2e 217 {
mustwillza 0:3d4bd1fdeb2e 218 // CRCIRq bit set - calculation done
mustwillza 0:3d4bd1fdeb2e 219 break;
mustwillza 0:3d4bd1fdeb2e 220 }
mustwillza 0:3d4bd1fdeb2e 221
mustwillza 0:3d4bd1fdeb2e 222 if (--i == 0)
mustwillza 0:3d4bd1fdeb2e 223 {
mustwillza 0:3d4bd1fdeb2e 224 // The emergency break. We will eventually terminate on this one after 89ms.
mustwillza 0:3d4bd1fdeb2e 225 // Communication with the MFRC522 might be down.
mustwillza 0:3d4bd1fdeb2e 226 return STATUS_TIMEOUT;
mustwillza 0:3d4bd1fdeb2e 227 }
mustwillza 0:3d4bd1fdeb2e 228 }
mustwillza 0:3d4bd1fdeb2e 229
mustwillza 0:3d4bd1fdeb2e 230 // Stop calculating CRC for new content in the FIFO.
mustwillza 0:3d4bd1fdeb2e 231 PCD_WriteRegister(CommandReg, PCD_Idle);
mustwillza 0:3d4bd1fdeb2e 232
mustwillza 0:3d4bd1fdeb2e 233 // Transfer the result from the registers to the result buffer
mustwillza 0:3d4bd1fdeb2e 234 result[0] = PCD_ReadRegister(CRCResultRegL);
mustwillza 0:3d4bd1fdeb2e 235 result[1] = PCD_ReadRegister(CRCResultRegH);
mustwillza 0:3d4bd1fdeb2e 236 return STATUS_OK;
mustwillza 0:3d4bd1fdeb2e 237 } // End PCD_CalculateCRC()
mustwillza 0:3d4bd1fdeb2e 238
mustwillza 0:3d4bd1fdeb2e 239
mustwillza 0:3d4bd1fdeb2e 240 /////////////////////////////////////////////////////////////////////////////////////
mustwillza 0:3d4bd1fdeb2e 241 // Functions for manipulating the MFRC522
mustwillza 0:3d4bd1fdeb2e 242 /////////////////////////////////////////////////////////////////////////////////////
mustwillza 0:3d4bd1fdeb2e 243
mustwillza 0:3d4bd1fdeb2e 244 /**
mustwillza 0:3d4bd1fdeb2e 245 * Initializes the MFRC522 chip.
mustwillza 0:3d4bd1fdeb2e 246 */
mustwillza 0:3d4bd1fdeb2e 247 void MFRC522::PCD_Init()
mustwillza 0:3d4bd1fdeb2e 248 {
mustwillza 0:3d4bd1fdeb2e 249 /* Reset MFRC522 */
mustwillza 0:3d4bd1fdeb2e 250 m_RESET = 0;
mustwillza 0:3d4bd1fdeb2e 251 wait_ms(10);
mustwillza 0:3d4bd1fdeb2e 252 m_RESET = 1;
mustwillza 0:3d4bd1fdeb2e 253
mustwillza 0:3d4bd1fdeb2e 254 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
mustwillza 0:3d4bd1fdeb2e 255 wait_ms(50);
mustwillza 0:3d4bd1fdeb2e 256
mustwillza 0:3d4bd1fdeb2e 257 // When communicating with a PICC we need a timeout if something goes wrong.
mustwillza 0:3d4bd1fdeb2e 258 // f_timer = 13.56 MHz / (2*TPreScaler+1) where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo].
mustwillza 0:3d4bd1fdeb2e 259 // TPrescaler_Hi are the four low bits in TModeReg. TPrescaler_Lo is TPrescalerReg.
mustwillza 0:3d4bd1fdeb2e 260 PCD_WriteRegister(TModeReg, 0x80); // TAuto=1; timer starts automatically at the end of the transmission in all communication modes at all speeds
mustwillza 0:3d4bd1fdeb2e 261 PCD_WriteRegister(TPrescalerReg, 0xA9); // TPreScaler = TModeReg[3..0]:TPrescalerReg, ie 0x0A9 = 169 => f_timer=40kHz, ie a timer period of 25us.
mustwillza 0:3d4bd1fdeb2e 262 PCD_WriteRegister(TReloadRegH, 0x03); // Reload timer with 0x3E8 = 1000, ie 25ms before timeout.
mustwillza 0:3d4bd1fdeb2e 263 PCD_WriteRegister(TReloadRegL, 0xE8);
mustwillza 0:3d4bd1fdeb2e 264
mustwillza 0:3d4bd1fdeb2e 265 PCD_WriteRegister(TxASKReg, 0x40); // Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting
mustwillza 0:3d4bd1fdeb2e 266 PCD_WriteRegister(ModeReg, 0x3D); // Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4)
mustwillza 0:3d4bd1fdeb2e 267
mustwillza 0:3d4bd1fdeb2e 268 PCD_WriteRegister(RFCfgReg, (0x07<<4)); // Set Rx Gain to max
mustwillza 0:3d4bd1fdeb2e 269
mustwillza 0:3d4bd1fdeb2e 270 PCD_AntennaOn(); // Enable the antenna driver pins TX1 and TX2 (they were disabled by the reset)
mustwillza 0:3d4bd1fdeb2e 271 } // End PCD_Init()
mustwillza 0:3d4bd1fdeb2e 272
mustwillza 0:3d4bd1fdeb2e 273 /**
mustwillza 0:3d4bd1fdeb2e 274 * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
mustwillza 0:3d4bd1fdeb2e 275 */
mustwillza 0:3d4bd1fdeb2e 276 void MFRC522::PCD_Reset()
mustwillza 0:3d4bd1fdeb2e 277 {
mustwillza 0:3d4bd1fdeb2e 278 PCD_WriteRegister(CommandReg, PCD_SoftReset); // Issue the SoftReset command.
mustwillza 0:3d4bd1fdeb2e 279 // The datasheet does not mention how long the SoftRest command takes to complete.
mustwillza 0:3d4bd1fdeb2e 280 // But the MFRC522 might have been in soft power-down mode (triggered by bit 4 of CommandReg)
mustwillza 0:3d4bd1fdeb2e 281 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
mustwillza 0:3d4bd1fdeb2e 282 wait_ms(50);
mustwillza 0:3d4bd1fdeb2e 283
mustwillza 0:3d4bd1fdeb2e 284 // Wait for the PowerDown bit in CommandReg to be cleared
mustwillza 0:3d4bd1fdeb2e 285 while (PCD_ReadRegister(CommandReg) & (1<<4))
mustwillza 0:3d4bd1fdeb2e 286 {
mustwillza 0:3d4bd1fdeb2e 287 // PCD still restarting - unlikely after waiting 50ms, but better safe than sorry.
mustwillza 0:3d4bd1fdeb2e 288 }
mustwillza 0:3d4bd1fdeb2e 289 } // End PCD_Reset()
mustwillza 0:3d4bd1fdeb2e 290
mustwillza 0:3d4bd1fdeb2e 291 /**
mustwillza 0:3d4bd1fdeb2e 292 * Turns the antenna on by enabling pins TX1 and TX2.
mustwillza 0:3d4bd1fdeb2e 293 * After a reset these pins disabled.
mustwillza 0:3d4bd1fdeb2e 294 */
mustwillza 0:3d4bd1fdeb2e 295 void MFRC522::PCD_AntennaOn()
mustwillza 0:3d4bd1fdeb2e 296 {
mustwillza 0:3d4bd1fdeb2e 297 uint8_t value = PCD_ReadRegister(TxControlReg);
mustwillza 0:3d4bd1fdeb2e 298 if ((value & 0x03) != 0x03)
mustwillza 0:3d4bd1fdeb2e 299 {
mustwillza 0:3d4bd1fdeb2e 300 PCD_WriteRegister(TxControlReg, value | 0x03);
mustwillza 0:3d4bd1fdeb2e 301 }
mustwillza 0:3d4bd1fdeb2e 302 } // End PCD_AntennaOn()
mustwillza 0:3d4bd1fdeb2e 303
mustwillza 0:3d4bd1fdeb2e 304 /////////////////////////////////////////////////////////////////////////////////////
mustwillza 0:3d4bd1fdeb2e 305 // Functions for communicating with PICCs
mustwillza 0:3d4bd1fdeb2e 306 /////////////////////////////////////////////////////////////////////////////////////
mustwillza 0:3d4bd1fdeb2e 307
mustwillza 0:3d4bd1fdeb2e 308 /**
mustwillza 0:3d4bd1fdeb2e 309 * Executes the Transceive command.
mustwillza 0:3d4bd1fdeb2e 310 * CRC validation can only be done if backData and backLen are specified.
mustwillza 0:3d4bd1fdeb2e 311 */
mustwillza 0:3d4bd1fdeb2e 312 uint8_t MFRC522::PCD_TransceiveData(uint8_t *sendData,
mustwillza 0:3d4bd1fdeb2e 313 uint8_t sendLen,
mustwillza 0:3d4bd1fdeb2e 314 uint8_t *backData,
mustwillza 0:3d4bd1fdeb2e 315 uint8_t *backLen,
mustwillza 0:3d4bd1fdeb2e 316 uint8_t *validBits,
mustwillza 0:3d4bd1fdeb2e 317 uint8_t rxAlign,
mustwillza 0:3d4bd1fdeb2e 318 bool checkCRC)
mustwillza 0:3d4bd1fdeb2e 319 {
mustwillza 0:3d4bd1fdeb2e 320 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
mustwillza 0:3d4bd1fdeb2e 321 return PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, sendData, sendLen, backData, backLen, validBits, rxAlign, checkCRC);
mustwillza 0:3d4bd1fdeb2e 322 } // End PCD_TransceiveData()
mustwillza 0:3d4bd1fdeb2e 323
mustwillza 0:3d4bd1fdeb2e 324 /**
mustwillza 0:3d4bd1fdeb2e 325 * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
mustwillza 0:3d4bd1fdeb2e 326 * CRC validation can only be done if backData and backLen are specified.
mustwillza 0:3d4bd1fdeb2e 327 */
mustwillza 0:3d4bd1fdeb2e 328 uint8_t MFRC522::PCD_CommunicateWithPICC(uint8_t command,
mustwillza 0:3d4bd1fdeb2e 329 uint8_t waitIRq,
mustwillza 0:3d4bd1fdeb2e 330 uint8_t *sendData,
mustwillza 0:3d4bd1fdeb2e 331 uint8_t sendLen,
mustwillza 0:3d4bd1fdeb2e 332 uint8_t *backData,
mustwillza 0:3d4bd1fdeb2e 333 uint8_t *backLen,
mustwillza 0:3d4bd1fdeb2e 334 uint8_t *validBits,
mustwillza 0:3d4bd1fdeb2e 335 uint8_t rxAlign,
mustwillza 0:3d4bd1fdeb2e 336 bool checkCRC)
mustwillza 0:3d4bd1fdeb2e 337 {
mustwillza 0:3d4bd1fdeb2e 338 uint8_t n, _validBits = 0;
mustwillza 0:3d4bd1fdeb2e 339 uint32_t i;
mustwillza 0:3d4bd1fdeb2e 340
mustwillza 0:3d4bd1fdeb2e 341 // Prepare values for BitFramingReg
mustwillza 0:3d4bd1fdeb2e 342 uint8_t txLastBits = validBits ? *validBits : 0;
mustwillza 0:3d4bd1fdeb2e 343 uint8_t bitFraming = (rxAlign << 4) + txLastBits; // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
mustwillza 0:3d4bd1fdeb2e 344
mustwillza 0:3d4bd1fdeb2e 345 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
mustwillza 0:3d4bd1fdeb2e 346 PCD_WriteRegister(ComIrqReg, 0x7F); // Clear all seven interrupt request bits
mustwillza 0:3d4bd1fdeb2e 347 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
mustwillza 0:3d4bd1fdeb2e 348 PCD_WriteRegister(FIFODataReg, sendLen, sendData); // Write sendData to the FIFO
mustwillza 0:3d4bd1fdeb2e 349 PCD_WriteRegister(BitFramingReg, bitFraming); // Bit adjustments
mustwillza 0:3d4bd1fdeb2e 350 PCD_WriteRegister(CommandReg, command); // Execute the command
mustwillza 0:3d4bd1fdeb2e 351 if (command == PCD_Transceive)
mustwillza 0:3d4bd1fdeb2e 352 {
mustwillza 0:3d4bd1fdeb2e 353 PCD_SetRegisterBits(BitFramingReg, 0x80); // StartSend=1, transmission of data starts
mustwillza 0:3d4bd1fdeb2e 354 }
mustwillza 0:3d4bd1fdeb2e 355
mustwillza 0:3d4bd1fdeb2e 356 // Wait for the command to complete.
mustwillza 0:3d4bd1fdeb2e 357 // In PCD_Init() we set the TAuto flag in TModeReg. This means the timer automatically starts when the PCD stops transmitting.
mustwillza 0:3d4bd1fdeb2e 358 // Each iteration of the do-while-loop takes 17.86us.
mustwillza 0:3d4bd1fdeb2e 359 i = 2000;
mustwillza 0:3d4bd1fdeb2e 360 while (1)
mustwillza 0:3d4bd1fdeb2e 361 {
mustwillza 0:3d4bd1fdeb2e 362 n = PCD_ReadRegister(ComIrqReg); // ComIrqReg[7..0] bits are: Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq
mustwillza 0:3d4bd1fdeb2e 363 if (n & waitIRq)
mustwillza 0:3d4bd1fdeb2e 364 { // One of the interrupts that signal success has been set.
mustwillza 0:3d4bd1fdeb2e 365 break;
mustwillza 0:3d4bd1fdeb2e 366 }
mustwillza 0:3d4bd1fdeb2e 367
mustwillza 0:3d4bd1fdeb2e 368 if (n & 0x01)
mustwillza 0:3d4bd1fdeb2e 369 { // Timer interrupt - nothing received in 25ms
mustwillza 0:3d4bd1fdeb2e 370 return STATUS_TIMEOUT;
mustwillza 0:3d4bd1fdeb2e 371 }
mustwillza 0:3d4bd1fdeb2e 372
mustwillza 0:3d4bd1fdeb2e 373 if (--i == 0)
mustwillza 0:3d4bd1fdeb2e 374 { // The emergency break. If all other condions fail we will eventually terminate on this one after 35.7ms. Communication with the MFRC522 might be down.
mustwillza 0:3d4bd1fdeb2e 375 return STATUS_TIMEOUT;
mustwillza 0:3d4bd1fdeb2e 376 }
mustwillza 0:3d4bd1fdeb2e 377 }
mustwillza 0:3d4bd1fdeb2e 378
mustwillza 0:3d4bd1fdeb2e 379 // Stop now if any errors except collisions were detected.
mustwillza 0:3d4bd1fdeb2e 380 uint8_t errorRegValue = PCD_ReadRegister(ErrorReg); // ErrorReg[7..0] bits are: WrErr TempErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr
mustwillza 0:3d4bd1fdeb2e 381 if (errorRegValue & 0x13)
mustwillza 0:3d4bd1fdeb2e 382 { // BufferOvfl ParityErr ProtocolErr
mustwillza 0:3d4bd1fdeb2e 383 return STATUS_ERROR;
mustwillza 0:3d4bd1fdeb2e 384 }
mustwillza 0:3d4bd1fdeb2e 385
mustwillza 0:3d4bd1fdeb2e 386 // If the caller wants data back, get it from the MFRC522.
mustwillza 0:3d4bd1fdeb2e 387 if (backData && backLen)
mustwillza 0:3d4bd1fdeb2e 388 {
mustwillza 0:3d4bd1fdeb2e 389 n = PCD_ReadRegister(FIFOLevelReg); // Number of bytes in the FIFO
mustwillza 0:3d4bd1fdeb2e 390 if (n > *backLen)
mustwillza 0:3d4bd1fdeb2e 391 {
mustwillza 0:3d4bd1fdeb2e 392 return STATUS_NO_ROOM;
mustwillza 0:3d4bd1fdeb2e 393 }
mustwillza 0:3d4bd1fdeb2e 394
mustwillza 0:3d4bd1fdeb2e 395 *backLen = n; // Number of bytes returned
mustwillza 0:3d4bd1fdeb2e 396 PCD_ReadRegister(FIFODataReg, n, backData, rxAlign); // Get received data from FIFO
mustwillza 0:3d4bd1fdeb2e 397 _validBits = PCD_ReadRegister(ControlReg) & 0x07; // RxLastBits[2:0] indicates the number of valid bits in the last received byte. If this value is 000b, the whole byte is valid.
mustwillza 0:3d4bd1fdeb2e 398 if (validBits)
mustwillza 0:3d4bd1fdeb2e 399 {
mustwillza 0:3d4bd1fdeb2e 400 *validBits = _validBits;
mustwillza 0:3d4bd1fdeb2e 401 }
mustwillza 0:3d4bd1fdeb2e 402 }
mustwillza 0:3d4bd1fdeb2e 403
mustwillza 0:3d4bd1fdeb2e 404 // Tell about collisions
mustwillza 0:3d4bd1fdeb2e 405 if (errorRegValue & 0x08)
mustwillza 0:3d4bd1fdeb2e 406 { // CollErr
mustwillza 0:3d4bd1fdeb2e 407 return STATUS_COLLISION;
mustwillza 0:3d4bd1fdeb2e 408 }
mustwillza 0:3d4bd1fdeb2e 409
mustwillza 0:3d4bd1fdeb2e 410 // Perform CRC_A validation if requested.
mustwillza 0:3d4bd1fdeb2e 411 if (backData && backLen && checkCRC)
mustwillza 0:3d4bd1fdeb2e 412 {
mustwillza 0:3d4bd1fdeb2e 413 // In this case a MIFARE Classic NAK is not OK.
mustwillza 0:3d4bd1fdeb2e 414 if ((*backLen == 1) && (_validBits == 4))
mustwillza 0:3d4bd1fdeb2e 415 {
mustwillza 0:3d4bd1fdeb2e 416 return STATUS_MIFARE_NACK;
mustwillza 0:3d4bd1fdeb2e 417 }
mustwillza 0:3d4bd1fdeb2e 418
mustwillza 0:3d4bd1fdeb2e 419 // We need at least the CRC_A value and all 8 bits of the last byte must be received.
mustwillza 0:3d4bd1fdeb2e 420 if ((*backLen < 2) || (_validBits != 0))
mustwillza 0:3d4bd1fdeb2e 421 {
mustwillza 0:3d4bd1fdeb2e 422 return STATUS_CRC_WRONG;
mustwillza 0:3d4bd1fdeb2e 423 }
mustwillza 0:3d4bd1fdeb2e 424
mustwillza 0:3d4bd1fdeb2e 425 // Verify CRC_A - do our own calculation and store the control in controlBuffer.
mustwillza 0:3d4bd1fdeb2e 426 uint8_t controlBuffer[2];
mustwillza 0:3d4bd1fdeb2e 427 n = PCD_CalculateCRC(&backData[0], *backLen - 2, &controlBuffer[0]);
mustwillza 0:3d4bd1fdeb2e 428 if (n != STATUS_OK)
mustwillza 0:3d4bd1fdeb2e 429 {
mustwillza 0:3d4bd1fdeb2e 430 return n;
mustwillza 0:3d4bd1fdeb2e 431 }
mustwillza 0:3d4bd1fdeb2e 432
mustwillza 0:3d4bd1fdeb2e 433 if ((backData[*backLen - 2] != controlBuffer[0]) || (backData[*backLen - 1] != controlBuffer[1]))
mustwillza 0:3d4bd1fdeb2e 434 {
mustwillza 0:3d4bd1fdeb2e 435 return STATUS_CRC_WRONG;
mustwillza 0:3d4bd1fdeb2e 436 }
mustwillza 0:3d4bd1fdeb2e 437 }
mustwillza 0:3d4bd1fdeb2e 438
mustwillza 0:3d4bd1fdeb2e 439 return STATUS_OK;
mustwillza 0:3d4bd1fdeb2e 440 } // End PCD_CommunicateWithPICC()
mustwillza 0:3d4bd1fdeb2e 441
mustwillza 0:3d4bd1fdeb2e 442 /*
mustwillza 0:3d4bd1fdeb2e 443 * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
mustwillza 0:3d4bd1fdeb2e 444 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
mustwillza 0:3d4bd1fdeb2e 445 */
mustwillza 0:3d4bd1fdeb2e 446 uint8_t MFRC522::PICC_RequestA(uint8_t *bufferATQA, uint8_t *bufferSize)
mustwillza 0:3d4bd1fdeb2e 447 {
mustwillza 0:3d4bd1fdeb2e 448 return PICC_REQA_or_WUPA(PICC_CMD_REQA, bufferATQA, bufferSize);
mustwillza 0:3d4bd1fdeb2e 449 } // End PICC_RequestA()
mustwillza 0:3d4bd1fdeb2e 450
mustwillza 0:3d4bd1fdeb2e 451 /**
mustwillza 0:3d4bd1fdeb2e 452 * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
mustwillza 0:3d4bd1fdeb2e 453 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
mustwillza 0:3d4bd1fdeb2e 454 */
mustwillza 0:3d4bd1fdeb2e 455 uint8_t MFRC522::PICC_WakeupA(uint8_t *bufferATQA, uint8_t *bufferSize)
mustwillza 0:3d4bd1fdeb2e 456 {
mustwillza 0:3d4bd1fdeb2e 457 return PICC_REQA_or_WUPA(PICC_CMD_WUPA, bufferATQA, bufferSize);
mustwillza 0:3d4bd1fdeb2e 458 } // End PICC_WakeupA()
mustwillza 0:3d4bd1fdeb2e 459
mustwillza 0:3d4bd1fdeb2e 460 /*
mustwillza 0:3d4bd1fdeb2e 461 * Transmits REQA or WUPA commands.
mustwillza 0:3d4bd1fdeb2e 462 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
mustwillza 0:3d4bd1fdeb2e 463 */
mustwillza 0:3d4bd1fdeb2e 464 uint8_t MFRC522::PICC_REQA_or_WUPA(uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize)
mustwillza 0:3d4bd1fdeb2e 465 {
mustwillza 0:3d4bd1fdeb2e 466 uint8_t validBits;
mustwillza 0:3d4bd1fdeb2e 467 uint8_t status;
mustwillza 0:3d4bd1fdeb2e 468
mustwillza 0:3d4bd1fdeb2e 469 if (bufferATQA == NULL || *bufferSize < 2)
mustwillza 0:3d4bd1fdeb2e 470 { // The ATQA response is 2 bytes long.
mustwillza 0:3d4bd1fdeb2e 471 return STATUS_NO_ROOM;
mustwillza 0:3d4bd1fdeb2e 472 }
mustwillza 0:3d4bd1fdeb2e 473
mustwillza 0:3d4bd1fdeb2e 474 // ValuesAfterColl=1 => Bits received after collision are cleared.
mustwillza 0:3d4bd1fdeb2e 475 PCD_ClrRegisterBits(CollReg, 0x80);
mustwillza 0:3d4bd1fdeb2e 476
mustwillza 0:3d4bd1fdeb2e 477 // For REQA and WUPA we need the short frame format
mustwillza 0:3d4bd1fdeb2e 478 // - transmit only 7 bits of the last (and only) byte. TxLastBits = BitFramingReg[2..0]
mustwillza 0:3d4bd1fdeb2e 479 validBits = 7;
mustwillza 0:3d4bd1fdeb2e 480
mustwillza 0:3d4bd1fdeb2e 481 status = PCD_TransceiveData(&command, 1, bufferATQA, bufferSize, &validBits);
mustwillza 0:3d4bd1fdeb2e 482 if (status != STATUS_OK)
mustwillza 0:3d4bd1fdeb2e 483 {
mustwillza 0:3d4bd1fdeb2e 484 return status;
mustwillza 0:3d4bd1fdeb2e 485 }
mustwillza 0:3d4bd1fdeb2e 486
mustwillza 0:3d4bd1fdeb2e 487 if ((*bufferSize != 2) || (validBits != 0))
mustwillza 0:3d4bd1fdeb2e 488 { // ATQA must be exactly 16 bits.
mustwillza 0:3d4bd1fdeb2e 489 return STATUS_ERROR;
mustwillza 0:3d4bd1fdeb2e 490 }
mustwillza 0:3d4bd1fdeb2e 491
mustwillza 0:3d4bd1fdeb2e 492 return STATUS_OK;
mustwillza 0:3d4bd1fdeb2e 493 } // End PICC_REQA_or_WUPA()
mustwillza 0:3d4bd1fdeb2e 494
mustwillza 0:3d4bd1fdeb2e 495 /*
mustwillza 0:3d4bd1fdeb2e 496 * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
mustwillza 0:3d4bd1fdeb2e 497 */
mustwillza 0:3d4bd1fdeb2e 498 uint8_t MFRC522::PICC_Select(Uid *uid, uint8_t validBits)
mustwillza 0:3d4bd1fdeb2e 499 {
mustwillza 0:3d4bd1fdeb2e 500 bool uidComplete;
mustwillza 0:3d4bd1fdeb2e 501 bool selectDone;
mustwillza 0:3d4bd1fdeb2e 502 bool useCascadeTag;
mustwillza 0:3d4bd1fdeb2e 503 uint8_t cascadeLevel = 1;
mustwillza 0:3d4bd1fdeb2e 504 uint8_t result;
mustwillza 0:3d4bd1fdeb2e 505 uint8_t count;
mustwillza 0:3d4bd1fdeb2e 506 uint8_t index;
mustwillza 0:3d4bd1fdeb2e 507 uint8_t uidIndex; // The first index in uid->uidByte[] that is used in the current Cascade Level.
mustwillza 0:3d4bd1fdeb2e 508 uint8_t currentLevelKnownBits; // The number of known UID bits in the current Cascade Level.
mustwillza 0:3d4bd1fdeb2e 509 uint8_t buffer[9]; // The SELECT/ANTICOLLISION commands uses a 7 byte standard frame + 2 bytes CRC_A
mustwillza 0:3d4bd1fdeb2e 510 uint8_t bufferUsed; // The number of bytes used in the buffer, ie the number of bytes to transfer to the FIFO.
mustwillza 0:3d4bd1fdeb2e 511 uint8_t rxAlign; // Used in BitFramingReg. Defines the bit position for the first bit received.
mustwillza 0:3d4bd1fdeb2e 512 uint8_t txLastBits; // Used in BitFramingReg. The number of valid bits in the last transmitted byte.
mustwillza 0:3d4bd1fdeb2e 513 uint8_t *responseBuffer;
mustwillza 0:3d4bd1fdeb2e 514 uint8_t responseLength;
mustwillza 0:3d4bd1fdeb2e 515
mustwillza 0:3d4bd1fdeb2e 516 // Description of buffer structure:
mustwillza 0:3d4bd1fdeb2e 517 // Byte 0: SEL Indicates the Cascade Level: PICC_CMD_SEL_CL1, PICC_CMD_SEL_CL2 or PICC_CMD_SEL_CL3
mustwillza 0:3d4bd1fdeb2e 518 // Byte 1: NVB Number of Valid Bits (in complete command, not just the UID): High nibble: complete bytes, Low nibble: Extra bits.
mustwillza 0:3d4bd1fdeb2e 519 // Byte 2: UID-data or CT See explanation below. CT means Cascade Tag.
mustwillza 0:3d4bd1fdeb2e 520 // Byte 3: UID-data
mustwillza 0:3d4bd1fdeb2e 521 // Byte 4: UID-data
mustwillza 0:3d4bd1fdeb2e 522 // Byte 5: UID-data
mustwillza 0:3d4bd1fdeb2e 523 // Byte 6: BCC Block Check Character - XOR of bytes 2-5
mustwillza 0:3d4bd1fdeb2e 524 // Byte 7: CRC_A
mustwillza 0:3d4bd1fdeb2e 525 // Byte 8: CRC_A
mustwillza 0:3d4bd1fdeb2e 526 // The BCC and CRC_A is only transmitted if we know all the UID bits of the current Cascade Level.
mustwillza 0:3d4bd1fdeb2e 527 //
mustwillza 0:3d4bd1fdeb2e 528 // Description of bytes 2-5: (Section 6.5.4 of the ISO/IEC 14443-3 draft: UID contents and cascade levels)
mustwillza 0:3d4bd1fdeb2e 529 // UID size Cascade level Byte2 Byte3 Byte4 Byte5
mustwillza 0:3d4bd1fdeb2e 530 // ======== ============= ===== ===== ===== =====
mustwillza 0:3d4bd1fdeb2e 531 // 4 bytes 1 uid0 uid1 uid2 uid3
mustwillza 0:3d4bd1fdeb2e 532 // 7 bytes 1 CT uid0 uid1 uid2
mustwillza 0:3d4bd1fdeb2e 533 // 2 uid3 uid4 uid5 uid6
mustwillza 0:3d4bd1fdeb2e 534 // 10 bytes 1 CT uid0 uid1 uid2
mustwillza 0:3d4bd1fdeb2e 535 // 2 CT uid3 uid4 uid5
mustwillza 0:3d4bd1fdeb2e 536 // 3 uid6 uid7 uid8 uid9
mustwillza 0:3d4bd1fdeb2e 537
mustwillza 0:3d4bd1fdeb2e 538 // Sanity checks
mustwillza 0:3d4bd1fdeb2e 539 if (validBits > 80)
mustwillza 0:3d4bd1fdeb2e 540 {
mustwillza 0:3d4bd1fdeb2e 541 return STATUS_INVALID;
mustwillza 0:3d4bd1fdeb2e 542 }
mustwillza 0:3d4bd1fdeb2e 543
mustwillza 0:3d4bd1fdeb2e 544 // Prepare MFRC522
mustwillza 0:3d4bd1fdeb2e 545 // ValuesAfterColl=1 => Bits received after collision are cleared.
mustwillza 0:3d4bd1fdeb2e 546 PCD_ClrRegisterBits(CollReg, 0x80);
mustwillza 0:3d4bd1fdeb2e 547
mustwillza 0:3d4bd1fdeb2e 548 // Repeat Cascade Level loop until we have a complete UID.
mustwillza 0:3d4bd1fdeb2e 549 uidComplete = false;
mustwillza 0:3d4bd1fdeb2e 550 while ( ! uidComplete)
mustwillza 0:3d4bd1fdeb2e 551 {
mustwillza 0:3d4bd1fdeb2e 552 // Set the Cascade Level in the SEL byte, find out if we need to use the Cascade Tag in byte 2.
mustwillza 0:3d4bd1fdeb2e 553 switch (cascadeLevel)
mustwillza 0:3d4bd1fdeb2e 554 {
mustwillza 0:3d4bd1fdeb2e 555 case 1:
mustwillza 0:3d4bd1fdeb2e 556 buffer[0] = PICC_CMD_SEL_CL1;
mustwillza 0:3d4bd1fdeb2e 557 uidIndex = 0;
mustwillza 0:3d4bd1fdeb2e 558 useCascadeTag = validBits && (uid->size > 4); // When we know that the UID has more than 4 bytes
mustwillza 0:3d4bd1fdeb2e 559 break;
mustwillza 0:3d4bd1fdeb2e 560
mustwillza 0:3d4bd1fdeb2e 561 case 2:
mustwillza 0:3d4bd1fdeb2e 562 buffer[0] = PICC_CMD_SEL_CL2;
mustwillza 0:3d4bd1fdeb2e 563 uidIndex = 3;
mustwillza 0:3d4bd1fdeb2e 564 useCascadeTag = validBits && (uid->size > 7); // When we know that the UID has more than 7 bytes
mustwillza 0:3d4bd1fdeb2e 565 break;
mustwillza 0:3d4bd1fdeb2e 566
mustwillza 0:3d4bd1fdeb2e 567 case 3:
mustwillza 0:3d4bd1fdeb2e 568 buffer[0] = PICC_CMD_SEL_CL3;
mustwillza 0:3d4bd1fdeb2e 569 uidIndex = 6;
mustwillza 0:3d4bd1fdeb2e 570 useCascadeTag = false; // Never used in CL3.
mustwillza 0:3d4bd1fdeb2e 571 break;
mustwillza 0:3d4bd1fdeb2e 572
mustwillza 0:3d4bd1fdeb2e 573 default:
mustwillza 0:3d4bd1fdeb2e 574 return STATUS_INTERNAL_ERROR;
mustwillza 0:3d4bd1fdeb2e 575 //break;
mustwillza 0:3d4bd1fdeb2e 576 }
mustwillza 0:3d4bd1fdeb2e 577
mustwillza 0:3d4bd1fdeb2e 578 // How many UID bits are known in this Cascade Level?
mustwillza 0:3d4bd1fdeb2e 579 if(validBits > (8 * uidIndex))
mustwillza 0:3d4bd1fdeb2e 580 {
mustwillza 0:3d4bd1fdeb2e 581 currentLevelKnownBits = validBits - (8 * uidIndex);
mustwillza 0:3d4bd1fdeb2e 582 }
mustwillza 0:3d4bd1fdeb2e 583 else
mustwillza 0:3d4bd1fdeb2e 584 {
mustwillza 0:3d4bd1fdeb2e 585 currentLevelKnownBits = 0;
mustwillza 0:3d4bd1fdeb2e 586 }
mustwillza 0:3d4bd1fdeb2e 587
mustwillza 0:3d4bd1fdeb2e 588 // Copy the known bits from uid->uidByte[] to buffer[]
mustwillza 0:3d4bd1fdeb2e 589 index = 2; // destination index in buffer[]
mustwillza 0:3d4bd1fdeb2e 590 if (useCascadeTag)
mustwillza 0:3d4bd1fdeb2e 591 {
mustwillza 0:3d4bd1fdeb2e 592 buffer[index++] = PICC_CMD_CT;
mustwillza 0:3d4bd1fdeb2e 593 }
mustwillza 0:3d4bd1fdeb2e 594
mustwillza 0:3d4bd1fdeb2e 595 uint8_t bytesToCopy = currentLevelKnownBits / 8 + (currentLevelKnownBits % 8 ? 1 : 0); // The number of bytes needed to represent the known bits for this level.
mustwillza 0:3d4bd1fdeb2e 596 if (bytesToCopy)
mustwillza 0:3d4bd1fdeb2e 597 {
mustwillza 0:3d4bd1fdeb2e 598 // Max 4 bytes in each Cascade Level. Only 3 left if we use the Cascade Tag
mustwillza 0:3d4bd1fdeb2e 599 uint8_t maxBytes = useCascadeTag ? 3 : 4;
mustwillza 0:3d4bd1fdeb2e 600 if (bytesToCopy > maxBytes)
mustwillza 0:3d4bd1fdeb2e 601 {
mustwillza 0:3d4bd1fdeb2e 602 bytesToCopy = maxBytes;
mustwillza 0:3d4bd1fdeb2e 603 }
mustwillza 0:3d4bd1fdeb2e 604
mustwillza 0:3d4bd1fdeb2e 605 for (count = 0; count < bytesToCopy; count++)
mustwillza 0:3d4bd1fdeb2e 606 {
mustwillza 0:3d4bd1fdeb2e 607 buffer[index++] = uid->uidByte[uidIndex + count];
mustwillza 0:3d4bd1fdeb2e 608 }
mustwillza 0:3d4bd1fdeb2e 609 }
mustwillza 0:3d4bd1fdeb2e 610
mustwillza 0:3d4bd1fdeb2e 611 // Now that the data has been copied we need to include the 8 bits in CT in currentLevelKnownBits
mustwillza 0:3d4bd1fdeb2e 612 if (useCascadeTag)
mustwillza 0:3d4bd1fdeb2e 613 {
mustwillza 0:3d4bd1fdeb2e 614 currentLevelKnownBits += 8;
mustwillza 0:3d4bd1fdeb2e 615 }
mustwillza 0:3d4bd1fdeb2e 616
mustwillza 0:3d4bd1fdeb2e 617 // Repeat anti collision loop until we can transmit all UID bits + BCC and receive a SAK - max 32 iterations.
mustwillza 0:3d4bd1fdeb2e 618 selectDone = false;
mustwillza 0:3d4bd1fdeb2e 619 while ( ! selectDone)
mustwillza 0:3d4bd1fdeb2e 620 {
mustwillza 0:3d4bd1fdeb2e 621 // Find out how many bits and bytes to send and receive.
mustwillza 0:3d4bd1fdeb2e 622 if (currentLevelKnownBits >= 32)
mustwillza 0:3d4bd1fdeb2e 623 { // All UID bits in this Cascade Level are known. This is a SELECT.
mustwillza 0:3d4bd1fdeb2e 624 //Serial.print("SELECT: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
mustwillza 0:3d4bd1fdeb2e 625 buffer[1] = 0x70; // NVB - Number of Valid Bits: Seven whole bytes
mustwillza 0:3d4bd1fdeb2e 626
mustwillza 0:3d4bd1fdeb2e 627 // Calulate BCC - Block Check Character
mustwillza 0:3d4bd1fdeb2e 628 buffer[6] = buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5];
mustwillza 0:3d4bd1fdeb2e 629
mustwillza 0:3d4bd1fdeb2e 630 // Calculate CRC_A
mustwillza 0:3d4bd1fdeb2e 631 result = PCD_CalculateCRC(buffer, 7, &buffer[7]);
mustwillza 0:3d4bd1fdeb2e 632 if (result != STATUS_OK)
mustwillza 0:3d4bd1fdeb2e 633 {
mustwillza 0:3d4bd1fdeb2e 634 return result;
mustwillza 0:3d4bd1fdeb2e 635 }
mustwillza 0:3d4bd1fdeb2e 636
mustwillza 0:3d4bd1fdeb2e 637 txLastBits = 0; // 0 => All 8 bits are valid.
mustwillza 0:3d4bd1fdeb2e 638 bufferUsed = 9;
mustwillza 0:3d4bd1fdeb2e 639
mustwillza 0:3d4bd1fdeb2e 640 // Store response in the last 3 bytes of buffer (BCC and CRC_A - not needed after tx)
mustwillza 0:3d4bd1fdeb2e 641 responseBuffer = &buffer[6];
mustwillza 0:3d4bd1fdeb2e 642 responseLength = 3;
mustwillza 0:3d4bd1fdeb2e 643 }
mustwillza 0:3d4bd1fdeb2e 644 else
mustwillza 0:3d4bd1fdeb2e 645 { // This is an ANTICOLLISION.
mustwillza 0:3d4bd1fdeb2e 646 //Serial.print("ANTICOLLISION: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
mustwillza 0:3d4bd1fdeb2e 647 txLastBits = currentLevelKnownBits % 8;
mustwillza 0:3d4bd1fdeb2e 648 count = currentLevelKnownBits / 8; // Number of whole bytes in the UID part.
mustwillza 0:3d4bd1fdeb2e 649 index = 2 + count; // Number of whole bytes: SEL + NVB + UIDs
mustwillza 0:3d4bd1fdeb2e 650 buffer[1] = (index << 4) + txLastBits; // NVB - Number of Valid Bits
mustwillza 0:3d4bd1fdeb2e 651 bufferUsed = index + (txLastBits ? 1 : 0);
mustwillza 0:3d4bd1fdeb2e 652
mustwillza 0:3d4bd1fdeb2e 653 // Store response in the unused part of buffer
mustwillza 0:3d4bd1fdeb2e 654 responseBuffer = &buffer[index];
mustwillza 0:3d4bd1fdeb2e 655 responseLength = sizeof(buffer) - index;
mustwillza 0:3d4bd1fdeb2e 656 }
mustwillza 0:3d4bd1fdeb2e 657
mustwillza 0:3d4bd1fdeb2e 658 // Set bit adjustments
mustwillza 0:3d4bd1fdeb2e 659 rxAlign = txLastBits; // Having a seperate variable is overkill. But it makes the next line easier to read.
mustwillza 0:3d4bd1fdeb2e 660 PCD_WriteRegister(BitFramingReg, (rxAlign << 4) + txLastBits); // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
mustwillza 0:3d4bd1fdeb2e 661
mustwillza 0:3d4bd1fdeb2e 662 // Transmit the buffer and receive the response.
mustwillza 0:3d4bd1fdeb2e 663 result = PCD_TransceiveData(buffer, bufferUsed, responseBuffer, &responseLength, &txLastBits, rxAlign);
mustwillza 0:3d4bd1fdeb2e 664 if (result == STATUS_COLLISION)
mustwillza 0:3d4bd1fdeb2e 665 { // More than one PICC in the field => collision.
mustwillza 0:3d4bd1fdeb2e 666 result = PCD_ReadRegister(CollReg); // CollReg[7..0] bits are: ValuesAfterColl reserved CollPosNotValid CollPos[4:0]
mustwillza 0:3d4bd1fdeb2e 667 if (result & 0x20)
mustwillza 0:3d4bd1fdeb2e 668 { // CollPosNotValid
mustwillza 0:3d4bd1fdeb2e 669 return STATUS_COLLISION; // Without a valid collision position we cannot continue
mustwillza 0:3d4bd1fdeb2e 670 }
mustwillza 0:3d4bd1fdeb2e 671
mustwillza 0:3d4bd1fdeb2e 672 uint8_t collisionPos = result & 0x1F; // Values 0-31, 0 means bit 32.
mustwillza 0:3d4bd1fdeb2e 673 if (collisionPos == 0)
mustwillza 0:3d4bd1fdeb2e 674 {
mustwillza 0:3d4bd1fdeb2e 675 collisionPos = 32;
mustwillza 0:3d4bd1fdeb2e 676 }
mustwillza 0:3d4bd1fdeb2e 677
mustwillza 0:3d4bd1fdeb2e 678 if (collisionPos <= currentLevelKnownBits)
mustwillza 0:3d4bd1fdeb2e 679 { // No progress - should not happen
mustwillza 0:3d4bd1fdeb2e 680 return STATUS_INTERNAL_ERROR;
mustwillza 0:3d4bd1fdeb2e 681 }
mustwillza 0:3d4bd1fdeb2e 682
mustwillza 0:3d4bd1fdeb2e 683 // Choose the PICC with the bit set.
mustwillza 0:3d4bd1fdeb2e 684 currentLevelKnownBits = collisionPos;
mustwillza 0:3d4bd1fdeb2e 685 count = (currentLevelKnownBits - 1) % 8; // The bit to modify
mustwillza 0:3d4bd1fdeb2e 686 index = 1 + (currentLevelKnownBits / 8) + (count ? 1 : 0); // First byte is index 0.
mustwillza 0:3d4bd1fdeb2e 687 buffer[index] |= (1 << count);
mustwillza 0:3d4bd1fdeb2e 688 }
mustwillza 0:3d4bd1fdeb2e 689 else if (result != STATUS_OK)
mustwillza 0:3d4bd1fdeb2e 690 {
mustwillza 0:3d4bd1fdeb2e 691 return result;
mustwillza 0:3d4bd1fdeb2e 692 }
mustwillza 0:3d4bd1fdeb2e 693 else
mustwillza 0:3d4bd1fdeb2e 694 { // STATUS_OK
mustwillza 0:3d4bd1fdeb2e 695 if (currentLevelKnownBits >= 32)
mustwillza 0:3d4bd1fdeb2e 696 { // This was a SELECT.
mustwillza 0:3d4bd1fdeb2e 697 selectDone = true; // No more anticollision
mustwillza 0:3d4bd1fdeb2e 698 // We continue below outside the while.
mustwillza 0:3d4bd1fdeb2e 699 }
mustwillza 0:3d4bd1fdeb2e 700 else
mustwillza 0:3d4bd1fdeb2e 701 { // This was an ANTICOLLISION.
mustwillza 0:3d4bd1fdeb2e 702 // We now have all 32 bits of the UID in this Cascade Level
mustwillza 0:3d4bd1fdeb2e 703 currentLevelKnownBits = 32;
mustwillza 0:3d4bd1fdeb2e 704 // Run loop again to do the SELECT.
mustwillza 0:3d4bd1fdeb2e 705 }
mustwillza 0:3d4bd1fdeb2e 706 }
mustwillza 0:3d4bd1fdeb2e 707 } // End of while ( ! selectDone)
mustwillza 0:3d4bd1fdeb2e 708
mustwillza 0:3d4bd1fdeb2e 709 // We do not check the CBB - it was constructed by us above.
mustwillza 0:3d4bd1fdeb2e 710
mustwillza 0:3d4bd1fdeb2e 711 // Copy the found UID bytes from buffer[] to uid->uidByte[]
mustwillza 0:3d4bd1fdeb2e 712 index = (buffer[2] == PICC_CMD_CT) ? 3 : 2; // source index in buffer[]
mustwillza 0:3d4bd1fdeb2e 713 bytesToCopy = (buffer[2] == PICC_CMD_CT) ? 3 : 4;
mustwillza 0:3d4bd1fdeb2e 714 for (count = 0; count < bytesToCopy; count++)
mustwillza 0:3d4bd1fdeb2e 715 {
mustwillza 0:3d4bd1fdeb2e 716 uid->uidByte[uidIndex + count] = buffer[index++];
mustwillza 0:3d4bd1fdeb2e 717 }
mustwillza 0:3d4bd1fdeb2e 718
mustwillza 0:3d4bd1fdeb2e 719 // Check response SAK (Select Acknowledge)
mustwillza 0:3d4bd1fdeb2e 720 if (responseLength != 3 || txLastBits != 0)
mustwillza 0:3d4bd1fdeb2e 721 { // SAK must be exactly 24 bits (1 byte + CRC_A).
mustwillza 0:3d4bd1fdeb2e 722 return STATUS_ERROR;
mustwillza 0:3d4bd1fdeb2e 723 }
mustwillza 0:3d4bd1fdeb2e 724
mustwillza 0:3d4bd1fdeb2e 725 // Verify CRC_A - do our own calculation and store the control in buffer[2..3] - those bytes are not needed anymore.
mustwillza 0:3d4bd1fdeb2e 726 result = PCD_CalculateCRC(responseBuffer, 1, &buffer[2]);
mustwillza 0:3d4bd1fdeb2e 727 if (result != STATUS_OK)
mustwillza 0:3d4bd1fdeb2e 728 {
mustwillza 0:3d4bd1fdeb2e 729 return result;
mustwillza 0:3d4bd1fdeb2e 730 }
mustwillza 0:3d4bd1fdeb2e 731
mustwillza 0:3d4bd1fdeb2e 732 if ((buffer[2] != responseBuffer[1]) || (buffer[3] != responseBuffer[2]))
mustwillza 0:3d4bd1fdeb2e 733 {
mustwillza 0:3d4bd1fdeb2e 734 return STATUS_CRC_WRONG;
mustwillza 0:3d4bd1fdeb2e 735 }
mustwillza 0:3d4bd1fdeb2e 736
mustwillza 0:3d4bd1fdeb2e 737 if (responseBuffer[0] & 0x04)
mustwillza 0:3d4bd1fdeb2e 738 { // Cascade bit set - UID not complete yes
mustwillza 0:3d4bd1fdeb2e 739 cascadeLevel++;
mustwillza 0:3d4bd1fdeb2e 740 }
mustwillza 0:3d4bd1fdeb2e 741 else
mustwillza 0:3d4bd1fdeb2e 742 {
mustwillza 0:3d4bd1fdeb2e 743 uidComplete = true;
mustwillza 0:3d4bd1fdeb2e 744 uid->sak = responseBuffer[0];
mustwillza 0:3d4bd1fdeb2e 745 }
mustwillza 0:3d4bd1fdeb2e 746 } // End of while ( ! uidComplete)
mustwillza 0:3d4bd1fdeb2e 747
mustwillza 0:3d4bd1fdeb2e 748 // Set correct uid->size
mustwillza 0:3d4bd1fdeb2e 749 uid->size = 3 * cascadeLevel + 1;
mustwillza 0:3d4bd1fdeb2e 750
mustwillza 0:3d4bd1fdeb2e 751 return STATUS_OK;
mustwillza 0:3d4bd1fdeb2e 752 } // End PICC_Select()
mustwillza 0:3d4bd1fdeb2e 753
mustwillza 0:3d4bd1fdeb2e 754 /*
mustwillza 0:3d4bd1fdeb2e 755 * Instructs a PICC in state ACTIVE(*) to go to state HALT.
mustwillza 0:3d4bd1fdeb2e 756 */
mustwillza 0:3d4bd1fdeb2e 757 uint8_t MFRC522::PICC_HaltA()
mustwillza 0:3d4bd1fdeb2e 758 {
mustwillza 0:3d4bd1fdeb2e 759 uint8_t result;
mustwillza 0:3d4bd1fdeb2e 760 uint8_t buffer[4];
mustwillza 0:3d4bd1fdeb2e 761
mustwillza 0:3d4bd1fdeb2e 762 // Build command buffer
mustwillza 0:3d4bd1fdeb2e 763 buffer[0] = PICC_CMD_HLTA;
mustwillza 0:3d4bd1fdeb2e 764 buffer[1] = 0;
mustwillza 0:3d4bd1fdeb2e 765
mustwillza 0:3d4bd1fdeb2e 766 // Calculate CRC_A
mustwillza 0:3d4bd1fdeb2e 767 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
mustwillza 0:3d4bd1fdeb2e 768 if (result == STATUS_OK)
mustwillza 0:3d4bd1fdeb2e 769 {
mustwillza 0:3d4bd1fdeb2e 770 // Send the command.
mustwillza 0:3d4bd1fdeb2e 771 // The standard says:
mustwillza 0:3d4bd1fdeb2e 772 // If the PICC responds with any modulation during a period of 1 ms after the end of the frame containing the
mustwillza 0:3d4bd1fdeb2e 773 // HLTA command, this response shall be interpreted as 'not acknowledge'.
mustwillza 0:3d4bd1fdeb2e 774 // We interpret that this way: Only STATUS_TIMEOUT is an success.
mustwillza 0:3d4bd1fdeb2e 775 result = PCD_TransceiveData(buffer, sizeof(buffer), NULL, 0);
mustwillza 0:3d4bd1fdeb2e 776 if (result == STATUS_TIMEOUT)
mustwillza 0:3d4bd1fdeb2e 777 {
mustwillza 0:3d4bd1fdeb2e 778 result = STATUS_OK;
mustwillza 0:3d4bd1fdeb2e 779 }
mustwillza 0:3d4bd1fdeb2e 780 else if (result == STATUS_OK)
mustwillza 0:3d4bd1fdeb2e 781 { // That is ironically NOT ok in this case ;-)
mustwillza 0:3d4bd1fdeb2e 782 result = STATUS_ERROR;
mustwillza 0:3d4bd1fdeb2e 783 }
mustwillza 0:3d4bd1fdeb2e 784 }
mustwillza 0:3d4bd1fdeb2e 785
mustwillza 0:3d4bd1fdeb2e 786 return result;
mustwillza 0:3d4bd1fdeb2e 787 } // End PICC_HaltA()
mustwillza 0:3d4bd1fdeb2e 788
mustwillza 0:3d4bd1fdeb2e 789
mustwillza 0:3d4bd1fdeb2e 790 /////////////////////////////////////////////////////////////////////////////////////
mustwillza 0:3d4bd1fdeb2e 791 // Functions for communicating with MIFARE PICCs
mustwillza 0:3d4bd1fdeb2e 792 /////////////////////////////////////////////////////////////////////////////////////
mustwillza 0:3d4bd1fdeb2e 793
mustwillza 0:3d4bd1fdeb2e 794 /*
mustwillza 0:3d4bd1fdeb2e 795 * Executes the MFRC522 MFAuthent command.
mustwillza 0:3d4bd1fdeb2e 796 */
mustwillza 0:3d4bd1fdeb2e 797 uint8_t MFRC522::PCD_Authenticate(uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid)
mustwillza 0:3d4bd1fdeb2e 798 {
mustwillza 0:3d4bd1fdeb2e 799 uint8_t i, waitIRq = 0x10; // IdleIRq
mustwillza 0:3d4bd1fdeb2e 800
mustwillza 0:3d4bd1fdeb2e 801 // Build command buffer
mustwillza 0:3d4bd1fdeb2e 802 uint8_t sendData[12];
mustwillza 0:3d4bd1fdeb2e 803 sendData[0] = command;
mustwillza 0:3d4bd1fdeb2e 804 sendData[1] = blockAddr;
mustwillza 0:3d4bd1fdeb2e 805
mustwillza 0:3d4bd1fdeb2e 806 for (i = 0; i < MF_KEY_SIZE; i++)
mustwillza 0:3d4bd1fdeb2e 807 { // 6 key bytes
mustwillza 0:3d4bd1fdeb2e 808 sendData[2+i] = key->keyByte[i];
mustwillza 0:3d4bd1fdeb2e 809 }
mustwillza 0:3d4bd1fdeb2e 810
mustwillza 0:3d4bd1fdeb2e 811 for (i = 0; i < 4; i++)
mustwillza 0:3d4bd1fdeb2e 812 { // The first 4 bytes of the UID
mustwillza 0:3d4bd1fdeb2e 813 sendData[8+i] = uid->uidByte[i];
mustwillza 0:3d4bd1fdeb2e 814 }
mustwillza 0:3d4bd1fdeb2e 815
mustwillza 0:3d4bd1fdeb2e 816 // Start the authentication.
mustwillza 0:3d4bd1fdeb2e 817 return PCD_CommunicateWithPICC(PCD_MFAuthent, waitIRq, &sendData[0], sizeof(sendData));
mustwillza 0:3d4bd1fdeb2e 818 } // End PCD_Authenticate()
mustwillza 0:3d4bd1fdeb2e 819
mustwillza 0:3d4bd1fdeb2e 820 /*
mustwillza 0:3d4bd1fdeb2e 821 * Used to exit the PCD from its authenticated state.
mustwillza 0:3d4bd1fdeb2e 822 * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
mustwillza 0:3d4bd1fdeb2e 823 */
mustwillza 0:3d4bd1fdeb2e 824 void MFRC522::PCD_StopCrypto1()
mustwillza 0:3d4bd1fdeb2e 825 {
mustwillza 0:3d4bd1fdeb2e 826 // Clear MFCrypto1On bit
mustwillza 0:3d4bd1fdeb2e 827 PCD_ClrRegisterBits(Status2Reg, 0x08); // Status2Reg[7..0] bits are: TempSensClear I2CForceHS reserved reserved MFCrypto1On ModemState[2:0]
mustwillza 0:3d4bd1fdeb2e 828 } // End PCD_StopCrypto1()
mustwillza 0:3d4bd1fdeb2e 829
mustwillza 0:3d4bd1fdeb2e 830 /*
mustwillza 0:3d4bd1fdeb2e 831 * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
mustwillza 0:3d4bd1fdeb2e 832 */
mustwillza 0:3d4bd1fdeb2e 833 uint8_t MFRC522::MIFARE_Read(uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize)
mustwillza 0:3d4bd1fdeb2e 834 {
mustwillza 0:3d4bd1fdeb2e 835 uint8_t result = STATUS_NO_ROOM;
mustwillza 0:3d4bd1fdeb2e 836
mustwillza 0:3d4bd1fdeb2e 837 // Sanity check
mustwillza 0:3d4bd1fdeb2e 838 if ((buffer == NULL) || (*bufferSize < 18))
mustwillza 0:3d4bd1fdeb2e 839 {
mustwillza 0:3d4bd1fdeb2e 840 return result;
mustwillza 0:3d4bd1fdeb2e 841 }
mustwillza 0:3d4bd1fdeb2e 842
mustwillza 0:3d4bd1fdeb2e 843 // Build command buffer
mustwillza 0:3d4bd1fdeb2e 844 buffer[0] = PICC_CMD_MF_READ;
mustwillza 0:3d4bd1fdeb2e 845 buffer[1] = blockAddr;
mustwillza 0:3d4bd1fdeb2e 846
mustwillza 0:3d4bd1fdeb2e 847 // Calculate CRC_A
mustwillza 0:3d4bd1fdeb2e 848 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
mustwillza 0:3d4bd1fdeb2e 849 if (result != STATUS_OK)
mustwillza 0:3d4bd1fdeb2e 850 {
mustwillza 0:3d4bd1fdeb2e 851 return result;
mustwillza 0:3d4bd1fdeb2e 852 }
mustwillza 0:3d4bd1fdeb2e 853
mustwillza 0:3d4bd1fdeb2e 854 // Transmit the buffer and receive the response, validate CRC_A.
mustwillza 0:3d4bd1fdeb2e 855 return PCD_TransceiveData(buffer, 4, buffer, bufferSize, NULL, 0, true);
mustwillza 0:3d4bd1fdeb2e 856 } // End MIFARE_Read()
mustwillza 0:3d4bd1fdeb2e 857
mustwillza 0:3d4bd1fdeb2e 858 /*
mustwillza 0:3d4bd1fdeb2e 859 * Writes 16 bytes to the active PICC.
mustwillza 0:3d4bd1fdeb2e 860 */
mustwillza 0:3d4bd1fdeb2e 861 uint8_t MFRC522::MIFARE_Write(uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize)
mustwillza 0:3d4bd1fdeb2e 862 {
mustwillza 0:3d4bd1fdeb2e 863 uint8_t result;
mustwillza 0:3d4bd1fdeb2e 864
mustwillza 0:3d4bd1fdeb2e 865 // Sanity check
mustwillza 0:3d4bd1fdeb2e 866 if (buffer == NULL || bufferSize < 16)
mustwillza 0:3d4bd1fdeb2e 867 {
mustwillza 0:3d4bd1fdeb2e 868 return STATUS_INVALID;
mustwillza 0:3d4bd1fdeb2e 869 }
mustwillza 0:3d4bd1fdeb2e 870
mustwillza 0:3d4bd1fdeb2e 871 // Mifare Classic protocol requires two communications to perform a write.
mustwillza 0:3d4bd1fdeb2e 872 // Step 1: Tell the PICC we want to write to block blockAddr.
mustwillza 0:3d4bd1fdeb2e 873 uint8_t cmdBuffer[2];
mustwillza 0:3d4bd1fdeb2e 874 cmdBuffer[0] = PICC_CMD_MF_WRITE;
mustwillza 0:3d4bd1fdeb2e 875 cmdBuffer[1] = blockAddr;
mustwillza 0:3d4bd1fdeb2e 876 // Adds CRC_A and checks that the response is MF_ACK.
mustwillza 0:3d4bd1fdeb2e 877 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
mustwillza 0:3d4bd1fdeb2e 878 if (result != STATUS_OK)
mustwillza 0:3d4bd1fdeb2e 879 {
mustwillza 0:3d4bd1fdeb2e 880 return result;
mustwillza 0:3d4bd1fdeb2e 881 }
mustwillza 0:3d4bd1fdeb2e 882
mustwillza 0:3d4bd1fdeb2e 883 // Step 2: Transfer the data
mustwillza 0:3d4bd1fdeb2e 884 // Adds CRC_A and checks that the response is MF_ACK.
mustwillza 0:3d4bd1fdeb2e 885 result = PCD_MIFARE_Transceive(buffer, bufferSize);
mustwillza 0:3d4bd1fdeb2e 886 if (result != STATUS_OK)
mustwillza 0:3d4bd1fdeb2e 887 {
mustwillza 0:3d4bd1fdeb2e 888 return result;
mustwillza 0:3d4bd1fdeb2e 889 }
mustwillza 0:3d4bd1fdeb2e 890
mustwillza 0:3d4bd1fdeb2e 891 return STATUS_OK;
mustwillza 0:3d4bd1fdeb2e 892 } // End MIFARE_Write()
mustwillza 0:3d4bd1fdeb2e 893
mustwillza 0:3d4bd1fdeb2e 894 /*
mustwillza 0:3d4bd1fdeb2e 895 * Writes a 4 byte page to the active MIFARE Ultralight PICC.
mustwillza 0:3d4bd1fdeb2e 896 */
mustwillza 0:3d4bd1fdeb2e 897 uint8_t MFRC522::MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize)
mustwillza 0:3d4bd1fdeb2e 898 {
mustwillza 0:3d4bd1fdeb2e 899 uint8_t result;
mustwillza 0:3d4bd1fdeb2e 900
mustwillza 0:3d4bd1fdeb2e 901 // Sanity check
mustwillza 0:3d4bd1fdeb2e 902 if (buffer == NULL || bufferSize < 4)
mustwillza 0:3d4bd1fdeb2e 903 {
mustwillza 0:3d4bd1fdeb2e 904 return STATUS_INVALID;
mustwillza 0:3d4bd1fdeb2e 905 }
mustwillza 0:3d4bd1fdeb2e 906
mustwillza 0:3d4bd1fdeb2e 907 // Build commmand buffer
mustwillza 0:3d4bd1fdeb2e 908 uint8_t cmdBuffer[6];
mustwillza 0:3d4bd1fdeb2e 909 cmdBuffer[0] = PICC_CMD_UL_WRITE;
mustwillza 0:3d4bd1fdeb2e 910 cmdBuffer[1] = page;
mustwillza 0:3d4bd1fdeb2e 911 memcpy(&cmdBuffer[2], buffer, 4);
mustwillza 0:3d4bd1fdeb2e 912
mustwillza 0:3d4bd1fdeb2e 913 // Perform the write
mustwillza 0:3d4bd1fdeb2e 914 result = PCD_MIFARE_Transceive(cmdBuffer, 6); // Adds CRC_A and checks that the response is MF_ACK.
mustwillza 0:3d4bd1fdeb2e 915 if (result != STATUS_OK)
mustwillza 0:3d4bd1fdeb2e 916 {
mustwillza 0:3d4bd1fdeb2e 917 return result;
mustwillza 0:3d4bd1fdeb2e 918 }
mustwillza 0:3d4bd1fdeb2e 919
mustwillza 0:3d4bd1fdeb2e 920 return STATUS_OK;
mustwillza 0:3d4bd1fdeb2e 921 } // End MIFARE_Ultralight_Write()
mustwillza 0:3d4bd1fdeb2e 922
mustwillza 0:3d4bd1fdeb2e 923 /*
mustwillza 0:3d4bd1fdeb2e 924 * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
mustwillza 0:3d4bd1fdeb2e 925 */
mustwillza 0:3d4bd1fdeb2e 926 uint8_t MFRC522::MIFARE_Decrement(uint8_t blockAddr, uint32_t delta)
mustwillza 0:3d4bd1fdeb2e 927 {
mustwillza 0:3d4bd1fdeb2e 928 return MIFARE_TwoStepHelper(PICC_CMD_MF_DECREMENT, blockAddr, delta);
mustwillza 0:3d4bd1fdeb2e 929 } // End MIFARE_Decrement()
mustwillza 0:3d4bd1fdeb2e 930
mustwillza 0:3d4bd1fdeb2e 931 /*
mustwillza 0:3d4bd1fdeb2e 932 * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
mustwillza 0:3d4bd1fdeb2e 933 */
mustwillza 0:3d4bd1fdeb2e 934 uint8_t MFRC522::MIFARE_Increment(uint8_t blockAddr, uint32_t delta)
mustwillza 0:3d4bd1fdeb2e 935 {
mustwillza 0:3d4bd1fdeb2e 936 return MIFARE_TwoStepHelper(PICC_CMD_MF_INCREMENT, blockAddr, delta);
mustwillza 0:3d4bd1fdeb2e 937 } // End MIFARE_Increment()
mustwillza 0:3d4bd1fdeb2e 938
mustwillza 0:3d4bd1fdeb2e 939 /**
mustwillza 0:3d4bd1fdeb2e 940 * MIFARE Restore copies the value of the addressed block into a volatile memory.
mustwillza 0:3d4bd1fdeb2e 941 */
mustwillza 0:3d4bd1fdeb2e 942 uint8_t MFRC522::MIFARE_Restore(uint8_t blockAddr)
mustwillza 0:3d4bd1fdeb2e 943 {
mustwillza 0:3d4bd1fdeb2e 944 // The datasheet describes Restore as a two step operation, but does not explain what data to transfer in step 2.
mustwillza 0:3d4bd1fdeb2e 945 // Doing only a single step does not work, so I chose to transfer 0L in step two.
mustwillza 0:3d4bd1fdeb2e 946 return MIFARE_TwoStepHelper(PICC_CMD_MF_RESTORE, blockAddr, 0L);
mustwillza 0:3d4bd1fdeb2e 947 } // End MIFARE_Restore()
mustwillza 0:3d4bd1fdeb2e 948
mustwillza 0:3d4bd1fdeb2e 949 /*
mustwillza 0:3d4bd1fdeb2e 950 * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
mustwillza 0:3d4bd1fdeb2e 951 */
mustwillza 0:3d4bd1fdeb2e 952 uint8_t MFRC522::MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data)
mustwillza 0:3d4bd1fdeb2e 953 {
mustwillza 0:3d4bd1fdeb2e 954 uint8_t result;
mustwillza 0:3d4bd1fdeb2e 955 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
mustwillza 0:3d4bd1fdeb2e 956
mustwillza 0:3d4bd1fdeb2e 957 // Step 1: Tell the PICC the command and block address
mustwillza 0:3d4bd1fdeb2e 958 cmdBuffer[0] = command;
mustwillza 0:3d4bd1fdeb2e 959 cmdBuffer[1] = blockAddr;
mustwillza 0:3d4bd1fdeb2e 960
mustwillza 0:3d4bd1fdeb2e 961 // Adds CRC_A and checks that the response is MF_ACK.
mustwillza 0:3d4bd1fdeb2e 962 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
mustwillza 0:3d4bd1fdeb2e 963 if (result != STATUS_OK)
mustwillza 0:3d4bd1fdeb2e 964 {
mustwillza 0:3d4bd1fdeb2e 965 return result;
mustwillza 0:3d4bd1fdeb2e 966 }
mustwillza 0:3d4bd1fdeb2e 967
mustwillza 0:3d4bd1fdeb2e 968 // Step 2: Transfer the data
mustwillza 0:3d4bd1fdeb2e 969 // Adds CRC_A and accept timeout as success.
mustwillza 0:3d4bd1fdeb2e 970 result = PCD_MIFARE_Transceive((uint8_t *) &data, 4, true);
mustwillza 0:3d4bd1fdeb2e 971 if (result != STATUS_OK)
mustwillza 0:3d4bd1fdeb2e 972 {
mustwillza 0:3d4bd1fdeb2e 973 return result;
mustwillza 0:3d4bd1fdeb2e 974 }
mustwillza 0:3d4bd1fdeb2e 975
mustwillza 0:3d4bd1fdeb2e 976 return STATUS_OK;
mustwillza 0:3d4bd1fdeb2e 977 } // End MIFARE_TwoStepHelper()
mustwillza 0:3d4bd1fdeb2e 978
mustwillza 0:3d4bd1fdeb2e 979 /*
mustwillza 0:3d4bd1fdeb2e 980 * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
mustwillza 0:3d4bd1fdeb2e 981 */
mustwillza 0:3d4bd1fdeb2e 982 uint8_t MFRC522::MIFARE_Transfer(uint8_t blockAddr)
mustwillza 0:3d4bd1fdeb2e 983 {
mustwillza 0:3d4bd1fdeb2e 984 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
mustwillza 0:3d4bd1fdeb2e 985
mustwillza 0:3d4bd1fdeb2e 986 // Tell the PICC we want to transfer the result into block blockAddr.
mustwillza 0:3d4bd1fdeb2e 987 cmdBuffer[0] = PICC_CMD_MF_TRANSFER;
mustwillza 0:3d4bd1fdeb2e 988 cmdBuffer[1] = blockAddr;
mustwillza 0:3d4bd1fdeb2e 989
mustwillza 0:3d4bd1fdeb2e 990 // Adds CRC_A and checks that the response is MF_ACK.
mustwillza 0:3d4bd1fdeb2e 991 return PCD_MIFARE_Transceive(cmdBuffer, 2);
mustwillza 0:3d4bd1fdeb2e 992 } // End MIFARE_Transfer()
mustwillza 0:3d4bd1fdeb2e 993
mustwillza 0:3d4bd1fdeb2e 994
mustwillza 0:3d4bd1fdeb2e 995 /////////////////////////////////////////////////////////////////////////////////////
mustwillza 0:3d4bd1fdeb2e 996 // Support functions
mustwillza 0:3d4bd1fdeb2e 997 /////////////////////////////////////////////////////////////////////////////////////
mustwillza 0:3d4bd1fdeb2e 998
mustwillza 0:3d4bd1fdeb2e 999 /*
mustwillza 0:3d4bd1fdeb2e 1000 * Wrapper for MIFARE protocol communication.
mustwillza 0:3d4bd1fdeb2e 1001 * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
mustwillza 0:3d4bd1fdeb2e 1002 */
mustwillza 0:3d4bd1fdeb2e 1003 uint8_t MFRC522::PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout)
mustwillza 0:3d4bd1fdeb2e 1004 {
mustwillza 0:3d4bd1fdeb2e 1005 uint8_t result;
mustwillza 0:3d4bd1fdeb2e 1006 uint8_t cmdBuffer[18]; // We need room for 16 bytes data and 2 bytes CRC_A.
mustwillza 0:3d4bd1fdeb2e 1007
mustwillza 0:3d4bd1fdeb2e 1008 // Sanity check
mustwillza 0:3d4bd1fdeb2e 1009 if (sendData == NULL || sendLen > 16)
mustwillza 0:3d4bd1fdeb2e 1010 {
mustwillza 0:3d4bd1fdeb2e 1011 return STATUS_INVALID;
mustwillza 0:3d4bd1fdeb2e 1012 }
mustwillza 0:3d4bd1fdeb2e 1013
mustwillza 0:3d4bd1fdeb2e 1014 // Copy sendData[] to cmdBuffer[] and add CRC_A
mustwillza 0:3d4bd1fdeb2e 1015 memcpy(cmdBuffer, sendData, sendLen);
mustwillza 0:3d4bd1fdeb2e 1016 result = PCD_CalculateCRC(cmdBuffer, sendLen, &cmdBuffer[sendLen]);
mustwillza 0:3d4bd1fdeb2e 1017 if (result != STATUS_OK)
mustwillza 0:3d4bd1fdeb2e 1018 {
mustwillza 0:3d4bd1fdeb2e 1019 return result;
mustwillza 0:3d4bd1fdeb2e 1020 }
mustwillza 0:3d4bd1fdeb2e 1021
mustwillza 0:3d4bd1fdeb2e 1022 sendLen += 2;
mustwillza 0:3d4bd1fdeb2e 1023
mustwillza 0:3d4bd1fdeb2e 1024 // Transceive the data, store the reply in cmdBuffer[]
mustwillza 0:3d4bd1fdeb2e 1025 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
mustwillza 0:3d4bd1fdeb2e 1026 uint8_t cmdBufferSize = sizeof(cmdBuffer);
mustwillza 0:3d4bd1fdeb2e 1027 uint8_t validBits = 0;
mustwillza 0:3d4bd1fdeb2e 1028 result = PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, cmdBuffer, sendLen, cmdBuffer, &cmdBufferSize, &validBits);
mustwillza 0:3d4bd1fdeb2e 1029 if (acceptTimeout && result == STATUS_TIMEOUT)
mustwillza 0:3d4bd1fdeb2e 1030 {
mustwillza 0:3d4bd1fdeb2e 1031 return STATUS_OK;
mustwillza 0:3d4bd1fdeb2e 1032 }
mustwillza 0:3d4bd1fdeb2e 1033
mustwillza 0:3d4bd1fdeb2e 1034 if (result != STATUS_OK)
mustwillza 0:3d4bd1fdeb2e 1035 {
mustwillza 0:3d4bd1fdeb2e 1036 return result;
mustwillza 0:3d4bd1fdeb2e 1037 }
mustwillza 0:3d4bd1fdeb2e 1038
mustwillza 0:3d4bd1fdeb2e 1039 // The PICC must reply with a 4 bit ACK
mustwillza 0:3d4bd1fdeb2e 1040 if (cmdBufferSize != 1 || validBits != 4)
mustwillza 0:3d4bd1fdeb2e 1041 {
mustwillza 0:3d4bd1fdeb2e 1042 return STATUS_ERROR;
mustwillza 0:3d4bd1fdeb2e 1043 }
mustwillza 0:3d4bd1fdeb2e 1044
mustwillza 0:3d4bd1fdeb2e 1045 if (cmdBuffer[0] != MF_ACK)
mustwillza 0:3d4bd1fdeb2e 1046 {
mustwillza 0:3d4bd1fdeb2e 1047 return STATUS_MIFARE_NACK;
mustwillza 0:3d4bd1fdeb2e 1048 }
mustwillza 0:3d4bd1fdeb2e 1049
mustwillza 0:3d4bd1fdeb2e 1050 return STATUS_OK;
mustwillza 0:3d4bd1fdeb2e 1051 } // End PCD_MIFARE_Transceive()
mustwillza 0:3d4bd1fdeb2e 1052
mustwillza 0:3d4bd1fdeb2e 1053
mustwillza 0:3d4bd1fdeb2e 1054 /*
mustwillza 0:3d4bd1fdeb2e 1055 * Translates the SAK (Select Acknowledge) to a PICC type.
mustwillza 0:3d4bd1fdeb2e 1056 */
mustwillza 0:3d4bd1fdeb2e 1057 uint8_t MFRC522::PICC_GetType(uint8_t sak)
mustwillza 0:3d4bd1fdeb2e 1058 {
mustwillza 0:3d4bd1fdeb2e 1059 uint8_t retType = PICC_TYPE_UNKNOWN;
mustwillza 0:3d4bd1fdeb2e 1060
mustwillza 0:3d4bd1fdeb2e 1061 if (sak & 0x04)
mustwillza 0:3d4bd1fdeb2e 1062 { // UID not complete
mustwillza 0:3d4bd1fdeb2e 1063 retType = PICC_TYPE_NOT_COMPLETE;
mustwillza 0:3d4bd1fdeb2e 1064 }
mustwillza 0:3d4bd1fdeb2e 1065 else
mustwillza 0:3d4bd1fdeb2e 1066 {
mustwillza 0:3d4bd1fdeb2e 1067 switch (sak)
mustwillza 0:3d4bd1fdeb2e 1068 {
mustwillza 0:3d4bd1fdeb2e 1069 case 0x09: retType = PICC_TYPE_MIFARE_MINI; break;
mustwillza 0:3d4bd1fdeb2e 1070 case 0x08: retType = PICC_TYPE_MIFARE_1K; break;
mustwillza 0:3d4bd1fdeb2e 1071 case 0x18: retType = PICC_TYPE_MIFARE_4K; break;
mustwillza 0:3d4bd1fdeb2e 1072 case 0x00: retType = PICC_TYPE_MIFARE_UL; break;
mustwillza 0:3d4bd1fdeb2e 1073 case 0x10:
mustwillza 0:3d4bd1fdeb2e 1074 case 0x11: retType = PICC_TYPE_MIFARE_PLUS; break;
mustwillza 0:3d4bd1fdeb2e 1075 case 0x01: retType = PICC_TYPE_TNP3XXX; break;
mustwillza 0:3d4bd1fdeb2e 1076 default:
mustwillza 0:3d4bd1fdeb2e 1077 if (sak & 0x20)
mustwillza 0:3d4bd1fdeb2e 1078 {
mustwillza 0:3d4bd1fdeb2e 1079 retType = PICC_TYPE_ISO_14443_4;
mustwillza 0:3d4bd1fdeb2e 1080 }
mustwillza 0:3d4bd1fdeb2e 1081 else if (sak & 0x40)
mustwillza 0:3d4bd1fdeb2e 1082 {
mustwillza 0:3d4bd1fdeb2e 1083 retType = PICC_TYPE_ISO_18092;
mustwillza 0:3d4bd1fdeb2e 1084 }
mustwillza 0:3d4bd1fdeb2e 1085 break;
mustwillza 0:3d4bd1fdeb2e 1086 }
mustwillza 0:3d4bd1fdeb2e 1087 }
mustwillza 0:3d4bd1fdeb2e 1088
mustwillza 0:3d4bd1fdeb2e 1089 return (retType);
mustwillza 0:3d4bd1fdeb2e 1090 } // End PICC_GetType()
mustwillza 0:3d4bd1fdeb2e 1091
mustwillza 0:3d4bd1fdeb2e 1092 /*
mustwillza 0:3d4bd1fdeb2e 1093 * Returns a string pointer to the PICC type name.
mustwillza 0:3d4bd1fdeb2e 1094 */
mustwillza 0:3d4bd1fdeb2e 1095 char* MFRC522::PICC_GetTypeName(uint8_t piccType)
mustwillza 0:3d4bd1fdeb2e 1096 {
mustwillza 0:3d4bd1fdeb2e 1097 if(piccType == PICC_TYPE_NOT_COMPLETE)
mustwillza 0:3d4bd1fdeb2e 1098 {
mustwillza 0:3d4bd1fdeb2e 1099 piccType = MFRC522_MaxPICCs - 1;
mustwillza 0:3d4bd1fdeb2e 1100 }
mustwillza 0:3d4bd1fdeb2e 1101
mustwillza 0:3d4bd1fdeb2e 1102 return((char *) _TypeNamePICC[piccType]);
mustwillza 0:3d4bd1fdeb2e 1103 } // End PICC_GetTypeName()
mustwillza 0:3d4bd1fdeb2e 1104
mustwillza 0:3d4bd1fdeb2e 1105 /*
mustwillza 0:3d4bd1fdeb2e 1106 * Returns a string pointer to a status code name.
mustwillza 0:3d4bd1fdeb2e 1107 */
mustwillza 0:3d4bd1fdeb2e 1108 char* MFRC522::GetStatusCodeName(uint8_t code)
mustwillza 0:3d4bd1fdeb2e 1109 {
mustwillza 0:3d4bd1fdeb2e 1110 return((char *) _ErrorMessage[code]);
mustwillza 0:3d4bd1fdeb2e 1111 } // End GetStatusCodeName()
mustwillza 0:3d4bd1fdeb2e 1112
mustwillza 0:3d4bd1fdeb2e 1113 /*
mustwillza 0:3d4bd1fdeb2e 1114 * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
mustwillza 0:3d4bd1fdeb2e 1115 */
mustwillza 0:3d4bd1fdeb2e 1116 void MFRC522::MIFARE_SetAccessBits(uint8_t *accessBitBuffer,
mustwillza 0:3d4bd1fdeb2e 1117 uint8_t g0,
mustwillza 0:3d4bd1fdeb2e 1118 uint8_t g1,
mustwillza 0:3d4bd1fdeb2e 1119 uint8_t g2,
mustwillza 0:3d4bd1fdeb2e 1120 uint8_t g3)
mustwillza 0:3d4bd1fdeb2e 1121 {
mustwillza 0:3d4bd1fdeb2e 1122 uint8_t c1 = ((g3 & 4) << 1) | ((g2 & 4) << 0) | ((g1 & 4) >> 1) | ((g0 & 4) >> 2);
mustwillza 0:3d4bd1fdeb2e 1123 uint8_t c2 = ((g3 & 2) << 2) | ((g2 & 2) << 1) | ((g1 & 2) << 0) | ((g0 & 2) >> 1);
mustwillza 0:3d4bd1fdeb2e 1124 uint8_t c3 = ((g3 & 1) << 3) | ((g2 & 1) << 2) | ((g1 & 1) << 1) | ((g0 & 1) << 0);
mustwillza 0:3d4bd1fdeb2e 1125
mustwillza 0:3d4bd1fdeb2e 1126 accessBitBuffer[0] = (~c2 & 0xF) << 4 | (~c1 & 0xF);
mustwillza 0:3d4bd1fdeb2e 1127 accessBitBuffer[1] = c1 << 4 | (~c3 & 0xF);
mustwillza 0:3d4bd1fdeb2e 1128 accessBitBuffer[2] = c3 << 4 | c2;
mustwillza 0:3d4bd1fdeb2e 1129 } // End MIFARE_SetAccessBits()
mustwillza 0:3d4bd1fdeb2e 1130
mustwillza 0:3d4bd1fdeb2e 1131 /////////////////////////////////////////////////////////////////////////////////////
mustwillza 0:3d4bd1fdeb2e 1132 // Convenience functions - does not add extra functionality
mustwillza 0:3d4bd1fdeb2e 1133 /////////////////////////////////////////////////////////////////////////////////////
mustwillza 0:3d4bd1fdeb2e 1134
mustwillza 0:3d4bd1fdeb2e 1135 /*
mustwillza 0:3d4bd1fdeb2e 1136 * Returns true if a PICC responds to PICC_CMD_REQA.
mustwillza 0:3d4bd1fdeb2e 1137 * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
mustwillza 0:3d4bd1fdeb2e 1138 */
mustwillza 0:3d4bd1fdeb2e 1139 bool MFRC522::PICC_IsNewCardPresent(void)
mustwillza 0:3d4bd1fdeb2e 1140 {
mustwillza 0:3d4bd1fdeb2e 1141 uint8_t bufferATQA[2];
mustwillza 0:3d4bd1fdeb2e 1142 uint8_t bufferSize = sizeof(bufferATQA);
mustwillza 0:3d4bd1fdeb2e 1143 uint8_t result = PICC_RequestA(bufferATQA, &bufferSize);
mustwillza 0:3d4bd1fdeb2e 1144 return ((result == STATUS_OK) || (result == STATUS_COLLISION));
mustwillza 0:3d4bd1fdeb2e 1145 } // End PICC_IsNewCardPresent()
mustwillza 0:3d4bd1fdeb2e 1146
mustwillza 0:3d4bd1fdeb2e 1147 /*
mustwillza 0:3d4bd1fdeb2e 1148 * Simple wrapper around PICC_Select.
mustwillza 0:3d4bd1fdeb2e 1149 */
mustwillza 0:3d4bd1fdeb2e 1150 bool MFRC522::PICC_ReadCardSerial(void)
mustwillza 0:3d4bd1fdeb2e 1151 {
mustwillza 0:3d4bd1fdeb2e 1152 uint8_t result = PICC_Select(&uid);
mustwillza 0:3d4bd1fdeb2e 1153 return (result == STATUS_OK);
mustwillza 0:3d4bd1fdeb2e 1154 } // End PICC_ReadCardSerial()