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targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*******************************************************************************
bogdanm 0:9b334a45a8ff 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Permission is hereby granted, free of charge, to any person obtaining a
bogdanm 0:9b334a45a8ff 5 * copy of this software and associated documentation files (the "Software"),
bogdanm 0:9b334a45a8ff 6 * to deal in the Software without restriction, including without limitation
bogdanm 0:9b334a45a8ff 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
bogdanm 0:9b334a45a8ff 8 * and/or sell copies of the Software, and to permit persons to whom the
bogdanm 0:9b334a45a8ff 9 * Software is furnished to do so, subject to the following conditions:
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * The above copyright notice and this permission notice shall be included
bogdanm 0:9b334a45a8ff 12 * in all copies or substantial portions of the Software.
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
bogdanm 0:9b334a45a8ff 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
bogdanm 0:9b334a45a8ff 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
bogdanm 0:9b334a45a8ff 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
bogdanm 0:9b334a45a8ff 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
bogdanm 0:9b334a45a8ff 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
bogdanm 0:9b334a45a8ff 20 * OTHER DEALINGS IN THE SOFTWARE.
bogdanm 0:9b334a45a8ff 21 *
bogdanm 0:9b334a45a8ff 22 * Except as contained in this notice, the name of Maxim Integrated
bogdanm 0:9b334a45a8ff 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
bogdanm 0:9b334a45a8ff 24 * Products, Inc. Branding Policy.
bogdanm 0:9b334a45a8ff 25 *
bogdanm 0:9b334a45a8ff 26 * The mere transfer of this software does not imply any licenses
bogdanm 0:9b334a45a8ff 27 * of trade secrets, proprietary technology, copyrights, patents,
bogdanm 0:9b334a45a8ff 28 * trademarks, maskwork rights, or any other form of intellectual
bogdanm 0:9b334a45a8ff 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
bogdanm 0:9b334a45a8ff 30 * ownership rights.
bogdanm 0:9b334a45a8ff 31 *******************************************************************************
bogdanm 0:9b334a45a8ff 32 */
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 #include "device.h"
bogdanm 0:9b334a45a8ff 35 #include "PeripheralPins.h"
bogdanm 0:9b334a45a8ff 36 #include "ioman_regs.h"
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 /*
bogdanm 0:9b334a45a8ff 39 * To select a peripheral function on Maxim microcontrollers, multiple
bogdanm 0:9b334a45a8ff 40 * configurations must be made. The mbed PinMap structure only includes one
bogdanm 0:9b334a45a8ff 41 * data member to hold this information. To extend the configuration storage,
bogdanm 0:9b334a45a8ff 42 * the "function" data member is used as a pointer to a pin_function_t
bogdanm 0:9b334a45a8ff 43 * structure. This structure is defined in objects.h. The definitions below
bogdanm 0:9b334a45a8ff 44 * include the creation of the pin_function_t structures and the assignment of
bogdanm 0:9b334a45a8ff 45 * the pointers to the "function" data members.
bogdanm 0:9b334a45a8ff 46 */
bogdanm 0:9b334a45a8ff 47
bogdanm 0:9b334a45a8ff 48 #ifdef TOOLCHAIN_ARM_STD
bogdanm 0:9b334a45a8ff 49 #pragma diag_suppress 1296
bogdanm 0:9b334a45a8ff 50 #endif
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 /************I2C***************/
bogdanm 0:9b334a45a8ff 53 const PinMap PinMap_I2C_SDA[] = {
bogdanm 0:9b334a45a8ff 54 { P0_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
bogdanm 0:9b334a45a8ff 55 { P0_6, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_H | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
bogdanm 0:9b334a45a8ff 56 { NC, NC, 0 }
bogdanm 0:9b334a45a8ff 57 };
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 const PinMap PinMap_I2C_SCL[] = {
bogdanm 0:9b334a45a8ff 60 { P0_5, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
bogdanm 0:9b334a45a8ff 61 { P0_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_H | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
bogdanm 0:9b334a45a8ff 62 { NC, NC, 0 }
bogdanm 0:9b334a45a8ff 63 };
bogdanm 0:9b334a45a8ff 64
bogdanm 0:9b334a45a8ff 65 /************UART***************/
bogdanm 0:9b334a45a8ff 66 const PinMap PinMap_UART_TX[] = {
bogdanm 0:9b334a45a8ff 67 { P1_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
bogdanm 0:9b334a45a8ff 68 { P1_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
bogdanm 0:9b334a45a8ff 69 { P2_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
bogdanm 0:9b334a45a8ff 70 { P2_5, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
bogdanm 0:9b334a45a8ff 71 { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
bogdanm 0:9b334a45a8ff 72 { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
bogdanm 0:9b334a45a8ff 73 { NC, NC, 0 }
bogdanm 0:9b334a45a8ff 74 };
bogdanm 0:9b334a45a8ff 75
bogdanm 0:9b334a45a8ff 76 const PinMap PinMap_UART_RX[] = {
bogdanm 0:9b334a45a8ff 77 { P1_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
bogdanm 0:9b334a45a8ff 78 { P1_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
bogdanm 0:9b334a45a8ff 79 { P2_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
bogdanm 0:9b334a45a8ff 80 { P2_4, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
bogdanm 0:9b334a45a8ff 81 { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
bogdanm 0:9b334a45a8ff 82 { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
bogdanm 0:9b334a45a8ff 83 { NC, NC, 0 }
bogdanm 0:9b334a45a8ff 84 };
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 const PinMap PinMap_UART_CTS[] = {
bogdanm 0:9b334a45a8ff 87 { P1_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
bogdanm 0:9b334a45a8ff 88 { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
bogdanm 0:9b334a45a8ff 89 { P2_4, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
bogdanm 0:9b334a45a8ff 90 { P2_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
bogdanm 0:9b334a45a8ff 91 { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
bogdanm 0:9b334a45a8ff 92 { NC, NC, 0 }
bogdanm 0:9b334a45a8ff 93 };
bogdanm 0:9b334a45a8ff 94
bogdanm 0:9b334a45a8ff 95 const PinMap PinMap_UART_RTS[] = {
bogdanm 0:9b334a45a8ff 96 { P1_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
bogdanm 0:9b334a45a8ff 97 { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
bogdanm 0:9b334a45a8ff 98 { P2_5, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
bogdanm 0:9b334a45a8ff 99 { P2_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
bogdanm 0:9b334a45a8ff 100 { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
bogdanm 0:9b334a45a8ff 101 { NC, NC, 0 }
bogdanm 0:9b334a45a8ff 102 };
bogdanm 0:9b334a45a8ff 103
bogdanm 0:9b334a45a8ff 104 /************SPI***************/
bogdanm 0:9b334a45a8ff 105 const PinMap PinMap_SPI_SCLK[] = {
bogdanm 0:9b334a45a8ff 106 { P0_0, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
bogdanm 0:9b334a45a8ff 107 { P2_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
bogdanm 0:9b334a45a8ff 108 { NC, NC, 0}
bogdanm 0:9b334a45a8ff 109 };
bogdanm 0:9b334a45a8ff 110
bogdanm 0:9b334a45a8ff 111 const PinMap PinMap_SPI_MOSI[] = {
bogdanm 0:9b334a45a8ff 112 { P0_1, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
bogdanm 0:9b334a45a8ff 113 { P2_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
bogdanm 0:9b334a45a8ff 114 { NC, NC, 0}
bogdanm 0:9b334a45a8ff 115 };
bogdanm 0:9b334a45a8ff 116
bogdanm 0:9b334a45a8ff 117 const PinMap PinMap_SPI_MISO[] = {
bogdanm 0:9b334a45a8ff 118 { P0_2, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
bogdanm 0:9b334a45a8ff 119 { P2_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
bogdanm 0:9b334a45a8ff 120 { NC, NC, 0}
bogdanm 0:9b334a45a8ff 121 };
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 const PinMap PinMap_SPI_SSEL[] = {
bogdanm 0:9b334a45a8ff 124 { P0_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
bogdanm 0:9b334a45a8ff 125 { P2_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO)}) },
bogdanm 0:9b334a45a8ff 126 { NC, NC, 0}
bogdanm 0:9b334a45a8ff 127 };
bogdanm 0:9b334a45a8ff 128
bogdanm 0:9b334a45a8ff 129 /************PWM***************/
bogdanm 0:9b334a45a8ff 130 const PinMap PinMap_PWM[] = {
bogdanm 0:9b334a45a8ff 131 {P0_0, PWM_0, 1}, {P0_0, PWM_0, 2}, {P0_0, PWM_4, 3},
bogdanm 0:9b334a45a8ff 132 {P0_1, PWM_1, 1}, {P0_1, PWM_4, 2}, {P0_1, PWM_0, 3},
bogdanm 0:9b334a45a8ff 133 {P0_2, PWM_2, 1}, {P0_2, PWM_1, 2}, {P0_2, PWM_5, 3},
bogdanm 0:9b334a45a8ff 134 {P0_3, PWM_3, 1}, {P0_3, PWM_5, 2}, {P0_3, PWM_1, 3},
bogdanm 0:9b334a45a8ff 135 {P0_4, PWM_4, 1}, {P0_4, PWM_2, 2}, {P0_4, PWM_6, 3},
bogdanm 0:9b334a45a8ff 136 {P0_5, PWM_5, 1}, {P0_5, PWM_6, 2}, {P0_5, PWM_2, 3},
bogdanm 0:9b334a45a8ff 137 {P0_6, PWM_6, 1}, {P0_6, PWM_3, 2}, {P0_6, PWM_7, 3},
bogdanm 0:9b334a45a8ff 138 {P0_7, PWM_7, 1}, {P0_7, PWM_7, 2}, {P0_7, PWM_3, 3},
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 {P1_0, PWM_0, 1}, {P1_0, PWM_0, 2}, {P1_0, PWM_4, 3},
bogdanm 0:9b334a45a8ff 141 {P1_1, PWM_1, 1}, {P1_1, PWM_4, 2}, {P1_1, PWM_0, 3},
bogdanm 0:9b334a45a8ff 142 {P1_2, PWM_2, 1}, {P1_2, PWM_1, 2}, {P1_2, PWM_5, 3},
bogdanm 0:9b334a45a8ff 143 {P1_3, PWM_3, 1}, {P1_3, PWM_5, 2}, {P1_3, PWM_1, 3},
bogdanm 0:9b334a45a8ff 144 {P1_4, PWM_4, 1}, {P1_4, PWM_2, 2}, {P1_4, PWM_6, 3},
bogdanm 0:9b334a45a8ff 145 {P1_5, PWM_5, 1}, {P1_5, PWM_6, 2}, {P1_5, PWM_2, 3},
bogdanm 0:9b334a45a8ff 146 {P1_6, PWM_6, 1}, {P1_6, PWM_3, 2}, {P1_6, PWM_7, 3},
bogdanm 0:9b334a45a8ff 147 {P1_7, PWM_7, 1}, {P1_7, PWM_7, 2}, {P1_7, PWM_3, 3},
bogdanm 0:9b334a45a8ff 148
bogdanm 0:9b334a45a8ff 149 {P2_0, PWM_0, 1}, {P2_0, PWM_0, 2}, {P2_0, PWM_4, 3},
bogdanm 0:9b334a45a8ff 150 {P2_1, PWM_1, 1}, {P2_1, PWM_4, 2}, {P2_1, PWM_0, 3},
bogdanm 0:9b334a45a8ff 151 {P2_2, PWM_2, 1}, {P2_2, PWM_1, 2}, {P2_2, PWM_5, 3},
bogdanm 0:9b334a45a8ff 152 {P2_3, PWM_3, 1}, {P2_3, PWM_5, 2}, {P2_3, PWM_1, 3},
bogdanm 0:9b334a45a8ff 153 {P2_4, PWM_4, 1}, {P2_4, PWM_2, 2}, {P2_4, PWM_6, 3},
bogdanm 0:9b334a45a8ff 154 {P2_5, PWM_5, 1}, {P2_5, PWM_6, 2}, {P2_5, PWM_2, 3},
bogdanm 0:9b334a45a8ff 155 {P2_6, PWM_6, 1}, {P2_6, PWM_3, 2}, {P2_6, PWM_7, 3},
bogdanm 0:9b334a45a8ff 156 {P2_7, PWM_7, 1}, {P2_7, PWM_7, 2}, {P2_7, PWM_3, 3},
bogdanm 0:9b334a45a8ff 157
bogdanm 0:9b334a45a8ff 158 {NC, NC, 0}
bogdanm 0:9b334a45a8ff 159 };
bogdanm 0:9b334a45a8ff 160
bogdanm 0:9b334a45a8ff 161 /************ADC***************/
bogdanm 0:9b334a45a8ff 162 const PinMap PinMap_ADC[] = {
bogdanm 0:9b334a45a8ff 163 {AIN_0P, ADC, 0},
bogdanm 0:9b334a45a8ff 164 {AIN_1P, ADC, 0},
bogdanm 0:9b334a45a8ff 165 {AIN_2P, ADC, 0},
bogdanm 0:9b334a45a8ff 166 {AIN_3P, ADC, 0},
bogdanm 0:9b334a45a8ff 167 {AIN_4P, ADC, 0},
bogdanm 0:9b334a45a8ff 168 {AIN_5P, ADC, 0},
bogdanm 0:9b334a45a8ff 169 {AIN_0N, ADC, 0},
bogdanm 0:9b334a45a8ff 170 {AIN_1N, ADC, 0},
bogdanm 0:9b334a45a8ff 171 {AIN_2N, ADC, 0},
bogdanm 0:9b334a45a8ff 172 {AIN_3N, ADC, 0},
bogdanm 0:9b334a45a8ff 173 {AIN_4N, ADC, 0},
bogdanm 0:9b334a45a8ff 174 {AIN_5N, ADC, 0},
bogdanm 0:9b334a45a8ff 175 {AIN_0D, ADC, 1},
bogdanm 0:9b334a45a8ff 176 {AIN_1D, ADC, 1},
bogdanm 0:9b334a45a8ff 177 {AIN_2D, ADC, 1},
bogdanm 0:9b334a45a8ff 178 {AIN_3D, ADC, 1},
bogdanm 0:9b334a45a8ff 179 {AIN_4D, ADC, 1},
bogdanm 0:9b334a45a8ff 180 {AIN_5D, ADC, 1},
bogdanm 0:9b334a45a8ff 181 {NC, NC, 0}
bogdanm 0:9b334a45a8ff 182 };
bogdanm 0:9b334a45a8ff 183
bogdanm 0:9b334a45a8ff 184 /************DAC***************/
bogdanm 0:9b334a45a8ff 185 const PinMap PinMap_DAC[] = {
bogdanm 0:9b334a45a8ff 186 {AOUT_AO, DAC0, 0},
bogdanm 0:9b334a45a8ff 187 {AOUT_BO, DAC1, 0},
bogdanm 0:9b334a45a8ff 188 {AOUT_CO, DAC2, 0},
bogdanm 0:9b334a45a8ff 189 {AOUT_DO, DAC3, 0},
bogdanm 0:9b334a45a8ff 190 {NC, NC, 0}
bogdanm 0:9b334a45a8ff 191 };