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mbed/hal/spi_api.h@0:d6c9b09b4042, 2020-12-02 (annotated)

Committer:
annieluo2
Date:
Wed Dec 02 18:02:03 2020 +0000
Revision:
0:d6c9b09b4042
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annieluo2 0:d6c9b09b4042 1
annieluo2 0:d6c9b09b4042 2 /** \addtogroup hal */
annieluo2 0:d6c9b09b4042 3 /** @{*/
annieluo2 0:d6c9b09b4042 4 /* mbed Microcontroller Library
annieluo2 0:d6c9b09b4042 5 * Copyright (c) 2006-2013 ARM Limited
annieluo2 0:d6c9b09b4042 6 *
annieluo2 0:d6c9b09b4042 7 * Licensed under the Apache License, Version 2.0 (the "License");
annieluo2 0:d6c9b09b4042 8 * you may not use this file except in compliance with the License.
annieluo2 0:d6c9b09b4042 9 * You may obtain a copy of the License at
annieluo2 0:d6c9b09b4042 10 *
annieluo2 0:d6c9b09b4042 11 * http://www.apache.org/licenses/LICENSE-2.0
annieluo2 0:d6c9b09b4042 12 *
annieluo2 0:d6c9b09b4042 13 * Unless required by applicable law or agreed to in writing, software
annieluo2 0:d6c9b09b4042 14 * distributed under the License is distributed on an "AS IS" BASIS,
annieluo2 0:d6c9b09b4042 15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
annieluo2 0:d6c9b09b4042 16 * See the License for the specific language governing permissions and
annieluo2 0:d6c9b09b4042 17 * limitations under the License.
annieluo2 0:d6c9b09b4042 18 */
annieluo2 0:d6c9b09b4042 19 #ifndef MBED_SPI_API_H
annieluo2 0:d6c9b09b4042 20 #define MBED_SPI_API_H
annieluo2 0:d6c9b09b4042 21
annieluo2 0:d6c9b09b4042 22 #include "device.h"
annieluo2 0:d6c9b09b4042 23 #include "hal/dma_api.h"
annieluo2 0:d6c9b09b4042 24 #include "hal/buffer.h"
annieluo2 0:d6c9b09b4042 25
annieluo2 0:d6c9b09b4042 26 #if DEVICE_SPI
annieluo2 0:d6c9b09b4042 27
annieluo2 0:d6c9b09b4042 28 #define SPI_EVENT_ERROR (1 << 1)
annieluo2 0:d6c9b09b4042 29 #define SPI_EVENT_COMPLETE (1 << 2)
annieluo2 0:d6c9b09b4042 30 #define SPI_EVENT_RX_OVERFLOW (1 << 3)
annieluo2 0:d6c9b09b4042 31 #define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
annieluo2 0:d6c9b09b4042 32
annieluo2 0:d6c9b09b4042 33 #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
annieluo2 0:d6c9b09b4042 34
annieluo2 0:d6c9b09b4042 35 #define SPI_FILL_WORD (0xFFFF)
annieluo2 0:d6c9b09b4042 36
annieluo2 0:d6c9b09b4042 37 #if DEVICE_SPI_ASYNCH
annieluo2 0:d6c9b09b4042 38 /** Asynch SPI HAL structure
annieluo2 0:d6c9b09b4042 39 */
annieluo2 0:d6c9b09b4042 40 typedef struct {
annieluo2 0:d6c9b09b4042 41 struct spi_s spi; /**< Target specific SPI structure */
annieluo2 0:d6c9b09b4042 42 struct buffer_s tx_buff; /**< Tx buffer */
annieluo2 0:d6c9b09b4042 43 struct buffer_s rx_buff; /**< Rx buffer */
annieluo2 0:d6c9b09b4042 44 } spi_t;
annieluo2 0:d6c9b09b4042 45
annieluo2 0:d6c9b09b4042 46 #else
annieluo2 0:d6c9b09b4042 47 /** Non-asynch SPI HAL structure
annieluo2 0:d6c9b09b4042 48 */
annieluo2 0:d6c9b09b4042 49 typedef struct spi_s spi_t;
annieluo2 0:d6c9b09b4042 50
annieluo2 0:d6c9b09b4042 51 #endif
annieluo2 0:d6c9b09b4042 52
annieluo2 0:d6c9b09b4042 53 #ifdef __cplusplus
annieluo2 0:d6c9b09b4042 54 extern "C" {
annieluo2 0:d6c9b09b4042 55 #endif
annieluo2 0:d6c9b09b4042 56
annieluo2 0:d6c9b09b4042 57 /**
annieluo2 0:d6c9b09b4042 58 * \defgroup hal_GeneralSPI SPI Configuration Functions
annieluo2 0:d6c9b09b4042 59 * @{
annieluo2 0:d6c9b09b4042 60 */
annieluo2 0:d6c9b09b4042 61
annieluo2 0:d6c9b09b4042 62 /** Initialize the SPI peripheral
annieluo2 0:d6c9b09b4042 63 *
annieluo2 0:d6c9b09b4042 64 * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
annieluo2 0:d6c9b09b4042 65 * @param[out] obj The SPI object to initialize
annieluo2 0:d6c9b09b4042 66 * @param[in] mosi The pin to use for MOSI
annieluo2 0:d6c9b09b4042 67 * @param[in] miso The pin to use for MISO
annieluo2 0:d6c9b09b4042 68 * @param[in] sclk The pin to use for SCLK
annieluo2 0:d6c9b09b4042 69 * @param[in] ssel The pin to use for SSEL
annieluo2 0:d6c9b09b4042 70 */
annieluo2 0:d6c9b09b4042 71 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
annieluo2 0:d6c9b09b4042 72
annieluo2 0:d6c9b09b4042 73 /** Release a SPI object
annieluo2 0:d6c9b09b4042 74 *
annieluo2 0:d6c9b09b4042 75 * TODO: spi_free is currently unimplemented
annieluo2 0:d6c9b09b4042 76 * This will require reference counting at the C++ level to be safe
annieluo2 0:d6c9b09b4042 77 *
annieluo2 0:d6c9b09b4042 78 * Return the pins owned by the SPI object to their reset state
annieluo2 0:d6c9b09b4042 79 * Disable the SPI peripheral
annieluo2 0:d6c9b09b4042 80 * Disable the SPI clock
annieluo2 0:d6c9b09b4042 81 * @param[in] obj The SPI object to deinitialize
annieluo2 0:d6c9b09b4042 82 */
annieluo2 0:d6c9b09b4042 83 void spi_free(spi_t *obj);
annieluo2 0:d6c9b09b4042 84
annieluo2 0:d6c9b09b4042 85 /** Configure the SPI format
annieluo2 0:d6c9b09b4042 86 *
annieluo2 0:d6c9b09b4042 87 * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
annieluo2 0:d6c9b09b4042 88 * The default bit order is MSB.
annieluo2 0:d6c9b09b4042 89 * @param[in,out] obj The SPI object to configure
annieluo2 0:d6c9b09b4042 90 * @param[in] bits The number of bits per frame
annieluo2 0:d6c9b09b4042 91 * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
annieluo2 0:d6c9b09b4042 92 * @param[in] slave Zero for master mode or non-zero for slave mode
annieluo2 0:d6c9b09b4042 93 */
annieluo2 0:d6c9b09b4042 94 void spi_format(spi_t *obj, int bits, int mode, int slave);
annieluo2 0:d6c9b09b4042 95
annieluo2 0:d6c9b09b4042 96 /** Set the SPI baud rate
annieluo2 0:d6c9b09b4042 97 *
annieluo2 0:d6c9b09b4042 98 * Actual frequency may differ from the desired frequency due to available dividers and bus clock
annieluo2 0:d6c9b09b4042 99 * Configures the SPI peripheral's baud rate
annieluo2 0:d6c9b09b4042 100 * @param[in,out] obj The SPI object to configure
annieluo2 0:d6c9b09b4042 101 * @param[in] hz The baud rate in Hz
annieluo2 0:d6c9b09b4042 102 */
annieluo2 0:d6c9b09b4042 103 void spi_frequency(spi_t *obj, int hz);
annieluo2 0:d6c9b09b4042 104
annieluo2 0:d6c9b09b4042 105 /**@}*/
annieluo2 0:d6c9b09b4042 106 /**
annieluo2 0:d6c9b09b4042 107 * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
annieluo2 0:d6c9b09b4042 108 * @{
annieluo2 0:d6c9b09b4042 109 */
annieluo2 0:d6c9b09b4042 110
annieluo2 0:d6c9b09b4042 111 /** Write a byte out in master mode and receive a value
annieluo2 0:d6c9b09b4042 112 *
annieluo2 0:d6c9b09b4042 113 * @param[in] obj The SPI peripheral to use for sending
annieluo2 0:d6c9b09b4042 114 * @param[in] value The value to send
annieluo2 0:d6c9b09b4042 115 * @return Returns the value received during send
annieluo2 0:d6c9b09b4042 116 */
annieluo2 0:d6c9b09b4042 117 int spi_master_write(spi_t *obj, int value);
annieluo2 0:d6c9b09b4042 118
annieluo2 0:d6c9b09b4042 119 /** Check if a value is available to read
annieluo2 0:d6c9b09b4042 120 *
annieluo2 0:d6c9b09b4042 121 * @param[in] obj The SPI peripheral to check
annieluo2 0:d6c9b09b4042 122 * @return non-zero if a value is available
annieluo2 0:d6c9b09b4042 123 */
annieluo2 0:d6c9b09b4042 124 int spi_slave_receive(spi_t *obj);
annieluo2 0:d6c9b09b4042 125
annieluo2 0:d6c9b09b4042 126 /** Get a received value out of the SPI receive buffer in slave mode
annieluo2 0:d6c9b09b4042 127 *
annieluo2 0:d6c9b09b4042 128 * Blocks until a value is available
annieluo2 0:d6c9b09b4042 129 * @param[in] obj The SPI peripheral to read
annieluo2 0:d6c9b09b4042 130 * @return The value received
annieluo2 0:d6c9b09b4042 131 */
annieluo2 0:d6c9b09b4042 132 int spi_slave_read(spi_t *obj);
annieluo2 0:d6c9b09b4042 133
annieluo2 0:d6c9b09b4042 134 /** Write a value to the SPI peripheral in slave mode
annieluo2 0:d6c9b09b4042 135 *
annieluo2 0:d6c9b09b4042 136 * Blocks until the SPI peripheral can be written to
annieluo2 0:d6c9b09b4042 137 * @param[in] obj The SPI peripheral to write
annieluo2 0:d6c9b09b4042 138 * @param[in] value The value to write
annieluo2 0:d6c9b09b4042 139 */
annieluo2 0:d6c9b09b4042 140 void spi_slave_write(spi_t *obj, int value);
annieluo2 0:d6c9b09b4042 141
annieluo2 0:d6c9b09b4042 142 /** Checks if the specified SPI peripheral is in use
annieluo2 0:d6c9b09b4042 143 *
annieluo2 0:d6c9b09b4042 144 * @param[in] obj The SPI peripheral to check
annieluo2 0:d6c9b09b4042 145 * @return non-zero if the peripheral is currently transmitting
annieluo2 0:d6c9b09b4042 146 */
annieluo2 0:d6c9b09b4042 147 int spi_busy(spi_t *obj);
annieluo2 0:d6c9b09b4042 148
annieluo2 0:d6c9b09b4042 149 /** Get the module number
annieluo2 0:d6c9b09b4042 150 *
annieluo2 0:d6c9b09b4042 151 * @param[in] obj The SPI peripheral to check
annieluo2 0:d6c9b09b4042 152 * @return The module number
annieluo2 0:d6c9b09b4042 153 */
annieluo2 0:d6c9b09b4042 154 uint8_t spi_get_module(spi_t *obj);
annieluo2 0:d6c9b09b4042 155
annieluo2 0:d6c9b09b4042 156 /**@}*/
annieluo2 0:d6c9b09b4042 157
annieluo2 0:d6c9b09b4042 158 #if DEVICE_SPI_ASYNCH
annieluo2 0:d6c9b09b4042 159 /**
annieluo2 0:d6c9b09b4042 160 * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
annieluo2 0:d6c9b09b4042 161 * @{
annieluo2 0:d6c9b09b4042 162 */
annieluo2 0:d6c9b09b4042 163
annieluo2 0:d6c9b09b4042 164 /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
annieluo2 0:d6c9b09b4042 165 *
annieluo2 0:d6c9b09b4042 166 * @param[in] obj The SPI object that holds the transfer information
annieluo2 0:d6c9b09b4042 167 * @param[in] tx The transmit buffer
annieluo2 0:d6c9b09b4042 168 * @param[in] tx_length The number of bytes to transmit
annieluo2 0:d6c9b09b4042 169 * @param[in] rx The receive buffer
annieluo2 0:d6c9b09b4042 170 * @param[in] rx_length The number of bytes to receive
annieluo2 0:d6c9b09b4042 171 * @param[in] bit_width The bit width of buffer words
annieluo2 0:d6c9b09b4042 172 * @param[in] event The logical OR of events to be registered
annieluo2 0:d6c9b09b4042 173 * @param[in] handler SPI interrupt handler
annieluo2 0:d6c9b09b4042 174 * @param[in] hint A suggestion for how to use DMA with this transfer
annieluo2 0:d6c9b09b4042 175 */
annieluo2 0:d6c9b09b4042 176 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
annieluo2 0:d6c9b09b4042 177
annieluo2 0:d6c9b09b4042 178 /** The asynchronous IRQ handler
annieluo2 0:d6c9b09b4042 179 *
annieluo2 0:d6c9b09b4042 180 * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
annieluo2 0:d6c9b09b4042 181 * conditions, such as buffer overflows or transfer complete.
annieluo2 0:d6c9b09b4042 182 * @param[in] obj The SPI object that holds the transfer information
annieluo2 0:d6c9b09b4042 183 * @return Event flags if a transfer termination condition was met; otherwise 0.
annieluo2 0:d6c9b09b4042 184 */
annieluo2 0:d6c9b09b4042 185 uint32_t spi_irq_handler_asynch(spi_t *obj);
annieluo2 0:d6c9b09b4042 186
annieluo2 0:d6c9b09b4042 187 /** Attempts to determine if the SPI peripheral is already in use
annieluo2 0:d6c9b09b4042 188 *
annieluo2 0:d6c9b09b4042 189 * If a temporary DMA channel has been allocated, peripheral is in use.
annieluo2 0:d6c9b09b4042 190 * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
annieluo2 0:d6c9b09b4042 191 * channel were allocated.
annieluo2 0:d6c9b09b4042 192 * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
annieluo2 0:d6c9b09b4042 193 * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
annieluo2 0:d6c9b09b4042 194 * there are any bytes in the FIFOs.
annieluo2 0:d6c9b09b4042 195 * @param[in] obj The SPI object to check for activity
annieluo2 0:d6c9b09b4042 196 * @return Non-zero if the SPI port is active or zero if it is not.
annieluo2 0:d6c9b09b4042 197 */
annieluo2 0:d6c9b09b4042 198 uint8_t spi_active(spi_t *obj);
annieluo2 0:d6c9b09b4042 199
annieluo2 0:d6c9b09b4042 200 /** Abort an SPI transfer
annieluo2 0:d6c9b09b4042 201 *
annieluo2 0:d6c9b09b4042 202 * @param obj The SPI peripheral to stop
annieluo2 0:d6c9b09b4042 203 */
annieluo2 0:d6c9b09b4042 204 void spi_abort_asynch(spi_t *obj);
annieluo2 0:d6c9b09b4042 205
annieluo2 0:d6c9b09b4042 206
annieluo2 0:d6c9b09b4042 207 #endif
annieluo2 0:d6c9b09b4042 208
annieluo2 0:d6c9b09b4042 209 /**@}*/
annieluo2 0:d6c9b09b4042 210
annieluo2 0:d6c9b09b4042 211 #ifdef __cplusplus
annieluo2 0:d6c9b09b4042 212 }
annieluo2 0:d6c9b09b4042 213 #endif // __cplusplus
annieluo2 0:d6c9b09b4042 214
annieluo2 0:d6c9b09b4042 215 #endif // SPI_DEVICE
annieluo2 0:d6c9b09b4042 216
annieluo2 0:d6c9b09b4042 217 #endif // MBED_SPI_API_H
annieluo2 0:d6c9b09b4042 218
annieluo2 0:d6c9b09b4042 219 /** @}*/