ECE 4180 Fitbit Project / Mbed 2 deprecated 4180_Fitness_Tracker

This is a repository for code relating to mbed Fitness Tracker

Dependencies:   mbed PulseSensor2 SCP1000 mbed-rtos 4DGL-uLCD-SE LSM9DS1_Library_cal PinDetect FatFileSystemCpp GP-20U7

USBHostLite/usbhost_lpc17xx.cpp@43:81f314c92d9f, 2020-04-28 (annotated)

Committer:
dyu2021
Date:
Tue Apr 28 20:00:56 2020 +0000
Revision:
43:81f314c92d9f
Parent:
18:9617bd66bdae 
Changed serial_USB to output all lines of prev_text, not hard set to 7

Who changed what in which revision?

UserRevisionLine numberNew contents of line
memig3 18:9617bd66bdae 1 /*
memig3 18:9617bd66bdae 2 **************************************************************************************************************
memig3 18:9617bd66bdae 3 * NXP USB Host Stack
memig3 18:9617bd66bdae 4 *
memig3 18:9617bd66bdae 5 * (c) Copyright 2008, NXP SemiConductors
memig3 18:9617bd66bdae 6 * (c) Copyright 2008, OnChip Technologies LLC
memig3 18:9617bd66bdae 7 * All Rights Reserved
memig3 18:9617bd66bdae 8 *
memig3 18:9617bd66bdae 9 * www.nxp.com
memig3 18:9617bd66bdae 10 * www.onchiptech.com
memig3 18:9617bd66bdae 11 *
memig3 18:9617bd66bdae 12 * File : usbhost_lpc17xx.c
memig3 18:9617bd66bdae 13 * Programmer(s) : Ravikanth.P
memig3 18:9617bd66bdae 14 * Version :
memig3 18:9617bd66bdae 15 *
memig3 18:9617bd66bdae 16 **************************************************************************************************************
memig3 18:9617bd66bdae 17 */
memig3 18:9617bd66bdae 18
memig3 18:9617bd66bdae 19 /*
memig3 18:9617bd66bdae 20 **************************************************************************************************************
memig3 18:9617bd66bdae 21 * INCLUDE HEADER FILES
memig3 18:9617bd66bdae 22 **************************************************************************************************************
memig3 18:9617bd66bdae 23 */
memig3 18:9617bd66bdae 24
memig3 18:9617bd66bdae 25 #include "usbhost_lpc17xx.h"
memig3 18:9617bd66bdae 26
memig3 18:9617bd66bdae 27 /*
memig3 18:9617bd66bdae 28 **************************************************************************************************************
memig3 18:9617bd66bdae 29 * GLOBAL VARIABLES
memig3 18:9617bd66bdae 30 **************************************************************************************************************
memig3 18:9617bd66bdae 31 */
memig3 18:9617bd66bdae 32 int gUSBConnected;
memig3 18:9617bd66bdae 33
memig3 18:9617bd66bdae 34 volatile USB_INT32U HOST_RhscIntr = 0; /* Root Hub Status Change interrupt */
memig3 18:9617bd66bdae 35 volatile USB_INT32U HOST_WdhIntr = 0; /* Semaphore to wait until the TD is submitted */
memig3 18:9617bd66bdae 36 volatile USB_INT08U HOST_TDControlStatus = 0;
memig3 18:9617bd66bdae 37 volatile HCED *EDCtrl; /* Control endpoint descriptor structure */
memig3 18:9617bd66bdae 38 volatile HCED *EDBulkIn; /* BulkIn endpoint descriptor structure */
memig3 18:9617bd66bdae 39 volatile HCED *EDBulkOut; /* BulkOut endpoint descriptor structure */
memig3 18:9617bd66bdae 40 volatile HCTD *TDHead; /* Head transfer descriptor structure */
memig3 18:9617bd66bdae 41 volatile HCTD *TDTail; /* Tail transfer descriptor structure */
memig3 18:9617bd66bdae 42 volatile HCCA *Hcca; /* Host Controller Communications Area structure */
memig3 18:9617bd66bdae 43 USB_INT16U *TDBufNonVol; /* Identical to TDBuffer just to reduce compiler warnings */
memig3 18:9617bd66bdae 44 volatile USB_INT08U *TDBuffer; /* Current Buffer Pointer of transfer descriptor */
memig3 18:9617bd66bdae 45
memig3 18:9617bd66bdae 46 // USB host structures
memig3 18:9617bd66bdae 47 // AHB SRAM block 1
memig3 18:9617bd66bdae 48 #define HOSTBASEADDR 0x2007C000
memig3 18:9617bd66bdae 49 // reserve memory for the linker
memig3 18:9617bd66bdae 50 static USB_INT08U HostBuf[0x200] __attribute__((at(HOSTBASEADDR)));
memig3 18:9617bd66bdae 51 /*
memig3 18:9617bd66bdae 52 **************************************************************************************************************
memig3 18:9617bd66bdae 53 * DELAY IN MILLI SECONDS
memig3 18:9617bd66bdae 54 *
memig3 18:9617bd66bdae 55 * Description: This function provides a delay in milli seconds
memig3 18:9617bd66bdae 56 *
memig3 18:9617bd66bdae 57 * Arguments : delay The delay required
memig3 18:9617bd66bdae 58 *
memig3 18:9617bd66bdae 59 * Returns : None
memig3 18:9617bd66bdae 60 *
memig3 18:9617bd66bdae 61 **************************************************************************************************************
memig3 18:9617bd66bdae 62 */
memig3 18:9617bd66bdae 63
memig3 18:9617bd66bdae 64 void Host_DelayMS (USB_INT32U delay)
memig3 18:9617bd66bdae 65 {
memig3 18:9617bd66bdae 66 volatile USB_INT32U i;
memig3 18:9617bd66bdae 67
memig3 18:9617bd66bdae 68
memig3 18:9617bd66bdae 69 for (i = 0; i < delay; i++) {
memig3 18:9617bd66bdae 70 Host_DelayUS(1000);
memig3 18:9617bd66bdae 71 }
memig3 18:9617bd66bdae 72 }
memig3 18:9617bd66bdae 73
memig3 18:9617bd66bdae 74 /*
memig3 18:9617bd66bdae 75 **************************************************************************************************************
memig3 18:9617bd66bdae 76 * DELAY IN MICRO SECONDS
memig3 18:9617bd66bdae 77 *
memig3 18:9617bd66bdae 78 * Description: This function provides a delay in micro seconds
memig3 18:9617bd66bdae 79 *
memig3 18:9617bd66bdae 80 * Arguments : delay The delay required
memig3 18:9617bd66bdae 81 *
memig3 18:9617bd66bdae 82 * Returns : None
memig3 18:9617bd66bdae 83 *
memig3 18:9617bd66bdae 84 **************************************************************************************************************
memig3 18:9617bd66bdae 85 */
memig3 18:9617bd66bdae 86
memig3 18:9617bd66bdae 87 void Host_DelayUS (USB_INT32U delay)
memig3 18:9617bd66bdae 88 {
memig3 18:9617bd66bdae 89 volatile USB_INT32U i;
memig3 18:9617bd66bdae 90
memig3 18:9617bd66bdae 91
memig3 18:9617bd66bdae 92 for (i = 0; i < (4 * delay); i++) { /* This logic was tested. It gives app. 1 micro sec delay */
memig3 18:9617bd66bdae 93 ;
memig3 18:9617bd66bdae 94 }
memig3 18:9617bd66bdae 95 }
memig3 18:9617bd66bdae 96
memig3 18:9617bd66bdae 97 // bits of the USB/OTG clock control register
memig3 18:9617bd66bdae 98 #define HOST_CLK_EN (1<<0)
memig3 18:9617bd66bdae 99 #define DEV_CLK_EN (1<<1)
memig3 18:9617bd66bdae 100 #define PORTSEL_CLK_EN (1<<3)
memig3 18:9617bd66bdae 101 #define AHB_CLK_EN (1<<4)
memig3 18:9617bd66bdae 102
memig3 18:9617bd66bdae 103 // bits of the USB/OTG clock status register
memig3 18:9617bd66bdae 104 #define HOST_CLK_ON (1<<0)
memig3 18:9617bd66bdae 105 #define DEV_CLK_ON (1<<1)
memig3 18:9617bd66bdae 106 #define PORTSEL_CLK_ON (1<<3)
memig3 18:9617bd66bdae 107 #define AHB_CLK_ON (1<<4)
memig3 18:9617bd66bdae 108
memig3 18:9617bd66bdae 109 // we need host clock, OTG/portsel clock and AHB clock
memig3 18:9617bd66bdae 110 #define CLOCK_MASK (HOST_CLK_EN | PORTSEL_CLK_EN | AHB_CLK_EN)
memig3 18:9617bd66bdae 111
memig3 18:9617bd66bdae 112 /*
memig3 18:9617bd66bdae 113 **************************************************************************************************************
memig3 18:9617bd66bdae 114 * INITIALIZE THE HOST CONTROLLER
memig3 18:9617bd66bdae 115 *
memig3 18:9617bd66bdae 116 * Description: This function initializes lpc17xx host controller
memig3 18:9617bd66bdae 117 *
memig3 18:9617bd66bdae 118 * Arguments : None
memig3 18:9617bd66bdae 119 *
memig3 18:9617bd66bdae 120 * Returns :
memig3 18:9617bd66bdae 121 *
memig3 18:9617bd66bdae 122 **************************************************************************************************************
memig3 18:9617bd66bdae 123 */
memig3 18:9617bd66bdae 124 void Host_Init (void)
memig3 18:9617bd66bdae 125 {
memig3 18:9617bd66bdae 126 PRINT_Log("In Host_Init\n");
memig3 18:9617bd66bdae 127 NVIC_DisableIRQ(USB_IRQn); /* Disable the USB interrupt source */
memig3 18:9617bd66bdae 128
memig3 18:9617bd66bdae 129 // turn on power for USB
memig3 18:9617bd66bdae 130 LPC_SC->PCONP |= (1UL<<31);
memig3 18:9617bd66bdae 131 // Enable USB host clock, port selection and AHB clock
memig3 18:9617bd66bdae 132 LPC_USB->USBClkCtrl |= CLOCK_MASK;
memig3 18:9617bd66bdae 133 // Wait for clocks to become available
memig3 18:9617bd66bdae 134 while ((LPC_USB->USBClkSt & CLOCK_MASK) != CLOCK_MASK)
memig3 18:9617bd66bdae 135 ;
memig3 18:9617bd66bdae 136
memig3 18:9617bd66bdae 137 // it seems the bits[0:1] mean the following
memig3 18:9617bd66bdae 138 // 0: U1=device, U2=host
memig3 18:9617bd66bdae 139 // 1: U1=host, U2=host
memig3 18:9617bd66bdae 140 // 2: reserved
memig3 18:9617bd66bdae 141 // 3: U1=host, U2=device
memig3 18:9617bd66bdae 142 // NB: this register is only available if OTG clock (aka "port select") is enabled!!
memig3 18:9617bd66bdae 143 // since we don't care about port 2, set just bit 0 to 1 (U1=host)
memig3 18:9617bd66bdae 144 LPC_USB->OTGStCtrl |= 1;
memig3 18:9617bd66bdae 145
memig3 18:9617bd66bdae 146 // now that we've configured the ports, we can turn off the portsel clock
memig3 18:9617bd66bdae 147 LPC_USB->USBClkCtrl &= ~PORTSEL_CLK_EN;
memig3 18:9617bd66bdae 148
memig3 18:9617bd66bdae 149 // power pins are not connected on mbed, so we can skip them
memig3 18:9617bd66bdae 150 /* P1[18] = USB_UP_LED, 01 */
memig3 18:9617bd66bdae 151 /* P1[19] = /USB_PPWR, 10 */
memig3 18:9617bd66bdae 152 /* P1[22] = USB_PWRD, 10 */
memig3 18:9617bd66bdae 153 /* P1[27] = /USB_OVRCR, 10 */
memig3 18:9617bd66bdae 154 /*LPC_PINCON->PINSEL3 &= ~((3<<4) | (3<<6) | (3<<12) | (3<<22));
memig3 18:9617bd66bdae 155 LPC_PINCON->PINSEL3 |= ((1<<4)|(2<<6) | (2<<12) | (2<<22)); // 0x00802080
memig3 18:9617bd66bdae 156 */
memig3 18:9617bd66bdae 157
memig3 18:9617bd66bdae 158 // configure USB D+/D- pins
memig3 18:9617bd66bdae 159 /* P0[29] = USB_D+, 01 */
memig3 18:9617bd66bdae 160 /* P0[30] = USB_D-, 01 */
memig3 18:9617bd66bdae 161 LPC_PINCON->PINSEL1 &= ~((3<<26) | (3<<28));
memig3 18:9617bd66bdae 162 LPC_PINCON->PINSEL1 |= ((1<<26)|(1<<28)); // 0x14000000
memig3 18:9617bd66bdae 163
memig3 18:9617bd66bdae 164 PRINT_Log("Initializing Host Stack\n");
memig3 18:9617bd66bdae 165
memig3 18:9617bd66bdae 166 Hcca = (volatile HCCA *)(HostBuf+0x000);
memig3 18:9617bd66bdae 167 TDHead = (volatile HCTD *)(HostBuf+0x100);
memig3 18:9617bd66bdae 168 TDTail = (volatile HCTD *)(HostBuf+0x110);
memig3 18:9617bd66bdae 169 EDCtrl = (volatile HCED *)(HostBuf+0x120);
memig3 18:9617bd66bdae 170 EDBulkIn = (volatile HCED *)(HostBuf+0x130);
memig3 18:9617bd66bdae 171 EDBulkOut = (volatile HCED *)(HostBuf+0x140);
memig3 18:9617bd66bdae 172 TDBuffer = (volatile USB_INT08U *)(HostBuf+0x150);
memig3 18:9617bd66bdae 173
memig3 18:9617bd66bdae 174 /* Initialize all the TDs, EDs and HCCA to 0 */
memig3 18:9617bd66bdae 175 Host_EDInit(EDCtrl);
memig3 18:9617bd66bdae 176 Host_EDInit(EDBulkIn);
memig3 18:9617bd66bdae 177 Host_EDInit(EDBulkOut);
memig3 18:9617bd66bdae 178 Host_TDInit(TDHead);
memig3 18:9617bd66bdae 179 Host_TDInit(TDTail);
memig3 18:9617bd66bdae 180 Host_HCCAInit(Hcca);
memig3 18:9617bd66bdae 181
memig3 18:9617bd66bdae 182 Host_DelayMS(50); /* Wait 50 ms before apply reset */
memig3 18:9617bd66bdae 183 LPC_USB->HcControl = 0; /* HARDWARE RESET */
memig3 18:9617bd66bdae 184 LPC_USB->HcControlHeadED = 0; /* Initialize Control list head to Zero */
memig3 18:9617bd66bdae 185 LPC_USB->HcBulkHeadED = 0; /* Initialize Bulk list head to Zero */
memig3 18:9617bd66bdae 186
memig3 18:9617bd66bdae 187 /* SOFTWARE RESET */
memig3 18:9617bd66bdae 188 LPC_USB->HcCommandStatus = OR_CMD_STATUS_HCR;
memig3 18:9617bd66bdae 189 LPC_USB->HcFmInterval = DEFAULT_FMINTERVAL; /* Write Fm Interval and Largest Data Packet Counter */
memig3 18:9617bd66bdae 190
memig3 18:9617bd66bdae 191 /* Put HC in operational state */
memig3 18:9617bd66bdae 192 LPC_USB->HcControl = (LPC_USB->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
memig3 18:9617bd66bdae 193 LPC_USB->HcRhStatus = OR_RH_STATUS_LPSC; /* Set Global Power */
memig3 18:9617bd66bdae 194
memig3 18:9617bd66bdae 195 LPC_USB->HcHCCA = (USB_INT32U)Hcca;
memig3 18:9617bd66bdae 196 LPC_USB->HcInterruptStatus |= LPC_USB->HcInterruptStatus; /* Clear Interrrupt Status */
memig3 18:9617bd66bdae 197
memig3 18:9617bd66bdae 198
memig3 18:9617bd66bdae 199 LPC_USB->HcInterruptEnable = OR_INTR_ENABLE_MIE |
memig3 18:9617bd66bdae 200 OR_INTR_ENABLE_WDH |
memig3 18:9617bd66bdae 201 OR_INTR_ENABLE_RHSC;
memig3 18:9617bd66bdae 202
memig3 18:9617bd66bdae 203 NVIC_SetPriority(USB_IRQn, 0); /* highest priority */
memig3 18:9617bd66bdae 204 /* Enable the USB Interrupt */
memig3 18:9617bd66bdae 205 NVIC_EnableIRQ(USB_IRQn);
memig3 18:9617bd66bdae 206 PRINT_Log("Host Initialized\n");
memig3 18:9617bd66bdae 207 }
memig3 18:9617bd66bdae 208
memig3 18:9617bd66bdae 209 /*
memig3 18:9617bd66bdae 210 **************************************************************************************************************
memig3 18:9617bd66bdae 211 * INTERRUPT SERVICE ROUTINE
memig3 18:9617bd66bdae 212 *
memig3 18:9617bd66bdae 213 * Description: This function services the interrupt caused by host controller
memig3 18:9617bd66bdae 214 *
memig3 18:9617bd66bdae 215 * Arguments : None
memig3 18:9617bd66bdae 216 *
memig3 18:9617bd66bdae 217 * Returns : None
memig3 18:9617bd66bdae 218 *
memig3 18:9617bd66bdae 219 **************************************************************************************************************
memig3 18:9617bd66bdae 220 */
memig3 18:9617bd66bdae 221
memig3 18:9617bd66bdae 222 void USB_IRQHandler (void) __irq
memig3 18:9617bd66bdae 223 {
memig3 18:9617bd66bdae 224 USB_INT32U int_status;
memig3 18:9617bd66bdae 225 USB_INT32U ie_status;
memig3 18:9617bd66bdae 226
memig3 18:9617bd66bdae 227 int_status = LPC_USB->HcInterruptStatus; /* Read Interrupt Status */
memig3 18:9617bd66bdae 228 ie_status = LPC_USB->HcInterruptEnable; /* Read Interrupt enable status */
memig3 18:9617bd66bdae 229
memig3 18:9617bd66bdae 230 if (!(int_status & ie_status)) {
memig3 18:9617bd66bdae 231 return;
memig3 18:9617bd66bdae 232 } else {
memig3 18:9617bd66bdae 233
memig3 18:9617bd66bdae 234 int_status = int_status & ie_status;
memig3 18:9617bd66bdae 235 if (int_status & OR_INTR_STATUS_RHSC) { /* Root hub status change interrupt */
memig3 18:9617bd66bdae 236 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CSC) {
memig3 18:9617bd66bdae 237 if (LPC_USB->HcRhStatus & OR_RH_STATUS_DRWE) {
memig3 18:9617bd66bdae 238 /*
memig3 18:9617bd66bdae 239 * When DRWE is on, Connect Status Change
memig3 18:9617bd66bdae 240 * means a remote wakeup event.
memig3 18:9617bd66bdae 241 */
memig3 18:9617bd66bdae 242 HOST_RhscIntr = 1;// JUST SOMETHING FOR A BREAKPOINT
memig3 18:9617bd66bdae 243 }
memig3 18:9617bd66bdae 244 else {
memig3 18:9617bd66bdae 245 /*
memig3 18:9617bd66bdae 246 * When DRWE is off, Connect Status Change
memig3 18:9617bd66bdae 247 * is NOT a remote wakeup event
memig3 18:9617bd66bdae 248 */
memig3 18:9617bd66bdae 249 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
memig3 18:9617bd66bdae 250 if (!gUSBConnected) {
memig3 18:9617bd66bdae 251 HOST_TDControlStatus = 0;
memig3 18:9617bd66bdae 252 HOST_WdhIntr = 0;
memig3 18:9617bd66bdae 253 HOST_RhscIntr = 1;
memig3 18:9617bd66bdae 254 gUSBConnected = 1;
memig3 18:9617bd66bdae 255 }
memig3 18:9617bd66bdae 256 else
memig3 18:9617bd66bdae 257 PRINT_Log("Spurious status change (connected)?\n");
memig3 18:9617bd66bdae 258 } else {
memig3 18:9617bd66bdae 259 if (gUSBConnected) {
memig3 18:9617bd66bdae 260 LPC_USB->HcInterruptEnable = 0; // why do we get multiple disc. rupts???
memig3 18:9617bd66bdae 261 HOST_RhscIntr = 0;
memig3 18:9617bd66bdae 262 gUSBConnected = 0;
memig3 18:9617bd66bdae 263 }
memig3 18:9617bd66bdae 264 else
memig3 18:9617bd66bdae 265 PRINT_Log("Spurious status change (disconnected)?\n");
memig3 18:9617bd66bdae 266 }
memig3 18:9617bd66bdae 267 }
memig3 18:9617bd66bdae 268 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
memig3 18:9617bd66bdae 269 }
memig3 18:9617bd66bdae 270 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRSC) {
memig3 18:9617bd66bdae 271 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
memig3 18:9617bd66bdae 272 }
memig3 18:9617bd66bdae 273 }
memig3 18:9617bd66bdae 274 if (int_status & OR_INTR_STATUS_WDH) { /* Writeback Done Head interrupt */
memig3 18:9617bd66bdae 275 HOST_WdhIntr = 1;
memig3 18:9617bd66bdae 276 HOST_TDControlStatus = (TDHead->Control >> 28) & 0xf;
memig3 18:9617bd66bdae 277 }
memig3 18:9617bd66bdae 278 LPC_USB->HcInterruptStatus = int_status; /* Clear interrupt status register */
memig3 18:9617bd66bdae 279 }
memig3 18:9617bd66bdae 280 return;
memig3 18:9617bd66bdae 281 }
memig3 18:9617bd66bdae 282
memig3 18:9617bd66bdae 283 /*
memig3 18:9617bd66bdae 284 **************************************************************************************************************
memig3 18:9617bd66bdae 285 * PROCESS TRANSFER DESCRIPTOR
memig3 18:9617bd66bdae 286 *
memig3 18:9617bd66bdae 287 * Description: This function processes the transfer descriptor
memig3 18:9617bd66bdae 288 *
memig3 18:9617bd66bdae 289 * Arguments : ed Endpoint descriptor that contains this transfer descriptor
memig3 18:9617bd66bdae 290 * token SETUP, IN, OUT
memig3 18:9617bd66bdae 291 * buffer Current Buffer Pointer of the transfer descriptor
memig3 18:9617bd66bdae 292 * buffer_len Length of the buffer
memig3 18:9617bd66bdae 293 *
memig3 18:9617bd66bdae 294 * Returns : OK if TD submission is successful
memig3 18:9617bd66bdae 295 * ERROR if TD submission fails
memig3 18:9617bd66bdae 296 *
memig3 18:9617bd66bdae 297 **************************************************************************************************************
memig3 18:9617bd66bdae 298 */
memig3 18:9617bd66bdae 299
memig3 18:9617bd66bdae 300 USB_INT32S Host_ProcessTD (volatile HCED *ed,
memig3 18:9617bd66bdae 301 volatile USB_INT32U token,
memig3 18:9617bd66bdae 302 volatile USB_INT08U *buffer,
memig3 18:9617bd66bdae 303 USB_INT32U buffer_len)
memig3 18:9617bd66bdae 304 {
memig3 18:9617bd66bdae 305 volatile USB_INT32U td_toggle;
memig3 18:9617bd66bdae 306
memig3 18:9617bd66bdae 307
memig3 18:9617bd66bdae 308 if (ed == EDCtrl) {
memig3 18:9617bd66bdae 309 if (token == TD_SETUP) {
memig3 18:9617bd66bdae 310 td_toggle = TD_TOGGLE_0;
memig3 18:9617bd66bdae 311 } else {
memig3 18:9617bd66bdae 312 td_toggle = TD_TOGGLE_1;
memig3 18:9617bd66bdae 313 }
memig3 18:9617bd66bdae 314 } else {
memig3 18:9617bd66bdae 315 td_toggle = 0;
memig3 18:9617bd66bdae 316 }
memig3 18:9617bd66bdae 317 TDHead->Control = (TD_ROUNDING |
memig3 18:9617bd66bdae 318 token |
memig3 18:9617bd66bdae 319 TD_DELAY_INT(0) |
memig3 18:9617bd66bdae 320 td_toggle |
memig3 18:9617bd66bdae 321 TD_CC);
memig3 18:9617bd66bdae 322 TDTail->Control = 0;
memig3 18:9617bd66bdae 323 TDHead->CurrBufPtr = (USB_INT32U) buffer;
memig3 18:9617bd66bdae 324 TDTail->CurrBufPtr = 0;
memig3 18:9617bd66bdae 325 TDHead->Next = (USB_INT32U) TDTail;
memig3 18:9617bd66bdae 326 TDTail->Next = 0;
memig3 18:9617bd66bdae 327 TDHead->BufEnd = (USB_INT32U)(buffer + (buffer_len - 1));
memig3 18:9617bd66bdae 328 TDTail->BufEnd = 0;
memig3 18:9617bd66bdae 329
memig3 18:9617bd66bdae 330 ed->HeadTd = (USB_INT32U)TDHead | ((ed->HeadTd) & 0x00000002);
memig3 18:9617bd66bdae 331 ed->TailTd = (USB_INT32U)TDTail;
memig3 18:9617bd66bdae 332 ed->Next = 0;
memig3 18:9617bd66bdae 333
memig3 18:9617bd66bdae 334 if (ed == EDCtrl) {
memig3 18:9617bd66bdae 335 LPC_USB->HcControlHeadED = (USB_INT32U)ed;
memig3 18:9617bd66bdae 336 LPC_USB->HcCommandStatus = LPC_USB->HcCommandStatus | OR_CMD_STATUS_CLF;
memig3 18:9617bd66bdae 337 LPC_USB->HcControl = LPC_USB->HcControl | OR_CONTROL_CLE;
memig3 18:9617bd66bdae 338 } else {
memig3 18:9617bd66bdae 339 LPC_USB->HcBulkHeadED = (USB_INT32U)ed;
memig3 18:9617bd66bdae 340 LPC_USB->HcCommandStatus = LPC_USB->HcCommandStatus | OR_CMD_STATUS_BLF;
memig3 18:9617bd66bdae 341 LPC_USB->HcControl = LPC_USB->HcControl | OR_CONTROL_BLE;
memig3 18:9617bd66bdae 342 }
memig3 18:9617bd66bdae 343
memig3 18:9617bd66bdae 344 Host_WDHWait();
memig3 18:9617bd66bdae 345
memig3 18:9617bd66bdae 346 // if (!(TDHead->Control & 0xF0000000)) {
memig3 18:9617bd66bdae 347 if (!HOST_TDControlStatus) {
memig3 18:9617bd66bdae 348 return (OK);
memig3 18:9617bd66bdae 349 } else {
memig3 18:9617bd66bdae 350 return (ERR_TD_FAIL);
memig3 18:9617bd66bdae 351 }
memig3 18:9617bd66bdae 352 }
memig3 18:9617bd66bdae 353
memig3 18:9617bd66bdae 354 /*
memig3 18:9617bd66bdae 355 **************************************************************************************************************
memig3 18:9617bd66bdae 356 * ENUMERATE THE DEVICE
memig3 18:9617bd66bdae 357 *
memig3 18:9617bd66bdae 358 * Description: This function is used to enumerate the device connected
memig3 18:9617bd66bdae 359 *
memig3 18:9617bd66bdae 360 * Arguments : None
memig3 18:9617bd66bdae 361 *
memig3 18:9617bd66bdae 362 * Returns : None
memig3 18:9617bd66bdae 363 *
memig3 18:9617bd66bdae 364 **************************************************************************************************************
memig3 18:9617bd66bdae 365 */
memig3 18:9617bd66bdae 366
memig3 18:9617bd66bdae 367 USB_INT32S Host_EnumDev (void)
memig3 18:9617bd66bdae 368 {
memig3 18:9617bd66bdae 369 USB_INT32S rc;
memig3 18:9617bd66bdae 370
memig3 18:9617bd66bdae 371 PRINT_Log("Connect a Mass Storage device\n");
memig3 18:9617bd66bdae 372 while (!HOST_RhscIntr)
memig3 18:9617bd66bdae 373 __WFI();
memig3 18:9617bd66bdae 374 Host_DelayMS(100); /* USB 2.0 spec says atleast 50ms delay beore port reset */
memig3 18:9617bd66bdae 375 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRS; // Initiate port reset
memig3 18:9617bd66bdae 376 while (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRS)
memig3 18:9617bd66bdae 377 __WFI(); // Wait for port reset to complete...
memig3 18:9617bd66bdae 378 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC; // ...and clear port reset signal
memig3 18:9617bd66bdae 379 Host_DelayMS(200); /* Wait for 100 MS after port reset */
memig3 18:9617bd66bdae 380
memig3 18:9617bd66bdae 381 EDCtrl->Control = 8 << 16; /* Put max pkt size = 8 */
memig3 18:9617bd66bdae 382 /* Read first 8 bytes of device desc */
memig3 18:9617bd66bdae 383 rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_DEVICE, 0, TDBuffer, 8);
memig3 18:9617bd66bdae 384 if (rc != OK) {
memig3 18:9617bd66bdae 385 PRINT_Err(rc);
memig3 18:9617bd66bdae 386 return (rc);
memig3 18:9617bd66bdae 387 }
memig3 18:9617bd66bdae 388 EDCtrl->Control = TDBuffer[7] << 16; /* Get max pkt size of endpoint 0 */
memig3 18:9617bd66bdae 389 rc = HOST_SET_ADDRESS(1); /* Set the device address to 1 */
memig3 18:9617bd66bdae 390 if (rc != OK) {
memig3 18:9617bd66bdae 391 PRINT_Err(rc);
memig3 18:9617bd66bdae 392 return (rc);
memig3 18:9617bd66bdae 393 }
memig3 18:9617bd66bdae 394 Host_DelayMS(2);
memig3 18:9617bd66bdae 395 EDCtrl->Control = (EDCtrl->Control) | 1; /* Modify control pipe with address 1 */
memig3 18:9617bd66bdae 396 /* Get the configuration descriptor */
memig3 18:9617bd66bdae 397 rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_CONFIGURATION, 0, TDBuffer, 9);
memig3 18:9617bd66bdae 398 if (rc != OK) {
memig3 18:9617bd66bdae 399 PRINT_Err(rc);
memig3 18:9617bd66bdae 400 return (rc);
memig3 18:9617bd66bdae 401 }
memig3 18:9617bd66bdae 402 /* Get the first configuration data */
memig3 18:9617bd66bdae 403 rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_CONFIGURATION, 0, TDBuffer, ReadLE16U(&TDBuffer[2]));
memig3 18:9617bd66bdae 404 if (rc != OK) {
memig3 18:9617bd66bdae 405 PRINT_Err(rc);
memig3 18:9617bd66bdae 406 return (rc);
memig3 18:9617bd66bdae 407 }
memig3 18:9617bd66bdae 408 rc = MS_ParseConfiguration(); /* Parse the configuration */
memig3 18:9617bd66bdae 409 if (rc != OK) {
memig3 18:9617bd66bdae 410 PRINT_Err(rc);
memig3 18:9617bd66bdae 411 return (rc);
memig3 18:9617bd66bdae 412 }
memig3 18:9617bd66bdae 413 rc = USBH_SET_CONFIGURATION(1); /* Select device configuration 1 */
memig3 18:9617bd66bdae 414 if (rc != OK) {
memig3 18:9617bd66bdae 415 PRINT_Err(rc);
memig3 18:9617bd66bdae 416 }
memig3 18:9617bd66bdae 417 Host_DelayMS(100); /* Some devices may require this delay */
memig3 18:9617bd66bdae 418 return (rc);
memig3 18:9617bd66bdae 419 }
memig3 18:9617bd66bdae 420
memig3 18:9617bd66bdae 421 /*
memig3 18:9617bd66bdae 422 **************************************************************************************************************
memig3 18:9617bd66bdae 423 * RECEIVE THE CONTROL INFORMATION
memig3 18:9617bd66bdae 424 *
memig3 18:9617bd66bdae 425 * Description: This function is used to receive the control information
memig3 18:9617bd66bdae 426 *
memig3 18:9617bd66bdae 427 * Arguments : bm_request_type
memig3 18:9617bd66bdae 428 * b_request
memig3 18:9617bd66bdae 429 * w_value
memig3 18:9617bd66bdae 430 * w_index
memig3 18:9617bd66bdae 431 * w_length
memig3 18:9617bd66bdae 432 * buffer
memig3 18:9617bd66bdae 433 *
memig3 18:9617bd66bdae 434 * Returns : OK if Success
memig3 18:9617bd66bdae 435 * ERROR if Failed
memig3 18:9617bd66bdae 436 *
memig3 18:9617bd66bdae 437 **************************************************************************************************************
memig3 18:9617bd66bdae 438 */
memig3 18:9617bd66bdae 439
memig3 18:9617bd66bdae 440 USB_INT32S Host_CtrlRecv ( USB_INT08U bm_request_type,
memig3 18:9617bd66bdae 441 USB_INT08U b_request,
memig3 18:9617bd66bdae 442 USB_INT16U w_value,
memig3 18:9617bd66bdae 443 USB_INT16U w_index,
memig3 18:9617bd66bdae 444 USB_INT16U w_length,
memig3 18:9617bd66bdae 445 volatile USB_INT08U *buffer)
memig3 18:9617bd66bdae 446 {
memig3 18:9617bd66bdae 447 USB_INT32S rc;
memig3 18:9617bd66bdae 448
memig3 18:9617bd66bdae 449
memig3 18:9617bd66bdae 450 Host_FillSetup(bm_request_type, b_request, w_value, w_index, w_length);
memig3 18:9617bd66bdae 451 rc = Host_ProcessTD(EDCtrl, TD_SETUP, TDBuffer, 8);
memig3 18:9617bd66bdae 452 if (rc == OK) {
memig3 18:9617bd66bdae 453 if (w_length) {
memig3 18:9617bd66bdae 454 rc = Host_ProcessTD(EDCtrl, TD_IN, TDBuffer, w_length);
memig3 18:9617bd66bdae 455 }
memig3 18:9617bd66bdae 456 if (rc == OK) {
memig3 18:9617bd66bdae 457 rc = Host_ProcessTD(EDCtrl, TD_OUT, NULL, 0);
memig3 18:9617bd66bdae 458 }
memig3 18:9617bd66bdae 459 }
memig3 18:9617bd66bdae 460 return (rc);
memig3 18:9617bd66bdae 461 }
memig3 18:9617bd66bdae 462
memig3 18:9617bd66bdae 463 /*
memig3 18:9617bd66bdae 464 **************************************************************************************************************
memig3 18:9617bd66bdae 465 * SEND THE CONTROL INFORMATION
memig3 18:9617bd66bdae 466 *
memig3 18:9617bd66bdae 467 * Description: This function is used to send the control information
memig3 18:9617bd66bdae 468 *
memig3 18:9617bd66bdae 469 * Arguments : None
memig3 18:9617bd66bdae 470 *
memig3 18:9617bd66bdae 471 * Returns : OK if Success
memig3 18:9617bd66bdae 472 * ERR_INVALID_BOOTSIG if Failed
memig3 18:9617bd66bdae 473 *
memig3 18:9617bd66bdae 474 **************************************************************************************************************
memig3 18:9617bd66bdae 475 */
memig3 18:9617bd66bdae 476
memig3 18:9617bd66bdae 477 USB_INT32S Host_CtrlSend ( USB_INT08U bm_request_type,
memig3 18:9617bd66bdae 478 USB_INT08U b_request,
memig3 18:9617bd66bdae 479 USB_INT16U w_value,
memig3 18:9617bd66bdae 480 USB_INT16U w_index,
memig3 18:9617bd66bdae 481 USB_INT16U w_length,
memig3 18:9617bd66bdae 482 volatile USB_INT08U *buffer)
memig3 18:9617bd66bdae 483 {
memig3 18:9617bd66bdae 484 USB_INT32S rc;
memig3 18:9617bd66bdae 485
memig3 18:9617bd66bdae 486
memig3 18:9617bd66bdae 487 Host_FillSetup(bm_request_type, b_request, w_value, w_index, w_length);
memig3 18:9617bd66bdae 488
memig3 18:9617bd66bdae 489 rc = Host_ProcessTD(EDCtrl, TD_SETUP, TDBuffer, 8);
memig3 18:9617bd66bdae 490 if (rc == OK) {
memig3 18:9617bd66bdae 491 if (w_length) {
memig3 18:9617bd66bdae 492 rc = Host_ProcessTD(EDCtrl, TD_OUT, TDBuffer, w_length);
memig3 18:9617bd66bdae 493 }
memig3 18:9617bd66bdae 494 if (rc == OK) {
memig3 18:9617bd66bdae 495 rc = Host_ProcessTD(EDCtrl, TD_IN, NULL, 0);
memig3 18:9617bd66bdae 496 }
memig3 18:9617bd66bdae 497 }
memig3 18:9617bd66bdae 498 return (rc);
memig3 18:9617bd66bdae 499 }
memig3 18:9617bd66bdae 500
memig3 18:9617bd66bdae 501 /*
memig3 18:9617bd66bdae 502 **************************************************************************************************************
memig3 18:9617bd66bdae 503 * FILL SETUP PACKET
memig3 18:9617bd66bdae 504 *
memig3 18:9617bd66bdae 505 * Description: This function is used to fill the setup packet
memig3 18:9617bd66bdae 506 *
memig3 18:9617bd66bdae 507 * Arguments : None
memig3 18:9617bd66bdae 508 *
memig3 18:9617bd66bdae 509 * Returns : OK if Success
memig3 18:9617bd66bdae 510 * ERR_INVALID_BOOTSIG if Failed
memig3 18:9617bd66bdae 511 *
memig3 18:9617bd66bdae 512 **************************************************************************************************************
memig3 18:9617bd66bdae 513 */
memig3 18:9617bd66bdae 514
memig3 18:9617bd66bdae 515 void Host_FillSetup (USB_INT08U bm_request_type,
memig3 18:9617bd66bdae 516 USB_INT08U b_request,
memig3 18:9617bd66bdae 517 USB_INT16U w_value,
memig3 18:9617bd66bdae 518 USB_INT16U w_index,
memig3 18:9617bd66bdae 519 USB_INT16U w_length)
memig3 18:9617bd66bdae 520 {
memig3 18:9617bd66bdae 521 int i;
memig3 18:9617bd66bdae 522 for (i=0;i<w_length;i++)
memig3 18:9617bd66bdae 523 TDBuffer[i] = 0;
memig3 18:9617bd66bdae 524
memig3 18:9617bd66bdae 525 TDBuffer[0] = bm_request_type;
memig3 18:9617bd66bdae 526 TDBuffer[1] = b_request;
memig3 18:9617bd66bdae 527 WriteLE16U(&TDBuffer[2], w_value);
memig3 18:9617bd66bdae 528 WriteLE16U(&TDBuffer[4], w_index);
memig3 18:9617bd66bdae 529 WriteLE16U(&TDBuffer[6], w_length);
memig3 18:9617bd66bdae 530 }
memig3 18:9617bd66bdae 531
memig3 18:9617bd66bdae 532
memig3 18:9617bd66bdae 533
memig3 18:9617bd66bdae 534 /*
memig3 18:9617bd66bdae 535 **************************************************************************************************************
memig3 18:9617bd66bdae 536 * INITIALIZE THE TRANSFER DESCRIPTOR
memig3 18:9617bd66bdae 537 *
memig3 18:9617bd66bdae 538 * Description: This function initializes transfer descriptor
memig3 18:9617bd66bdae 539 *
memig3 18:9617bd66bdae 540 * Arguments : Pointer to TD structure
memig3 18:9617bd66bdae 541 *
memig3 18:9617bd66bdae 542 * Returns : None
memig3 18:9617bd66bdae 543 *
memig3 18:9617bd66bdae 544 **************************************************************************************************************
memig3 18:9617bd66bdae 545 */
memig3 18:9617bd66bdae 546
memig3 18:9617bd66bdae 547 void Host_TDInit (volatile HCTD *td)
memig3 18:9617bd66bdae 548 {
memig3 18:9617bd66bdae 549
memig3 18:9617bd66bdae 550 td->Control = 0;
memig3 18:9617bd66bdae 551 td->CurrBufPtr = 0;
memig3 18:9617bd66bdae 552 td->Next = 0;
memig3 18:9617bd66bdae 553 td->BufEnd = 0;
memig3 18:9617bd66bdae 554 }
memig3 18:9617bd66bdae 555
memig3 18:9617bd66bdae 556 /*
memig3 18:9617bd66bdae 557 **************************************************************************************************************
memig3 18:9617bd66bdae 558 * INITIALIZE THE ENDPOINT DESCRIPTOR
memig3 18:9617bd66bdae 559 *
memig3 18:9617bd66bdae 560 * Description: This function initializes endpoint descriptor
memig3 18:9617bd66bdae 561 *
memig3 18:9617bd66bdae 562 * Arguments : Pointer to ED strcuture
memig3 18:9617bd66bdae 563 *
memig3 18:9617bd66bdae 564 * Returns : None
memig3 18:9617bd66bdae 565 *
memig3 18:9617bd66bdae 566 **************************************************************************************************************
memig3 18:9617bd66bdae 567 */
memig3 18:9617bd66bdae 568
memig3 18:9617bd66bdae 569 void Host_EDInit (volatile HCED *ed)
memig3 18:9617bd66bdae 570 {
memig3 18:9617bd66bdae 571
memig3 18:9617bd66bdae 572 ed->Control = 0;
memig3 18:9617bd66bdae 573 ed->TailTd = 0;
memig3 18:9617bd66bdae 574 ed->HeadTd = 0;
memig3 18:9617bd66bdae 575 ed->Next = 0;
memig3 18:9617bd66bdae 576 }
memig3 18:9617bd66bdae 577
memig3 18:9617bd66bdae 578 /*
memig3 18:9617bd66bdae 579 **************************************************************************************************************
memig3 18:9617bd66bdae 580 * INITIALIZE HOST CONTROLLER COMMUNICATIONS AREA
memig3 18:9617bd66bdae 581 *
memig3 18:9617bd66bdae 582 * Description: This function initializes host controller communications area
memig3 18:9617bd66bdae 583 *
memig3 18:9617bd66bdae 584 * Arguments : Pointer to HCCA
memig3 18:9617bd66bdae 585 *
memig3 18:9617bd66bdae 586 * Returns :
memig3 18:9617bd66bdae 587 *
memig3 18:9617bd66bdae 588 **************************************************************************************************************
memig3 18:9617bd66bdae 589 */
memig3 18:9617bd66bdae 590
memig3 18:9617bd66bdae 591 void Host_HCCAInit (volatile HCCA *hcca)
memig3 18:9617bd66bdae 592 {
memig3 18:9617bd66bdae 593 USB_INT32U i;
memig3 18:9617bd66bdae 594
memig3 18:9617bd66bdae 595
memig3 18:9617bd66bdae 596 for (i = 0; i < 32; i++) {
memig3 18:9617bd66bdae 597
memig3 18:9617bd66bdae 598 hcca->IntTable[i] = 0;
memig3 18:9617bd66bdae 599 hcca->FrameNumber = 0;
memig3 18:9617bd66bdae 600 hcca->DoneHead = 0;
memig3 18:9617bd66bdae 601 }
memig3 18:9617bd66bdae 602
memig3 18:9617bd66bdae 603 }
memig3 18:9617bd66bdae 604
memig3 18:9617bd66bdae 605 /*
memig3 18:9617bd66bdae 606 **************************************************************************************************************
memig3 18:9617bd66bdae 607 * WAIT FOR WDH INTERRUPT
memig3 18:9617bd66bdae 608 *
memig3 18:9617bd66bdae 609 * Description: This function is infinite loop which breaks when ever a WDH interrupt rises
memig3 18:9617bd66bdae 610 *
memig3 18:9617bd66bdae 611 * Arguments : None
memig3 18:9617bd66bdae 612 *
memig3 18:9617bd66bdae 613 * Returns : None
memig3 18:9617bd66bdae 614 *
memig3 18:9617bd66bdae 615 **************************************************************************************************************
memig3 18:9617bd66bdae 616 */
memig3 18:9617bd66bdae 617
memig3 18:9617bd66bdae 618 void Host_WDHWait (void)
memig3 18:9617bd66bdae 619 {
memig3 18:9617bd66bdae 620 while (!HOST_WdhIntr)
memig3 18:9617bd66bdae 621 __WFI();
memig3 18:9617bd66bdae 622
memig3 18:9617bd66bdae 623 HOST_WdhIntr = 0;
memig3 18:9617bd66bdae 624 }
memig3 18:9617bd66bdae 625
memig3 18:9617bd66bdae 626 /*
memig3 18:9617bd66bdae 627 **************************************************************************************************************
memig3 18:9617bd66bdae 628 * READ LE 32U
memig3 18:9617bd66bdae 629 *
memig3 18:9617bd66bdae 630 * Description: This function is used to read an unsigned integer from a character buffer in the platform
memig3 18:9617bd66bdae 631 * containing little endian processor
memig3 18:9617bd66bdae 632 *
memig3 18:9617bd66bdae 633 * Arguments : pmem Pointer to the character buffer
memig3 18:9617bd66bdae 634 *
memig3 18:9617bd66bdae 635 * Returns : val Unsigned integer
memig3 18:9617bd66bdae 636 *
memig3 18:9617bd66bdae 637 **************************************************************************************************************
memig3 18:9617bd66bdae 638 */
memig3 18:9617bd66bdae 639
memig3 18:9617bd66bdae 640 USB_INT32U ReadLE32U (volatile USB_INT08U *pmem)
memig3 18:9617bd66bdae 641 {
memig3 18:9617bd66bdae 642 USB_INT32U val = *(USB_INT32U*)pmem;
memig3 18:9617bd66bdae 643 #ifdef __BIG_ENDIAN
memig3 18:9617bd66bdae 644 return __REV(val);
memig3 18:9617bd66bdae 645 #else
memig3 18:9617bd66bdae 646 return val;
memig3 18:9617bd66bdae 647 #endif
memig3 18:9617bd66bdae 648 }
memig3 18:9617bd66bdae 649
memig3 18:9617bd66bdae 650 /*
memig3 18:9617bd66bdae 651 **************************************************************************************************************
memig3 18:9617bd66bdae 652 * WRITE LE 32U
memig3 18:9617bd66bdae 653 *
memig3 18:9617bd66bdae 654 * Description: This function is used to write an unsigned integer into a charecter buffer in the platform
memig3 18:9617bd66bdae 655 * containing little endian processor.
memig3 18:9617bd66bdae 656 *
memig3 18:9617bd66bdae 657 * Arguments : pmem Pointer to the charecter buffer
memig3 18:9617bd66bdae 658 * val Integer value to be placed in the charecter buffer
memig3 18:9617bd66bdae 659 *
memig3 18:9617bd66bdae 660 * Returns : None
memig3 18:9617bd66bdae 661 *
memig3 18:9617bd66bdae 662 **************************************************************************************************************
memig3 18:9617bd66bdae 663 */
memig3 18:9617bd66bdae 664
memig3 18:9617bd66bdae 665 void WriteLE32U (volatile USB_INT08U *pmem,
memig3 18:9617bd66bdae 666 USB_INT32U val)
memig3 18:9617bd66bdae 667 {
memig3 18:9617bd66bdae 668 #ifdef __BIG_ENDIAN
memig3 18:9617bd66bdae 669 *(USB_INT32U*)pmem = __REV(val);
memig3 18:9617bd66bdae 670 #else
memig3 18:9617bd66bdae 671 *(USB_INT32U*)pmem = val;
memig3 18:9617bd66bdae 672 #endif
memig3 18:9617bd66bdae 673 }
memig3 18:9617bd66bdae 674
memig3 18:9617bd66bdae 675 /*
memig3 18:9617bd66bdae 676 **************************************************************************************************************
memig3 18:9617bd66bdae 677 * READ LE 16U
memig3 18:9617bd66bdae 678 *
memig3 18:9617bd66bdae 679 * Description: This function is used to read an unsigned short integer from a charecter buffer in the platform
memig3 18:9617bd66bdae 680 * containing little endian processor
memig3 18:9617bd66bdae 681 *
memig3 18:9617bd66bdae 682 * Arguments : pmem Pointer to the charecter buffer
memig3 18:9617bd66bdae 683 *
memig3 18:9617bd66bdae 684 * Returns : val Unsigned short integer
memig3 18:9617bd66bdae 685 *
memig3 18:9617bd66bdae 686 **************************************************************************************************************
memig3 18:9617bd66bdae 687 */
memig3 18:9617bd66bdae 688
memig3 18:9617bd66bdae 689 USB_INT16U ReadLE16U (volatile USB_INT08U *pmem)
memig3 18:9617bd66bdae 690 {
memig3 18:9617bd66bdae 691 USB_INT16U val = *(USB_INT16U*)pmem;
memig3 18:9617bd66bdae 692 #ifdef __BIG_ENDIAN
memig3 18:9617bd66bdae 693 return __REV16(val);
memig3 18:9617bd66bdae 694 #else
memig3 18:9617bd66bdae 695 return val;
memig3 18:9617bd66bdae 696 #endif
memig3 18:9617bd66bdae 697 }
memig3 18:9617bd66bdae 698
memig3 18:9617bd66bdae 699 /*
memig3 18:9617bd66bdae 700 **************************************************************************************************************
memig3 18:9617bd66bdae 701 * WRITE LE 16U
memig3 18:9617bd66bdae 702 *
memig3 18:9617bd66bdae 703 * Description: This function is used to write an unsigned short integer into a charecter buffer in the
memig3 18:9617bd66bdae 704 * platform containing little endian processor
memig3 18:9617bd66bdae 705 *
memig3 18:9617bd66bdae 706 * Arguments : pmem Pointer to the charecter buffer
memig3 18:9617bd66bdae 707 * val Value to be placed in the charecter buffer
memig3 18:9617bd66bdae 708 *
memig3 18:9617bd66bdae 709 * Returns : None
memig3 18:9617bd66bdae 710 *
memig3 18:9617bd66bdae 711 **************************************************************************************************************
memig3 18:9617bd66bdae 712 */
memig3 18:9617bd66bdae 713
memig3 18:9617bd66bdae 714 void WriteLE16U (volatile USB_INT08U *pmem,
memig3 18:9617bd66bdae 715 USB_INT16U val)
memig3 18:9617bd66bdae 716 {
memig3 18:9617bd66bdae 717 #ifdef __BIG_ENDIAN
memig3 18:9617bd66bdae 718 *(USB_INT16U*)pmem = (__REV16(val) & 0xFFFF);
memig3 18:9617bd66bdae 719 #else
memig3 18:9617bd66bdae 720 *(USB_INT16U*)pmem = val;
memig3 18:9617bd66bdae 721 #endif
memig3 18:9617bd66bdae 722 }
memig3 18:9617bd66bdae 723
memig3 18:9617bd66bdae 724 /*
memig3 18:9617bd66bdae 725 **************************************************************************************************************
memig3 18:9617bd66bdae 726 * READ BE 32U
memig3 18:9617bd66bdae 727 *
memig3 18:9617bd66bdae 728 * Description: This function is used to read an unsigned integer from a charecter buffer in the platform
memig3 18:9617bd66bdae 729 * containing big endian processor
memig3 18:9617bd66bdae 730 *
memig3 18:9617bd66bdae 731 * Arguments : pmem Pointer to the charecter buffer
memig3 18:9617bd66bdae 732 *
memig3 18:9617bd66bdae 733 * Returns : val Unsigned integer
memig3 18:9617bd66bdae 734 *
memig3 18:9617bd66bdae 735 **************************************************************************************************************
memig3 18:9617bd66bdae 736 */
memig3 18:9617bd66bdae 737
memig3 18:9617bd66bdae 738 USB_INT32U ReadBE32U (volatile USB_INT08U *pmem)
memig3 18:9617bd66bdae 739 {
memig3 18:9617bd66bdae 740 USB_INT32U val = *(USB_INT32U*)pmem;
memig3 18:9617bd66bdae 741 #ifdef __BIG_ENDIAN
memig3 18:9617bd66bdae 742 return val;
memig3 18:9617bd66bdae 743 #else
memig3 18:9617bd66bdae 744 return __REV(val);
memig3 18:9617bd66bdae 745 #endif
memig3 18:9617bd66bdae 746 }
memig3 18:9617bd66bdae 747
memig3 18:9617bd66bdae 748 /*
memig3 18:9617bd66bdae 749 **************************************************************************************************************
memig3 18:9617bd66bdae 750 * WRITE BE 32U
memig3 18:9617bd66bdae 751 *
memig3 18:9617bd66bdae 752 * Description: This function is used to write an unsigned integer into a charecter buffer in the platform
memig3 18:9617bd66bdae 753 * containing big endian processor
memig3 18:9617bd66bdae 754 *
memig3 18:9617bd66bdae 755 * Arguments : pmem Pointer to the charecter buffer
memig3 18:9617bd66bdae 756 * val Value to be placed in the charecter buffer
memig3 18:9617bd66bdae 757 *
memig3 18:9617bd66bdae 758 * Returns : None
memig3 18:9617bd66bdae 759 *
memig3 18:9617bd66bdae 760 **************************************************************************************************************
memig3 18:9617bd66bdae 761 */
memig3 18:9617bd66bdae 762
memig3 18:9617bd66bdae 763 void WriteBE32U (volatile USB_INT08U *pmem,
memig3 18:9617bd66bdae 764 USB_INT32U val)
memig3 18:9617bd66bdae 765 {
memig3 18:9617bd66bdae 766 #ifdef __BIG_ENDIAN
memig3 18:9617bd66bdae 767 *(USB_INT32U*)pmem = val;
memig3 18:9617bd66bdae 768 #else
memig3 18:9617bd66bdae 769 *(USB_INT32U*)pmem = __REV(val);
memig3 18:9617bd66bdae 770 #endif
memig3 18:9617bd66bdae 771 }
memig3 18:9617bd66bdae 772
memig3 18:9617bd66bdae 773 /*
memig3 18:9617bd66bdae 774 **************************************************************************************************************
memig3 18:9617bd66bdae 775 * READ BE 16U
memig3 18:9617bd66bdae 776 *
memig3 18:9617bd66bdae 777 * Description: This function is used to read an unsigned short integer from a charecter buffer in the platform
memig3 18:9617bd66bdae 778 * containing big endian processor
memig3 18:9617bd66bdae 779 *
memig3 18:9617bd66bdae 780 * Arguments : pmem Pointer to the charecter buffer
memig3 18:9617bd66bdae 781 *
memig3 18:9617bd66bdae 782 * Returns : val Unsigned short integer
memig3 18:9617bd66bdae 783 *
memig3 18:9617bd66bdae 784 **************************************************************************************************************
memig3 18:9617bd66bdae 785 */
memig3 18:9617bd66bdae 786
memig3 18:9617bd66bdae 787 USB_INT16U ReadBE16U (volatile USB_INT08U *pmem)
memig3 18:9617bd66bdae 788 {
memig3 18:9617bd66bdae 789 USB_INT16U val = *(USB_INT16U*)pmem;
memig3 18:9617bd66bdae 790 #ifdef __BIG_ENDIAN
memig3 18:9617bd66bdae 791 return val;
memig3 18:9617bd66bdae 792 #else
memig3 18:9617bd66bdae 793 return __REV16(val);
memig3 18:9617bd66bdae 794 #endif
memig3 18:9617bd66bdae 795 }
memig3 18:9617bd66bdae 796
memig3 18:9617bd66bdae 797 /*
memig3 18:9617bd66bdae 798 **************************************************************************************************************
memig3 18:9617bd66bdae 799 * WRITE BE 16U
memig3 18:9617bd66bdae 800 *
memig3 18:9617bd66bdae 801 * Description: This function is used to write an unsigned short integer into the charecter buffer in the
memig3 18:9617bd66bdae 802 * platform containing big endian processor
memig3 18:9617bd66bdae 803 *
memig3 18:9617bd66bdae 804 * Arguments : pmem Pointer to the charecter buffer
memig3 18:9617bd66bdae 805 * val Value to be placed in the charecter buffer
memig3 18:9617bd66bdae 806 *
memig3 18:9617bd66bdae 807 * Returns : None
memig3 18:9617bd66bdae 808 *
memig3 18:9617bd66bdae 809 **************************************************************************************************************
memig3 18:9617bd66bdae 810 */
memig3 18:9617bd66bdae 811
memig3 18:9617bd66bdae 812 void WriteBE16U (volatile USB_INT08U *pmem,
memig3 18:9617bd66bdae 813 USB_INT16U val)
memig3 18:9617bd66bdae 814 {
memig3 18:9617bd66bdae 815 #ifdef __BIG_ENDIAN
memig3 18:9617bd66bdae 816 *(USB_INT16U*)pmem = val;
memig3 18:9617bd66bdae 817 #else
memig3 18:9617bd66bdae 818 *(USB_INT16U*)pmem = (__REV16(val) & 0xFFFF);
memig3 18:9617bd66bdae 819 #endif
memig3 18:9617bd66bdae 820 }