Due Ingegneri Ed Un Controllore
Dependencies: X_NUCLEO_COMMON
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X_NUCLEO_IKS01A1-f2df
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Ant Robinson
X_NUCLEO_IKS01A1-f255a2c75ecb/Components/lsm6ds3/lsm6ds3.h@0:5a49275457c6, 2016-05-17 (annotated)
- Committer:
- antseggs
- Date:
- Tue May 17 15:40:45 2016 +0000
- Revision:
- 0:5a49275457c6
Watchdog in place
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| antseggs | 0:5a49275457c6 | 1 | /** |
| antseggs | 0:5a49275457c6 | 2 | ****************************************************************************** |
| antseggs | 0:5a49275457c6 | 3 | * @file lsm6ds3.h |
| antseggs | 0:5a49275457c6 | 4 | * @author MEMS Application Team |
| antseggs | 0:5a49275457c6 | 5 | * @version V1.2.0 |
| antseggs | 0:5a49275457c6 | 6 | * @date 28-May-2015 |
| antseggs | 0:5a49275457c6 | 7 | * @brief This file contains definitions for the lsm6ds3.c firmware driver |
| antseggs | 0:5a49275457c6 | 8 | ****************************************************************************** |
| antseggs | 0:5a49275457c6 | 9 | * @attention |
| antseggs | 0:5a49275457c6 | 10 | * |
| antseggs | 0:5a49275457c6 | 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| antseggs | 0:5a49275457c6 | 12 | * |
| antseggs | 0:5a49275457c6 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| antseggs | 0:5a49275457c6 | 14 | * are permitted provided that the following conditions are met: |
| antseggs | 0:5a49275457c6 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| antseggs | 0:5a49275457c6 | 16 | * this list of conditions and the following disclaimer. |
| antseggs | 0:5a49275457c6 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| antseggs | 0:5a49275457c6 | 18 | * this list of conditions and the following disclaimer in the documentation |
| antseggs | 0:5a49275457c6 | 19 | * and/or other materials provided with the distribution. |
| antseggs | 0:5a49275457c6 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| antseggs | 0:5a49275457c6 | 21 | * may be used to endorse or promote products derived from this software |
| antseggs | 0:5a49275457c6 | 22 | * without specific prior written permission. |
| antseggs | 0:5a49275457c6 | 23 | * |
| antseggs | 0:5a49275457c6 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| antseggs | 0:5a49275457c6 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| antseggs | 0:5a49275457c6 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| antseggs | 0:5a49275457c6 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| antseggs | 0:5a49275457c6 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| antseggs | 0:5a49275457c6 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| antseggs | 0:5a49275457c6 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| antseggs | 0:5a49275457c6 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| antseggs | 0:5a49275457c6 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| antseggs | 0:5a49275457c6 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| antseggs | 0:5a49275457c6 | 34 | * |
| antseggs | 0:5a49275457c6 | 35 | ****************************************************************************** |
| antseggs | 0:5a49275457c6 | 36 | */ |
| antseggs | 0:5a49275457c6 | 37 | |
| antseggs | 0:5a49275457c6 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| antseggs | 0:5a49275457c6 | 39 | #ifndef __LSM6DS3_H |
| antseggs | 0:5a49275457c6 | 40 | #define __LSM6DS3_H |
| antseggs | 0:5a49275457c6 | 41 | |
| antseggs | 0:5a49275457c6 | 42 | #ifdef __cplusplus |
| antseggs | 0:5a49275457c6 | 43 | extern "C" { |
| antseggs | 0:5a49275457c6 | 44 | #endif |
| antseggs | 0:5a49275457c6 | 45 | |
| antseggs | 0:5a49275457c6 | 46 | /* Includes ------------------------------------------------------------------*/ |
| antseggs | 0:5a49275457c6 | 47 | #include "imu_6axes.h" |
| antseggs | 0:5a49275457c6 | 48 | |
| antseggs | 0:5a49275457c6 | 49 | /** @addtogroup BSP |
| antseggs | 0:5a49275457c6 | 50 | * @{ |
| antseggs | 0:5a49275457c6 | 51 | */ |
| antseggs | 0:5a49275457c6 | 52 | |
| antseggs | 0:5a49275457c6 | 53 | /** @addtogroup Components |
| antseggs | 0:5a49275457c6 | 54 | * @{ |
| antseggs | 0:5a49275457c6 | 55 | */ |
| antseggs | 0:5a49275457c6 | 56 | |
| antseggs | 0:5a49275457c6 | 57 | /** @addtogroup LSM6DS3 |
| antseggs | 0:5a49275457c6 | 58 | * @{ |
| antseggs | 0:5a49275457c6 | 59 | */ |
| antseggs | 0:5a49275457c6 | 60 | |
| antseggs | 0:5a49275457c6 | 61 | /** @addtogroup LSM6DS3_Exported_Defines LSM6DS3_Exported_Defines |
| antseggs | 0:5a49275457c6 | 62 | * @{ |
| antseggs | 0:5a49275457c6 | 63 | */ |
| antseggs | 0:5a49275457c6 | 64 | #ifndef NULL |
| antseggs | 0:5a49275457c6 | 65 | #define NULL (void *) 0 |
| antseggs | 0:5a49275457c6 | 66 | #endif |
| antseggs | 0:5a49275457c6 | 67 | |
| antseggs | 0:5a49275457c6 | 68 | /******************************************************************************/ |
| antseggs | 0:5a49275457c6 | 69 | /*********** START ACCELEROMETER AND GYROSCOPE REGISTER MAPPING **************/ |
| antseggs | 0:5a49275457c6 | 70 | /******************************************************************************/ |
| antseggs | 0:5a49275457c6 | 71 | |
| antseggs | 0:5a49275457c6 | 72 | |
| antseggs | 0:5a49275457c6 | 73 | /***************************************** COMMON REGISTERS ********************************************/ |
| antseggs | 0:5a49275457c6 | 74 | |
| antseggs | 0:5a49275457c6 | 75 | /** |
| antseggs | 0:5a49275457c6 | 76 | * @brief FIFO control register |
| antseggs | 0:5a49275457c6 | 77 | * \code |
| antseggs | 0:5a49275457c6 | 78 | * Read/write |
| antseggs | 0:5a49275457c6 | 79 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 80 | * [7] FUNC_CFG_EN: Enable access to the embedded functions configuration registers (1) from address 02h to 32h. Default value: 0. |
| antseggs | 0:5a49275457c6 | 81 | * [6:0] This bit must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 82 | * \endcode |
| antseggs | 0:5a49275457c6 | 83 | */ |
| antseggs | 0:5a49275457c6 | 84 | #define LSM6DS3_XG_FUNC_CFG_ACCESS 0x01 |
| antseggs | 0:5a49275457c6 | 85 | |
| antseggs | 0:5a49275457c6 | 86 | /** |
| antseggs | 0:5a49275457c6 | 87 | * @brief FIFO control register |
| antseggs | 0:5a49275457c6 | 88 | * \code |
| antseggs | 0:5a49275457c6 | 89 | * Read/write |
| antseggs | 0:5a49275457c6 | 90 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 91 | * [7:0] TPH_[7:0]: Sensor SyncronizationTime Frame with the step of 500ms and full range of 5s. Default: 0000 0000 |
| antseggs | 0:5a49275457c6 | 92 | * \endcode |
| antseggs | 0:5a49275457c6 | 93 | */ |
| antseggs | 0:5a49275457c6 | 94 | #define LSM6DS3_XG_SENSOR_SYNC_TIME_FRAME 0x04 |
| antseggs | 0:5a49275457c6 | 95 | |
| antseggs | 0:5a49275457c6 | 96 | /** |
| antseggs | 0:5a49275457c6 | 97 | * @brief FIFO control register |
| antseggs | 0:5a49275457c6 | 98 | * \code |
| antseggs | 0:5a49275457c6 | 99 | * Read/write |
| antseggs | 0:5a49275457c6 | 100 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 101 | * [7:2] This bit must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 102 | * [1] HP_RST: Gyro digital HP filter reset. Default: 0 |
| antseggs | 0:5a49275457c6 | 103 | * [1] SENSOR_SYNC_ENHP_RST: Enable sensor synchronization feature. Default 0 |
| antseggs | 0:5a49275457c6 | 104 | * \endcode |
| antseggs | 0:5a49275457c6 | 105 | */ |
| antseggs | 0:5a49275457c6 | 106 | #define LSM6DS3_XG_SENSOR_SYNC_ENABLE 0x05 |
| antseggs | 0:5a49275457c6 | 107 | |
| antseggs | 0:5a49275457c6 | 108 | |
| antseggs | 0:5a49275457c6 | 109 | /** |
| antseggs | 0:5a49275457c6 | 110 | * @brief FIFO control register |
| antseggs | 0:5a49275457c6 | 111 | * \code |
| antseggs | 0:5a49275457c6 | 112 | * Read/write |
| antseggs | 0:5a49275457c6 | 113 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 114 | * [7:0] FTH_7-0 FIFO threshold level setting - watermark flag is toggled when the number of bytes written to FIFO is greater or equal to threshold level. |
| antseggs | 0:5a49275457c6 | 115 | * \endcode |
| antseggs | 0:5a49275457c6 | 116 | */ |
| antseggs | 0:5a49275457c6 | 117 | #define LSM6DS3_XG_FIFO_CTRL1 0x06 |
| antseggs | 0:5a49275457c6 | 118 | |
| antseggs | 0:5a49275457c6 | 119 | /** |
| antseggs | 0:5a49275457c6 | 120 | * @brief FIFO control register |
| antseggs | 0:5a49275457c6 | 121 | * \code |
| antseggs | 0:5a49275457c6 | 122 | * Read/write |
| antseggs | 0:5a49275457c6 | 123 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 124 | * [7] TIMER_PEDO_FIFO_EN: Enable Pedometer step counter and time stamp as 4th sensor FIFO data. Default: 0 disabled |
| antseggs | 0:5a49275457c6 | 125 | * [6] TIMER_PEDO_FIFO_DRDY : Pedometer FIFO write mode. Default: 0 disabled |
| antseggs | 0:5a49275457c6 | 126 | * [5:4] This bit must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 127 | * [3:0] FTH_[11:8] FIFO threshold level setting(1). Default value: 0000 |
| antseggs | 0:5a49275457c6 | 128 | * \endcode |
| antseggs | 0:5a49275457c6 | 129 | */ |
| antseggs | 0:5a49275457c6 | 130 | #define LSM6DS3_XG_FIFO_CTRL2 0x07 |
| antseggs | 0:5a49275457c6 | 131 | |
| antseggs | 0:5a49275457c6 | 132 | /** |
| antseggs | 0:5a49275457c6 | 133 | * @brief FIFO control register |
| antseggs | 0:5a49275457c6 | 134 | * \code |
| antseggs | 0:5a49275457c6 | 135 | * Read/write |
| antseggs | 0:5a49275457c6 | 136 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 137 | * [7:6] This bit must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 138 | * [5:3] DEC_FIFO_GYRO[2:0]: Gyro FIFO decimation setting. Default value: 000 |
| antseggs | 0:5a49275457c6 | 139 | * [2:0] DEC_FIFO_XL[2:0]: XL FIFO decimation setting. Default value: 000 |
| antseggs | 0:5a49275457c6 | 140 | * \endcode |
| antseggs | 0:5a49275457c6 | 141 | */ |
| antseggs | 0:5a49275457c6 | 142 | #define LSM6DS3_XG_FIFO_CTRL3 0x08 |
| antseggs | 0:5a49275457c6 | 143 | |
| antseggs | 0:5a49275457c6 | 144 | /** |
| antseggs | 0:5a49275457c6 | 145 | * @brief FIFO control register |
| antseggs | 0:5a49275457c6 | 146 | * \code |
| antseggs | 0:5a49275457c6 | 147 | * Read/write |
| antseggs | 0:5a49275457c6 | 148 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 149 | * [7] This bit must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 150 | * [6] ONLY_HIGH_DATA :8 bit data storing in FIFO. Default: 0 |
| antseggs | 0:5a49275457c6 | 151 | * [5:3] DEC_SLV1_FIFO[2:0] Second external sensor FIFO decimation setting. Default: 000 |
| antseggs | 0:5a49275457c6 | 152 | * [2:0] DEC_SLV1_FIFO[2:0] First external sensor FIFO decimation setting. Default: 000 |
| antseggs | 0:5a49275457c6 | 153 | * \endcode |
| antseggs | 0:5a49275457c6 | 154 | */ |
| antseggs | 0:5a49275457c6 | 155 | #define LSM6DS3_XG_FIFO_CTRL4 0x09 |
| antseggs | 0:5a49275457c6 | 156 | |
| antseggs | 0:5a49275457c6 | 157 | |
| antseggs | 0:5a49275457c6 | 158 | /** |
| antseggs | 0:5a49275457c6 | 159 | * @brief FIFO control register |
| antseggs | 0:5a49275457c6 | 160 | * \code |
| antseggs | 0:5a49275457c6 | 161 | * Read/write |
| antseggs | 0:5a49275457c6 | 162 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 163 | * [7] This bit must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 164 | * [6:3] ODR_FIFO_[3:0]: FIFO ODR selection. Default: 0000 |
| antseggs | 0:5a49275457c6 | 165 | * [2:0] FIFO_MODE_[2:0] : FIFO mode selection bits. Default value: 000 |
| antseggs | 0:5a49275457c6 | 166 | * \endcode |
| antseggs | 0:5a49275457c6 | 167 | */ |
| antseggs | 0:5a49275457c6 | 168 | #define LSM6DS3_XG_FIFO_CTRL5 0x0A |
| antseggs | 0:5a49275457c6 | 169 | |
| antseggs | 0:5a49275457c6 | 170 | |
| antseggs | 0:5a49275457c6 | 171 | /** |
| antseggs | 0:5a49275457c6 | 172 | * @brief Angular rate sensor sign and orientation register |
| antseggs | 0:5a49275457c6 | 173 | * \code |
| antseggs | 0:5a49275457c6 | 174 | * Read/write |
| antseggs | 0:5a49275457c6 | 175 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 176 | * [7:6] This bit must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 177 | * [5] SignX_G: Pitch axis (X) Angular rate sign. Default value: 0 |
| antseggs | 0:5a49275457c6 | 178 | * [5] SignY_G: Roll axis (Y) Angular rate sign. Default value: 0 |
| antseggs | 0:5a49275457c6 | 179 | * [5] SignZ_G: Pitch axis (Z) Angular rate sign. Default value: 0 |
| antseggs | 0:5a49275457c6 | 180 | * [2:0] Orient[2:0] : Directional user orientation selection. Default Value: 000 |
| antseggs | 0:5a49275457c6 | 181 | * \endcode |
| antseggs | 0:5a49275457c6 | 182 | */ |
| antseggs | 0:5a49275457c6 | 183 | #define LSM6DS3_XG_ORIENT_CFG_G 0x0B |
| antseggs | 0:5a49275457c6 | 184 | |
| antseggs | 0:5a49275457c6 | 185 | /** |
| antseggs | 0:5a49275457c6 | 186 | * @brief INT1 pad control registrer |
| antseggs | 0:5a49275457c6 | 187 | * \code |
| antseggs | 0:5a49275457c6 | 188 | * Read/write |
| antseggs | 0:5a49275457c6 | 189 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 190 | * [7] INT1_PEDO: Pedometer step recognition interrupt enable on INT1 pad. Default value: 0 |
| antseggs | 0:5a49275457c6 | 191 | * [6] INT1_SIGN_MOT: Significant motion interrupt enable on INT1 pad. Default value: 0 |
| antseggs | 0:5a49275457c6 | 192 | * [5] INT1_FULL_FLAG: Full flag Interrupt Enable on INT1 pad. Default value: 0 |
| antseggs | 0:5a49275457c6 | 193 | * [4] INT1_OVR: Overrun Interrupt on INT1 pad. Default value: 0 |
| antseggs | 0:5a49275457c6 | 194 | * [3] INT1_FTH: FIFO threshold interrupt on INT1 pad. Default value: 0 |
| antseggs | 0:5a49275457c6 | 195 | * [2] INT1_BOOT: Overrun Interrupt on INT1 pad. Default value: 0 |
| antseggs | 0:5a49275457c6 | 196 | * [1] INT1_DRDY_G: Gyroscope Data Ready on INT1 pad. Default value: 0. |
| antseggs | 0:5a49275457c6 | 197 | * [0] INT1_DRDY_XL: Accelerometer Data Ready on INT1 pad. Default value: 0 |
| antseggs | 0:5a49275457c6 | 198 | * \endcode |
| antseggs | 0:5a49275457c6 | 199 | */ |
| antseggs | 0:5a49275457c6 | 200 | #define LSM6DS3_XG_INT1_CTRL 0x0D |
| antseggs | 0:5a49275457c6 | 201 | |
| antseggs | 0:5a49275457c6 | 202 | |
| antseggs | 0:5a49275457c6 | 203 | //new, done |
| antseggs | 0:5a49275457c6 | 204 | /** |
| antseggs | 0:5a49275457c6 | 205 | * @brief INT2 pad control registrer |
| antseggs | 0:5a49275457c6 | 206 | * \code |
| antseggs | 0:5a49275457c6 | 207 | * Read/write |
| antseggs | 0:5a49275457c6 | 208 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 209 | * [7] INT2_PEDO: Pedometer step recognition interrupt enable on INT1 pad. Default value: 0 |
| antseggs | 0:5a49275457c6 | 210 | * [6] INT2_SIGN_MOT: Significant motion interrupt enable on INT1 pad. Default value: 0 |
| antseggs | 0:5a49275457c6 | 211 | * [5] INT2_FULL_FLAG: Full flag Interrupt Enable on INT1 pad. Default value: 0 |
| antseggs | 0:5a49275457c6 | 212 | * [4] INT2_OVR: Overrun Interrupt on INT1 pad. Default value: 0 |
| antseggs | 0:5a49275457c6 | 213 | * [3] INT2_FTH: FIFO threshold interrupt on INT1 pad. Default value: 0 |
| antseggs | 0:5a49275457c6 | 214 | * [2] INT2_BOOT: Overrun Interrupt on INT1 pad. Default value: 0 |
| antseggs | 0:5a49275457c6 | 215 | * [1] INT2_DRDY_G: Gyroscope Data Ready on INT1 pad. Default value: 0. |
| antseggs | 0:5a49275457c6 | 216 | * [0] INT2_DRDY_XL: Accelerometer Data Ready on INT1 pad. Default value: 0 |
| antseggs | 0:5a49275457c6 | 217 | * \endcode |
| antseggs | 0:5a49275457c6 | 218 | */ |
| antseggs | 0:5a49275457c6 | 219 | #define LSM6DS3_XG_INT2_CTRL 0x0E |
| antseggs | 0:5a49275457c6 | 220 | |
| antseggs | 0:5a49275457c6 | 221 | |
| antseggs | 0:5a49275457c6 | 222 | /** |
| antseggs | 0:5a49275457c6 | 223 | * @brief Device identifier register. |
| antseggs | 0:5a49275457c6 | 224 | * \code |
| antseggs | 0:5a49275457c6 | 225 | * Read |
| antseggs | 0:5a49275457c6 | 226 | * Default value:69 |
| antseggs | 0:5a49275457c6 | 227 | * [7:0] This read-only register contains the device identifier |
| antseggs | 0:5a49275457c6 | 228 | * \endcode |
| antseggs | 0:5a49275457c6 | 229 | */ |
| antseggs | 0:5a49275457c6 | 230 | #define LSM6DS3_XG_WHO_AM_I_ADDR 0x0F |
| antseggs | 0:5a49275457c6 | 231 | |
| antseggs | 0:5a49275457c6 | 232 | |
| antseggs | 0:5a49275457c6 | 233 | /** |
| antseggs | 0:5a49275457c6 | 234 | * @brief Control Register 3 |
| antseggs | 0:5a49275457c6 | 235 | * \code |
| antseggs | 0:5a49275457c6 | 236 | * Read/write |
| antseggs | 0:5a49275457c6 | 237 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 238 | * [7] BOOT: Reboot memory content. Default value: 0 |
| antseggs | 0:5a49275457c6 | 239 | * [6] BDU: Block Data Update. Default value: 0 |
| antseggs | 0:5a49275457c6 | 240 | * [5] H_LACTIVE: Interrupt activation level. Default value: 0 |
| antseggs | 0:5a49275457c6 | 241 | * [4] PP_OD: Push-pull/Open Drain selection on INT pad. Default value: 0 |
| antseggs | 0:5a49275457c6 | 242 | * [3] SIM: SPI Serial Interface Mode selection. Default value: 0 |
| antseggs | 0:5a49275457c6 | 243 | * [2] IF_INC: Register address automatically incremented during a multiple byte access with a serial interface (I2C or SPI). Default value: 0 |
| antseggs | 0:5a49275457c6 | 244 | * [1] BLE: Big/Little Endian Data Selection. Default value: 0 |
| antseggs | 0:5a49275457c6 | 245 | * [0] SW_RESET: Software Reset. Default value: 0 |
| antseggs | 0:5a49275457c6 | 246 | * \endcode |
| antseggs | 0:5a49275457c6 | 247 | */ |
| antseggs | 0:5a49275457c6 | 248 | #define LSM6DS3_XG_CTRL3_C 0x12 |
| antseggs | 0:5a49275457c6 | 249 | |
| antseggs | 0:5a49275457c6 | 250 | /** |
| antseggs | 0:5a49275457c6 | 251 | * @brief Control Register 4 |
| antseggs | 0:5a49275457c6 | 252 | * \code |
| antseggs | 0:5a49275457c6 | 253 | * Read/write |
| antseggs | 0:5a49275457c6 | 254 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 255 | * [7] BW_SCAL_ODR: Accelerometer bandwidth selection. Default value: 0 |
| antseggs | 0:5a49275457c6 | 256 | * [6] SLEEP_G: Gyroscope sleep mode enable. Default value: 0 |
| antseggs | 0:5a49275457c6 | 257 | * [5] INT2_on_INT1: All interrupt signals available on INT1 pad enable. Default value: 0 |
| antseggs | 0:5a49275457c6 | 258 | * [4] This bit must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 259 | * [3] DRDY_MASK: Configuration 1(3) Data Available Enable bit. Default Value: 0 |
| antseggs | 0:5a49275457c6 | 260 | * [2] I2C_disable Disable I2C interface. Default value: 0 |
| antseggs | 0:5a49275457c6 | 261 | * [1] MODE3_EN Enable auxiliary SPI interface (Mode3, refer to Table 1.). Default value: 0 |
| antseggs | 0:5a49275457c6 | 262 | * [0] STOP_ON_FTH Enable FIFO threshold level use. Default value: 0. |
| antseggs | 0:5a49275457c6 | 263 | |
| antseggs | 0:5a49275457c6 | 264 | * \endcode |
| antseggs | 0:5a49275457c6 | 265 | */ |
| antseggs | 0:5a49275457c6 | 266 | #define LSM6DS3_XG_CTRL4_C 0x13 |
| antseggs | 0:5a49275457c6 | 267 | |
| antseggs | 0:5a49275457c6 | 268 | /** |
| antseggs | 0:5a49275457c6 | 269 | * @brief Control Register 4 |
| antseggs | 0:5a49275457c6 | 270 | * \code |
| antseggs | 0:5a49275457c6 | 271 | * Read/write |
| antseggs | 0:5a49275457c6 | 272 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 273 | * [7:4] This bit must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 274 | * [3:2] ST_G[1:0]: Angular rate sensor Self Test Enable. Default value: 00 |
| antseggs | 0:5a49275457c6 | 275 | * [1:0] ST_XL[1:0]: Linear acceleration sensor Self Test Enable. Default value: 00 |
| antseggs | 0:5a49275457c6 | 276 | * \endcode |
| antseggs | 0:5a49275457c6 | 277 | */ |
| antseggs | 0:5a49275457c6 | 278 | #define LSM6DS3_XG_CTRL5_C 0x14 |
| antseggs | 0:5a49275457c6 | 279 | |
| antseggs | 0:5a49275457c6 | 280 | |
| antseggs | 0:5a49275457c6 | 281 | /** |
| antseggs | 0:5a49275457c6 | 282 | * @brief Control Register 10 |
| antseggs | 0:5a49275457c6 | 283 | * \code |
| antseggs | 0:5a49275457c6 | 284 | * Read/write |
| antseggs | 0:5a49275457c6 | 285 | * Default value: 0x38 |
| antseggs | 0:5a49275457c6 | 286 | * [7:6] These bits must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 287 | * [5] Zen_G: Gyroscope�s Z-axis output enable. Default value: 1 |
| antseggs | 0:5a49275457c6 | 288 | * [4] Yen_G: Gyroscope�s Y-axis output enable. Default value: 1 |
| antseggs | 0:5a49275457c6 | 289 | * [3] Xen_G: Gyroscope�s X-axis output enable. Default value: 1 |
| antseggs | 0:5a49275457c6 | 290 | * [2] FUNC_EN: Enable embedded functionalities (pedometer, tilt and significant motion) . Default value: 0 |
| antseggs | 0:5a49275457c6 | 291 | * [1] PEDO_RST_STEP: Reset pedometer step counter . Default value: 0 |
| antseggs | 0:5a49275457c6 | 292 | * [0] SIGN_MOTION_EN: Enable significant motion function. For a correct functionality of significant motion function, TILT_EN bit in FUNC_SRC (53h) register must be set to 1 . Default value: 1 |
| antseggs | 0:5a49275457c6 | 293 | * \endcode |
| antseggs | 0:5a49275457c6 | 294 | */ |
| antseggs | 0:5a49275457c6 | 295 | #define LSM6DS3_XG_CTRL10_C 0x19 |
| antseggs | 0:5a49275457c6 | 296 | |
| antseggs | 0:5a49275457c6 | 297 | |
| antseggs | 0:5a49275457c6 | 298 | /** |
| antseggs | 0:5a49275457c6 | 299 | * @brief Sensor hub Master config Register |
| antseggs | 0:5a49275457c6 | 300 | * \code |
| antseggs | 0:5a49275457c6 | 301 | * Read/write |
| antseggs | 0:5a49275457c6 | 302 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 303 | * [7] DRDY_ON_INT1:Manage the DRDY signal on INT1 pad. Default: 0 |
| antseggs | 0:5a49275457c6 | 304 | * [6] DATA_VALID_SEL_FIFO: Selection of FIFO data-valid signal. Default value: 0 |
| antseggs | 0:5a49275457c6 | 305 | * [5] This bit must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 306 | * [4] START_CONFIG: Sensor Hub trigger signal selection. Default value: 0 |
| antseggs | 0:5a49275457c6 | 307 | * [3] PULL_UP_EN: Auxiliary I2C pull-up. Default value: 0 |
| antseggs | 0:5a49275457c6 | 308 | * [2] PASS_THROUGH_MODE: I2C interface pass-through. Default value: 0 |
| antseggs | 0:5a49275457c6 | 309 | * [1] IRON_EN:Enable soft iron correction algorithm for magnetometer. Default value: 0. |
| antseggs | 0:5a49275457c6 | 310 | * [0] MASTER_ON: Sensor Hub I2C master enable. Default: 0 |
| antseggs | 0:5a49275457c6 | 311 | * \endcode |
| antseggs | 0:5a49275457c6 | 312 | */ |
| antseggs | 0:5a49275457c6 | 313 | #define LSM6DS3_XG_MASTER_CONFIG 0x1A |
| antseggs | 0:5a49275457c6 | 314 | |
| antseggs | 0:5a49275457c6 | 315 | |
| antseggs | 0:5a49275457c6 | 316 | /** |
| antseggs | 0:5a49275457c6 | 317 | * @brief Wake up interrupt source register |
| antseggs | 0:5a49275457c6 | 318 | * \code |
| antseggs | 0:5a49275457c6 | 319 | * Read |
| antseggs | 0:5a49275457c6 | 320 | * Default value: output |
| antseggs | 0:5a49275457c6 | 321 | * [7:6] This bit must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 322 | * [5] FF_IA: Free fall event detection status. Default: 0 |
| antseggs | 0:5a49275457c6 | 323 | * [4] SLEEP_STATE_IA: Sleep event status. Default value: 0 |
| antseggs | 0:5a49275457c6 | 324 | * [3] WU_IA: Wake up event detection status. Default |
| antseggs | 0:5a49275457c6 | 325 | * [2] X_WU: detection status on X axis. Default value: 0 |
| antseggs | 0:5a49275457c6 | 326 | * [1] Y_WU: detection status on Y axis. Default value: 0 |
| antseggs | 0:5a49275457c6 | 327 | * [0] Z_WU: detection status on Z axis. Default value: 0 |
| antseggs | 0:5a49275457c6 | 328 | * \endcode |
| antseggs | 0:5a49275457c6 | 329 | */ |
| antseggs | 0:5a49275457c6 | 330 | #define LSM6DS3_XG_WAKE_UP_SRC 0x1B |
| antseggs | 0:5a49275457c6 | 331 | |
| antseggs | 0:5a49275457c6 | 332 | /** |
| antseggs | 0:5a49275457c6 | 333 | * @brief Tap source register |
| antseggs | 0:5a49275457c6 | 334 | * \code |
| antseggs | 0:5a49275457c6 | 335 | * Read |
| antseggs | 0:5a49275457c6 | 336 | * Default value: output |
| antseggs | 0:5a49275457c6 | 337 | * [7] This bit must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 338 | * [6] TAP_IA: Tap event detection status. Default: 0 |
| antseggs | 0:5a49275457c6 | 339 | * [5] SINGLE_TAP: Single tap event status. Default value: 0 |
| antseggs | 0:5a49275457c6 | 340 | * [4] DOUBLE_TAP: Double tap event detection status. Default value: 0 |
| antseggs | 0:5a49275457c6 | 341 | * [3] TAP_SIGN: Sign of acceleration detected by tap event. Default: 0 |
| antseggs | 0:5a49275457c6 | 342 | * [2] X_TAP: Tap event detection status on X axis. Default value: 0 |
| antseggs | 0:5a49275457c6 | 343 | * [1] Y_TAP: Tap event detection status on Y axis. Default value: 0 |
| antseggs | 0:5a49275457c6 | 344 | * [0] Z_TAP: Tap event detection status on Z axis. Default value: 0 |
| antseggs | 0:5a49275457c6 | 345 | * \endcode |
| antseggs | 0:5a49275457c6 | 346 | */ |
| antseggs | 0:5a49275457c6 | 347 | #define LSM6DS3_XG_TAP_SRC 0x1C |
| antseggs | 0:5a49275457c6 | 348 | |
| antseggs | 0:5a49275457c6 | 349 | /** |
| antseggs | 0:5a49275457c6 | 350 | * @brief Portrait, landscape face-up and face-down source register |
| antseggs | 0:5a49275457c6 | 351 | * \code |
| antseggs | 0:5a49275457c6 | 352 | * Read |
| antseggs | 0:5a49275457c6 | 353 | * Default value: output |
| antseggs | 0:5a49275457c6 | 354 | * [7] This bit must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 355 | * [6] D6D_IA: Interrupt active for change position portrait, landscape, face-up, face-down. Default value: 0 |
| antseggs | 0:5a49275457c6 | 356 | * [5] ZH: Z-axis high event (over-threshold). Default value: 0 |
| antseggs | 0:5a49275457c6 | 357 | * [4] ZL: Z-axis low event (under-threshold). Default value: 0 |
| antseggs | 0:5a49275457c6 | 358 | * [5] YH: Y-axis high event (over-threshold). Default value: 0 |
| antseggs | 0:5a49275457c6 | 359 | * [4] YL: Y-axis low event (under-threshold). Default value: 0 |
| antseggs | 0:5a49275457c6 | 360 | * [5] X_H: X-axis high event (over-threshold). Default value: 0 |
| antseggs | 0:5a49275457c6 | 361 | * [4] X_L: X-axis low event (under-threshold). Default value: 0 |
| antseggs | 0:5a49275457c6 | 362 | * \endcode |
| antseggs | 0:5a49275457c6 | 363 | */ |
| antseggs | 0:5a49275457c6 | 364 | #define LSM6DS3_XG_D6D_SRC 0x1D |
| antseggs | 0:5a49275457c6 | 365 | |
| antseggs | 0:5a49275457c6 | 366 | /** |
| antseggs | 0:5a49275457c6 | 367 | * @brief Status register |
| antseggs | 0:5a49275457c6 | 368 | * \code |
| antseggs | 0:5a49275457c6 | 369 | * Read |
| antseggs | 0:5a49275457c6 | 370 | * Default value: output |
| antseggs | 0:5a49275457c6 | 371 | * [7:4] No meaning set |
| antseggs | 0:5a49275457c6 | 372 | * [3] EV_BOOT: Boot running flag signal. Default value: 0 |
| antseggs | 0:5a49275457c6 | 373 | * [2] No meaning set |
| antseggs | 0:5a49275457c6 | 374 | * [1] GDA: Gyroscope new data avaialble. Default value: 0 |
| antseggs | 0:5a49275457c6 | 375 | * [0] XLDA: Accelerometer new data avaialble. Default value: 0 |
| antseggs | 0:5a49275457c6 | 376 | * \endcode |
| antseggs | 0:5a49275457c6 | 377 | */ |
| antseggs | 0:5a49275457c6 | 378 | #define LSM6DS3_XG_STATUS_REG 0x1E |
| antseggs | 0:5a49275457c6 | 379 | |
| antseggs | 0:5a49275457c6 | 380 | /** |
| antseggs | 0:5a49275457c6 | 381 | * @brief FIFO status control register |
| antseggs | 0:5a49275457c6 | 382 | * \code |
| antseggs | 0:5a49275457c6 | 383 | * Read |
| antseggs | 0:5a49275457c6 | 384 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 385 | * [7:0] DIFF_FIFO_[7:0]: Number of unread words (16 bit axes) stored in FIFO . For a complete number of unread samples, consider DIFF_FIFO [11:8] in FIFO_STATUS2 (3Bh) |
| antseggs | 0:5a49275457c6 | 386 | * \endcode |
| antseggs | 0:5a49275457c6 | 387 | */ |
| antseggs | 0:5a49275457c6 | 388 | #define LSM6DS3_XG_FIFO_STATUS1 0x3A |
| antseggs | 0:5a49275457c6 | 389 | |
| antseggs | 0:5a49275457c6 | 390 | /** |
| antseggs | 0:5a49275457c6 | 391 | * @brief FIFO status control register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0. |
| antseggs | 0:5a49275457c6 | 392 | * \code |
| antseggs | 0:5a49275457c6 | 393 | * Read |
| antseggs | 0:5a49275457c6 | 394 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 395 | * [7] FTH FIFO watermark status. Deafult value: 0 |
| antseggs | 0:5a49275457c6 | 396 | * [6] OVER_RUN: FIFO overrun status. Default value: 0 |
| antseggs | 0:5a49275457c6 | 397 | * [5] FIFO_FULL: FIFO full status. Default value: 0 |
| antseggs | 0:5a49275457c6 | 398 | * [5] FIFO_EMPTY: FIFO empty bit. Default value: 0; 0: FIFO contains data; 1: FIFO is empty |
| antseggs | 0:5a49275457c6 | 399 | * [3:0] DIFF_FIFO_[11:8] Number of unread words (16 bit axes) stored in FIFO : For a complete number of unread samples, consider DIFF_FIFO [11:8] in FIFO_STATUS1 (3Ah) |
| antseggs | 0:5a49275457c6 | 400 | * \endcode |
| antseggs | 0:5a49275457c6 | 401 | */ |
| antseggs | 0:5a49275457c6 | 402 | #define LSM6DS3_XG_FIFO_STATUS2 0x3B |
| antseggs | 0:5a49275457c6 | 403 | |
| antseggs | 0:5a49275457c6 | 404 | /** |
| antseggs | 0:5a49275457c6 | 405 | * @brief FIFO status control register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0 |
| antseggs | 0:5a49275457c6 | 406 | * \code |
| antseggs | 0:5a49275457c6 | 407 | * Read |
| antseggs | 0:5a49275457c6 | 408 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 409 | * [7:0] FIFO_PATTERN_[7:0] : Word of recursive pattern read at the next reading |
| antseggs | 0:5a49275457c6 | 410 | * \endcode |
| antseggs | 0:5a49275457c6 | 411 | */ |
| antseggs | 0:5a49275457c6 | 412 | #define LSM6DS3_XG_FIFO_STATUS3 0x3C |
| antseggs | 0:5a49275457c6 | 413 | |
| antseggs | 0:5a49275457c6 | 414 | /** |
| antseggs | 0:5a49275457c6 | 415 | * @brief FIFO status control register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0 |
| antseggs | 0:5a49275457c6 | 416 | * \code |
| antseggs | 0:5a49275457c6 | 417 | * Read |
| antseggs | 0:5a49275457c6 | 418 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 419 | * [1:0] FIFO_PATTERN_[9:8] : Word of recursive pattern read at the next reading |
| antseggs | 0:5a49275457c6 | 420 | * \endcode |
| antseggs | 0:5a49275457c6 | 421 | */ |
| antseggs | 0:5a49275457c6 | 422 | #define LSM6DS3_XG_FIFO_STATUS4 0x3D |
| antseggs | 0:5a49275457c6 | 423 | |
| antseggs | 0:5a49275457c6 | 424 | /** |
| antseggs | 0:5a49275457c6 | 425 | * @brief FIFO status control register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0. |
| antseggs | 0:5a49275457c6 | 426 | * \code |
| antseggs | 0:5a49275457c6 | 427 | * Read |
| antseggs | 0:5a49275457c6 | 428 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 429 | * [4:0] FIFO_PATTERN_[9:8] : Word of recursive pattern read at the next reading |
| antseggs | 0:5a49275457c6 | 430 | * \endcode |
| antseggs | 0:5a49275457c6 | 431 | */ |
| antseggs | 0:5a49275457c6 | 432 | #define LSM6DS3_XG_FIFO_STATUS4 0x3D |
| antseggs | 0:5a49275457c6 | 433 | |
| antseggs | 0:5a49275457c6 | 434 | /** |
| antseggs | 0:5a49275457c6 | 435 | * @brief FIFO data output register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0. |
| antseggs | 0:5a49275457c6 | 436 | * \code |
| antseggs | 0:5a49275457c6 | 437 | * Read |
| antseggs | 0:5a49275457c6 | 438 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 439 | * [7:0] DATA_OUT_FIFO_L_[7:0]: FIFO data output (First byte) |
| antseggs | 0:5a49275457c6 | 440 | * \endcode |
| antseggs | 0:5a49275457c6 | 441 | */ |
| antseggs | 0:5a49275457c6 | 442 | #define LSM6DS3_XG_FIFO_DATA_OUT_L 0x3E |
| antseggs | 0:5a49275457c6 | 443 | |
| antseggs | 0:5a49275457c6 | 444 | /** |
| antseggs | 0:5a49275457c6 | 445 | * @brief FIFO data output register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0. |
| antseggs | 0:5a49275457c6 | 446 | * \code |
| antseggs | 0:5a49275457c6 | 447 | * Read |
| antseggs | 0:5a49275457c6 | 448 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 449 | * [7:0] DATA_OUT_FIFO_H_[7:0]: FIFO data output (second byte) |
| antseggs | 0:5a49275457c6 | 450 | * \endcode |
| antseggs | 0:5a49275457c6 | 451 | */ |
| antseggs | 0:5a49275457c6 | 452 | #define LSM6DS3_XG_FIFO_DATA_OUT_H 0x3F |
| antseggs | 0:5a49275457c6 | 453 | |
| antseggs | 0:5a49275457c6 | 454 | /** |
| antseggs | 0:5a49275457c6 | 455 | * @brief Time stamp first byte data output register (r). The value is expressed as 24 bit and the bit resolution is defined by setting value in WAKE_UP_DUR (5Ch). |
| antseggs | 0:5a49275457c6 | 456 | * \code |
| antseggs | 0:5a49275457c6 | 457 | * Read |
| antseggs | 0:5a49275457c6 | 458 | * Default value: output |
| antseggs | 0:5a49275457c6 | 459 | * [7:0] TIMESTAMP0_[7:0]: FIFO first byte data output |
| antseggs | 0:5a49275457c6 | 460 | * \endcode |
| antseggs | 0:5a49275457c6 | 461 | */ |
| antseggs | 0:5a49275457c6 | 462 | #define LSM6DS3_XG_TIMESTAMP0_REG 0x40 |
| antseggs | 0:5a49275457c6 | 463 | |
| antseggs | 0:5a49275457c6 | 464 | /** |
| antseggs | 0:5a49275457c6 | 465 | * @brief Time stamp second byte data output register (r). The value is expressed as 24 bit and the bit resolution is defined by setting value in WAKE_UP_DUR (5Ch). |
| antseggs | 0:5a49275457c6 | 466 | * \code |
| antseggs | 0:5a49275457c6 | 467 | * Read |
| antseggs | 0:5a49275457c6 | 468 | * Default value: output |
| antseggs | 0:5a49275457c6 | 469 | * [7:0] TIMESTAMP1_[7:0]: FIFO second byte data output |
| antseggs | 0:5a49275457c6 | 470 | * \endcode |
| antseggs | 0:5a49275457c6 | 471 | */ |
| antseggs | 0:5a49275457c6 | 472 | #define LSM6DS3_XG_TIMESTAMP1_REG 0x41 |
| antseggs | 0:5a49275457c6 | 473 | |
| antseggs | 0:5a49275457c6 | 474 | /** |
| antseggs | 0:5a49275457c6 | 475 | * @brief Time stamp third byte data output register (r). The value is expressed as 24 bit and the bit resolution is defined by setting value in WAKE_UP_DUR (5Ch). |
| antseggs | 0:5a49275457c6 | 476 | * \code |
| antseggs | 0:5a49275457c6 | 477 | * Read |
| antseggs | 0:5a49275457c6 | 478 | * Default value: output |
| antseggs | 0:5a49275457c6 | 479 | * [7:0] TIMESTAMP2_[7:0]: FIFO third byte data output |
| antseggs | 0:5a49275457c6 | 480 | * \endcode |
| antseggs | 0:5a49275457c6 | 481 | */ |
| antseggs | 0:5a49275457c6 | 482 | #define LSM6DS3_XG_TIMESTAMP2_REG 0x42 |
| antseggs | 0:5a49275457c6 | 483 | |
| antseggs | 0:5a49275457c6 | 484 | /** |
| antseggs | 0:5a49275457c6 | 485 | * @brief Step counter output register (r). |
| antseggs | 0:5a49275457c6 | 486 | * \code |
| antseggs | 0:5a49275457c6 | 487 | * Read |
| antseggs | 0:5a49275457c6 | 488 | * Default value: output |
| antseggs | 0:5a49275457c6 | 489 | * [7:0] STEP_COUNTER_L_[7:0]: Step counter output (LSbyte) |
| antseggs | 0:5a49275457c6 | 490 | * \endcode |
| antseggs | 0:5a49275457c6 | 491 | */ |
| antseggs | 0:5a49275457c6 | 492 | #define LSM6DS3_XG_STEP_COUNTER_L 0x4B |
| antseggs | 0:5a49275457c6 | 493 | |
| antseggs | 0:5a49275457c6 | 494 | /** |
| antseggs | 0:5a49275457c6 | 495 | * @brief Step counter output register (r). |
| antseggs | 0:5a49275457c6 | 496 | * \code |
| antseggs | 0:5a49275457c6 | 497 | * Read |
| antseggs | 0:5a49275457c6 | 498 | * Default value: output |
| antseggs | 0:5a49275457c6 | 499 | * [7:0] STEP_COUNTER_H_[7:0]: Step counter output (MSbyte) |
| antseggs | 0:5a49275457c6 | 500 | * \endcode |
| antseggs | 0:5a49275457c6 | 501 | */ |
| antseggs | 0:5a49275457c6 | 502 | #define LSM6DS3_XG_STEP_COUNTER_H 0x4C |
| antseggs | 0:5a49275457c6 | 503 | |
| antseggs | 0:5a49275457c6 | 504 | /** |
| antseggs | 0:5a49275457c6 | 505 | * @brief Significant motion, tilt, step detector, soft iron and sensor hub interrupt source register |
| antseggs | 0:5a49275457c6 | 506 | * \code |
| antseggs | 0:5a49275457c6 | 507 | * Read |
| antseggs | 0:5a49275457c6 | 508 | * Default value: output |
| antseggs | 0:5a49275457c6 | 509 | * [7] This bit must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 510 | * [6] SIGN_MOTION_IA: Significant motion event detection status. Default value: 0 |
| antseggs | 0:5a49275457c6 | 511 | * [5] TILT_IA: Tilt event detection status. Default value: 0 |
| antseggs | 0:5a49275457c6 | 512 | * [5] STEP_DETECTED: Step detector event detection status. Default value: 0 |
| antseggs | 0:5a49275457c6 | 513 | * [3:2] This bit must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 514 | * [1] SI_END_OP:Soft iron calculation status. Default value: 0 |
| antseggs | 0:5a49275457c6 | 515 | * [0] SENSORHUB_END_OP:Senso hub communication status. Default value: 0 |
| antseggs | 0:5a49275457c6 | 516 | * \endcode |
| antseggs | 0:5a49275457c6 | 517 | */ |
| antseggs | 0:5a49275457c6 | 518 | #define LSM6DS3_XG_FUNC_SRC 0x53 |
| antseggs | 0:5a49275457c6 | 519 | |
| antseggs | 0:5a49275457c6 | 520 | /** |
| antseggs | 0:5a49275457c6 | 521 | * @brief Time stamp, pedometer, tilt, filtering, and tap recognition functions configuration register |
| antseggs | 0:5a49275457c6 | 522 | * \code |
| antseggs | 0:5a49275457c6 | 523 | * Read/write |
| antseggs | 0:5a49275457c6 | 524 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 525 | * [7] TIMER_EN: Time stamp count enable, output data are collected in TIMESTAMP0_REG (40h), TIMESTAMP1_REG (41h), TIMESTAMP2_REG (42h) register. Default: 0 |
| antseggs | 0:5a49275457c6 | 526 | * [6] PEDO_EN: Pedometer algorithm enable(1). Default value: 0 |
| antseggs | 0:5a49275457c6 | 527 | * [5] TILT_EN: Tilt calculation enable.(2) Default value: 0 |
| antseggs | 0:5a49275457c6 | 528 | * [4] This bit must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 529 | * [3] TAP_X_EN: Enable X direction in tap recognition. Default value: 0 |
| antseggs | 0:5a49275457c6 | 530 | * [2] TAP_Y_EN: Enable Z direction in tap recognition. Default value: 0 |
| antseggs | 0:5a49275457c6 | 531 | * [1] TAP_Z_EN: Enable Z direction in tap recognition. Default value: 0 |
| antseggs | 0:5a49275457c6 | 532 | * [0] LIR: Relatch of the time stamp, pedometer, tilt, filtering, and tap recognition functions routed to PINs. |
| antseggs | 0:5a49275457c6 | 533 | * \endcode |
| antseggs | 0:5a49275457c6 | 534 | */ |
| antseggs | 0:5a49275457c6 | 535 | #define LSM6DS3_XG_TAP_CFG 0x58 |
| antseggs | 0:5a49275457c6 | 536 | |
| antseggs | 0:5a49275457c6 | 537 | /** |
| antseggs | 0:5a49275457c6 | 538 | * @brief Portrait/landscape position and tap function threshold register |
| antseggs | 0:5a49275457c6 | 539 | * \code |
| antseggs | 0:5a49275457c6 | 540 | * Read/write |
| antseggs | 0:5a49275457c6 | 541 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 542 | * [7] This bit must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 543 | * [6:5] SIXD_THS[1:0]: Threshold for D6D function. Default value: 00 |
| antseggs | 0:5a49275457c6 | 544 | * [4:0] TAP_THS[4:0]: Threshold for tap recognition. Default value: 0000 |
| antseggs | 0:5a49275457c6 | 545 | * \endcode |
| antseggs | 0:5a49275457c6 | 546 | */ |
| antseggs | 0:5a49275457c6 | 547 | #define LSM6DS3_XG_TAP_THS_6D 0x59 |
| antseggs | 0:5a49275457c6 | 548 | |
| antseggs | 0:5a49275457c6 | 549 | /** |
| antseggs | 0:5a49275457c6 | 550 | * @brief Tap recognition function setting register (r/w) |
| antseggs | 0:5a49275457c6 | 551 | * \code |
| antseggs | 0:5a49275457c6 | 552 | * Read/write |
| antseggs | 0:5a49275457c6 | 553 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 554 | * [7:4] DUR[3:0]: Duration of maximum time gap for double tap recognition. Default: 0000 |
| antseggs | 0:5a49275457c6 | 555 | * [3:2] QUIET[1:0]: Expected quiet time after a tap detection. Default value: 00 |
| antseggs | 0:5a49275457c6 | 556 | * [1:0] SHOCK[1:0]: Maximum duration of over-threshold event. Default value: 00 |
| antseggs | 0:5a49275457c6 | 557 | * \endcode |
| antseggs | 0:5a49275457c6 | 558 | */ |
| antseggs | 0:5a49275457c6 | 559 | #define LSM6DS3_XG_INT_DUR2 0x5A |
| antseggs | 0:5a49275457c6 | 560 | |
| antseggs | 0:5a49275457c6 | 561 | /** |
| antseggs | 0:5a49275457c6 | 562 | * @brief Tap recognition function setting register |
| antseggs | 0:5a49275457c6 | 563 | * \code |
| antseggs | 0:5a49275457c6 | 564 | * Read/write |
| antseggs | 0:5a49275457c6 | 565 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 566 | * [7] SINGLE_DOUBLE_TAP: Single/double tap event detection. Default: 0 |
| antseggs | 0:5a49275457c6 | 567 | * [6] INACTIVITY: Inactivity event enable. Default value: 0 |
| antseggs | 0:5a49275457c6 | 568 | * [5:0] WK_THS[5:0]:Threshold for wake-up. Default value: 0000 |
| antseggs | 0:5a49275457c6 | 569 | * \endcode |
| antseggs | 0:5a49275457c6 | 570 | */ |
| antseggs | 0:5a49275457c6 | 571 | #define LSM6DS3_XG_WAKE_UP_THS 0x5B |
| antseggs | 0:5a49275457c6 | 572 | |
| antseggs | 0:5a49275457c6 | 573 | /** |
| antseggs | 0:5a49275457c6 | 574 | * @brief Free-fall, wake-up, time stamp and sleep mode functions duration setting register (r/w). |
| antseggs | 0:5a49275457c6 | 575 | * \code |
| antseggs | 0:5a49275457c6 | 576 | * Read/write |
| antseggs | 0:5a49275457c6 | 577 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 578 | * [7] FF_DUR5:Free fall duration event. Default: 0 |
| antseggs | 0:5a49275457c6 | 579 | * [6:5] WAKE_DUR[1:0]: Wake up duration event. Default: 00 |
| antseggs | 0:5a49275457c6 | 580 | * [4] TIMER_HR: Time stamp register resolution setting(1). Default value: 0 |
| antseggs | 0:5a49275457c6 | 581 | * [3:0] SLEEP_DUR[3:0] : Duration to go in sleep mode. Default value: 0000 |
| antseggs | 0:5a49275457c6 | 582 | * \endcode |
| antseggs | 0:5a49275457c6 | 583 | */ |
| antseggs | 0:5a49275457c6 | 584 | #define LSM6DS3_XG_WAKE_UP_DUR 0x5C |
| antseggs | 0:5a49275457c6 | 585 | |
| antseggs | 0:5a49275457c6 | 586 | /** |
| antseggs | 0:5a49275457c6 | 587 | * @brief Free-fall function duration setting register |
| antseggs | 0:5a49275457c6 | 588 | * \code |
| antseggs | 0:5a49275457c6 | 589 | * Read/write |
| antseggs | 0:5a49275457c6 | 590 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 591 | * [7:3] FF_DUR[4:0]: Free fall duration event. Default: 0. For the complete configuration of the free fall duration, refer to FF_DUR5 in WAKE_UP_DUR (5Ch) configuration |
| antseggs | 0:5a49275457c6 | 592 | * [2:0] FF_THS[2:0]: Free fall threshold setting. Default: 000. |
| antseggs | 0:5a49275457c6 | 593 | * \endcode |
| antseggs | 0:5a49275457c6 | 594 | */ |
| antseggs | 0:5a49275457c6 | 595 | #define LSM6DS3_XG_WAKE_FREE_FALL 0x5D |
| antseggs | 0:5a49275457c6 | 596 | |
| antseggs | 0:5a49275457c6 | 597 | /** |
| antseggs | 0:5a49275457c6 | 598 | * @brief Functions routing on INT1 register |
| antseggs | 0:5a49275457c6 | 599 | * \code |
| antseggs | 0:5a49275457c6 | 600 | * Read/write |
| antseggs | 0:5a49275457c6 | 601 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 602 | * [7] INT1_INACT_STATE: Routing on INT1 of inactivity mode. Default: 0 |
| antseggs | 0:5a49275457c6 | 603 | * [6] INT1_SINGLE_TAP: Single tap recognition routing on INT1. Default: 0 |
| antseggs | 0:5a49275457c6 | 604 | * [5] INT1_WU: Routing of wake-up event on INT1. Default value: 0 |
| antseggs | 0:5a49275457c6 | 605 | * [4] INT1_FF: Routing of free-fall event on INT1. Default value: 0 |
| antseggs | 0:5a49275457c6 | 606 | * [3] INT1_TAP: Routing of tap event on INT1. Default value: 0 |
| antseggs | 0:5a49275457c6 | 607 | * [2] INT1_6D: Routing of 6D event on INT1. Default value: 0 |
| antseggs | 0:5a49275457c6 | 608 | * [1] INT1_TILT: Routing of tilt event on INT1. Default value: 0 |
| antseggs | 0:5a49275457c6 | 609 | * [0] INT1_TIMER: Routing of end counter event of timer on INT1. Default value: 0 |
| antseggs | 0:5a49275457c6 | 610 | * \endcode |
| antseggs | 0:5a49275457c6 | 611 | */ |
| antseggs | 0:5a49275457c6 | 612 | #define LSM6DS3_XG_MD1_CFG 0x5E |
| antseggs | 0:5a49275457c6 | 613 | |
| antseggs | 0:5a49275457c6 | 614 | /** |
| antseggs | 0:5a49275457c6 | 615 | * @brief Functions routing on INT2 register |
| antseggs | 0:5a49275457c6 | 616 | * \code |
| antseggs | 0:5a49275457c6 | 617 | * Read/write |
| antseggs | 0:5a49275457c6 | 618 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 619 | * [7] INT2_INACT_STATE: Routing on INT1 of inactivity mode. Default: 0 |
| antseggs | 0:5a49275457c6 | 620 | * [6] INT2_SINGLE_TAP: Single tap recognition routing on INT1. Default: 0 |
| antseggs | 0:5a49275457c6 | 621 | * [5] INT2_WU: Routing of wake-up event on INT1. Default value: 0 |
| antseggs | 0:5a49275457c6 | 622 | * [4] INT2_FF: Routing of free-fall event on INT1. Default value: 0 |
| antseggs | 0:5a49275457c6 | 623 | * [3] INT2_TAP: Routing of tap event on INT1. Default value: 0 |
| antseggs | 0:5a49275457c6 | 624 | * [2] INT2_6D: Routing of 6D event on INT1. Default value: 0 |
| antseggs | 0:5a49275457c6 | 625 | * [1] INT2_TILT: Routing of tilt event on INT1. Default value: 0 |
| antseggs | 0:5a49275457c6 | 626 | * [0] INT2_TIMER: Routing of end counter event of timer on INT1. Default value: 0 |
| antseggs | 0:5a49275457c6 | 627 | * \endcode |
| antseggs | 0:5a49275457c6 | 628 | */ |
| antseggs | 0:5a49275457c6 | 629 | #define LSM6DS3_XG_MD2_CFG 0x5F |
| antseggs | 0:5a49275457c6 | 630 | |
| antseggs | 0:5a49275457c6 | 631 | /***************************************** SENSORHUB REGISTERS ********************************************/ |
| antseggs | 0:5a49275457c6 | 632 | |
| antseggs | 0:5a49275457c6 | 633 | /** |
| antseggs | 0:5a49275457c6 | 634 | * @brief SENSORHUB REGISTER 1 : SLV0 first external sensor, first axis output register (r). The value is expressed as 16bit word in two�s complement |
| antseggs | 0:5a49275457c6 | 635 | * \code |
| antseggs | 0:5a49275457c6 | 636 | * Read |
| antseggs | 0:5a49275457c6 | 637 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 638 | * [7:0] SHUB1[7:0]: SLV0 first external sensor, first byte of the first axis. |
| antseggs | 0:5a49275457c6 | 639 | * \endcode |
| antseggs | 0:5a49275457c6 | 640 | */ |
| antseggs | 0:5a49275457c6 | 641 | #define LSM6DS3_XG_SENSORHUB1_REG 0x2E |
| antseggs | 0:5a49275457c6 | 642 | |
| antseggs | 0:5a49275457c6 | 643 | /** |
| antseggs | 0:5a49275457c6 | 644 | * @brief SENSORHUB REGISTER 2 : SLV0 first external sensor, first axis output register (r). The value is expressed as 16bit word in two�s complement |
| antseggs | 0:5a49275457c6 | 645 | * \code |
| antseggs | 0:5a49275457c6 | 646 | * Read |
| antseggs | 0:5a49275457c6 | 647 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 648 | * [7:0] SHUB2[7:0]: SLV0 first external sensor, second byte of the first axis. |
| antseggs | 0:5a49275457c6 | 649 | * \endcode |
| antseggs | 0:5a49275457c6 | 650 | */ |
| antseggs | 0:5a49275457c6 | 651 | #define LSM6DS3_XG_SENSORHUB2_REG 0x2F |
| antseggs | 0:5a49275457c6 | 652 | |
| antseggs | 0:5a49275457c6 | 653 | /** |
| antseggs | 0:5a49275457c6 | 654 | * @brief SENSORHUB REGISTER 3 : SLV0 first external sensor, second axis output register (r). The value is expressed as 16bit word in two�s complement |
| antseggs | 0:5a49275457c6 | 655 | * \code |
| antseggs | 0:5a49275457c6 | 656 | * Read |
| antseggs | 0:5a49275457c6 | 657 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 658 | * [7:0] SHUB3[7:0]: SLV0 first external sensor, first byte of the second axis. |
| antseggs | 0:5a49275457c6 | 659 | * \endcode |
| antseggs | 0:5a49275457c6 | 660 | */ |
| antseggs | 0:5a49275457c6 | 661 | #define LSM6DS3_XG_SENSORHUB3_REG 0x30 |
| antseggs | 0:5a49275457c6 | 662 | |
| antseggs | 0:5a49275457c6 | 663 | /** |
| antseggs | 0:5a49275457c6 | 664 | * @brief SENSORHUB REGISTER 4 : SLV0 first external sensor, second axis output register (r). The value is expressed as 16bit word in two�s complement |
| antseggs | 0:5a49275457c6 | 665 | * \code |
| antseggs | 0:5a49275457c6 | 666 | * Read |
| antseggs | 0:5a49275457c6 | 667 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 668 | * [7:0] SHUB4[7:0]: SLV0 first external sensor, second byte of the second axis. |
| antseggs | 0:5a49275457c6 | 669 | * \endcode |
| antseggs | 0:5a49275457c6 | 670 | */ |
| antseggs | 0:5a49275457c6 | 671 | #define LSM6DS3_XG_SENSORHUB4_REG 0x31 |
| antseggs | 0:5a49275457c6 | 672 | |
| antseggs | 0:5a49275457c6 | 673 | /** |
| antseggs | 0:5a49275457c6 | 674 | * @brief SENSORHUB REGISTER 5 : SLV0 first external sensor, third axis output register (r). The value is expressed as 16bit word in two�s complement |
| antseggs | 0:5a49275457c6 | 675 | * \code |
| antseggs | 0:5a49275457c6 | 676 | * Read |
| antseggs | 0:5a49275457c6 | 677 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 678 | * [7:0] SHUB5[7:0]: SLV0 first external sensor, second byte of the second axis. |
| antseggs | 0:5a49275457c6 | 679 | * \endcode |
| antseggs | 0:5a49275457c6 | 680 | */ |
| antseggs | 0:5a49275457c6 | 681 | #define LSM6DS3_XG_SENSORHUB5_REG 0x32 |
| antseggs | 0:5a49275457c6 | 682 | |
| antseggs | 0:5a49275457c6 | 683 | /** |
| antseggs | 0:5a49275457c6 | 684 | * @brief SENSORHUB REGISTER 6 : SLV0 first external sensor, third axis output register (r). The value is expressed as 16bit word in two�s complement |
| antseggs | 0:5a49275457c6 | 685 | * \code |
| antseggs | 0:5a49275457c6 | 686 | * Read |
| antseggs | 0:5a49275457c6 | 687 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 688 | * [7:0] SHUB6[7:0]: SLV0 first external sensor, second byte of the third axis |
| antseggs | 0:5a49275457c6 | 689 | * \endcode |
| antseggs | 0:5a49275457c6 | 690 | */ |
| antseggs | 0:5a49275457c6 | 691 | #define LSM6DS3_XG_SENSORHUB6_REG 0x33 |
| antseggs | 0:5a49275457c6 | 692 | |
| antseggs | 0:5a49275457c6 | 693 | /** |
| antseggs | 0:5a49275457c6 | 694 | * @brief SENSORHUB REGISTER 7 : SLV1 second external sensor, first axis output register (r). The value is expressed as 16bit word in two�s complement |
| antseggs | 0:5a49275457c6 | 695 | * \code |
| antseggs | 0:5a49275457c6 | 696 | * Read |
| antseggs | 0:5a49275457c6 | 697 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 698 | * [7:0] SHUB7[7:0]: SLV1 second external sensor, first byte of the first axis. |
| antseggs | 0:5a49275457c6 | 699 | * \endcode |
| antseggs | 0:5a49275457c6 | 700 | */ |
| antseggs | 0:5a49275457c6 | 701 | #define LSM6DS3_XG_SENSORHUB7_REG 0x34 |
| antseggs | 0:5a49275457c6 | 702 | |
| antseggs | 0:5a49275457c6 | 703 | /** |
| antseggs | 0:5a49275457c6 | 704 | * @brief SENSORHUB REGISTER 8 : SLV1 second external sensor, first axis output register (r). The value is expressed as 16bit word in two�s complement |
| antseggs | 0:5a49275457c6 | 705 | * \code |
| antseggs | 0:5a49275457c6 | 706 | * Read |
| antseggs | 0:5a49275457c6 | 707 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 708 | * [7:0] SHUB8[7:0]: SLV1 second external sensor, second byte of the first axis. |
| antseggs | 0:5a49275457c6 | 709 | * \endcode |
| antseggs | 0:5a49275457c6 | 710 | */ |
| antseggs | 0:5a49275457c6 | 711 | #define LSM6DS3_XG_SENSORHUB8_REG 0x35 |
| antseggs | 0:5a49275457c6 | 712 | |
| antseggs | 0:5a49275457c6 | 713 | /** |
| antseggs | 0:5a49275457c6 | 714 | * @brief SENSORHUB REGISTER 9 : SLV1 second external sensor,, second axis output register (r). The value is expressed as 16bit word in two�s complement |
| antseggs | 0:5a49275457c6 | 715 | * \code |
| antseggs | 0:5a49275457c6 | 716 | * Read |
| antseggs | 0:5a49275457c6 | 717 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 718 | * [7:0] SHUB9[7:0]: SLV1 second external sensor, first byte of the second axis. |
| antseggs | 0:5a49275457c6 | 719 | * \endcode |
| antseggs | 0:5a49275457c6 | 720 | */ |
| antseggs | 0:5a49275457c6 | 721 | #define LSM6DS3_XG_SENSORHUB9_REG 0x36 |
| antseggs | 0:5a49275457c6 | 722 | |
| antseggs | 0:5a49275457c6 | 723 | /** |
| antseggs | 0:5a49275457c6 | 724 | * @brief SLV1 second external sensor, second axis output register (r). The value is expressed as 16bit word in two�s complement |
| antseggs | 0:5a49275457c6 | 725 | * \code |
| antseggs | 0:5a49275457c6 | 726 | * Read |
| antseggs | 0:5a49275457c6 | 727 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 728 | * [7:0] SHUB10[7:0]: SLV1 second external sensor, second byte of the second axis. |
| antseggs | 0:5a49275457c6 | 729 | * \endcode |
| antseggs | 0:5a49275457c6 | 730 | */ |
| antseggs | 0:5a49275457c6 | 731 | #define LSM6DS3_XG_SENSORHUB10_REG 0x37 |
| antseggs | 0:5a49275457c6 | 732 | |
| antseggs | 0:5a49275457c6 | 733 | /** |
| antseggs | 0:5a49275457c6 | 734 | * @brief SLV1 second external sensor, third axis output register (r). The value is expressed as 16bit word in two�s complement |
| antseggs | 0:5a49275457c6 | 735 | * \code |
| antseggs | 0:5a49275457c6 | 736 | * Read |
| antseggs | 0:5a49275457c6 | 737 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 738 | * [7:0] SHUB11[7:0]: SLV1 second external sensor, first byte of the third axis. |
| antseggs | 0:5a49275457c6 | 739 | * \endcode |
| antseggs | 0:5a49275457c6 | 740 | */ |
| antseggs | 0:5a49275457c6 | 741 | #define LSM6DS3_XG_SENSORHUB11_REG 0x38 |
| antseggs | 0:5a49275457c6 | 742 | |
| antseggs | 0:5a49275457c6 | 743 | /** |
| antseggs | 0:5a49275457c6 | 744 | * @brief SLV1 second external sensor, third axis output register (r). The value is expressed as 16bit word in two�s complement |
| antseggs | 0:5a49275457c6 | 745 | * \code |
| antseggs | 0:5a49275457c6 | 746 | * Read |
| antseggs | 0:5a49275457c6 | 747 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 748 | * [7:0] SHUB12[7:0]: SLV1 second external sensor, second byte of the third axis. |
| antseggs | 0:5a49275457c6 | 749 | * \endcode |
| antseggs | 0:5a49275457c6 | 750 | */ |
| antseggs | 0:5a49275457c6 | 751 | #define LSM6DS3_XG_SENSORHUB12_REG 0x39 |
| antseggs | 0:5a49275457c6 | 752 | |
| antseggs | 0:5a49275457c6 | 753 | |
| antseggs | 0:5a49275457c6 | 754 | |
| antseggs | 0:5a49275457c6 | 755 | |
| antseggs | 0:5a49275457c6 | 756 | /***************************************** GYROSCOPE REGISTERS ********************************************/ |
| antseggs | 0:5a49275457c6 | 757 | |
| antseggs | 0:5a49275457c6 | 758 | /** |
| antseggs | 0:5a49275457c6 | 759 | * @brief Angular rate sensor Control Register 2 |
| antseggs | 0:5a49275457c6 | 760 | * \code |
| antseggs | 0:5a49275457c6 | 761 | * Read/write |
| antseggs | 0:5a49275457c6 | 762 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 763 | * [7:4] ODR_G[3:0]: Gyroscope output data rate selection |
| antseggs | 0:5a49275457c6 | 764 | * [3:2] FS_G[1-0]: Gyroscope full-scale selection |
| antseggs | 0:5a49275457c6 | 765 | * [1] FS_125: Gyroscope full-scale at 125 dps |
| antseggs | 0:5a49275457c6 | 766 | * [0] This bit must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 767 | * \endcode |
| antseggs | 0:5a49275457c6 | 768 | */ |
| antseggs | 0:5a49275457c6 | 769 | #define LSM6DS3_XG_CTRL2_G 0x11 |
| antseggs | 0:5a49275457c6 | 770 | |
| antseggs | 0:5a49275457c6 | 771 | |
| antseggs | 0:5a49275457c6 | 772 | /** |
| antseggs | 0:5a49275457c6 | 773 | * @brief Angular rate sensor Control Register 6 |
| antseggs | 0:5a49275457c6 | 774 | * \code |
| antseggs | 0:5a49275457c6 | 775 | * Read/write |
| antseggs | 0:5a49275457c6 | 776 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 777 | * [7] TRIG_EN: Data edge sensitive trigger Enable. Default value: 0 |
| antseggs | 0:5a49275457c6 | 778 | * [6] LVLen: Data level sensitive trigger Enable. Default value: 0 |
| antseggs | 0:5a49275457c6 | 779 | * [5] LVL2en: Level sensitive latched Enable. Default value: 0 |
| antseggs | 0:5a49275457c6 | 780 | * [4] XL_H_MODE: High Performance operating mode disable for accelerometer(1). Default value: 0 |
| antseggs | 0:5a49275457c6 | 781 | * [3:0] This bit must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 782 | * \endcode |
| antseggs | 0:5a49275457c6 | 783 | */ |
| antseggs | 0:5a49275457c6 | 784 | #define LSM6DS3_XG_CTRL6_G 0x15 |
| antseggs | 0:5a49275457c6 | 785 | |
| antseggs | 0:5a49275457c6 | 786 | |
| antseggs | 0:5a49275457c6 | 787 | /** |
| antseggs | 0:5a49275457c6 | 788 | * @brief Angular rate sensor Control Register 7 |
| antseggs | 0:5a49275457c6 | 789 | * \code |
| antseggs | 0:5a49275457c6 | 790 | * Read/write |
| antseggs | 0:5a49275457c6 | 791 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 792 | * [7] G_H_MODE: High Performance operating mode disable for Gyroscope(1) . Default: 0 |
| antseggs | 0:5a49275457c6 | 793 | * [6] HP_EN: High Pass filter Enable. Default Value: 0 |
| antseggs | 0:5a49275457c6 | 794 | * [5:4] HPCF_G[1:0]: Gyroscope High Pass filter Cut Off frequency selection. Default value: 00 |
| antseggs | 0:5a49275457c6 | 795 | * [3:0] This bit must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 796 | * \endcode |
| antseggs | 0:5a49275457c6 | 797 | */ |
| antseggs | 0:5a49275457c6 | 798 | #define LSM6DS3_XG_CTRL7_G 0x16 |
| antseggs | 0:5a49275457c6 | 799 | |
| antseggs | 0:5a49275457c6 | 800 | /** |
| antseggs | 0:5a49275457c6 | 801 | * @brief Gyroscope data (LSB) |
| antseggs | 0:5a49275457c6 | 802 | * \code |
| antseggs | 0:5a49275457c6 | 803 | * Read |
| antseggs | 0:5a49275457c6 | 804 | * \endcode |
| antseggs | 0:5a49275457c6 | 805 | */ |
| antseggs | 0:5a49275457c6 | 806 | #define LSM6DS3_XG_OUT_X_L_G 0x22 |
| antseggs | 0:5a49275457c6 | 807 | |
| antseggs | 0:5a49275457c6 | 808 | |
| antseggs | 0:5a49275457c6 | 809 | /** |
| antseggs | 0:5a49275457c6 | 810 | * @brief Gyroscope data (MSB) |
| antseggs | 0:5a49275457c6 | 811 | * \code |
| antseggs | 0:5a49275457c6 | 812 | * Read |
| antseggs | 0:5a49275457c6 | 813 | * \endcode |
| antseggs | 0:5a49275457c6 | 814 | */ |
| antseggs | 0:5a49275457c6 | 815 | #define LSM6DS3_XG_OUT_X_H_G 0x23 |
| antseggs | 0:5a49275457c6 | 816 | |
| antseggs | 0:5a49275457c6 | 817 | |
| antseggs | 0:5a49275457c6 | 818 | /** |
| antseggs | 0:5a49275457c6 | 819 | * @brief Gyroscope data (LSB) |
| antseggs | 0:5a49275457c6 | 820 | * \code |
| antseggs | 0:5a49275457c6 | 821 | * Read |
| antseggs | 0:5a49275457c6 | 822 | * \endcode |
| antseggs | 0:5a49275457c6 | 823 | */ |
| antseggs | 0:5a49275457c6 | 824 | #define LSM6DS3_XG_OUT_Y_L_G 0x24 |
| antseggs | 0:5a49275457c6 | 825 | |
| antseggs | 0:5a49275457c6 | 826 | |
| antseggs | 0:5a49275457c6 | 827 | /** |
| antseggs | 0:5a49275457c6 | 828 | * @brief Gyroscope data (MSB) |
| antseggs | 0:5a49275457c6 | 829 | * \code |
| antseggs | 0:5a49275457c6 | 830 | * Read |
| antseggs | 0:5a49275457c6 | 831 | * \endcode |
| antseggs | 0:5a49275457c6 | 832 | */ |
| antseggs | 0:5a49275457c6 | 833 | #define LSM6DS3_XG_OUT_Y_H_G 0x25 |
| antseggs | 0:5a49275457c6 | 834 | |
| antseggs | 0:5a49275457c6 | 835 | |
| antseggs | 0:5a49275457c6 | 836 | /** |
| antseggs | 0:5a49275457c6 | 837 | * @brief Gyroscope data (LSB) |
| antseggs | 0:5a49275457c6 | 838 | * \code |
| antseggs | 0:5a49275457c6 | 839 | * Read |
| antseggs | 0:5a49275457c6 | 840 | * \endcode |
| antseggs | 0:5a49275457c6 | 841 | */ |
| antseggs | 0:5a49275457c6 | 842 | #define LSM6DS3_XG_OUT_Z_L_G 0x26 |
| antseggs | 0:5a49275457c6 | 843 | |
| antseggs | 0:5a49275457c6 | 844 | |
| antseggs | 0:5a49275457c6 | 845 | /** |
| antseggs | 0:5a49275457c6 | 846 | * @brief Gyroscope data (MSB) |
| antseggs | 0:5a49275457c6 | 847 | * \code |
| antseggs | 0:5a49275457c6 | 848 | * Read |
| antseggs | 0:5a49275457c6 | 849 | * \endcode |
| antseggs | 0:5a49275457c6 | 850 | */ |
| antseggs | 0:5a49275457c6 | 851 | #define LSM6DS3_XG_OUT_Z_H_G 0x27 |
| antseggs | 0:5a49275457c6 | 852 | |
| antseggs | 0:5a49275457c6 | 853 | |
| antseggs | 0:5a49275457c6 | 854 | |
| antseggs | 0:5a49275457c6 | 855 | /*************************************** ACCELEROMETER REGISTERS *******************************************/ |
| antseggs | 0:5a49275457c6 | 856 | |
| antseggs | 0:5a49275457c6 | 857 | /** |
| antseggs | 0:5a49275457c6 | 858 | * @brief Linear acceleration sensor Control Register 1 |
| antseggs | 0:5a49275457c6 | 859 | * \code |
| antseggs | 0:5a49275457c6 | 860 | * Read/write |
| antseggs | 0:5a49275457c6 | 861 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 862 | * [7:4] ODR_XL3-0: Accelerometer Output data rate and power mode selection |
| antseggs | 0:5a49275457c6 | 863 | * [3:2] FS_XL1-0: Accelerometer full-scale selection |
| antseggs | 0:5a49275457c6 | 864 | * [1:0] BW_XL1-0: Anti-aliasing filter bandwidth selection |
| antseggs | 0:5a49275457c6 | 865 | * \endcode |
| antseggs | 0:5a49275457c6 | 866 | */ |
| antseggs | 0:5a49275457c6 | 867 | #define LSM6DS3_XG_CTRL1_XL 0x10 |
| antseggs | 0:5a49275457c6 | 868 | |
| antseggs | 0:5a49275457c6 | 869 | /** |
| antseggs | 0:5a49275457c6 | 870 | * @brief XL sensor Control Register 8 |
| antseggs | 0:5a49275457c6 | 871 | * \code |
| antseggs | 0:5a49275457c6 | 872 | * Read/write |
| antseggs | 0:5a49275457c6 | 873 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 874 | * [7:3] This bit must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 875 | * [2] SLOPE_FDS: Enable HP filter on output registers and FIFO. Default value: 0 |
| antseggs | 0:5a49275457c6 | 876 | * [1:0] This bit must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 877 | * \endcode |
| antseggs | 0:5a49275457c6 | 878 | */ |
| antseggs | 0:5a49275457c6 | 879 | #define LSM6DS3_XG_CTRL8_XL 0x17 |
| antseggs | 0:5a49275457c6 | 880 | |
| antseggs | 0:5a49275457c6 | 881 | /** |
| antseggs | 0:5a49275457c6 | 882 | * @brief Linear acceleration sensor Control Register 9 |
| antseggs | 0:5a49275457c6 | 883 | * \code |
| antseggs | 0:5a49275457c6 | 884 | * Read/write |
| antseggs | 0:5a49275457c6 | 885 | * Default value: 0x38 |
| antseggs | 0:5a49275457c6 | 886 | * [7:6] These bits must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 887 | * [5] Zen_XL: Accelerometers�s Z-axis output enable |
| antseggs | 0:5a49275457c6 | 888 | * [4] Yen_XL: Accelerometers�s Y-axis output enable |
| antseggs | 0:5a49275457c6 | 889 | * [3] Xen_XL: Accelerometers�s X-axis output enable |
| antseggs | 0:5a49275457c6 | 890 | * [2:0] These bits must be set to �0� for the correct operation of the device |
| antseggs | 0:5a49275457c6 | 891 | * \endcode |
| antseggs | 0:5a49275457c6 | 892 | */ |
| antseggs | 0:5a49275457c6 | 893 | #define LSM6DS3_XG_CTRL9_XL 0x18 |
| antseggs | 0:5a49275457c6 | 894 | |
| antseggs | 0:5a49275457c6 | 895 | |
| antseggs | 0:5a49275457c6 | 896 | /** |
| antseggs | 0:5a49275457c6 | 897 | * @brief Accelerometer data (LSB) |
| antseggs | 0:5a49275457c6 | 898 | * \code |
| antseggs | 0:5a49275457c6 | 899 | * Read |
| antseggs | 0:5a49275457c6 | 900 | * \endcode |
| antseggs | 0:5a49275457c6 | 901 | */ |
| antseggs | 0:5a49275457c6 | 902 | #define LSM6DS3_XG_OUT_X_L_XL 0x28 |
| antseggs | 0:5a49275457c6 | 903 | |
| antseggs | 0:5a49275457c6 | 904 | |
| antseggs | 0:5a49275457c6 | 905 | /** |
| antseggs | 0:5a49275457c6 | 906 | * @brief Accelerometer data (MSB) |
| antseggs | 0:5a49275457c6 | 907 | * \code |
| antseggs | 0:5a49275457c6 | 908 | * Read |
| antseggs | 0:5a49275457c6 | 909 | * \endcode |
| antseggs | 0:5a49275457c6 | 910 | */ |
| antseggs | 0:5a49275457c6 | 911 | #define LSM6DS3_XG_OUT_X_H_XL 0x29 |
| antseggs | 0:5a49275457c6 | 912 | |
| antseggs | 0:5a49275457c6 | 913 | |
| antseggs | 0:5a49275457c6 | 914 | /** |
| antseggs | 0:5a49275457c6 | 915 | * @brief Accelerometer data (LSB) |
| antseggs | 0:5a49275457c6 | 916 | * \code |
| antseggs | 0:5a49275457c6 | 917 | * Read |
| antseggs | 0:5a49275457c6 | 918 | * \endcode |
| antseggs | 0:5a49275457c6 | 919 | */ |
| antseggs | 0:5a49275457c6 | 920 | #define LSM6DS3_XG_OUT_Y_L_XL 0x2A |
| antseggs | 0:5a49275457c6 | 921 | |
| antseggs | 0:5a49275457c6 | 922 | |
| antseggs | 0:5a49275457c6 | 923 | /** |
| antseggs | 0:5a49275457c6 | 924 | * @brief Accelerometer data (MSB) |
| antseggs | 0:5a49275457c6 | 925 | * \code |
| antseggs | 0:5a49275457c6 | 926 | * Read |
| antseggs | 0:5a49275457c6 | 927 | * \endcode |
| antseggs | 0:5a49275457c6 | 928 | */ |
| antseggs | 0:5a49275457c6 | 929 | #define LSM6DS3_XG_OUT_Y_H_XL 0x2B |
| antseggs | 0:5a49275457c6 | 930 | |
| antseggs | 0:5a49275457c6 | 931 | |
| antseggs | 0:5a49275457c6 | 932 | /** |
| antseggs | 0:5a49275457c6 | 933 | * @brief Accelerometer data (LSB) |
| antseggs | 0:5a49275457c6 | 934 | * \code |
| antseggs | 0:5a49275457c6 | 935 | * Read |
| antseggs | 0:5a49275457c6 | 936 | * \endcode |
| antseggs | 0:5a49275457c6 | 937 | */ |
| antseggs | 0:5a49275457c6 | 938 | #define LSM6DS3_XG_OUT_Z_L_XL 0x2C |
| antseggs | 0:5a49275457c6 | 939 | |
| antseggs | 0:5a49275457c6 | 940 | |
| antseggs | 0:5a49275457c6 | 941 | /** |
| antseggs | 0:5a49275457c6 | 942 | * @brief Accelerometer data (MSB) |
| antseggs | 0:5a49275457c6 | 943 | * \code |
| antseggs | 0:5a49275457c6 | 944 | * Read |
| antseggs | 0:5a49275457c6 | 945 | * \endcode |
| antseggs | 0:5a49275457c6 | 946 | */ |
| antseggs | 0:5a49275457c6 | 947 | #define LSM6DS3_XG_OUT_Z_H_XL 0x2D |
| antseggs | 0:5a49275457c6 | 948 | |
| antseggs | 0:5a49275457c6 | 949 | /******************************************************************************/ |
| antseggs | 0:5a49275457c6 | 950 | /************* END ACCELEROMETER AND GYROSCOPE REGISTER MAPPING **************/ |
| antseggs | 0:5a49275457c6 | 951 | /******************************************************************************/ |
| antseggs | 0:5a49275457c6 | 952 | |
| antseggs | 0:5a49275457c6 | 953 | |
| antseggs | 0:5a49275457c6 | 954 | /************************************** COMMON REGISTERS VALUE *******************************************/ |
| antseggs | 0:5a49275457c6 | 955 | |
| antseggs | 0:5a49275457c6 | 956 | /** |
| antseggs | 0:5a49275457c6 | 957 | * @brief Device Address |
| antseggs | 0:5a49275457c6 | 958 | */ |
| antseggs | 0:5a49275457c6 | 959 | #define LSM6DS3_ADDRESS_LOW 0xD4 // SAD[0] = 0 |
| antseggs | 0:5a49275457c6 | 960 | #define LSM6DS3_ADDRESS_HIGH 0xD6 // SAD[0] = 1 |
| antseggs | 0:5a49275457c6 | 961 | #define LSM6DS3_XG_MEMS_ADDRESS LSM6DS3_ADDRESS_LOW // SAD[0] = 0 |
| antseggs | 0:5a49275457c6 | 962 | |
| antseggs | 0:5a49275457c6 | 963 | |
| antseggs | 0:5a49275457c6 | 964 | /** |
| antseggs | 0:5a49275457c6 | 965 | * @brief Device Identifier. Default value of the WHO_AM_I register. |
| antseggs | 0:5a49275457c6 | 966 | */ |
| antseggs | 0:5a49275457c6 | 967 | #define I_AM_LSM6DS3_XG ((uint8_t)0x69) |
| antseggs | 0:5a49275457c6 | 968 | |
| antseggs | 0:5a49275457c6 | 969 | |
| antseggs | 0:5a49275457c6 | 970 | /** |
| antseggs | 0:5a49275457c6 | 971 | * @brief Register address automatically incremented during a multiple byte |
| antseggs | 0:5a49275457c6 | 972 | * access with a serial interface (I2C or SPI). Default value of the |
| antseggs | 0:5a49275457c6 | 973 | * LSM6DS3_XG_CTRL3_C register. |
| antseggs | 0:5a49275457c6 | 974 | */ |
| antseggs | 0:5a49275457c6 | 975 | #define LSM6DS3_XG_IF_INC ((uint8_t)0x04) |
| antseggs | 0:5a49275457c6 | 976 | |
| antseggs | 0:5a49275457c6 | 977 | #define LSM6DS3_XG_IF_INC_MASK ((uint8_t)0x04) |
| antseggs | 0:5a49275457c6 | 978 | |
| antseggs | 0:5a49275457c6 | 979 | /** @defgroup LSM6DS3_XG_FIFO_Output_Data_Rate_Selection_FIFO_CTRL5 LSM6DS3_XG_FIFO_Output_Data_Rate_Selection_FIFO_CTRL5 |
| antseggs | 0:5a49275457c6 | 980 | * @{ |
| antseggs | 0:5a49275457c6 | 981 | */ |
| antseggs | 0:5a49275457c6 | 982 | #define LSM6DS3_XG_FIFO_ODR_NA ((uint8_t)0x00) /*!< FIFO ODR NA */ |
| antseggs | 0:5a49275457c6 | 983 | #define LSM6DS3_XG_FIFO_ODR_10HZ ((uint8_t)0x08) /*!< FIFO ODR 10Hz */ |
| antseggs | 0:5a49275457c6 | 984 | #define LSM6DS3_XG_FIFO_ODR_25HZ ((uint8_t)0x10) /*!< FIFO ODR 25Hz */ |
| antseggs | 0:5a49275457c6 | 985 | #define LSM6DS3_XG_FIFO_ODR_50HZ ((uint8_t)0x18) /*!< FIFO ODR 50Hz */ |
| antseggs | 0:5a49275457c6 | 986 | #define LSM6DS3_XG_FIFO_ODR_100HZ ((uint8_t)0x20) /*!< FIFO ODR 100Hz */ |
| antseggs | 0:5a49275457c6 | 987 | #define LSM6DS3_XG_FIFO_ODR_200HZ ((uint8_t)0x28) /*!< FIFO ODR 200Hz */ |
| antseggs | 0:5a49275457c6 | 988 | #define LSM6DS3_XG_FIFO_ODR_400HZ ((uint8_t)0x30) /*!< FIFO ODR 400Hz */ |
| antseggs | 0:5a49275457c6 | 989 | #define LSM6DS3_XG_FIFO_ODR_800HZ ((uint8_t)0x38) /*!< FIFO ODR 800Hz */ |
| antseggs | 0:5a49275457c6 | 990 | #define LSM6DS3_XG_FIFO_ODR_1600HZ ((uint8_t)0x40) /*!< FIFO ODR 1600Hz */ |
| antseggs | 0:5a49275457c6 | 991 | #define LSM6DS3_XG_FIFO_ODR_3300HZ ((uint8_t)0x48) /*!< FIFO ODR 3300Hz */ |
| antseggs | 0:5a49275457c6 | 992 | #define LSM6DS3_XG_FIFO_ODR_6600HZ ((uint8_t)0x50) /*!< FIFO ODR 6600Hz */ |
| antseggs | 0:5a49275457c6 | 993 | |
| antseggs | 0:5a49275457c6 | 994 | #define LSM6DS3_XG_FIFO_ODR_MASK ((uint8_t)0x78) |
| antseggs | 0:5a49275457c6 | 995 | /** |
| antseggs | 0:5a49275457c6 | 996 | * @} |
| antseggs | 0:5a49275457c6 | 997 | */ |
| antseggs | 0:5a49275457c6 | 998 | |
| antseggs | 0:5a49275457c6 | 999 | /** @defgroup LSM6DS3_XG_FIFO_Mode_Selection_FIFO_CTRL5 LSM6DS3_XG_FIFO_Mode_Selection_FIFO_CTRL5 |
| antseggs | 0:5a49275457c6 | 1000 | * @{ |
| antseggs | 0:5a49275457c6 | 1001 | */ |
| antseggs | 0:5a49275457c6 | 1002 | #define LSM6DS3_XG_FIFO_MODE_BYPASS ((uint8_t)0x00) /*!< BYPASS Mode. FIFO turned off */ |
| antseggs | 0:5a49275457c6 | 1003 | #define LSM6DS3_XG_FIFO_MODE_FIFO ((uint8_t)0x01) /*!< FIFO Mode. Stop collecting data when FIFO is full */ |
| antseggs | 0:5a49275457c6 | 1004 | #define LSM6DS3_XG_FIFO_MODE_CONTINUOUS_THEN_FIFO ((uint8_t)0x03) /*!< CONTINUOUS mode until trigger is deasserted, then FIFO mode */ |
| antseggs | 0:5a49275457c6 | 1005 | #define LSM6DS3_XG_FIFO_MODE_BYPASS_THEN_CONTINUOUS ((uint8_t)0x04) /*!< BYPASS mode until trigger is deasserted, then CONTINUOUS mode */ |
| antseggs | 0:5a49275457c6 | 1006 | #define LSM6DS3_XG_FIFO_MODE_CONTINUOUS_OVERWRITE ((uint8_t)0x05) /*!< CONTINUOUS mode. If the FIFO is full the new sample overwrite the older one */ |
| antseggs | 0:5a49275457c6 | 1007 | |
| antseggs | 0:5a49275457c6 | 1008 | #define LSM6DS3_XG_FIFO_MODE_MASK ((uint8_t)0x07) |
| antseggs | 0:5a49275457c6 | 1009 | /** |
| antseggs | 0:5a49275457c6 | 1010 | * @} |
| antseggs | 0:5a49275457c6 | 1011 | */ |
| antseggs | 0:5a49275457c6 | 1012 | |
| antseggs | 0:5a49275457c6 | 1013 | |
| antseggs | 0:5a49275457c6 | 1014 | /************************************** GYROSCOPE REGISTERS VALUE *******************************************/ |
| antseggs | 0:5a49275457c6 | 1015 | |
| antseggs | 0:5a49275457c6 | 1016 | |
| antseggs | 0:5a49275457c6 | 1017 | /** @addtogroup LSM6DS3_XG_Gyroscope_Output_Data_Rate_Selection_CTRL_REG1_G LSM6DS3_XG_Gyroscope_Output_Data_Rate_Selection_CTRL_REG1_G |
| antseggs | 0:5a49275457c6 | 1018 | * @{ |
| antseggs | 0:5a49275457c6 | 1019 | */ |
| antseggs | 0:5a49275457c6 | 1020 | #define LSM6DS3_G_ODR_PD ((uint8_t)0x00) /*!< Output Data Rate: Power-down*/ |
| antseggs | 0:5a49275457c6 | 1021 | #define LSM6DS3_G_ODR_13HZ ((uint8_t)0x10) /*!< Output Data Rate: 13 Hz*/ |
| antseggs | 0:5a49275457c6 | 1022 | #define LSM6DS3_G_ODR_26HZ ((uint8_t)0x20) /*!< Output Data Rate: 26 Hz*/ |
| antseggs | 0:5a49275457c6 | 1023 | #define LSM6DS3_G_ODR_52HZ ((uint8_t)0x30) /*!< Output Data Rate: 52 Hz */ |
| antseggs | 0:5a49275457c6 | 1024 | #define LSM6DS3_G_ODR_104HZ ((uint8_t)0x40) /*!< Output Data Rate: 104 Hz */ |
| antseggs | 0:5a49275457c6 | 1025 | #define LSM6DS3_G_ODR_208HZ ((uint8_t)0x50) /*!< Output Data Rate: 208 Hz */ |
| antseggs | 0:5a49275457c6 | 1026 | #define LSM6DS3_G_ODR_416HZ ((uint8_t)0x60) /*!< Output Data Rate: 416 Hz */ |
| antseggs | 0:5a49275457c6 | 1027 | #define LSM6DS3_G_ODR_833HZ ((uint8_t)0x70) /*!< Output Data Rate: 833 Hz */ |
| antseggs | 0:5a49275457c6 | 1028 | #define LSM6DS3_G_ODR_1660HZ ((uint8_t)0x80) /*!< Output Data Rate: 1.66 kHz */ |
| antseggs | 0:5a49275457c6 | 1029 | |
| antseggs | 0:5a49275457c6 | 1030 | #define LSM6DS3_G_ODR_MASK ((uint8_t)0xF0) |
| antseggs | 0:5a49275457c6 | 1031 | |
| antseggs | 0:5a49275457c6 | 1032 | /** |
| antseggs | 0:5a49275457c6 | 1033 | * @} |
| antseggs | 0:5a49275457c6 | 1034 | */ |
| antseggs | 0:5a49275457c6 | 1035 | |
| antseggs | 0:5a49275457c6 | 1036 | |
| antseggs | 0:5a49275457c6 | 1037 | /** @addtogroup LSM6DS3_XG_Gyroscope_Full_Scale_Selection_CTRL2_G LSM6DS3_XG_Gyroscope_Full_Scale_Selection_CTRL2_G |
| antseggs | 0:5a49275457c6 | 1038 | * @{ |
| antseggs | 0:5a49275457c6 | 1039 | */ |
| antseggs | 0:5a49275457c6 | 1040 | #define LSM6DS3_G_FS_125_DISABLE ((uint8_t)0x00) /*!< Full scale: 125 dps enable: disable */ |
| antseggs | 0:5a49275457c6 | 1041 | #define LSM6DS3_G_FS_125_ENABLE ((uint8_t)0x02) /*!< Full scale: 125 dps enable: enable */ |
| antseggs | 0:5a49275457c6 | 1042 | |
| antseggs | 0:5a49275457c6 | 1043 | #define LSM6DS3_G_FS_125_MASK ((uint8_t)0x02) |
| antseggs | 0:5a49275457c6 | 1044 | |
| antseggs | 0:5a49275457c6 | 1045 | #define LSM6DS3_G_FS_245 ((uint8_t)0x00) /*!< Full scale: 245 dps*/ |
| antseggs | 0:5a49275457c6 | 1046 | #define LSM6DS3_G_FS_500 ((uint8_t)0x04) /*!< Full scale: 500 dps */ |
| antseggs | 0:5a49275457c6 | 1047 | #define LSM6DS3_G_FS_1000 ((uint8_t)0x08) /*!< Full scale: 1000 dps */ |
| antseggs | 0:5a49275457c6 | 1048 | #define LSM6DS3_G_FS_2000 ((uint8_t)0x0C) /*!< Full scale: 2000 dps */ |
| antseggs | 0:5a49275457c6 | 1049 | |
| antseggs | 0:5a49275457c6 | 1050 | #define LSM6DS3_G_FS_MASK ((uint8_t)0x0C) |
| antseggs | 0:5a49275457c6 | 1051 | |
| antseggs | 0:5a49275457c6 | 1052 | /** |
| antseggs | 0:5a49275457c6 | 1053 | * @} |
| antseggs | 0:5a49275457c6 | 1054 | */ |
| antseggs | 0:5a49275457c6 | 1055 | |
| antseggs | 0:5a49275457c6 | 1056 | |
| antseggs | 0:5a49275457c6 | 1057 | /** @addtogroup LSM6DS3_XG_Gyroscope_Z_Axis_Output_Enable_Selection_CTRL10_C LSM6DS3_XG_Gyroscope_Z_Axis_Output_Enable_Selection_CTRL10_C |
| antseggs | 0:5a49275457c6 | 1058 | * @{ |
| antseggs | 0:5a49275457c6 | 1059 | */ |
| antseggs | 0:5a49275457c6 | 1060 | #define LSM6DS3_G_ZEN_DISABLE ((uint8_t)0x00) /*!< Gyroscope�s Z-axis output enable: disable */ |
| antseggs | 0:5a49275457c6 | 1061 | #define LSM6DS3_G_ZEN_ENABLE ((uint8_t)0x20) /*!< Gyroscope�s Z-axis output enable: enable */ |
| antseggs | 0:5a49275457c6 | 1062 | |
| antseggs | 0:5a49275457c6 | 1063 | #define LSM6DS3_G_ZEN_MASK ((uint8_t)0x20) |
| antseggs | 0:5a49275457c6 | 1064 | |
| antseggs | 0:5a49275457c6 | 1065 | /** |
| antseggs | 0:5a49275457c6 | 1066 | * @} |
| antseggs | 0:5a49275457c6 | 1067 | */ |
| antseggs | 0:5a49275457c6 | 1068 | |
| antseggs | 0:5a49275457c6 | 1069 | |
| antseggs | 0:5a49275457c6 | 1070 | /** @addtogroup LSM6DS3_XG_Gyroscope_Y_Axis_Output_Enable_Selection_CTRL10_C LSM6DS3_XG_Gyroscope_Y_Axis_Output_Enable_Selection_CTRL10_C |
| antseggs | 0:5a49275457c6 | 1071 | * @{ |
| antseggs | 0:5a49275457c6 | 1072 | */ |
| antseggs | 0:5a49275457c6 | 1073 | #define LSM6DS3_G_YEN_DISABLE ((uint8_t)0x00) /*!< Gyroscope�s Y-axis output enable: disable */ |
| antseggs | 0:5a49275457c6 | 1074 | #define LSM6DS3_G_YEN_ENABLE ((uint8_t)0x10) /*!< Gyroscope�s Y-axis output enable: enable */ |
| antseggs | 0:5a49275457c6 | 1075 | |
| antseggs | 0:5a49275457c6 | 1076 | #define LSM6DS3_G_YEN_MASK ((uint8_t)0x10) |
| antseggs | 0:5a49275457c6 | 1077 | |
| antseggs | 0:5a49275457c6 | 1078 | /** |
| antseggs | 0:5a49275457c6 | 1079 | * @} |
| antseggs | 0:5a49275457c6 | 1080 | */ |
| antseggs | 0:5a49275457c6 | 1081 | |
| antseggs | 0:5a49275457c6 | 1082 | |
| antseggs | 0:5a49275457c6 | 1083 | /** @addtogroup LSM6DS3_XG_Gyroscope_X_Axis_Output_Enable_Selection_CTRL10_C LSM6DS3_XG_Gyroscope_X_Axis_Output_Enable_Selection_CTRL10_C |
| antseggs | 0:5a49275457c6 | 1084 | * @{ |
| antseggs | 0:5a49275457c6 | 1085 | */ |
| antseggs | 0:5a49275457c6 | 1086 | #define LSM6DS3_G_XEN_DISABLE ((uint8_t)0x00) /*!< Gyroscope�s X-axis output enable: disable */ |
| antseggs | 0:5a49275457c6 | 1087 | #define LSM6DS3_G_XEN_ENABLE ((uint8_t)0x08) /*!< Gyroscope�s X-axis output enable: enable */ |
| antseggs | 0:5a49275457c6 | 1088 | |
| antseggs | 0:5a49275457c6 | 1089 | #define LSM6DS3_G_XEN_MASK ((uint8_t)0x08) |
| antseggs | 0:5a49275457c6 | 1090 | |
| antseggs | 0:5a49275457c6 | 1091 | /** |
| antseggs | 0:5a49275457c6 | 1092 | * @} |
| antseggs | 0:5a49275457c6 | 1093 | */ |
| antseggs | 0:5a49275457c6 | 1094 | |
| antseggs | 0:5a49275457c6 | 1095 | |
| antseggs | 0:5a49275457c6 | 1096 | /************************************ ACCELEROMETER REGISTERS VALUE *****************************************/ |
| antseggs | 0:5a49275457c6 | 1097 | |
| antseggs | 0:5a49275457c6 | 1098 | /** @addtogroup LSM6DS3_XG_Accelerometer_Output_Data_Rate_Selection_CTRL1_XL LSM6DS3_XG_Accelerometer_Output_Data_Rate_Selection_CTRL1_XL |
| antseggs | 0:5a49275457c6 | 1099 | * @{ |
| antseggs | 0:5a49275457c6 | 1100 | */ |
| antseggs | 0:5a49275457c6 | 1101 | #define LSM6DS3_XL_ODR_PD ((uint8_t)0x00) /*!< Output Data Rate: Power-down*/ |
| antseggs | 0:5a49275457c6 | 1102 | #define LSM6DS3_XL_ODR_13HZ ((uint8_t)0x10) /*!< Output Data Rate: 13 Hz*/ |
| antseggs | 0:5a49275457c6 | 1103 | #define LSM6DS3_XL_ODR_26HZ ((uint8_t)0x20) /*!< Output Data Rate: 26 Hz*/ |
| antseggs | 0:5a49275457c6 | 1104 | #define LSM6DS3_XL_ODR_52HZ ((uint8_t)0x30) /*!< Output Data Rate: 52 Hz */ |
| antseggs | 0:5a49275457c6 | 1105 | #define LSM6DS3_XL_ODR_104HZ ((uint8_t)0x40) /*!< Output Data Rate: 104 Hz */ |
| antseggs | 0:5a49275457c6 | 1106 | #define LSM6DS3_XL_ODR_208HZ ((uint8_t)0x50) /*!< Output Data Rate: 208 Hz */ |
| antseggs | 0:5a49275457c6 | 1107 | #define LSM6DS3_XL_ODR_416HZ ((uint8_t)0x60) /*!< Output Data Rate: 416 Hz */ |
| antseggs | 0:5a49275457c6 | 1108 | #define LSM6DS3_XL_ODR_833HZ ((uint8_t)0x70) /*!< Output Data Rate: 833 Hz */ |
| antseggs | 0:5a49275457c6 | 1109 | #define LSM6DS3_XL_ODR_1660HZ ((uint8_t)0x80) /*!< Output Data Rate: 1.66 kHz */ |
| antseggs | 0:5a49275457c6 | 1110 | #define LSM6DS3_XL_ODR_3330HZ ((uint8_t)0x90) /*!< Output Data Rate: 3.33 kHz */ |
| antseggs | 0:5a49275457c6 | 1111 | #define LSM6DS3_XL_ODR_6660HZ ((uint8_t)0xA0) /*!< Output Data Rate: 6.66 kHz */ |
| antseggs | 0:5a49275457c6 | 1112 | |
| antseggs | 0:5a49275457c6 | 1113 | #define LSM6DS3_XL_ODR_MASK ((uint8_t)0xF0) |
| antseggs | 0:5a49275457c6 | 1114 | |
| antseggs | 0:5a49275457c6 | 1115 | /** |
| antseggs | 0:5a49275457c6 | 1116 | * @} |
| antseggs | 0:5a49275457c6 | 1117 | */ |
| antseggs | 0:5a49275457c6 | 1118 | |
| antseggs | 0:5a49275457c6 | 1119 | |
| antseggs | 0:5a49275457c6 | 1120 | /** @addtogroup LSM6DS3_XG_Accelerometer_Full_Scale_Selection_CTRL1_XL LSM6DS3_XG_Accelerometer_Full_Scale_Selection_CTRL1_XL |
| antseggs | 0:5a49275457c6 | 1121 | * @{ |
| antseggs | 0:5a49275457c6 | 1122 | */ |
| antseggs | 0:5a49275457c6 | 1123 | #define LSM6DS3_XL_FS_2G ((uint8_t)0x00) /*!< Full scale: +- 2g */ |
| antseggs | 0:5a49275457c6 | 1124 | #define LSM6DS3_XL_FS_4G ((uint8_t)0x08) /*!< Full scale: +- 4g */ |
| antseggs | 0:5a49275457c6 | 1125 | #define LSM6DS3_XL_FS_8G ((uint8_t)0x0C) /*!< Full scale: +- 8g */ |
| antseggs | 0:5a49275457c6 | 1126 | #define LSM6DS3_XL_FS_16G ((uint8_t)0x04) /*!< Full scale: +- 16g */ |
| antseggs | 0:5a49275457c6 | 1127 | |
| antseggs | 0:5a49275457c6 | 1128 | #define LSM6DS3_XL_FS_MASK ((uint8_t)0x0C) |
| antseggs | 0:5a49275457c6 | 1129 | |
| antseggs | 0:5a49275457c6 | 1130 | /** |
| antseggs | 0:5a49275457c6 | 1131 | * @} |
| antseggs | 0:5a49275457c6 | 1132 | */ |
| antseggs | 0:5a49275457c6 | 1133 | |
| antseggs | 0:5a49275457c6 | 1134 | |
| antseggs | 0:5a49275457c6 | 1135 | /** @addtogroup LSM6DS3_XG_Accelerometer_Anti_Aliasing_Filter_Bandwidth_Selection_CTRL1_XL LSM6DS3_XG_Accelerometer_Anti_Aliasing_Filter_Bandwidth_Selection_CTRL1_XL |
| antseggs | 0:5a49275457c6 | 1136 | * @{ |
| antseggs | 0:5a49275457c6 | 1137 | */ |
| antseggs | 0:5a49275457c6 | 1138 | #define LSM6DS3_XL_BW_400HZ ((uint8_t)0x00) /*!< Anti-aliasing filter bandwidht: 400 Hz */ |
| antseggs | 0:5a49275457c6 | 1139 | #define LSM6DS3_XL_BW_200HZ ((uint8_t)0x01) /*!< Anti-aliasing filter bandwidht: 200 Hz */ |
| antseggs | 0:5a49275457c6 | 1140 | #define LSM6DS3_XL_BW_100HZ ((uint8_t)0x02) /*!< Anti-aliasing filter bandwidht: 100 Hz */ |
| antseggs | 0:5a49275457c6 | 1141 | #define LSM6DS3_XL_BW_50HZ ((uint8_t)0x03) /*!< Anti-aliasing filter bandwidht: 50 Hz */ |
| antseggs | 0:5a49275457c6 | 1142 | |
| antseggs | 0:5a49275457c6 | 1143 | #define LSM6DS3_XL_BW_MASK ((uint8_t)0x03) |
| antseggs | 0:5a49275457c6 | 1144 | |
| antseggs | 0:5a49275457c6 | 1145 | /** |
| antseggs | 0:5a49275457c6 | 1146 | * @} |
| antseggs | 0:5a49275457c6 | 1147 | */ |
| antseggs | 0:5a49275457c6 | 1148 | |
| antseggs | 0:5a49275457c6 | 1149 | |
| antseggs | 0:5a49275457c6 | 1150 | /** @addtogroup LSM6DS3_XG_Accelerometer_Z_Axis_Output_Enable_Selection_CTRL9_XL LSM6DS3_XG_Accelerometer_Z_Axis_Output_Enable_Selection_CTRL9_XL |
| antseggs | 0:5a49275457c6 | 1151 | * @{ |
| antseggs | 0:5a49275457c6 | 1152 | */ |
| antseggs | 0:5a49275457c6 | 1153 | #define LSM6DS3_XL_ZEN_DISABLE ((uint8_t)0x00) /*!< Accelerometer�s Z-axis output enable: disable */ |
| antseggs | 0:5a49275457c6 | 1154 | #define LSM6DS3_XL_ZEN_ENABLE ((uint8_t)0x20) /*!< Accelerometer�s Z-axis output enable: enable */ |
| antseggs | 0:5a49275457c6 | 1155 | |
| antseggs | 0:5a49275457c6 | 1156 | #define LSM6DS3_XL_ZEN_MASK ((uint8_t)0x20) |
| antseggs | 0:5a49275457c6 | 1157 | |
| antseggs | 0:5a49275457c6 | 1158 | /** |
| antseggs | 0:5a49275457c6 | 1159 | * @} |
| antseggs | 0:5a49275457c6 | 1160 | */ |
| antseggs | 0:5a49275457c6 | 1161 | |
| antseggs | 0:5a49275457c6 | 1162 | |
| antseggs | 0:5a49275457c6 | 1163 | /** @addtogroup LSM6DS3_XG_Accelerometer_Y_Axis_Output_Enable_Selection_CTRL9_XL LSM6DS3_XG_Accelerometer_Y_Axis_Output_Enable_Selection_CTRL9_XL |
| antseggs | 0:5a49275457c6 | 1164 | * @{ |
| antseggs | 0:5a49275457c6 | 1165 | */ |
| antseggs | 0:5a49275457c6 | 1166 | #define LSM6DS3_XL_YEN_DISABLE ((uint8_t)0x00) /*!< Accelerometer�s Y-axis output enable: disable */ |
| antseggs | 0:5a49275457c6 | 1167 | #define LSM6DS3_XL_YEN_ENABLE ((uint8_t)0x10) /*!< Accelerometer�s Y-axis output enable: enable */ |
| antseggs | 0:5a49275457c6 | 1168 | |
| antseggs | 0:5a49275457c6 | 1169 | #define LSM6DS3_XL_YEN_MASK ((uint8_t)0x10) |
| antseggs | 0:5a49275457c6 | 1170 | |
| antseggs | 0:5a49275457c6 | 1171 | /** |
| antseggs | 0:5a49275457c6 | 1172 | * @} |
| antseggs | 0:5a49275457c6 | 1173 | */ |
| antseggs | 0:5a49275457c6 | 1174 | |
| antseggs | 0:5a49275457c6 | 1175 | |
| antseggs | 0:5a49275457c6 | 1176 | /** @addtogroup LSM6DS3_XG_Accelerometer_X_Axis_Output_Enable_Selection_CTRL9_XL LSM6DS3_XG_Accelerometer_X_Axis_Output_Enable_Selection_CTRL9_XL |
| antseggs | 0:5a49275457c6 | 1177 | * @{ |
| antseggs | 0:5a49275457c6 | 1178 | */ |
| antseggs | 0:5a49275457c6 | 1179 | #define LSM6DS3_XL_XEN_DISABLE ((uint8_t)0x00) /*!< Accelerometer�s X-axis output enable: disable */ |
| antseggs | 0:5a49275457c6 | 1180 | #define LSM6DS3_XL_XEN_ENABLE ((uint8_t)0x08) /*!< Accelerometer�s X-axis output enable: enable */ |
| antseggs | 0:5a49275457c6 | 1181 | |
| antseggs | 0:5a49275457c6 | 1182 | #define LSM6DS3_XL_XEN_MASK ((uint8_t)0x08) |
| antseggs | 0:5a49275457c6 | 1183 | |
| antseggs | 0:5a49275457c6 | 1184 | /** |
| antseggs | 0:5a49275457c6 | 1185 | * @} |
| antseggs | 0:5a49275457c6 | 1186 | */ |
| antseggs | 0:5a49275457c6 | 1187 | |
| antseggs | 0:5a49275457c6 | 1188 | /** @addtogroup LSM6DS3_XG_Accelerometer_FF_DUR5_Selection_WAKE_UP_DUR LSM6DS3_XG_Accelerometer_FF_DUR5_Selection_WAKE_UP_DUR |
| antseggs | 0:5a49275457c6 | 1189 | * @{ |
| antseggs | 0:5a49275457c6 | 1190 | */ |
| antseggs | 0:5a49275457c6 | 1191 | #define LSM6DS3_XG_WAKE_UP_DUR_FF_DUR5_DEFAULT ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 1192 | |
| antseggs | 0:5a49275457c6 | 1193 | #define LSM6DS3_XG_WAKE_UP_DUR_FF_DUR5_MASK ((uint8_t)0x80) |
| antseggs | 0:5a49275457c6 | 1194 | /** |
| antseggs | 0:5a49275457c6 | 1195 | * @} |
| antseggs | 0:5a49275457c6 | 1196 | */ |
| antseggs | 0:5a49275457c6 | 1197 | |
| antseggs | 0:5a49275457c6 | 1198 | /** @addtogroup LSM6DS3_XG_Accelerometer_WAKE_DUR_Selection_WAKE_UP_DUR LSM6DS3_XG_Accelerometer_WAKE_DUR_Selection_WAKE_UP_DUR |
| antseggs | 0:5a49275457c6 | 1199 | * @{ |
| antseggs | 0:5a49275457c6 | 1200 | */ |
| antseggs | 0:5a49275457c6 | 1201 | #define LSM6DS3_XG_WAKE_UP_DUR_WAKE_DUR_DEFAULT ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 1202 | |
| antseggs | 0:5a49275457c6 | 1203 | #define LSM6DS3_XG_WAKE_UP_DUR_WAKE_DUR_MASK ((uint8_t)0x60) |
| antseggs | 0:5a49275457c6 | 1204 | /** |
| antseggs | 0:5a49275457c6 | 1205 | * @} |
| antseggs | 0:5a49275457c6 | 1206 | */ |
| antseggs | 0:5a49275457c6 | 1207 | |
| antseggs | 0:5a49275457c6 | 1208 | /** @addtogroup LSM6DS3_XG_Accelerometer_TIMER_HR_Selection_WAKE_UP_DUR LSM6DS3_XG_Accelerometer_TIMER_HR_Selection_WAKE_UP_DUR |
| antseggs | 0:5a49275457c6 | 1209 | * @{ |
| antseggs | 0:5a49275457c6 | 1210 | */ |
| antseggs | 0:5a49275457c6 | 1211 | #define LSM6DS3_XG_WAKE_UP_DUR_TIMER_HR_DEFAULT ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 1212 | |
| antseggs | 0:5a49275457c6 | 1213 | #define LSM6DS3_XG_WAKE_UP_DUR_TIMER_HR_MASK ((uint8_t)0x10) |
| antseggs | 0:5a49275457c6 | 1214 | /** |
| antseggs | 0:5a49275457c6 | 1215 | * @} |
| antseggs | 0:5a49275457c6 | 1216 | */ |
| antseggs | 0:5a49275457c6 | 1217 | |
| antseggs | 0:5a49275457c6 | 1218 | /** @addtogroup LSM6DS3_XG_Accelerometer_SLEEP_DUR_Selection_WAKE_UP_DUR LSM6DS3_XG_Accelerometer_SLEEP_DUR_Selection_WAKE_UP_DUR |
| antseggs | 0:5a49275457c6 | 1219 | * @{ |
| antseggs | 0:5a49275457c6 | 1220 | */ |
| antseggs | 0:5a49275457c6 | 1221 | #define LSM6DS3_XG_WAKE_UP_DUR_SLEEP_DUR_DEFAULT ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 1222 | |
| antseggs | 0:5a49275457c6 | 1223 | #define LSM6DS3_XG_WAKE_UP_DUR_SLEEP_DUR_MASK ((uint8_t)0x0F) |
| antseggs | 0:5a49275457c6 | 1224 | /** |
| antseggs | 0:5a49275457c6 | 1225 | * @} |
| antseggs | 0:5a49275457c6 | 1226 | */ |
| antseggs | 0:5a49275457c6 | 1227 | |
| antseggs | 0:5a49275457c6 | 1228 | /** @addtogroup LSM6DS3_XG_Accelerometer_FF_DUR_Selection_FREE_FALL LSM6DS3_XG_Accelerometer_FF_DUR_Selection_FREE_FALL |
| antseggs | 0:5a49275457c6 | 1229 | * @{ |
| antseggs | 0:5a49275457c6 | 1230 | */ |
| antseggs | 0:5a49275457c6 | 1231 | #define LSM6DS3_XG_WAKE_FREE_FALL_FF_DUR_DEFAULT ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 1232 | #define LSM6DS3_XG_WAKE_FREE_FALL_FF_DUR_TYPICAL ((uint8_t)0x30) |
| antseggs | 0:5a49275457c6 | 1233 | |
| antseggs | 0:5a49275457c6 | 1234 | #define LSM6DS3_XG_WAKE_FREE_FALL_FF_DUR_MASK ((uint8_t)0xF8) |
| antseggs | 0:5a49275457c6 | 1235 | /** |
| antseggs | 0:5a49275457c6 | 1236 | * @} |
| antseggs | 0:5a49275457c6 | 1237 | */ |
| antseggs | 0:5a49275457c6 | 1238 | |
| antseggs | 0:5a49275457c6 | 1239 | /** @addtogroup LSM6DS3_XG_Accelerometer_FF_THS_Selection_FREE_FALL LSM6DS3_XG_Accelerometer_FF_THS_Selection_FREE_FALL |
| antseggs | 0:5a49275457c6 | 1240 | * @{ |
| antseggs | 0:5a49275457c6 | 1241 | */ |
| antseggs | 0:5a49275457c6 | 1242 | #define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_156MG ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 1243 | #define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_219MG ((uint8_t)0x01) |
| antseggs | 0:5a49275457c6 | 1244 | #define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_250MG ((uint8_t)0x02) |
| antseggs | 0:5a49275457c6 | 1245 | #define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_312MG ((uint8_t)0x03) |
| antseggs | 0:5a49275457c6 | 1246 | #define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_344MG ((uint8_t)0x04) |
| antseggs | 0:5a49275457c6 | 1247 | #define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_406MG ((uint8_t)0x05) |
| antseggs | 0:5a49275457c6 | 1248 | #define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_469MG ((uint8_t)0x06) |
| antseggs | 0:5a49275457c6 | 1249 | #define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_500MG ((uint8_t)0x07) |
| antseggs | 0:5a49275457c6 | 1250 | |
| antseggs | 0:5a49275457c6 | 1251 | #define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_MASK ((uint8_t)0x07) |
| antseggs | 0:5a49275457c6 | 1252 | |
| antseggs | 0:5a49275457c6 | 1253 | /** |
| antseggs | 0:5a49275457c6 | 1254 | * @} |
| antseggs | 0:5a49275457c6 | 1255 | */ |
| antseggs | 0:5a49275457c6 | 1256 | |
| antseggs | 0:5a49275457c6 | 1257 | |
| antseggs | 0:5a49275457c6 | 1258 | /** @addtogroup LSM6DS3_XG_Accelerometer_INT1_INACT_STATE_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_INACT_STATE_Selection_MD1_CFG |
| antseggs | 0:5a49275457c6 | 1259 | * @{ |
| antseggs | 0:5a49275457c6 | 1260 | */ |
| antseggs | 0:5a49275457c6 | 1261 | #define LSM6DS3_XG_MD1_CFG_INT1_INACT_STATE_DISABLE ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 1262 | #define LSM6DS3_XG_MD1_CFG_INT1_INACT_STATE_ENABLE ((uint8_t)0x80) |
| antseggs | 0:5a49275457c6 | 1263 | |
| antseggs | 0:5a49275457c6 | 1264 | #define LSM6DS3_XG_MD1_CFG_INT1_INACT_STATE_MASK ((uint8_t)0x80) |
| antseggs | 0:5a49275457c6 | 1265 | /** |
| antseggs | 0:5a49275457c6 | 1266 | * @} |
| antseggs | 0:5a49275457c6 | 1267 | */ |
| antseggs | 0:5a49275457c6 | 1268 | |
| antseggs | 0:5a49275457c6 | 1269 | /** @addtogroup LSM6DS3_XG_Accelerometer_INT1_SINGLE_TAP_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_SINGLE_TAP_Selection_MD1_CFG |
| antseggs | 0:5a49275457c6 | 1270 | * @{ |
| antseggs | 0:5a49275457c6 | 1271 | */ |
| antseggs | 0:5a49275457c6 | 1272 | #define LSM6DS3_XG_MD1_CFG_INT1_SINGLE_TAP_DISABLE ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 1273 | #define LSM6DS3_XG_MD1_CFG_INT1_SINGLE_TAP_ENABLE ((uint8_t)0x40) |
| antseggs | 0:5a49275457c6 | 1274 | |
| antseggs | 0:5a49275457c6 | 1275 | #define LSM6DS3_XG_MD1_CFG_INT1_SINGLE_TAP_MASK ((uint8_t)0x40) |
| antseggs | 0:5a49275457c6 | 1276 | /** |
| antseggs | 0:5a49275457c6 | 1277 | * @} |
| antseggs | 0:5a49275457c6 | 1278 | */ |
| antseggs | 0:5a49275457c6 | 1279 | |
| antseggs | 0:5a49275457c6 | 1280 | /** @addtogroup LSM6DS3_XG_Accelerometer_INT1_WU_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_WU_Selection_MD1_CFG |
| antseggs | 0:5a49275457c6 | 1281 | * @{ |
| antseggs | 0:5a49275457c6 | 1282 | */ |
| antseggs | 0:5a49275457c6 | 1283 | #define LSM6DS3_XG_MD1_CFG_INT1_WU_DISABLE ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 1284 | #define LSM6DS3_XG_MD1_CFG_INT1_WU_ENABLE ((uint8_t)0x20) |
| antseggs | 0:5a49275457c6 | 1285 | |
| antseggs | 0:5a49275457c6 | 1286 | #define LSM6DS3_XG_MD1_CFG_INT1_WU_MASK ((uint8_t)0x20) |
| antseggs | 0:5a49275457c6 | 1287 | /** |
| antseggs | 0:5a49275457c6 | 1288 | * @} |
| antseggs | 0:5a49275457c6 | 1289 | */ |
| antseggs | 0:5a49275457c6 | 1290 | |
| antseggs | 0:5a49275457c6 | 1291 | /** @addtogroup LSM6DS3_XG_Accelerometer_INT1_FF_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_FF_Selection_MD1_CFG |
| antseggs | 0:5a49275457c6 | 1292 | * @{ |
| antseggs | 0:5a49275457c6 | 1293 | */ |
| antseggs | 0:5a49275457c6 | 1294 | #define LSM6DS3_XG_MD1_CFG_INT1_FF_DISABLE ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 1295 | #define LSM6DS3_XG_MD1_CFG_INT1_FF_ENABLE ((uint8_t)0x10) |
| antseggs | 0:5a49275457c6 | 1296 | |
| antseggs | 0:5a49275457c6 | 1297 | #define LSM6DS3_XG_MD1_CFG_INT1_FF_MASK ((uint8_t)0x10) |
| antseggs | 0:5a49275457c6 | 1298 | /** |
| antseggs | 0:5a49275457c6 | 1299 | * @} |
| antseggs | 0:5a49275457c6 | 1300 | */ |
| antseggs | 0:5a49275457c6 | 1301 | |
| antseggs | 0:5a49275457c6 | 1302 | /** @addtogroup LSM6DS3_XG_Accelerometer_INT1_DOUBLE_TAP_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_DOUBLE_TAP_Selection_MD1_CFG |
| antseggs | 0:5a49275457c6 | 1303 | * @{ |
| antseggs | 0:5a49275457c6 | 1304 | */ |
| antseggs | 0:5a49275457c6 | 1305 | #define LSM6DS3_XG_MD1_CFG_INT1_DOUBLE_TAP_DISABLE ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 1306 | #define LSM6DS3_XG_MD1_CFG_INT1_DOUBLE_TAP_ENABLE ((uint8_t)0x08) |
| antseggs | 0:5a49275457c6 | 1307 | |
| antseggs | 0:5a49275457c6 | 1308 | #define LSM6DS3_XG_MD1_CFG_INT1_DOUBLE_TAP_MASK ((uint8_t)0x08) |
| antseggs | 0:5a49275457c6 | 1309 | /** |
| antseggs | 0:5a49275457c6 | 1310 | * @} |
| antseggs | 0:5a49275457c6 | 1311 | */ |
| antseggs | 0:5a49275457c6 | 1312 | |
| antseggs | 0:5a49275457c6 | 1313 | /** @addtogroup LSM6DS3_XG_Accelerometer_INT1_6D_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_6D_Selection_MD1_CFG |
| antseggs | 0:5a49275457c6 | 1314 | * @{ |
| antseggs | 0:5a49275457c6 | 1315 | */ |
| antseggs | 0:5a49275457c6 | 1316 | #define LSM6DS3_XG_MD1_CFG_INT1_6D_DISABLE ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 1317 | #define LSM6DS3_XG_MD1_CFG_INT1_6D_ENABLE ((uint8_t)0x04) |
| antseggs | 0:5a49275457c6 | 1318 | |
| antseggs | 0:5a49275457c6 | 1319 | #define LSM6DS3_XG_MD1_CFG_INT1_6D_MASK ((uint8_t)0x04) |
| antseggs | 0:5a49275457c6 | 1320 | /** |
| antseggs | 0:5a49275457c6 | 1321 | * @} |
| antseggs | 0:5a49275457c6 | 1322 | */ |
| antseggs | 0:5a49275457c6 | 1323 | |
| antseggs | 0:5a49275457c6 | 1324 | /** @addtogroup LSM6DS3_XG_Accelerometer_INT1_TILT_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_TILT_Selection_MD1_CFG |
| antseggs | 0:5a49275457c6 | 1325 | * @{ |
| antseggs | 0:5a49275457c6 | 1326 | */ |
| antseggs | 0:5a49275457c6 | 1327 | #define LSM6DS3_XG_MD1_CFG_INT1_TILT_DISABLE ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 1328 | #define LSM6DS3_XG_MD1_CFG_INT1_TILT_ENABLE ((uint8_t)0x02) |
| antseggs | 0:5a49275457c6 | 1329 | |
| antseggs | 0:5a49275457c6 | 1330 | #define LSM6DS3_XG_MD1_CFG_INT1_TILT_MASK ((uint8_t)0x02) |
| antseggs | 0:5a49275457c6 | 1331 | /** |
| antseggs | 0:5a49275457c6 | 1332 | * @} |
| antseggs | 0:5a49275457c6 | 1333 | */ |
| antseggs | 0:5a49275457c6 | 1334 | |
| antseggs | 0:5a49275457c6 | 1335 | /** @addtogroup LSM6DS3_XG_Accelerometer_INT1_TIMER_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_TIMER_Selection_MD1_CFG |
| antseggs | 0:5a49275457c6 | 1336 | * @{ |
| antseggs | 0:5a49275457c6 | 1337 | */ |
| antseggs | 0:5a49275457c6 | 1338 | #define LSM6DS3_XG_MD1_CFG_INT1_TIMER_DISABLE ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 1339 | #define LSM6DS3_XG_MD1_CFG_INT1_TIMER_ENABLE ((uint8_t)0x01) |
| antseggs | 0:5a49275457c6 | 1340 | |
| antseggs | 0:5a49275457c6 | 1341 | #define LSM6DS3_XG_MD1_CFG_INT1_TIMER_MASK ((uint8_t)0x01) |
| antseggs | 0:5a49275457c6 | 1342 | |
| antseggs | 0:5a49275457c6 | 1343 | /** |
| antseggs | 0:5a49275457c6 | 1344 | * @} |
| antseggs | 0:5a49275457c6 | 1345 | */ |
| antseggs | 0:5a49275457c6 | 1346 | |
| antseggs | 0:5a49275457c6 | 1347 | /** @addtogroup LSM6DS3_XG_Accelerometer_FF_IA_Enable_WAKE_UP_SRC LSM6DS3_XG_Accelerometer_FF_IA_Enable_WAKE_UP_SRC |
| antseggs | 0:5a49275457c6 | 1348 | * @{ |
| antseggs | 0:5a49275457c6 | 1349 | */ |
| antseggs | 0:5a49275457c6 | 1350 | #define LSM6DS3_XG_WAKE_UP_SRC_FF_IA_DISABLE ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 1351 | #define LSM6DS3_XG_WAKE_UP_SRC_FF_IA_ENABLE ((uint8_t)0x20) |
| antseggs | 0:5a49275457c6 | 1352 | |
| antseggs | 0:5a49275457c6 | 1353 | #define LSM6DS3_XG_WAKE_UP_SRC_FF_IA_MASK ((uint8_t)0x20) |
| antseggs | 0:5a49275457c6 | 1354 | /** |
| antseggs | 0:5a49275457c6 | 1355 | * @} |
| antseggs | 0:5a49275457c6 | 1356 | */ |
| antseggs | 0:5a49275457c6 | 1357 | |
| antseggs | 0:5a49275457c6 | 1358 | /** @addtogroup LSM6DS3_XG_Accelerometer_SLEEP_STATE_IA_Enable_WAKE_UP_SRC LSM6DS3_XG_Accelerometer_SLEEP_STATE_IA_Enable_WAKE_UP_SRC |
| antseggs | 0:5a49275457c6 | 1359 | * @{ |
| antseggs | 0:5a49275457c6 | 1360 | */ |
| antseggs | 0:5a49275457c6 | 1361 | #define LSM6DS3_XG_WAKE_UP_SRC_SLEEP_STATE_IA_DISABLE ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 1362 | #define LSM6DS3_XG_WAKE_UP_SRC_SLEEP_STATE_IA_ENABLE ((uint8_t)0x10) |
| antseggs | 0:5a49275457c6 | 1363 | |
| antseggs | 0:5a49275457c6 | 1364 | #define LSM6DS3_XG_WAKE_UP_SRC_SLEEP_STATE_IA_MASK ((uint8_t)0x10) |
| antseggs | 0:5a49275457c6 | 1365 | /** |
| antseggs | 0:5a49275457c6 | 1366 | * @} |
| antseggs | 0:5a49275457c6 | 1367 | */ |
| antseggs | 0:5a49275457c6 | 1368 | |
| antseggs | 0:5a49275457c6 | 1369 | /** @addtogroup LSM6DS3_XG_Accelerometer_WU_IA_Enable_WAKE_UP_SRC LSM6DS3_XG_Accelerometer_WU_IA_Enable_WAKE_UP_SRC |
| antseggs | 0:5a49275457c6 | 1370 | * @{ |
| antseggs | 0:5a49275457c6 | 1371 | */ |
| antseggs | 0:5a49275457c6 | 1372 | #define LSM6DS3_XG_WAKE_UP_SRC_WU_IA_DISABLE ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 1373 | #define LSM6DS3_XG_WAKE_UP_SRC_WU_IA_ENABLE ((uint8_t)0x08) |
| antseggs | 0:5a49275457c6 | 1374 | |
| antseggs | 0:5a49275457c6 | 1375 | #define LSM6DS3_XG_WAKE_UP_SRC_WU_IA_MASK ((uint8_t)0x08) |
| antseggs | 0:5a49275457c6 | 1376 | /** |
| antseggs | 0:5a49275457c6 | 1377 | * @} |
| antseggs | 0:5a49275457c6 | 1378 | */ |
| antseggs | 0:5a49275457c6 | 1379 | |
| antseggs | 0:5a49275457c6 | 1380 | /** @addtogroup LSM6DS3_XG_Accelerometer_X_WU_Enable_WAKE_UP_SRC LSM6DS3_XG_Accelerometer_X_WU_Enable_WAKE_UP_SRC |
| antseggs | 0:5a49275457c6 | 1381 | * @{ |
| antseggs | 0:5a49275457c6 | 1382 | */ |
| antseggs | 0:5a49275457c6 | 1383 | #define LSM6DS3_XG_WAKE_UP_SRC_X_WU_DISABLE ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 1384 | #define LSM6DS3_XG_WAKE_UP_SRC_X_WU_ENABLE ((uint8_t)0x04) |
| antseggs | 0:5a49275457c6 | 1385 | |
| antseggs | 0:5a49275457c6 | 1386 | #define LSM6DS3_XG_WAKE_UP_SRC_X_WU_MASK ((uint8_t)0x04) |
| antseggs | 0:5a49275457c6 | 1387 | /** |
| antseggs | 0:5a49275457c6 | 1388 | * @} |
| antseggs | 0:5a49275457c6 | 1389 | */ |
| antseggs | 0:5a49275457c6 | 1390 | |
| antseggs | 0:5a49275457c6 | 1391 | /** @addtogroup LSM6DS3_XG_Accelerometer_Y_WU_Enable_WAKE_UP_SRC LSM6DS3_XG_Accelerometer_Y_WU_Enable_WAKE_UP_SRC |
| antseggs | 0:5a49275457c6 | 1392 | * @{ |
| antseggs | 0:5a49275457c6 | 1393 | */ |
| antseggs | 0:5a49275457c6 | 1394 | #define LSM6DS3_XG_WAKE_UP_SRC_Y_WU_DISABLE ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 1395 | #define LSM6DS3_XG_WAKE_UP_SRC_Y_WU_ENABLE ((uint8_t)0x02) |
| antseggs | 0:5a49275457c6 | 1396 | |
| antseggs | 0:5a49275457c6 | 1397 | |
| antseggs | 0:5a49275457c6 | 1398 | #define LSM6DS3_XG_WAKE_UP_SRC_Y_WU_MASK ((uint8_t)0x02) |
| antseggs | 0:5a49275457c6 | 1399 | /** |
| antseggs | 0:5a49275457c6 | 1400 | * @} |
| antseggs | 0:5a49275457c6 | 1401 | */ |
| antseggs | 0:5a49275457c6 | 1402 | |
| antseggs | 0:5a49275457c6 | 1403 | /** @addtogroup LSM6DS3_XG_Accelerometer_Z_WU_Enable_WAKE_UP_SRC LSM6DS3_XG_Accelerometer_Z_WU_Enable_WAKE_UP_SRC |
| antseggs | 0:5a49275457c6 | 1404 | * @{ |
| antseggs | 0:5a49275457c6 | 1405 | */ |
| antseggs | 0:5a49275457c6 | 1406 | #define LSM6DS3_XG_WAKE_UP_SRC_Z_WU_DISABLE ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 1407 | #define LSM6DS3_XG_WAKE_UP_SRC_Z_WU_ENABLE ((uint8_t)0x01) |
| antseggs | 0:5a49275457c6 | 1408 | |
| antseggs | 0:5a49275457c6 | 1409 | #define LSM6DS3_XG_WAKE_UP_SRC_Z_WU_MASK ((uint8_t)0x01) |
| antseggs | 0:5a49275457c6 | 1410 | /** |
| antseggs | 0:5a49275457c6 | 1411 | * @} |
| antseggs | 0:5a49275457c6 | 1412 | */ |
| antseggs | 0:5a49275457c6 | 1413 | |
| antseggs | 0:5a49275457c6 | 1414 | /** |
| antseggs | 0:5a49275457c6 | 1415 | * @} |
| antseggs | 0:5a49275457c6 | 1416 | */ |
| antseggs | 0:5a49275457c6 | 1417 | |
| antseggs | 0:5a49275457c6 | 1418 | /** @addtogroup LSM6DS3_Imported_Functions LSM6DS3_Imported_Functions |
| antseggs | 0:5a49275457c6 | 1419 | * @{ |
| antseggs | 0:5a49275457c6 | 1420 | */ |
| antseggs | 0:5a49275457c6 | 1421 | |
| antseggs | 0:5a49275457c6 | 1422 | /* Six axes sensor IO functions */ |
| antseggs | 0:5a49275457c6 | 1423 | extern IMU_6AXES_StatusTypeDef LSM6DS3_IO_Init( void ); |
| antseggs | 0:5a49275457c6 | 1424 | extern IMU_6AXES_StatusTypeDef LSM6DS3_IO_Write( uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, |
| antseggs | 0:5a49275457c6 | 1425 | uint16_t NumByteToWrite ); |
| antseggs | 0:5a49275457c6 | 1426 | extern IMU_6AXES_StatusTypeDef LSM6DS3_IO_Read( uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, |
| antseggs | 0:5a49275457c6 | 1427 | uint16_t NumByteToRead ); |
| antseggs | 0:5a49275457c6 | 1428 | extern void LSM6DS3_IO_ITConfig( void ); |
| antseggs | 0:5a49275457c6 | 1429 | |
| antseggs | 0:5a49275457c6 | 1430 | /** |
| antseggs | 0:5a49275457c6 | 1431 | * @} |
| antseggs | 0:5a49275457c6 | 1432 | */ |
| antseggs | 0:5a49275457c6 | 1433 | |
| antseggs | 0:5a49275457c6 | 1434 | /** @addtogroup LSM6DS3_Exported_Types LSM6DS3_Exported_Types |
| antseggs | 0:5a49275457c6 | 1435 | * @{ |
| antseggs | 0:5a49275457c6 | 1436 | */ |
| antseggs | 0:5a49275457c6 | 1437 | /** |
| antseggs | 0:5a49275457c6 | 1438 | * @brief LSM6DS3 driver extended internal structure definition |
| antseggs | 0:5a49275457c6 | 1439 | */ |
| antseggs | 0:5a49275457c6 | 1440 | typedef struct |
| antseggs | 0:5a49275457c6 | 1441 | { |
| antseggs | 0:5a49275457c6 | 1442 | IMU_6AXES_StatusTypeDef (*Enable_Free_Fall_Detection) (void); |
| antseggs | 0:5a49275457c6 | 1443 | IMU_6AXES_StatusTypeDef (*Disable_Free_Fall_Detection) (void); |
| antseggs | 0:5a49275457c6 | 1444 | IMU_6AXES_StatusTypeDef (*Get_Status_Free_Fall_Detection) (uint8_t *); |
| antseggs | 0:5a49275457c6 | 1445 | } LSM6DS3_DrvExtTypeDef; |
| antseggs | 0:5a49275457c6 | 1446 | |
| antseggs | 0:5a49275457c6 | 1447 | /** |
| antseggs | 0:5a49275457c6 | 1448 | * @} |
| antseggs | 0:5a49275457c6 | 1449 | */ |
| antseggs | 0:5a49275457c6 | 1450 | |
| antseggs | 0:5a49275457c6 | 1451 | /** @addtogroup LSM6DS3_Exported_Variables LSM6DS3_Exported_Variables |
| antseggs | 0:5a49275457c6 | 1452 | * @{ |
| antseggs | 0:5a49275457c6 | 1453 | */ |
| antseggs | 0:5a49275457c6 | 1454 | |
| antseggs | 0:5a49275457c6 | 1455 | /* Six axes sensor driver structure */ |
| antseggs | 0:5a49275457c6 | 1456 | extern IMU_6AXES_DrvTypeDef LSM6DS3Drv; |
| antseggs | 0:5a49275457c6 | 1457 | extern IMU_6AXES_DrvExtTypeDef LSM6DS3Drv_ext; |
| antseggs | 0:5a49275457c6 | 1458 | |
| antseggs | 0:5a49275457c6 | 1459 | /** |
| antseggs | 0:5a49275457c6 | 1460 | * @} |
| antseggs | 0:5a49275457c6 | 1461 | */ |
| antseggs | 0:5a49275457c6 | 1462 | |
| antseggs | 0:5a49275457c6 | 1463 | /** |
| antseggs | 0:5a49275457c6 | 1464 | * @} |
| antseggs | 0:5a49275457c6 | 1465 | */ |
| antseggs | 0:5a49275457c6 | 1466 | |
| antseggs | 0:5a49275457c6 | 1467 | /** |
| antseggs | 0:5a49275457c6 | 1468 | * @} |
| antseggs | 0:5a49275457c6 | 1469 | */ |
| antseggs | 0:5a49275457c6 | 1470 | |
| antseggs | 0:5a49275457c6 | 1471 | /** |
| antseggs | 0:5a49275457c6 | 1472 | * @} |
| antseggs | 0:5a49275457c6 | 1473 | */ |
| antseggs | 0:5a49275457c6 | 1474 | |
| antseggs | 0:5a49275457c6 | 1475 | #ifdef __cplusplus |
| antseggs | 0:5a49275457c6 | 1476 | } |
| antseggs | 0:5a49275457c6 | 1477 | #endif |
| antseggs | 0:5a49275457c6 | 1478 | |
| antseggs | 0:5a49275457c6 | 1479 | #endif /* __LSM6DS3_H */ |
| antseggs | 0:5a49275457c6 | 1480 | |
| antseggs | 0:5a49275457c6 | 1481 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |