Denver / Mbed 2 deprecated denver_train_proj

Denver trai project

Dependencies:   mbed TextLCD

MCP23017.h@33:24ce12dec157, 2018-06-13 (annotated)

Committer:
mglmx
Date:
Wed Jun 13 12:02:48 2018 +0000
Revision:
33:24ce12dec157
New interrupts programmed

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mglmx 33:24ce12dec157 1 /* MCP23017 - drive the Microchip MCP23017 16-bit Port Extender using I2C
mglmx 33:24ce12dec157 2 * Copyright (c) 2010 Wim Huiskamp, Romilly Cocking (original version for SPI)
mglmx 33:24ce12dec157 3 *
mglmx 33:24ce12dec157 4 * Changed by Jacco van Splunter:
mglmx 33:24ce12dec157 5 * The _read and _write functions are moved from protected -> public
mglmx 33:24ce12dec157 6 *
mglmx 33:24ce12dec157 7 * Released under the MIT License: http://mbed.org/license/mit
mglmx 33:24ce12dec157 8 *
mglmx 33:24ce12dec157 9 * version 0.2 Initial Release
mglmx 33:24ce12dec157 10 * version 0.3 Cleaned up
mglmx 33:24ce12dec157 11 * version 0.4 Fixed problem with _read method
mglmx 33:24ce12dec157 12 * version 0.5 Added support for 'Banked' access to registers
mglmx 33:24ce12dec157 13 */
mglmx 33:24ce12dec157 14 #include "mbed.h"
mglmx 33:24ce12dec157 15
mglmx 33:24ce12dec157 16 #ifndef MCP23017_H
mglmx 33:24ce12dec157 17 #define MCP23017_H
mglmx 33:24ce12dec157 18
mglmx 33:24ce12dec157 19 // All register addresses assume IOCON.BANK = 0 (POR default)
mglmx 33:24ce12dec157 20 #define IODIRA 0x00
mglmx 33:24ce12dec157 21 #define IODIRB 0x01
mglmx 33:24ce12dec157 22 #define IPOLA 0x02
mglmx 33:24ce12dec157 23 #define IPOLB 0x03
mglmx 33:24ce12dec157 24 #define GPINTENA 0x04
mglmx 33:24ce12dec157 25 #define GPINTENB 0x05
mglmx 33:24ce12dec157 26 #define DEFVALA 0x06
mglmx 33:24ce12dec157 27 #define DEFVALB 0x07
mglmx 33:24ce12dec157 28 #define INTCONA 0x08
mglmx 33:24ce12dec157 29 #define INTCONB 0x09
mglmx 33:24ce12dec157 30 #define IOCONA 0x0A
mglmx 33:24ce12dec157 31 #define IOCONB 0x0B
mglmx 33:24ce12dec157 32 #define GPPUA 0x0C
mglmx 33:24ce12dec157 33 #define GPPUB 0x0D
mglmx 33:24ce12dec157 34 #define INTFA 0x0E
mglmx 33:24ce12dec157 35 #define INTFB 0x0F
mglmx 33:24ce12dec157 36 #define INTCAPA 0x10
mglmx 33:24ce12dec157 37 #define INTCAPB 0x11
mglmx 33:24ce12dec157 38 #define GPIOA 0x12
mglmx 33:24ce12dec157 39 #define GPIOB 0x13
mglmx 33:24ce12dec157 40 #define OLATA 0x14
mglmx 33:24ce12dec157 41 #define OLATB 0x15
mglmx 33:24ce12dec157 42
mglmx 33:24ce12dec157 43 // The following register addresses assume IOCON.BANK = 1
mglmx 33:24ce12dec157 44 #define IODIRA_BNK 0x00
mglmx 33:24ce12dec157 45 #define IPOLA_BNK 0x01
mglmx 33:24ce12dec157 46 #define GPINTENA_BNK 0x02
mglmx 33:24ce12dec157 47 #define DEFVALA_BNK 0x03
mglmx 33:24ce12dec157 48 #define INTCONA_BNK 0x04
mglmx 33:24ce12dec157 49 #define IOCONA_BNK 0x05
mglmx 33:24ce12dec157 50 #define GPPUA_BNK 0x06
mglmx 33:24ce12dec157 51 #define INTFA_BNK 0x07
mglmx 33:24ce12dec157 52 #define INTCAPA_BNK 0x08
mglmx 33:24ce12dec157 53 #define GPIOA_BNK 0x09
mglmx 33:24ce12dec157 54 #define OLATA_BNK 0x0A
mglmx 33:24ce12dec157 55
mglmx 33:24ce12dec157 56 #define IODIRB_BNK 0x10
mglmx 33:24ce12dec157 57 #define IPOLB_BNK 0x11
mglmx 33:24ce12dec157 58 #define GPINTENB_BNK 0x12
mglmx 33:24ce12dec157 59 #define DEFVALB_BNK 0x13
mglmx 33:24ce12dec157 60 #define INTCONB_BNK 0x14
mglmx 33:24ce12dec157 61 #define IOCONB_BNK 0x15
mglmx 33:24ce12dec157 62 #define GPPUB_BNK 0x16
mglmx 33:24ce12dec157 63 #define INTFB_BNK 0x17
mglmx 33:24ce12dec157 64 #define INTCAPB_BNK 0x18
mglmx 33:24ce12dec157 65 #define GPIOB_BNK 0x19
mglmx 33:24ce12dec157 66 #define OLATB_BNK 0x1A
mglmx 33:24ce12dec157 67
mglmx 33:24ce12dec157 68 // This array allows structured access to Port_A and Port_B registers for both bankModes
mglmx 33:24ce12dec157 69 const int IODIR_AB[2][2] = {{IODIRA, IODIRB}, {IODIRA_BNK, IODIRB_BNK}};
mglmx 33:24ce12dec157 70 const int IPOL_AB[2][2] = {{IPOLA, IPOLB}, {IPOLA_BNK, IPOLB_BNK}};
mglmx 33:24ce12dec157 71 const int GPINTEN_AB[2][2] = {{GPINTENA, GPINTENB}, {GPINTENA_BNK, GPINTENB_BNK}};
mglmx 33:24ce12dec157 72 const int DEFVAL_AB[2][2] = {{DEFVALA, DEFVALB}, {DEFVALA_BNK, DEFVALB_BNK}};
mglmx 33:24ce12dec157 73 const int INTCON_AB[2][2] = {{INTCONA, INTCONB}, {INTCONA_BNK, INTCONB_BNK}};
mglmx 33:24ce12dec157 74 const int IOCON_AB[2][2] = {{IOCONA, IOCONB}, {IOCONA_BNK, IOCONB_BNK}};
mglmx 33:24ce12dec157 75 const int GPPU_AB[2][2] = {{GPPUA, GPPUB}, {GPPUA_BNK, GPPUB_BNK}};
mglmx 33:24ce12dec157 76 const int INTF_AB[2][2] = {{INTFA, INTFB}, {INTFA_BNK, INTFB_BNK}};
mglmx 33:24ce12dec157 77 const int INTCAP_AB[2][2] = {{INTCAPA, INTCAPB}, {INTCAPA_BNK, INTCAPB_BNK}};
mglmx 33:24ce12dec157 78 const int GPIO_AB[2][2] = {{GPIOA, GPIOB}, {GPIOA_BNK, GPIOB_BNK}};
mglmx 33:24ce12dec157 79 const int OLAT_AB[2][2] = {{OLATA, OLATB}, {OLATA_BNK, OLATB_BNK}};
mglmx 33:24ce12dec157 80
mglmx 33:24ce12dec157 81
mglmx 33:24ce12dec157 82 // Control settings
mglmx 33:24ce12dec157 83 #define IOCON_BANK 0x80 // Banked registers for Port A and B
mglmx 33:24ce12dec157 84 #define IOCON_BYTE_MODE 0x20 // Disables sequential operation, Address Ptr does not increment
mglmx 33:24ce12dec157 85 // If Disabled and Bank = 0, operations toggle between Port A and B registers
mglmx 33:24ce12dec157 86 // If Disabled and Bank = 1, operations do not increment registeraddress
mglmx 33:24ce12dec157 87 #define IOCON_HAEN 0x08 // Hardware address enable
mglmx 33:24ce12dec157 88
mglmx 33:24ce12dec157 89 #define INTERRUPT_POLARITY_BIT 0x02
mglmx 33:24ce12dec157 90 #define INTERRUPT_MIRROR_BIT 0x40
mglmx 33:24ce12dec157 91
mglmx 33:24ce12dec157 92 #define PORT_DIR_OUT 0x00
mglmx 33:24ce12dec157 93 #define PORT_DIR_IN 0xFF
mglmx 33:24ce12dec157 94
mglmx 33:24ce12dec157 95 enum Polarity { ACTIVE_LOW , ACTIVE_HIGH };
mglmx 33:24ce12dec157 96 enum Port { PORT_A=0, PORT_B=1 };
mglmx 33:24ce12dec157 97 enum Bank { NOT_BNK=0, BNK=1 };
mglmx 33:24ce12dec157 98
mglmx 33:24ce12dec157 99 class MCP23017 {
mglmx 33:24ce12dec157 100 public:
mglmx 33:24ce12dec157 101 /** Create an MCP23017 object connected to the specified I2C object and using the specified deviceAddress
mglmx 33:24ce12dec157 102 *
mglmx 33:24ce12dec157 103 * @param I2C &i2c the I2C port to connect to
mglmx 33:24ce12dec157 104 * @param char deviceAddress the address of the MCP23017
mglmx 33:24ce12dec157 105 */
mglmx 33:24ce12dec157 106 MCP23017(I2C &i2c, char deviceAddress);
mglmx 33:24ce12dec157 107
mglmx 33:24ce12dec157 108 /** Set I/O direction of specified MCP23017 Port
mglmx 33:24ce12dec157 109 *
mglmx 33:24ce12dec157 110 * @param Port Port address (Port_A or Port_B)
mglmx 33:24ce12dec157 111 * @param char direction pin direction (0 = output, 1 = input)
mglmx 33:24ce12dec157 112 */
mglmx 33:24ce12dec157 113 void direction(Port port, char direction);
mglmx 33:24ce12dec157 114
mglmx 33:24ce12dec157 115 /** Set Pull-Up Resistors on specified MCP23017 Port
mglmx 33:24ce12dec157 116 *
mglmx 33:24ce12dec157 117 * @param Port Port address (Port_A or Port_B)
mglmx 33:24ce12dec157 118 * @param char offOrOn per pin (0 = off, 1 = on)
mglmx 33:24ce12dec157 119 */
mglmx 33:24ce12dec157 120 void configurePullUps(Port port, char offOrOn);
mglmx 33:24ce12dec157 121
mglmx 33:24ce12dec157 122 void configureBanked(Bank bankmode);
mglmx 33:24ce12dec157 123 void interruptEnable(Port port, char interruptsEnabledMask);
mglmx 33:24ce12dec157 124 void interruptPolarity(Polarity polarity);
mglmx 33:24ce12dec157 125 void mirrorInterrupts(bool mirror);
mglmx 33:24ce12dec157 126 void defaultValue(Port port, char valuesToCompare);
mglmx 33:24ce12dec157 127 void interruptControl(Port port, char interruptControlBits);
mglmx 33:24ce12dec157 128
mglmx 33:24ce12dec157 129 /** Read from specified MCP23017 Port
mglmx 33:24ce12dec157 130 *
mglmx 33:24ce12dec157 131 * @param Port Port address (Port_A or Port_B)
mglmx 33:24ce12dec157 132 * @returns data from Port
mglmx 33:24ce12dec157 133 */
mglmx 33:24ce12dec157 134 char read(Port port);
mglmx 33:24ce12dec157 135
mglmx 33:24ce12dec157 136 /** Write to specified MCP23017 Port
mglmx 33:24ce12dec157 137 *
mglmx 33:24ce12dec157 138 * @param Port Port address (Port_A or Port_B)
mglmx 33:24ce12dec157 139 * @param char byte data to write
mglmx 33:24ce12dec157 140 */
mglmx 33:24ce12dec157 141 void write(Port port, char byte);
mglmx 33:24ce12dec157 142
mglmx 33:24ce12dec157 143 /** Write to specified MCP23017 register
mglmx 33:24ce12dec157 144 *
mglmx 33:24ce12dec157 145 * @param char address the internal registeraddress of the MCP23017
mglmx 33:24ce12dec157 146 */
mglmx 33:24ce12dec157 147 void _write(char address, char byte);
mglmx 33:24ce12dec157 148
mglmx 33:24ce12dec157 149 /** Read from specified MCP23017 register
mglmx 33:24ce12dec157 150 *
mglmx 33:24ce12dec157 151 * @param char address the internal registeraddress of the MCP23017
mglmx 33:24ce12dec157 152 * @returns data from register
mglmx 33:24ce12dec157 153 */
mglmx 33:24ce12dec157 154 char _read(char address);
mglmx 33:24ce12dec157 155
mglmx 33:24ce12dec157 156 protected:
mglmx 33:24ce12dec157 157 I2C &_i2c;
mglmx 33:24ce12dec157 158 char _readOpcode;
mglmx 33:24ce12dec157 159 char _writeOpcode;
mglmx 33:24ce12dec157 160 Bank _bankMode;
mglmx 33:24ce12dec157 161
mglmx 33:24ce12dec157 162 /** Init MCP23017
mglmx 33:24ce12dec157 163 *
mglmx 33:24ce12dec157 164 * @param
mglmx 33:24ce12dec157 165 * @returns
mglmx 33:24ce12dec157 166 */
mglmx 33:24ce12dec157 167 void _init();
mglmx 33:24ce12dec157 168 };
mglmx 33:24ce12dec157 169
mglmx 33:24ce12dec157 170 #endif