Delta / AM1805_DEMO

Demo the function of RTC module AM1805

Dependencies:   mbed-dev

Fork of I2C_HelloWorld_Mbed by mbed official

AM1805.h@2:16b8f527b5c7, 2015-12-24 (annotated)

Committer:
marcusC
Date:
Thu Dec 24 05:15:42 2015 +0000
Revision:
2:16b8f527b5c7
Parent:
1:c45df8c46fa8 
Remove the redundant log

Who changed what in which revision?

UserRevisionLine numberNew contents of line
marcusC 1:c45df8c46fa8 1 /* AM1805.h , AM1805 Sample code: external RTC module is used by host MCU */
marcusC 1:c45df8c46fa8 2
marcusC 1:c45df8c46fa8 3 typedef struct
marcusC 1:c45df8c46fa8 4 {
marcusC 1:c45df8c46fa8 5 uint8_t hundredth;
marcusC 1:c45df8c46fa8 6 uint8_t second;
marcusC 1:c45df8c46fa8 7 uint8_t minute;
marcusC 1:c45df8c46fa8 8 uint8_t hour;
marcusC 1:c45df8c46fa8 9 uint8_t date;
marcusC 1:c45df8c46fa8 10 uint8_t weekday;
marcusC 1:c45df8c46fa8 11 uint8_t month;
marcusC 1:c45df8c46fa8 12 uint8_t year;
marcusC 1:c45df8c46fa8 13 uint8_t century;
marcusC 1:c45df8c46fa8 14 uint8_t mode;
marcusC 1:c45df8c46fa8 15 } time_reg_struct_t;
marcusC 1:c45df8c46fa8 16
marcusC 1:c45df8c46fa8 17 typedef enum
marcusC 1:c45df8c46fa8 18 {
marcusC 1:c45df8c46fa8 19 XT1_INTERRUPT = 0x01, /**< WDI input pin will generate XT1 interrupt */
marcusC 1:c45df8c46fa8 20 XT2_INTERRUPT = 0x02 /**< EXTI input pin will generate XT2 interrupt */
marcusC 1:c45df8c46fa8 21 } input_interrupt_t;
marcusC 1:c45df8c46fa8 22
marcusC 1:c45df8c46fa8 23 typedef enum
marcusC 1:c45df8c46fa8 24 {
marcusC 1:c45df8c46fa8 25 DISABLE_ALARM = 0, /**< disable alarm */
marcusC 1:c45df8c46fa8 26 ONCE_PER_YEAR = 1, /**< once per year */
marcusC 1:c45df8c46fa8 27 ONCE_PER_MONTH = 2, /**< once per month */
marcusC 1:c45df8c46fa8 28 ONCE_PER_WEEK = 3, /**< once per week */
marcusC 1:c45df8c46fa8 29 ONCE_PER_DAY = 4, /**< once per day */
marcusC 1:c45df8c46fa8 30 ONCE_PER_HOUR = 5, /**< once per hour */
marcusC 1:c45df8c46fa8 31 ONCE_PER_MINUTE = 6, /**< once per minute */
marcusC 1:c45df8c46fa8 32 ONCE_PER_SECOND = 7, /**< once per second */
marcusC 1:c45df8c46fa8 33 ONCE_PER_10TH_SEC = 8, /**< once per 10th of a second */
marcusC 1:c45df8c46fa8 34 ONCE_PER_100TH_SEC = 9 /**< once per 100th of a second */
marcusC 1:c45df8c46fa8 35 } alarm_repeat_t;
marcusC 1:c45df8c46fa8 36
marcusC 1:c45df8c46fa8 37 typedef enum
marcusC 1:c45df8c46fa8 38 {
marcusC 1:c45df8c46fa8 39 PERIOD_US = 0, /**< period in us */
marcusC 1:c45df8c46fa8 40 PERIOD_SEC = 1 /**< period in seconds */
marcusC 1:c45df8c46fa8 41 } count_down_range_t;
marcusC 1:c45df8c46fa8 42
marcusC 1:c45df8c46fa8 43 typedef enum
marcusC 1:c45df8c46fa8 44 {
marcusC 1:c45df8c46fa8 45 SINGLE_LEVEL_INTERRUPT = 0, /**< single level interrupt */
marcusC 1:c45df8c46fa8 46 REPEAT_PULSE_1_4096_SEC = 1, /**< a repeated pulsed interrupt, 1/4096 s (XT mode), 1/128 s (RC mode) (range must be 0) */
marcusC 1:c45df8c46fa8 47 SINGLE_PULSE_1_4096_SEC = 2, /**< a single pulsed interrupt, 1/4096 s (XT mode), 1/128 s (RC mode) (range must be 0) */
marcusC 1:c45df8c46fa8 48 REPEAT_PLUSE_1_128_SEC = 3, /**< a repeated pulsed interrupt, 1/128 s (range must be 0) */
marcusC 1:c45df8c46fa8 49 SINGLE_PLUSE_1_128_SEC = 4, /**< a single pulsed interrupt, 1/128 s (range must be 0) */
marcusC 1:c45df8c46fa8 50 REPEAT_PLUSE_1_64_SEC = 5, /**< a repeated pulsed interrupt, 1/64 s (range must be 1) */
marcusC 1:c45df8c46fa8 51 SINGLE_PLUSE_1_64_SEC = 6 /**< a single pulsed interrupt, 1/64 s (range must be 1) */
marcusC 1:c45df8c46fa8 52 } count_down_repeat_t;
marcusC 1:c45df8c46fa8 53
marcusC 1:c45df8c46fa8 54 typedef enum
marcusC 1:c45df8c46fa8 55 {
marcusC 1:c45df8c46fa8 56 LEVEL_INTERRUPT = 0x00, /**< level interrupt */
marcusC 1:c45df8c46fa8 57 PULSE_1_8192_SEC = 0x01, /**< pulse of 1/8192s (XT) or 1/128 s (RC) */
marcusC 1:c45df8c46fa8 58 PULSE_1_64_SEC = 0x10, /**< pulse of 1/64 s */
marcusC 1:c45df8c46fa8 59 PULSE_1_4_SEC = 0x11 /**< pulse of 1/4 s */
marcusC 1:c45df8c46fa8 60 } interrupt_mode_t;
marcusC 1:c45df8c46fa8 61
marcusC 1:c45df8c46fa8 62 typedef enum
marcusC 1:c45df8c46fa8 63 {
marcusC 1:c45df8c46fa8 64 INTERNAL_FLAG = 0, /**< internal flag only */
marcusC 1:c45df8c46fa8 65 PIN_FOUT_nIRQ = 1, /**< generate the interrupt on FOUT/nIRQ */
marcusC 1:c45df8c46fa8 66 PIN_PSW_nIRQ2 = 2, /**< generate the interrupt on PSW/nIRQ2 */
marcusC 1:c45df8c46fa8 67 PIN_nTIRQ = 3 /**< generate the interrupt on nTIRQ (not apply to ALARM) */
marcusC 1:c45df8c46fa8 68 } interrupt_pin_t;
marcusC 1:c45df8c46fa8 69
marcusC 1:c45df8c46fa8 70 bool am1805_init(void);
marcusC 1:c45df8c46fa8 71
marcusC 1:c45df8c46fa8 72 void am1805_register_read(char register_address, char *destination, uint8_t number_of_bytes);
marcusC 1:c45df8c46fa8 73
marcusC 1:c45df8c46fa8 74 void am1805_register_write(char register_address, uint8_t value);
marcusC 1:c45df8c46fa8 75
marcusC 1:c45df8c46fa8 76 void am1805_burst_write(uint8_t *value, uint8_t number_of_bytes);
marcusC 1:c45df8c46fa8 77
marcusC 1:c45df8c46fa8 78 uint8_t am1805_read_ram(uint8_t address);
marcusC 1:c45df8c46fa8 79
marcusC 1:c45df8c46fa8 80 void am1805_write_ram(uint8_t address, uint8_t data);
marcusC 1:c45df8c46fa8 81
marcusC 1:c45df8c46fa8 82 void am1805_config_input_interrupt(input_interrupt_t index_Interrupt);
marcusC 1:c45df8c46fa8 83
marcusC 1:c45df8c46fa8 84 void am1805_set_time(time_reg_struct_t time_regs);
marcusC 1:c45df8c46fa8 85
marcusC 1:c45df8c46fa8 86 void am1805_get_time(time_reg_struct_t *time_regs);
marcusC 1:c45df8c46fa8 87
marcusC 1:c45df8c46fa8 88 void am1805_config_alarm(time_reg_struct_t time_regs, alarm_repeat_t repeat, interrupt_mode_t intmode, interrupt_pin_t pin);
marcusC 1:c45df8c46fa8 89
marcusC 1:c45df8c46fa8 90 void am1805_config_countdown_timer(count_down_range_t range, int32_t period, count_down_repeat_t repeat, interrupt_pin_t pin);
marcusC 1:c45df8c46fa8 91
marcusC 1:c45df8c46fa8 92 void am1805_set_sleep(uint8_t timeout, uint8_t mode);