DeepPass
AT Command Set mDot firmware with updated libmDot, to fix endian problem with joining LoRaWAN network
Dependencies: MTS-Serial libmDot mbed-rtos mbed-src
Fork of
mDot_AT_firmware
by 
MultiTech
Revision 0:e2b8246361bc, committed 2015-06-25
- Comitter:
- mfiore
- Date:
- Thu Jun 25 14:52:56 2015 +0000
- Child:
- 1:e52ae6584f1c
- Commit message:
- initial commit, main, debug, version, wakeup, doc
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/MTS-Serial.lib Thu Jun 25 14:52:56 2015 +0000 @@ -0,0 +1,1 @@ +http://developer.mbed.org/teams/MultiTech/code/MTS-Serial/#4afbbafcd6b3
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/debug.h Thu Jun 25 14:52:56 2015 +0000
@@ -0,0 +1,12 @@
+#include "mbed.h"
+#include <stdio.h>
+
+// enable to turn on debug prints
+#define DEBUG_MAC 1
+
+#ifdef DEBUG_MAC
+ #define MTS_RADIO_DEBUG_COMMANDS 1
+ #define DEBUG_PRINTF(fmt, args...) printf("%s:%d: "fmt, __FUNCTION__, __LINE__, ## args)
+#else
+ #define DEBUG_PRINTF(fmt, args...)
+#endif
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/doc/mdot-at-commands.txt Thu Jun 25 14:52:56 2015 +0000 @@ -0,0 +1,79 @@ +# vim: expandtab sts=8 sw=8 ts=8 +Command Name Description + +General commands +---------------- +Command Name Description + +AT Attention Attention +ATI Request Id Request Identification +ATZ Reset CPU Reset the CPU +ATE0/1 Enable/Disable Echo ATE0: disable, ATE1: enable +ATV0/1 Enable/Disable Verbose ATV0: disable, ATV1: enable +AT&F Reset Factory Defaults Reset current configuration to factory defaults +AT&W Save Configuration Save configuration to flash memory +AT&V Display Settings Displays current settings and status +AT+IPR Serial Baud Rate Set serial baud rate, default: 115200 +AT+DIPR Debug Baud Rate Set debug serial baud rate, default: 115200 +AT+SMODE Start Up Mode 0: AT command mode, 1: Serial data mode +AT+LOG Debug Log Level Enable/disable debug logging. (0: off, 1:Fatal - 6:Trace) + +Network/Addressing commands +--------------------------- + +AT+FREQ Frequency Band Configured Frequency Band '868' or '915' +AT+FSB Frequency Sub-band Set the frequency sub-band for US 915, (0:ALL, 1-8) +AT+PN Public Network Enable/disable public network mode. (0: off, 1: on) +AT+DI Device ID Device EUI (unique, set at factory) (8 bytes) +AT+NA Network Address Network address (devAddr in LoraMac) (4 bytes) +AT+NSK Network Session Key Network session encryption key (16 bytes) +AT+DSK Data Session Key Data session encryption key (16 bytes) +AT+NK Network Key Configured network key/passphrase (App Key in LoraMac) ## AT+NK=0,hex AT+NK=1,passphrase (Net key = cmac(passphrase)) (16 bytes) +AT+NI Network ID Configured Network EUI/Name (App EUI in LoraMac) AT+NI=0,hex AT+NI=1,network_name (Net ID = crc64(network_name)) (8 bytes) +AT+JOIN Join Network Join network (acquire network address and session keys) +AT+NJM Network Join Mode 0: Manual configuration, 1: OTA Network Join, 2: Auto OTA Network Join on start up (default: 1) +AT+NJS Network Join Status 0: Not joined, 1: Joined +AT+NLC Network Link Check Perform network link check, displays dBm above floor, number of gateways in range and optional packet payload if received +AT+LCC Link Check Count Set number of packets between each link check if ACK's are disabled +AT+ENC AES Encryption Enable/disable AES encryption (0: off, 1: on) +AT+RSSI Signal Strength Displays signal strength of received packets, last,min,max,avg +AT+SNR Signal To Noise Ratio Display signal to noise ratio received packets last,min,max,avg +AT+DP Data Pending Indicator of data in queue on server +AT+PING Send Ping Sends ping, displays RSSI and SNR from gateway on pong + +Radio Configuration +------------------- + +AT+TXDR Tx Data Rate Set the Tx data rate for all channels +AT+TXP Tx Power Set the Tx power for all channels +AT+TXF Tx Frequency Set Tx frequency +AT+TXI Set Tx inverted Set Tx signal inverted, (default:off) +AT+TXCH Tx Channels List Tx channel frequencies for sub-band +AT+RXDR Rx Data Rate Set the Rx data rate +AT+RXF Rx Frequency Set the Rx frequency for +RECV,+RECVC +AT+RXO Rx Output Set the Rx output type (0:hexadecimal, 1:binary) +AT+RXI Set Rx inverted Set Rx signal inverted, (default:on) +AT+FEC Error Correction Configure Forward Error Correction bytes (1 to 4) +AT+CRC CRC Checking Enable/disable CRC checking of received packets. (0: off, 1: on) +AT+ADR Adaptive Data Rate Enable/disable Adaptive Data Rate (0: off, 1: on) + + +Send/Receive +------------ + +AT+ACK Require ACK Enable to require send acknowledgement (0: off, N: number of retries until ACK recevied) +AT+SEND Send Once Sends supplied packet data one time and return response, (max:240 bytes) +AT+SENDH Send Once High BW Sends supplied packet data one time and return response using High Bandwidth channel, (max:240 bytes) +AT+SENDB Send Binary Sends supplied binary (hex) packet data one time and return response +AT+SENDI Send Continuous Sends supplied packet data on interval between sends, output any recevied packets (escape sequence: +++) +AT+RECV Receive Once Receive and display one packet, optional timeout in ms overrides configured Rx Timeout. +AT+RECVC Receive Continuous Continously receive and display packets, optional timeout in ms overrides configured Rx Timeout. (escape sequence: +++) +AT+TXN Tx Next Get time in ms until next free channel + +Serial data mode options +------------------------ + +AT+SD Serial Data Mode Reads serial data and sends Lora packets (escape sequence: +++) +AT+SDWI Serial Wake Interval Serial data wakeup interval to generate wake signal (seconds) +AT+SDWD Serial Wake Delay Time to wait for data after wakeup signal (milliseconds) +AT+SDTO Serial Receive Timeout Read serial data until timeout (milliseconds)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/libmDot.lib Thu Jun 25 14:52:56 2015 +0000 @@ -0,0 +1,1 @@ +http://developer.mbed.org/teams/MultiTech/code/libmDot/#5e805b567124
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/main.cpp Thu Jun 25 14:52:56 2015 +0000
@@ -0,0 +1,29 @@
+#include "mbed.h"
+#include "mDot.h"
+#include "CommandTerminal.h"
+
+Serial debug(USBTX, USBRX);
+
+mts::MTSSerial serial(XBEE_DOUT, XBEE_DIN, 512, 512);
+DigitalOut led(LED1);
+Ticker tick;
+
+void tock() {
+ led = !led;
+}
+
+int main()
+{
+ debug.baud(115200);
+
+ tick.attach(&tock, 0.5);
+
+ mDot* dot = mDot::getInstance();
+
+ debug.baud(dot->getDebugBaud());
+ serial.baud(dot->getBaud());
+
+ CommandTerminal term(serial, dot);
+
+ term.start();
+}
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-rtos.lib Thu Jun 25 14:52:56 2015 +0000 @@ -0,0 +1,1 @@ +http://mbed.org/users/mbed_official/code/mbed-rtos/#ef0a22cdf839
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-src.lib Thu Jun 25 14:52:56 2015 +0000 @@ -0,0 +1,1 @@ +http://mbed.org/users/mbed_official/code/mbed-src/#30f9462b5296
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/version.h Thu Jun 25 14:52:56 2015 +0000 @@ -0,0 +1,6 @@ +#ifndef __VERSION_H__ +#define __VERSION_H__ + +#define AT_APPLICATION_VERSION "060215_mbed-19-gdadc7ac" + +#endif \ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/wakeup.c Thu Jun 25 14:52:56 2015 +0000
@@ -0,0 +1,153 @@
+#include "stm32f4xx_hal.h"
+#include "wakeup.h"
+
+
+static int rtc_inited = 0;
+static uint32_t timeout = 10;
+
+uint32_t wakeup_init(uint32_t seconds) {
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ uint32_t rtc_freq = 0;
+
+ if (rtc_inited) {
+ if (timeout != seconds) {
+ timeout = seconds;
+ HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, timeout, RTC_WAKEUPCLOCK_CK_SPRE_16BITS);
+ }
+ return 0;
+ }
+ rtc_inited = 1;
+
+ RtcHandle.Instance = RTC;
+
+ // Enable Power clock
+ __PWR_CLK_ENABLE();
+
+ // Enable access to Backup domain
+ HAL_PWR_EnableBkUpAccess();
+
+ uint32_t count = RTC_ReadBackupRegister(RTC_BKP_DR0);
+ printf("UPLINK: %lu\r\n", count);
+
+
+ // Reset Backup domain
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+
+ // Enable LSE Oscillator
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; /* Mandatory, otherwise the PLL is reconfigured! */
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON; /* External 32.768 kHz clock on OSC_IN/OSC_OUT */
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+ // Connect LSE to RTC
+ __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE);
+ __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
+ rtc_freq = LSE_VALUE;
+ } else {
+ // Enable LSI clock
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
+ RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ //error("RTC error: LSI clock initialization failed.");
+ }
+ // Connect LSI to RTC
+ __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI);
+ __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
+ // [TODO] This value is LSI typical value. To be measured precisely using a timer input capture
+ rtc_freq = 32000;
+ }
+
+ // Enable RTC
+ __HAL_RCC_RTC_ENABLE();
+
+ RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24;
+ RtcHandle.Init.AsynchPrediv = 127;
+ RtcHandle.Init.SynchPrediv = (rtc_freq / 128) - 1;
+ RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE;
+ RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+ RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+
+ if (HAL_RTC_Init(&RtcHandle) != HAL_OK) {
+ //error("RTC error: RTC initialization failed.");
+ }
+
+ timeout = seconds;
+ HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, timeout, RTC_WAKEUPCLOCK_CK_SPRE_16BITS);
+
+ return count;
+}
+
+void wakeup_clear(void)
+{
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&RtcHandle, RTC_FLAG_WUTF);
+}
+
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)
+{
+ __IO uint32_t tmp = 0;
+
+ // Check the parameters
+ assert_param(IS_RTC_BKP(RTC_BKP_DR));
+ tmp = RTC_BASE + 0x50;
+ tmp += (RTC_BKP_DR * 4);
+ // Read the specified register
+ return (*(__IO uint32_t *)tmp);
+}
+
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ // Check the parameters/
+ assert_param(IS_RTC_BKP(RTC_BKP_DR));
+ tmp = RTC_BASE + 0x50;
+ tmp += (RTC_BKP_DR * 4);
+ // Write the specified register/
+ *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+
+uint8_t TM_WATCHDOG_Init(uint16_t reload) {
+ uint8_t result = 0;
+
+ /* Check if the system has resumed from IWDG reset */
+ if (RCC->CSR & (0x20000000)) {
+ /* Reset by IWDG */
+ result = 1;
+
+ /* Clear reset flags */
+ RCC->CSR |= RCC_CSR_RMVF;
+ }
+
+ /* Enable write access to IWDG_PR and IWDG_RLR registers */
+ IWDG->KR = 0x5555;
+
+ /* IWDG counter clock: LSI/32 = 1024Hz */
+ IWDG->PR = 0x03;
+
+ reload = 4095;
+
+ printf("WATCHDOG RELOAD: %lu\r\n", reload);
+ /* Set reload */
+ IWDG->RLR = reload;
+
+ /* Reload IWDG counter */
+ IWDG->KR = 0xAAAA;
+
+ /* Enable IWDG (the LSI oscillator will be enabled by hardware) */
+ IWDG->KR = 0xCCCC;
+
+ /* Return status */
+ return result;
+}
+
+void TM_WATCHDOG_Disable(void) {
+ IWDG->KR = 0x0000;
+}
+
+void TM_WATCHDOG_Reset(void) {
+ /* Reload IWDG counter */
+ IWDG->KR = 0xAAAA;
+}
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/wakeup.h Thu Jun 25 14:52:56 2015 +0000
@@ -0,0 +1,114 @@
+#ifndef __WAKEUP_H__
+#define __WAKEUP_H__
+
+#include <inttypes.h>
+
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
+
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
+
+static RTC_HandleTypeDef RtcHandle;
+
+uint32_t wakeup_init(uint32_t seconds);
+
+void wakeup_clear(void);
+
+
+#ifndef TM_WATCHDOG_H
+#define TM_WATCHDOG_H 110
+/**
+ * * @addtogroup TM_STM32F4xx_Libraries
+ * * @{
+ * */
+
+/**
+ * * @defgroup TM_WATCHDOG
+ * * @brief Independent Watchdog timer for STM32F4xx - http://stm32f4-discovery.com/2014/07/library-20-independent-watchdog-timer-on-stm32f4xx/
+ * * @{
+ * *
+ * * \par Changelog
+ * *
+ * @verbatim
+ * Version 1.1
+ * - March 10, 2015
+ * - Support for STD/HAL drivers
+ * Version 1.0
+ * - First release
+ * @endverbatim
+ * *
+ * * \par Dependencies
+ * *
+ * @verbatim
+ * - STM32F4xx
+ * - defines.h
+ * @endverbatim
+ * */
+
+/**
+ * * @defgroup TM_WATCHDOG_Typedefs
+ * * @brief Library Typedefs
+ * * @{
+ * */
+
+/**
+ * * @brief Watchdog timeout settings
+ * */
+typedef enum {
+ TM_WATCHDOG_Timeout_5ms, /*!< System reset called every 5ms */
+ TM_WATCHDOG_Timeout_10ms, /*!< System reset called every 10ms */
+ TM_WATCHDOG_Timeout_15ms, /*!< System reset called every 15ms */
+ TM_WATCHDOG_Timeout_30ms, /*!< System reset called every 30ms */
+ TM_WATCHDOG_Timeout_60ms, /*!< System reset called every 60ms */
+ TM_WATCHDOG_Timeout_120ms, /*!< System reset called every 120ms */
+ TM_WATCHDOG_Timeout_250ms, /*!< System reset called every 250ms */
+ TM_WATCHDOG_Timeout_500ms, /*!< System reset called every 500ms */
+ TM_WATCHDOG_Timeout_1s, /*!< System reset called every 1s */
+ TM_WATCHDOG_Timeout_2s, /*!< System reset called every 2s */
+ TM_WATCHDOG_Timeout_4s /*!< System reset called every 4s */
+} TM_WATCHDOG_Timeout_t;
+
+/**
+ * * @}
+ * */
+
+/**
+ * * @defgroup TM_WATCHDOG_Functions
+ * * @brief Library Functions
+ * * @{
+ * */
+
+/**
+ * * @brief Initialize Watchdog timer
+ * * @note After you initialize it, you can't disable it unless reset occur.
+ * * @param timeout. Timeout value when watchdog reset happen if not reset by user.
+ * * This parameter can be a value of @ref TM_WATCHDOG_Timeout_t enumeration
+ * * @retval Value if system was reset because of watchdog timer
+ * * - 1: Reset happen because of watchdog
+ * * - 0: Otherwise
+ * *
+ * */
+uint8_t TM_WATCHDOG_Init(uint16_t reloa);
+
+/**
+ * * @brief Reset Watchdog timer
+ * * @note This function have to be called periodically to reset watchdog timer, or your system will reset
+ * * @param None
+ * * @retval None
+ * */
+void TM_WATCHDOG_Reset(void);
+
+/**
+ * * @}
+ * */
+
+/**
+ * * @}
+ * */
+
+/**
+ * * @}
+ * */
+
+#endif
+
+#endif // __WAKEUP_H__
\ No newline at end of file