DeepPass / mDot_AT_firmware

AT Command Set mDot firmware with updated libmDot, to fix endian problem with joining LoRaWAN network

Dependencies:   MTS-Serial libmDot mbed-rtos mbed-src

Fork of mDot_AT_firmware by MultiTech

wakeup.c@3:321cf5e5b89b, 2015-08-07 (annotated)

Committer:
ruairisdad
Date:
Fri Aug 07 19:22:28 2015 +0000
Revision:
3:321cf5e5b89b
Parent:
1:e52ae6584f1c 
AT command firmware with updated libmDot to fix endian problem when connecting to LoRaWAN Gateways

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mfiore 0:e2b8246361bc 1 #include "stm32f4xx_hal.h"
mfiore 0:e2b8246361bc 2 #include "wakeup.h"
mfiore 0:e2b8246361bc 3
mfiore 0:e2b8246361bc 4
mfiore 0:e2b8246361bc 5 static int rtc_inited = 0;
mfiore 0:e2b8246361bc 6 static uint32_t timeout = 10;
mfiore 0:e2b8246361bc 7
mfiore 0:e2b8246361bc 8 uint32_t wakeup_init(uint32_t seconds) {
mfiore 0:e2b8246361bc 9 RCC_OscInitTypeDef RCC_OscInitStruct;
mfiore 0:e2b8246361bc 10 uint32_t rtc_freq = 0;
mfiore 0:e2b8246361bc 11
mfiore 0:e2b8246361bc 12 if (rtc_inited) {
mfiore 0:e2b8246361bc 13 if (timeout != seconds) {
mfiore 0:e2b8246361bc 14 timeout = seconds;
mfiore 0:e2b8246361bc 15 HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, timeout, RTC_WAKEUPCLOCK_CK_SPRE_16BITS);
mfiore 0:e2b8246361bc 16 }
mfiore 0:e2b8246361bc 17 return 0;
mfiore 0:e2b8246361bc 18 }
mfiore 0:e2b8246361bc 19 rtc_inited = 1;
mfiore 0:e2b8246361bc 20
mfiore 0:e2b8246361bc 21 RtcHandle.Instance = RTC;
mfiore 0:e2b8246361bc 22
mfiore 0:e2b8246361bc 23 // Enable Power clock
mfiore 0:e2b8246361bc 24 __PWR_CLK_ENABLE();
mfiore 0:e2b8246361bc 25
mfiore 0:e2b8246361bc 26 // Enable access to Backup domain
mfiore 0:e2b8246361bc 27 HAL_PWR_EnableBkUpAccess();
mfiore 0:e2b8246361bc 28
mfiore 0:e2b8246361bc 29 uint32_t count = RTC_ReadBackupRegister(RTC_BKP_DR0);
mfiore 0:e2b8246361bc 30 printf("UPLINK: %lu\r\n", count);
mfiore 0:e2b8246361bc 31
mfiore 0:e2b8246361bc 32
mfiore 0:e2b8246361bc 33 // Reset Backup domain
mfiore 0:e2b8246361bc 34 __HAL_RCC_BACKUPRESET_FORCE();
mfiore 0:e2b8246361bc 35 __HAL_RCC_BACKUPRESET_RELEASE();
mfiore 0:e2b8246361bc 36
mfiore 0:e2b8246361bc 37 // Enable LSE Oscillator
mfiore 0:e2b8246361bc 38 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
mfiore 0:e2b8246361bc 39 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; /* Mandatory, otherwise the PLL is reconfigured! */
mfiore 0:e2b8246361bc 40 RCC_OscInitStruct.LSEState = RCC_LSE_ON; /* External 32.768 kHz clock on OSC_IN/OSC_OUT */
mfiore 0:e2b8246361bc 41 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
mfiore 0:e2b8246361bc 42 // Connect LSE to RTC
mfiore 0:e2b8246361bc 43 __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE);
mfiore 0:e2b8246361bc 44 __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
mfiore 0:e2b8246361bc 45 rtc_freq = LSE_VALUE;
mfiore 0:e2b8246361bc 46 } else {
mfiore 0:e2b8246361bc 47 // Enable LSI clock
mfiore 0:e2b8246361bc 48 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
mfiore 0:e2b8246361bc 49 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
mfiore 0:e2b8246361bc 50 RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
mfiore 0:e2b8246361bc 51 RCC_OscInitStruct.LSIState = RCC_LSI_ON;
mfiore 0:e2b8246361bc 52 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
mfiore 0:e2b8246361bc 53 //error("RTC error: LSI clock initialization failed.");
mfiore 0:e2b8246361bc 54 }
mfiore 0:e2b8246361bc 55 // Connect LSI to RTC
mfiore 0:e2b8246361bc 56 __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI);
mfiore 0:e2b8246361bc 57 __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
mfiore 0:e2b8246361bc 58 // [TODO] This value is LSI typical value. To be measured precisely using a timer input capture
mfiore 0:e2b8246361bc 59 rtc_freq = 32000;
mfiore 0:e2b8246361bc 60 }
mfiore 0:e2b8246361bc 61
mfiore 0:e2b8246361bc 62 // Enable RTC
mfiore 0:e2b8246361bc 63 __HAL_RCC_RTC_ENABLE();
mfiore 0:e2b8246361bc 64
mfiore 0:e2b8246361bc 65 RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24;
mfiore 0:e2b8246361bc 66 RtcHandle.Init.AsynchPrediv = 127;
mfiore 0:e2b8246361bc 67 RtcHandle.Init.SynchPrediv = (rtc_freq / 128) - 1;
mfiore 0:e2b8246361bc 68 RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE;
mfiore 0:e2b8246361bc 69 RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
mfiore 0:e2b8246361bc 70 RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
mfiore 0:e2b8246361bc 71
mfiore 0:e2b8246361bc 72 if (HAL_RTC_Init(&RtcHandle) != HAL_OK) {
mfiore 0:e2b8246361bc 73 //error("RTC error: RTC initialization failed.");
mfiore 0:e2b8246361bc 74 }
mfiore 0:e2b8246361bc 75
mfiore 0:e2b8246361bc 76 timeout = seconds;
mfiore 0:e2b8246361bc 77 HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, timeout, RTC_WAKEUPCLOCK_CK_SPRE_16BITS);
mfiore 0:e2b8246361bc 78
mfiore 0:e2b8246361bc 79 return count;
mfiore 0:e2b8246361bc 80 }
mfiore 0:e2b8246361bc 81
mfiore 0:e2b8246361bc 82 void wakeup_clear(void)
mfiore 0:e2b8246361bc 83 {
mfiore 0:e2b8246361bc 84 __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&RtcHandle, RTC_FLAG_WUTF);
mfiore 0:e2b8246361bc 85 }
mfiore 0:e2b8246361bc 86
mfiore 0:e2b8246361bc 87 uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)
mfiore 0:e2b8246361bc 88 {
mfiore 0:e2b8246361bc 89 __IO uint32_t tmp = 0;
mfiore 0:e2b8246361bc 90
mfiore 0:e2b8246361bc 91 // Check the parameters
mfiore 0:e2b8246361bc 92 assert_param(IS_RTC_BKP(RTC_BKP_DR));
mfiore 0:e2b8246361bc 93 tmp = RTC_BASE + 0x50;
mfiore 0:e2b8246361bc 94 tmp += (RTC_BKP_DR * 4);
mfiore 0:e2b8246361bc 95 // Read the specified register
mfiore 0:e2b8246361bc 96 return (*(__IO uint32_t *)tmp);
mfiore 0:e2b8246361bc 97 }
mfiore 0:e2b8246361bc 98
mfiore 0:e2b8246361bc 99 void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data)
mfiore 0:e2b8246361bc 100 {
mfiore 0:e2b8246361bc 101 __IO uint32_t tmp = 0;
mfiore 0:e2b8246361bc 102
mfiore 0:e2b8246361bc 103 // Check the parameters/
mfiore 0:e2b8246361bc 104 assert_param(IS_RTC_BKP(RTC_BKP_DR));
mfiore 0:e2b8246361bc 105 tmp = RTC_BASE + 0x50;
mfiore 0:e2b8246361bc 106 tmp += (RTC_BKP_DR * 4);
mfiore 0:e2b8246361bc 107 // Write the specified register/
mfiore 0:e2b8246361bc 108 *(__IO uint32_t *)tmp = (uint32_t)Data;
mfiore 0:e2b8246361bc 109 }
mfiore 0:e2b8246361bc 110
mfiore 0:e2b8246361bc 111
mfiore 0:e2b8246361bc 112 uint8_t TM_WATCHDOG_Init(uint16_t reload) {
mfiore 0:e2b8246361bc 113 uint8_t result = 0;
mfiore 0:e2b8246361bc 114
mfiore 0:e2b8246361bc 115 /* Check if the system has resumed from IWDG reset */
mfiore 0:e2b8246361bc 116 if (RCC->CSR & (0x20000000)) {
mfiore 0:e2b8246361bc 117 /* Reset by IWDG */
mfiore 0:e2b8246361bc 118 result = 1;
mfiore 0:e2b8246361bc 119
mfiore 0:e2b8246361bc 120 /* Clear reset flags */
mfiore 0:e2b8246361bc 121 RCC->CSR |= RCC_CSR_RMVF;
mfiore 0:e2b8246361bc 122 }
mfiore 0:e2b8246361bc 123
mfiore 0:e2b8246361bc 124 /* Enable write access to IWDG_PR and IWDG_RLR registers */
mfiore 0:e2b8246361bc 125 IWDG->KR = 0x5555;
mfiore 0:e2b8246361bc 126
mfiore 0:e2b8246361bc 127 /* IWDG counter clock: LSI/32 = 1024Hz */
mfiore 0:e2b8246361bc 128 IWDG->PR = 0x03;
mfiore 0:e2b8246361bc 129
mfiore 0:e2b8246361bc 130 reload = 4095;
mfiore 0:e2b8246361bc 131
mfiore 0:e2b8246361bc 132 printf("WATCHDOG RELOAD: %lu\r\n", reload);
mfiore 0:e2b8246361bc 133 /* Set reload */
mfiore 0:e2b8246361bc 134 IWDG->RLR = reload;
mfiore 0:e2b8246361bc 135
mfiore 0:e2b8246361bc 136 /* Reload IWDG counter */
mfiore 0:e2b8246361bc 137 IWDG->KR = 0xAAAA;
mfiore 0:e2b8246361bc 138
mfiore 0:e2b8246361bc 139 /* Enable IWDG (the LSI oscillator will be enabled by hardware) */
mfiore 0:e2b8246361bc 140 IWDG->KR = 0xCCCC;
mfiore 0:e2b8246361bc 141
mfiore 0:e2b8246361bc 142 /* Return status */
mfiore 0:e2b8246361bc 143 return result;
mfiore 0:e2b8246361bc 144 }
mfiore 0:e2b8246361bc 145
mfiore 0:e2b8246361bc 146 void TM_WATCHDOG_Disable(void) {
mfiore 0:e2b8246361bc 147 IWDG->KR = 0x0000;
mfiore 0:e2b8246361bc 148 }
mfiore 0:e2b8246361bc 149
mfiore 0:e2b8246361bc 150 void TM_WATCHDOG_Reset(void) {
mfiore 0:e2b8246361bc 151 /* Reload IWDG counter */
mfiore 0:e2b8246361bc 152 IWDG->KR = 0xAAAA;
Mike Fiore 1:e52ae6584f1c 153 }