Mouse code for the MacroRat
mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /** |
sahilmgandhi | 18:6a4db94011d3 | 2 | ******************************************************************************* |
sahilmgandhi | 18:6a4db94011d3 | 3 | * @file sleep.c |
sahilmgandhi | 18:6a4db94011d3 | 4 | * @brief Implementation of an sleep functionality |
sahilmgandhi | 18:6a4db94011d3 | 5 | * @internal |
sahilmgandhi | 18:6a4db94011d3 | 6 | * @author ON Semiconductor |
sahilmgandhi | 18:6a4db94011d3 | 7 | * $Rev: 0.1 $ |
sahilmgandhi | 18:6a4db94011d3 | 8 | * $Date: 01-21-2016 $ |
sahilmgandhi | 18:6a4db94011d3 | 9 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 10 | * Copyright 2016 Semiconductor Components Industries LLC (d/b/a ON Semiconductor). |
sahilmgandhi | 18:6a4db94011d3 | 11 | * All rights reserved. This software and/or documentation is licensed by ON Semiconductor |
sahilmgandhi | 18:6a4db94011d3 | 12 | * under limited terms and conditions. The terms and conditions pertaining to the software |
sahilmgandhi | 18:6a4db94011d3 | 13 | * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf |
sahilmgandhi | 18:6a4db94011d3 | 14 | * (ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software) and |
sahilmgandhi | 18:6a4db94011d3 | 15 | * if applicable the software license agreement. Do not use this software and/or |
sahilmgandhi | 18:6a4db94011d3 | 16 | * documentation unless you have carefully read and you agree to the limited terms and |
sahilmgandhi | 18:6a4db94011d3 | 17 | * conditions. By using this software and/or documentation, you agree to the limited |
sahilmgandhi | 18:6a4db94011d3 | 18 | * terms and conditions. |
sahilmgandhi | 18:6a4db94011d3 | 19 | * |
sahilmgandhi | 18:6a4db94011d3 | 20 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
sahilmgandhi | 18:6a4db94011d3 | 21 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
sahilmgandhi | 18:6a4db94011d3 | 22 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
sahilmgandhi | 18:6a4db94011d3 | 23 | * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, |
sahilmgandhi | 18:6a4db94011d3 | 24 | * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
sahilmgandhi | 18:6a4db94011d3 | 25 | * @endinternal |
sahilmgandhi | 18:6a4db94011d3 | 26 | * |
sahilmgandhi | 18:6a4db94011d3 | 27 | * @ingroup sleep |
sahilmgandhi | 18:6a4db94011d3 | 28 | * |
sahilmgandhi | 18:6a4db94011d3 | 29 | * @details |
sahilmgandhi | 18:6a4db94011d3 | 30 | * Sleep implementation |
sahilmgandhi | 18:6a4db94011d3 | 31 | * |
sahilmgandhi | 18:6a4db94011d3 | 32 | */ |
sahilmgandhi | 18:6a4db94011d3 | 33 | #if DEVICE_SLEEP |
sahilmgandhi | 18:6a4db94011d3 | 34 | #include "mbed_sleep.h" |
sahilmgandhi | 18:6a4db94011d3 | 35 | #include "sleep_api.h" |
sahilmgandhi | 18:6a4db94011d3 | 36 | #include "cmsis_nvic.h" |
sahilmgandhi | 18:6a4db94011d3 | 37 | |
sahilmgandhi | 18:6a4db94011d3 | 38 | #define ENABLE (uint8_t)0x01 |
sahilmgandhi | 18:6a4db94011d3 | 39 | #define DISABLE (uint8_t)0x00 |
sahilmgandhi | 18:6a4db94011d3 | 40 | #define MAC_LUT_SIZE (uint8_t)96 |
sahilmgandhi | 18:6a4db94011d3 | 41 | |
sahilmgandhi | 18:6a4db94011d3 | 42 | #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) ) |
sahilmgandhi | 18:6a4db94011d3 | 43 | #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) |
sahilmgandhi | 18:6a4db94011d3 | 44 | #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) |
sahilmgandhi | 18:6a4db94011d3 | 45 | #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) |
sahilmgandhi | 18:6a4db94011d3 | 46 | |
sahilmgandhi | 18:6a4db94011d3 | 47 | void fncs36510_sleep(void) |
sahilmgandhi | 18:6a4db94011d3 | 48 | { |
sahilmgandhi | 18:6a4db94011d3 | 49 | /** Unset SLEEPDEEP (SCR) and COMA to select sleep mode */ |
sahilmgandhi | 18:6a4db94011d3 | 50 | SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 51 | PMUREG->CONTROL.BITS.ENCOMA = DISABLE; |
sahilmgandhi | 18:6a4db94011d3 | 52 | |
sahilmgandhi | 18:6a4db94011d3 | 53 | /* Enter into sleep mode */ |
sahilmgandhi | 18:6a4db94011d3 | 54 | __ISB(); |
sahilmgandhi | 18:6a4db94011d3 | 55 | __WFI(); |
sahilmgandhi | 18:6a4db94011d3 | 56 | } |
sahilmgandhi | 18:6a4db94011d3 | 57 | |
sahilmgandhi | 18:6a4db94011d3 | 58 | void fncs36510_deepsleep(void) |
sahilmgandhi | 18:6a4db94011d3 | 59 | { |
sahilmgandhi | 18:6a4db94011d3 | 60 | /** Set SLEEPDEEP (SCR) and unset COMA to select deep sleep mode */ |
sahilmgandhi | 18:6a4db94011d3 | 61 | SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 62 | PMUREG->CONTROL.BITS.ENCOMA = DISABLE; |
sahilmgandhi | 18:6a4db94011d3 | 63 | |
sahilmgandhi | 18:6a4db94011d3 | 64 | /** Enter into deep sleep mode */ |
sahilmgandhi | 18:6a4db94011d3 | 65 | __ISB(); |
sahilmgandhi | 18:6a4db94011d3 | 66 | __WFI(); |
sahilmgandhi | 18:6a4db94011d3 | 67 | |
sahilmgandhi | 18:6a4db94011d3 | 68 | /** Wait for the external 32MHz to be power-ed up & running |
sahilmgandhi | 18:6a4db94011d3 | 69 | * Re-power down the 32MHz internal osc |
sahilmgandhi | 18:6a4db94011d3 | 70 | */ |
sahilmgandhi | 18:6a4db94011d3 | 71 | while (!CLOCKREG->CSR.BITS.XTAL32M); |
sahilmgandhi | 18:6a4db94011d3 | 72 | PMUREG->CONTROL.BITS.INT32M = 1; |
sahilmgandhi | 18:6a4db94011d3 | 73 | } |
sahilmgandhi | 18:6a4db94011d3 | 74 | |
sahilmgandhi | 18:6a4db94011d3 | 75 | void fncs36510_coma(void) |
sahilmgandhi | 18:6a4db94011d3 | 76 | { |
sahilmgandhi | 18:6a4db94011d3 | 77 | /** Set SLEEPDEEP (SCR) and set COMA to select coma mode */ |
sahilmgandhi | 18:6a4db94011d3 | 78 | SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 79 | PMUREG->CONTROL.BITS.ENCOMA = ENABLE; |
sahilmgandhi | 18:6a4db94011d3 | 80 | |
sahilmgandhi | 18:6a4db94011d3 | 81 | /* TODO Wait till MAC is idle */ |
sahilmgandhi | 18:6a4db94011d3 | 82 | // while((MACHWREG->SEQUENCER == MACHW_SEQ_TX) || (MACHWREG->SEQUENCER == MACHW_SEQ_ED) || (MACHWREG->SEQUENCER == MACHW_SEQ_CCA)); |
sahilmgandhi | 18:6a4db94011d3 | 83 | |
sahilmgandhi | 18:6a4db94011d3 | 84 | /* TODO Back up MAC_LUT * |
sahilmgandhi | 18:6a4db94011d3 | 85 | uint8_t MAC_LUT_BackUp[MAC_LUT_SIZE]; |
sahilmgandhi | 18:6a4db94011d3 | 86 | fMacBackupFrameStoreLUT(MAC_LUT_BackUp); */ |
sahilmgandhi | 18:6a4db94011d3 | 87 | |
sahilmgandhi | 18:6a4db94011d3 | 88 | /* Disable UART 1 & 2 FIFO during coma*/ |
sahilmgandhi | 18:6a4db94011d3 | 89 | UART1REG->FCR.WORD &= ~(FCR_FIFO_ENABLE); |
sahilmgandhi | 18:6a4db94011d3 | 90 | UART2REG->FCR.WORD &= ~(FCR_FIFO_ENABLE); |
sahilmgandhi | 18:6a4db94011d3 | 91 | |
sahilmgandhi | 18:6a4db94011d3 | 92 | /** Enter into coma mode */ |
sahilmgandhi | 18:6a4db94011d3 | 93 | __ISB(); |
sahilmgandhi | 18:6a4db94011d3 | 94 | __WFI(); |
sahilmgandhi | 18:6a4db94011d3 | 95 | |
sahilmgandhi | 18:6a4db94011d3 | 96 | /** Wait for the external 32MHz to be power-ed up & running |
sahilmgandhi | 18:6a4db94011d3 | 97 | * Re-power down the 32MHz internal osc |
sahilmgandhi | 18:6a4db94011d3 | 98 | */ |
sahilmgandhi | 18:6a4db94011d3 | 99 | while (!CLOCKREG->CSR.BITS.XTAL32M); |
sahilmgandhi | 18:6a4db94011d3 | 100 | PMUREG->CONTROL.BITS.INT32M = 1; |
sahilmgandhi | 18:6a4db94011d3 | 101 | |
sahilmgandhi | 18:6a4db94011d3 | 102 | /** Trim the oscillators */ |
sahilmgandhi | 18:6a4db94011d3 | 103 | if ((TRIMREG->TRIM_32K_EXT & 0xFFFF0000) != 0xFFFF0000) { |
sahilmgandhi | 18:6a4db94011d3 | 104 | CLOCKREG->TRIM_32K_EXT.WORD = TRIMREG->TRIM_32K_EXT; |
sahilmgandhi | 18:6a4db94011d3 | 105 | } |
sahilmgandhi | 18:6a4db94011d3 | 106 | if ((TRIMREG->TRIM_32M_EXT & 0xFFFF0000) != 0xFFFF0000) { |
sahilmgandhi | 18:6a4db94011d3 | 107 | CLOCKREG->TRIM_32M_EXT.WORD = TRIMREG->TRIM_32M_EXT; |
sahilmgandhi | 18:6a4db94011d3 | 108 | } |
sahilmgandhi | 18:6a4db94011d3 | 109 | |
sahilmgandhi | 18:6a4db94011d3 | 110 | /* Enable UART 1 & 2 FIFO */ |
sahilmgandhi | 18:6a4db94011d3 | 111 | UART1REG->FCR.WORD |= FCR_FIFO_ENABLE; |
sahilmgandhi | 18:6a4db94011d3 | 112 | UART2REG->FCR.WORD |= FCR_FIFO_ENABLE; |
sahilmgandhi | 18:6a4db94011d3 | 113 | |
sahilmgandhi | 18:6a4db94011d3 | 114 | /* TODO Restore MAC_LUT * |
sahilmgandhi | 18:6a4db94011d3 | 115 | fMacRestoreFrameStoreLUT(MAC_LUT_BackUp); */ |
sahilmgandhi | 18:6a4db94011d3 | 116 | } |
sahilmgandhi | 18:6a4db94011d3 | 117 | |
sahilmgandhi | 18:6a4db94011d3 | 118 | #endif /* DEVICE_SLEEP */ |